1 /* drivers/net/ethernet/freescale/gianfar.c 2 * 3 * Gianfar Ethernet Driver 4 * This driver is designed for the non-CPM ethernet controllers 5 * on the 85xx and 83xx family of integrated processors 6 * Based on 8260_io/fcc_enet.c 7 * 8 * Author: Andy Fleming 9 * Maintainer: Kumar Gala 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 11 * 12 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc. 13 * Copyright 2007 MontaVista Software, Inc. 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 * 20 * Gianfar: AKA Lambda Draconis, "Dragon" 21 * RA 11 31 24.2 22 * Dec +69 19 52 23 * V 3.84 24 * B-V +1.62 25 * 26 * Theory of operation 27 * 28 * The driver is initialized through of_device. Configuration information 29 * is therefore conveyed through an OF-style device tree. 30 * 31 * The Gianfar Ethernet Controller uses a ring of buffer 32 * descriptors. The beginning is indicated by a register 33 * pointing to the physical address of the start of the ring. 34 * The end is determined by a "wrap" bit being set in the 35 * last descriptor of the ring. 36 * 37 * When a packet is received, the RXF bit in the 38 * IEVENT register is set, triggering an interrupt when the 39 * corresponding bit in the IMASK register is also set (if 40 * interrupt coalescing is active, then the interrupt may not 41 * happen immediately, but will wait until either a set number 42 * of frames or amount of time have passed). In NAPI, the 43 * interrupt handler will signal there is work to be done, and 44 * exit. This method will start at the last known empty 45 * descriptor, and process every subsequent descriptor until there 46 * are none left with data (NAPI will stop after a set number of 47 * packets to give time to other tasks, but will eventually 48 * process all the packets). The data arrives inside a 49 * pre-allocated skb, and so after the skb is passed up to the 50 * stack, a new skb must be allocated, and the address field in 51 * the buffer descriptor must be updated to indicate this new 52 * skb. 53 * 54 * When the kernel requests that a packet be transmitted, the 55 * driver starts where it left off last time, and points the 56 * descriptor at the buffer which was passed in. The driver 57 * then informs the DMA engine that there are packets ready to 58 * be transmitted. Once the controller is finished transmitting 59 * the packet, an interrupt may be triggered (under the same 60 * conditions as for reception, but depending on the TXF bit). 61 * The driver then cleans up the buffer. 62 */ 63 64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 65 #define DEBUG 66 67 #include <linux/kernel.h> 68 #include <linux/string.h> 69 #include <linux/errno.h> 70 #include <linux/unistd.h> 71 #include <linux/slab.h> 72 #include <linux/interrupt.h> 73 #include <linux/init.h> 74 #include <linux/delay.h> 75 #include <linux/netdevice.h> 76 #include <linux/etherdevice.h> 77 #include <linux/skbuff.h> 78 #include <linux/if_vlan.h> 79 #include <linux/spinlock.h> 80 #include <linux/mm.h> 81 #include <linux/of_mdio.h> 82 #include <linux/of_platform.h> 83 #include <linux/ip.h> 84 #include <linux/tcp.h> 85 #include <linux/udp.h> 86 #include <linux/in.h> 87 #include <linux/net_tstamp.h> 88 89 #include <asm/io.h> 90 #include <asm/reg.h> 91 #include <asm/irq.h> 92 #include <asm/uaccess.h> 93 #include <linux/module.h> 94 #include <linux/dma-mapping.h> 95 #include <linux/crc32.h> 96 #include <linux/mii.h> 97 #include <linux/phy.h> 98 #include <linux/phy_fixed.h> 99 #include <linux/of.h> 100 #include <linux/of_net.h> 101 102 #include "gianfar.h" 103 104 #define TX_TIMEOUT (1*HZ) 105 106 const char gfar_driver_version[] = "1.3"; 107 108 static int gfar_enet_open(struct net_device *dev); 109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); 110 static void gfar_reset_task(struct work_struct *work); 111 static void gfar_timeout(struct net_device *dev); 112 static int gfar_close(struct net_device *dev); 113 struct sk_buff *gfar_new_skb(struct net_device *dev); 114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, 115 struct sk_buff *skb); 116 static int gfar_set_mac_address(struct net_device *dev); 117 static int gfar_change_mtu(struct net_device *dev, int new_mtu); 118 static irqreturn_t gfar_error(int irq, void *dev_id); 119 static irqreturn_t gfar_transmit(int irq, void *dev_id); 120 static irqreturn_t gfar_interrupt(int irq, void *dev_id); 121 static void adjust_link(struct net_device *dev); 122 static void init_registers(struct net_device *dev); 123 static int init_phy(struct net_device *dev); 124 static int gfar_probe(struct platform_device *ofdev); 125 static int gfar_remove(struct platform_device *ofdev); 126 static void free_skb_resources(struct gfar_private *priv); 127 static void gfar_set_multi(struct net_device *dev); 128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); 129 static void gfar_configure_serdes(struct net_device *dev); 130 static int gfar_poll(struct napi_struct *napi, int budget); 131 static int gfar_poll_sq(struct napi_struct *napi, int budget); 132 #ifdef CONFIG_NET_POLL_CONTROLLER 133 static void gfar_netpoll(struct net_device *dev); 134 #endif 135 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); 136 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); 137 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, 138 int amount_pull, struct napi_struct *napi); 139 void gfar_halt(struct net_device *dev); 140 static void gfar_halt_nodisable(struct net_device *dev); 141 void gfar_start(struct net_device *dev); 142 static void gfar_clear_exact_match(struct net_device *dev); 143 static void gfar_set_mac_for_addr(struct net_device *dev, int num, 144 const u8 *addr); 145 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 146 147 MODULE_AUTHOR("Freescale Semiconductor, Inc"); 148 MODULE_DESCRIPTION("Gianfar Ethernet Driver"); 149 MODULE_LICENSE("GPL"); 150 151 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, 152 dma_addr_t buf) 153 { 154 u32 lstatus; 155 156 bdp->bufPtr = buf; 157 158 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); 159 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) 160 lstatus |= BD_LFLAG(RXBD_WRAP); 161 162 eieio(); 163 164 bdp->lstatus = lstatus; 165 } 166 167 static int gfar_init_bds(struct net_device *ndev) 168 { 169 struct gfar_private *priv = netdev_priv(ndev); 170 struct gfar_priv_tx_q *tx_queue = NULL; 171 struct gfar_priv_rx_q *rx_queue = NULL; 172 struct txbd8 *txbdp; 173 struct rxbd8 *rxbdp; 174 int i, j; 175 176 for (i = 0; i < priv->num_tx_queues; i++) { 177 tx_queue = priv->tx_queue[i]; 178 /* Initialize some variables in our dev structure */ 179 tx_queue->num_txbdfree = tx_queue->tx_ring_size; 180 tx_queue->dirty_tx = tx_queue->tx_bd_base; 181 tx_queue->cur_tx = tx_queue->tx_bd_base; 182 tx_queue->skb_curtx = 0; 183 tx_queue->skb_dirtytx = 0; 184 185 /* Initialize Transmit Descriptor Ring */ 186 txbdp = tx_queue->tx_bd_base; 187 for (j = 0; j < tx_queue->tx_ring_size; j++) { 188 txbdp->lstatus = 0; 189 txbdp->bufPtr = 0; 190 txbdp++; 191 } 192 193 /* Set the last descriptor in the ring to indicate wrap */ 194 txbdp--; 195 txbdp->status |= TXBD_WRAP; 196 } 197 198 for (i = 0; i < priv->num_rx_queues; i++) { 199 rx_queue = priv->rx_queue[i]; 200 rx_queue->cur_rx = rx_queue->rx_bd_base; 201 rx_queue->skb_currx = 0; 202 rxbdp = rx_queue->rx_bd_base; 203 204 for (j = 0; j < rx_queue->rx_ring_size; j++) { 205 struct sk_buff *skb = rx_queue->rx_skbuff[j]; 206 207 if (skb) { 208 gfar_init_rxbdp(rx_queue, rxbdp, 209 rxbdp->bufPtr); 210 } else { 211 skb = gfar_new_skb(ndev); 212 if (!skb) { 213 netdev_err(ndev, "Can't allocate RX buffers\n"); 214 return -ENOMEM; 215 } 216 rx_queue->rx_skbuff[j] = skb; 217 218 gfar_new_rxbdp(rx_queue, rxbdp, skb); 219 } 220 221 rxbdp++; 222 } 223 224 } 225 226 return 0; 227 } 228 229 static int gfar_alloc_skb_resources(struct net_device *ndev) 230 { 231 void *vaddr; 232 dma_addr_t addr; 233 int i, j, k; 234 struct gfar_private *priv = netdev_priv(ndev); 235 struct device *dev = priv->dev; 236 struct gfar_priv_tx_q *tx_queue = NULL; 237 struct gfar_priv_rx_q *rx_queue = NULL; 238 239 priv->total_tx_ring_size = 0; 240 for (i = 0; i < priv->num_tx_queues; i++) 241 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; 242 243 priv->total_rx_ring_size = 0; 244 for (i = 0; i < priv->num_rx_queues; i++) 245 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; 246 247 /* Allocate memory for the buffer descriptors */ 248 vaddr = dma_alloc_coherent(dev, 249 (priv->total_tx_ring_size * 250 sizeof(struct txbd8)) + 251 (priv->total_rx_ring_size * 252 sizeof(struct rxbd8)), 253 &addr, GFP_KERNEL); 254 if (!vaddr) 255 return -ENOMEM; 256 257 for (i = 0; i < priv->num_tx_queues; i++) { 258 tx_queue = priv->tx_queue[i]; 259 tx_queue->tx_bd_base = vaddr; 260 tx_queue->tx_bd_dma_base = addr; 261 tx_queue->dev = ndev; 262 /* enet DMA only understands physical addresses */ 263 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; 264 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; 265 } 266 267 /* Start the rx descriptor ring where the tx ring leaves off */ 268 for (i = 0; i < priv->num_rx_queues; i++) { 269 rx_queue = priv->rx_queue[i]; 270 rx_queue->rx_bd_base = vaddr; 271 rx_queue->rx_bd_dma_base = addr; 272 rx_queue->dev = ndev; 273 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; 274 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; 275 } 276 277 /* Setup the skbuff rings */ 278 for (i = 0; i < priv->num_tx_queues; i++) { 279 tx_queue = priv->tx_queue[i]; 280 tx_queue->tx_skbuff = 281 kmalloc_array(tx_queue->tx_ring_size, 282 sizeof(*tx_queue->tx_skbuff), 283 GFP_KERNEL); 284 if (!tx_queue->tx_skbuff) 285 goto cleanup; 286 287 for (k = 0; k < tx_queue->tx_ring_size; k++) 288 tx_queue->tx_skbuff[k] = NULL; 289 } 290 291 for (i = 0; i < priv->num_rx_queues; i++) { 292 rx_queue = priv->rx_queue[i]; 293 rx_queue->rx_skbuff = 294 kmalloc_array(rx_queue->rx_ring_size, 295 sizeof(*rx_queue->rx_skbuff), 296 GFP_KERNEL); 297 if (!rx_queue->rx_skbuff) 298 goto cleanup; 299 300 for (j = 0; j < rx_queue->rx_ring_size; j++) 301 rx_queue->rx_skbuff[j] = NULL; 302 } 303 304 if (gfar_init_bds(ndev)) 305 goto cleanup; 306 307 return 0; 308 309 cleanup: 310 free_skb_resources(priv); 311 return -ENOMEM; 312 } 313 314 static void gfar_init_tx_rx_base(struct gfar_private *priv) 315 { 316 struct gfar __iomem *regs = priv->gfargrp[0].regs; 317 u32 __iomem *baddr; 318 int i; 319 320 baddr = ®s->tbase0; 321 for (i = 0; i < priv->num_tx_queues; i++) { 322 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); 323 baddr += 2; 324 } 325 326 baddr = ®s->rbase0; 327 for (i = 0; i < priv->num_rx_queues; i++) { 328 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); 329 baddr += 2; 330 } 331 } 332 333 static void gfar_init_mac(struct net_device *ndev) 334 { 335 struct gfar_private *priv = netdev_priv(ndev); 336 struct gfar __iomem *regs = priv->gfargrp[0].regs; 337 u32 rctrl = 0; 338 u32 tctrl = 0; 339 u32 attrs = 0; 340 341 /* write the tx/rx base registers */ 342 gfar_init_tx_rx_base(priv); 343 344 /* Configure the coalescing support */ 345 gfar_configure_coalescing_all(priv); 346 347 /* set this when rx hw offload (TOE) functions are being used */ 348 priv->uses_rxfcb = 0; 349 350 if (priv->rx_filer_enable) { 351 rctrl |= RCTRL_FILREN; 352 /* Program the RIR0 reg with the required distribution */ 353 gfar_write(®s->rir0, DEFAULT_RIR0); 354 } 355 356 /* Restore PROMISC mode */ 357 if (ndev->flags & IFF_PROMISC) 358 rctrl |= RCTRL_PROM; 359 360 if (ndev->features & NETIF_F_RXCSUM) { 361 rctrl |= RCTRL_CHECKSUMMING; 362 priv->uses_rxfcb = 1; 363 } 364 365 if (priv->extended_hash) { 366 rctrl |= RCTRL_EXTHASH; 367 368 gfar_clear_exact_match(ndev); 369 rctrl |= RCTRL_EMEN; 370 } 371 372 if (priv->padding) { 373 rctrl &= ~RCTRL_PAL_MASK; 374 rctrl |= RCTRL_PADDING(priv->padding); 375 } 376 377 /* Insert receive time stamps into padding alignment bytes */ 378 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) { 379 rctrl &= ~RCTRL_PAL_MASK; 380 rctrl |= RCTRL_PADDING(8); 381 priv->padding = 8; 382 } 383 384 /* Enable HW time stamping if requested from user space */ 385 if (priv->hwts_rx_en) { 386 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; 387 priv->uses_rxfcb = 1; 388 } 389 390 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) { 391 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; 392 priv->uses_rxfcb = 1; 393 } 394 395 /* Init rctrl based on our settings */ 396 gfar_write(®s->rctrl, rctrl); 397 398 if (ndev->features & NETIF_F_IP_CSUM) 399 tctrl |= TCTRL_INIT_CSUM; 400 401 if (priv->prio_sched_en) 402 tctrl |= TCTRL_TXSCHED_PRIO; 403 else { 404 tctrl |= TCTRL_TXSCHED_WRRS; 405 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT); 406 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT); 407 } 408 409 gfar_write(®s->tctrl, tctrl); 410 411 /* Set the extraction length and index */ 412 attrs = ATTRELI_EL(priv->rx_stash_size) | 413 ATTRELI_EI(priv->rx_stash_index); 414 415 gfar_write(®s->attreli, attrs); 416 417 /* Start with defaults, and add stashing or locking 418 * depending on the approprate variables 419 */ 420 attrs = ATTR_INIT_SETTINGS; 421 422 if (priv->bd_stash_en) 423 attrs |= ATTR_BDSTASH; 424 425 if (priv->rx_stash_size != 0) 426 attrs |= ATTR_BUFSTASH; 427 428 gfar_write(®s->attr, attrs); 429 430 gfar_write(®s->fifo_tx_thr, priv->fifo_threshold); 431 gfar_write(®s->fifo_tx_starve, priv->fifo_starve); 432 gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off); 433 } 434 435 static struct net_device_stats *gfar_get_stats(struct net_device *dev) 436 { 437 struct gfar_private *priv = netdev_priv(dev); 438 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; 439 unsigned long tx_packets = 0, tx_bytes = 0; 440 int i; 441 442 for (i = 0; i < priv->num_rx_queues; i++) { 443 rx_packets += priv->rx_queue[i]->stats.rx_packets; 444 rx_bytes += priv->rx_queue[i]->stats.rx_bytes; 445 rx_dropped += priv->rx_queue[i]->stats.rx_dropped; 446 } 447 448 dev->stats.rx_packets = rx_packets; 449 dev->stats.rx_bytes = rx_bytes; 450 dev->stats.rx_dropped = rx_dropped; 451 452 for (i = 0; i < priv->num_tx_queues; i++) { 453 tx_bytes += priv->tx_queue[i]->stats.tx_bytes; 454 tx_packets += priv->tx_queue[i]->stats.tx_packets; 455 } 456 457 dev->stats.tx_bytes = tx_bytes; 458 dev->stats.tx_packets = tx_packets; 459 460 return &dev->stats; 461 } 462 463 static const struct net_device_ops gfar_netdev_ops = { 464 .ndo_open = gfar_enet_open, 465 .ndo_start_xmit = gfar_start_xmit, 466 .ndo_stop = gfar_close, 467 .ndo_change_mtu = gfar_change_mtu, 468 .ndo_set_features = gfar_set_features, 469 .ndo_set_rx_mode = gfar_set_multi, 470 .ndo_tx_timeout = gfar_timeout, 471 .ndo_do_ioctl = gfar_ioctl, 472 .ndo_get_stats = gfar_get_stats, 473 .ndo_set_mac_address = eth_mac_addr, 474 .ndo_validate_addr = eth_validate_addr, 475 #ifdef CONFIG_NET_POLL_CONTROLLER 476 .ndo_poll_controller = gfar_netpoll, 477 #endif 478 }; 479 480 void lock_rx_qs(struct gfar_private *priv) 481 { 482 int i; 483 484 for (i = 0; i < priv->num_rx_queues; i++) 485 spin_lock(&priv->rx_queue[i]->rxlock); 486 } 487 488 void lock_tx_qs(struct gfar_private *priv) 489 { 490 int i; 491 492 for (i = 0; i < priv->num_tx_queues; i++) 493 spin_lock(&priv->tx_queue[i]->txlock); 494 } 495 496 void unlock_rx_qs(struct gfar_private *priv) 497 { 498 int i; 499 500 for (i = 0; i < priv->num_rx_queues; i++) 501 spin_unlock(&priv->rx_queue[i]->rxlock); 502 } 503 504 void unlock_tx_qs(struct gfar_private *priv) 505 { 506 int i; 507 508 for (i = 0; i < priv->num_tx_queues; i++) 509 spin_unlock(&priv->tx_queue[i]->txlock); 510 } 511 512 static void free_tx_pointers(struct gfar_private *priv) 513 { 514 int i; 515 516 for (i = 0; i < priv->num_tx_queues; i++) 517 kfree(priv->tx_queue[i]); 518 } 519 520 static void free_rx_pointers(struct gfar_private *priv) 521 { 522 int i; 523 524 for (i = 0; i < priv->num_rx_queues; i++) 525 kfree(priv->rx_queue[i]); 526 } 527 528 static void unmap_group_regs(struct gfar_private *priv) 529 { 530 int i; 531 532 for (i = 0; i < MAXGROUPS; i++) 533 if (priv->gfargrp[i].regs) 534 iounmap(priv->gfargrp[i].regs); 535 } 536 537 static void free_gfar_dev(struct gfar_private *priv) 538 { 539 int i, j; 540 541 for (i = 0; i < priv->num_grps; i++) 542 for (j = 0; j < GFAR_NUM_IRQS; j++) { 543 kfree(priv->gfargrp[i].irqinfo[j]); 544 priv->gfargrp[i].irqinfo[j] = NULL; 545 } 546 547 free_netdev(priv->ndev); 548 } 549 550 static void disable_napi(struct gfar_private *priv) 551 { 552 int i; 553 554 for (i = 0; i < priv->num_grps; i++) 555 napi_disable(&priv->gfargrp[i].napi); 556 } 557 558 static void enable_napi(struct gfar_private *priv) 559 { 560 int i; 561 562 for (i = 0; i < priv->num_grps; i++) 563 napi_enable(&priv->gfargrp[i].napi); 564 } 565 566 static int gfar_parse_group(struct device_node *np, 567 struct gfar_private *priv, const char *model) 568 { 569 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps]; 570 u32 *queue_mask; 571 int i; 572 573 for (i = 0; i < GFAR_NUM_IRQS; i++) { 574 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo), 575 GFP_KERNEL); 576 if (!grp->irqinfo[i]) 577 return -ENOMEM; 578 } 579 580 grp->regs = of_iomap(np, 0); 581 if (!grp->regs) 582 return -ENOMEM; 583 584 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0); 585 586 /* If we aren't the FEC we have multiple interrupts */ 587 if (model && strcasecmp(model, "FEC")) { 588 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1); 589 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2); 590 if (gfar_irq(grp, TX)->irq == NO_IRQ || 591 gfar_irq(grp, RX)->irq == NO_IRQ || 592 gfar_irq(grp, ER)->irq == NO_IRQ) 593 return -EINVAL; 594 } 595 596 grp->priv = priv; 597 spin_lock_init(&grp->grplock); 598 if (priv->mode == MQ_MG_MODE) { 599 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL); 600 grp->rx_bit_map = queue_mask ? 601 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); 602 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL); 603 grp->tx_bit_map = queue_mask ? 604 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); 605 } else { 606 grp->rx_bit_map = 0xFF; 607 grp->tx_bit_map = 0xFF; 608 } 609 priv->num_grps++; 610 611 return 0; 612 } 613 614 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) 615 { 616 const char *model; 617 const char *ctype; 618 const void *mac_addr; 619 int err = 0, i; 620 struct net_device *dev = NULL; 621 struct gfar_private *priv = NULL; 622 struct device_node *np = ofdev->dev.of_node; 623 struct device_node *child = NULL; 624 const u32 *stash; 625 const u32 *stash_len; 626 const u32 *stash_idx; 627 unsigned int num_tx_qs, num_rx_qs; 628 u32 *tx_queues, *rx_queues; 629 630 if (!np || !of_device_is_available(np)) 631 return -ENODEV; 632 633 /* parse the num of tx and rx queues */ 634 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL); 635 num_tx_qs = tx_queues ? *tx_queues : 1; 636 637 if (num_tx_qs > MAX_TX_QS) { 638 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", 639 num_tx_qs, MAX_TX_QS); 640 pr_err("Cannot do alloc_etherdev, aborting\n"); 641 return -EINVAL; 642 } 643 644 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL); 645 num_rx_qs = rx_queues ? *rx_queues : 1; 646 647 if (num_rx_qs > MAX_RX_QS) { 648 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", 649 num_rx_qs, MAX_RX_QS); 650 pr_err("Cannot do alloc_etherdev, aborting\n"); 651 return -EINVAL; 652 } 653 654 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); 655 dev = *pdev; 656 if (NULL == dev) 657 return -ENOMEM; 658 659 priv = netdev_priv(dev); 660 priv->ndev = dev; 661 662 priv->num_tx_queues = num_tx_qs; 663 netif_set_real_num_rx_queues(dev, num_rx_qs); 664 priv->num_rx_queues = num_rx_qs; 665 priv->num_grps = 0x0; 666 667 /* Init Rx queue filer rule set linked list */ 668 INIT_LIST_HEAD(&priv->rx_list.list); 669 priv->rx_list.count = 0; 670 mutex_init(&priv->rx_queue_access); 671 672 model = of_get_property(np, "model", NULL); 673 674 for (i = 0; i < MAXGROUPS; i++) 675 priv->gfargrp[i].regs = NULL; 676 677 /* Parse and initialize group specific information */ 678 if (of_device_is_compatible(np, "fsl,etsec2")) { 679 priv->mode = MQ_MG_MODE; 680 for_each_child_of_node(np, child) { 681 err = gfar_parse_group(child, priv, model); 682 if (err) 683 goto err_grp_init; 684 } 685 } else { 686 priv->mode = SQ_SG_MODE; 687 err = gfar_parse_group(np, priv, model); 688 if (err) 689 goto err_grp_init; 690 } 691 692 for (i = 0; i < priv->num_tx_queues; i++) 693 priv->tx_queue[i] = NULL; 694 for (i = 0; i < priv->num_rx_queues; i++) 695 priv->rx_queue[i] = NULL; 696 697 for (i = 0; i < priv->num_tx_queues; i++) { 698 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), 699 GFP_KERNEL); 700 if (!priv->tx_queue[i]) { 701 err = -ENOMEM; 702 goto tx_alloc_failed; 703 } 704 priv->tx_queue[i]->tx_skbuff = NULL; 705 priv->tx_queue[i]->qindex = i; 706 priv->tx_queue[i]->dev = dev; 707 spin_lock_init(&(priv->tx_queue[i]->txlock)); 708 } 709 710 for (i = 0; i < priv->num_rx_queues; i++) { 711 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), 712 GFP_KERNEL); 713 if (!priv->rx_queue[i]) { 714 err = -ENOMEM; 715 goto rx_alloc_failed; 716 } 717 priv->rx_queue[i]->rx_skbuff = NULL; 718 priv->rx_queue[i]->qindex = i; 719 priv->rx_queue[i]->dev = dev; 720 spin_lock_init(&(priv->rx_queue[i]->rxlock)); 721 } 722 723 724 stash = of_get_property(np, "bd-stash", NULL); 725 726 if (stash) { 727 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; 728 priv->bd_stash_en = 1; 729 } 730 731 stash_len = of_get_property(np, "rx-stash-len", NULL); 732 733 if (stash_len) 734 priv->rx_stash_size = *stash_len; 735 736 stash_idx = of_get_property(np, "rx-stash-idx", NULL); 737 738 if (stash_idx) 739 priv->rx_stash_index = *stash_idx; 740 741 if (stash_len || stash_idx) 742 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; 743 744 mac_addr = of_get_mac_address(np); 745 746 if (mac_addr) 747 memcpy(dev->dev_addr, mac_addr, ETH_ALEN); 748 749 if (model && !strcasecmp(model, "TSEC")) 750 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | 751 FSL_GIANFAR_DEV_HAS_COALESCE | 752 FSL_GIANFAR_DEV_HAS_RMON | 753 FSL_GIANFAR_DEV_HAS_MULTI_INTR; 754 755 if (model && !strcasecmp(model, "eTSEC")) 756 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | 757 FSL_GIANFAR_DEV_HAS_COALESCE | 758 FSL_GIANFAR_DEV_HAS_RMON | 759 FSL_GIANFAR_DEV_HAS_MULTI_INTR | 760 FSL_GIANFAR_DEV_HAS_PADDING | 761 FSL_GIANFAR_DEV_HAS_CSUM | 762 FSL_GIANFAR_DEV_HAS_VLAN | 763 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | 764 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | 765 FSL_GIANFAR_DEV_HAS_TIMER; 766 767 ctype = of_get_property(np, "phy-connection-type", NULL); 768 769 /* We only care about rgmii-id. The rest are autodetected */ 770 if (ctype && !strcmp(ctype, "rgmii-id")) 771 priv->interface = PHY_INTERFACE_MODE_RGMII_ID; 772 else 773 priv->interface = PHY_INTERFACE_MODE_MII; 774 775 if (of_get_property(np, "fsl,magic-packet", NULL)) 776 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; 777 778 priv->phy_node = of_parse_phandle(np, "phy-handle", 0); 779 780 /* Find the TBI PHY. If it's not there, we don't support SGMII */ 781 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); 782 783 return 0; 784 785 rx_alloc_failed: 786 free_rx_pointers(priv); 787 tx_alloc_failed: 788 free_tx_pointers(priv); 789 err_grp_init: 790 unmap_group_regs(priv); 791 free_gfar_dev(priv); 792 return err; 793 } 794 795 static int gfar_hwtstamp_ioctl(struct net_device *netdev, 796 struct ifreq *ifr, int cmd) 797 { 798 struct hwtstamp_config config; 799 struct gfar_private *priv = netdev_priv(netdev); 800 801 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 802 return -EFAULT; 803 804 /* reserved for future extensions */ 805 if (config.flags) 806 return -EINVAL; 807 808 switch (config.tx_type) { 809 case HWTSTAMP_TX_OFF: 810 priv->hwts_tx_en = 0; 811 break; 812 case HWTSTAMP_TX_ON: 813 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) 814 return -ERANGE; 815 priv->hwts_tx_en = 1; 816 break; 817 default: 818 return -ERANGE; 819 } 820 821 switch (config.rx_filter) { 822 case HWTSTAMP_FILTER_NONE: 823 if (priv->hwts_rx_en) { 824 stop_gfar(netdev); 825 priv->hwts_rx_en = 0; 826 startup_gfar(netdev); 827 } 828 break; 829 default: 830 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) 831 return -ERANGE; 832 if (!priv->hwts_rx_en) { 833 stop_gfar(netdev); 834 priv->hwts_rx_en = 1; 835 startup_gfar(netdev); 836 } 837 config.rx_filter = HWTSTAMP_FILTER_ALL; 838 break; 839 } 840 841 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 842 -EFAULT : 0; 843 } 844 845 /* Ioctl MII Interface */ 846 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 847 { 848 struct gfar_private *priv = netdev_priv(dev); 849 850 if (!netif_running(dev)) 851 return -EINVAL; 852 853 if (cmd == SIOCSHWTSTAMP) 854 return gfar_hwtstamp_ioctl(dev, rq, cmd); 855 856 if (!priv->phydev) 857 return -ENODEV; 858 859 return phy_mii_ioctl(priv->phydev, rq, cmd); 860 } 861 862 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs) 863 { 864 unsigned int new_bit_map = 0x0; 865 int mask = 0x1 << (max_qs - 1), i; 866 867 for (i = 0; i < max_qs; i++) { 868 if (bit_map & mask) 869 new_bit_map = new_bit_map + (1 << i); 870 mask = mask >> 0x1; 871 } 872 return new_bit_map; 873 } 874 875 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, 876 u32 class) 877 { 878 u32 rqfpr = FPR_FILER_MASK; 879 u32 rqfcr = 0x0; 880 881 rqfar--; 882 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; 883 priv->ftp_rqfpr[rqfar] = rqfpr; 884 priv->ftp_rqfcr[rqfar] = rqfcr; 885 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 886 887 rqfar--; 888 rqfcr = RQFCR_CMP_NOMATCH; 889 priv->ftp_rqfpr[rqfar] = rqfpr; 890 priv->ftp_rqfcr[rqfar] = rqfcr; 891 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 892 893 rqfar--; 894 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; 895 rqfpr = class; 896 priv->ftp_rqfcr[rqfar] = rqfcr; 897 priv->ftp_rqfpr[rqfar] = rqfpr; 898 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 899 900 rqfar--; 901 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; 902 rqfpr = class; 903 priv->ftp_rqfcr[rqfar] = rqfcr; 904 priv->ftp_rqfpr[rqfar] = rqfpr; 905 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 906 907 return rqfar; 908 } 909 910 static void gfar_init_filer_table(struct gfar_private *priv) 911 { 912 int i = 0x0; 913 u32 rqfar = MAX_FILER_IDX; 914 u32 rqfcr = 0x0; 915 u32 rqfpr = FPR_FILER_MASK; 916 917 /* Default rule */ 918 rqfcr = RQFCR_CMP_MATCH; 919 priv->ftp_rqfcr[rqfar] = rqfcr; 920 priv->ftp_rqfpr[rqfar] = rqfpr; 921 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 922 923 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); 924 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); 925 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); 926 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); 927 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); 928 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); 929 930 /* cur_filer_idx indicated the first non-masked rule */ 931 priv->cur_filer_idx = rqfar; 932 933 /* Rest are masked rules */ 934 rqfcr = RQFCR_CMP_NOMATCH; 935 for (i = 0; i < rqfar; i++) { 936 priv->ftp_rqfcr[i] = rqfcr; 937 priv->ftp_rqfpr[i] = rqfpr; 938 gfar_write_filer(priv, i, rqfcr, rqfpr); 939 } 940 } 941 942 static void gfar_detect_errata(struct gfar_private *priv) 943 { 944 struct device *dev = &priv->ofdev->dev; 945 unsigned int pvr = mfspr(SPRN_PVR); 946 unsigned int svr = mfspr(SPRN_SVR); 947 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ 948 unsigned int rev = svr & 0xffff; 949 950 /* MPC8313 Rev 2.0 and higher; All MPC837x */ 951 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || 952 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) 953 priv->errata |= GFAR_ERRATA_74; 954 955 /* MPC8313 and MPC837x all rev */ 956 if ((pvr == 0x80850010 && mod == 0x80b0) || 957 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) 958 priv->errata |= GFAR_ERRATA_76; 959 960 /* MPC8313 and MPC837x all rev */ 961 if ((pvr == 0x80850010 && mod == 0x80b0) || 962 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) 963 priv->errata |= GFAR_ERRATA_A002; 964 965 /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */ 966 if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) || 967 (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020)) 968 priv->errata |= GFAR_ERRATA_12; 969 970 if (priv->errata) 971 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", 972 priv->errata); 973 } 974 975 /* Set up the ethernet device structure, private data, 976 * and anything else we need before we start 977 */ 978 static int gfar_probe(struct platform_device *ofdev) 979 { 980 u32 tempval; 981 struct net_device *dev = NULL; 982 struct gfar_private *priv = NULL; 983 struct gfar __iomem *regs = NULL; 984 int err = 0, i, grp_idx = 0; 985 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0; 986 u32 isrg = 0; 987 u32 __iomem *baddr; 988 989 err = gfar_of_init(ofdev, &dev); 990 991 if (err) 992 return err; 993 994 priv = netdev_priv(dev); 995 priv->ndev = dev; 996 priv->ofdev = ofdev; 997 priv->dev = &ofdev->dev; 998 SET_NETDEV_DEV(dev, &ofdev->dev); 999 1000 spin_lock_init(&priv->bflock); 1001 INIT_WORK(&priv->reset_task, gfar_reset_task); 1002 1003 platform_set_drvdata(ofdev, priv); 1004 regs = priv->gfargrp[0].regs; 1005 1006 gfar_detect_errata(priv); 1007 1008 /* Stop the DMA engine now, in case it was running before 1009 * (The firmware could have used it, and left it running). 1010 */ 1011 gfar_halt(dev); 1012 1013 /* Reset MAC layer */ 1014 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); 1015 1016 /* We need to delay at least 3 TX clocks */ 1017 udelay(2); 1018 1019 tempval = 0; 1020 if (!priv->pause_aneg_en && priv->tx_pause_en) 1021 tempval |= MACCFG1_TX_FLOW; 1022 if (!priv->pause_aneg_en && priv->rx_pause_en) 1023 tempval |= MACCFG1_RX_FLOW; 1024 /* the soft reset bit is not self-resetting, so we need to 1025 * clear it before resuming normal operation 1026 */ 1027 gfar_write(®s->maccfg1, tempval); 1028 1029 /* Initialize MACCFG2. */ 1030 tempval = MACCFG2_INIT_SETTINGS; 1031 if (gfar_has_errata(priv, GFAR_ERRATA_74)) 1032 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; 1033 gfar_write(®s->maccfg2, tempval); 1034 1035 /* Initialize ECNTRL */ 1036 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); 1037 1038 /* Set the dev->base_addr to the gfar reg region */ 1039 dev->base_addr = (unsigned long) regs; 1040 1041 /* Fill in the dev structure */ 1042 dev->watchdog_timeo = TX_TIMEOUT; 1043 dev->mtu = 1500; 1044 dev->netdev_ops = &gfar_netdev_ops; 1045 dev->ethtool_ops = &gfar_ethtool_ops; 1046 1047 /* Register for napi ...We are registering NAPI for each grp */ 1048 if (priv->mode == SQ_SG_MODE) 1049 netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq, 1050 GFAR_DEV_WEIGHT); 1051 else 1052 for (i = 0; i < priv->num_grps; i++) 1053 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, 1054 GFAR_DEV_WEIGHT); 1055 1056 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { 1057 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | 1058 NETIF_F_RXCSUM; 1059 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | 1060 NETIF_F_RXCSUM | NETIF_F_HIGHDMA; 1061 } 1062 1063 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { 1064 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 1065 NETIF_F_HW_VLAN_CTAG_RX; 1066 dev->features |= NETIF_F_HW_VLAN_CTAG_RX; 1067 } 1068 1069 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { 1070 priv->extended_hash = 1; 1071 priv->hash_width = 9; 1072 1073 priv->hash_regs[0] = ®s->igaddr0; 1074 priv->hash_regs[1] = ®s->igaddr1; 1075 priv->hash_regs[2] = ®s->igaddr2; 1076 priv->hash_regs[3] = ®s->igaddr3; 1077 priv->hash_regs[4] = ®s->igaddr4; 1078 priv->hash_regs[5] = ®s->igaddr5; 1079 priv->hash_regs[6] = ®s->igaddr6; 1080 priv->hash_regs[7] = ®s->igaddr7; 1081 priv->hash_regs[8] = ®s->gaddr0; 1082 priv->hash_regs[9] = ®s->gaddr1; 1083 priv->hash_regs[10] = ®s->gaddr2; 1084 priv->hash_regs[11] = ®s->gaddr3; 1085 priv->hash_regs[12] = ®s->gaddr4; 1086 priv->hash_regs[13] = ®s->gaddr5; 1087 priv->hash_regs[14] = ®s->gaddr6; 1088 priv->hash_regs[15] = ®s->gaddr7; 1089 1090 } else { 1091 priv->extended_hash = 0; 1092 priv->hash_width = 8; 1093 1094 priv->hash_regs[0] = ®s->gaddr0; 1095 priv->hash_regs[1] = ®s->gaddr1; 1096 priv->hash_regs[2] = ®s->gaddr2; 1097 priv->hash_regs[3] = ®s->gaddr3; 1098 priv->hash_regs[4] = ®s->gaddr4; 1099 priv->hash_regs[5] = ®s->gaddr5; 1100 priv->hash_regs[6] = ®s->gaddr6; 1101 priv->hash_regs[7] = ®s->gaddr7; 1102 } 1103 1104 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) 1105 priv->padding = DEFAULT_PADDING; 1106 else 1107 priv->padding = 0; 1108 1109 if (dev->features & NETIF_F_IP_CSUM || 1110 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) 1111 dev->needed_headroom = GMAC_FCB_LEN; 1112 1113 /* Program the isrg regs only if number of grps > 1 */ 1114 if (priv->num_grps > 1) { 1115 baddr = ®s->isrg0; 1116 for (i = 0; i < priv->num_grps; i++) { 1117 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX); 1118 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX); 1119 gfar_write(baddr, isrg); 1120 baddr++; 1121 isrg = 0x0; 1122 } 1123 } 1124 1125 /* Need to reverse the bit maps as bit_map's MSB is q0 1126 * but, for_each_set_bit parses from right to left, which 1127 * basically reverses the queue numbers 1128 */ 1129 for (i = 0; i< priv->num_grps; i++) { 1130 priv->gfargrp[i].tx_bit_map = 1131 reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS); 1132 priv->gfargrp[i].rx_bit_map = 1133 reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS); 1134 } 1135 1136 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, 1137 * also assign queues to groups 1138 */ 1139 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { 1140 priv->gfargrp[grp_idx].num_rx_queues = 0x0; 1141 1142 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map, 1143 priv->num_rx_queues) { 1144 priv->gfargrp[grp_idx].num_rx_queues++; 1145 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx]; 1146 rstat = rstat | (RSTAT_CLEAR_RHALT >> i); 1147 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i); 1148 } 1149 priv->gfargrp[grp_idx].num_tx_queues = 0x0; 1150 1151 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map, 1152 priv->num_tx_queues) { 1153 priv->gfargrp[grp_idx].num_tx_queues++; 1154 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx]; 1155 tstat = tstat | (TSTAT_CLEAR_THALT >> i); 1156 tqueue = tqueue | (TQUEUE_EN0 >> i); 1157 } 1158 priv->gfargrp[grp_idx].rstat = rstat; 1159 priv->gfargrp[grp_idx].tstat = tstat; 1160 rstat = tstat =0; 1161 } 1162 1163 gfar_write(®s->rqueue, rqueue); 1164 gfar_write(®s->tqueue, tqueue); 1165 1166 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; 1167 1168 /* Initializing some of the rx/tx queue level parameters */ 1169 for (i = 0; i < priv->num_tx_queues; i++) { 1170 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; 1171 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; 1172 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; 1173 priv->tx_queue[i]->txic = DEFAULT_TXIC; 1174 } 1175 1176 for (i = 0; i < priv->num_rx_queues; i++) { 1177 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; 1178 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; 1179 priv->rx_queue[i]->rxic = DEFAULT_RXIC; 1180 } 1181 1182 /* always enable rx filer */ 1183 priv->rx_filer_enable = 1; 1184 /* Enable most messages by default */ 1185 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; 1186 /* use pritority h/w tx queue scheduling for single queue devices */ 1187 if (priv->num_tx_queues == 1) 1188 priv->prio_sched_en = 1; 1189 1190 /* Carrier starts down, phylib will bring it up */ 1191 netif_carrier_off(dev); 1192 1193 err = register_netdev(dev); 1194 1195 if (err) { 1196 pr_err("%s: Cannot register net device, aborting\n", dev->name); 1197 goto register_fail; 1198 } 1199 1200 device_init_wakeup(&dev->dev, 1201 priv->device_flags & 1202 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); 1203 1204 /* fill out IRQ number and name fields */ 1205 for (i = 0; i < priv->num_grps; i++) { 1206 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 1207 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 1208 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s", 1209 dev->name, "_g", '0' + i, "_tx"); 1210 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s", 1211 dev->name, "_g", '0' + i, "_rx"); 1212 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s", 1213 dev->name, "_g", '0' + i, "_er"); 1214 } else 1215 strcpy(gfar_irq(grp, TX)->name, dev->name); 1216 } 1217 1218 /* Initialize the filer table */ 1219 gfar_init_filer_table(priv); 1220 1221 /* Create all the sysfs files */ 1222 gfar_init_sysfs(dev); 1223 1224 /* Print out the device info */ 1225 netdev_info(dev, "mac: %pM\n", dev->dev_addr); 1226 1227 /* Even more device info helps when determining which kernel 1228 * provided which set of benchmarks. 1229 */ 1230 netdev_info(dev, "Running with NAPI enabled\n"); 1231 for (i = 0; i < priv->num_rx_queues; i++) 1232 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n", 1233 i, priv->rx_queue[i]->rx_ring_size); 1234 for (i = 0; i < priv->num_tx_queues; i++) 1235 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n", 1236 i, priv->tx_queue[i]->tx_ring_size); 1237 1238 return 0; 1239 1240 register_fail: 1241 unmap_group_regs(priv); 1242 free_tx_pointers(priv); 1243 free_rx_pointers(priv); 1244 if (priv->phy_node) 1245 of_node_put(priv->phy_node); 1246 if (priv->tbi_node) 1247 of_node_put(priv->tbi_node); 1248 free_gfar_dev(priv); 1249 return err; 1250 } 1251 1252 static int gfar_remove(struct platform_device *ofdev) 1253 { 1254 struct gfar_private *priv = platform_get_drvdata(ofdev); 1255 1256 if (priv->phy_node) 1257 of_node_put(priv->phy_node); 1258 if (priv->tbi_node) 1259 of_node_put(priv->tbi_node); 1260 1261 unregister_netdev(priv->ndev); 1262 unmap_group_regs(priv); 1263 free_gfar_dev(priv); 1264 1265 return 0; 1266 } 1267 1268 #ifdef CONFIG_PM 1269 1270 static int gfar_suspend(struct device *dev) 1271 { 1272 struct gfar_private *priv = dev_get_drvdata(dev); 1273 struct net_device *ndev = priv->ndev; 1274 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1275 unsigned long flags; 1276 u32 tempval; 1277 1278 int magic_packet = priv->wol_en && 1279 (priv->device_flags & 1280 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); 1281 1282 netif_device_detach(ndev); 1283 1284 if (netif_running(ndev)) { 1285 1286 local_irq_save(flags); 1287 lock_tx_qs(priv); 1288 lock_rx_qs(priv); 1289 1290 gfar_halt_nodisable(ndev); 1291 1292 /* Disable Tx, and Rx if wake-on-LAN is disabled. */ 1293 tempval = gfar_read(®s->maccfg1); 1294 1295 tempval &= ~MACCFG1_TX_EN; 1296 1297 if (!magic_packet) 1298 tempval &= ~MACCFG1_RX_EN; 1299 1300 gfar_write(®s->maccfg1, tempval); 1301 1302 unlock_rx_qs(priv); 1303 unlock_tx_qs(priv); 1304 local_irq_restore(flags); 1305 1306 disable_napi(priv); 1307 1308 if (magic_packet) { 1309 /* Enable interrupt on Magic Packet */ 1310 gfar_write(®s->imask, IMASK_MAG); 1311 1312 /* Enable Magic Packet mode */ 1313 tempval = gfar_read(®s->maccfg2); 1314 tempval |= MACCFG2_MPEN; 1315 gfar_write(®s->maccfg2, tempval); 1316 } else { 1317 phy_stop(priv->phydev); 1318 } 1319 } 1320 1321 return 0; 1322 } 1323 1324 static int gfar_resume(struct device *dev) 1325 { 1326 struct gfar_private *priv = dev_get_drvdata(dev); 1327 struct net_device *ndev = priv->ndev; 1328 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1329 unsigned long flags; 1330 u32 tempval; 1331 int magic_packet = priv->wol_en && 1332 (priv->device_flags & 1333 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); 1334 1335 if (!netif_running(ndev)) { 1336 netif_device_attach(ndev); 1337 return 0; 1338 } 1339 1340 if (!magic_packet && priv->phydev) 1341 phy_start(priv->phydev); 1342 1343 /* Disable Magic Packet mode, in case something 1344 * else woke us up. 1345 */ 1346 local_irq_save(flags); 1347 lock_tx_qs(priv); 1348 lock_rx_qs(priv); 1349 1350 tempval = gfar_read(®s->maccfg2); 1351 tempval &= ~MACCFG2_MPEN; 1352 gfar_write(®s->maccfg2, tempval); 1353 1354 gfar_start(ndev); 1355 1356 unlock_rx_qs(priv); 1357 unlock_tx_qs(priv); 1358 local_irq_restore(flags); 1359 1360 netif_device_attach(ndev); 1361 1362 enable_napi(priv); 1363 1364 return 0; 1365 } 1366 1367 static int gfar_restore(struct device *dev) 1368 { 1369 struct gfar_private *priv = dev_get_drvdata(dev); 1370 struct net_device *ndev = priv->ndev; 1371 1372 if (!netif_running(ndev)) { 1373 netif_device_attach(ndev); 1374 1375 return 0; 1376 } 1377 1378 if (gfar_init_bds(ndev)) { 1379 free_skb_resources(priv); 1380 return -ENOMEM; 1381 } 1382 1383 init_registers(ndev); 1384 gfar_set_mac_address(ndev); 1385 gfar_init_mac(ndev); 1386 gfar_start(ndev); 1387 1388 priv->oldlink = 0; 1389 priv->oldspeed = 0; 1390 priv->oldduplex = -1; 1391 1392 if (priv->phydev) 1393 phy_start(priv->phydev); 1394 1395 netif_device_attach(ndev); 1396 enable_napi(priv); 1397 1398 return 0; 1399 } 1400 1401 static struct dev_pm_ops gfar_pm_ops = { 1402 .suspend = gfar_suspend, 1403 .resume = gfar_resume, 1404 .freeze = gfar_suspend, 1405 .thaw = gfar_resume, 1406 .restore = gfar_restore, 1407 }; 1408 1409 #define GFAR_PM_OPS (&gfar_pm_ops) 1410 1411 #else 1412 1413 #define GFAR_PM_OPS NULL 1414 1415 #endif 1416 1417 /* Reads the controller's registers to determine what interface 1418 * connects it to the PHY. 1419 */ 1420 static phy_interface_t gfar_get_interface(struct net_device *dev) 1421 { 1422 struct gfar_private *priv = netdev_priv(dev); 1423 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1424 u32 ecntrl; 1425 1426 ecntrl = gfar_read(®s->ecntrl); 1427 1428 if (ecntrl & ECNTRL_SGMII_MODE) 1429 return PHY_INTERFACE_MODE_SGMII; 1430 1431 if (ecntrl & ECNTRL_TBI_MODE) { 1432 if (ecntrl & ECNTRL_REDUCED_MODE) 1433 return PHY_INTERFACE_MODE_RTBI; 1434 else 1435 return PHY_INTERFACE_MODE_TBI; 1436 } 1437 1438 if (ecntrl & ECNTRL_REDUCED_MODE) { 1439 if (ecntrl & ECNTRL_REDUCED_MII_MODE) { 1440 return PHY_INTERFACE_MODE_RMII; 1441 } 1442 else { 1443 phy_interface_t interface = priv->interface; 1444 1445 /* This isn't autodetected right now, so it must 1446 * be set by the device tree or platform code. 1447 */ 1448 if (interface == PHY_INTERFACE_MODE_RGMII_ID) 1449 return PHY_INTERFACE_MODE_RGMII_ID; 1450 1451 return PHY_INTERFACE_MODE_RGMII; 1452 } 1453 } 1454 1455 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) 1456 return PHY_INTERFACE_MODE_GMII; 1457 1458 return PHY_INTERFACE_MODE_MII; 1459 } 1460 1461 1462 /* Initializes driver's PHY state, and attaches to the PHY. 1463 * Returns 0 on success. 1464 */ 1465 static int init_phy(struct net_device *dev) 1466 { 1467 struct gfar_private *priv = netdev_priv(dev); 1468 uint gigabit_support = 1469 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? 1470 GFAR_SUPPORTED_GBIT : 0; 1471 phy_interface_t interface; 1472 1473 priv->oldlink = 0; 1474 priv->oldspeed = 0; 1475 priv->oldduplex = -1; 1476 1477 interface = gfar_get_interface(dev); 1478 1479 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, 1480 interface); 1481 if (!priv->phydev) 1482 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link, 1483 interface); 1484 if (!priv->phydev) { 1485 dev_err(&dev->dev, "could not attach to PHY\n"); 1486 return -ENODEV; 1487 } 1488 1489 if (interface == PHY_INTERFACE_MODE_SGMII) 1490 gfar_configure_serdes(dev); 1491 1492 /* Remove any features not supported by the controller */ 1493 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); 1494 priv->phydev->advertising = priv->phydev->supported; 1495 1496 return 0; 1497 } 1498 1499 /* Initialize TBI PHY interface for communicating with the 1500 * SERDES lynx PHY on the chip. We communicate with this PHY 1501 * through the MDIO bus on each controller, treating it as a 1502 * "normal" PHY at the address found in the TBIPA register. We assume 1503 * that the TBIPA register is valid. Either the MDIO bus code will set 1504 * it to a value that doesn't conflict with other PHYs on the bus, or the 1505 * value doesn't matter, as there are no other PHYs on the bus. 1506 */ 1507 static void gfar_configure_serdes(struct net_device *dev) 1508 { 1509 struct gfar_private *priv = netdev_priv(dev); 1510 struct phy_device *tbiphy; 1511 1512 if (!priv->tbi_node) { 1513 dev_warn(&dev->dev, "error: SGMII mode requires that the " 1514 "device tree specify a tbi-handle\n"); 1515 return; 1516 } 1517 1518 tbiphy = of_phy_find_device(priv->tbi_node); 1519 if (!tbiphy) { 1520 dev_err(&dev->dev, "error: Could not get TBI device\n"); 1521 return; 1522 } 1523 1524 /* If the link is already up, we must already be ok, and don't need to 1525 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured 1526 * everything for us? Resetting it takes the link down and requires 1527 * several seconds for it to come back. 1528 */ 1529 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) 1530 return; 1531 1532 /* Single clk mode, mii mode off(for serdes communication) */ 1533 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); 1534 1535 phy_write(tbiphy, MII_ADVERTISE, 1536 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | 1537 ADVERTISE_1000XPSE_ASYM); 1538 1539 phy_write(tbiphy, MII_BMCR, 1540 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | 1541 BMCR_SPEED1000); 1542 } 1543 1544 static void init_registers(struct net_device *dev) 1545 { 1546 struct gfar_private *priv = netdev_priv(dev); 1547 struct gfar __iomem *regs = NULL; 1548 int i; 1549 1550 for (i = 0; i < priv->num_grps; i++) { 1551 regs = priv->gfargrp[i].regs; 1552 /* Clear IEVENT */ 1553 gfar_write(®s->ievent, IEVENT_INIT_CLEAR); 1554 1555 /* Initialize IMASK */ 1556 gfar_write(®s->imask, IMASK_INIT_CLEAR); 1557 } 1558 1559 regs = priv->gfargrp[0].regs; 1560 /* Init hash registers to zero */ 1561 gfar_write(®s->igaddr0, 0); 1562 gfar_write(®s->igaddr1, 0); 1563 gfar_write(®s->igaddr2, 0); 1564 gfar_write(®s->igaddr3, 0); 1565 gfar_write(®s->igaddr4, 0); 1566 gfar_write(®s->igaddr5, 0); 1567 gfar_write(®s->igaddr6, 0); 1568 gfar_write(®s->igaddr7, 0); 1569 1570 gfar_write(®s->gaddr0, 0); 1571 gfar_write(®s->gaddr1, 0); 1572 gfar_write(®s->gaddr2, 0); 1573 gfar_write(®s->gaddr3, 0); 1574 gfar_write(®s->gaddr4, 0); 1575 gfar_write(®s->gaddr5, 0); 1576 gfar_write(®s->gaddr6, 0); 1577 gfar_write(®s->gaddr7, 0); 1578 1579 /* Zero out the rmon mib registers if it has them */ 1580 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { 1581 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib)); 1582 1583 /* Mask off the CAM interrupts */ 1584 gfar_write(®s->rmon.cam1, 0xffffffff); 1585 gfar_write(®s->rmon.cam2, 0xffffffff); 1586 } 1587 1588 /* Initialize the max receive buffer length */ 1589 gfar_write(®s->mrblr, priv->rx_buffer_size); 1590 1591 /* Initialize the Minimum Frame Length Register */ 1592 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); 1593 } 1594 1595 static int __gfar_is_rx_idle(struct gfar_private *priv) 1596 { 1597 u32 res; 1598 1599 /* Normaly TSEC should not hang on GRS commands, so we should 1600 * actually wait for IEVENT_GRSC flag. 1601 */ 1602 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002))) 1603 return 0; 1604 1605 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are 1606 * the same as bits 23-30, the eTSEC Rx is assumed to be idle 1607 * and the Rx can be safely reset. 1608 */ 1609 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); 1610 res &= 0x7f807f80; 1611 if ((res & 0xffff) == (res >> 16)) 1612 return 1; 1613 1614 return 0; 1615 } 1616 1617 /* Halt the receive and transmit queues */ 1618 static void gfar_halt_nodisable(struct net_device *dev) 1619 { 1620 struct gfar_private *priv = netdev_priv(dev); 1621 struct gfar __iomem *regs = NULL; 1622 u32 tempval; 1623 int i; 1624 1625 for (i = 0; i < priv->num_grps; i++) { 1626 regs = priv->gfargrp[i].regs; 1627 /* Mask all interrupts */ 1628 gfar_write(®s->imask, IMASK_INIT_CLEAR); 1629 1630 /* Clear all interrupts */ 1631 gfar_write(®s->ievent, IEVENT_INIT_CLEAR); 1632 } 1633 1634 regs = priv->gfargrp[0].regs; 1635 /* Stop the DMA, and wait for it to stop */ 1636 tempval = gfar_read(®s->dmactrl); 1637 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) != 1638 (DMACTRL_GRS | DMACTRL_GTS)) { 1639 int ret; 1640 1641 tempval |= (DMACTRL_GRS | DMACTRL_GTS); 1642 gfar_write(®s->dmactrl, tempval); 1643 1644 do { 1645 ret = spin_event_timeout(((gfar_read(®s->ievent) & 1646 (IEVENT_GRSC | IEVENT_GTSC)) == 1647 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0); 1648 if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC)) 1649 ret = __gfar_is_rx_idle(priv); 1650 } while (!ret); 1651 } 1652 } 1653 1654 /* Halt the receive and transmit queues */ 1655 void gfar_halt(struct net_device *dev) 1656 { 1657 struct gfar_private *priv = netdev_priv(dev); 1658 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1659 u32 tempval; 1660 1661 gfar_halt_nodisable(dev); 1662 1663 /* Disable Rx and Tx */ 1664 tempval = gfar_read(®s->maccfg1); 1665 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); 1666 gfar_write(®s->maccfg1, tempval); 1667 } 1668 1669 static void free_grp_irqs(struct gfar_priv_grp *grp) 1670 { 1671 free_irq(gfar_irq(grp, TX)->irq, grp); 1672 free_irq(gfar_irq(grp, RX)->irq, grp); 1673 free_irq(gfar_irq(grp, ER)->irq, grp); 1674 } 1675 1676 void stop_gfar(struct net_device *dev) 1677 { 1678 struct gfar_private *priv = netdev_priv(dev); 1679 unsigned long flags; 1680 int i; 1681 1682 phy_stop(priv->phydev); 1683 1684 1685 /* Lock it down */ 1686 local_irq_save(flags); 1687 lock_tx_qs(priv); 1688 lock_rx_qs(priv); 1689 1690 gfar_halt(dev); 1691 1692 unlock_rx_qs(priv); 1693 unlock_tx_qs(priv); 1694 local_irq_restore(flags); 1695 1696 /* Free the IRQs */ 1697 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 1698 for (i = 0; i < priv->num_grps; i++) 1699 free_grp_irqs(&priv->gfargrp[i]); 1700 } else { 1701 for (i = 0; i < priv->num_grps; i++) 1702 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq, 1703 &priv->gfargrp[i]); 1704 } 1705 1706 free_skb_resources(priv); 1707 } 1708 1709 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) 1710 { 1711 struct txbd8 *txbdp; 1712 struct gfar_private *priv = netdev_priv(tx_queue->dev); 1713 int i, j; 1714 1715 txbdp = tx_queue->tx_bd_base; 1716 1717 for (i = 0; i < tx_queue->tx_ring_size; i++) { 1718 if (!tx_queue->tx_skbuff[i]) 1719 continue; 1720 1721 dma_unmap_single(priv->dev, txbdp->bufPtr, 1722 txbdp->length, DMA_TO_DEVICE); 1723 txbdp->lstatus = 0; 1724 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; 1725 j++) { 1726 txbdp++; 1727 dma_unmap_page(priv->dev, txbdp->bufPtr, 1728 txbdp->length, DMA_TO_DEVICE); 1729 } 1730 txbdp++; 1731 dev_kfree_skb_any(tx_queue->tx_skbuff[i]); 1732 tx_queue->tx_skbuff[i] = NULL; 1733 } 1734 kfree(tx_queue->tx_skbuff); 1735 tx_queue->tx_skbuff = NULL; 1736 } 1737 1738 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) 1739 { 1740 struct rxbd8 *rxbdp; 1741 struct gfar_private *priv = netdev_priv(rx_queue->dev); 1742 int i; 1743 1744 rxbdp = rx_queue->rx_bd_base; 1745 1746 for (i = 0; i < rx_queue->rx_ring_size; i++) { 1747 if (rx_queue->rx_skbuff[i]) { 1748 dma_unmap_single(priv->dev, rxbdp->bufPtr, 1749 priv->rx_buffer_size, 1750 DMA_FROM_DEVICE); 1751 dev_kfree_skb_any(rx_queue->rx_skbuff[i]); 1752 rx_queue->rx_skbuff[i] = NULL; 1753 } 1754 rxbdp->lstatus = 0; 1755 rxbdp->bufPtr = 0; 1756 rxbdp++; 1757 } 1758 kfree(rx_queue->rx_skbuff); 1759 rx_queue->rx_skbuff = NULL; 1760 } 1761 1762 /* If there are any tx skbs or rx skbs still around, free them. 1763 * Then free tx_skbuff and rx_skbuff 1764 */ 1765 static void free_skb_resources(struct gfar_private *priv) 1766 { 1767 struct gfar_priv_tx_q *tx_queue = NULL; 1768 struct gfar_priv_rx_q *rx_queue = NULL; 1769 int i; 1770 1771 /* Go through all the buffer descriptors and free their data buffers */ 1772 for (i = 0; i < priv->num_tx_queues; i++) { 1773 struct netdev_queue *txq; 1774 1775 tx_queue = priv->tx_queue[i]; 1776 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); 1777 if (tx_queue->tx_skbuff) 1778 free_skb_tx_queue(tx_queue); 1779 netdev_tx_reset_queue(txq); 1780 } 1781 1782 for (i = 0; i < priv->num_rx_queues; i++) { 1783 rx_queue = priv->rx_queue[i]; 1784 if (rx_queue->rx_skbuff) 1785 free_skb_rx_queue(rx_queue); 1786 } 1787 1788 dma_free_coherent(priv->dev, 1789 sizeof(struct txbd8) * priv->total_tx_ring_size + 1790 sizeof(struct rxbd8) * priv->total_rx_ring_size, 1791 priv->tx_queue[0]->tx_bd_base, 1792 priv->tx_queue[0]->tx_bd_dma_base); 1793 } 1794 1795 void gfar_start(struct net_device *dev) 1796 { 1797 struct gfar_private *priv = netdev_priv(dev); 1798 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1799 u32 tempval; 1800 int i = 0; 1801 1802 /* Enable Rx and Tx in MACCFG1 */ 1803 tempval = gfar_read(®s->maccfg1); 1804 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 1805 gfar_write(®s->maccfg1, tempval); 1806 1807 /* Initialize DMACTRL to have WWR and WOP */ 1808 tempval = gfar_read(®s->dmactrl); 1809 tempval |= DMACTRL_INIT_SETTINGS; 1810 gfar_write(®s->dmactrl, tempval); 1811 1812 /* Make sure we aren't stopped */ 1813 tempval = gfar_read(®s->dmactrl); 1814 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); 1815 gfar_write(®s->dmactrl, tempval); 1816 1817 for (i = 0; i < priv->num_grps; i++) { 1818 regs = priv->gfargrp[i].regs; 1819 /* Clear THLT/RHLT, so that the DMA starts polling now */ 1820 gfar_write(®s->tstat, priv->gfargrp[i].tstat); 1821 gfar_write(®s->rstat, priv->gfargrp[i].rstat); 1822 /* Unmask the interrupts we look for */ 1823 gfar_write(®s->imask, IMASK_DEFAULT); 1824 } 1825 1826 dev->trans_start = jiffies; /* prevent tx timeout */ 1827 } 1828 1829 static void gfar_configure_coalescing(struct gfar_private *priv, 1830 unsigned long tx_mask, unsigned long rx_mask) 1831 { 1832 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1833 u32 __iomem *baddr; 1834 1835 if (priv->mode == MQ_MG_MODE) { 1836 int i = 0; 1837 1838 baddr = ®s->txic0; 1839 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { 1840 gfar_write(baddr + i, 0); 1841 if (likely(priv->tx_queue[i]->txcoalescing)) 1842 gfar_write(baddr + i, priv->tx_queue[i]->txic); 1843 } 1844 1845 baddr = ®s->rxic0; 1846 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { 1847 gfar_write(baddr + i, 0); 1848 if (likely(priv->rx_queue[i]->rxcoalescing)) 1849 gfar_write(baddr + i, priv->rx_queue[i]->rxic); 1850 } 1851 } else { 1852 /* Backward compatible case -- even if we enable 1853 * multiple queues, there's only single reg to program 1854 */ 1855 gfar_write(®s->txic, 0); 1856 if (likely(priv->tx_queue[0]->txcoalescing)) 1857 gfar_write(®s->txic, priv->tx_queue[0]->txic); 1858 1859 gfar_write(®s->rxic, 0); 1860 if (unlikely(priv->rx_queue[0]->rxcoalescing)) 1861 gfar_write(®s->rxic, priv->rx_queue[0]->rxic); 1862 } 1863 } 1864 1865 void gfar_configure_coalescing_all(struct gfar_private *priv) 1866 { 1867 gfar_configure_coalescing(priv, 0xFF, 0xFF); 1868 } 1869 1870 static int register_grp_irqs(struct gfar_priv_grp *grp) 1871 { 1872 struct gfar_private *priv = grp->priv; 1873 struct net_device *dev = priv->ndev; 1874 int err; 1875 1876 /* If the device has multiple interrupts, register for 1877 * them. Otherwise, only register for the one 1878 */ 1879 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 1880 /* Install our interrupt handlers for Error, 1881 * Transmit, and Receive 1882 */ 1883 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0, 1884 gfar_irq(grp, ER)->name, grp); 1885 if (err < 0) { 1886 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 1887 gfar_irq(grp, ER)->irq); 1888 1889 goto err_irq_fail; 1890 } 1891 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0, 1892 gfar_irq(grp, TX)->name, grp); 1893 if (err < 0) { 1894 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 1895 gfar_irq(grp, TX)->irq); 1896 goto tx_irq_fail; 1897 } 1898 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0, 1899 gfar_irq(grp, RX)->name, grp); 1900 if (err < 0) { 1901 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 1902 gfar_irq(grp, RX)->irq); 1903 goto rx_irq_fail; 1904 } 1905 } else { 1906 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0, 1907 gfar_irq(grp, TX)->name, grp); 1908 if (err < 0) { 1909 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 1910 gfar_irq(grp, TX)->irq); 1911 goto err_irq_fail; 1912 } 1913 } 1914 1915 return 0; 1916 1917 rx_irq_fail: 1918 free_irq(gfar_irq(grp, TX)->irq, grp); 1919 tx_irq_fail: 1920 free_irq(gfar_irq(grp, ER)->irq, grp); 1921 err_irq_fail: 1922 return err; 1923 1924 } 1925 1926 /* Bring the controller up and running */ 1927 int startup_gfar(struct net_device *ndev) 1928 { 1929 struct gfar_private *priv = netdev_priv(ndev); 1930 struct gfar __iomem *regs = NULL; 1931 int err, i, j; 1932 1933 for (i = 0; i < priv->num_grps; i++) { 1934 regs= priv->gfargrp[i].regs; 1935 gfar_write(®s->imask, IMASK_INIT_CLEAR); 1936 } 1937 1938 regs= priv->gfargrp[0].regs; 1939 err = gfar_alloc_skb_resources(ndev); 1940 if (err) 1941 return err; 1942 1943 gfar_init_mac(ndev); 1944 1945 for (i = 0; i < priv->num_grps; i++) { 1946 err = register_grp_irqs(&priv->gfargrp[i]); 1947 if (err) { 1948 for (j = 0; j < i; j++) 1949 free_grp_irqs(&priv->gfargrp[j]); 1950 goto irq_fail; 1951 } 1952 } 1953 1954 /* Start the controller */ 1955 gfar_start(ndev); 1956 1957 phy_start(priv->phydev); 1958 1959 gfar_configure_coalescing_all(priv); 1960 1961 return 0; 1962 1963 irq_fail: 1964 free_skb_resources(priv); 1965 return err; 1966 } 1967 1968 /* Called when something needs to use the ethernet device 1969 * Returns 0 for success. 1970 */ 1971 static int gfar_enet_open(struct net_device *dev) 1972 { 1973 struct gfar_private *priv = netdev_priv(dev); 1974 int err; 1975 1976 enable_napi(priv); 1977 1978 /* Initialize a bunch of registers */ 1979 init_registers(dev); 1980 1981 gfar_set_mac_address(dev); 1982 1983 err = init_phy(dev); 1984 1985 if (err) { 1986 disable_napi(priv); 1987 return err; 1988 } 1989 1990 err = startup_gfar(dev); 1991 if (err) { 1992 disable_napi(priv); 1993 return err; 1994 } 1995 1996 netif_tx_start_all_queues(dev); 1997 1998 device_set_wakeup_enable(&dev->dev, priv->wol_en); 1999 2000 return err; 2001 } 2002 2003 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) 2004 { 2005 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); 2006 2007 memset(fcb, 0, GMAC_FCB_LEN); 2008 2009 return fcb; 2010 } 2011 2012 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb, 2013 int fcb_length) 2014 { 2015 /* If we're here, it's a IP packet with a TCP or UDP 2016 * payload. We set it to checksum, using a pseudo-header 2017 * we provide 2018 */ 2019 u8 flags = TXFCB_DEFAULT; 2020 2021 /* Tell the controller what the protocol is 2022 * And provide the already calculated phcs 2023 */ 2024 if (ip_hdr(skb)->protocol == IPPROTO_UDP) { 2025 flags |= TXFCB_UDP; 2026 fcb->phcs = udp_hdr(skb)->check; 2027 } else 2028 fcb->phcs = tcp_hdr(skb)->check; 2029 2030 /* l3os is the distance between the start of the 2031 * frame (skb->data) and the start of the IP hdr. 2032 * l4os is the distance between the start of the 2033 * l3 hdr and the l4 hdr 2034 */ 2035 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length); 2036 fcb->l4os = skb_network_header_len(skb); 2037 2038 fcb->flags = flags; 2039 } 2040 2041 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) 2042 { 2043 fcb->flags |= TXFCB_VLN; 2044 fcb->vlctl = vlan_tx_tag_get(skb); 2045 } 2046 2047 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, 2048 struct txbd8 *base, int ring_size) 2049 { 2050 struct txbd8 *new_bd = bdp + stride; 2051 2052 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; 2053 } 2054 2055 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, 2056 int ring_size) 2057 { 2058 return skip_txbd(bdp, 1, base, ring_size); 2059 } 2060 2061 /* eTSEC12: csum generation not supported for some fcb offsets */ 2062 static inline bool gfar_csum_errata_12(struct gfar_private *priv, 2063 unsigned long fcb_addr) 2064 { 2065 return (gfar_has_errata(priv, GFAR_ERRATA_12) && 2066 (fcb_addr % 0x20) > 0x18); 2067 } 2068 2069 /* eTSEC76: csum generation for frames larger than 2500 may 2070 * cause excess delays before start of transmission 2071 */ 2072 static inline bool gfar_csum_errata_76(struct gfar_private *priv, 2073 unsigned int len) 2074 { 2075 return (gfar_has_errata(priv, GFAR_ERRATA_76) && 2076 (len > 2500)); 2077 } 2078 2079 /* This is called by the kernel when a frame is ready for transmission. 2080 * It is pointed to by the dev->hard_start_xmit function pointer 2081 */ 2082 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) 2083 { 2084 struct gfar_private *priv = netdev_priv(dev); 2085 struct gfar_priv_tx_q *tx_queue = NULL; 2086 struct netdev_queue *txq; 2087 struct gfar __iomem *regs = NULL; 2088 struct txfcb *fcb = NULL; 2089 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; 2090 u32 lstatus; 2091 int i, rq = 0; 2092 int do_tstamp, do_csum, do_vlan; 2093 u32 bufaddr; 2094 unsigned long flags; 2095 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0; 2096 2097 rq = skb->queue_mapping; 2098 tx_queue = priv->tx_queue[rq]; 2099 txq = netdev_get_tx_queue(dev, rq); 2100 base = tx_queue->tx_bd_base; 2101 regs = tx_queue->grp->regs; 2102 2103 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed); 2104 do_vlan = vlan_tx_tag_present(skb); 2105 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2106 priv->hwts_tx_en; 2107 2108 if (do_csum || do_vlan) 2109 fcb_len = GMAC_FCB_LEN; 2110 2111 /* check if time stamp should be generated */ 2112 if (unlikely(do_tstamp)) 2113 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN; 2114 2115 /* make space for additional header when fcb is needed */ 2116 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) { 2117 struct sk_buff *skb_new; 2118 2119 skb_new = skb_realloc_headroom(skb, fcb_len); 2120 if (!skb_new) { 2121 dev->stats.tx_errors++; 2122 kfree_skb(skb); 2123 return NETDEV_TX_OK; 2124 } 2125 2126 if (skb->sk) 2127 skb_set_owner_w(skb_new, skb->sk); 2128 consume_skb(skb); 2129 skb = skb_new; 2130 } 2131 2132 /* total number of fragments in the SKB */ 2133 nr_frags = skb_shinfo(skb)->nr_frags; 2134 2135 /* calculate the required number of TxBDs for this skb */ 2136 if (unlikely(do_tstamp)) 2137 nr_txbds = nr_frags + 2; 2138 else 2139 nr_txbds = nr_frags + 1; 2140 2141 /* check if there is space to queue this packet */ 2142 if (nr_txbds > tx_queue->num_txbdfree) { 2143 /* no space, stop the queue */ 2144 netif_tx_stop_queue(txq); 2145 dev->stats.tx_fifo_errors++; 2146 return NETDEV_TX_BUSY; 2147 } 2148 2149 /* Update transmit stats */ 2150 bytes_sent = skb->len; 2151 tx_queue->stats.tx_bytes += bytes_sent; 2152 /* keep Tx bytes on wire for BQL accounting */ 2153 GFAR_CB(skb)->bytes_sent = bytes_sent; 2154 tx_queue->stats.tx_packets++; 2155 2156 txbdp = txbdp_start = tx_queue->cur_tx; 2157 lstatus = txbdp->lstatus; 2158 2159 /* Time stamp insertion requires one additional TxBD */ 2160 if (unlikely(do_tstamp)) 2161 txbdp_tstamp = txbdp = next_txbd(txbdp, base, 2162 tx_queue->tx_ring_size); 2163 2164 if (nr_frags == 0) { 2165 if (unlikely(do_tstamp)) 2166 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST | 2167 TXBD_INTERRUPT); 2168 else 2169 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 2170 } else { 2171 /* Place the fragment addresses and lengths into the TxBDs */ 2172 for (i = 0; i < nr_frags; i++) { 2173 unsigned int frag_len; 2174 /* Point at the next BD, wrapping as needed */ 2175 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2176 2177 frag_len = skb_shinfo(skb)->frags[i].size; 2178 2179 lstatus = txbdp->lstatus | frag_len | 2180 BD_LFLAG(TXBD_READY); 2181 2182 /* Handle the last BD specially */ 2183 if (i == nr_frags - 1) 2184 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 2185 2186 bufaddr = skb_frag_dma_map(priv->dev, 2187 &skb_shinfo(skb)->frags[i], 2188 0, 2189 frag_len, 2190 DMA_TO_DEVICE); 2191 2192 /* set the TxBD length and buffer pointer */ 2193 txbdp->bufPtr = bufaddr; 2194 txbdp->lstatus = lstatus; 2195 } 2196 2197 lstatus = txbdp_start->lstatus; 2198 } 2199 2200 /* Add TxPAL between FCB and frame if required */ 2201 if (unlikely(do_tstamp)) { 2202 skb_push(skb, GMAC_TXPAL_LEN); 2203 memset(skb->data, 0, GMAC_TXPAL_LEN); 2204 } 2205 2206 /* Add TxFCB if required */ 2207 if (fcb_len) { 2208 fcb = gfar_add_fcb(skb); 2209 lstatus |= BD_LFLAG(TXBD_TOE); 2210 } 2211 2212 /* Set up checksumming */ 2213 if (do_csum) { 2214 gfar_tx_checksum(skb, fcb, fcb_len); 2215 2216 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) || 2217 unlikely(gfar_csum_errata_76(priv, skb->len))) { 2218 __skb_pull(skb, GMAC_FCB_LEN); 2219 skb_checksum_help(skb); 2220 if (do_vlan || do_tstamp) { 2221 /* put back a new fcb for vlan/tstamp TOE */ 2222 fcb = gfar_add_fcb(skb); 2223 } else { 2224 /* Tx TOE not used */ 2225 lstatus &= ~(BD_LFLAG(TXBD_TOE)); 2226 fcb = NULL; 2227 } 2228 } 2229 } 2230 2231 if (do_vlan) 2232 gfar_tx_vlan(skb, fcb); 2233 2234 /* Setup tx hardware time stamping if requested */ 2235 if (unlikely(do_tstamp)) { 2236 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2237 fcb->ptp = 1; 2238 } 2239 2240 txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data, 2241 skb_headlen(skb), DMA_TO_DEVICE); 2242 2243 /* If time stamping is requested one additional TxBD must be set up. The 2244 * first TxBD points to the FCB and must have a data length of 2245 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with 2246 * the full frame length. 2247 */ 2248 if (unlikely(do_tstamp)) { 2249 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len; 2250 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) | 2251 (skb_headlen(skb) - fcb_len); 2252 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; 2253 } else { 2254 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); 2255 } 2256 2257 netdev_tx_sent_queue(txq, bytes_sent); 2258 2259 /* We can work in parallel with gfar_clean_tx_ring(), except 2260 * when modifying num_txbdfree. Note that we didn't grab the lock 2261 * when we were reading the num_txbdfree and checking for available 2262 * space, that's because outside of this function it can only grow, 2263 * and once we've got needed space, it cannot suddenly disappear. 2264 * 2265 * The lock also protects us from gfar_error(), which can modify 2266 * regs->tstat and thus retrigger the transfers, which is why we 2267 * also must grab the lock before setting ready bit for the first 2268 * to be transmitted BD. 2269 */ 2270 spin_lock_irqsave(&tx_queue->txlock, flags); 2271 2272 /* The powerpc-specific eieio() is used, as wmb() has too strong 2273 * semantics (it requires synchronization between cacheable and 2274 * uncacheable mappings, which eieio doesn't provide and which we 2275 * don't need), thus requiring a more expensive sync instruction. At 2276 * some point, the set of architecture-independent barrier functions 2277 * should be expanded to include weaker barriers. 2278 */ 2279 eieio(); 2280 2281 txbdp_start->lstatus = lstatus; 2282 2283 eieio(); /* force lstatus write before tx_skbuff */ 2284 2285 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; 2286 2287 /* Update the current skb pointer to the next entry we will use 2288 * (wrapping if necessary) 2289 */ 2290 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & 2291 TX_RING_MOD_MASK(tx_queue->tx_ring_size); 2292 2293 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2294 2295 /* reduce TxBD free count */ 2296 tx_queue->num_txbdfree -= (nr_txbds); 2297 2298 /* If the next BD still needs to be cleaned up, then the bds 2299 * are full. We need to tell the kernel to stop sending us stuff. 2300 */ 2301 if (!tx_queue->num_txbdfree) { 2302 netif_tx_stop_queue(txq); 2303 2304 dev->stats.tx_fifo_errors++; 2305 } 2306 2307 /* Tell the DMA to go go go */ 2308 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); 2309 2310 /* Unlock priv */ 2311 spin_unlock_irqrestore(&tx_queue->txlock, flags); 2312 2313 return NETDEV_TX_OK; 2314 } 2315 2316 /* Stops the kernel queue, and halts the controller */ 2317 static int gfar_close(struct net_device *dev) 2318 { 2319 struct gfar_private *priv = netdev_priv(dev); 2320 2321 disable_napi(priv); 2322 2323 cancel_work_sync(&priv->reset_task); 2324 stop_gfar(dev); 2325 2326 /* Disconnect from the PHY */ 2327 phy_disconnect(priv->phydev); 2328 priv->phydev = NULL; 2329 2330 netif_tx_stop_all_queues(dev); 2331 2332 return 0; 2333 } 2334 2335 /* Changes the mac address if the controller is not running. */ 2336 static int gfar_set_mac_address(struct net_device *dev) 2337 { 2338 gfar_set_mac_for_addr(dev, 0, dev->dev_addr); 2339 2340 return 0; 2341 } 2342 2343 /* Check if rx parser should be activated */ 2344 void gfar_check_rx_parser_mode(struct gfar_private *priv) 2345 { 2346 struct gfar __iomem *regs; 2347 u32 tempval; 2348 2349 regs = priv->gfargrp[0].regs; 2350 2351 tempval = gfar_read(®s->rctrl); 2352 /* If parse is no longer required, then disable parser */ 2353 if (tempval & RCTRL_REQ_PARSER) { 2354 tempval |= RCTRL_PRSDEP_INIT; 2355 priv->uses_rxfcb = 1; 2356 } else { 2357 tempval &= ~RCTRL_PRSDEP_INIT; 2358 priv->uses_rxfcb = 0; 2359 } 2360 gfar_write(®s->rctrl, tempval); 2361 } 2362 2363 /* Enables and disables VLAN insertion/extraction */ 2364 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features) 2365 { 2366 struct gfar_private *priv = netdev_priv(dev); 2367 struct gfar __iomem *regs = NULL; 2368 unsigned long flags; 2369 u32 tempval; 2370 2371 regs = priv->gfargrp[0].regs; 2372 local_irq_save(flags); 2373 lock_rx_qs(priv); 2374 2375 if (features & NETIF_F_HW_VLAN_CTAG_TX) { 2376 /* Enable VLAN tag insertion */ 2377 tempval = gfar_read(®s->tctrl); 2378 tempval |= TCTRL_VLINS; 2379 gfar_write(®s->tctrl, tempval); 2380 } else { 2381 /* Disable VLAN tag insertion */ 2382 tempval = gfar_read(®s->tctrl); 2383 tempval &= ~TCTRL_VLINS; 2384 gfar_write(®s->tctrl, tempval); 2385 } 2386 2387 if (features & NETIF_F_HW_VLAN_CTAG_RX) { 2388 /* Enable VLAN tag extraction */ 2389 tempval = gfar_read(®s->rctrl); 2390 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); 2391 gfar_write(®s->rctrl, tempval); 2392 priv->uses_rxfcb = 1; 2393 } else { 2394 /* Disable VLAN tag extraction */ 2395 tempval = gfar_read(®s->rctrl); 2396 tempval &= ~RCTRL_VLEX; 2397 gfar_write(®s->rctrl, tempval); 2398 2399 gfar_check_rx_parser_mode(priv); 2400 } 2401 2402 gfar_change_mtu(dev, dev->mtu); 2403 2404 unlock_rx_qs(priv); 2405 local_irq_restore(flags); 2406 } 2407 2408 static int gfar_change_mtu(struct net_device *dev, int new_mtu) 2409 { 2410 int tempsize, tempval; 2411 struct gfar_private *priv = netdev_priv(dev); 2412 struct gfar __iomem *regs = priv->gfargrp[0].regs; 2413 int oldsize = priv->rx_buffer_size; 2414 int frame_size = new_mtu + ETH_HLEN; 2415 2416 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { 2417 netif_err(priv, drv, dev, "Invalid MTU setting\n"); 2418 return -EINVAL; 2419 } 2420 2421 if (priv->uses_rxfcb) 2422 frame_size += GMAC_FCB_LEN; 2423 2424 frame_size += priv->padding; 2425 2426 tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + 2427 INCREMENTAL_BUFFER_SIZE; 2428 2429 /* Only stop and start the controller if it isn't already 2430 * stopped, and we changed something 2431 */ 2432 if ((oldsize != tempsize) && (dev->flags & IFF_UP)) 2433 stop_gfar(dev); 2434 2435 priv->rx_buffer_size = tempsize; 2436 2437 dev->mtu = new_mtu; 2438 2439 gfar_write(®s->mrblr, priv->rx_buffer_size); 2440 gfar_write(®s->maxfrm, priv->rx_buffer_size); 2441 2442 /* If the mtu is larger than the max size for standard 2443 * ethernet frames (ie, a jumbo frame), then set maccfg2 2444 * to allow huge frames, and to check the length 2445 */ 2446 tempval = gfar_read(®s->maccfg2); 2447 2448 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE || 2449 gfar_has_errata(priv, GFAR_ERRATA_74)) 2450 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); 2451 else 2452 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); 2453 2454 gfar_write(®s->maccfg2, tempval); 2455 2456 if ((oldsize != tempsize) && (dev->flags & IFF_UP)) 2457 startup_gfar(dev); 2458 2459 return 0; 2460 } 2461 2462 /* gfar_reset_task gets scheduled when a packet has not been 2463 * transmitted after a set amount of time. 2464 * For now, assume that clearing out all the structures, and 2465 * starting over will fix the problem. 2466 */ 2467 static void gfar_reset_task(struct work_struct *work) 2468 { 2469 struct gfar_private *priv = container_of(work, struct gfar_private, 2470 reset_task); 2471 struct net_device *dev = priv->ndev; 2472 2473 if (dev->flags & IFF_UP) { 2474 netif_tx_stop_all_queues(dev); 2475 stop_gfar(dev); 2476 startup_gfar(dev); 2477 netif_tx_start_all_queues(dev); 2478 } 2479 2480 netif_tx_schedule_all(dev); 2481 } 2482 2483 static void gfar_timeout(struct net_device *dev) 2484 { 2485 struct gfar_private *priv = netdev_priv(dev); 2486 2487 dev->stats.tx_errors++; 2488 schedule_work(&priv->reset_task); 2489 } 2490 2491 static void gfar_align_skb(struct sk_buff *skb) 2492 { 2493 /* We need the data buffer to be aligned properly. We will reserve 2494 * as many bytes as needed to align the data properly 2495 */ 2496 skb_reserve(skb, RXBUF_ALIGNMENT - 2497 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1))); 2498 } 2499 2500 /* Interrupt Handler for Transmit complete */ 2501 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) 2502 { 2503 struct net_device *dev = tx_queue->dev; 2504 struct netdev_queue *txq; 2505 struct gfar_private *priv = netdev_priv(dev); 2506 struct txbd8 *bdp, *next = NULL; 2507 struct txbd8 *lbdp = NULL; 2508 struct txbd8 *base = tx_queue->tx_bd_base; 2509 struct sk_buff *skb; 2510 int skb_dirtytx; 2511 int tx_ring_size = tx_queue->tx_ring_size; 2512 int frags = 0, nr_txbds = 0; 2513 int i; 2514 int howmany = 0; 2515 int tqi = tx_queue->qindex; 2516 unsigned int bytes_sent = 0; 2517 u32 lstatus; 2518 size_t buflen; 2519 2520 txq = netdev_get_tx_queue(dev, tqi); 2521 bdp = tx_queue->dirty_tx; 2522 skb_dirtytx = tx_queue->skb_dirtytx; 2523 2524 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { 2525 unsigned long flags; 2526 2527 frags = skb_shinfo(skb)->nr_frags; 2528 2529 /* When time stamping, one additional TxBD must be freed. 2530 * Also, we need to dma_unmap_single() the TxPAL. 2531 */ 2532 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) 2533 nr_txbds = frags + 2; 2534 else 2535 nr_txbds = frags + 1; 2536 2537 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); 2538 2539 lstatus = lbdp->lstatus; 2540 2541 /* Only clean completed frames */ 2542 if ((lstatus & BD_LFLAG(TXBD_READY)) && 2543 (lstatus & BD_LENGTH_MASK)) 2544 break; 2545 2546 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { 2547 next = next_txbd(bdp, base, tx_ring_size); 2548 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN; 2549 } else 2550 buflen = bdp->length; 2551 2552 dma_unmap_single(priv->dev, bdp->bufPtr, 2553 buflen, DMA_TO_DEVICE); 2554 2555 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { 2556 struct skb_shared_hwtstamps shhwtstamps; 2557 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7); 2558 2559 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 2560 shhwtstamps.hwtstamp = ns_to_ktime(*ns); 2561 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN); 2562 skb_tstamp_tx(skb, &shhwtstamps); 2563 bdp->lstatus &= BD_LFLAG(TXBD_WRAP); 2564 bdp = next; 2565 } 2566 2567 bdp->lstatus &= BD_LFLAG(TXBD_WRAP); 2568 bdp = next_txbd(bdp, base, tx_ring_size); 2569 2570 for (i = 0; i < frags; i++) { 2571 dma_unmap_page(priv->dev, bdp->bufPtr, 2572 bdp->length, DMA_TO_DEVICE); 2573 bdp->lstatus &= BD_LFLAG(TXBD_WRAP); 2574 bdp = next_txbd(bdp, base, tx_ring_size); 2575 } 2576 2577 bytes_sent += GFAR_CB(skb)->bytes_sent; 2578 2579 dev_kfree_skb_any(skb); 2580 2581 tx_queue->tx_skbuff[skb_dirtytx] = NULL; 2582 2583 skb_dirtytx = (skb_dirtytx + 1) & 2584 TX_RING_MOD_MASK(tx_ring_size); 2585 2586 howmany++; 2587 spin_lock_irqsave(&tx_queue->txlock, flags); 2588 tx_queue->num_txbdfree += nr_txbds; 2589 spin_unlock_irqrestore(&tx_queue->txlock, flags); 2590 } 2591 2592 /* If we freed a buffer, we can restart transmission, if necessary */ 2593 if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree) 2594 netif_wake_subqueue(dev, tqi); 2595 2596 /* Update dirty indicators */ 2597 tx_queue->skb_dirtytx = skb_dirtytx; 2598 tx_queue->dirty_tx = bdp; 2599 2600 netdev_tx_completed_queue(txq, howmany, bytes_sent); 2601 } 2602 2603 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp) 2604 { 2605 unsigned long flags; 2606 2607 spin_lock_irqsave(&gfargrp->grplock, flags); 2608 if (napi_schedule_prep(&gfargrp->napi)) { 2609 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED); 2610 __napi_schedule(&gfargrp->napi); 2611 } else { 2612 /* Clear IEVENT, so interrupts aren't called again 2613 * because of the packets that have already arrived. 2614 */ 2615 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK); 2616 } 2617 spin_unlock_irqrestore(&gfargrp->grplock, flags); 2618 2619 } 2620 2621 /* Interrupt Handler for Transmit complete */ 2622 static irqreturn_t gfar_transmit(int irq, void *grp_id) 2623 { 2624 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); 2625 return IRQ_HANDLED; 2626 } 2627 2628 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, 2629 struct sk_buff *skb) 2630 { 2631 struct net_device *dev = rx_queue->dev; 2632 struct gfar_private *priv = netdev_priv(dev); 2633 dma_addr_t buf; 2634 2635 buf = dma_map_single(priv->dev, skb->data, 2636 priv->rx_buffer_size, DMA_FROM_DEVICE); 2637 gfar_init_rxbdp(rx_queue, bdp, buf); 2638 } 2639 2640 static struct sk_buff *gfar_alloc_skb(struct net_device *dev) 2641 { 2642 struct gfar_private *priv = netdev_priv(dev); 2643 struct sk_buff *skb; 2644 2645 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT); 2646 if (!skb) 2647 return NULL; 2648 2649 gfar_align_skb(skb); 2650 2651 return skb; 2652 } 2653 2654 struct sk_buff *gfar_new_skb(struct net_device *dev) 2655 { 2656 return gfar_alloc_skb(dev); 2657 } 2658 2659 static inline void count_errors(unsigned short status, struct net_device *dev) 2660 { 2661 struct gfar_private *priv = netdev_priv(dev); 2662 struct net_device_stats *stats = &dev->stats; 2663 struct gfar_extra_stats *estats = &priv->extra_stats; 2664 2665 /* If the packet was truncated, none of the other errors matter */ 2666 if (status & RXBD_TRUNCATED) { 2667 stats->rx_length_errors++; 2668 2669 atomic64_inc(&estats->rx_trunc); 2670 2671 return; 2672 } 2673 /* Count the errors, if there were any */ 2674 if (status & (RXBD_LARGE | RXBD_SHORT)) { 2675 stats->rx_length_errors++; 2676 2677 if (status & RXBD_LARGE) 2678 atomic64_inc(&estats->rx_large); 2679 else 2680 atomic64_inc(&estats->rx_short); 2681 } 2682 if (status & RXBD_NONOCTET) { 2683 stats->rx_frame_errors++; 2684 atomic64_inc(&estats->rx_nonoctet); 2685 } 2686 if (status & RXBD_CRCERR) { 2687 atomic64_inc(&estats->rx_crcerr); 2688 stats->rx_crc_errors++; 2689 } 2690 if (status & RXBD_OVERRUN) { 2691 atomic64_inc(&estats->rx_overrun); 2692 stats->rx_crc_errors++; 2693 } 2694 } 2695 2696 irqreturn_t gfar_receive(int irq, void *grp_id) 2697 { 2698 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); 2699 return IRQ_HANDLED; 2700 } 2701 2702 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) 2703 { 2704 /* If valid headers were found, and valid sums 2705 * were verified, then we tell the kernel that no 2706 * checksumming is necessary. Otherwise, it is [FIXME] 2707 */ 2708 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) 2709 skb->ip_summed = CHECKSUM_UNNECESSARY; 2710 else 2711 skb_checksum_none_assert(skb); 2712 } 2713 2714 2715 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */ 2716 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, 2717 int amount_pull, struct napi_struct *napi) 2718 { 2719 struct gfar_private *priv = netdev_priv(dev); 2720 struct rxfcb *fcb = NULL; 2721 2722 /* fcb is at the beginning if exists */ 2723 fcb = (struct rxfcb *)skb->data; 2724 2725 /* Remove the FCB from the skb 2726 * Remove the padded bytes, if there are any 2727 */ 2728 if (amount_pull) { 2729 skb_record_rx_queue(skb, fcb->rq); 2730 skb_pull(skb, amount_pull); 2731 } 2732 2733 /* Get receive timestamp from the skb */ 2734 if (priv->hwts_rx_en) { 2735 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); 2736 u64 *ns = (u64 *) skb->data; 2737 2738 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 2739 shhwtstamps->hwtstamp = ns_to_ktime(*ns); 2740 } 2741 2742 if (priv->padding) 2743 skb_pull(skb, priv->padding); 2744 2745 if (dev->features & NETIF_F_RXCSUM) 2746 gfar_rx_checksum(skb, fcb); 2747 2748 /* Tell the skb what kind of packet this is */ 2749 skb->protocol = eth_type_trans(skb, dev); 2750 2751 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here. 2752 * Even if vlan rx accel is disabled, on some chips 2753 * RXFCB_VLN is pseudo randomly set. 2754 */ 2755 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX && 2756 fcb->flags & RXFCB_VLN) 2757 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl); 2758 2759 /* Send the packet up the stack */ 2760 napi_gro_receive(napi, skb); 2761 2762 } 2763 2764 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring 2765 * until the budget/quota has been reached. Returns the number 2766 * of frames handled 2767 */ 2768 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit) 2769 { 2770 struct net_device *dev = rx_queue->dev; 2771 struct rxbd8 *bdp, *base; 2772 struct sk_buff *skb; 2773 int pkt_len; 2774 int amount_pull; 2775 int howmany = 0; 2776 struct gfar_private *priv = netdev_priv(dev); 2777 2778 /* Get the first full descriptor */ 2779 bdp = rx_queue->cur_rx; 2780 base = rx_queue->rx_bd_base; 2781 2782 amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0; 2783 2784 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { 2785 struct sk_buff *newskb; 2786 2787 rmb(); 2788 2789 /* Add another skb for the future */ 2790 newskb = gfar_new_skb(dev); 2791 2792 skb = rx_queue->rx_skbuff[rx_queue->skb_currx]; 2793 2794 dma_unmap_single(priv->dev, bdp->bufPtr, 2795 priv->rx_buffer_size, DMA_FROM_DEVICE); 2796 2797 if (unlikely(!(bdp->status & RXBD_ERR) && 2798 bdp->length > priv->rx_buffer_size)) 2799 bdp->status = RXBD_LARGE; 2800 2801 /* We drop the frame if we failed to allocate a new buffer */ 2802 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || 2803 bdp->status & RXBD_ERR)) { 2804 count_errors(bdp->status, dev); 2805 2806 if (unlikely(!newskb)) 2807 newskb = skb; 2808 else if (skb) 2809 dev_kfree_skb(skb); 2810 } else { 2811 /* Increment the number of packets */ 2812 rx_queue->stats.rx_packets++; 2813 howmany++; 2814 2815 if (likely(skb)) { 2816 pkt_len = bdp->length - ETH_FCS_LEN; 2817 /* Remove the FCS from the packet length */ 2818 skb_put(skb, pkt_len); 2819 rx_queue->stats.rx_bytes += pkt_len; 2820 skb_record_rx_queue(skb, rx_queue->qindex); 2821 gfar_process_frame(dev, skb, amount_pull, 2822 &rx_queue->grp->napi); 2823 2824 } else { 2825 netif_warn(priv, rx_err, dev, "Missing skb!\n"); 2826 rx_queue->stats.rx_dropped++; 2827 atomic64_inc(&priv->extra_stats.rx_skbmissing); 2828 } 2829 2830 } 2831 2832 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb; 2833 2834 /* Setup the new bdp */ 2835 gfar_new_rxbdp(rx_queue, bdp, newskb); 2836 2837 /* Update to the next pointer */ 2838 bdp = next_bd(bdp, base, rx_queue->rx_ring_size); 2839 2840 /* update to point at the next skb */ 2841 rx_queue->skb_currx = (rx_queue->skb_currx + 1) & 2842 RX_RING_MOD_MASK(rx_queue->rx_ring_size); 2843 } 2844 2845 /* Update the current rxbd pointer to be the next one */ 2846 rx_queue->cur_rx = bdp; 2847 2848 return howmany; 2849 } 2850 2851 static int gfar_poll_sq(struct napi_struct *napi, int budget) 2852 { 2853 struct gfar_priv_grp *gfargrp = 2854 container_of(napi, struct gfar_priv_grp, napi); 2855 struct gfar __iomem *regs = gfargrp->regs; 2856 struct gfar_priv_tx_q *tx_queue = gfargrp->priv->tx_queue[0]; 2857 struct gfar_priv_rx_q *rx_queue = gfargrp->priv->rx_queue[0]; 2858 int work_done = 0; 2859 2860 /* Clear IEVENT, so interrupts aren't called again 2861 * because of the packets that have already arrived 2862 */ 2863 gfar_write(®s->ievent, IEVENT_RTX_MASK); 2864 2865 /* run Tx cleanup to completion */ 2866 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) 2867 gfar_clean_tx_ring(tx_queue); 2868 2869 work_done = gfar_clean_rx_ring(rx_queue, budget); 2870 2871 if (work_done < budget) { 2872 napi_complete(napi); 2873 /* Clear the halt bit in RSTAT */ 2874 gfar_write(®s->rstat, gfargrp->rstat); 2875 2876 gfar_write(®s->imask, IMASK_DEFAULT); 2877 2878 /* If we are coalescing interrupts, update the timer 2879 * Otherwise, clear it 2880 */ 2881 gfar_write(®s->txic, 0); 2882 if (likely(tx_queue->txcoalescing)) 2883 gfar_write(®s->txic, tx_queue->txic); 2884 2885 gfar_write(®s->rxic, 0); 2886 if (unlikely(rx_queue->rxcoalescing)) 2887 gfar_write(®s->rxic, rx_queue->rxic); 2888 } 2889 2890 return work_done; 2891 } 2892 2893 static int gfar_poll(struct napi_struct *napi, int budget) 2894 { 2895 struct gfar_priv_grp *gfargrp = 2896 container_of(napi, struct gfar_priv_grp, napi); 2897 struct gfar_private *priv = gfargrp->priv; 2898 struct gfar __iomem *regs = gfargrp->regs; 2899 struct gfar_priv_tx_q *tx_queue = NULL; 2900 struct gfar_priv_rx_q *rx_queue = NULL; 2901 int work_done = 0, work_done_per_q = 0; 2902 int i, budget_per_q = 0; 2903 int has_tx_work; 2904 unsigned long rstat_rxf; 2905 int num_act_queues; 2906 2907 /* Clear IEVENT, so interrupts aren't called again 2908 * because of the packets that have already arrived 2909 */ 2910 gfar_write(®s->ievent, IEVENT_RTX_MASK); 2911 2912 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK; 2913 2914 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS); 2915 if (num_act_queues) 2916 budget_per_q = budget/num_act_queues; 2917 2918 while (1) { 2919 has_tx_work = 0; 2920 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) { 2921 tx_queue = priv->tx_queue[i]; 2922 /* run Tx cleanup to completion */ 2923 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) { 2924 gfar_clean_tx_ring(tx_queue); 2925 has_tx_work = 1; 2926 } 2927 } 2928 2929 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { 2930 /* skip queue if not active */ 2931 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i))) 2932 continue; 2933 2934 rx_queue = priv->rx_queue[i]; 2935 work_done_per_q = 2936 gfar_clean_rx_ring(rx_queue, budget_per_q); 2937 work_done += work_done_per_q; 2938 2939 /* finished processing this queue */ 2940 if (work_done_per_q < budget_per_q) { 2941 /* clear active queue hw indication */ 2942 gfar_write(®s->rstat, 2943 RSTAT_CLEAR_RXF0 >> i); 2944 rstat_rxf &= ~(RSTAT_CLEAR_RXF0 >> i); 2945 num_act_queues--; 2946 2947 if (!num_act_queues) 2948 break; 2949 /* recompute budget per Rx queue */ 2950 budget_per_q = 2951 (budget - work_done) / num_act_queues; 2952 } 2953 } 2954 2955 if (work_done >= budget) 2956 break; 2957 2958 if (!num_act_queues && !has_tx_work) { 2959 2960 napi_complete(napi); 2961 2962 /* Clear the halt bit in RSTAT */ 2963 gfar_write(®s->rstat, gfargrp->rstat); 2964 2965 gfar_write(®s->imask, IMASK_DEFAULT); 2966 2967 /* If we are coalescing interrupts, update the timer 2968 * Otherwise, clear it 2969 */ 2970 gfar_configure_coalescing(priv, gfargrp->rx_bit_map, 2971 gfargrp->tx_bit_map); 2972 break; 2973 } 2974 } 2975 2976 return work_done; 2977 } 2978 2979 #ifdef CONFIG_NET_POLL_CONTROLLER 2980 /* Polling 'interrupt' - used by things like netconsole to send skbs 2981 * without having to re-enable interrupts. It's not called while 2982 * the interrupt routine is executing. 2983 */ 2984 static void gfar_netpoll(struct net_device *dev) 2985 { 2986 struct gfar_private *priv = netdev_priv(dev); 2987 int i; 2988 2989 /* If the device has multiple interrupts, run tx/rx */ 2990 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 2991 for (i = 0; i < priv->num_grps; i++) { 2992 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 2993 2994 disable_irq(gfar_irq(grp, TX)->irq); 2995 disable_irq(gfar_irq(grp, RX)->irq); 2996 disable_irq(gfar_irq(grp, ER)->irq); 2997 gfar_interrupt(gfar_irq(grp, TX)->irq, grp); 2998 enable_irq(gfar_irq(grp, ER)->irq); 2999 enable_irq(gfar_irq(grp, RX)->irq); 3000 enable_irq(gfar_irq(grp, TX)->irq); 3001 } 3002 } else { 3003 for (i = 0; i < priv->num_grps; i++) { 3004 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 3005 3006 disable_irq(gfar_irq(grp, TX)->irq); 3007 gfar_interrupt(gfar_irq(grp, TX)->irq, grp); 3008 enable_irq(gfar_irq(grp, TX)->irq); 3009 } 3010 } 3011 } 3012 #endif 3013 3014 /* The interrupt handler for devices with one interrupt */ 3015 static irqreturn_t gfar_interrupt(int irq, void *grp_id) 3016 { 3017 struct gfar_priv_grp *gfargrp = grp_id; 3018 3019 /* Save ievent for future reference */ 3020 u32 events = gfar_read(&gfargrp->regs->ievent); 3021 3022 /* Check for reception */ 3023 if (events & IEVENT_RX_MASK) 3024 gfar_receive(irq, grp_id); 3025 3026 /* Check for transmit completion */ 3027 if (events & IEVENT_TX_MASK) 3028 gfar_transmit(irq, grp_id); 3029 3030 /* Check for errors */ 3031 if (events & IEVENT_ERR_MASK) 3032 gfar_error(irq, grp_id); 3033 3034 return IRQ_HANDLED; 3035 } 3036 3037 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv) 3038 { 3039 struct phy_device *phydev = priv->phydev; 3040 u32 val = 0; 3041 3042 if (!phydev->duplex) 3043 return val; 3044 3045 if (!priv->pause_aneg_en) { 3046 if (priv->tx_pause_en) 3047 val |= MACCFG1_TX_FLOW; 3048 if (priv->rx_pause_en) 3049 val |= MACCFG1_RX_FLOW; 3050 } else { 3051 u16 lcl_adv, rmt_adv; 3052 u8 flowctrl; 3053 /* get link partner capabilities */ 3054 rmt_adv = 0; 3055 if (phydev->pause) 3056 rmt_adv = LPA_PAUSE_CAP; 3057 if (phydev->asym_pause) 3058 rmt_adv |= LPA_PAUSE_ASYM; 3059 3060 lcl_adv = mii_advertise_flowctrl(phydev->advertising); 3061 3062 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 3063 if (flowctrl & FLOW_CTRL_TX) 3064 val |= MACCFG1_TX_FLOW; 3065 if (flowctrl & FLOW_CTRL_RX) 3066 val |= MACCFG1_RX_FLOW; 3067 } 3068 3069 return val; 3070 } 3071 3072 /* Called every time the controller might need to be made 3073 * aware of new link state. The PHY code conveys this 3074 * information through variables in the phydev structure, and this 3075 * function converts those variables into the appropriate 3076 * register values, and can bring down the device if needed. 3077 */ 3078 static void adjust_link(struct net_device *dev) 3079 { 3080 struct gfar_private *priv = netdev_priv(dev); 3081 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3082 unsigned long flags; 3083 struct phy_device *phydev = priv->phydev; 3084 int new_state = 0; 3085 3086 local_irq_save(flags); 3087 lock_tx_qs(priv); 3088 3089 if (phydev->link) { 3090 u32 tempval1 = gfar_read(®s->maccfg1); 3091 u32 tempval = gfar_read(®s->maccfg2); 3092 u32 ecntrl = gfar_read(®s->ecntrl); 3093 3094 /* Now we make sure that we can be in full duplex mode. 3095 * If not, we operate in half-duplex mode. 3096 */ 3097 if (phydev->duplex != priv->oldduplex) { 3098 new_state = 1; 3099 if (!(phydev->duplex)) 3100 tempval &= ~(MACCFG2_FULL_DUPLEX); 3101 else 3102 tempval |= MACCFG2_FULL_DUPLEX; 3103 3104 priv->oldduplex = phydev->duplex; 3105 } 3106 3107 if (phydev->speed != priv->oldspeed) { 3108 new_state = 1; 3109 switch (phydev->speed) { 3110 case 1000: 3111 tempval = 3112 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); 3113 3114 ecntrl &= ~(ECNTRL_R100); 3115 break; 3116 case 100: 3117 case 10: 3118 tempval = 3119 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); 3120 3121 /* Reduced mode distinguishes 3122 * between 10 and 100 3123 */ 3124 if (phydev->speed == SPEED_100) 3125 ecntrl |= ECNTRL_R100; 3126 else 3127 ecntrl &= ~(ECNTRL_R100); 3128 break; 3129 default: 3130 netif_warn(priv, link, dev, 3131 "Ack! Speed (%d) is not 10/100/1000!\n", 3132 phydev->speed); 3133 break; 3134 } 3135 3136 priv->oldspeed = phydev->speed; 3137 } 3138 3139 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); 3140 tempval1 |= gfar_get_flowctrl_cfg(priv); 3141 3142 gfar_write(®s->maccfg1, tempval1); 3143 gfar_write(®s->maccfg2, tempval); 3144 gfar_write(®s->ecntrl, ecntrl); 3145 3146 if (!priv->oldlink) { 3147 new_state = 1; 3148 priv->oldlink = 1; 3149 } 3150 } else if (priv->oldlink) { 3151 new_state = 1; 3152 priv->oldlink = 0; 3153 priv->oldspeed = 0; 3154 priv->oldduplex = -1; 3155 } 3156 3157 if (new_state && netif_msg_link(priv)) 3158 phy_print_status(phydev); 3159 unlock_tx_qs(priv); 3160 local_irq_restore(flags); 3161 } 3162 3163 /* Update the hash table based on the current list of multicast 3164 * addresses we subscribe to. Also, change the promiscuity of 3165 * the device based on the flags (this function is called 3166 * whenever dev->flags is changed 3167 */ 3168 static void gfar_set_multi(struct net_device *dev) 3169 { 3170 struct netdev_hw_addr *ha; 3171 struct gfar_private *priv = netdev_priv(dev); 3172 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3173 u32 tempval; 3174 3175 if (dev->flags & IFF_PROMISC) { 3176 /* Set RCTRL to PROM */ 3177 tempval = gfar_read(®s->rctrl); 3178 tempval |= RCTRL_PROM; 3179 gfar_write(®s->rctrl, tempval); 3180 } else { 3181 /* Set RCTRL to not PROM */ 3182 tempval = gfar_read(®s->rctrl); 3183 tempval &= ~(RCTRL_PROM); 3184 gfar_write(®s->rctrl, tempval); 3185 } 3186 3187 if (dev->flags & IFF_ALLMULTI) { 3188 /* Set the hash to rx all multicast frames */ 3189 gfar_write(®s->igaddr0, 0xffffffff); 3190 gfar_write(®s->igaddr1, 0xffffffff); 3191 gfar_write(®s->igaddr2, 0xffffffff); 3192 gfar_write(®s->igaddr3, 0xffffffff); 3193 gfar_write(®s->igaddr4, 0xffffffff); 3194 gfar_write(®s->igaddr5, 0xffffffff); 3195 gfar_write(®s->igaddr6, 0xffffffff); 3196 gfar_write(®s->igaddr7, 0xffffffff); 3197 gfar_write(®s->gaddr0, 0xffffffff); 3198 gfar_write(®s->gaddr1, 0xffffffff); 3199 gfar_write(®s->gaddr2, 0xffffffff); 3200 gfar_write(®s->gaddr3, 0xffffffff); 3201 gfar_write(®s->gaddr4, 0xffffffff); 3202 gfar_write(®s->gaddr5, 0xffffffff); 3203 gfar_write(®s->gaddr6, 0xffffffff); 3204 gfar_write(®s->gaddr7, 0xffffffff); 3205 } else { 3206 int em_num; 3207 int idx; 3208 3209 /* zero out the hash */ 3210 gfar_write(®s->igaddr0, 0x0); 3211 gfar_write(®s->igaddr1, 0x0); 3212 gfar_write(®s->igaddr2, 0x0); 3213 gfar_write(®s->igaddr3, 0x0); 3214 gfar_write(®s->igaddr4, 0x0); 3215 gfar_write(®s->igaddr5, 0x0); 3216 gfar_write(®s->igaddr6, 0x0); 3217 gfar_write(®s->igaddr7, 0x0); 3218 gfar_write(®s->gaddr0, 0x0); 3219 gfar_write(®s->gaddr1, 0x0); 3220 gfar_write(®s->gaddr2, 0x0); 3221 gfar_write(®s->gaddr3, 0x0); 3222 gfar_write(®s->gaddr4, 0x0); 3223 gfar_write(®s->gaddr5, 0x0); 3224 gfar_write(®s->gaddr6, 0x0); 3225 gfar_write(®s->gaddr7, 0x0); 3226 3227 /* If we have extended hash tables, we need to 3228 * clear the exact match registers to prepare for 3229 * setting them 3230 */ 3231 if (priv->extended_hash) { 3232 em_num = GFAR_EM_NUM + 1; 3233 gfar_clear_exact_match(dev); 3234 idx = 1; 3235 } else { 3236 idx = 0; 3237 em_num = 0; 3238 } 3239 3240 if (netdev_mc_empty(dev)) 3241 return; 3242 3243 /* Parse the list, and set the appropriate bits */ 3244 netdev_for_each_mc_addr(ha, dev) { 3245 if (idx < em_num) { 3246 gfar_set_mac_for_addr(dev, idx, ha->addr); 3247 idx++; 3248 } else 3249 gfar_set_hash_for_addr(dev, ha->addr); 3250 } 3251 } 3252 } 3253 3254 3255 /* Clears each of the exact match registers to zero, so they 3256 * don't interfere with normal reception 3257 */ 3258 static void gfar_clear_exact_match(struct net_device *dev) 3259 { 3260 int idx; 3261 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; 3262 3263 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++) 3264 gfar_set_mac_for_addr(dev, idx, zero_arr); 3265 } 3266 3267 /* Set the appropriate hash bit for the given addr */ 3268 /* The algorithm works like so: 3269 * 1) Take the Destination Address (ie the multicast address), and 3270 * do a CRC on it (little endian), and reverse the bits of the 3271 * result. 3272 * 2) Use the 8 most significant bits as a hash into a 256-entry 3273 * table. The table is controlled through 8 32-bit registers: 3274 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 3275 * gaddr7. This means that the 3 most significant bits in the 3276 * hash index which gaddr register to use, and the 5 other bits 3277 * indicate which bit (assuming an IBM numbering scheme, which 3278 * for PowerPC (tm) is usually the case) in the register holds 3279 * the entry. 3280 */ 3281 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) 3282 { 3283 u32 tempval; 3284 struct gfar_private *priv = netdev_priv(dev); 3285 u32 result = ether_crc(ETH_ALEN, addr); 3286 int width = priv->hash_width; 3287 u8 whichbit = (result >> (32 - width)) & 0x1f; 3288 u8 whichreg = result >> (32 - width + 5); 3289 u32 value = (1 << (31-whichbit)); 3290 3291 tempval = gfar_read(priv->hash_regs[whichreg]); 3292 tempval |= value; 3293 gfar_write(priv->hash_regs[whichreg], tempval); 3294 } 3295 3296 3297 /* There are multiple MAC Address register pairs on some controllers 3298 * This function sets the numth pair to a given address 3299 */ 3300 static void gfar_set_mac_for_addr(struct net_device *dev, int num, 3301 const u8 *addr) 3302 { 3303 struct gfar_private *priv = netdev_priv(dev); 3304 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3305 int idx; 3306 char tmpbuf[ETH_ALEN]; 3307 u32 tempval; 3308 u32 __iomem *macptr = ®s->macstnaddr1; 3309 3310 macptr += num*2; 3311 3312 /* Now copy it into the mac registers backwards, cuz 3313 * little endian is silly 3314 */ 3315 for (idx = 0; idx < ETH_ALEN; idx++) 3316 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx]; 3317 3318 gfar_write(macptr, *((u32 *) (tmpbuf))); 3319 3320 tempval = *((u32 *) (tmpbuf + 4)); 3321 3322 gfar_write(macptr+1, tempval); 3323 } 3324 3325 /* GFAR error interrupt handler */ 3326 static irqreturn_t gfar_error(int irq, void *grp_id) 3327 { 3328 struct gfar_priv_grp *gfargrp = grp_id; 3329 struct gfar __iomem *regs = gfargrp->regs; 3330 struct gfar_private *priv= gfargrp->priv; 3331 struct net_device *dev = priv->ndev; 3332 3333 /* Save ievent for future reference */ 3334 u32 events = gfar_read(®s->ievent); 3335 3336 /* Clear IEVENT */ 3337 gfar_write(®s->ievent, events & IEVENT_ERR_MASK); 3338 3339 /* Magic Packet is not an error. */ 3340 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && 3341 (events & IEVENT_MAG)) 3342 events &= ~IEVENT_MAG; 3343 3344 /* Hmm... */ 3345 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) 3346 netdev_dbg(dev, 3347 "error interrupt (ievent=0x%08x imask=0x%08x)\n", 3348 events, gfar_read(®s->imask)); 3349 3350 /* Update the error counters */ 3351 if (events & IEVENT_TXE) { 3352 dev->stats.tx_errors++; 3353 3354 if (events & IEVENT_LC) 3355 dev->stats.tx_window_errors++; 3356 if (events & IEVENT_CRL) 3357 dev->stats.tx_aborted_errors++; 3358 if (events & IEVENT_XFUN) { 3359 unsigned long flags; 3360 3361 netif_dbg(priv, tx_err, dev, 3362 "TX FIFO underrun, packet dropped\n"); 3363 dev->stats.tx_dropped++; 3364 atomic64_inc(&priv->extra_stats.tx_underrun); 3365 3366 local_irq_save(flags); 3367 lock_tx_qs(priv); 3368 3369 /* Reactivate the Tx Queues */ 3370 gfar_write(®s->tstat, gfargrp->tstat); 3371 3372 unlock_tx_qs(priv); 3373 local_irq_restore(flags); 3374 } 3375 netif_dbg(priv, tx_err, dev, "Transmit Error\n"); 3376 } 3377 if (events & IEVENT_BSY) { 3378 dev->stats.rx_errors++; 3379 atomic64_inc(&priv->extra_stats.rx_bsy); 3380 3381 gfar_receive(irq, grp_id); 3382 3383 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n", 3384 gfar_read(®s->rstat)); 3385 } 3386 if (events & IEVENT_BABR) { 3387 dev->stats.rx_errors++; 3388 atomic64_inc(&priv->extra_stats.rx_babr); 3389 3390 netif_dbg(priv, rx_err, dev, "babbling RX error\n"); 3391 } 3392 if (events & IEVENT_EBERR) { 3393 atomic64_inc(&priv->extra_stats.eberr); 3394 netif_dbg(priv, rx_err, dev, "bus error\n"); 3395 } 3396 if (events & IEVENT_RXC) 3397 netif_dbg(priv, rx_status, dev, "control frame\n"); 3398 3399 if (events & IEVENT_BABT) { 3400 atomic64_inc(&priv->extra_stats.tx_babt); 3401 netif_dbg(priv, tx_err, dev, "babbling TX error\n"); 3402 } 3403 return IRQ_HANDLED; 3404 } 3405 3406 static struct of_device_id gfar_match[] = 3407 { 3408 { 3409 .type = "network", 3410 .compatible = "gianfar", 3411 }, 3412 { 3413 .compatible = "fsl,etsec2", 3414 }, 3415 {}, 3416 }; 3417 MODULE_DEVICE_TABLE(of, gfar_match); 3418 3419 /* Structure for a device driver */ 3420 static struct platform_driver gfar_driver = { 3421 .driver = { 3422 .name = "fsl-gianfar", 3423 .owner = THIS_MODULE, 3424 .pm = GFAR_PM_OPS, 3425 .of_match_table = gfar_match, 3426 }, 3427 .probe = gfar_probe, 3428 .remove = gfar_remove, 3429 }; 3430 3431 module_platform_driver(gfar_driver); 3432