1 /* drivers/net/ethernet/freescale/gianfar.c 2 * 3 * Gianfar Ethernet Driver 4 * This driver is designed for the non-CPM ethernet controllers 5 * on the 85xx and 83xx family of integrated processors 6 * Based on 8260_io/fcc_enet.c 7 * 8 * Author: Andy Fleming 9 * Maintainer: Kumar Gala 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 11 * 12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc. 13 * Copyright 2007 MontaVista Software, Inc. 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 * 20 * Gianfar: AKA Lambda Draconis, "Dragon" 21 * RA 11 31 24.2 22 * Dec +69 19 52 23 * V 3.84 24 * B-V +1.62 25 * 26 * Theory of operation 27 * 28 * The driver is initialized through of_device. Configuration information 29 * is therefore conveyed through an OF-style device tree. 30 * 31 * The Gianfar Ethernet Controller uses a ring of buffer 32 * descriptors. The beginning is indicated by a register 33 * pointing to the physical address of the start of the ring. 34 * The end is determined by a "wrap" bit being set in the 35 * last descriptor of the ring. 36 * 37 * When a packet is received, the RXF bit in the 38 * IEVENT register is set, triggering an interrupt when the 39 * corresponding bit in the IMASK register is also set (if 40 * interrupt coalescing is active, then the interrupt may not 41 * happen immediately, but will wait until either a set number 42 * of frames or amount of time have passed). In NAPI, the 43 * interrupt handler will signal there is work to be done, and 44 * exit. This method will start at the last known empty 45 * descriptor, and process every subsequent descriptor until there 46 * are none left with data (NAPI will stop after a set number of 47 * packets to give time to other tasks, but will eventually 48 * process all the packets). The data arrives inside a 49 * pre-allocated skb, and so after the skb is passed up to the 50 * stack, a new skb must be allocated, and the address field in 51 * the buffer descriptor must be updated to indicate this new 52 * skb. 53 * 54 * When the kernel requests that a packet be transmitted, the 55 * driver starts where it left off last time, and points the 56 * descriptor at the buffer which was passed in. The driver 57 * then informs the DMA engine that there are packets ready to 58 * be transmitted. Once the controller is finished transmitting 59 * the packet, an interrupt may be triggered (under the same 60 * conditions as for reception, but depending on the TXF bit). 61 * The driver then cleans up the buffer. 62 */ 63 64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 65 #define DEBUG 66 67 #include <linux/kernel.h> 68 #include <linux/string.h> 69 #include <linux/errno.h> 70 #include <linux/unistd.h> 71 #include <linux/slab.h> 72 #include <linux/interrupt.h> 73 #include <linux/delay.h> 74 #include <linux/netdevice.h> 75 #include <linux/etherdevice.h> 76 #include <linux/skbuff.h> 77 #include <linux/if_vlan.h> 78 #include <linux/spinlock.h> 79 #include <linux/mm.h> 80 #include <linux/of_address.h> 81 #include <linux/of_irq.h> 82 #include <linux/of_mdio.h> 83 #include <linux/of_platform.h> 84 #include <linux/ip.h> 85 #include <linux/tcp.h> 86 #include <linux/udp.h> 87 #include <linux/in.h> 88 #include <linux/net_tstamp.h> 89 90 #include <asm/io.h> 91 #ifdef CONFIG_PPC 92 #include <asm/reg.h> 93 #include <asm/mpc85xx.h> 94 #endif 95 #include <asm/irq.h> 96 #include <linux/uaccess.h> 97 #include <linux/module.h> 98 #include <linux/dma-mapping.h> 99 #include <linux/crc32.h> 100 #include <linux/mii.h> 101 #include <linux/phy.h> 102 #include <linux/phy_fixed.h> 103 #include <linux/of.h> 104 #include <linux/of_net.h> 105 #include <linux/of_address.h> 106 #include <linux/of_irq.h> 107 108 #include "gianfar.h" 109 110 #define TX_TIMEOUT (5*HZ) 111 112 const char gfar_driver_version[] = "2.0"; 113 114 static int gfar_enet_open(struct net_device *dev); 115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); 116 static void gfar_reset_task(struct work_struct *work); 117 static void gfar_timeout(struct net_device *dev); 118 static int gfar_close(struct net_device *dev); 119 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue, 120 int alloc_cnt); 121 static int gfar_set_mac_address(struct net_device *dev); 122 static int gfar_change_mtu(struct net_device *dev, int new_mtu); 123 static irqreturn_t gfar_error(int irq, void *dev_id); 124 static irqreturn_t gfar_transmit(int irq, void *dev_id); 125 static irqreturn_t gfar_interrupt(int irq, void *dev_id); 126 static void adjust_link(struct net_device *dev); 127 static noinline void gfar_update_link_state(struct gfar_private *priv); 128 static int init_phy(struct net_device *dev); 129 static int gfar_probe(struct platform_device *ofdev); 130 static int gfar_remove(struct platform_device *ofdev); 131 static void free_skb_resources(struct gfar_private *priv); 132 static void gfar_set_multi(struct net_device *dev); 133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); 134 static void gfar_configure_serdes(struct net_device *dev); 135 static int gfar_poll_rx(struct napi_struct *napi, int budget); 136 static int gfar_poll_tx(struct napi_struct *napi, int budget); 137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget); 138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget); 139 #ifdef CONFIG_NET_POLL_CONTROLLER 140 static void gfar_netpoll(struct net_device *dev); 141 #endif 142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); 143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); 144 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb); 145 static void gfar_halt_nodisable(struct gfar_private *priv); 146 static void gfar_clear_exact_match(struct net_device *dev); 147 static void gfar_set_mac_for_addr(struct net_device *dev, int num, 148 const u8 *addr); 149 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 150 151 MODULE_AUTHOR("Freescale Semiconductor, Inc"); 152 MODULE_DESCRIPTION("Gianfar Ethernet Driver"); 153 MODULE_LICENSE("GPL"); 154 155 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, 156 dma_addr_t buf) 157 { 158 u32 lstatus; 159 160 bdp->bufPtr = cpu_to_be32(buf); 161 162 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); 163 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) 164 lstatus |= BD_LFLAG(RXBD_WRAP); 165 166 gfar_wmb(); 167 168 bdp->lstatus = cpu_to_be32(lstatus); 169 } 170 171 static void gfar_init_bds(struct net_device *ndev) 172 { 173 struct gfar_private *priv = netdev_priv(ndev); 174 struct gfar __iomem *regs = priv->gfargrp[0].regs; 175 struct gfar_priv_tx_q *tx_queue = NULL; 176 struct gfar_priv_rx_q *rx_queue = NULL; 177 struct txbd8 *txbdp; 178 u32 __iomem *rfbptr; 179 int i, j; 180 181 for (i = 0; i < priv->num_tx_queues; i++) { 182 tx_queue = priv->tx_queue[i]; 183 /* Initialize some variables in our dev structure */ 184 tx_queue->num_txbdfree = tx_queue->tx_ring_size; 185 tx_queue->dirty_tx = tx_queue->tx_bd_base; 186 tx_queue->cur_tx = tx_queue->tx_bd_base; 187 tx_queue->skb_curtx = 0; 188 tx_queue->skb_dirtytx = 0; 189 190 /* Initialize Transmit Descriptor Ring */ 191 txbdp = tx_queue->tx_bd_base; 192 for (j = 0; j < tx_queue->tx_ring_size; j++) { 193 txbdp->lstatus = 0; 194 txbdp->bufPtr = 0; 195 txbdp++; 196 } 197 198 /* Set the last descriptor in the ring to indicate wrap */ 199 txbdp--; 200 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) | 201 TXBD_WRAP); 202 } 203 204 rfbptr = ®s->rfbptr0; 205 for (i = 0; i < priv->num_rx_queues; i++) { 206 rx_queue = priv->rx_queue[i]; 207 208 rx_queue->next_to_clean = 0; 209 rx_queue->next_to_use = 0; 210 rx_queue->next_to_alloc = 0; 211 212 /* make sure next_to_clean != next_to_use after this 213 * by leaving at least 1 unused descriptor 214 */ 215 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue)); 216 217 rx_queue->rfbptr = rfbptr; 218 rfbptr += 2; 219 } 220 } 221 222 static int gfar_alloc_skb_resources(struct net_device *ndev) 223 { 224 void *vaddr; 225 dma_addr_t addr; 226 int i, j; 227 struct gfar_private *priv = netdev_priv(ndev); 228 struct device *dev = priv->dev; 229 struct gfar_priv_tx_q *tx_queue = NULL; 230 struct gfar_priv_rx_q *rx_queue = NULL; 231 232 priv->total_tx_ring_size = 0; 233 for (i = 0; i < priv->num_tx_queues; i++) 234 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; 235 236 priv->total_rx_ring_size = 0; 237 for (i = 0; i < priv->num_rx_queues; i++) 238 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; 239 240 /* Allocate memory for the buffer descriptors */ 241 vaddr = dma_alloc_coherent(dev, 242 (priv->total_tx_ring_size * 243 sizeof(struct txbd8)) + 244 (priv->total_rx_ring_size * 245 sizeof(struct rxbd8)), 246 &addr, GFP_KERNEL); 247 if (!vaddr) 248 return -ENOMEM; 249 250 for (i = 0; i < priv->num_tx_queues; i++) { 251 tx_queue = priv->tx_queue[i]; 252 tx_queue->tx_bd_base = vaddr; 253 tx_queue->tx_bd_dma_base = addr; 254 tx_queue->dev = ndev; 255 /* enet DMA only understands physical addresses */ 256 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; 257 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; 258 } 259 260 /* Start the rx descriptor ring where the tx ring leaves off */ 261 for (i = 0; i < priv->num_rx_queues; i++) { 262 rx_queue = priv->rx_queue[i]; 263 rx_queue->rx_bd_base = vaddr; 264 rx_queue->rx_bd_dma_base = addr; 265 rx_queue->ndev = ndev; 266 rx_queue->dev = dev; 267 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; 268 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; 269 } 270 271 /* Setup the skbuff rings */ 272 for (i = 0; i < priv->num_tx_queues; i++) { 273 tx_queue = priv->tx_queue[i]; 274 tx_queue->tx_skbuff = 275 kmalloc_array(tx_queue->tx_ring_size, 276 sizeof(*tx_queue->tx_skbuff), 277 GFP_KERNEL); 278 if (!tx_queue->tx_skbuff) 279 goto cleanup; 280 281 for (j = 0; j < tx_queue->tx_ring_size; j++) 282 tx_queue->tx_skbuff[j] = NULL; 283 } 284 285 for (i = 0; i < priv->num_rx_queues; i++) { 286 rx_queue = priv->rx_queue[i]; 287 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size, 288 sizeof(*rx_queue->rx_buff), 289 GFP_KERNEL); 290 if (!rx_queue->rx_buff) 291 goto cleanup; 292 } 293 294 gfar_init_bds(ndev); 295 296 return 0; 297 298 cleanup: 299 free_skb_resources(priv); 300 return -ENOMEM; 301 } 302 303 static void gfar_init_tx_rx_base(struct gfar_private *priv) 304 { 305 struct gfar __iomem *regs = priv->gfargrp[0].regs; 306 u32 __iomem *baddr; 307 int i; 308 309 baddr = ®s->tbase0; 310 for (i = 0; i < priv->num_tx_queues; i++) { 311 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); 312 baddr += 2; 313 } 314 315 baddr = ®s->rbase0; 316 for (i = 0; i < priv->num_rx_queues; i++) { 317 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); 318 baddr += 2; 319 } 320 } 321 322 static void gfar_init_rqprm(struct gfar_private *priv) 323 { 324 struct gfar __iomem *regs = priv->gfargrp[0].regs; 325 u32 __iomem *baddr; 326 int i; 327 328 baddr = ®s->rqprm0; 329 for (i = 0; i < priv->num_rx_queues; i++) { 330 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size | 331 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT)); 332 baddr++; 333 } 334 } 335 336 static void gfar_rx_offload_en(struct gfar_private *priv) 337 { 338 /* set this when rx hw offload (TOE) functions are being used */ 339 priv->uses_rxfcb = 0; 340 341 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) 342 priv->uses_rxfcb = 1; 343 344 if (priv->hwts_rx_en || priv->rx_filer_enable) 345 priv->uses_rxfcb = 1; 346 } 347 348 static void gfar_mac_rx_config(struct gfar_private *priv) 349 { 350 struct gfar __iomem *regs = priv->gfargrp[0].regs; 351 u32 rctrl = 0; 352 353 if (priv->rx_filer_enable) { 354 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT; 355 /* Program the RIR0 reg with the required distribution */ 356 if (priv->poll_mode == GFAR_SQ_POLLING) 357 gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0); 358 else /* GFAR_MQ_POLLING */ 359 gfar_write(®s->rir0, DEFAULT_8RXQ_RIR0); 360 } 361 362 /* Restore PROMISC mode */ 363 if (priv->ndev->flags & IFF_PROMISC) 364 rctrl |= RCTRL_PROM; 365 366 if (priv->ndev->features & NETIF_F_RXCSUM) 367 rctrl |= RCTRL_CHECKSUMMING; 368 369 if (priv->extended_hash) 370 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN; 371 372 if (priv->padding) { 373 rctrl &= ~RCTRL_PAL_MASK; 374 rctrl |= RCTRL_PADDING(priv->padding); 375 } 376 377 /* Enable HW time stamping if requested from user space */ 378 if (priv->hwts_rx_en) 379 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; 380 381 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) 382 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; 383 384 /* Clear the LFC bit */ 385 gfar_write(®s->rctrl, rctrl); 386 /* Init flow control threshold values */ 387 gfar_init_rqprm(priv); 388 gfar_write(®s->ptv, DEFAULT_LFC_PTVVAL); 389 rctrl |= RCTRL_LFC; 390 391 /* Init rctrl based on our settings */ 392 gfar_write(®s->rctrl, rctrl); 393 } 394 395 static void gfar_mac_tx_config(struct gfar_private *priv) 396 { 397 struct gfar __iomem *regs = priv->gfargrp[0].regs; 398 u32 tctrl = 0; 399 400 if (priv->ndev->features & NETIF_F_IP_CSUM) 401 tctrl |= TCTRL_INIT_CSUM; 402 403 if (priv->prio_sched_en) 404 tctrl |= TCTRL_TXSCHED_PRIO; 405 else { 406 tctrl |= TCTRL_TXSCHED_WRRS; 407 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT); 408 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT); 409 } 410 411 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX) 412 tctrl |= TCTRL_VLINS; 413 414 gfar_write(®s->tctrl, tctrl); 415 } 416 417 static void gfar_configure_coalescing(struct gfar_private *priv, 418 unsigned long tx_mask, unsigned long rx_mask) 419 { 420 struct gfar __iomem *regs = priv->gfargrp[0].regs; 421 u32 __iomem *baddr; 422 423 if (priv->mode == MQ_MG_MODE) { 424 int i = 0; 425 426 baddr = ®s->txic0; 427 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { 428 gfar_write(baddr + i, 0); 429 if (likely(priv->tx_queue[i]->txcoalescing)) 430 gfar_write(baddr + i, priv->tx_queue[i]->txic); 431 } 432 433 baddr = ®s->rxic0; 434 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { 435 gfar_write(baddr + i, 0); 436 if (likely(priv->rx_queue[i]->rxcoalescing)) 437 gfar_write(baddr + i, priv->rx_queue[i]->rxic); 438 } 439 } else { 440 /* Backward compatible case -- even if we enable 441 * multiple queues, there's only single reg to program 442 */ 443 gfar_write(®s->txic, 0); 444 if (likely(priv->tx_queue[0]->txcoalescing)) 445 gfar_write(®s->txic, priv->tx_queue[0]->txic); 446 447 gfar_write(®s->rxic, 0); 448 if (unlikely(priv->rx_queue[0]->rxcoalescing)) 449 gfar_write(®s->rxic, priv->rx_queue[0]->rxic); 450 } 451 } 452 453 void gfar_configure_coalescing_all(struct gfar_private *priv) 454 { 455 gfar_configure_coalescing(priv, 0xFF, 0xFF); 456 } 457 458 static struct net_device_stats *gfar_get_stats(struct net_device *dev) 459 { 460 struct gfar_private *priv = netdev_priv(dev); 461 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; 462 unsigned long tx_packets = 0, tx_bytes = 0; 463 int i; 464 465 for (i = 0; i < priv->num_rx_queues; i++) { 466 rx_packets += priv->rx_queue[i]->stats.rx_packets; 467 rx_bytes += priv->rx_queue[i]->stats.rx_bytes; 468 rx_dropped += priv->rx_queue[i]->stats.rx_dropped; 469 } 470 471 dev->stats.rx_packets = rx_packets; 472 dev->stats.rx_bytes = rx_bytes; 473 dev->stats.rx_dropped = rx_dropped; 474 475 for (i = 0; i < priv->num_tx_queues; i++) { 476 tx_bytes += priv->tx_queue[i]->stats.tx_bytes; 477 tx_packets += priv->tx_queue[i]->stats.tx_packets; 478 } 479 480 dev->stats.tx_bytes = tx_bytes; 481 dev->stats.tx_packets = tx_packets; 482 483 return &dev->stats; 484 } 485 486 static int gfar_set_mac_addr(struct net_device *dev, void *p) 487 { 488 eth_mac_addr(dev, p); 489 490 gfar_set_mac_for_addr(dev, 0, dev->dev_addr); 491 492 return 0; 493 } 494 495 static const struct net_device_ops gfar_netdev_ops = { 496 .ndo_open = gfar_enet_open, 497 .ndo_start_xmit = gfar_start_xmit, 498 .ndo_stop = gfar_close, 499 .ndo_change_mtu = gfar_change_mtu, 500 .ndo_set_features = gfar_set_features, 501 .ndo_set_rx_mode = gfar_set_multi, 502 .ndo_tx_timeout = gfar_timeout, 503 .ndo_do_ioctl = gfar_ioctl, 504 .ndo_get_stats = gfar_get_stats, 505 .ndo_set_mac_address = gfar_set_mac_addr, 506 .ndo_validate_addr = eth_validate_addr, 507 #ifdef CONFIG_NET_POLL_CONTROLLER 508 .ndo_poll_controller = gfar_netpoll, 509 #endif 510 }; 511 512 static void gfar_ints_disable(struct gfar_private *priv) 513 { 514 int i; 515 for (i = 0; i < priv->num_grps; i++) { 516 struct gfar __iomem *regs = priv->gfargrp[i].regs; 517 /* Clear IEVENT */ 518 gfar_write(®s->ievent, IEVENT_INIT_CLEAR); 519 520 /* Initialize IMASK */ 521 gfar_write(®s->imask, IMASK_INIT_CLEAR); 522 } 523 } 524 525 static void gfar_ints_enable(struct gfar_private *priv) 526 { 527 int i; 528 for (i = 0; i < priv->num_grps; i++) { 529 struct gfar __iomem *regs = priv->gfargrp[i].regs; 530 /* Unmask the interrupts we look for */ 531 gfar_write(®s->imask, IMASK_DEFAULT); 532 } 533 } 534 535 static int gfar_alloc_tx_queues(struct gfar_private *priv) 536 { 537 int i; 538 539 for (i = 0; i < priv->num_tx_queues; i++) { 540 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), 541 GFP_KERNEL); 542 if (!priv->tx_queue[i]) 543 return -ENOMEM; 544 545 priv->tx_queue[i]->tx_skbuff = NULL; 546 priv->tx_queue[i]->qindex = i; 547 priv->tx_queue[i]->dev = priv->ndev; 548 spin_lock_init(&(priv->tx_queue[i]->txlock)); 549 } 550 return 0; 551 } 552 553 static int gfar_alloc_rx_queues(struct gfar_private *priv) 554 { 555 int i; 556 557 for (i = 0; i < priv->num_rx_queues; i++) { 558 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), 559 GFP_KERNEL); 560 if (!priv->rx_queue[i]) 561 return -ENOMEM; 562 563 priv->rx_queue[i]->qindex = i; 564 priv->rx_queue[i]->ndev = priv->ndev; 565 } 566 return 0; 567 } 568 569 static void gfar_free_tx_queues(struct gfar_private *priv) 570 { 571 int i; 572 573 for (i = 0; i < priv->num_tx_queues; i++) 574 kfree(priv->tx_queue[i]); 575 } 576 577 static void gfar_free_rx_queues(struct gfar_private *priv) 578 { 579 int i; 580 581 for (i = 0; i < priv->num_rx_queues; i++) 582 kfree(priv->rx_queue[i]); 583 } 584 585 static void unmap_group_regs(struct gfar_private *priv) 586 { 587 int i; 588 589 for (i = 0; i < MAXGROUPS; i++) 590 if (priv->gfargrp[i].regs) 591 iounmap(priv->gfargrp[i].regs); 592 } 593 594 static void free_gfar_dev(struct gfar_private *priv) 595 { 596 int i, j; 597 598 for (i = 0; i < priv->num_grps; i++) 599 for (j = 0; j < GFAR_NUM_IRQS; j++) { 600 kfree(priv->gfargrp[i].irqinfo[j]); 601 priv->gfargrp[i].irqinfo[j] = NULL; 602 } 603 604 free_netdev(priv->ndev); 605 } 606 607 static void disable_napi(struct gfar_private *priv) 608 { 609 int i; 610 611 for (i = 0; i < priv->num_grps; i++) { 612 napi_disable(&priv->gfargrp[i].napi_rx); 613 napi_disable(&priv->gfargrp[i].napi_tx); 614 } 615 } 616 617 static void enable_napi(struct gfar_private *priv) 618 { 619 int i; 620 621 for (i = 0; i < priv->num_grps; i++) { 622 napi_enable(&priv->gfargrp[i].napi_rx); 623 napi_enable(&priv->gfargrp[i].napi_tx); 624 } 625 } 626 627 static int gfar_parse_group(struct device_node *np, 628 struct gfar_private *priv, const char *model) 629 { 630 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps]; 631 int i; 632 633 for (i = 0; i < GFAR_NUM_IRQS; i++) { 634 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo), 635 GFP_KERNEL); 636 if (!grp->irqinfo[i]) 637 return -ENOMEM; 638 } 639 640 grp->regs = of_iomap(np, 0); 641 if (!grp->regs) 642 return -ENOMEM; 643 644 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0); 645 646 /* If we aren't the FEC we have multiple interrupts */ 647 if (model && strcasecmp(model, "FEC")) { 648 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1); 649 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2); 650 if (!gfar_irq(grp, TX)->irq || 651 !gfar_irq(grp, RX)->irq || 652 !gfar_irq(grp, ER)->irq) 653 return -EINVAL; 654 } 655 656 grp->priv = priv; 657 spin_lock_init(&grp->grplock); 658 if (priv->mode == MQ_MG_MODE) { 659 u32 rxq_mask, txq_mask; 660 int ret; 661 662 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps); 663 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps); 664 665 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask); 666 if (!ret) { 667 grp->rx_bit_map = rxq_mask ? 668 rxq_mask : (DEFAULT_MAPPING >> priv->num_grps); 669 } 670 671 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask); 672 if (!ret) { 673 grp->tx_bit_map = txq_mask ? 674 txq_mask : (DEFAULT_MAPPING >> priv->num_grps); 675 } 676 677 if (priv->poll_mode == GFAR_SQ_POLLING) { 678 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */ 679 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps); 680 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps); 681 } 682 } else { 683 grp->rx_bit_map = 0xFF; 684 grp->tx_bit_map = 0xFF; 685 } 686 687 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses 688 * right to left, so we need to revert the 8 bits to get the q index 689 */ 690 grp->rx_bit_map = bitrev8(grp->rx_bit_map); 691 grp->tx_bit_map = bitrev8(grp->tx_bit_map); 692 693 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, 694 * also assign queues to groups 695 */ 696 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) { 697 if (!grp->rx_queue) 698 grp->rx_queue = priv->rx_queue[i]; 699 grp->num_rx_queues++; 700 grp->rstat |= (RSTAT_CLEAR_RHALT >> i); 701 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i); 702 priv->rx_queue[i]->grp = grp; 703 } 704 705 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) { 706 if (!grp->tx_queue) 707 grp->tx_queue = priv->tx_queue[i]; 708 grp->num_tx_queues++; 709 grp->tstat |= (TSTAT_CLEAR_THALT >> i); 710 priv->tqueue |= (TQUEUE_EN0 >> i); 711 priv->tx_queue[i]->grp = grp; 712 } 713 714 priv->num_grps++; 715 716 return 0; 717 } 718 719 static int gfar_of_group_count(struct device_node *np) 720 { 721 struct device_node *child; 722 int num = 0; 723 724 for_each_available_child_of_node(np, child) 725 if (!of_node_cmp(child->name, "queue-group")) 726 num++; 727 728 return num; 729 } 730 731 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) 732 { 733 const char *model; 734 const char *ctype; 735 const void *mac_addr; 736 int err = 0, i; 737 struct net_device *dev = NULL; 738 struct gfar_private *priv = NULL; 739 struct device_node *np = ofdev->dev.of_node; 740 struct device_node *child = NULL; 741 u32 stash_len = 0; 742 u32 stash_idx = 0; 743 unsigned int num_tx_qs, num_rx_qs; 744 unsigned short mode, poll_mode; 745 746 if (!np) 747 return -ENODEV; 748 749 if (of_device_is_compatible(np, "fsl,etsec2")) { 750 mode = MQ_MG_MODE; 751 poll_mode = GFAR_SQ_POLLING; 752 } else { 753 mode = SQ_SG_MODE; 754 poll_mode = GFAR_SQ_POLLING; 755 } 756 757 if (mode == SQ_SG_MODE) { 758 num_tx_qs = 1; 759 num_rx_qs = 1; 760 } else { /* MQ_MG_MODE */ 761 /* get the actual number of supported groups */ 762 unsigned int num_grps = gfar_of_group_count(np); 763 764 if (num_grps == 0 || num_grps > MAXGROUPS) { 765 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n", 766 num_grps); 767 pr_err("Cannot do alloc_etherdev, aborting\n"); 768 return -EINVAL; 769 } 770 771 if (poll_mode == GFAR_SQ_POLLING) { 772 num_tx_qs = num_grps; /* one txq per int group */ 773 num_rx_qs = num_grps; /* one rxq per int group */ 774 } else { /* GFAR_MQ_POLLING */ 775 u32 tx_queues, rx_queues; 776 int ret; 777 778 /* parse the num of HW tx and rx queues */ 779 ret = of_property_read_u32(np, "fsl,num_tx_queues", 780 &tx_queues); 781 num_tx_qs = ret ? 1 : tx_queues; 782 783 ret = of_property_read_u32(np, "fsl,num_rx_queues", 784 &rx_queues); 785 num_rx_qs = ret ? 1 : rx_queues; 786 } 787 } 788 789 if (num_tx_qs > MAX_TX_QS) { 790 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", 791 num_tx_qs, MAX_TX_QS); 792 pr_err("Cannot do alloc_etherdev, aborting\n"); 793 return -EINVAL; 794 } 795 796 if (num_rx_qs > MAX_RX_QS) { 797 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", 798 num_rx_qs, MAX_RX_QS); 799 pr_err("Cannot do alloc_etherdev, aborting\n"); 800 return -EINVAL; 801 } 802 803 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); 804 dev = *pdev; 805 if (NULL == dev) 806 return -ENOMEM; 807 808 priv = netdev_priv(dev); 809 priv->ndev = dev; 810 811 priv->mode = mode; 812 priv->poll_mode = poll_mode; 813 814 priv->num_tx_queues = num_tx_qs; 815 netif_set_real_num_rx_queues(dev, num_rx_qs); 816 priv->num_rx_queues = num_rx_qs; 817 818 err = gfar_alloc_tx_queues(priv); 819 if (err) 820 goto tx_alloc_failed; 821 822 err = gfar_alloc_rx_queues(priv); 823 if (err) 824 goto rx_alloc_failed; 825 826 err = of_property_read_string(np, "model", &model); 827 if (err) { 828 pr_err("Device model property missing, aborting\n"); 829 goto rx_alloc_failed; 830 } 831 832 /* Init Rx queue filer rule set linked list */ 833 INIT_LIST_HEAD(&priv->rx_list.list); 834 priv->rx_list.count = 0; 835 mutex_init(&priv->rx_queue_access); 836 837 for (i = 0; i < MAXGROUPS; i++) 838 priv->gfargrp[i].regs = NULL; 839 840 /* Parse and initialize group specific information */ 841 if (priv->mode == MQ_MG_MODE) { 842 for_each_available_child_of_node(np, child) { 843 if (of_node_cmp(child->name, "queue-group")) 844 continue; 845 846 err = gfar_parse_group(child, priv, model); 847 if (err) 848 goto err_grp_init; 849 } 850 } else { /* SQ_SG_MODE */ 851 err = gfar_parse_group(np, priv, model); 852 if (err) 853 goto err_grp_init; 854 } 855 856 if (of_property_read_bool(np, "bd-stash")) { 857 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; 858 priv->bd_stash_en = 1; 859 } 860 861 err = of_property_read_u32(np, "rx-stash-len", &stash_len); 862 863 if (err == 0) 864 priv->rx_stash_size = stash_len; 865 866 err = of_property_read_u32(np, "rx-stash-idx", &stash_idx); 867 868 if (err == 0) 869 priv->rx_stash_index = stash_idx; 870 871 if (stash_len || stash_idx) 872 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; 873 874 mac_addr = of_get_mac_address(np); 875 876 if (mac_addr) 877 memcpy(dev->dev_addr, mac_addr, ETH_ALEN); 878 879 if (model && !strcasecmp(model, "TSEC")) 880 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT | 881 FSL_GIANFAR_DEV_HAS_COALESCE | 882 FSL_GIANFAR_DEV_HAS_RMON | 883 FSL_GIANFAR_DEV_HAS_MULTI_INTR; 884 885 if (model && !strcasecmp(model, "eTSEC")) 886 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT | 887 FSL_GIANFAR_DEV_HAS_COALESCE | 888 FSL_GIANFAR_DEV_HAS_RMON | 889 FSL_GIANFAR_DEV_HAS_MULTI_INTR | 890 FSL_GIANFAR_DEV_HAS_CSUM | 891 FSL_GIANFAR_DEV_HAS_VLAN | 892 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | 893 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | 894 FSL_GIANFAR_DEV_HAS_TIMER | 895 FSL_GIANFAR_DEV_HAS_RX_FILER; 896 897 err = of_property_read_string(np, "phy-connection-type", &ctype); 898 899 /* We only care about rgmii-id. The rest are autodetected */ 900 if (err == 0 && !strcmp(ctype, "rgmii-id")) 901 priv->interface = PHY_INTERFACE_MODE_RGMII_ID; 902 else 903 priv->interface = PHY_INTERFACE_MODE_MII; 904 905 if (of_find_property(np, "fsl,magic-packet", NULL)) 906 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; 907 908 if (of_get_property(np, "fsl,wake-on-filer", NULL)) 909 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER; 910 911 priv->phy_node = of_parse_phandle(np, "phy-handle", 0); 912 913 /* In the case of a fixed PHY, the DT node associated 914 * to the PHY is the Ethernet MAC DT node. 915 */ 916 if (!priv->phy_node && of_phy_is_fixed_link(np)) { 917 err = of_phy_register_fixed_link(np); 918 if (err) 919 goto err_grp_init; 920 921 priv->phy_node = of_node_get(np); 922 } 923 924 /* Find the TBI PHY. If it's not there, we don't support SGMII */ 925 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); 926 927 return 0; 928 929 err_grp_init: 930 unmap_group_regs(priv); 931 rx_alloc_failed: 932 gfar_free_rx_queues(priv); 933 tx_alloc_failed: 934 gfar_free_tx_queues(priv); 935 free_gfar_dev(priv); 936 return err; 937 } 938 939 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 940 { 941 struct hwtstamp_config config; 942 struct gfar_private *priv = netdev_priv(netdev); 943 944 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 945 return -EFAULT; 946 947 /* reserved for future extensions */ 948 if (config.flags) 949 return -EINVAL; 950 951 switch (config.tx_type) { 952 case HWTSTAMP_TX_OFF: 953 priv->hwts_tx_en = 0; 954 break; 955 case HWTSTAMP_TX_ON: 956 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) 957 return -ERANGE; 958 priv->hwts_tx_en = 1; 959 break; 960 default: 961 return -ERANGE; 962 } 963 964 switch (config.rx_filter) { 965 case HWTSTAMP_FILTER_NONE: 966 if (priv->hwts_rx_en) { 967 priv->hwts_rx_en = 0; 968 reset_gfar(netdev); 969 } 970 break; 971 default: 972 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) 973 return -ERANGE; 974 if (!priv->hwts_rx_en) { 975 priv->hwts_rx_en = 1; 976 reset_gfar(netdev); 977 } 978 config.rx_filter = HWTSTAMP_FILTER_ALL; 979 break; 980 } 981 982 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 983 -EFAULT : 0; 984 } 985 986 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 987 { 988 struct hwtstamp_config config; 989 struct gfar_private *priv = netdev_priv(netdev); 990 991 config.flags = 0; 992 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 993 config.rx_filter = (priv->hwts_rx_en ? 994 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE); 995 996 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 997 -EFAULT : 0; 998 } 999 1000 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1001 { 1002 struct phy_device *phydev = dev->phydev; 1003 1004 if (!netif_running(dev)) 1005 return -EINVAL; 1006 1007 if (cmd == SIOCSHWTSTAMP) 1008 return gfar_hwtstamp_set(dev, rq); 1009 if (cmd == SIOCGHWTSTAMP) 1010 return gfar_hwtstamp_get(dev, rq); 1011 1012 if (!phydev) 1013 return -ENODEV; 1014 1015 return phy_mii_ioctl(phydev, rq, cmd); 1016 } 1017 1018 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, 1019 u32 class) 1020 { 1021 u32 rqfpr = FPR_FILER_MASK; 1022 u32 rqfcr = 0x0; 1023 1024 rqfar--; 1025 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; 1026 priv->ftp_rqfpr[rqfar] = rqfpr; 1027 priv->ftp_rqfcr[rqfar] = rqfcr; 1028 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1029 1030 rqfar--; 1031 rqfcr = RQFCR_CMP_NOMATCH; 1032 priv->ftp_rqfpr[rqfar] = rqfpr; 1033 priv->ftp_rqfcr[rqfar] = rqfcr; 1034 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1035 1036 rqfar--; 1037 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; 1038 rqfpr = class; 1039 priv->ftp_rqfcr[rqfar] = rqfcr; 1040 priv->ftp_rqfpr[rqfar] = rqfpr; 1041 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1042 1043 rqfar--; 1044 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; 1045 rqfpr = class; 1046 priv->ftp_rqfcr[rqfar] = rqfcr; 1047 priv->ftp_rqfpr[rqfar] = rqfpr; 1048 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1049 1050 return rqfar; 1051 } 1052 1053 static void gfar_init_filer_table(struct gfar_private *priv) 1054 { 1055 int i = 0x0; 1056 u32 rqfar = MAX_FILER_IDX; 1057 u32 rqfcr = 0x0; 1058 u32 rqfpr = FPR_FILER_MASK; 1059 1060 /* Default rule */ 1061 rqfcr = RQFCR_CMP_MATCH; 1062 priv->ftp_rqfcr[rqfar] = rqfcr; 1063 priv->ftp_rqfpr[rqfar] = rqfpr; 1064 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1065 1066 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); 1067 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); 1068 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); 1069 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); 1070 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); 1071 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); 1072 1073 /* cur_filer_idx indicated the first non-masked rule */ 1074 priv->cur_filer_idx = rqfar; 1075 1076 /* Rest are masked rules */ 1077 rqfcr = RQFCR_CMP_NOMATCH; 1078 for (i = 0; i < rqfar; i++) { 1079 priv->ftp_rqfcr[i] = rqfcr; 1080 priv->ftp_rqfpr[i] = rqfpr; 1081 gfar_write_filer(priv, i, rqfcr, rqfpr); 1082 } 1083 } 1084 1085 #ifdef CONFIG_PPC 1086 static void __gfar_detect_errata_83xx(struct gfar_private *priv) 1087 { 1088 unsigned int pvr = mfspr(SPRN_PVR); 1089 unsigned int svr = mfspr(SPRN_SVR); 1090 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ 1091 unsigned int rev = svr & 0xffff; 1092 1093 /* MPC8313 Rev 2.0 and higher; All MPC837x */ 1094 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || 1095 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) 1096 priv->errata |= GFAR_ERRATA_74; 1097 1098 /* MPC8313 and MPC837x all rev */ 1099 if ((pvr == 0x80850010 && mod == 0x80b0) || 1100 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) 1101 priv->errata |= GFAR_ERRATA_76; 1102 1103 /* MPC8313 Rev < 2.0 */ 1104 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) 1105 priv->errata |= GFAR_ERRATA_12; 1106 } 1107 1108 static void __gfar_detect_errata_85xx(struct gfar_private *priv) 1109 { 1110 unsigned int svr = mfspr(SPRN_SVR); 1111 1112 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20)) 1113 priv->errata |= GFAR_ERRATA_12; 1114 /* P2020/P1010 Rev 1; MPC8548 Rev 2 */ 1115 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) || 1116 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) || 1117 ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31))) 1118 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */ 1119 } 1120 #endif 1121 1122 static void gfar_detect_errata(struct gfar_private *priv) 1123 { 1124 struct device *dev = &priv->ofdev->dev; 1125 1126 /* no plans to fix */ 1127 priv->errata |= GFAR_ERRATA_A002; 1128 1129 #ifdef CONFIG_PPC 1130 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)) 1131 __gfar_detect_errata_85xx(priv); 1132 else /* non-mpc85xx parts, i.e. e300 core based */ 1133 __gfar_detect_errata_83xx(priv); 1134 #endif 1135 1136 if (priv->errata) 1137 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", 1138 priv->errata); 1139 } 1140 1141 void gfar_mac_reset(struct gfar_private *priv) 1142 { 1143 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1144 u32 tempval; 1145 1146 /* Reset MAC layer */ 1147 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); 1148 1149 /* We need to delay at least 3 TX clocks */ 1150 udelay(3); 1151 1152 /* the soft reset bit is not self-resetting, so we need to 1153 * clear it before resuming normal operation 1154 */ 1155 gfar_write(®s->maccfg1, 0); 1156 1157 udelay(3); 1158 1159 gfar_rx_offload_en(priv); 1160 1161 /* Initialize the max receive frame/buffer lengths */ 1162 gfar_write(®s->maxfrm, GFAR_JUMBO_FRAME_SIZE); 1163 gfar_write(®s->mrblr, GFAR_RXB_SIZE); 1164 1165 /* Initialize the Minimum Frame Length Register */ 1166 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); 1167 1168 /* Initialize MACCFG2. */ 1169 tempval = MACCFG2_INIT_SETTINGS; 1170 1171 /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1 1172 * are marked as truncated. Avoid this by MACCFG2[Huge Frame]=1, 1173 * and by checking RxBD[LG] and discarding larger than MAXFRM. 1174 */ 1175 if (gfar_has_errata(priv, GFAR_ERRATA_74)) 1176 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; 1177 1178 gfar_write(®s->maccfg2, tempval); 1179 1180 /* Clear mac addr hash registers */ 1181 gfar_write(®s->igaddr0, 0); 1182 gfar_write(®s->igaddr1, 0); 1183 gfar_write(®s->igaddr2, 0); 1184 gfar_write(®s->igaddr3, 0); 1185 gfar_write(®s->igaddr4, 0); 1186 gfar_write(®s->igaddr5, 0); 1187 gfar_write(®s->igaddr6, 0); 1188 gfar_write(®s->igaddr7, 0); 1189 1190 gfar_write(®s->gaddr0, 0); 1191 gfar_write(®s->gaddr1, 0); 1192 gfar_write(®s->gaddr2, 0); 1193 gfar_write(®s->gaddr3, 0); 1194 gfar_write(®s->gaddr4, 0); 1195 gfar_write(®s->gaddr5, 0); 1196 gfar_write(®s->gaddr6, 0); 1197 gfar_write(®s->gaddr7, 0); 1198 1199 if (priv->extended_hash) 1200 gfar_clear_exact_match(priv->ndev); 1201 1202 gfar_mac_rx_config(priv); 1203 1204 gfar_mac_tx_config(priv); 1205 1206 gfar_set_mac_address(priv->ndev); 1207 1208 gfar_set_multi(priv->ndev); 1209 1210 /* clear ievent and imask before configuring coalescing */ 1211 gfar_ints_disable(priv); 1212 1213 /* Configure the coalescing support */ 1214 gfar_configure_coalescing_all(priv); 1215 } 1216 1217 static void gfar_hw_init(struct gfar_private *priv) 1218 { 1219 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1220 u32 attrs; 1221 1222 /* Stop the DMA engine now, in case it was running before 1223 * (The firmware could have used it, and left it running). 1224 */ 1225 gfar_halt(priv); 1226 1227 gfar_mac_reset(priv); 1228 1229 /* Zero out the rmon mib registers if it has them */ 1230 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { 1231 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib)); 1232 1233 /* Mask off the CAM interrupts */ 1234 gfar_write(®s->rmon.cam1, 0xffffffff); 1235 gfar_write(®s->rmon.cam2, 0xffffffff); 1236 } 1237 1238 /* Initialize ECNTRL */ 1239 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); 1240 1241 /* Set the extraction length and index */ 1242 attrs = ATTRELI_EL(priv->rx_stash_size) | 1243 ATTRELI_EI(priv->rx_stash_index); 1244 1245 gfar_write(®s->attreli, attrs); 1246 1247 /* Start with defaults, and add stashing 1248 * depending on driver parameters 1249 */ 1250 attrs = ATTR_INIT_SETTINGS; 1251 1252 if (priv->bd_stash_en) 1253 attrs |= ATTR_BDSTASH; 1254 1255 if (priv->rx_stash_size != 0) 1256 attrs |= ATTR_BUFSTASH; 1257 1258 gfar_write(®s->attr, attrs); 1259 1260 /* FIFO configs */ 1261 gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR); 1262 gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE); 1263 gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF); 1264 1265 /* Program the interrupt steering regs, only for MG devices */ 1266 if (priv->num_grps > 1) 1267 gfar_write_isrg(priv); 1268 } 1269 1270 static void gfar_init_addr_hash_table(struct gfar_private *priv) 1271 { 1272 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1273 1274 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { 1275 priv->extended_hash = 1; 1276 priv->hash_width = 9; 1277 1278 priv->hash_regs[0] = ®s->igaddr0; 1279 priv->hash_regs[1] = ®s->igaddr1; 1280 priv->hash_regs[2] = ®s->igaddr2; 1281 priv->hash_regs[3] = ®s->igaddr3; 1282 priv->hash_regs[4] = ®s->igaddr4; 1283 priv->hash_regs[5] = ®s->igaddr5; 1284 priv->hash_regs[6] = ®s->igaddr6; 1285 priv->hash_regs[7] = ®s->igaddr7; 1286 priv->hash_regs[8] = ®s->gaddr0; 1287 priv->hash_regs[9] = ®s->gaddr1; 1288 priv->hash_regs[10] = ®s->gaddr2; 1289 priv->hash_regs[11] = ®s->gaddr3; 1290 priv->hash_regs[12] = ®s->gaddr4; 1291 priv->hash_regs[13] = ®s->gaddr5; 1292 priv->hash_regs[14] = ®s->gaddr6; 1293 priv->hash_regs[15] = ®s->gaddr7; 1294 1295 } else { 1296 priv->extended_hash = 0; 1297 priv->hash_width = 8; 1298 1299 priv->hash_regs[0] = ®s->gaddr0; 1300 priv->hash_regs[1] = ®s->gaddr1; 1301 priv->hash_regs[2] = ®s->gaddr2; 1302 priv->hash_regs[3] = ®s->gaddr3; 1303 priv->hash_regs[4] = ®s->gaddr4; 1304 priv->hash_regs[5] = ®s->gaddr5; 1305 priv->hash_regs[6] = ®s->gaddr6; 1306 priv->hash_regs[7] = ®s->gaddr7; 1307 } 1308 } 1309 1310 /* Set up the ethernet device structure, private data, 1311 * and anything else we need before we start 1312 */ 1313 static int gfar_probe(struct platform_device *ofdev) 1314 { 1315 struct device_node *np = ofdev->dev.of_node; 1316 struct net_device *dev = NULL; 1317 struct gfar_private *priv = NULL; 1318 int err = 0, i; 1319 1320 err = gfar_of_init(ofdev, &dev); 1321 1322 if (err) 1323 return err; 1324 1325 priv = netdev_priv(dev); 1326 priv->ndev = dev; 1327 priv->ofdev = ofdev; 1328 priv->dev = &ofdev->dev; 1329 SET_NETDEV_DEV(dev, &ofdev->dev); 1330 1331 INIT_WORK(&priv->reset_task, gfar_reset_task); 1332 1333 platform_set_drvdata(ofdev, priv); 1334 1335 gfar_detect_errata(priv); 1336 1337 /* Set the dev->base_addr to the gfar reg region */ 1338 dev->base_addr = (unsigned long) priv->gfargrp[0].regs; 1339 1340 /* Fill in the dev structure */ 1341 dev->watchdog_timeo = TX_TIMEOUT; 1342 /* MTU range: 50 - 9586 */ 1343 dev->mtu = 1500; 1344 dev->min_mtu = 50; 1345 dev->max_mtu = GFAR_JUMBO_FRAME_SIZE - ETH_HLEN; 1346 dev->netdev_ops = &gfar_netdev_ops; 1347 dev->ethtool_ops = &gfar_ethtool_ops; 1348 1349 /* Register for napi ...We are registering NAPI for each grp */ 1350 for (i = 0; i < priv->num_grps; i++) { 1351 if (priv->poll_mode == GFAR_SQ_POLLING) { 1352 netif_napi_add(dev, &priv->gfargrp[i].napi_rx, 1353 gfar_poll_rx_sq, GFAR_DEV_WEIGHT); 1354 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx, 1355 gfar_poll_tx_sq, 2); 1356 } else { 1357 netif_napi_add(dev, &priv->gfargrp[i].napi_rx, 1358 gfar_poll_rx, GFAR_DEV_WEIGHT); 1359 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx, 1360 gfar_poll_tx, 2); 1361 } 1362 } 1363 1364 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { 1365 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | 1366 NETIF_F_RXCSUM; 1367 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | 1368 NETIF_F_RXCSUM | NETIF_F_HIGHDMA; 1369 } 1370 1371 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { 1372 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 1373 NETIF_F_HW_VLAN_CTAG_RX; 1374 dev->features |= NETIF_F_HW_VLAN_CTAG_RX; 1375 } 1376 1377 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 1378 1379 gfar_init_addr_hash_table(priv); 1380 1381 /* Insert receive time stamps into padding alignment bytes */ 1382 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) 1383 priv->padding = 8; 1384 1385 if (dev->features & NETIF_F_IP_CSUM || 1386 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) 1387 dev->needed_headroom = GMAC_FCB_LEN; 1388 1389 /* Initializing some of the rx/tx queue level parameters */ 1390 for (i = 0; i < priv->num_tx_queues; i++) { 1391 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; 1392 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; 1393 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; 1394 priv->tx_queue[i]->txic = DEFAULT_TXIC; 1395 } 1396 1397 for (i = 0; i < priv->num_rx_queues; i++) { 1398 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; 1399 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; 1400 priv->rx_queue[i]->rxic = DEFAULT_RXIC; 1401 } 1402 1403 /* Always enable rx filer if available */ 1404 priv->rx_filer_enable = 1405 (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0; 1406 /* Enable most messages by default */ 1407 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; 1408 /* use pritority h/w tx queue scheduling for single queue devices */ 1409 if (priv->num_tx_queues == 1) 1410 priv->prio_sched_en = 1; 1411 1412 set_bit(GFAR_DOWN, &priv->state); 1413 1414 gfar_hw_init(priv); 1415 1416 /* Carrier starts down, phylib will bring it up */ 1417 netif_carrier_off(dev); 1418 1419 err = register_netdev(dev); 1420 1421 if (err) { 1422 pr_err("%s: Cannot register net device, aborting\n", dev->name); 1423 goto register_fail; 1424 } 1425 1426 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) 1427 priv->wol_supported |= GFAR_WOL_MAGIC; 1428 1429 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) && 1430 priv->rx_filer_enable) 1431 priv->wol_supported |= GFAR_WOL_FILER_UCAST; 1432 1433 device_set_wakeup_capable(&ofdev->dev, priv->wol_supported); 1434 1435 /* fill out IRQ number and name fields */ 1436 for (i = 0; i < priv->num_grps; i++) { 1437 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 1438 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 1439 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s", 1440 dev->name, "_g", '0' + i, "_tx"); 1441 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s", 1442 dev->name, "_g", '0' + i, "_rx"); 1443 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s", 1444 dev->name, "_g", '0' + i, "_er"); 1445 } else 1446 strcpy(gfar_irq(grp, TX)->name, dev->name); 1447 } 1448 1449 /* Initialize the filer table */ 1450 gfar_init_filer_table(priv); 1451 1452 /* Print out the device info */ 1453 netdev_info(dev, "mac: %pM\n", dev->dev_addr); 1454 1455 /* Even more device info helps when determining which kernel 1456 * provided which set of benchmarks. 1457 */ 1458 netdev_info(dev, "Running with NAPI enabled\n"); 1459 for (i = 0; i < priv->num_rx_queues; i++) 1460 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n", 1461 i, priv->rx_queue[i]->rx_ring_size); 1462 for (i = 0; i < priv->num_tx_queues; i++) 1463 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n", 1464 i, priv->tx_queue[i]->tx_ring_size); 1465 1466 return 0; 1467 1468 register_fail: 1469 if (of_phy_is_fixed_link(np)) 1470 of_phy_deregister_fixed_link(np); 1471 unmap_group_regs(priv); 1472 gfar_free_rx_queues(priv); 1473 gfar_free_tx_queues(priv); 1474 of_node_put(priv->phy_node); 1475 of_node_put(priv->tbi_node); 1476 free_gfar_dev(priv); 1477 return err; 1478 } 1479 1480 static int gfar_remove(struct platform_device *ofdev) 1481 { 1482 struct gfar_private *priv = platform_get_drvdata(ofdev); 1483 struct device_node *np = ofdev->dev.of_node; 1484 1485 of_node_put(priv->phy_node); 1486 of_node_put(priv->tbi_node); 1487 1488 unregister_netdev(priv->ndev); 1489 1490 if (of_phy_is_fixed_link(np)) 1491 of_phy_deregister_fixed_link(np); 1492 1493 unmap_group_regs(priv); 1494 gfar_free_rx_queues(priv); 1495 gfar_free_tx_queues(priv); 1496 free_gfar_dev(priv); 1497 1498 return 0; 1499 } 1500 1501 #ifdef CONFIG_PM 1502 1503 static void __gfar_filer_disable(struct gfar_private *priv) 1504 { 1505 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1506 u32 temp; 1507 1508 temp = gfar_read(®s->rctrl); 1509 temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT); 1510 gfar_write(®s->rctrl, temp); 1511 } 1512 1513 static void __gfar_filer_enable(struct gfar_private *priv) 1514 { 1515 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1516 u32 temp; 1517 1518 temp = gfar_read(®s->rctrl); 1519 temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT; 1520 gfar_write(®s->rctrl, temp); 1521 } 1522 1523 /* Filer rules implementing wol capabilities */ 1524 static void gfar_filer_config_wol(struct gfar_private *priv) 1525 { 1526 unsigned int i; 1527 u32 rqfcr; 1528 1529 __gfar_filer_disable(priv); 1530 1531 /* clear the filer table, reject any packet by default */ 1532 rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH; 1533 for (i = 0; i <= MAX_FILER_IDX; i++) 1534 gfar_write_filer(priv, i, rqfcr, 0); 1535 1536 i = 0; 1537 if (priv->wol_opts & GFAR_WOL_FILER_UCAST) { 1538 /* unicast packet, accept it */ 1539 struct net_device *ndev = priv->ndev; 1540 /* get the default rx queue index */ 1541 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex; 1542 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) | 1543 (ndev->dev_addr[1] << 8) | 1544 ndev->dev_addr[2]; 1545 1546 rqfcr = (qindex << 10) | RQFCR_AND | 1547 RQFCR_CMP_EXACT | RQFCR_PID_DAH; 1548 1549 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr); 1550 1551 dest_mac_addr = (ndev->dev_addr[3] << 16) | 1552 (ndev->dev_addr[4] << 8) | 1553 ndev->dev_addr[5]; 1554 rqfcr = (qindex << 10) | RQFCR_GPI | 1555 RQFCR_CMP_EXACT | RQFCR_PID_DAL; 1556 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr); 1557 } 1558 1559 __gfar_filer_enable(priv); 1560 } 1561 1562 static void gfar_filer_restore_table(struct gfar_private *priv) 1563 { 1564 u32 rqfcr, rqfpr; 1565 unsigned int i; 1566 1567 __gfar_filer_disable(priv); 1568 1569 for (i = 0; i <= MAX_FILER_IDX; i++) { 1570 rqfcr = priv->ftp_rqfcr[i]; 1571 rqfpr = priv->ftp_rqfpr[i]; 1572 gfar_write_filer(priv, i, rqfcr, rqfpr); 1573 } 1574 1575 __gfar_filer_enable(priv); 1576 } 1577 1578 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */ 1579 static void gfar_start_wol_filer(struct gfar_private *priv) 1580 { 1581 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1582 u32 tempval; 1583 int i = 0; 1584 1585 /* Enable Rx hw queues */ 1586 gfar_write(®s->rqueue, priv->rqueue); 1587 1588 /* Initialize DMACTRL to have WWR and WOP */ 1589 tempval = gfar_read(®s->dmactrl); 1590 tempval |= DMACTRL_INIT_SETTINGS; 1591 gfar_write(®s->dmactrl, tempval); 1592 1593 /* Make sure we aren't stopped */ 1594 tempval = gfar_read(®s->dmactrl); 1595 tempval &= ~DMACTRL_GRS; 1596 gfar_write(®s->dmactrl, tempval); 1597 1598 for (i = 0; i < priv->num_grps; i++) { 1599 regs = priv->gfargrp[i].regs; 1600 /* Clear RHLT, so that the DMA starts polling now */ 1601 gfar_write(®s->rstat, priv->gfargrp[i].rstat); 1602 /* enable the Filer General Purpose Interrupt */ 1603 gfar_write(®s->imask, IMASK_FGPI); 1604 } 1605 1606 /* Enable Rx DMA */ 1607 tempval = gfar_read(®s->maccfg1); 1608 tempval |= MACCFG1_RX_EN; 1609 gfar_write(®s->maccfg1, tempval); 1610 } 1611 1612 static int gfar_suspend(struct device *dev) 1613 { 1614 struct gfar_private *priv = dev_get_drvdata(dev); 1615 struct net_device *ndev = priv->ndev; 1616 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1617 u32 tempval; 1618 u16 wol = priv->wol_opts; 1619 1620 if (!netif_running(ndev)) 1621 return 0; 1622 1623 disable_napi(priv); 1624 netif_tx_lock(ndev); 1625 netif_device_detach(ndev); 1626 netif_tx_unlock(ndev); 1627 1628 gfar_halt(priv); 1629 1630 if (wol & GFAR_WOL_MAGIC) { 1631 /* Enable interrupt on Magic Packet */ 1632 gfar_write(®s->imask, IMASK_MAG); 1633 1634 /* Enable Magic Packet mode */ 1635 tempval = gfar_read(®s->maccfg2); 1636 tempval |= MACCFG2_MPEN; 1637 gfar_write(®s->maccfg2, tempval); 1638 1639 /* re-enable the Rx block */ 1640 tempval = gfar_read(®s->maccfg1); 1641 tempval |= MACCFG1_RX_EN; 1642 gfar_write(®s->maccfg1, tempval); 1643 1644 } else if (wol & GFAR_WOL_FILER_UCAST) { 1645 gfar_filer_config_wol(priv); 1646 gfar_start_wol_filer(priv); 1647 1648 } else { 1649 phy_stop(ndev->phydev); 1650 } 1651 1652 return 0; 1653 } 1654 1655 static int gfar_resume(struct device *dev) 1656 { 1657 struct gfar_private *priv = dev_get_drvdata(dev); 1658 struct net_device *ndev = priv->ndev; 1659 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1660 u32 tempval; 1661 u16 wol = priv->wol_opts; 1662 1663 if (!netif_running(ndev)) 1664 return 0; 1665 1666 if (wol & GFAR_WOL_MAGIC) { 1667 /* Disable Magic Packet mode */ 1668 tempval = gfar_read(®s->maccfg2); 1669 tempval &= ~MACCFG2_MPEN; 1670 gfar_write(®s->maccfg2, tempval); 1671 1672 } else if (wol & GFAR_WOL_FILER_UCAST) { 1673 /* need to stop rx only, tx is already down */ 1674 gfar_halt(priv); 1675 gfar_filer_restore_table(priv); 1676 1677 } else { 1678 phy_start(ndev->phydev); 1679 } 1680 1681 gfar_start(priv); 1682 1683 netif_device_attach(ndev); 1684 enable_napi(priv); 1685 1686 return 0; 1687 } 1688 1689 static int gfar_restore(struct device *dev) 1690 { 1691 struct gfar_private *priv = dev_get_drvdata(dev); 1692 struct net_device *ndev = priv->ndev; 1693 1694 if (!netif_running(ndev)) { 1695 netif_device_attach(ndev); 1696 1697 return 0; 1698 } 1699 1700 gfar_init_bds(ndev); 1701 1702 gfar_mac_reset(priv); 1703 1704 gfar_init_tx_rx_base(priv); 1705 1706 gfar_start(priv); 1707 1708 priv->oldlink = 0; 1709 priv->oldspeed = 0; 1710 priv->oldduplex = -1; 1711 1712 if (ndev->phydev) 1713 phy_start(ndev->phydev); 1714 1715 netif_device_attach(ndev); 1716 enable_napi(priv); 1717 1718 return 0; 1719 } 1720 1721 static const struct dev_pm_ops gfar_pm_ops = { 1722 .suspend = gfar_suspend, 1723 .resume = gfar_resume, 1724 .freeze = gfar_suspend, 1725 .thaw = gfar_resume, 1726 .restore = gfar_restore, 1727 }; 1728 1729 #define GFAR_PM_OPS (&gfar_pm_ops) 1730 1731 #else 1732 1733 #define GFAR_PM_OPS NULL 1734 1735 #endif 1736 1737 /* Reads the controller's registers to determine what interface 1738 * connects it to the PHY. 1739 */ 1740 static phy_interface_t gfar_get_interface(struct net_device *dev) 1741 { 1742 struct gfar_private *priv = netdev_priv(dev); 1743 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1744 u32 ecntrl; 1745 1746 ecntrl = gfar_read(®s->ecntrl); 1747 1748 if (ecntrl & ECNTRL_SGMII_MODE) 1749 return PHY_INTERFACE_MODE_SGMII; 1750 1751 if (ecntrl & ECNTRL_TBI_MODE) { 1752 if (ecntrl & ECNTRL_REDUCED_MODE) 1753 return PHY_INTERFACE_MODE_RTBI; 1754 else 1755 return PHY_INTERFACE_MODE_TBI; 1756 } 1757 1758 if (ecntrl & ECNTRL_REDUCED_MODE) { 1759 if (ecntrl & ECNTRL_REDUCED_MII_MODE) { 1760 return PHY_INTERFACE_MODE_RMII; 1761 } 1762 else { 1763 phy_interface_t interface = priv->interface; 1764 1765 /* This isn't autodetected right now, so it must 1766 * be set by the device tree or platform code. 1767 */ 1768 if (interface == PHY_INTERFACE_MODE_RGMII_ID) 1769 return PHY_INTERFACE_MODE_RGMII_ID; 1770 1771 return PHY_INTERFACE_MODE_RGMII; 1772 } 1773 } 1774 1775 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) 1776 return PHY_INTERFACE_MODE_GMII; 1777 1778 return PHY_INTERFACE_MODE_MII; 1779 } 1780 1781 1782 /* Initializes driver's PHY state, and attaches to the PHY. 1783 * Returns 0 on success. 1784 */ 1785 static int init_phy(struct net_device *dev) 1786 { 1787 struct gfar_private *priv = netdev_priv(dev); 1788 uint gigabit_support = 1789 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? 1790 GFAR_SUPPORTED_GBIT : 0; 1791 phy_interface_t interface; 1792 struct phy_device *phydev; 1793 1794 priv->oldlink = 0; 1795 priv->oldspeed = 0; 1796 priv->oldduplex = -1; 1797 1798 interface = gfar_get_interface(dev); 1799 1800 phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, 1801 interface); 1802 if (!phydev) { 1803 dev_err(&dev->dev, "could not attach to PHY\n"); 1804 return -ENODEV; 1805 } 1806 1807 if (interface == PHY_INTERFACE_MODE_SGMII) 1808 gfar_configure_serdes(dev); 1809 1810 /* Remove any features not supported by the controller */ 1811 phydev->supported &= (GFAR_SUPPORTED | gigabit_support); 1812 phydev->advertising = phydev->supported; 1813 1814 /* Add support for flow control, but don't advertise it by default */ 1815 phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause); 1816 1817 return 0; 1818 } 1819 1820 /* Initialize TBI PHY interface for communicating with the 1821 * SERDES lynx PHY on the chip. We communicate with this PHY 1822 * through the MDIO bus on each controller, treating it as a 1823 * "normal" PHY at the address found in the TBIPA register. We assume 1824 * that the TBIPA register is valid. Either the MDIO bus code will set 1825 * it to a value that doesn't conflict with other PHYs on the bus, or the 1826 * value doesn't matter, as there are no other PHYs on the bus. 1827 */ 1828 static void gfar_configure_serdes(struct net_device *dev) 1829 { 1830 struct gfar_private *priv = netdev_priv(dev); 1831 struct phy_device *tbiphy; 1832 1833 if (!priv->tbi_node) { 1834 dev_warn(&dev->dev, "error: SGMII mode requires that the " 1835 "device tree specify a tbi-handle\n"); 1836 return; 1837 } 1838 1839 tbiphy = of_phy_find_device(priv->tbi_node); 1840 if (!tbiphy) { 1841 dev_err(&dev->dev, "error: Could not get TBI device\n"); 1842 return; 1843 } 1844 1845 /* If the link is already up, we must already be ok, and don't need to 1846 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured 1847 * everything for us? Resetting it takes the link down and requires 1848 * several seconds for it to come back. 1849 */ 1850 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) { 1851 put_device(&tbiphy->mdio.dev); 1852 return; 1853 } 1854 1855 /* Single clk mode, mii mode off(for serdes communication) */ 1856 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); 1857 1858 phy_write(tbiphy, MII_ADVERTISE, 1859 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | 1860 ADVERTISE_1000XPSE_ASYM); 1861 1862 phy_write(tbiphy, MII_BMCR, 1863 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | 1864 BMCR_SPEED1000); 1865 1866 put_device(&tbiphy->mdio.dev); 1867 } 1868 1869 static int __gfar_is_rx_idle(struct gfar_private *priv) 1870 { 1871 u32 res; 1872 1873 /* Normaly TSEC should not hang on GRS commands, so we should 1874 * actually wait for IEVENT_GRSC flag. 1875 */ 1876 if (!gfar_has_errata(priv, GFAR_ERRATA_A002)) 1877 return 0; 1878 1879 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are 1880 * the same as bits 23-30, the eTSEC Rx is assumed to be idle 1881 * and the Rx can be safely reset. 1882 */ 1883 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); 1884 res &= 0x7f807f80; 1885 if ((res & 0xffff) == (res >> 16)) 1886 return 1; 1887 1888 return 0; 1889 } 1890 1891 /* Halt the receive and transmit queues */ 1892 static void gfar_halt_nodisable(struct gfar_private *priv) 1893 { 1894 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1895 u32 tempval; 1896 unsigned int timeout; 1897 int stopped; 1898 1899 gfar_ints_disable(priv); 1900 1901 if (gfar_is_dma_stopped(priv)) 1902 return; 1903 1904 /* Stop the DMA, and wait for it to stop */ 1905 tempval = gfar_read(®s->dmactrl); 1906 tempval |= (DMACTRL_GRS | DMACTRL_GTS); 1907 gfar_write(®s->dmactrl, tempval); 1908 1909 retry: 1910 timeout = 1000; 1911 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) { 1912 cpu_relax(); 1913 timeout--; 1914 } 1915 1916 if (!timeout) 1917 stopped = gfar_is_dma_stopped(priv); 1918 1919 if (!stopped && !gfar_is_rx_dma_stopped(priv) && 1920 !__gfar_is_rx_idle(priv)) 1921 goto retry; 1922 } 1923 1924 /* Halt the receive and transmit queues */ 1925 void gfar_halt(struct gfar_private *priv) 1926 { 1927 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1928 u32 tempval; 1929 1930 /* Dissable the Rx/Tx hw queues */ 1931 gfar_write(®s->rqueue, 0); 1932 gfar_write(®s->tqueue, 0); 1933 1934 mdelay(10); 1935 1936 gfar_halt_nodisable(priv); 1937 1938 /* Disable Rx/Tx DMA */ 1939 tempval = gfar_read(®s->maccfg1); 1940 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); 1941 gfar_write(®s->maccfg1, tempval); 1942 } 1943 1944 void stop_gfar(struct net_device *dev) 1945 { 1946 struct gfar_private *priv = netdev_priv(dev); 1947 1948 netif_tx_stop_all_queues(dev); 1949 1950 smp_mb__before_atomic(); 1951 set_bit(GFAR_DOWN, &priv->state); 1952 smp_mb__after_atomic(); 1953 1954 disable_napi(priv); 1955 1956 /* disable ints and gracefully shut down Rx/Tx DMA */ 1957 gfar_halt(priv); 1958 1959 phy_stop(dev->phydev); 1960 1961 free_skb_resources(priv); 1962 } 1963 1964 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) 1965 { 1966 struct txbd8 *txbdp; 1967 struct gfar_private *priv = netdev_priv(tx_queue->dev); 1968 int i, j; 1969 1970 txbdp = tx_queue->tx_bd_base; 1971 1972 for (i = 0; i < tx_queue->tx_ring_size; i++) { 1973 if (!tx_queue->tx_skbuff[i]) 1974 continue; 1975 1976 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr), 1977 be16_to_cpu(txbdp->length), DMA_TO_DEVICE); 1978 txbdp->lstatus = 0; 1979 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; 1980 j++) { 1981 txbdp++; 1982 dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr), 1983 be16_to_cpu(txbdp->length), 1984 DMA_TO_DEVICE); 1985 } 1986 txbdp++; 1987 dev_kfree_skb_any(tx_queue->tx_skbuff[i]); 1988 tx_queue->tx_skbuff[i] = NULL; 1989 } 1990 kfree(tx_queue->tx_skbuff); 1991 tx_queue->tx_skbuff = NULL; 1992 } 1993 1994 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) 1995 { 1996 int i; 1997 1998 struct rxbd8 *rxbdp = rx_queue->rx_bd_base; 1999 2000 if (rx_queue->skb) 2001 dev_kfree_skb(rx_queue->skb); 2002 2003 for (i = 0; i < rx_queue->rx_ring_size; i++) { 2004 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[i]; 2005 2006 rxbdp->lstatus = 0; 2007 rxbdp->bufPtr = 0; 2008 rxbdp++; 2009 2010 if (!rxb->page) 2011 continue; 2012 2013 dma_unmap_page(rx_queue->dev, rxb->dma, 2014 PAGE_SIZE, DMA_FROM_DEVICE); 2015 __free_page(rxb->page); 2016 2017 rxb->page = NULL; 2018 } 2019 2020 kfree(rx_queue->rx_buff); 2021 rx_queue->rx_buff = NULL; 2022 } 2023 2024 /* If there are any tx skbs or rx skbs still around, free them. 2025 * Then free tx_skbuff and rx_skbuff 2026 */ 2027 static void free_skb_resources(struct gfar_private *priv) 2028 { 2029 struct gfar_priv_tx_q *tx_queue = NULL; 2030 struct gfar_priv_rx_q *rx_queue = NULL; 2031 int i; 2032 2033 /* Go through all the buffer descriptors and free their data buffers */ 2034 for (i = 0; i < priv->num_tx_queues; i++) { 2035 struct netdev_queue *txq; 2036 2037 tx_queue = priv->tx_queue[i]; 2038 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); 2039 if (tx_queue->tx_skbuff) 2040 free_skb_tx_queue(tx_queue); 2041 netdev_tx_reset_queue(txq); 2042 } 2043 2044 for (i = 0; i < priv->num_rx_queues; i++) { 2045 rx_queue = priv->rx_queue[i]; 2046 if (rx_queue->rx_buff) 2047 free_skb_rx_queue(rx_queue); 2048 } 2049 2050 dma_free_coherent(priv->dev, 2051 sizeof(struct txbd8) * priv->total_tx_ring_size + 2052 sizeof(struct rxbd8) * priv->total_rx_ring_size, 2053 priv->tx_queue[0]->tx_bd_base, 2054 priv->tx_queue[0]->tx_bd_dma_base); 2055 } 2056 2057 void gfar_start(struct gfar_private *priv) 2058 { 2059 struct gfar __iomem *regs = priv->gfargrp[0].regs; 2060 u32 tempval; 2061 int i = 0; 2062 2063 /* Enable Rx/Tx hw queues */ 2064 gfar_write(®s->rqueue, priv->rqueue); 2065 gfar_write(®s->tqueue, priv->tqueue); 2066 2067 /* Initialize DMACTRL to have WWR and WOP */ 2068 tempval = gfar_read(®s->dmactrl); 2069 tempval |= DMACTRL_INIT_SETTINGS; 2070 gfar_write(®s->dmactrl, tempval); 2071 2072 /* Make sure we aren't stopped */ 2073 tempval = gfar_read(®s->dmactrl); 2074 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); 2075 gfar_write(®s->dmactrl, tempval); 2076 2077 for (i = 0; i < priv->num_grps; i++) { 2078 regs = priv->gfargrp[i].regs; 2079 /* Clear THLT/RHLT, so that the DMA starts polling now */ 2080 gfar_write(®s->tstat, priv->gfargrp[i].tstat); 2081 gfar_write(®s->rstat, priv->gfargrp[i].rstat); 2082 } 2083 2084 /* Enable Rx/Tx DMA */ 2085 tempval = gfar_read(®s->maccfg1); 2086 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 2087 gfar_write(®s->maccfg1, tempval); 2088 2089 gfar_ints_enable(priv); 2090 2091 netif_trans_update(priv->ndev); /* prevent tx timeout */ 2092 } 2093 2094 static void free_grp_irqs(struct gfar_priv_grp *grp) 2095 { 2096 free_irq(gfar_irq(grp, TX)->irq, grp); 2097 free_irq(gfar_irq(grp, RX)->irq, grp); 2098 free_irq(gfar_irq(grp, ER)->irq, grp); 2099 } 2100 2101 static int register_grp_irqs(struct gfar_priv_grp *grp) 2102 { 2103 struct gfar_private *priv = grp->priv; 2104 struct net_device *dev = priv->ndev; 2105 int err; 2106 2107 /* If the device has multiple interrupts, register for 2108 * them. Otherwise, only register for the one 2109 */ 2110 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 2111 /* Install our interrupt handlers for Error, 2112 * Transmit, and Receive 2113 */ 2114 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0, 2115 gfar_irq(grp, ER)->name, grp); 2116 if (err < 0) { 2117 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2118 gfar_irq(grp, ER)->irq); 2119 2120 goto err_irq_fail; 2121 } 2122 enable_irq_wake(gfar_irq(grp, ER)->irq); 2123 2124 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0, 2125 gfar_irq(grp, TX)->name, grp); 2126 if (err < 0) { 2127 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2128 gfar_irq(grp, TX)->irq); 2129 goto tx_irq_fail; 2130 } 2131 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0, 2132 gfar_irq(grp, RX)->name, grp); 2133 if (err < 0) { 2134 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2135 gfar_irq(grp, RX)->irq); 2136 goto rx_irq_fail; 2137 } 2138 enable_irq_wake(gfar_irq(grp, RX)->irq); 2139 2140 } else { 2141 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0, 2142 gfar_irq(grp, TX)->name, grp); 2143 if (err < 0) { 2144 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2145 gfar_irq(grp, TX)->irq); 2146 goto err_irq_fail; 2147 } 2148 enable_irq_wake(gfar_irq(grp, TX)->irq); 2149 } 2150 2151 return 0; 2152 2153 rx_irq_fail: 2154 free_irq(gfar_irq(grp, TX)->irq, grp); 2155 tx_irq_fail: 2156 free_irq(gfar_irq(grp, ER)->irq, grp); 2157 err_irq_fail: 2158 return err; 2159 2160 } 2161 2162 static void gfar_free_irq(struct gfar_private *priv) 2163 { 2164 int i; 2165 2166 /* Free the IRQs */ 2167 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 2168 for (i = 0; i < priv->num_grps; i++) 2169 free_grp_irqs(&priv->gfargrp[i]); 2170 } else { 2171 for (i = 0; i < priv->num_grps; i++) 2172 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq, 2173 &priv->gfargrp[i]); 2174 } 2175 } 2176 2177 static int gfar_request_irq(struct gfar_private *priv) 2178 { 2179 int err, i, j; 2180 2181 for (i = 0; i < priv->num_grps; i++) { 2182 err = register_grp_irqs(&priv->gfargrp[i]); 2183 if (err) { 2184 for (j = 0; j < i; j++) 2185 free_grp_irqs(&priv->gfargrp[j]); 2186 return err; 2187 } 2188 } 2189 2190 return 0; 2191 } 2192 2193 /* Bring the controller up and running */ 2194 int startup_gfar(struct net_device *ndev) 2195 { 2196 struct gfar_private *priv = netdev_priv(ndev); 2197 int err; 2198 2199 gfar_mac_reset(priv); 2200 2201 err = gfar_alloc_skb_resources(ndev); 2202 if (err) 2203 return err; 2204 2205 gfar_init_tx_rx_base(priv); 2206 2207 smp_mb__before_atomic(); 2208 clear_bit(GFAR_DOWN, &priv->state); 2209 smp_mb__after_atomic(); 2210 2211 /* Start Rx/Tx DMA and enable the interrupts */ 2212 gfar_start(priv); 2213 2214 /* force link state update after mac reset */ 2215 priv->oldlink = 0; 2216 priv->oldspeed = 0; 2217 priv->oldduplex = -1; 2218 2219 phy_start(ndev->phydev); 2220 2221 enable_napi(priv); 2222 2223 netif_tx_wake_all_queues(ndev); 2224 2225 return 0; 2226 } 2227 2228 /* Called when something needs to use the ethernet device 2229 * Returns 0 for success. 2230 */ 2231 static int gfar_enet_open(struct net_device *dev) 2232 { 2233 struct gfar_private *priv = netdev_priv(dev); 2234 int err; 2235 2236 err = init_phy(dev); 2237 if (err) 2238 return err; 2239 2240 err = gfar_request_irq(priv); 2241 if (err) 2242 return err; 2243 2244 err = startup_gfar(dev); 2245 if (err) 2246 return err; 2247 2248 return err; 2249 } 2250 2251 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) 2252 { 2253 struct txfcb *fcb = skb_push(skb, GMAC_FCB_LEN); 2254 2255 memset(fcb, 0, GMAC_FCB_LEN); 2256 2257 return fcb; 2258 } 2259 2260 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb, 2261 int fcb_length) 2262 { 2263 /* If we're here, it's a IP packet with a TCP or UDP 2264 * payload. We set it to checksum, using a pseudo-header 2265 * we provide 2266 */ 2267 u8 flags = TXFCB_DEFAULT; 2268 2269 /* Tell the controller what the protocol is 2270 * And provide the already calculated phcs 2271 */ 2272 if (ip_hdr(skb)->protocol == IPPROTO_UDP) { 2273 flags |= TXFCB_UDP; 2274 fcb->phcs = (__force __be16)(udp_hdr(skb)->check); 2275 } else 2276 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check); 2277 2278 /* l3os is the distance between the start of the 2279 * frame (skb->data) and the start of the IP hdr. 2280 * l4os is the distance between the start of the 2281 * l3 hdr and the l4 hdr 2282 */ 2283 fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length); 2284 fcb->l4os = skb_network_header_len(skb); 2285 2286 fcb->flags = flags; 2287 } 2288 2289 static inline void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) 2290 { 2291 fcb->flags |= TXFCB_VLN; 2292 fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb)); 2293 } 2294 2295 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, 2296 struct txbd8 *base, int ring_size) 2297 { 2298 struct txbd8 *new_bd = bdp + stride; 2299 2300 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; 2301 } 2302 2303 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, 2304 int ring_size) 2305 { 2306 return skip_txbd(bdp, 1, base, ring_size); 2307 } 2308 2309 /* eTSEC12: csum generation not supported for some fcb offsets */ 2310 static inline bool gfar_csum_errata_12(struct gfar_private *priv, 2311 unsigned long fcb_addr) 2312 { 2313 return (gfar_has_errata(priv, GFAR_ERRATA_12) && 2314 (fcb_addr % 0x20) > 0x18); 2315 } 2316 2317 /* eTSEC76: csum generation for frames larger than 2500 may 2318 * cause excess delays before start of transmission 2319 */ 2320 static inline bool gfar_csum_errata_76(struct gfar_private *priv, 2321 unsigned int len) 2322 { 2323 return (gfar_has_errata(priv, GFAR_ERRATA_76) && 2324 (len > 2500)); 2325 } 2326 2327 /* This is called by the kernel when a frame is ready for transmission. 2328 * It is pointed to by the dev->hard_start_xmit function pointer 2329 */ 2330 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) 2331 { 2332 struct gfar_private *priv = netdev_priv(dev); 2333 struct gfar_priv_tx_q *tx_queue = NULL; 2334 struct netdev_queue *txq; 2335 struct gfar __iomem *regs = NULL; 2336 struct txfcb *fcb = NULL; 2337 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; 2338 u32 lstatus; 2339 skb_frag_t *frag; 2340 int i, rq = 0; 2341 int do_tstamp, do_csum, do_vlan; 2342 u32 bufaddr; 2343 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0; 2344 2345 rq = skb->queue_mapping; 2346 tx_queue = priv->tx_queue[rq]; 2347 txq = netdev_get_tx_queue(dev, rq); 2348 base = tx_queue->tx_bd_base; 2349 regs = tx_queue->grp->regs; 2350 2351 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed); 2352 do_vlan = skb_vlan_tag_present(skb); 2353 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2354 priv->hwts_tx_en; 2355 2356 if (do_csum || do_vlan) 2357 fcb_len = GMAC_FCB_LEN; 2358 2359 /* check if time stamp should be generated */ 2360 if (unlikely(do_tstamp)) 2361 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN; 2362 2363 /* make space for additional header when fcb is needed */ 2364 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) { 2365 struct sk_buff *skb_new; 2366 2367 skb_new = skb_realloc_headroom(skb, fcb_len); 2368 if (!skb_new) { 2369 dev->stats.tx_errors++; 2370 dev_kfree_skb_any(skb); 2371 return NETDEV_TX_OK; 2372 } 2373 2374 if (skb->sk) 2375 skb_set_owner_w(skb_new, skb->sk); 2376 dev_consume_skb_any(skb); 2377 skb = skb_new; 2378 } 2379 2380 /* total number of fragments in the SKB */ 2381 nr_frags = skb_shinfo(skb)->nr_frags; 2382 2383 /* calculate the required number of TxBDs for this skb */ 2384 if (unlikely(do_tstamp)) 2385 nr_txbds = nr_frags + 2; 2386 else 2387 nr_txbds = nr_frags + 1; 2388 2389 /* check if there is space to queue this packet */ 2390 if (nr_txbds > tx_queue->num_txbdfree) { 2391 /* no space, stop the queue */ 2392 netif_tx_stop_queue(txq); 2393 dev->stats.tx_fifo_errors++; 2394 return NETDEV_TX_BUSY; 2395 } 2396 2397 /* Update transmit stats */ 2398 bytes_sent = skb->len; 2399 tx_queue->stats.tx_bytes += bytes_sent; 2400 /* keep Tx bytes on wire for BQL accounting */ 2401 GFAR_CB(skb)->bytes_sent = bytes_sent; 2402 tx_queue->stats.tx_packets++; 2403 2404 txbdp = txbdp_start = tx_queue->cur_tx; 2405 lstatus = be32_to_cpu(txbdp->lstatus); 2406 2407 /* Add TxPAL between FCB and frame if required */ 2408 if (unlikely(do_tstamp)) { 2409 skb_push(skb, GMAC_TXPAL_LEN); 2410 memset(skb->data, 0, GMAC_TXPAL_LEN); 2411 } 2412 2413 /* Add TxFCB if required */ 2414 if (fcb_len) { 2415 fcb = gfar_add_fcb(skb); 2416 lstatus |= BD_LFLAG(TXBD_TOE); 2417 } 2418 2419 /* Set up checksumming */ 2420 if (do_csum) { 2421 gfar_tx_checksum(skb, fcb, fcb_len); 2422 2423 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) || 2424 unlikely(gfar_csum_errata_76(priv, skb->len))) { 2425 __skb_pull(skb, GMAC_FCB_LEN); 2426 skb_checksum_help(skb); 2427 if (do_vlan || do_tstamp) { 2428 /* put back a new fcb for vlan/tstamp TOE */ 2429 fcb = gfar_add_fcb(skb); 2430 } else { 2431 /* Tx TOE not used */ 2432 lstatus &= ~(BD_LFLAG(TXBD_TOE)); 2433 fcb = NULL; 2434 } 2435 } 2436 } 2437 2438 if (do_vlan) 2439 gfar_tx_vlan(skb, fcb); 2440 2441 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb), 2442 DMA_TO_DEVICE); 2443 if (unlikely(dma_mapping_error(priv->dev, bufaddr))) 2444 goto dma_map_err; 2445 2446 txbdp_start->bufPtr = cpu_to_be32(bufaddr); 2447 2448 /* Time stamp insertion requires one additional TxBD */ 2449 if (unlikely(do_tstamp)) 2450 txbdp_tstamp = txbdp = next_txbd(txbdp, base, 2451 tx_queue->tx_ring_size); 2452 2453 if (likely(!nr_frags)) { 2454 if (likely(!do_tstamp)) 2455 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 2456 } else { 2457 u32 lstatus_start = lstatus; 2458 2459 /* Place the fragment addresses and lengths into the TxBDs */ 2460 frag = &skb_shinfo(skb)->frags[0]; 2461 for (i = 0; i < nr_frags; i++, frag++) { 2462 unsigned int size; 2463 2464 /* Point at the next BD, wrapping as needed */ 2465 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2466 2467 size = skb_frag_size(frag); 2468 2469 lstatus = be32_to_cpu(txbdp->lstatus) | size | 2470 BD_LFLAG(TXBD_READY); 2471 2472 /* Handle the last BD specially */ 2473 if (i == nr_frags - 1) 2474 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 2475 2476 bufaddr = skb_frag_dma_map(priv->dev, frag, 0, 2477 size, DMA_TO_DEVICE); 2478 if (unlikely(dma_mapping_error(priv->dev, bufaddr))) 2479 goto dma_map_err; 2480 2481 /* set the TxBD length and buffer pointer */ 2482 txbdp->bufPtr = cpu_to_be32(bufaddr); 2483 txbdp->lstatus = cpu_to_be32(lstatus); 2484 } 2485 2486 lstatus = lstatus_start; 2487 } 2488 2489 /* If time stamping is requested one additional TxBD must be set up. The 2490 * first TxBD points to the FCB and must have a data length of 2491 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with 2492 * the full frame length. 2493 */ 2494 if (unlikely(do_tstamp)) { 2495 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus); 2496 2497 bufaddr = be32_to_cpu(txbdp_start->bufPtr); 2498 bufaddr += fcb_len; 2499 2500 lstatus_ts |= BD_LFLAG(TXBD_READY) | 2501 (skb_headlen(skb) - fcb_len); 2502 if (!nr_frags) 2503 lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 2504 2505 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr); 2506 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts); 2507 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; 2508 2509 /* Setup tx hardware time stamping */ 2510 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2511 fcb->ptp = 1; 2512 } else { 2513 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); 2514 } 2515 2516 netdev_tx_sent_queue(txq, bytes_sent); 2517 2518 gfar_wmb(); 2519 2520 txbdp_start->lstatus = cpu_to_be32(lstatus); 2521 2522 gfar_wmb(); /* force lstatus write before tx_skbuff */ 2523 2524 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; 2525 2526 /* Update the current skb pointer to the next entry we will use 2527 * (wrapping if necessary) 2528 */ 2529 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & 2530 TX_RING_MOD_MASK(tx_queue->tx_ring_size); 2531 2532 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2533 2534 /* We can work in parallel with gfar_clean_tx_ring(), except 2535 * when modifying num_txbdfree. Note that we didn't grab the lock 2536 * when we were reading the num_txbdfree and checking for available 2537 * space, that's because outside of this function it can only grow. 2538 */ 2539 spin_lock_bh(&tx_queue->txlock); 2540 /* reduce TxBD free count */ 2541 tx_queue->num_txbdfree -= (nr_txbds); 2542 spin_unlock_bh(&tx_queue->txlock); 2543 2544 /* If the next BD still needs to be cleaned up, then the bds 2545 * are full. We need to tell the kernel to stop sending us stuff. 2546 */ 2547 if (!tx_queue->num_txbdfree) { 2548 netif_tx_stop_queue(txq); 2549 2550 dev->stats.tx_fifo_errors++; 2551 } 2552 2553 /* Tell the DMA to go go go */ 2554 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); 2555 2556 return NETDEV_TX_OK; 2557 2558 dma_map_err: 2559 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size); 2560 if (do_tstamp) 2561 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2562 for (i = 0; i < nr_frags; i++) { 2563 lstatus = be32_to_cpu(txbdp->lstatus); 2564 if (!(lstatus & BD_LFLAG(TXBD_READY))) 2565 break; 2566 2567 lstatus &= ~BD_LFLAG(TXBD_READY); 2568 txbdp->lstatus = cpu_to_be32(lstatus); 2569 bufaddr = be32_to_cpu(txbdp->bufPtr); 2570 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length), 2571 DMA_TO_DEVICE); 2572 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2573 } 2574 gfar_wmb(); 2575 dev_kfree_skb_any(skb); 2576 return NETDEV_TX_OK; 2577 } 2578 2579 /* Stops the kernel queue, and halts the controller */ 2580 static int gfar_close(struct net_device *dev) 2581 { 2582 struct gfar_private *priv = netdev_priv(dev); 2583 2584 cancel_work_sync(&priv->reset_task); 2585 stop_gfar(dev); 2586 2587 /* Disconnect from the PHY */ 2588 phy_disconnect(dev->phydev); 2589 2590 gfar_free_irq(priv); 2591 2592 return 0; 2593 } 2594 2595 /* Changes the mac address if the controller is not running. */ 2596 static int gfar_set_mac_address(struct net_device *dev) 2597 { 2598 gfar_set_mac_for_addr(dev, 0, dev->dev_addr); 2599 2600 return 0; 2601 } 2602 2603 static int gfar_change_mtu(struct net_device *dev, int new_mtu) 2604 { 2605 struct gfar_private *priv = netdev_priv(dev); 2606 2607 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state)) 2608 cpu_relax(); 2609 2610 if (dev->flags & IFF_UP) 2611 stop_gfar(dev); 2612 2613 dev->mtu = new_mtu; 2614 2615 if (dev->flags & IFF_UP) 2616 startup_gfar(dev); 2617 2618 clear_bit_unlock(GFAR_RESETTING, &priv->state); 2619 2620 return 0; 2621 } 2622 2623 void reset_gfar(struct net_device *ndev) 2624 { 2625 struct gfar_private *priv = netdev_priv(ndev); 2626 2627 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state)) 2628 cpu_relax(); 2629 2630 stop_gfar(ndev); 2631 startup_gfar(ndev); 2632 2633 clear_bit_unlock(GFAR_RESETTING, &priv->state); 2634 } 2635 2636 /* gfar_reset_task gets scheduled when a packet has not been 2637 * transmitted after a set amount of time. 2638 * For now, assume that clearing out all the structures, and 2639 * starting over will fix the problem. 2640 */ 2641 static void gfar_reset_task(struct work_struct *work) 2642 { 2643 struct gfar_private *priv = container_of(work, struct gfar_private, 2644 reset_task); 2645 reset_gfar(priv->ndev); 2646 } 2647 2648 static void gfar_timeout(struct net_device *dev) 2649 { 2650 struct gfar_private *priv = netdev_priv(dev); 2651 2652 dev->stats.tx_errors++; 2653 schedule_work(&priv->reset_task); 2654 } 2655 2656 /* Interrupt Handler for Transmit complete */ 2657 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) 2658 { 2659 struct net_device *dev = tx_queue->dev; 2660 struct netdev_queue *txq; 2661 struct gfar_private *priv = netdev_priv(dev); 2662 struct txbd8 *bdp, *next = NULL; 2663 struct txbd8 *lbdp = NULL; 2664 struct txbd8 *base = tx_queue->tx_bd_base; 2665 struct sk_buff *skb; 2666 int skb_dirtytx; 2667 int tx_ring_size = tx_queue->tx_ring_size; 2668 int frags = 0, nr_txbds = 0; 2669 int i; 2670 int howmany = 0; 2671 int tqi = tx_queue->qindex; 2672 unsigned int bytes_sent = 0; 2673 u32 lstatus; 2674 size_t buflen; 2675 2676 txq = netdev_get_tx_queue(dev, tqi); 2677 bdp = tx_queue->dirty_tx; 2678 skb_dirtytx = tx_queue->skb_dirtytx; 2679 2680 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { 2681 2682 frags = skb_shinfo(skb)->nr_frags; 2683 2684 /* When time stamping, one additional TxBD must be freed. 2685 * Also, we need to dma_unmap_single() the TxPAL. 2686 */ 2687 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) 2688 nr_txbds = frags + 2; 2689 else 2690 nr_txbds = frags + 1; 2691 2692 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); 2693 2694 lstatus = be32_to_cpu(lbdp->lstatus); 2695 2696 /* Only clean completed frames */ 2697 if ((lstatus & BD_LFLAG(TXBD_READY)) && 2698 (lstatus & BD_LENGTH_MASK)) 2699 break; 2700 2701 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { 2702 next = next_txbd(bdp, base, tx_ring_size); 2703 buflen = be16_to_cpu(next->length) + 2704 GMAC_FCB_LEN + GMAC_TXPAL_LEN; 2705 } else 2706 buflen = be16_to_cpu(bdp->length); 2707 2708 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr), 2709 buflen, DMA_TO_DEVICE); 2710 2711 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { 2712 struct skb_shared_hwtstamps shhwtstamps; 2713 u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) & 2714 ~0x7UL); 2715 2716 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 2717 shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns)); 2718 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN); 2719 skb_tstamp_tx(skb, &shhwtstamps); 2720 gfar_clear_txbd_status(bdp); 2721 bdp = next; 2722 } 2723 2724 gfar_clear_txbd_status(bdp); 2725 bdp = next_txbd(bdp, base, tx_ring_size); 2726 2727 for (i = 0; i < frags; i++) { 2728 dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr), 2729 be16_to_cpu(bdp->length), 2730 DMA_TO_DEVICE); 2731 gfar_clear_txbd_status(bdp); 2732 bdp = next_txbd(bdp, base, tx_ring_size); 2733 } 2734 2735 bytes_sent += GFAR_CB(skb)->bytes_sent; 2736 2737 dev_kfree_skb_any(skb); 2738 2739 tx_queue->tx_skbuff[skb_dirtytx] = NULL; 2740 2741 skb_dirtytx = (skb_dirtytx + 1) & 2742 TX_RING_MOD_MASK(tx_ring_size); 2743 2744 howmany++; 2745 spin_lock(&tx_queue->txlock); 2746 tx_queue->num_txbdfree += nr_txbds; 2747 spin_unlock(&tx_queue->txlock); 2748 } 2749 2750 /* If we freed a buffer, we can restart transmission, if necessary */ 2751 if (tx_queue->num_txbdfree && 2752 netif_tx_queue_stopped(txq) && 2753 !(test_bit(GFAR_DOWN, &priv->state))) 2754 netif_wake_subqueue(priv->ndev, tqi); 2755 2756 /* Update dirty indicators */ 2757 tx_queue->skb_dirtytx = skb_dirtytx; 2758 tx_queue->dirty_tx = bdp; 2759 2760 netdev_tx_completed_queue(txq, howmany, bytes_sent); 2761 } 2762 2763 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb) 2764 { 2765 struct page *page; 2766 dma_addr_t addr; 2767 2768 page = dev_alloc_page(); 2769 if (unlikely(!page)) 2770 return false; 2771 2772 addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 2773 if (unlikely(dma_mapping_error(rxq->dev, addr))) { 2774 __free_page(page); 2775 2776 return false; 2777 } 2778 2779 rxb->dma = addr; 2780 rxb->page = page; 2781 rxb->page_offset = 0; 2782 2783 return true; 2784 } 2785 2786 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue) 2787 { 2788 struct gfar_private *priv = netdev_priv(rx_queue->ndev); 2789 struct gfar_extra_stats *estats = &priv->extra_stats; 2790 2791 netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n"); 2792 atomic64_inc(&estats->rx_alloc_err); 2793 } 2794 2795 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue, 2796 int alloc_cnt) 2797 { 2798 struct rxbd8 *bdp; 2799 struct gfar_rx_buff *rxb; 2800 int i; 2801 2802 i = rx_queue->next_to_use; 2803 bdp = &rx_queue->rx_bd_base[i]; 2804 rxb = &rx_queue->rx_buff[i]; 2805 2806 while (alloc_cnt--) { 2807 /* try reuse page */ 2808 if (unlikely(!rxb->page)) { 2809 if (unlikely(!gfar_new_page(rx_queue, rxb))) { 2810 gfar_rx_alloc_err(rx_queue); 2811 break; 2812 } 2813 } 2814 2815 /* Setup the new RxBD */ 2816 gfar_init_rxbdp(rx_queue, bdp, 2817 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT); 2818 2819 /* Update to the next pointer */ 2820 bdp++; 2821 rxb++; 2822 2823 if (unlikely(++i == rx_queue->rx_ring_size)) { 2824 i = 0; 2825 bdp = rx_queue->rx_bd_base; 2826 rxb = rx_queue->rx_buff; 2827 } 2828 } 2829 2830 rx_queue->next_to_use = i; 2831 rx_queue->next_to_alloc = i; 2832 } 2833 2834 static void count_errors(u32 lstatus, struct net_device *ndev) 2835 { 2836 struct gfar_private *priv = netdev_priv(ndev); 2837 struct net_device_stats *stats = &ndev->stats; 2838 struct gfar_extra_stats *estats = &priv->extra_stats; 2839 2840 /* If the packet was truncated, none of the other errors matter */ 2841 if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) { 2842 stats->rx_length_errors++; 2843 2844 atomic64_inc(&estats->rx_trunc); 2845 2846 return; 2847 } 2848 /* Count the errors, if there were any */ 2849 if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) { 2850 stats->rx_length_errors++; 2851 2852 if (lstatus & BD_LFLAG(RXBD_LARGE)) 2853 atomic64_inc(&estats->rx_large); 2854 else 2855 atomic64_inc(&estats->rx_short); 2856 } 2857 if (lstatus & BD_LFLAG(RXBD_NONOCTET)) { 2858 stats->rx_frame_errors++; 2859 atomic64_inc(&estats->rx_nonoctet); 2860 } 2861 if (lstatus & BD_LFLAG(RXBD_CRCERR)) { 2862 atomic64_inc(&estats->rx_crcerr); 2863 stats->rx_crc_errors++; 2864 } 2865 if (lstatus & BD_LFLAG(RXBD_OVERRUN)) { 2866 atomic64_inc(&estats->rx_overrun); 2867 stats->rx_over_errors++; 2868 } 2869 } 2870 2871 irqreturn_t gfar_receive(int irq, void *grp_id) 2872 { 2873 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id; 2874 unsigned long flags; 2875 u32 imask, ievent; 2876 2877 ievent = gfar_read(&grp->regs->ievent); 2878 2879 if (unlikely(ievent & IEVENT_FGPI)) { 2880 gfar_write(&grp->regs->ievent, IEVENT_FGPI); 2881 return IRQ_HANDLED; 2882 } 2883 2884 if (likely(napi_schedule_prep(&grp->napi_rx))) { 2885 spin_lock_irqsave(&grp->grplock, flags); 2886 imask = gfar_read(&grp->regs->imask); 2887 imask &= IMASK_RX_DISABLED; 2888 gfar_write(&grp->regs->imask, imask); 2889 spin_unlock_irqrestore(&grp->grplock, flags); 2890 __napi_schedule(&grp->napi_rx); 2891 } else { 2892 /* Clear IEVENT, so interrupts aren't called again 2893 * because of the packets that have already arrived. 2894 */ 2895 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK); 2896 } 2897 2898 return IRQ_HANDLED; 2899 } 2900 2901 /* Interrupt Handler for Transmit complete */ 2902 static irqreturn_t gfar_transmit(int irq, void *grp_id) 2903 { 2904 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id; 2905 unsigned long flags; 2906 u32 imask; 2907 2908 if (likely(napi_schedule_prep(&grp->napi_tx))) { 2909 spin_lock_irqsave(&grp->grplock, flags); 2910 imask = gfar_read(&grp->regs->imask); 2911 imask &= IMASK_TX_DISABLED; 2912 gfar_write(&grp->regs->imask, imask); 2913 spin_unlock_irqrestore(&grp->grplock, flags); 2914 __napi_schedule(&grp->napi_tx); 2915 } else { 2916 /* Clear IEVENT, so interrupts aren't called again 2917 * because of the packets that have already arrived. 2918 */ 2919 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK); 2920 } 2921 2922 return IRQ_HANDLED; 2923 } 2924 2925 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus, 2926 struct sk_buff *skb, bool first) 2927 { 2928 unsigned int size = lstatus & BD_LENGTH_MASK; 2929 struct page *page = rxb->page; 2930 bool last = !!(lstatus & BD_LFLAG(RXBD_LAST)); 2931 2932 /* Remove the FCS from the packet length */ 2933 if (last) 2934 size -= ETH_FCS_LEN; 2935 2936 if (likely(first)) { 2937 skb_put(skb, size); 2938 } else { 2939 /* the last fragments' length contains the full frame length */ 2940 if (last) 2941 size -= skb->len; 2942 2943 /* in case the last fragment consisted only of the FCS */ 2944 if (size > 0) 2945 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 2946 rxb->page_offset + RXBUF_ALIGNMENT, 2947 size, GFAR_RXB_TRUESIZE); 2948 } 2949 2950 /* try reuse page */ 2951 if (unlikely(page_count(page) != 1 || page_is_pfmemalloc(page))) 2952 return false; 2953 2954 /* change offset to the other half */ 2955 rxb->page_offset ^= GFAR_RXB_TRUESIZE; 2956 2957 page_ref_inc(page); 2958 2959 return true; 2960 } 2961 2962 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq, 2963 struct gfar_rx_buff *old_rxb) 2964 { 2965 struct gfar_rx_buff *new_rxb; 2966 u16 nta = rxq->next_to_alloc; 2967 2968 new_rxb = &rxq->rx_buff[nta]; 2969 2970 /* find next buf that can reuse a page */ 2971 nta++; 2972 rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0; 2973 2974 /* copy page reference */ 2975 *new_rxb = *old_rxb; 2976 2977 /* sync for use by the device */ 2978 dma_sync_single_range_for_device(rxq->dev, old_rxb->dma, 2979 old_rxb->page_offset, 2980 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE); 2981 } 2982 2983 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue, 2984 u32 lstatus, struct sk_buff *skb) 2985 { 2986 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean]; 2987 struct page *page = rxb->page; 2988 bool first = false; 2989 2990 if (likely(!skb)) { 2991 void *buff_addr = page_address(page) + rxb->page_offset; 2992 2993 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE); 2994 if (unlikely(!skb)) { 2995 gfar_rx_alloc_err(rx_queue); 2996 return NULL; 2997 } 2998 skb_reserve(skb, RXBUF_ALIGNMENT); 2999 first = true; 3000 } 3001 3002 dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset, 3003 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE); 3004 3005 if (gfar_add_rx_frag(rxb, lstatus, skb, first)) { 3006 /* reuse the free half of the page */ 3007 gfar_reuse_rx_page(rx_queue, rxb); 3008 } else { 3009 /* page cannot be reused, unmap it */ 3010 dma_unmap_page(rx_queue->dev, rxb->dma, 3011 PAGE_SIZE, DMA_FROM_DEVICE); 3012 } 3013 3014 /* clear rxb content */ 3015 rxb->page = NULL; 3016 3017 return skb; 3018 } 3019 3020 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) 3021 { 3022 /* If valid headers were found, and valid sums 3023 * were verified, then we tell the kernel that no 3024 * checksumming is necessary. Otherwise, it is [FIXME] 3025 */ 3026 if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) == 3027 (RXFCB_CIP | RXFCB_CTU)) 3028 skb->ip_summed = CHECKSUM_UNNECESSARY; 3029 else 3030 skb_checksum_none_assert(skb); 3031 } 3032 3033 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */ 3034 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb) 3035 { 3036 struct gfar_private *priv = netdev_priv(ndev); 3037 struct rxfcb *fcb = NULL; 3038 3039 /* fcb is at the beginning if exists */ 3040 fcb = (struct rxfcb *)skb->data; 3041 3042 /* Remove the FCB from the skb 3043 * Remove the padded bytes, if there are any 3044 */ 3045 if (priv->uses_rxfcb) 3046 skb_pull(skb, GMAC_FCB_LEN); 3047 3048 /* Get receive timestamp from the skb */ 3049 if (priv->hwts_rx_en) { 3050 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); 3051 u64 *ns = (u64 *) skb->data; 3052 3053 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 3054 shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns)); 3055 } 3056 3057 if (priv->padding) 3058 skb_pull(skb, priv->padding); 3059 3060 if (ndev->features & NETIF_F_RXCSUM) 3061 gfar_rx_checksum(skb, fcb); 3062 3063 /* Tell the skb what kind of packet this is */ 3064 skb->protocol = eth_type_trans(skb, ndev); 3065 3066 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here. 3067 * Even if vlan rx accel is disabled, on some chips 3068 * RXFCB_VLN is pseudo randomly set. 3069 */ 3070 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX && 3071 be16_to_cpu(fcb->flags) & RXFCB_VLN) 3072 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 3073 be16_to_cpu(fcb->vlctl)); 3074 } 3075 3076 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring 3077 * until the budget/quota has been reached. Returns the number 3078 * of frames handled 3079 */ 3080 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit) 3081 { 3082 struct net_device *ndev = rx_queue->ndev; 3083 struct gfar_private *priv = netdev_priv(ndev); 3084 struct rxbd8 *bdp; 3085 int i, howmany = 0; 3086 struct sk_buff *skb = rx_queue->skb; 3087 int cleaned_cnt = gfar_rxbd_unused(rx_queue); 3088 unsigned int total_bytes = 0, total_pkts = 0; 3089 3090 /* Get the first full descriptor */ 3091 i = rx_queue->next_to_clean; 3092 3093 while (rx_work_limit--) { 3094 u32 lstatus; 3095 3096 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) { 3097 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt); 3098 cleaned_cnt = 0; 3099 } 3100 3101 bdp = &rx_queue->rx_bd_base[i]; 3102 lstatus = be32_to_cpu(bdp->lstatus); 3103 if (lstatus & BD_LFLAG(RXBD_EMPTY)) 3104 break; 3105 3106 /* order rx buffer descriptor reads */ 3107 rmb(); 3108 3109 /* fetch next to clean buffer from the ring */ 3110 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb); 3111 if (unlikely(!skb)) 3112 break; 3113 3114 cleaned_cnt++; 3115 howmany++; 3116 3117 if (unlikely(++i == rx_queue->rx_ring_size)) 3118 i = 0; 3119 3120 rx_queue->next_to_clean = i; 3121 3122 /* fetch next buffer if not the last in frame */ 3123 if (!(lstatus & BD_LFLAG(RXBD_LAST))) 3124 continue; 3125 3126 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) { 3127 count_errors(lstatus, ndev); 3128 3129 /* discard faulty buffer */ 3130 dev_kfree_skb(skb); 3131 skb = NULL; 3132 rx_queue->stats.rx_dropped++; 3133 continue; 3134 } 3135 3136 /* Increment the number of packets */ 3137 total_pkts++; 3138 total_bytes += skb->len; 3139 3140 skb_record_rx_queue(skb, rx_queue->qindex); 3141 3142 gfar_process_frame(ndev, skb); 3143 3144 /* Send the packet up the stack */ 3145 napi_gro_receive(&rx_queue->grp->napi_rx, skb); 3146 3147 skb = NULL; 3148 } 3149 3150 /* Store incomplete frames for completion */ 3151 rx_queue->skb = skb; 3152 3153 rx_queue->stats.rx_packets += total_pkts; 3154 rx_queue->stats.rx_bytes += total_bytes; 3155 3156 if (cleaned_cnt) 3157 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt); 3158 3159 /* Update Last Free RxBD pointer for LFC */ 3160 if (unlikely(priv->tx_actual_en)) { 3161 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue); 3162 3163 gfar_write(rx_queue->rfbptr, bdp_dma); 3164 } 3165 3166 return howmany; 3167 } 3168 3169 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget) 3170 { 3171 struct gfar_priv_grp *gfargrp = 3172 container_of(napi, struct gfar_priv_grp, napi_rx); 3173 struct gfar __iomem *regs = gfargrp->regs; 3174 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue; 3175 int work_done = 0; 3176 3177 /* Clear IEVENT, so interrupts aren't called again 3178 * because of the packets that have already arrived 3179 */ 3180 gfar_write(®s->ievent, IEVENT_RX_MASK); 3181 3182 work_done = gfar_clean_rx_ring(rx_queue, budget); 3183 3184 if (work_done < budget) { 3185 u32 imask; 3186 napi_complete_done(napi, work_done); 3187 /* Clear the halt bit in RSTAT */ 3188 gfar_write(®s->rstat, gfargrp->rstat); 3189 3190 spin_lock_irq(&gfargrp->grplock); 3191 imask = gfar_read(®s->imask); 3192 imask |= IMASK_RX_DEFAULT; 3193 gfar_write(®s->imask, imask); 3194 spin_unlock_irq(&gfargrp->grplock); 3195 } 3196 3197 return work_done; 3198 } 3199 3200 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget) 3201 { 3202 struct gfar_priv_grp *gfargrp = 3203 container_of(napi, struct gfar_priv_grp, napi_tx); 3204 struct gfar __iomem *regs = gfargrp->regs; 3205 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue; 3206 u32 imask; 3207 3208 /* Clear IEVENT, so interrupts aren't called again 3209 * because of the packets that have already arrived 3210 */ 3211 gfar_write(®s->ievent, IEVENT_TX_MASK); 3212 3213 /* run Tx cleanup to completion */ 3214 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) 3215 gfar_clean_tx_ring(tx_queue); 3216 3217 napi_complete(napi); 3218 3219 spin_lock_irq(&gfargrp->grplock); 3220 imask = gfar_read(®s->imask); 3221 imask |= IMASK_TX_DEFAULT; 3222 gfar_write(®s->imask, imask); 3223 spin_unlock_irq(&gfargrp->grplock); 3224 3225 return 0; 3226 } 3227 3228 static int gfar_poll_rx(struct napi_struct *napi, int budget) 3229 { 3230 struct gfar_priv_grp *gfargrp = 3231 container_of(napi, struct gfar_priv_grp, napi_rx); 3232 struct gfar_private *priv = gfargrp->priv; 3233 struct gfar __iomem *regs = gfargrp->regs; 3234 struct gfar_priv_rx_q *rx_queue = NULL; 3235 int work_done = 0, work_done_per_q = 0; 3236 int i, budget_per_q = 0; 3237 unsigned long rstat_rxf; 3238 int num_act_queues; 3239 3240 /* Clear IEVENT, so interrupts aren't called again 3241 * because of the packets that have already arrived 3242 */ 3243 gfar_write(®s->ievent, IEVENT_RX_MASK); 3244 3245 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK; 3246 3247 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS); 3248 if (num_act_queues) 3249 budget_per_q = budget/num_act_queues; 3250 3251 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { 3252 /* skip queue if not active */ 3253 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i))) 3254 continue; 3255 3256 rx_queue = priv->rx_queue[i]; 3257 work_done_per_q = 3258 gfar_clean_rx_ring(rx_queue, budget_per_q); 3259 work_done += work_done_per_q; 3260 3261 /* finished processing this queue */ 3262 if (work_done_per_q < budget_per_q) { 3263 /* clear active queue hw indication */ 3264 gfar_write(®s->rstat, 3265 RSTAT_CLEAR_RXF0 >> i); 3266 num_act_queues--; 3267 3268 if (!num_act_queues) 3269 break; 3270 } 3271 } 3272 3273 if (!num_act_queues) { 3274 u32 imask; 3275 napi_complete_done(napi, work_done); 3276 3277 /* Clear the halt bit in RSTAT */ 3278 gfar_write(®s->rstat, gfargrp->rstat); 3279 3280 spin_lock_irq(&gfargrp->grplock); 3281 imask = gfar_read(®s->imask); 3282 imask |= IMASK_RX_DEFAULT; 3283 gfar_write(®s->imask, imask); 3284 spin_unlock_irq(&gfargrp->grplock); 3285 } 3286 3287 return work_done; 3288 } 3289 3290 static int gfar_poll_tx(struct napi_struct *napi, int budget) 3291 { 3292 struct gfar_priv_grp *gfargrp = 3293 container_of(napi, struct gfar_priv_grp, napi_tx); 3294 struct gfar_private *priv = gfargrp->priv; 3295 struct gfar __iomem *regs = gfargrp->regs; 3296 struct gfar_priv_tx_q *tx_queue = NULL; 3297 int has_tx_work = 0; 3298 int i; 3299 3300 /* Clear IEVENT, so interrupts aren't called again 3301 * because of the packets that have already arrived 3302 */ 3303 gfar_write(®s->ievent, IEVENT_TX_MASK); 3304 3305 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) { 3306 tx_queue = priv->tx_queue[i]; 3307 /* run Tx cleanup to completion */ 3308 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) { 3309 gfar_clean_tx_ring(tx_queue); 3310 has_tx_work = 1; 3311 } 3312 } 3313 3314 if (!has_tx_work) { 3315 u32 imask; 3316 napi_complete(napi); 3317 3318 spin_lock_irq(&gfargrp->grplock); 3319 imask = gfar_read(®s->imask); 3320 imask |= IMASK_TX_DEFAULT; 3321 gfar_write(®s->imask, imask); 3322 spin_unlock_irq(&gfargrp->grplock); 3323 } 3324 3325 return 0; 3326 } 3327 3328 3329 #ifdef CONFIG_NET_POLL_CONTROLLER 3330 /* Polling 'interrupt' - used by things like netconsole to send skbs 3331 * without having to re-enable interrupts. It's not called while 3332 * the interrupt routine is executing. 3333 */ 3334 static void gfar_netpoll(struct net_device *dev) 3335 { 3336 struct gfar_private *priv = netdev_priv(dev); 3337 int i; 3338 3339 /* If the device has multiple interrupts, run tx/rx */ 3340 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 3341 for (i = 0; i < priv->num_grps; i++) { 3342 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 3343 3344 disable_irq(gfar_irq(grp, TX)->irq); 3345 disable_irq(gfar_irq(grp, RX)->irq); 3346 disable_irq(gfar_irq(grp, ER)->irq); 3347 gfar_interrupt(gfar_irq(grp, TX)->irq, grp); 3348 enable_irq(gfar_irq(grp, ER)->irq); 3349 enable_irq(gfar_irq(grp, RX)->irq); 3350 enable_irq(gfar_irq(grp, TX)->irq); 3351 } 3352 } else { 3353 for (i = 0; i < priv->num_grps; i++) { 3354 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 3355 3356 disable_irq(gfar_irq(grp, TX)->irq); 3357 gfar_interrupt(gfar_irq(grp, TX)->irq, grp); 3358 enable_irq(gfar_irq(grp, TX)->irq); 3359 } 3360 } 3361 } 3362 #endif 3363 3364 /* The interrupt handler for devices with one interrupt */ 3365 static irqreturn_t gfar_interrupt(int irq, void *grp_id) 3366 { 3367 struct gfar_priv_grp *gfargrp = grp_id; 3368 3369 /* Save ievent for future reference */ 3370 u32 events = gfar_read(&gfargrp->regs->ievent); 3371 3372 /* Check for reception */ 3373 if (events & IEVENT_RX_MASK) 3374 gfar_receive(irq, grp_id); 3375 3376 /* Check for transmit completion */ 3377 if (events & IEVENT_TX_MASK) 3378 gfar_transmit(irq, grp_id); 3379 3380 /* Check for errors */ 3381 if (events & IEVENT_ERR_MASK) 3382 gfar_error(irq, grp_id); 3383 3384 return IRQ_HANDLED; 3385 } 3386 3387 /* Called every time the controller might need to be made 3388 * aware of new link state. The PHY code conveys this 3389 * information through variables in the phydev structure, and this 3390 * function converts those variables into the appropriate 3391 * register values, and can bring down the device if needed. 3392 */ 3393 static void adjust_link(struct net_device *dev) 3394 { 3395 struct gfar_private *priv = netdev_priv(dev); 3396 struct phy_device *phydev = dev->phydev; 3397 3398 if (unlikely(phydev->link != priv->oldlink || 3399 (phydev->link && (phydev->duplex != priv->oldduplex || 3400 phydev->speed != priv->oldspeed)))) 3401 gfar_update_link_state(priv); 3402 } 3403 3404 /* Update the hash table based on the current list of multicast 3405 * addresses we subscribe to. Also, change the promiscuity of 3406 * the device based on the flags (this function is called 3407 * whenever dev->flags is changed 3408 */ 3409 static void gfar_set_multi(struct net_device *dev) 3410 { 3411 struct netdev_hw_addr *ha; 3412 struct gfar_private *priv = netdev_priv(dev); 3413 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3414 u32 tempval; 3415 3416 if (dev->flags & IFF_PROMISC) { 3417 /* Set RCTRL to PROM */ 3418 tempval = gfar_read(®s->rctrl); 3419 tempval |= RCTRL_PROM; 3420 gfar_write(®s->rctrl, tempval); 3421 } else { 3422 /* Set RCTRL to not PROM */ 3423 tempval = gfar_read(®s->rctrl); 3424 tempval &= ~(RCTRL_PROM); 3425 gfar_write(®s->rctrl, tempval); 3426 } 3427 3428 if (dev->flags & IFF_ALLMULTI) { 3429 /* Set the hash to rx all multicast frames */ 3430 gfar_write(®s->igaddr0, 0xffffffff); 3431 gfar_write(®s->igaddr1, 0xffffffff); 3432 gfar_write(®s->igaddr2, 0xffffffff); 3433 gfar_write(®s->igaddr3, 0xffffffff); 3434 gfar_write(®s->igaddr4, 0xffffffff); 3435 gfar_write(®s->igaddr5, 0xffffffff); 3436 gfar_write(®s->igaddr6, 0xffffffff); 3437 gfar_write(®s->igaddr7, 0xffffffff); 3438 gfar_write(®s->gaddr0, 0xffffffff); 3439 gfar_write(®s->gaddr1, 0xffffffff); 3440 gfar_write(®s->gaddr2, 0xffffffff); 3441 gfar_write(®s->gaddr3, 0xffffffff); 3442 gfar_write(®s->gaddr4, 0xffffffff); 3443 gfar_write(®s->gaddr5, 0xffffffff); 3444 gfar_write(®s->gaddr6, 0xffffffff); 3445 gfar_write(®s->gaddr7, 0xffffffff); 3446 } else { 3447 int em_num; 3448 int idx; 3449 3450 /* zero out the hash */ 3451 gfar_write(®s->igaddr0, 0x0); 3452 gfar_write(®s->igaddr1, 0x0); 3453 gfar_write(®s->igaddr2, 0x0); 3454 gfar_write(®s->igaddr3, 0x0); 3455 gfar_write(®s->igaddr4, 0x0); 3456 gfar_write(®s->igaddr5, 0x0); 3457 gfar_write(®s->igaddr6, 0x0); 3458 gfar_write(®s->igaddr7, 0x0); 3459 gfar_write(®s->gaddr0, 0x0); 3460 gfar_write(®s->gaddr1, 0x0); 3461 gfar_write(®s->gaddr2, 0x0); 3462 gfar_write(®s->gaddr3, 0x0); 3463 gfar_write(®s->gaddr4, 0x0); 3464 gfar_write(®s->gaddr5, 0x0); 3465 gfar_write(®s->gaddr6, 0x0); 3466 gfar_write(®s->gaddr7, 0x0); 3467 3468 /* If we have extended hash tables, we need to 3469 * clear the exact match registers to prepare for 3470 * setting them 3471 */ 3472 if (priv->extended_hash) { 3473 em_num = GFAR_EM_NUM + 1; 3474 gfar_clear_exact_match(dev); 3475 idx = 1; 3476 } else { 3477 idx = 0; 3478 em_num = 0; 3479 } 3480 3481 if (netdev_mc_empty(dev)) 3482 return; 3483 3484 /* Parse the list, and set the appropriate bits */ 3485 netdev_for_each_mc_addr(ha, dev) { 3486 if (idx < em_num) { 3487 gfar_set_mac_for_addr(dev, idx, ha->addr); 3488 idx++; 3489 } else 3490 gfar_set_hash_for_addr(dev, ha->addr); 3491 } 3492 } 3493 } 3494 3495 3496 /* Clears each of the exact match registers to zero, so they 3497 * don't interfere with normal reception 3498 */ 3499 static void gfar_clear_exact_match(struct net_device *dev) 3500 { 3501 int idx; 3502 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; 3503 3504 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++) 3505 gfar_set_mac_for_addr(dev, idx, zero_arr); 3506 } 3507 3508 /* Set the appropriate hash bit for the given addr */ 3509 /* The algorithm works like so: 3510 * 1) Take the Destination Address (ie the multicast address), and 3511 * do a CRC on it (little endian), and reverse the bits of the 3512 * result. 3513 * 2) Use the 8 most significant bits as a hash into a 256-entry 3514 * table. The table is controlled through 8 32-bit registers: 3515 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 3516 * gaddr7. This means that the 3 most significant bits in the 3517 * hash index which gaddr register to use, and the 5 other bits 3518 * indicate which bit (assuming an IBM numbering scheme, which 3519 * for PowerPC (tm) is usually the case) in the register holds 3520 * the entry. 3521 */ 3522 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) 3523 { 3524 u32 tempval; 3525 struct gfar_private *priv = netdev_priv(dev); 3526 u32 result = ether_crc(ETH_ALEN, addr); 3527 int width = priv->hash_width; 3528 u8 whichbit = (result >> (32 - width)) & 0x1f; 3529 u8 whichreg = result >> (32 - width + 5); 3530 u32 value = (1 << (31-whichbit)); 3531 3532 tempval = gfar_read(priv->hash_regs[whichreg]); 3533 tempval |= value; 3534 gfar_write(priv->hash_regs[whichreg], tempval); 3535 } 3536 3537 3538 /* There are multiple MAC Address register pairs on some controllers 3539 * This function sets the numth pair to a given address 3540 */ 3541 static void gfar_set_mac_for_addr(struct net_device *dev, int num, 3542 const u8 *addr) 3543 { 3544 struct gfar_private *priv = netdev_priv(dev); 3545 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3546 u32 tempval; 3547 u32 __iomem *macptr = ®s->macstnaddr1; 3548 3549 macptr += num*2; 3550 3551 /* For a station address of 0x12345678ABCD in transmission 3552 * order (BE), MACnADDR1 is set to 0xCDAB7856 and 3553 * MACnADDR2 is set to 0x34120000. 3554 */ 3555 tempval = (addr[5] << 24) | (addr[4] << 16) | 3556 (addr[3] << 8) | addr[2]; 3557 3558 gfar_write(macptr, tempval); 3559 3560 tempval = (addr[1] << 24) | (addr[0] << 16); 3561 3562 gfar_write(macptr+1, tempval); 3563 } 3564 3565 /* GFAR error interrupt handler */ 3566 static irqreturn_t gfar_error(int irq, void *grp_id) 3567 { 3568 struct gfar_priv_grp *gfargrp = grp_id; 3569 struct gfar __iomem *regs = gfargrp->regs; 3570 struct gfar_private *priv= gfargrp->priv; 3571 struct net_device *dev = priv->ndev; 3572 3573 /* Save ievent for future reference */ 3574 u32 events = gfar_read(®s->ievent); 3575 3576 /* Clear IEVENT */ 3577 gfar_write(®s->ievent, events & IEVENT_ERR_MASK); 3578 3579 /* Magic Packet is not an error. */ 3580 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && 3581 (events & IEVENT_MAG)) 3582 events &= ~IEVENT_MAG; 3583 3584 /* Hmm... */ 3585 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) 3586 netdev_dbg(dev, 3587 "error interrupt (ievent=0x%08x imask=0x%08x)\n", 3588 events, gfar_read(®s->imask)); 3589 3590 /* Update the error counters */ 3591 if (events & IEVENT_TXE) { 3592 dev->stats.tx_errors++; 3593 3594 if (events & IEVENT_LC) 3595 dev->stats.tx_window_errors++; 3596 if (events & IEVENT_CRL) 3597 dev->stats.tx_aborted_errors++; 3598 if (events & IEVENT_XFUN) { 3599 netif_dbg(priv, tx_err, dev, 3600 "TX FIFO underrun, packet dropped\n"); 3601 dev->stats.tx_dropped++; 3602 atomic64_inc(&priv->extra_stats.tx_underrun); 3603 3604 schedule_work(&priv->reset_task); 3605 } 3606 netif_dbg(priv, tx_err, dev, "Transmit Error\n"); 3607 } 3608 if (events & IEVENT_BSY) { 3609 dev->stats.rx_over_errors++; 3610 atomic64_inc(&priv->extra_stats.rx_bsy); 3611 3612 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n", 3613 gfar_read(®s->rstat)); 3614 } 3615 if (events & IEVENT_BABR) { 3616 dev->stats.rx_errors++; 3617 atomic64_inc(&priv->extra_stats.rx_babr); 3618 3619 netif_dbg(priv, rx_err, dev, "babbling RX error\n"); 3620 } 3621 if (events & IEVENT_EBERR) { 3622 atomic64_inc(&priv->extra_stats.eberr); 3623 netif_dbg(priv, rx_err, dev, "bus error\n"); 3624 } 3625 if (events & IEVENT_RXC) 3626 netif_dbg(priv, rx_status, dev, "control frame\n"); 3627 3628 if (events & IEVENT_BABT) { 3629 atomic64_inc(&priv->extra_stats.tx_babt); 3630 netif_dbg(priv, tx_err, dev, "babbling TX error\n"); 3631 } 3632 return IRQ_HANDLED; 3633 } 3634 3635 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv) 3636 { 3637 struct net_device *ndev = priv->ndev; 3638 struct phy_device *phydev = ndev->phydev; 3639 u32 val = 0; 3640 3641 if (!phydev->duplex) 3642 return val; 3643 3644 if (!priv->pause_aneg_en) { 3645 if (priv->tx_pause_en) 3646 val |= MACCFG1_TX_FLOW; 3647 if (priv->rx_pause_en) 3648 val |= MACCFG1_RX_FLOW; 3649 } else { 3650 u16 lcl_adv, rmt_adv; 3651 u8 flowctrl; 3652 /* get link partner capabilities */ 3653 rmt_adv = 0; 3654 if (phydev->pause) 3655 rmt_adv = LPA_PAUSE_CAP; 3656 if (phydev->asym_pause) 3657 rmt_adv |= LPA_PAUSE_ASYM; 3658 3659 lcl_adv = 0; 3660 if (phydev->advertising & ADVERTISED_Pause) 3661 lcl_adv |= ADVERTISE_PAUSE_CAP; 3662 if (phydev->advertising & ADVERTISED_Asym_Pause) 3663 lcl_adv |= ADVERTISE_PAUSE_ASYM; 3664 3665 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 3666 if (flowctrl & FLOW_CTRL_TX) 3667 val |= MACCFG1_TX_FLOW; 3668 if (flowctrl & FLOW_CTRL_RX) 3669 val |= MACCFG1_RX_FLOW; 3670 } 3671 3672 return val; 3673 } 3674 3675 static noinline void gfar_update_link_state(struct gfar_private *priv) 3676 { 3677 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3678 struct net_device *ndev = priv->ndev; 3679 struct phy_device *phydev = ndev->phydev; 3680 struct gfar_priv_rx_q *rx_queue = NULL; 3681 int i; 3682 3683 if (unlikely(test_bit(GFAR_RESETTING, &priv->state))) 3684 return; 3685 3686 if (phydev->link) { 3687 u32 tempval1 = gfar_read(®s->maccfg1); 3688 u32 tempval = gfar_read(®s->maccfg2); 3689 u32 ecntrl = gfar_read(®s->ecntrl); 3690 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW); 3691 3692 if (phydev->duplex != priv->oldduplex) { 3693 if (!(phydev->duplex)) 3694 tempval &= ~(MACCFG2_FULL_DUPLEX); 3695 else 3696 tempval |= MACCFG2_FULL_DUPLEX; 3697 3698 priv->oldduplex = phydev->duplex; 3699 } 3700 3701 if (phydev->speed != priv->oldspeed) { 3702 switch (phydev->speed) { 3703 case 1000: 3704 tempval = 3705 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); 3706 3707 ecntrl &= ~(ECNTRL_R100); 3708 break; 3709 case 100: 3710 case 10: 3711 tempval = 3712 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); 3713 3714 /* Reduced mode distinguishes 3715 * between 10 and 100 3716 */ 3717 if (phydev->speed == SPEED_100) 3718 ecntrl |= ECNTRL_R100; 3719 else 3720 ecntrl &= ~(ECNTRL_R100); 3721 break; 3722 default: 3723 netif_warn(priv, link, priv->ndev, 3724 "Ack! Speed (%d) is not 10/100/1000!\n", 3725 phydev->speed); 3726 break; 3727 } 3728 3729 priv->oldspeed = phydev->speed; 3730 } 3731 3732 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); 3733 tempval1 |= gfar_get_flowctrl_cfg(priv); 3734 3735 /* Turn last free buffer recording on */ 3736 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) { 3737 for (i = 0; i < priv->num_rx_queues; i++) { 3738 u32 bdp_dma; 3739 3740 rx_queue = priv->rx_queue[i]; 3741 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue); 3742 gfar_write(rx_queue->rfbptr, bdp_dma); 3743 } 3744 3745 priv->tx_actual_en = 1; 3746 } 3747 3748 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval)) 3749 priv->tx_actual_en = 0; 3750 3751 gfar_write(®s->maccfg1, tempval1); 3752 gfar_write(®s->maccfg2, tempval); 3753 gfar_write(®s->ecntrl, ecntrl); 3754 3755 if (!priv->oldlink) 3756 priv->oldlink = 1; 3757 3758 } else if (priv->oldlink) { 3759 priv->oldlink = 0; 3760 priv->oldspeed = 0; 3761 priv->oldduplex = -1; 3762 } 3763 3764 if (netif_msg_link(priv)) 3765 phy_print_status(phydev); 3766 } 3767 3768 static const struct of_device_id gfar_match[] = 3769 { 3770 { 3771 .type = "network", 3772 .compatible = "gianfar", 3773 }, 3774 { 3775 .compatible = "fsl,etsec2", 3776 }, 3777 {}, 3778 }; 3779 MODULE_DEVICE_TABLE(of, gfar_match); 3780 3781 /* Structure for a device driver */ 3782 static struct platform_driver gfar_driver = { 3783 .driver = { 3784 .name = "fsl-gianfar", 3785 .pm = GFAR_PM_OPS, 3786 .of_match_table = gfar_match, 3787 }, 3788 .probe = gfar_probe, 3789 .remove = gfar_remove, 3790 }; 3791 3792 module_platform_driver(gfar_driver); 3793