1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* drivers/net/ethernet/freescale/gianfar.c 3 * 4 * Gianfar Ethernet Driver 5 * This driver is designed for the non-CPM ethernet controllers 6 * on the 85xx and 83xx family of integrated processors 7 * Based on 8260_io/fcc_enet.c 8 * 9 * Author: Andy Fleming 10 * Maintainer: Kumar Gala 11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 12 * 13 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc. 14 * Copyright 2007 MontaVista Software, Inc. 15 * 16 * Gianfar: AKA Lambda Draconis, "Dragon" 17 * RA 11 31 24.2 18 * Dec +69 19 52 19 * V 3.84 20 * B-V +1.62 21 * 22 * Theory of operation 23 * 24 * The driver is initialized through of_device. Configuration information 25 * is therefore conveyed through an OF-style device tree. 26 * 27 * The Gianfar Ethernet Controller uses a ring of buffer 28 * descriptors. The beginning is indicated by a register 29 * pointing to the physical address of the start of the ring. 30 * The end is determined by a "wrap" bit being set in the 31 * last descriptor of the ring. 32 * 33 * When a packet is received, the RXF bit in the 34 * IEVENT register is set, triggering an interrupt when the 35 * corresponding bit in the IMASK register is also set (if 36 * interrupt coalescing is active, then the interrupt may not 37 * happen immediately, but will wait until either a set number 38 * of frames or amount of time have passed). In NAPI, the 39 * interrupt handler will signal there is work to be done, and 40 * exit. This method will start at the last known empty 41 * descriptor, and process every subsequent descriptor until there 42 * are none left with data (NAPI will stop after a set number of 43 * packets to give time to other tasks, but will eventually 44 * process all the packets). The data arrives inside a 45 * pre-allocated skb, and so after the skb is passed up to the 46 * stack, a new skb must be allocated, and the address field in 47 * the buffer descriptor must be updated to indicate this new 48 * skb. 49 * 50 * When the kernel requests that a packet be transmitted, the 51 * driver starts where it left off last time, and points the 52 * descriptor at the buffer which was passed in. The driver 53 * then informs the DMA engine that there are packets ready to 54 * be transmitted. Once the controller is finished transmitting 55 * the packet, an interrupt may be triggered (under the same 56 * conditions as for reception, but depending on the TXF bit). 57 * The driver then cleans up the buffer. 58 */ 59 60 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 61 #define DEBUG 62 63 #include <linux/kernel.h> 64 #include <linux/string.h> 65 #include <linux/errno.h> 66 #include <linux/unistd.h> 67 #include <linux/slab.h> 68 #include <linux/interrupt.h> 69 #include <linux/delay.h> 70 #include <linux/netdevice.h> 71 #include <linux/etherdevice.h> 72 #include <linux/skbuff.h> 73 #include <linux/if_vlan.h> 74 #include <linux/spinlock.h> 75 #include <linux/mm.h> 76 #include <linux/of_address.h> 77 #include <linux/of_irq.h> 78 #include <linux/of_mdio.h> 79 #include <linux/of_platform.h> 80 #include <linux/ip.h> 81 #include <linux/tcp.h> 82 #include <linux/udp.h> 83 #include <linux/in.h> 84 #include <linux/net_tstamp.h> 85 86 #include <asm/io.h> 87 #ifdef CONFIG_PPC 88 #include <asm/reg.h> 89 #include <asm/mpc85xx.h> 90 #endif 91 #include <asm/irq.h> 92 #include <linux/uaccess.h> 93 #include <linux/module.h> 94 #include <linux/dma-mapping.h> 95 #include <linux/crc32.h> 96 #include <linux/mii.h> 97 #include <linux/phy.h> 98 #include <linux/phy_fixed.h> 99 #include <linux/of.h> 100 #include <linux/of_net.h> 101 102 #include "gianfar.h" 103 104 #define TX_TIMEOUT (5*HZ) 105 106 const char gfar_driver_version[] = "2.0"; 107 108 MODULE_AUTHOR("Freescale Semiconductor, Inc"); 109 MODULE_DESCRIPTION("Gianfar Ethernet Driver"); 110 MODULE_LICENSE("GPL"); 111 112 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, 113 dma_addr_t buf) 114 { 115 u32 lstatus; 116 117 bdp->bufPtr = cpu_to_be32(buf); 118 119 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); 120 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) 121 lstatus |= BD_LFLAG(RXBD_WRAP); 122 123 gfar_wmb(); 124 125 bdp->lstatus = cpu_to_be32(lstatus); 126 } 127 128 static void gfar_init_tx_rx_base(struct gfar_private *priv) 129 { 130 struct gfar __iomem *regs = priv->gfargrp[0].regs; 131 u32 __iomem *baddr; 132 int i; 133 134 baddr = ®s->tbase0; 135 for (i = 0; i < priv->num_tx_queues; i++) { 136 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); 137 baddr += 2; 138 } 139 140 baddr = ®s->rbase0; 141 for (i = 0; i < priv->num_rx_queues; i++) { 142 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); 143 baddr += 2; 144 } 145 } 146 147 static void gfar_init_rqprm(struct gfar_private *priv) 148 { 149 struct gfar __iomem *regs = priv->gfargrp[0].regs; 150 u32 __iomem *baddr; 151 int i; 152 153 baddr = ®s->rqprm0; 154 for (i = 0; i < priv->num_rx_queues; i++) { 155 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size | 156 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT)); 157 baddr++; 158 } 159 } 160 161 static void gfar_rx_offload_en(struct gfar_private *priv) 162 { 163 /* set this when rx hw offload (TOE) functions are being used */ 164 priv->uses_rxfcb = 0; 165 166 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) 167 priv->uses_rxfcb = 1; 168 169 if (priv->hwts_rx_en || priv->rx_filer_enable) 170 priv->uses_rxfcb = 1; 171 } 172 173 static void gfar_mac_rx_config(struct gfar_private *priv) 174 { 175 struct gfar __iomem *regs = priv->gfargrp[0].regs; 176 u32 rctrl = 0; 177 178 if (priv->rx_filer_enable) { 179 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT; 180 /* Program the RIR0 reg with the required distribution */ 181 if (priv->poll_mode == GFAR_SQ_POLLING) 182 gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0); 183 else /* GFAR_MQ_POLLING */ 184 gfar_write(®s->rir0, DEFAULT_8RXQ_RIR0); 185 } 186 187 /* Restore PROMISC mode */ 188 if (priv->ndev->flags & IFF_PROMISC) 189 rctrl |= RCTRL_PROM; 190 191 if (priv->ndev->features & NETIF_F_RXCSUM) 192 rctrl |= RCTRL_CHECKSUMMING; 193 194 if (priv->extended_hash) 195 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN; 196 197 if (priv->padding) { 198 rctrl &= ~RCTRL_PAL_MASK; 199 rctrl |= RCTRL_PADDING(priv->padding); 200 } 201 202 /* Enable HW time stamping if requested from user space */ 203 if (priv->hwts_rx_en) 204 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; 205 206 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) 207 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; 208 209 /* Clear the LFC bit */ 210 gfar_write(®s->rctrl, rctrl); 211 /* Init flow control threshold values */ 212 gfar_init_rqprm(priv); 213 gfar_write(®s->ptv, DEFAULT_LFC_PTVVAL); 214 rctrl |= RCTRL_LFC; 215 216 /* Init rctrl based on our settings */ 217 gfar_write(®s->rctrl, rctrl); 218 } 219 220 static void gfar_mac_tx_config(struct gfar_private *priv) 221 { 222 struct gfar __iomem *regs = priv->gfargrp[0].regs; 223 u32 tctrl = 0; 224 225 if (priv->ndev->features & NETIF_F_IP_CSUM) 226 tctrl |= TCTRL_INIT_CSUM; 227 228 if (priv->prio_sched_en) 229 tctrl |= TCTRL_TXSCHED_PRIO; 230 else { 231 tctrl |= TCTRL_TXSCHED_WRRS; 232 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT); 233 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT); 234 } 235 236 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX) 237 tctrl |= TCTRL_VLINS; 238 239 gfar_write(®s->tctrl, tctrl); 240 } 241 242 static void gfar_configure_coalescing(struct gfar_private *priv, 243 unsigned long tx_mask, unsigned long rx_mask) 244 { 245 struct gfar __iomem *regs = priv->gfargrp[0].regs; 246 u32 __iomem *baddr; 247 248 if (priv->mode == MQ_MG_MODE) { 249 int i = 0; 250 251 baddr = ®s->txic0; 252 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { 253 gfar_write(baddr + i, 0); 254 if (likely(priv->tx_queue[i]->txcoalescing)) 255 gfar_write(baddr + i, priv->tx_queue[i]->txic); 256 } 257 258 baddr = ®s->rxic0; 259 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { 260 gfar_write(baddr + i, 0); 261 if (likely(priv->rx_queue[i]->rxcoalescing)) 262 gfar_write(baddr + i, priv->rx_queue[i]->rxic); 263 } 264 } else { 265 /* Backward compatible case -- even if we enable 266 * multiple queues, there's only single reg to program 267 */ 268 gfar_write(®s->txic, 0); 269 if (likely(priv->tx_queue[0]->txcoalescing)) 270 gfar_write(®s->txic, priv->tx_queue[0]->txic); 271 272 gfar_write(®s->rxic, 0); 273 if (unlikely(priv->rx_queue[0]->rxcoalescing)) 274 gfar_write(®s->rxic, priv->rx_queue[0]->rxic); 275 } 276 } 277 278 static void gfar_configure_coalescing_all(struct gfar_private *priv) 279 { 280 gfar_configure_coalescing(priv, 0xFF, 0xFF); 281 } 282 283 static struct net_device_stats *gfar_get_stats(struct net_device *dev) 284 { 285 struct gfar_private *priv = netdev_priv(dev); 286 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; 287 unsigned long tx_packets = 0, tx_bytes = 0; 288 int i; 289 290 for (i = 0; i < priv->num_rx_queues; i++) { 291 rx_packets += priv->rx_queue[i]->stats.rx_packets; 292 rx_bytes += priv->rx_queue[i]->stats.rx_bytes; 293 rx_dropped += priv->rx_queue[i]->stats.rx_dropped; 294 } 295 296 dev->stats.rx_packets = rx_packets; 297 dev->stats.rx_bytes = rx_bytes; 298 dev->stats.rx_dropped = rx_dropped; 299 300 for (i = 0; i < priv->num_tx_queues; i++) { 301 tx_bytes += priv->tx_queue[i]->stats.tx_bytes; 302 tx_packets += priv->tx_queue[i]->stats.tx_packets; 303 } 304 305 dev->stats.tx_bytes = tx_bytes; 306 dev->stats.tx_packets = tx_packets; 307 308 return &dev->stats; 309 } 310 311 /* Set the appropriate hash bit for the given addr */ 312 /* The algorithm works like so: 313 * 1) Take the Destination Address (ie the multicast address), and 314 * do a CRC on it (little endian), and reverse the bits of the 315 * result. 316 * 2) Use the 8 most significant bits as a hash into a 256-entry 317 * table. The table is controlled through 8 32-bit registers: 318 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 319 * gaddr7. This means that the 3 most significant bits in the 320 * hash index which gaddr register to use, and the 5 other bits 321 * indicate which bit (assuming an IBM numbering scheme, which 322 * for PowerPC (tm) is usually the case) in the register holds 323 * the entry. 324 */ 325 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) 326 { 327 u32 tempval; 328 struct gfar_private *priv = netdev_priv(dev); 329 u32 result = ether_crc(ETH_ALEN, addr); 330 int width = priv->hash_width; 331 u8 whichbit = (result >> (32 - width)) & 0x1f; 332 u8 whichreg = result >> (32 - width + 5); 333 u32 value = (1 << (31-whichbit)); 334 335 tempval = gfar_read(priv->hash_regs[whichreg]); 336 tempval |= value; 337 gfar_write(priv->hash_regs[whichreg], tempval); 338 } 339 340 /* There are multiple MAC Address register pairs on some controllers 341 * This function sets the numth pair to a given address 342 */ 343 static void gfar_set_mac_for_addr(struct net_device *dev, int num, 344 const u8 *addr) 345 { 346 struct gfar_private *priv = netdev_priv(dev); 347 struct gfar __iomem *regs = priv->gfargrp[0].regs; 348 u32 tempval; 349 u32 __iomem *macptr = ®s->macstnaddr1; 350 351 macptr += num*2; 352 353 /* For a station address of 0x12345678ABCD in transmission 354 * order (BE), MACnADDR1 is set to 0xCDAB7856 and 355 * MACnADDR2 is set to 0x34120000. 356 */ 357 tempval = (addr[5] << 24) | (addr[4] << 16) | 358 (addr[3] << 8) | addr[2]; 359 360 gfar_write(macptr, tempval); 361 362 tempval = (addr[1] << 24) | (addr[0] << 16); 363 364 gfar_write(macptr+1, tempval); 365 } 366 367 static int gfar_set_mac_addr(struct net_device *dev, void *p) 368 { 369 eth_mac_addr(dev, p); 370 371 gfar_set_mac_for_addr(dev, 0, dev->dev_addr); 372 373 return 0; 374 } 375 376 static void gfar_ints_disable(struct gfar_private *priv) 377 { 378 int i; 379 for (i = 0; i < priv->num_grps; i++) { 380 struct gfar __iomem *regs = priv->gfargrp[i].regs; 381 /* Clear IEVENT */ 382 gfar_write(®s->ievent, IEVENT_INIT_CLEAR); 383 384 /* Initialize IMASK */ 385 gfar_write(®s->imask, IMASK_INIT_CLEAR); 386 } 387 } 388 389 static void gfar_ints_enable(struct gfar_private *priv) 390 { 391 int i; 392 for (i = 0; i < priv->num_grps; i++) { 393 struct gfar __iomem *regs = priv->gfargrp[i].regs; 394 /* Unmask the interrupts we look for */ 395 gfar_write(®s->imask, IMASK_DEFAULT); 396 } 397 } 398 399 static int gfar_alloc_tx_queues(struct gfar_private *priv) 400 { 401 int i; 402 403 for (i = 0; i < priv->num_tx_queues; i++) { 404 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), 405 GFP_KERNEL); 406 if (!priv->tx_queue[i]) 407 return -ENOMEM; 408 409 priv->tx_queue[i]->tx_skbuff = NULL; 410 priv->tx_queue[i]->qindex = i; 411 priv->tx_queue[i]->dev = priv->ndev; 412 spin_lock_init(&(priv->tx_queue[i]->txlock)); 413 } 414 return 0; 415 } 416 417 static int gfar_alloc_rx_queues(struct gfar_private *priv) 418 { 419 int i; 420 421 for (i = 0; i < priv->num_rx_queues; i++) { 422 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), 423 GFP_KERNEL); 424 if (!priv->rx_queue[i]) 425 return -ENOMEM; 426 427 priv->rx_queue[i]->qindex = i; 428 priv->rx_queue[i]->ndev = priv->ndev; 429 } 430 return 0; 431 } 432 433 static void gfar_free_tx_queues(struct gfar_private *priv) 434 { 435 int i; 436 437 for (i = 0; i < priv->num_tx_queues; i++) 438 kfree(priv->tx_queue[i]); 439 } 440 441 static void gfar_free_rx_queues(struct gfar_private *priv) 442 { 443 int i; 444 445 for (i = 0; i < priv->num_rx_queues; i++) 446 kfree(priv->rx_queue[i]); 447 } 448 449 static void unmap_group_regs(struct gfar_private *priv) 450 { 451 int i; 452 453 for (i = 0; i < MAXGROUPS; i++) 454 if (priv->gfargrp[i].regs) 455 iounmap(priv->gfargrp[i].regs); 456 } 457 458 static void free_gfar_dev(struct gfar_private *priv) 459 { 460 int i, j; 461 462 for (i = 0; i < priv->num_grps; i++) 463 for (j = 0; j < GFAR_NUM_IRQS; j++) { 464 kfree(priv->gfargrp[i].irqinfo[j]); 465 priv->gfargrp[i].irqinfo[j] = NULL; 466 } 467 468 free_netdev(priv->ndev); 469 } 470 471 static void disable_napi(struct gfar_private *priv) 472 { 473 int i; 474 475 for (i = 0; i < priv->num_grps; i++) { 476 napi_disable(&priv->gfargrp[i].napi_rx); 477 napi_disable(&priv->gfargrp[i].napi_tx); 478 } 479 } 480 481 static void enable_napi(struct gfar_private *priv) 482 { 483 int i; 484 485 for (i = 0; i < priv->num_grps; i++) { 486 napi_enable(&priv->gfargrp[i].napi_rx); 487 napi_enable(&priv->gfargrp[i].napi_tx); 488 } 489 } 490 491 static int gfar_parse_group(struct device_node *np, 492 struct gfar_private *priv, const char *model) 493 { 494 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps]; 495 int i; 496 497 for (i = 0; i < GFAR_NUM_IRQS; i++) { 498 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo), 499 GFP_KERNEL); 500 if (!grp->irqinfo[i]) 501 return -ENOMEM; 502 } 503 504 grp->regs = of_iomap(np, 0); 505 if (!grp->regs) 506 return -ENOMEM; 507 508 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0); 509 510 /* If we aren't the FEC we have multiple interrupts */ 511 if (model && strcasecmp(model, "FEC")) { 512 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1); 513 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2); 514 if (!gfar_irq(grp, TX)->irq || 515 !gfar_irq(grp, RX)->irq || 516 !gfar_irq(grp, ER)->irq) 517 return -EINVAL; 518 } 519 520 grp->priv = priv; 521 spin_lock_init(&grp->grplock); 522 if (priv->mode == MQ_MG_MODE) { 523 u32 rxq_mask, txq_mask; 524 int ret; 525 526 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps); 527 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps); 528 529 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask); 530 if (!ret) { 531 grp->rx_bit_map = rxq_mask ? 532 rxq_mask : (DEFAULT_MAPPING >> priv->num_grps); 533 } 534 535 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask); 536 if (!ret) { 537 grp->tx_bit_map = txq_mask ? 538 txq_mask : (DEFAULT_MAPPING >> priv->num_grps); 539 } 540 541 if (priv->poll_mode == GFAR_SQ_POLLING) { 542 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */ 543 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps); 544 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps); 545 } 546 } else { 547 grp->rx_bit_map = 0xFF; 548 grp->tx_bit_map = 0xFF; 549 } 550 551 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses 552 * right to left, so we need to revert the 8 bits to get the q index 553 */ 554 grp->rx_bit_map = bitrev8(grp->rx_bit_map); 555 grp->tx_bit_map = bitrev8(grp->tx_bit_map); 556 557 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, 558 * also assign queues to groups 559 */ 560 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) { 561 if (!grp->rx_queue) 562 grp->rx_queue = priv->rx_queue[i]; 563 grp->num_rx_queues++; 564 grp->rstat |= (RSTAT_CLEAR_RHALT >> i); 565 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i); 566 priv->rx_queue[i]->grp = grp; 567 } 568 569 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) { 570 if (!grp->tx_queue) 571 grp->tx_queue = priv->tx_queue[i]; 572 grp->num_tx_queues++; 573 grp->tstat |= (TSTAT_CLEAR_THALT >> i); 574 priv->tqueue |= (TQUEUE_EN0 >> i); 575 priv->tx_queue[i]->grp = grp; 576 } 577 578 priv->num_grps++; 579 580 return 0; 581 } 582 583 static int gfar_of_group_count(struct device_node *np) 584 { 585 struct device_node *child; 586 int num = 0; 587 588 for_each_available_child_of_node(np, child) 589 if (of_node_name_eq(child, "queue-group")) 590 num++; 591 592 return num; 593 } 594 595 /* Reads the controller's registers to determine what interface 596 * connects it to the PHY. 597 */ 598 static phy_interface_t gfar_get_interface(struct net_device *dev) 599 { 600 struct gfar_private *priv = netdev_priv(dev); 601 struct gfar __iomem *regs = priv->gfargrp[0].regs; 602 u32 ecntrl; 603 604 ecntrl = gfar_read(®s->ecntrl); 605 606 if (ecntrl & ECNTRL_SGMII_MODE) 607 return PHY_INTERFACE_MODE_SGMII; 608 609 if (ecntrl & ECNTRL_TBI_MODE) { 610 if (ecntrl & ECNTRL_REDUCED_MODE) 611 return PHY_INTERFACE_MODE_RTBI; 612 else 613 return PHY_INTERFACE_MODE_TBI; 614 } 615 616 if (ecntrl & ECNTRL_REDUCED_MODE) { 617 if (ecntrl & ECNTRL_REDUCED_MII_MODE) { 618 return PHY_INTERFACE_MODE_RMII; 619 } 620 else { 621 phy_interface_t interface = priv->interface; 622 623 /* This isn't autodetected right now, so it must 624 * be set by the device tree or platform code. 625 */ 626 if (interface == PHY_INTERFACE_MODE_RGMII_ID) 627 return PHY_INTERFACE_MODE_RGMII_ID; 628 629 return PHY_INTERFACE_MODE_RGMII; 630 } 631 } 632 633 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) 634 return PHY_INTERFACE_MODE_GMII; 635 636 return PHY_INTERFACE_MODE_MII; 637 } 638 639 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) 640 { 641 const char *model; 642 const void *mac_addr; 643 int err = 0, i; 644 phy_interface_t interface; 645 struct net_device *dev = NULL; 646 struct gfar_private *priv = NULL; 647 struct device_node *np = ofdev->dev.of_node; 648 struct device_node *child = NULL; 649 u32 stash_len = 0; 650 u32 stash_idx = 0; 651 unsigned int num_tx_qs, num_rx_qs; 652 unsigned short mode, poll_mode; 653 654 if (!np) 655 return -ENODEV; 656 657 if (of_device_is_compatible(np, "fsl,etsec2")) { 658 mode = MQ_MG_MODE; 659 poll_mode = GFAR_SQ_POLLING; 660 } else { 661 mode = SQ_SG_MODE; 662 poll_mode = GFAR_SQ_POLLING; 663 } 664 665 if (mode == SQ_SG_MODE) { 666 num_tx_qs = 1; 667 num_rx_qs = 1; 668 } else { /* MQ_MG_MODE */ 669 /* get the actual number of supported groups */ 670 unsigned int num_grps = gfar_of_group_count(np); 671 672 if (num_grps == 0 || num_grps > MAXGROUPS) { 673 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n", 674 num_grps); 675 pr_err("Cannot do alloc_etherdev, aborting\n"); 676 return -EINVAL; 677 } 678 679 if (poll_mode == GFAR_SQ_POLLING) { 680 num_tx_qs = num_grps; /* one txq per int group */ 681 num_rx_qs = num_grps; /* one rxq per int group */ 682 } else { /* GFAR_MQ_POLLING */ 683 u32 tx_queues, rx_queues; 684 int ret; 685 686 /* parse the num of HW tx and rx queues */ 687 ret = of_property_read_u32(np, "fsl,num_tx_queues", 688 &tx_queues); 689 num_tx_qs = ret ? 1 : tx_queues; 690 691 ret = of_property_read_u32(np, "fsl,num_rx_queues", 692 &rx_queues); 693 num_rx_qs = ret ? 1 : rx_queues; 694 } 695 } 696 697 if (num_tx_qs > MAX_TX_QS) { 698 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", 699 num_tx_qs, MAX_TX_QS); 700 pr_err("Cannot do alloc_etherdev, aborting\n"); 701 return -EINVAL; 702 } 703 704 if (num_rx_qs > MAX_RX_QS) { 705 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", 706 num_rx_qs, MAX_RX_QS); 707 pr_err("Cannot do alloc_etherdev, aborting\n"); 708 return -EINVAL; 709 } 710 711 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); 712 dev = *pdev; 713 if (NULL == dev) 714 return -ENOMEM; 715 716 priv = netdev_priv(dev); 717 priv->ndev = dev; 718 719 priv->mode = mode; 720 priv->poll_mode = poll_mode; 721 722 priv->num_tx_queues = num_tx_qs; 723 netif_set_real_num_rx_queues(dev, num_rx_qs); 724 priv->num_rx_queues = num_rx_qs; 725 726 err = gfar_alloc_tx_queues(priv); 727 if (err) 728 goto tx_alloc_failed; 729 730 err = gfar_alloc_rx_queues(priv); 731 if (err) 732 goto rx_alloc_failed; 733 734 err = of_property_read_string(np, "model", &model); 735 if (err) { 736 pr_err("Device model property missing, aborting\n"); 737 goto rx_alloc_failed; 738 } 739 740 /* Init Rx queue filer rule set linked list */ 741 INIT_LIST_HEAD(&priv->rx_list.list); 742 priv->rx_list.count = 0; 743 mutex_init(&priv->rx_queue_access); 744 745 for (i = 0; i < MAXGROUPS; i++) 746 priv->gfargrp[i].regs = NULL; 747 748 /* Parse and initialize group specific information */ 749 if (priv->mode == MQ_MG_MODE) { 750 for_each_available_child_of_node(np, child) { 751 if (!of_node_name_eq(child, "queue-group")) 752 continue; 753 754 err = gfar_parse_group(child, priv, model); 755 if (err) 756 goto err_grp_init; 757 } 758 } else { /* SQ_SG_MODE */ 759 err = gfar_parse_group(np, priv, model); 760 if (err) 761 goto err_grp_init; 762 } 763 764 if (of_property_read_bool(np, "bd-stash")) { 765 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; 766 priv->bd_stash_en = 1; 767 } 768 769 err = of_property_read_u32(np, "rx-stash-len", &stash_len); 770 771 if (err == 0) 772 priv->rx_stash_size = stash_len; 773 774 err = of_property_read_u32(np, "rx-stash-idx", &stash_idx); 775 776 if (err == 0) 777 priv->rx_stash_index = stash_idx; 778 779 if (stash_len || stash_idx) 780 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; 781 782 mac_addr = of_get_mac_address(np); 783 784 if (!IS_ERR(mac_addr)) 785 ether_addr_copy(dev->dev_addr, mac_addr); 786 787 if (model && !strcasecmp(model, "TSEC")) 788 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT | 789 FSL_GIANFAR_DEV_HAS_COALESCE | 790 FSL_GIANFAR_DEV_HAS_RMON | 791 FSL_GIANFAR_DEV_HAS_MULTI_INTR; 792 793 if (model && !strcasecmp(model, "eTSEC")) 794 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT | 795 FSL_GIANFAR_DEV_HAS_COALESCE | 796 FSL_GIANFAR_DEV_HAS_RMON | 797 FSL_GIANFAR_DEV_HAS_MULTI_INTR | 798 FSL_GIANFAR_DEV_HAS_CSUM | 799 FSL_GIANFAR_DEV_HAS_VLAN | 800 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | 801 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | 802 FSL_GIANFAR_DEV_HAS_TIMER | 803 FSL_GIANFAR_DEV_HAS_RX_FILER; 804 805 /* Use PHY connection type from the DT node if one is specified there. 806 * rgmii-id really needs to be specified. Other types can be 807 * detected by hardware 808 */ 809 err = of_get_phy_mode(np, &interface); 810 if (!err) 811 priv->interface = interface; 812 else 813 priv->interface = gfar_get_interface(dev); 814 815 if (of_find_property(np, "fsl,magic-packet", NULL)) 816 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; 817 818 if (of_get_property(np, "fsl,wake-on-filer", NULL)) 819 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER; 820 821 priv->phy_node = of_parse_phandle(np, "phy-handle", 0); 822 823 /* In the case of a fixed PHY, the DT node associated 824 * to the PHY is the Ethernet MAC DT node. 825 */ 826 if (!priv->phy_node && of_phy_is_fixed_link(np)) { 827 err = of_phy_register_fixed_link(np); 828 if (err) 829 goto err_grp_init; 830 831 priv->phy_node = of_node_get(np); 832 } 833 834 /* Find the TBI PHY. If it's not there, we don't support SGMII */ 835 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); 836 837 return 0; 838 839 err_grp_init: 840 unmap_group_regs(priv); 841 rx_alloc_failed: 842 gfar_free_rx_queues(priv); 843 tx_alloc_failed: 844 gfar_free_tx_queues(priv); 845 free_gfar_dev(priv); 846 return err; 847 } 848 849 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, 850 u32 class) 851 { 852 u32 rqfpr = FPR_FILER_MASK; 853 u32 rqfcr = 0x0; 854 855 rqfar--; 856 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; 857 priv->ftp_rqfpr[rqfar] = rqfpr; 858 priv->ftp_rqfcr[rqfar] = rqfcr; 859 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 860 861 rqfar--; 862 rqfcr = RQFCR_CMP_NOMATCH; 863 priv->ftp_rqfpr[rqfar] = rqfpr; 864 priv->ftp_rqfcr[rqfar] = rqfcr; 865 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 866 867 rqfar--; 868 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; 869 rqfpr = class; 870 priv->ftp_rqfcr[rqfar] = rqfcr; 871 priv->ftp_rqfpr[rqfar] = rqfpr; 872 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 873 874 rqfar--; 875 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; 876 rqfpr = class; 877 priv->ftp_rqfcr[rqfar] = rqfcr; 878 priv->ftp_rqfpr[rqfar] = rqfpr; 879 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 880 881 return rqfar; 882 } 883 884 static void gfar_init_filer_table(struct gfar_private *priv) 885 { 886 int i = 0x0; 887 u32 rqfar = MAX_FILER_IDX; 888 u32 rqfcr = 0x0; 889 u32 rqfpr = FPR_FILER_MASK; 890 891 /* Default rule */ 892 rqfcr = RQFCR_CMP_MATCH; 893 priv->ftp_rqfcr[rqfar] = rqfcr; 894 priv->ftp_rqfpr[rqfar] = rqfpr; 895 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 896 897 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); 898 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); 899 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); 900 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); 901 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); 902 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); 903 904 /* cur_filer_idx indicated the first non-masked rule */ 905 priv->cur_filer_idx = rqfar; 906 907 /* Rest are masked rules */ 908 rqfcr = RQFCR_CMP_NOMATCH; 909 for (i = 0; i < rqfar; i++) { 910 priv->ftp_rqfcr[i] = rqfcr; 911 priv->ftp_rqfpr[i] = rqfpr; 912 gfar_write_filer(priv, i, rqfcr, rqfpr); 913 } 914 } 915 916 #ifdef CONFIG_PPC 917 static void __gfar_detect_errata_83xx(struct gfar_private *priv) 918 { 919 unsigned int pvr = mfspr(SPRN_PVR); 920 unsigned int svr = mfspr(SPRN_SVR); 921 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ 922 unsigned int rev = svr & 0xffff; 923 924 /* MPC8313 Rev 2.0 and higher; All MPC837x */ 925 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || 926 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) 927 priv->errata |= GFAR_ERRATA_74; 928 929 /* MPC8313 and MPC837x all rev */ 930 if ((pvr == 0x80850010 && mod == 0x80b0) || 931 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) 932 priv->errata |= GFAR_ERRATA_76; 933 934 /* MPC8313 Rev < 2.0 */ 935 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) 936 priv->errata |= GFAR_ERRATA_12; 937 } 938 939 static void __gfar_detect_errata_85xx(struct gfar_private *priv) 940 { 941 unsigned int svr = mfspr(SPRN_SVR); 942 943 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20)) 944 priv->errata |= GFAR_ERRATA_12; 945 /* P2020/P1010 Rev 1; MPC8548 Rev 2 */ 946 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) || 947 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) || 948 ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31))) 949 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */ 950 } 951 #endif 952 953 static void gfar_detect_errata(struct gfar_private *priv) 954 { 955 struct device *dev = &priv->ofdev->dev; 956 957 /* no plans to fix */ 958 priv->errata |= GFAR_ERRATA_A002; 959 960 #ifdef CONFIG_PPC 961 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)) 962 __gfar_detect_errata_85xx(priv); 963 else /* non-mpc85xx parts, i.e. e300 core based */ 964 __gfar_detect_errata_83xx(priv); 965 #endif 966 967 if (priv->errata) 968 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", 969 priv->errata); 970 } 971 972 static void gfar_init_addr_hash_table(struct gfar_private *priv) 973 { 974 struct gfar __iomem *regs = priv->gfargrp[0].regs; 975 976 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { 977 priv->extended_hash = 1; 978 priv->hash_width = 9; 979 980 priv->hash_regs[0] = ®s->igaddr0; 981 priv->hash_regs[1] = ®s->igaddr1; 982 priv->hash_regs[2] = ®s->igaddr2; 983 priv->hash_regs[3] = ®s->igaddr3; 984 priv->hash_regs[4] = ®s->igaddr4; 985 priv->hash_regs[5] = ®s->igaddr5; 986 priv->hash_regs[6] = ®s->igaddr6; 987 priv->hash_regs[7] = ®s->igaddr7; 988 priv->hash_regs[8] = ®s->gaddr0; 989 priv->hash_regs[9] = ®s->gaddr1; 990 priv->hash_regs[10] = ®s->gaddr2; 991 priv->hash_regs[11] = ®s->gaddr3; 992 priv->hash_regs[12] = ®s->gaddr4; 993 priv->hash_regs[13] = ®s->gaddr5; 994 priv->hash_regs[14] = ®s->gaddr6; 995 priv->hash_regs[15] = ®s->gaddr7; 996 997 } else { 998 priv->extended_hash = 0; 999 priv->hash_width = 8; 1000 1001 priv->hash_regs[0] = ®s->gaddr0; 1002 priv->hash_regs[1] = ®s->gaddr1; 1003 priv->hash_regs[2] = ®s->gaddr2; 1004 priv->hash_regs[3] = ®s->gaddr3; 1005 priv->hash_regs[4] = ®s->gaddr4; 1006 priv->hash_regs[5] = ®s->gaddr5; 1007 priv->hash_regs[6] = ®s->gaddr6; 1008 priv->hash_regs[7] = ®s->gaddr7; 1009 } 1010 } 1011 1012 static int __gfar_is_rx_idle(struct gfar_private *priv) 1013 { 1014 u32 res; 1015 1016 /* Normaly TSEC should not hang on GRS commands, so we should 1017 * actually wait for IEVENT_GRSC flag. 1018 */ 1019 if (!gfar_has_errata(priv, GFAR_ERRATA_A002)) 1020 return 0; 1021 1022 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are 1023 * the same as bits 23-30, the eTSEC Rx is assumed to be idle 1024 * and the Rx can be safely reset. 1025 */ 1026 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); 1027 res &= 0x7f807f80; 1028 if ((res & 0xffff) == (res >> 16)) 1029 return 1; 1030 1031 return 0; 1032 } 1033 1034 /* Halt the receive and transmit queues */ 1035 static void gfar_halt_nodisable(struct gfar_private *priv) 1036 { 1037 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1038 u32 tempval; 1039 unsigned int timeout; 1040 int stopped; 1041 1042 gfar_ints_disable(priv); 1043 1044 if (gfar_is_dma_stopped(priv)) 1045 return; 1046 1047 /* Stop the DMA, and wait for it to stop */ 1048 tempval = gfar_read(®s->dmactrl); 1049 tempval |= (DMACTRL_GRS | DMACTRL_GTS); 1050 gfar_write(®s->dmactrl, tempval); 1051 1052 retry: 1053 timeout = 1000; 1054 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) { 1055 cpu_relax(); 1056 timeout--; 1057 } 1058 1059 if (!timeout) 1060 stopped = gfar_is_dma_stopped(priv); 1061 1062 if (!stopped && !gfar_is_rx_dma_stopped(priv) && 1063 !__gfar_is_rx_idle(priv)) 1064 goto retry; 1065 } 1066 1067 /* Halt the receive and transmit queues */ 1068 static void gfar_halt(struct gfar_private *priv) 1069 { 1070 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1071 u32 tempval; 1072 1073 /* Dissable the Rx/Tx hw queues */ 1074 gfar_write(®s->rqueue, 0); 1075 gfar_write(®s->tqueue, 0); 1076 1077 mdelay(10); 1078 1079 gfar_halt_nodisable(priv); 1080 1081 /* Disable Rx/Tx DMA */ 1082 tempval = gfar_read(®s->maccfg1); 1083 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); 1084 gfar_write(®s->maccfg1, tempval); 1085 } 1086 1087 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) 1088 { 1089 struct txbd8 *txbdp; 1090 struct gfar_private *priv = netdev_priv(tx_queue->dev); 1091 int i, j; 1092 1093 txbdp = tx_queue->tx_bd_base; 1094 1095 for (i = 0; i < tx_queue->tx_ring_size; i++) { 1096 if (!tx_queue->tx_skbuff[i]) 1097 continue; 1098 1099 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr), 1100 be16_to_cpu(txbdp->length), DMA_TO_DEVICE); 1101 txbdp->lstatus = 0; 1102 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; 1103 j++) { 1104 txbdp++; 1105 dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr), 1106 be16_to_cpu(txbdp->length), 1107 DMA_TO_DEVICE); 1108 } 1109 txbdp++; 1110 dev_kfree_skb_any(tx_queue->tx_skbuff[i]); 1111 tx_queue->tx_skbuff[i] = NULL; 1112 } 1113 kfree(tx_queue->tx_skbuff); 1114 tx_queue->tx_skbuff = NULL; 1115 } 1116 1117 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) 1118 { 1119 int i; 1120 1121 struct rxbd8 *rxbdp = rx_queue->rx_bd_base; 1122 1123 dev_kfree_skb(rx_queue->skb); 1124 1125 for (i = 0; i < rx_queue->rx_ring_size; i++) { 1126 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[i]; 1127 1128 rxbdp->lstatus = 0; 1129 rxbdp->bufPtr = 0; 1130 rxbdp++; 1131 1132 if (!rxb->page) 1133 continue; 1134 1135 dma_unmap_page(rx_queue->dev, rxb->dma, 1136 PAGE_SIZE, DMA_FROM_DEVICE); 1137 __free_page(rxb->page); 1138 1139 rxb->page = NULL; 1140 } 1141 1142 kfree(rx_queue->rx_buff); 1143 rx_queue->rx_buff = NULL; 1144 } 1145 1146 /* If there are any tx skbs or rx skbs still around, free them. 1147 * Then free tx_skbuff and rx_skbuff 1148 */ 1149 static void free_skb_resources(struct gfar_private *priv) 1150 { 1151 struct gfar_priv_tx_q *tx_queue = NULL; 1152 struct gfar_priv_rx_q *rx_queue = NULL; 1153 int i; 1154 1155 /* Go through all the buffer descriptors and free their data buffers */ 1156 for (i = 0; i < priv->num_tx_queues; i++) { 1157 struct netdev_queue *txq; 1158 1159 tx_queue = priv->tx_queue[i]; 1160 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); 1161 if (tx_queue->tx_skbuff) 1162 free_skb_tx_queue(tx_queue); 1163 netdev_tx_reset_queue(txq); 1164 } 1165 1166 for (i = 0; i < priv->num_rx_queues; i++) { 1167 rx_queue = priv->rx_queue[i]; 1168 if (rx_queue->rx_buff) 1169 free_skb_rx_queue(rx_queue); 1170 } 1171 1172 dma_free_coherent(priv->dev, 1173 sizeof(struct txbd8) * priv->total_tx_ring_size + 1174 sizeof(struct rxbd8) * priv->total_rx_ring_size, 1175 priv->tx_queue[0]->tx_bd_base, 1176 priv->tx_queue[0]->tx_bd_dma_base); 1177 } 1178 1179 void stop_gfar(struct net_device *dev) 1180 { 1181 struct gfar_private *priv = netdev_priv(dev); 1182 1183 netif_tx_stop_all_queues(dev); 1184 1185 smp_mb__before_atomic(); 1186 set_bit(GFAR_DOWN, &priv->state); 1187 smp_mb__after_atomic(); 1188 1189 disable_napi(priv); 1190 1191 /* disable ints and gracefully shut down Rx/Tx DMA */ 1192 gfar_halt(priv); 1193 1194 phy_stop(dev->phydev); 1195 1196 free_skb_resources(priv); 1197 } 1198 1199 static void gfar_start(struct gfar_private *priv) 1200 { 1201 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1202 u32 tempval; 1203 int i = 0; 1204 1205 /* Enable Rx/Tx hw queues */ 1206 gfar_write(®s->rqueue, priv->rqueue); 1207 gfar_write(®s->tqueue, priv->tqueue); 1208 1209 /* Initialize DMACTRL to have WWR and WOP */ 1210 tempval = gfar_read(®s->dmactrl); 1211 tempval |= DMACTRL_INIT_SETTINGS; 1212 gfar_write(®s->dmactrl, tempval); 1213 1214 /* Make sure we aren't stopped */ 1215 tempval = gfar_read(®s->dmactrl); 1216 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); 1217 gfar_write(®s->dmactrl, tempval); 1218 1219 for (i = 0; i < priv->num_grps; i++) { 1220 regs = priv->gfargrp[i].regs; 1221 /* Clear THLT/RHLT, so that the DMA starts polling now */ 1222 gfar_write(®s->tstat, priv->gfargrp[i].tstat); 1223 gfar_write(®s->rstat, priv->gfargrp[i].rstat); 1224 } 1225 1226 /* Enable Rx/Tx DMA */ 1227 tempval = gfar_read(®s->maccfg1); 1228 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 1229 gfar_write(®s->maccfg1, tempval); 1230 1231 gfar_ints_enable(priv); 1232 1233 netif_trans_update(priv->ndev); /* prevent tx timeout */ 1234 } 1235 1236 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb) 1237 { 1238 struct page *page; 1239 dma_addr_t addr; 1240 1241 page = dev_alloc_page(); 1242 if (unlikely(!page)) 1243 return false; 1244 1245 addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 1246 if (unlikely(dma_mapping_error(rxq->dev, addr))) { 1247 __free_page(page); 1248 1249 return false; 1250 } 1251 1252 rxb->dma = addr; 1253 rxb->page = page; 1254 rxb->page_offset = 0; 1255 1256 return true; 1257 } 1258 1259 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue) 1260 { 1261 struct gfar_private *priv = netdev_priv(rx_queue->ndev); 1262 struct gfar_extra_stats *estats = &priv->extra_stats; 1263 1264 netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n"); 1265 atomic64_inc(&estats->rx_alloc_err); 1266 } 1267 1268 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue, 1269 int alloc_cnt) 1270 { 1271 struct rxbd8 *bdp; 1272 struct gfar_rx_buff *rxb; 1273 int i; 1274 1275 i = rx_queue->next_to_use; 1276 bdp = &rx_queue->rx_bd_base[i]; 1277 rxb = &rx_queue->rx_buff[i]; 1278 1279 while (alloc_cnt--) { 1280 /* try reuse page */ 1281 if (unlikely(!rxb->page)) { 1282 if (unlikely(!gfar_new_page(rx_queue, rxb))) { 1283 gfar_rx_alloc_err(rx_queue); 1284 break; 1285 } 1286 } 1287 1288 /* Setup the new RxBD */ 1289 gfar_init_rxbdp(rx_queue, bdp, 1290 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT); 1291 1292 /* Update to the next pointer */ 1293 bdp++; 1294 rxb++; 1295 1296 if (unlikely(++i == rx_queue->rx_ring_size)) { 1297 i = 0; 1298 bdp = rx_queue->rx_bd_base; 1299 rxb = rx_queue->rx_buff; 1300 } 1301 } 1302 1303 rx_queue->next_to_use = i; 1304 rx_queue->next_to_alloc = i; 1305 } 1306 1307 static void gfar_init_bds(struct net_device *ndev) 1308 { 1309 struct gfar_private *priv = netdev_priv(ndev); 1310 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1311 struct gfar_priv_tx_q *tx_queue = NULL; 1312 struct gfar_priv_rx_q *rx_queue = NULL; 1313 struct txbd8 *txbdp; 1314 u32 __iomem *rfbptr; 1315 int i, j; 1316 1317 for (i = 0; i < priv->num_tx_queues; i++) { 1318 tx_queue = priv->tx_queue[i]; 1319 /* Initialize some variables in our dev structure */ 1320 tx_queue->num_txbdfree = tx_queue->tx_ring_size; 1321 tx_queue->dirty_tx = tx_queue->tx_bd_base; 1322 tx_queue->cur_tx = tx_queue->tx_bd_base; 1323 tx_queue->skb_curtx = 0; 1324 tx_queue->skb_dirtytx = 0; 1325 1326 /* Initialize Transmit Descriptor Ring */ 1327 txbdp = tx_queue->tx_bd_base; 1328 for (j = 0; j < tx_queue->tx_ring_size; j++) { 1329 txbdp->lstatus = 0; 1330 txbdp->bufPtr = 0; 1331 txbdp++; 1332 } 1333 1334 /* Set the last descriptor in the ring to indicate wrap */ 1335 txbdp--; 1336 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) | 1337 TXBD_WRAP); 1338 } 1339 1340 rfbptr = ®s->rfbptr0; 1341 for (i = 0; i < priv->num_rx_queues; i++) { 1342 rx_queue = priv->rx_queue[i]; 1343 1344 rx_queue->next_to_clean = 0; 1345 rx_queue->next_to_use = 0; 1346 rx_queue->next_to_alloc = 0; 1347 1348 /* make sure next_to_clean != next_to_use after this 1349 * by leaving at least 1 unused descriptor 1350 */ 1351 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue)); 1352 1353 rx_queue->rfbptr = rfbptr; 1354 rfbptr += 2; 1355 } 1356 } 1357 1358 static int gfar_alloc_skb_resources(struct net_device *ndev) 1359 { 1360 void *vaddr; 1361 dma_addr_t addr; 1362 int i, j; 1363 struct gfar_private *priv = netdev_priv(ndev); 1364 struct device *dev = priv->dev; 1365 struct gfar_priv_tx_q *tx_queue = NULL; 1366 struct gfar_priv_rx_q *rx_queue = NULL; 1367 1368 priv->total_tx_ring_size = 0; 1369 for (i = 0; i < priv->num_tx_queues; i++) 1370 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; 1371 1372 priv->total_rx_ring_size = 0; 1373 for (i = 0; i < priv->num_rx_queues; i++) 1374 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; 1375 1376 /* Allocate memory for the buffer descriptors */ 1377 vaddr = dma_alloc_coherent(dev, 1378 (priv->total_tx_ring_size * 1379 sizeof(struct txbd8)) + 1380 (priv->total_rx_ring_size * 1381 sizeof(struct rxbd8)), 1382 &addr, GFP_KERNEL); 1383 if (!vaddr) 1384 return -ENOMEM; 1385 1386 for (i = 0; i < priv->num_tx_queues; i++) { 1387 tx_queue = priv->tx_queue[i]; 1388 tx_queue->tx_bd_base = vaddr; 1389 tx_queue->tx_bd_dma_base = addr; 1390 tx_queue->dev = ndev; 1391 /* enet DMA only understands physical addresses */ 1392 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; 1393 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; 1394 } 1395 1396 /* Start the rx descriptor ring where the tx ring leaves off */ 1397 for (i = 0; i < priv->num_rx_queues; i++) { 1398 rx_queue = priv->rx_queue[i]; 1399 rx_queue->rx_bd_base = vaddr; 1400 rx_queue->rx_bd_dma_base = addr; 1401 rx_queue->ndev = ndev; 1402 rx_queue->dev = dev; 1403 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; 1404 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; 1405 } 1406 1407 /* Setup the skbuff rings */ 1408 for (i = 0; i < priv->num_tx_queues; i++) { 1409 tx_queue = priv->tx_queue[i]; 1410 tx_queue->tx_skbuff = 1411 kmalloc_array(tx_queue->tx_ring_size, 1412 sizeof(*tx_queue->tx_skbuff), 1413 GFP_KERNEL); 1414 if (!tx_queue->tx_skbuff) 1415 goto cleanup; 1416 1417 for (j = 0; j < tx_queue->tx_ring_size; j++) 1418 tx_queue->tx_skbuff[j] = NULL; 1419 } 1420 1421 for (i = 0; i < priv->num_rx_queues; i++) { 1422 rx_queue = priv->rx_queue[i]; 1423 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size, 1424 sizeof(*rx_queue->rx_buff), 1425 GFP_KERNEL); 1426 if (!rx_queue->rx_buff) 1427 goto cleanup; 1428 } 1429 1430 gfar_init_bds(ndev); 1431 1432 return 0; 1433 1434 cleanup: 1435 free_skb_resources(priv); 1436 return -ENOMEM; 1437 } 1438 1439 /* Bring the controller up and running */ 1440 int startup_gfar(struct net_device *ndev) 1441 { 1442 struct gfar_private *priv = netdev_priv(ndev); 1443 int err; 1444 1445 gfar_mac_reset(priv); 1446 1447 err = gfar_alloc_skb_resources(ndev); 1448 if (err) 1449 return err; 1450 1451 gfar_init_tx_rx_base(priv); 1452 1453 smp_mb__before_atomic(); 1454 clear_bit(GFAR_DOWN, &priv->state); 1455 smp_mb__after_atomic(); 1456 1457 /* Start Rx/Tx DMA and enable the interrupts */ 1458 gfar_start(priv); 1459 1460 /* force link state update after mac reset */ 1461 priv->oldlink = 0; 1462 priv->oldspeed = 0; 1463 priv->oldduplex = -1; 1464 1465 phy_start(ndev->phydev); 1466 1467 enable_napi(priv); 1468 1469 netif_tx_wake_all_queues(ndev); 1470 1471 return 0; 1472 } 1473 1474 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv) 1475 { 1476 struct net_device *ndev = priv->ndev; 1477 struct phy_device *phydev = ndev->phydev; 1478 u32 val = 0; 1479 1480 if (!phydev->duplex) 1481 return val; 1482 1483 if (!priv->pause_aneg_en) { 1484 if (priv->tx_pause_en) 1485 val |= MACCFG1_TX_FLOW; 1486 if (priv->rx_pause_en) 1487 val |= MACCFG1_RX_FLOW; 1488 } else { 1489 u16 lcl_adv, rmt_adv; 1490 u8 flowctrl; 1491 /* get link partner capabilities */ 1492 rmt_adv = 0; 1493 if (phydev->pause) 1494 rmt_adv = LPA_PAUSE_CAP; 1495 if (phydev->asym_pause) 1496 rmt_adv |= LPA_PAUSE_ASYM; 1497 1498 lcl_adv = linkmode_adv_to_lcl_adv_t(phydev->advertising); 1499 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 1500 if (flowctrl & FLOW_CTRL_TX) 1501 val |= MACCFG1_TX_FLOW; 1502 if (flowctrl & FLOW_CTRL_RX) 1503 val |= MACCFG1_RX_FLOW; 1504 } 1505 1506 return val; 1507 } 1508 1509 static noinline void gfar_update_link_state(struct gfar_private *priv) 1510 { 1511 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1512 struct net_device *ndev = priv->ndev; 1513 struct phy_device *phydev = ndev->phydev; 1514 struct gfar_priv_rx_q *rx_queue = NULL; 1515 int i; 1516 1517 if (unlikely(test_bit(GFAR_RESETTING, &priv->state))) 1518 return; 1519 1520 if (phydev->link) { 1521 u32 tempval1 = gfar_read(®s->maccfg1); 1522 u32 tempval = gfar_read(®s->maccfg2); 1523 u32 ecntrl = gfar_read(®s->ecntrl); 1524 u32 tx_flow_oldval = (tempval1 & MACCFG1_TX_FLOW); 1525 1526 if (phydev->duplex != priv->oldduplex) { 1527 if (!(phydev->duplex)) 1528 tempval &= ~(MACCFG2_FULL_DUPLEX); 1529 else 1530 tempval |= MACCFG2_FULL_DUPLEX; 1531 1532 priv->oldduplex = phydev->duplex; 1533 } 1534 1535 if (phydev->speed != priv->oldspeed) { 1536 switch (phydev->speed) { 1537 case 1000: 1538 tempval = 1539 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); 1540 1541 ecntrl &= ~(ECNTRL_R100); 1542 break; 1543 case 100: 1544 case 10: 1545 tempval = 1546 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); 1547 1548 /* Reduced mode distinguishes 1549 * between 10 and 100 1550 */ 1551 if (phydev->speed == SPEED_100) 1552 ecntrl |= ECNTRL_R100; 1553 else 1554 ecntrl &= ~(ECNTRL_R100); 1555 break; 1556 default: 1557 netif_warn(priv, link, priv->ndev, 1558 "Ack! Speed (%d) is not 10/100/1000!\n", 1559 phydev->speed); 1560 break; 1561 } 1562 1563 priv->oldspeed = phydev->speed; 1564 } 1565 1566 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); 1567 tempval1 |= gfar_get_flowctrl_cfg(priv); 1568 1569 /* Turn last free buffer recording on */ 1570 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) { 1571 for (i = 0; i < priv->num_rx_queues; i++) { 1572 u32 bdp_dma; 1573 1574 rx_queue = priv->rx_queue[i]; 1575 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue); 1576 gfar_write(rx_queue->rfbptr, bdp_dma); 1577 } 1578 1579 priv->tx_actual_en = 1; 1580 } 1581 1582 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval)) 1583 priv->tx_actual_en = 0; 1584 1585 gfar_write(®s->maccfg1, tempval1); 1586 gfar_write(®s->maccfg2, tempval); 1587 gfar_write(®s->ecntrl, ecntrl); 1588 1589 if (!priv->oldlink) 1590 priv->oldlink = 1; 1591 1592 } else if (priv->oldlink) { 1593 priv->oldlink = 0; 1594 priv->oldspeed = 0; 1595 priv->oldduplex = -1; 1596 } 1597 1598 if (netif_msg_link(priv)) 1599 phy_print_status(phydev); 1600 } 1601 1602 /* Called every time the controller might need to be made 1603 * aware of new link state. The PHY code conveys this 1604 * information through variables in the phydev structure, and this 1605 * function converts those variables into the appropriate 1606 * register values, and can bring down the device if needed. 1607 */ 1608 static void adjust_link(struct net_device *dev) 1609 { 1610 struct gfar_private *priv = netdev_priv(dev); 1611 struct phy_device *phydev = dev->phydev; 1612 1613 if (unlikely(phydev->link != priv->oldlink || 1614 (phydev->link && (phydev->duplex != priv->oldduplex || 1615 phydev->speed != priv->oldspeed)))) 1616 gfar_update_link_state(priv); 1617 } 1618 1619 /* Initialize TBI PHY interface for communicating with the 1620 * SERDES lynx PHY on the chip. We communicate with this PHY 1621 * through the MDIO bus on each controller, treating it as a 1622 * "normal" PHY at the address found in the TBIPA register. We assume 1623 * that the TBIPA register is valid. Either the MDIO bus code will set 1624 * it to a value that doesn't conflict with other PHYs on the bus, or the 1625 * value doesn't matter, as there are no other PHYs on the bus. 1626 */ 1627 static void gfar_configure_serdes(struct net_device *dev) 1628 { 1629 struct gfar_private *priv = netdev_priv(dev); 1630 struct phy_device *tbiphy; 1631 1632 if (!priv->tbi_node) { 1633 dev_warn(&dev->dev, "error: SGMII mode requires that the " 1634 "device tree specify a tbi-handle\n"); 1635 return; 1636 } 1637 1638 tbiphy = of_phy_find_device(priv->tbi_node); 1639 if (!tbiphy) { 1640 dev_err(&dev->dev, "error: Could not get TBI device\n"); 1641 return; 1642 } 1643 1644 /* If the link is already up, we must already be ok, and don't need to 1645 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured 1646 * everything for us? Resetting it takes the link down and requires 1647 * several seconds for it to come back. 1648 */ 1649 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) { 1650 put_device(&tbiphy->mdio.dev); 1651 return; 1652 } 1653 1654 /* Single clk mode, mii mode off(for serdes communication) */ 1655 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); 1656 1657 phy_write(tbiphy, MII_ADVERTISE, 1658 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | 1659 ADVERTISE_1000XPSE_ASYM); 1660 1661 phy_write(tbiphy, MII_BMCR, 1662 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | 1663 BMCR_SPEED1000); 1664 1665 put_device(&tbiphy->mdio.dev); 1666 } 1667 1668 /* Initializes driver's PHY state, and attaches to the PHY. 1669 * Returns 0 on success. 1670 */ 1671 static int init_phy(struct net_device *dev) 1672 { 1673 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1674 struct gfar_private *priv = netdev_priv(dev); 1675 phy_interface_t interface = priv->interface; 1676 struct phy_device *phydev; 1677 struct ethtool_eee edata; 1678 1679 linkmode_set_bit_array(phy_10_100_features_array, 1680 ARRAY_SIZE(phy_10_100_features_array), 1681 mask); 1682 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask); 1683 linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask); 1684 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) 1685 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mask); 1686 1687 priv->oldlink = 0; 1688 priv->oldspeed = 0; 1689 priv->oldduplex = -1; 1690 1691 phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, 1692 interface); 1693 if (!phydev) { 1694 dev_err(&dev->dev, "could not attach to PHY\n"); 1695 return -ENODEV; 1696 } 1697 1698 if (interface == PHY_INTERFACE_MODE_SGMII) 1699 gfar_configure_serdes(dev); 1700 1701 /* Remove any features not supported by the controller */ 1702 linkmode_and(phydev->supported, phydev->supported, mask); 1703 linkmode_copy(phydev->advertising, phydev->supported); 1704 1705 /* Add support for flow control */ 1706 phy_support_asym_pause(phydev); 1707 1708 /* disable EEE autoneg, EEE not supported by eTSEC */ 1709 memset(&edata, 0, sizeof(struct ethtool_eee)); 1710 phy_ethtool_set_eee(phydev, &edata); 1711 1712 return 0; 1713 } 1714 1715 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) 1716 { 1717 struct txfcb *fcb = skb_push(skb, GMAC_FCB_LEN); 1718 1719 memset(fcb, 0, GMAC_FCB_LEN); 1720 1721 return fcb; 1722 } 1723 1724 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb, 1725 int fcb_length) 1726 { 1727 /* If we're here, it's a IP packet with a TCP or UDP 1728 * payload. We set it to checksum, using a pseudo-header 1729 * we provide 1730 */ 1731 u8 flags = TXFCB_DEFAULT; 1732 1733 /* Tell the controller what the protocol is 1734 * And provide the already calculated phcs 1735 */ 1736 if (ip_hdr(skb)->protocol == IPPROTO_UDP) { 1737 flags |= TXFCB_UDP; 1738 fcb->phcs = (__force __be16)(udp_hdr(skb)->check); 1739 } else 1740 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check); 1741 1742 /* l3os is the distance between the start of the 1743 * frame (skb->data) and the start of the IP hdr. 1744 * l4os is the distance between the start of the 1745 * l3 hdr and the l4 hdr 1746 */ 1747 fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length); 1748 fcb->l4os = skb_network_header_len(skb); 1749 1750 fcb->flags = flags; 1751 } 1752 1753 static inline void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) 1754 { 1755 fcb->flags |= TXFCB_VLN; 1756 fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb)); 1757 } 1758 1759 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, 1760 struct txbd8 *base, int ring_size) 1761 { 1762 struct txbd8 *new_bd = bdp + stride; 1763 1764 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; 1765 } 1766 1767 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, 1768 int ring_size) 1769 { 1770 return skip_txbd(bdp, 1, base, ring_size); 1771 } 1772 1773 /* eTSEC12: csum generation not supported for some fcb offsets */ 1774 static inline bool gfar_csum_errata_12(struct gfar_private *priv, 1775 unsigned long fcb_addr) 1776 { 1777 return (gfar_has_errata(priv, GFAR_ERRATA_12) && 1778 (fcb_addr % 0x20) > 0x18); 1779 } 1780 1781 /* eTSEC76: csum generation for frames larger than 2500 may 1782 * cause excess delays before start of transmission 1783 */ 1784 static inline bool gfar_csum_errata_76(struct gfar_private *priv, 1785 unsigned int len) 1786 { 1787 return (gfar_has_errata(priv, GFAR_ERRATA_76) && 1788 (len > 2500)); 1789 } 1790 1791 /* This is called by the kernel when a frame is ready for transmission. 1792 * It is pointed to by the dev->hard_start_xmit function pointer 1793 */ 1794 static netdev_tx_t gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) 1795 { 1796 struct gfar_private *priv = netdev_priv(dev); 1797 struct gfar_priv_tx_q *tx_queue = NULL; 1798 struct netdev_queue *txq; 1799 struct gfar __iomem *regs = NULL; 1800 struct txfcb *fcb = NULL; 1801 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; 1802 u32 lstatus; 1803 skb_frag_t *frag; 1804 int i, rq = 0; 1805 int do_tstamp, do_csum, do_vlan; 1806 u32 bufaddr; 1807 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0; 1808 1809 rq = skb->queue_mapping; 1810 tx_queue = priv->tx_queue[rq]; 1811 txq = netdev_get_tx_queue(dev, rq); 1812 base = tx_queue->tx_bd_base; 1813 regs = tx_queue->grp->regs; 1814 1815 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed); 1816 do_vlan = skb_vlan_tag_present(skb); 1817 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1818 priv->hwts_tx_en; 1819 1820 if (do_csum || do_vlan) 1821 fcb_len = GMAC_FCB_LEN; 1822 1823 /* check if time stamp should be generated */ 1824 if (unlikely(do_tstamp)) 1825 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN; 1826 1827 /* make space for additional header when fcb is needed */ 1828 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) { 1829 struct sk_buff *skb_new; 1830 1831 skb_new = skb_realloc_headroom(skb, fcb_len); 1832 if (!skb_new) { 1833 dev->stats.tx_errors++; 1834 dev_kfree_skb_any(skb); 1835 return NETDEV_TX_OK; 1836 } 1837 1838 if (skb->sk) 1839 skb_set_owner_w(skb_new, skb->sk); 1840 dev_consume_skb_any(skb); 1841 skb = skb_new; 1842 } 1843 1844 /* total number of fragments in the SKB */ 1845 nr_frags = skb_shinfo(skb)->nr_frags; 1846 1847 /* calculate the required number of TxBDs for this skb */ 1848 if (unlikely(do_tstamp)) 1849 nr_txbds = nr_frags + 2; 1850 else 1851 nr_txbds = nr_frags + 1; 1852 1853 /* check if there is space to queue this packet */ 1854 if (nr_txbds > tx_queue->num_txbdfree) { 1855 /* no space, stop the queue */ 1856 netif_tx_stop_queue(txq); 1857 dev->stats.tx_fifo_errors++; 1858 return NETDEV_TX_BUSY; 1859 } 1860 1861 /* Update transmit stats */ 1862 bytes_sent = skb->len; 1863 tx_queue->stats.tx_bytes += bytes_sent; 1864 /* keep Tx bytes on wire for BQL accounting */ 1865 GFAR_CB(skb)->bytes_sent = bytes_sent; 1866 tx_queue->stats.tx_packets++; 1867 1868 txbdp = txbdp_start = tx_queue->cur_tx; 1869 lstatus = be32_to_cpu(txbdp->lstatus); 1870 1871 /* Add TxPAL between FCB and frame if required */ 1872 if (unlikely(do_tstamp)) { 1873 skb_push(skb, GMAC_TXPAL_LEN); 1874 memset(skb->data, 0, GMAC_TXPAL_LEN); 1875 } 1876 1877 /* Add TxFCB if required */ 1878 if (fcb_len) { 1879 fcb = gfar_add_fcb(skb); 1880 lstatus |= BD_LFLAG(TXBD_TOE); 1881 } 1882 1883 /* Set up checksumming */ 1884 if (do_csum) { 1885 gfar_tx_checksum(skb, fcb, fcb_len); 1886 1887 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) || 1888 unlikely(gfar_csum_errata_76(priv, skb->len))) { 1889 __skb_pull(skb, GMAC_FCB_LEN); 1890 skb_checksum_help(skb); 1891 if (do_vlan || do_tstamp) { 1892 /* put back a new fcb for vlan/tstamp TOE */ 1893 fcb = gfar_add_fcb(skb); 1894 } else { 1895 /* Tx TOE not used */ 1896 lstatus &= ~(BD_LFLAG(TXBD_TOE)); 1897 fcb = NULL; 1898 } 1899 } 1900 } 1901 1902 if (do_vlan) 1903 gfar_tx_vlan(skb, fcb); 1904 1905 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb), 1906 DMA_TO_DEVICE); 1907 if (unlikely(dma_mapping_error(priv->dev, bufaddr))) 1908 goto dma_map_err; 1909 1910 txbdp_start->bufPtr = cpu_to_be32(bufaddr); 1911 1912 /* Time stamp insertion requires one additional TxBD */ 1913 if (unlikely(do_tstamp)) 1914 txbdp_tstamp = txbdp = next_txbd(txbdp, base, 1915 tx_queue->tx_ring_size); 1916 1917 if (likely(!nr_frags)) { 1918 if (likely(!do_tstamp)) 1919 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 1920 } else { 1921 u32 lstatus_start = lstatus; 1922 1923 /* Place the fragment addresses and lengths into the TxBDs */ 1924 frag = &skb_shinfo(skb)->frags[0]; 1925 for (i = 0; i < nr_frags; i++, frag++) { 1926 unsigned int size; 1927 1928 /* Point at the next BD, wrapping as needed */ 1929 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 1930 1931 size = skb_frag_size(frag); 1932 1933 lstatus = be32_to_cpu(txbdp->lstatus) | size | 1934 BD_LFLAG(TXBD_READY); 1935 1936 /* Handle the last BD specially */ 1937 if (i == nr_frags - 1) 1938 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 1939 1940 bufaddr = skb_frag_dma_map(priv->dev, frag, 0, 1941 size, DMA_TO_DEVICE); 1942 if (unlikely(dma_mapping_error(priv->dev, bufaddr))) 1943 goto dma_map_err; 1944 1945 /* set the TxBD length and buffer pointer */ 1946 txbdp->bufPtr = cpu_to_be32(bufaddr); 1947 txbdp->lstatus = cpu_to_be32(lstatus); 1948 } 1949 1950 lstatus = lstatus_start; 1951 } 1952 1953 /* If time stamping is requested one additional TxBD must be set up. The 1954 * first TxBD points to the FCB and must have a data length of 1955 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with 1956 * the full frame length. 1957 */ 1958 if (unlikely(do_tstamp)) { 1959 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus); 1960 1961 bufaddr = be32_to_cpu(txbdp_start->bufPtr); 1962 bufaddr += fcb_len; 1963 1964 lstatus_ts |= BD_LFLAG(TXBD_READY) | 1965 (skb_headlen(skb) - fcb_len); 1966 if (!nr_frags) 1967 lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 1968 1969 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr); 1970 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts); 1971 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; 1972 1973 /* Setup tx hardware time stamping */ 1974 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1975 fcb->ptp = 1; 1976 } else { 1977 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); 1978 } 1979 1980 netdev_tx_sent_queue(txq, bytes_sent); 1981 1982 gfar_wmb(); 1983 1984 txbdp_start->lstatus = cpu_to_be32(lstatus); 1985 1986 gfar_wmb(); /* force lstatus write before tx_skbuff */ 1987 1988 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; 1989 1990 /* Update the current skb pointer to the next entry we will use 1991 * (wrapping if necessary) 1992 */ 1993 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & 1994 TX_RING_MOD_MASK(tx_queue->tx_ring_size); 1995 1996 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); 1997 1998 /* We can work in parallel with gfar_clean_tx_ring(), except 1999 * when modifying num_txbdfree. Note that we didn't grab the lock 2000 * when we were reading the num_txbdfree and checking for available 2001 * space, that's because outside of this function it can only grow. 2002 */ 2003 spin_lock_bh(&tx_queue->txlock); 2004 /* reduce TxBD free count */ 2005 tx_queue->num_txbdfree -= (nr_txbds); 2006 spin_unlock_bh(&tx_queue->txlock); 2007 2008 /* If the next BD still needs to be cleaned up, then the bds 2009 * are full. We need to tell the kernel to stop sending us stuff. 2010 */ 2011 if (!tx_queue->num_txbdfree) { 2012 netif_tx_stop_queue(txq); 2013 2014 dev->stats.tx_fifo_errors++; 2015 } 2016 2017 /* Tell the DMA to go go go */ 2018 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); 2019 2020 return NETDEV_TX_OK; 2021 2022 dma_map_err: 2023 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size); 2024 if (do_tstamp) 2025 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2026 for (i = 0; i < nr_frags; i++) { 2027 lstatus = be32_to_cpu(txbdp->lstatus); 2028 if (!(lstatus & BD_LFLAG(TXBD_READY))) 2029 break; 2030 2031 lstatus &= ~BD_LFLAG(TXBD_READY); 2032 txbdp->lstatus = cpu_to_be32(lstatus); 2033 bufaddr = be32_to_cpu(txbdp->bufPtr); 2034 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length), 2035 DMA_TO_DEVICE); 2036 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2037 } 2038 gfar_wmb(); 2039 dev_kfree_skb_any(skb); 2040 return NETDEV_TX_OK; 2041 } 2042 2043 /* Changes the mac address if the controller is not running. */ 2044 static int gfar_set_mac_address(struct net_device *dev) 2045 { 2046 gfar_set_mac_for_addr(dev, 0, dev->dev_addr); 2047 2048 return 0; 2049 } 2050 2051 static int gfar_change_mtu(struct net_device *dev, int new_mtu) 2052 { 2053 struct gfar_private *priv = netdev_priv(dev); 2054 2055 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state)) 2056 cpu_relax(); 2057 2058 if (dev->flags & IFF_UP) 2059 stop_gfar(dev); 2060 2061 dev->mtu = new_mtu; 2062 2063 if (dev->flags & IFF_UP) 2064 startup_gfar(dev); 2065 2066 clear_bit_unlock(GFAR_RESETTING, &priv->state); 2067 2068 return 0; 2069 } 2070 2071 static void reset_gfar(struct net_device *ndev) 2072 { 2073 struct gfar_private *priv = netdev_priv(ndev); 2074 2075 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state)) 2076 cpu_relax(); 2077 2078 stop_gfar(ndev); 2079 startup_gfar(ndev); 2080 2081 clear_bit_unlock(GFAR_RESETTING, &priv->state); 2082 } 2083 2084 /* gfar_reset_task gets scheduled when a packet has not been 2085 * transmitted after a set amount of time. 2086 * For now, assume that clearing out all the structures, and 2087 * starting over will fix the problem. 2088 */ 2089 static void gfar_reset_task(struct work_struct *work) 2090 { 2091 struct gfar_private *priv = container_of(work, struct gfar_private, 2092 reset_task); 2093 reset_gfar(priv->ndev); 2094 } 2095 2096 static void gfar_timeout(struct net_device *dev) 2097 { 2098 struct gfar_private *priv = netdev_priv(dev); 2099 2100 dev->stats.tx_errors++; 2101 schedule_work(&priv->reset_task); 2102 } 2103 2104 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 2105 { 2106 struct hwtstamp_config config; 2107 struct gfar_private *priv = netdev_priv(netdev); 2108 2109 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2110 return -EFAULT; 2111 2112 /* reserved for future extensions */ 2113 if (config.flags) 2114 return -EINVAL; 2115 2116 switch (config.tx_type) { 2117 case HWTSTAMP_TX_OFF: 2118 priv->hwts_tx_en = 0; 2119 break; 2120 case HWTSTAMP_TX_ON: 2121 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) 2122 return -ERANGE; 2123 priv->hwts_tx_en = 1; 2124 break; 2125 default: 2126 return -ERANGE; 2127 } 2128 2129 switch (config.rx_filter) { 2130 case HWTSTAMP_FILTER_NONE: 2131 if (priv->hwts_rx_en) { 2132 priv->hwts_rx_en = 0; 2133 reset_gfar(netdev); 2134 } 2135 break; 2136 default: 2137 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) 2138 return -ERANGE; 2139 if (!priv->hwts_rx_en) { 2140 priv->hwts_rx_en = 1; 2141 reset_gfar(netdev); 2142 } 2143 config.rx_filter = HWTSTAMP_FILTER_ALL; 2144 break; 2145 } 2146 2147 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 2148 -EFAULT : 0; 2149 } 2150 2151 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 2152 { 2153 struct hwtstamp_config config; 2154 struct gfar_private *priv = netdev_priv(netdev); 2155 2156 config.flags = 0; 2157 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 2158 config.rx_filter = (priv->hwts_rx_en ? 2159 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE); 2160 2161 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 2162 -EFAULT : 0; 2163 } 2164 2165 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2166 { 2167 struct phy_device *phydev = dev->phydev; 2168 2169 if (!netif_running(dev)) 2170 return -EINVAL; 2171 2172 if (cmd == SIOCSHWTSTAMP) 2173 return gfar_hwtstamp_set(dev, rq); 2174 if (cmd == SIOCGHWTSTAMP) 2175 return gfar_hwtstamp_get(dev, rq); 2176 2177 if (!phydev) 2178 return -ENODEV; 2179 2180 return phy_mii_ioctl(phydev, rq, cmd); 2181 } 2182 2183 /* Interrupt Handler for Transmit complete */ 2184 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) 2185 { 2186 struct net_device *dev = tx_queue->dev; 2187 struct netdev_queue *txq; 2188 struct gfar_private *priv = netdev_priv(dev); 2189 struct txbd8 *bdp, *next = NULL; 2190 struct txbd8 *lbdp = NULL; 2191 struct txbd8 *base = tx_queue->tx_bd_base; 2192 struct sk_buff *skb; 2193 int skb_dirtytx; 2194 int tx_ring_size = tx_queue->tx_ring_size; 2195 int frags = 0, nr_txbds = 0; 2196 int i; 2197 int howmany = 0; 2198 int tqi = tx_queue->qindex; 2199 unsigned int bytes_sent = 0; 2200 u32 lstatus; 2201 size_t buflen; 2202 2203 txq = netdev_get_tx_queue(dev, tqi); 2204 bdp = tx_queue->dirty_tx; 2205 skb_dirtytx = tx_queue->skb_dirtytx; 2206 2207 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { 2208 2209 frags = skb_shinfo(skb)->nr_frags; 2210 2211 /* When time stamping, one additional TxBD must be freed. 2212 * Also, we need to dma_unmap_single() the TxPAL. 2213 */ 2214 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) 2215 nr_txbds = frags + 2; 2216 else 2217 nr_txbds = frags + 1; 2218 2219 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); 2220 2221 lstatus = be32_to_cpu(lbdp->lstatus); 2222 2223 /* Only clean completed frames */ 2224 if ((lstatus & BD_LFLAG(TXBD_READY)) && 2225 (lstatus & BD_LENGTH_MASK)) 2226 break; 2227 2228 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { 2229 next = next_txbd(bdp, base, tx_ring_size); 2230 buflen = be16_to_cpu(next->length) + 2231 GMAC_FCB_LEN + GMAC_TXPAL_LEN; 2232 } else 2233 buflen = be16_to_cpu(bdp->length); 2234 2235 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr), 2236 buflen, DMA_TO_DEVICE); 2237 2238 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { 2239 struct skb_shared_hwtstamps shhwtstamps; 2240 u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) & 2241 ~0x7UL); 2242 2243 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 2244 shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns)); 2245 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN); 2246 skb_tstamp_tx(skb, &shhwtstamps); 2247 gfar_clear_txbd_status(bdp); 2248 bdp = next; 2249 } 2250 2251 gfar_clear_txbd_status(bdp); 2252 bdp = next_txbd(bdp, base, tx_ring_size); 2253 2254 for (i = 0; i < frags; i++) { 2255 dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr), 2256 be16_to_cpu(bdp->length), 2257 DMA_TO_DEVICE); 2258 gfar_clear_txbd_status(bdp); 2259 bdp = next_txbd(bdp, base, tx_ring_size); 2260 } 2261 2262 bytes_sent += GFAR_CB(skb)->bytes_sent; 2263 2264 dev_kfree_skb_any(skb); 2265 2266 tx_queue->tx_skbuff[skb_dirtytx] = NULL; 2267 2268 skb_dirtytx = (skb_dirtytx + 1) & 2269 TX_RING_MOD_MASK(tx_ring_size); 2270 2271 howmany++; 2272 spin_lock(&tx_queue->txlock); 2273 tx_queue->num_txbdfree += nr_txbds; 2274 spin_unlock(&tx_queue->txlock); 2275 } 2276 2277 /* If we freed a buffer, we can restart transmission, if necessary */ 2278 if (tx_queue->num_txbdfree && 2279 netif_tx_queue_stopped(txq) && 2280 !(test_bit(GFAR_DOWN, &priv->state))) 2281 netif_wake_subqueue(priv->ndev, tqi); 2282 2283 /* Update dirty indicators */ 2284 tx_queue->skb_dirtytx = skb_dirtytx; 2285 tx_queue->dirty_tx = bdp; 2286 2287 netdev_tx_completed_queue(txq, howmany, bytes_sent); 2288 } 2289 2290 static void count_errors(u32 lstatus, struct net_device *ndev) 2291 { 2292 struct gfar_private *priv = netdev_priv(ndev); 2293 struct net_device_stats *stats = &ndev->stats; 2294 struct gfar_extra_stats *estats = &priv->extra_stats; 2295 2296 /* If the packet was truncated, none of the other errors matter */ 2297 if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) { 2298 stats->rx_length_errors++; 2299 2300 atomic64_inc(&estats->rx_trunc); 2301 2302 return; 2303 } 2304 /* Count the errors, if there were any */ 2305 if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) { 2306 stats->rx_length_errors++; 2307 2308 if (lstatus & BD_LFLAG(RXBD_LARGE)) 2309 atomic64_inc(&estats->rx_large); 2310 else 2311 atomic64_inc(&estats->rx_short); 2312 } 2313 if (lstatus & BD_LFLAG(RXBD_NONOCTET)) { 2314 stats->rx_frame_errors++; 2315 atomic64_inc(&estats->rx_nonoctet); 2316 } 2317 if (lstatus & BD_LFLAG(RXBD_CRCERR)) { 2318 atomic64_inc(&estats->rx_crcerr); 2319 stats->rx_crc_errors++; 2320 } 2321 if (lstatus & BD_LFLAG(RXBD_OVERRUN)) { 2322 atomic64_inc(&estats->rx_overrun); 2323 stats->rx_over_errors++; 2324 } 2325 } 2326 2327 static irqreturn_t gfar_receive(int irq, void *grp_id) 2328 { 2329 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id; 2330 unsigned long flags; 2331 u32 imask, ievent; 2332 2333 ievent = gfar_read(&grp->regs->ievent); 2334 2335 if (unlikely(ievent & IEVENT_FGPI)) { 2336 gfar_write(&grp->regs->ievent, IEVENT_FGPI); 2337 return IRQ_HANDLED; 2338 } 2339 2340 if (likely(napi_schedule_prep(&grp->napi_rx))) { 2341 spin_lock_irqsave(&grp->grplock, flags); 2342 imask = gfar_read(&grp->regs->imask); 2343 imask &= IMASK_RX_DISABLED; 2344 gfar_write(&grp->regs->imask, imask); 2345 spin_unlock_irqrestore(&grp->grplock, flags); 2346 __napi_schedule(&grp->napi_rx); 2347 } else { 2348 /* Clear IEVENT, so interrupts aren't called again 2349 * because of the packets that have already arrived. 2350 */ 2351 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK); 2352 } 2353 2354 return IRQ_HANDLED; 2355 } 2356 2357 /* Interrupt Handler for Transmit complete */ 2358 static irqreturn_t gfar_transmit(int irq, void *grp_id) 2359 { 2360 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id; 2361 unsigned long flags; 2362 u32 imask; 2363 2364 if (likely(napi_schedule_prep(&grp->napi_tx))) { 2365 spin_lock_irqsave(&grp->grplock, flags); 2366 imask = gfar_read(&grp->regs->imask); 2367 imask &= IMASK_TX_DISABLED; 2368 gfar_write(&grp->regs->imask, imask); 2369 spin_unlock_irqrestore(&grp->grplock, flags); 2370 __napi_schedule(&grp->napi_tx); 2371 } else { 2372 /* Clear IEVENT, so interrupts aren't called again 2373 * because of the packets that have already arrived. 2374 */ 2375 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK); 2376 } 2377 2378 return IRQ_HANDLED; 2379 } 2380 2381 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus, 2382 struct sk_buff *skb, bool first) 2383 { 2384 int size = lstatus & BD_LENGTH_MASK; 2385 struct page *page = rxb->page; 2386 2387 if (likely(first)) { 2388 skb_put(skb, size); 2389 } else { 2390 /* the last fragments' length contains the full frame length */ 2391 if (lstatus & BD_LFLAG(RXBD_LAST)) 2392 size -= skb->len; 2393 2394 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 2395 rxb->page_offset + RXBUF_ALIGNMENT, 2396 size, GFAR_RXB_TRUESIZE); 2397 } 2398 2399 /* try reuse page */ 2400 if (unlikely(page_count(page) != 1 || page_is_pfmemalloc(page))) 2401 return false; 2402 2403 /* change offset to the other half */ 2404 rxb->page_offset ^= GFAR_RXB_TRUESIZE; 2405 2406 page_ref_inc(page); 2407 2408 return true; 2409 } 2410 2411 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq, 2412 struct gfar_rx_buff *old_rxb) 2413 { 2414 struct gfar_rx_buff *new_rxb; 2415 u16 nta = rxq->next_to_alloc; 2416 2417 new_rxb = &rxq->rx_buff[nta]; 2418 2419 /* find next buf that can reuse a page */ 2420 nta++; 2421 rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0; 2422 2423 /* copy page reference */ 2424 *new_rxb = *old_rxb; 2425 2426 /* sync for use by the device */ 2427 dma_sync_single_range_for_device(rxq->dev, old_rxb->dma, 2428 old_rxb->page_offset, 2429 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE); 2430 } 2431 2432 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue, 2433 u32 lstatus, struct sk_buff *skb) 2434 { 2435 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean]; 2436 struct page *page = rxb->page; 2437 bool first = false; 2438 2439 if (likely(!skb)) { 2440 void *buff_addr = page_address(page) + rxb->page_offset; 2441 2442 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE); 2443 if (unlikely(!skb)) { 2444 gfar_rx_alloc_err(rx_queue); 2445 return NULL; 2446 } 2447 skb_reserve(skb, RXBUF_ALIGNMENT); 2448 first = true; 2449 } 2450 2451 dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset, 2452 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE); 2453 2454 if (gfar_add_rx_frag(rxb, lstatus, skb, first)) { 2455 /* reuse the free half of the page */ 2456 gfar_reuse_rx_page(rx_queue, rxb); 2457 } else { 2458 /* page cannot be reused, unmap it */ 2459 dma_unmap_page(rx_queue->dev, rxb->dma, 2460 PAGE_SIZE, DMA_FROM_DEVICE); 2461 } 2462 2463 /* clear rxb content */ 2464 rxb->page = NULL; 2465 2466 return skb; 2467 } 2468 2469 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) 2470 { 2471 /* If valid headers were found, and valid sums 2472 * were verified, then we tell the kernel that no 2473 * checksumming is necessary. Otherwise, it is [FIXME] 2474 */ 2475 if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) == 2476 (RXFCB_CIP | RXFCB_CTU)) 2477 skb->ip_summed = CHECKSUM_UNNECESSARY; 2478 else 2479 skb_checksum_none_assert(skb); 2480 } 2481 2482 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */ 2483 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb) 2484 { 2485 struct gfar_private *priv = netdev_priv(ndev); 2486 struct rxfcb *fcb = NULL; 2487 2488 /* fcb is at the beginning if exists */ 2489 fcb = (struct rxfcb *)skb->data; 2490 2491 /* Remove the FCB from the skb 2492 * Remove the padded bytes, if there are any 2493 */ 2494 if (priv->uses_rxfcb) 2495 skb_pull(skb, GMAC_FCB_LEN); 2496 2497 /* Get receive timestamp from the skb */ 2498 if (priv->hwts_rx_en) { 2499 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); 2500 u64 *ns = (u64 *) skb->data; 2501 2502 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 2503 shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns)); 2504 } 2505 2506 if (priv->padding) 2507 skb_pull(skb, priv->padding); 2508 2509 /* Trim off the FCS */ 2510 pskb_trim(skb, skb->len - ETH_FCS_LEN); 2511 2512 if (ndev->features & NETIF_F_RXCSUM) 2513 gfar_rx_checksum(skb, fcb); 2514 2515 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here. 2516 * Even if vlan rx accel is disabled, on some chips 2517 * RXFCB_VLN is pseudo randomly set. 2518 */ 2519 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX && 2520 be16_to_cpu(fcb->flags) & RXFCB_VLN) 2521 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 2522 be16_to_cpu(fcb->vlctl)); 2523 } 2524 2525 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring 2526 * until the budget/quota has been reached. Returns the number 2527 * of frames handled 2528 */ 2529 static int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, 2530 int rx_work_limit) 2531 { 2532 struct net_device *ndev = rx_queue->ndev; 2533 struct gfar_private *priv = netdev_priv(ndev); 2534 struct rxbd8 *bdp; 2535 int i, howmany = 0; 2536 struct sk_buff *skb = rx_queue->skb; 2537 int cleaned_cnt = gfar_rxbd_unused(rx_queue); 2538 unsigned int total_bytes = 0, total_pkts = 0; 2539 2540 /* Get the first full descriptor */ 2541 i = rx_queue->next_to_clean; 2542 2543 while (rx_work_limit--) { 2544 u32 lstatus; 2545 2546 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) { 2547 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt); 2548 cleaned_cnt = 0; 2549 } 2550 2551 bdp = &rx_queue->rx_bd_base[i]; 2552 lstatus = be32_to_cpu(bdp->lstatus); 2553 if (lstatus & BD_LFLAG(RXBD_EMPTY)) 2554 break; 2555 2556 /* order rx buffer descriptor reads */ 2557 rmb(); 2558 2559 /* fetch next to clean buffer from the ring */ 2560 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb); 2561 if (unlikely(!skb)) 2562 break; 2563 2564 cleaned_cnt++; 2565 howmany++; 2566 2567 if (unlikely(++i == rx_queue->rx_ring_size)) 2568 i = 0; 2569 2570 rx_queue->next_to_clean = i; 2571 2572 /* fetch next buffer if not the last in frame */ 2573 if (!(lstatus & BD_LFLAG(RXBD_LAST))) 2574 continue; 2575 2576 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) { 2577 count_errors(lstatus, ndev); 2578 2579 /* discard faulty buffer */ 2580 dev_kfree_skb(skb); 2581 skb = NULL; 2582 rx_queue->stats.rx_dropped++; 2583 continue; 2584 } 2585 2586 gfar_process_frame(ndev, skb); 2587 2588 /* Increment the number of packets */ 2589 total_pkts++; 2590 total_bytes += skb->len; 2591 2592 skb_record_rx_queue(skb, rx_queue->qindex); 2593 2594 skb->protocol = eth_type_trans(skb, ndev); 2595 2596 /* Send the packet up the stack */ 2597 napi_gro_receive(&rx_queue->grp->napi_rx, skb); 2598 2599 skb = NULL; 2600 } 2601 2602 /* Store incomplete frames for completion */ 2603 rx_queue->skb = skb; 2604 2605 rx_queue->stats.rx_packets += total_pkts; 2606 rx_queue->stats.rx_bytes += total_bytes; 2607 2608 if (cleaned_cnt) 2609 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt); 2610 2611 /* Update Last Free RxBD pointer for LFC */ 2612 if (unlikely(priv->tx_actual_en)) { 2613 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue); 2614 2615 gfar_write(rx_queue->rfbptr, bdp_dma); 2616 } 2617 2618 return howmany; 2619 } 2620 2621 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget) 2622 { 2623 struct gfar_priv_grp *gfargrp = 2624 container_of(napi, struct gfar_priv_grp, napi_rx); 2625 struct gfar __iomem *regs = gfargrp->regs; 2626 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue; 2627 int work_done = 0; 2628 2629 /* Clear IEVENT, so interrupts aren't called again 2630 * because of the packets that have already arrived 2631 */ 2632 gfar_write(®s->ievent, IEVENT_RX_MASK); 2633 2634 work_done = gfar_clean_rx_ring(rx_queue, budget); 2635 2636 if (work_done < budget) { 2637 u32 imask; 2638 napi_complete_done(napi, work_done); 2639 /* Clear the halt bit in RSTAT */ 2640 gfar_write(®s->rstat, gfargrp->rstat); 2641 2642 spin_lock_irq(&gfargrp->grplock); 2643 imask = gfar_read(®s->imask); 2644 imask |= IMASK_RX_DEFAULT; 2645 gfar_write(®s->imask, imask); 2646 spin_unlock_irq(&gfargrp->grplock); 2647 } 2648 2649 return work_done; 2650 } 2651 2652 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget) 2653 { 2654 struct gfar_priv_grp *gfargrp = 2655 container_of(napi, struct gfar_priv_grp, napi_tx); 2656 struct gfar __iomem *regs = gfargrp->regs; 2657 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue; 2658 u32 imask; 2659 2660 /* Clear IEVENT, so interrupts aren't called again 2661 * because of the packets that have already arrived 2662 */ 2663 gfar_write(®s->ievent, IEVENT_TX_MASK); 2664 2665 /* run Tx cleanup to completion */ 2666 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) 2667 gfar_clean_tx_ring(tx_queue); 2668 2669 napi_complete(napi); 2670 2671 spin_lock_irq(&gfargrp->grplock); 2672 imask = gfar_read(®s->imask); 2673 imask |= IMASK_TX_DEFAULT; 2674 gfar_write(®s->imask, imask); 2675 spin_unlock_irq(&gfargrp->grplock); 2676 2677 return 0; 2678 } 2679 2680 static int gfar_poll_rx(struct napi_struct *napi, int budget) 2681 { 2682 struct gfar_priv_grp *gfargrp = 2683 container_of(napi, struct gfar_priv_grp, napi_rx); 2684 struct gfar_private *priv = gfargrp->priv; 2685 struct gfar __iomem *regs = gfargrp->regs; 2686 struct gfar_priv_rx_q *rx_queue = NULL; 2687 int work_done = 0, work_done_per_q = 0; 2688 int i, budget_per_q = 0; 2689 unsigned long rstat_rxf; 2690 int num_act_queues; 2691 2692 /* Clear IEVENT, so interrupts aren't called again 2693 * because of the packets that have already arrived 2694 */ 2695 gfar_write(®s->ievent, IEVENT_RX_MASK); 2696 2697 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK; 2698 2699 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS); 2700 if (num_act_queues) 2701 budget_per_q = budget/num_act_queues; 2702 2703 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { 2704 /* skip queue if not active */ 2705 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i))) 2706 continue; 2707 2708 rx_queue = priv->rx_queue[i]; 2709 work_done_per_q = 2710 gfar_clean_rx_ring(rx_queue, budget_per_q); 2711 work_done += work_done_per_q; 2712 2713 /* finished processing this queue */ 2714 if (work_done_per_q < budget_per_q) { 2715 /* clear active queue hw indication */ 2716 gfar_write(®s->rstat, 2717 RSTAT_CLEAR_RXF0 >> i); 2718 num_act_queues--; 2719 2720 if (!num_act_queues) 2721 break; 2722 } 2723 } 2724 2725 if (!num_act_queues) { 2726 u32 imask; 2727 napi_complete_done(napi, work_done); 2728 2729 /* Clear the halt bit in RSTAT */ 2730 gfar_write(®s->rstat, gfargrp->rstat); 2731 2732 spin_lock_irq(&gfargrp->grplock); 2733 imask = gfar_read(®s->imask); 2734 imask |= IMASK_RX_DEFAULT; 2735 gfar_write(®s->imask, imask); 2736 spin_unlock_irq(&gfargrp->grplock); 2737 } 2738 2739 return work_done; 2740 } 2741 2742 static int gfar_poll_tx(struct napi_struct *napi, int budget) 2743 { 2744 struct gfar_priv_grp *gfargrp = 2745 container_of(napi, struct gfar_priv_grp, napi_tx); 2746 struct gfar_private *priv = gfargrp->priv; 2747 struct gfar __iomem *regs = gfargrp->regs; 2748 struct gfar_priv_tx_q *tx_queue = NULL; 2749 int has_tx_work = 0; 2750 int i; 2751 2752 /* Clear IEVENT, so interrupts aren't called again 2753 * because of the packets that have already arrived 2754 */ 2755 gfar_write(®s->ievent, IEVENT_TX_MASK); 2756 2757 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) { 2758 tx_queue = priv->tx_queue[i]; 2759 /* run Tx cleanup to completion */ 2760 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) { 2761 gfar_clean_tx_ring(tx_queue); 2762 has_tx_work = 1; 2763 } 2764 } 2765 2766 if (!has_tx_work) { 2767 u32 imask; 2768 napi_complete(napi); 2769 2770 spin_lock_irq(&gfargrp->grplock); 2771 imask = gfar_read(®s->imask); 2772 imask |= IMASK_TX_DEFAULT; 2773 gfar_write(®s->imask, imask); 2774 spin_unlock_irq(&gfargrp->grplock); 2775 } 2776 2777 return 0; 2778 } 2779 2780 /* GFAR error interrupt handler */ 2781 static irqreturn_t gfar_error(int irq, void *grp_id) 2782 { 2783 struct gfar_priv_grp *gfargrp = grp_id; 2784 struct gfar __iomem *regs = gfargrp->regs; 2785 struct gfar_private *priv= gfargrp->priv; 2786 struct net_device *dev = priv->ndev; 2787 2788 /* Save ievent for future reference */ 2789 u32 events = gfar_read(®s->ievent); 2790 2791 /* Clear IEVENT */ 2792 gfar_write(®s->ievent, events & IEVENT_ERR_MASK); 2793 2794 /* Magic Packet is not an error. */ 2795 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && 2796 (events & IEVENT_MAG)) 2797 events &= ~IEVENT_MAG; 2798 2799 /* Hmm... */ 2800 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) 2801 netdev_dbg(dev, 2802 "error interrupt (ievent=0x%08x imask=0x%08x)\n", 2803 events, gfar_read(®s->imask)); 2804 2805 /* Update the error counters */ 2806 if (events & IEVENT_TXE) { 2807 dev->stats.tx_errors++; 2808 2809 if (events & IEVENT_LC) 2810 dev->stats.tx_window_errors++; 2811 if (events & IEVENT_CRL) 2812 dev->stats.tx_aborted_errors++; 2813 if (events & IEVENT_XFUN) { 2814 netif_dbg(priv, tx_err, dev, 2815 "TX FIFO underrun, packet dropped\n"); 2816 dev->stats.tx_dropped++; 2817 atomic64_inc(&priv->extra_stats.tx_underrun); 2818 2819 schedule_work(&priv->reset_task); 2820 } 2821 netif_dbg(priv, tx_err, dev, "Transmit Error\n"); 2822 } 2823 if (events & IEVENT_BSY) { 2824 dev->stats.rx_over_errors++; 2825 atomic64_inc(&priv->extra_stats.rx_bsy); 2826 2827 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n", 2828 gfar_read(®s->rstat)); 2829 } 2830 if (events & IEVENT_BABR) { 2831 dev->stats.rx_errors++; 2832 atomic64_inc(&priv->extra_stats.rx_babr); 2833 2834 netif_dbg(priv, rx_err, dev, "babbling RX error\n"); 2835 } 2836 if (events & IEVENT_EBERR) { 2837 atomic64_inc(&priv->extra_stats.eberr); 2838 netif_dbg(priv, rx_err, dev, "bus error\n"); 2839 } 2840 if (events & IEVENT_RXC) 2841 netif_dbg(priv, rx_status, dev, "control frame\n"); 2842 2843 if (events & IEVENT_BABT) { 2844 atomic64_inc(&priv->extra_stats.tx_babt); 2845 netif_dbg(priv, tx_err, dev, "babbling TX error\n"); 2846 } 2847 return IRQ_HANDLED; 2848 } 2849 2850 /* The interrupt handler for devices with one interrupt */ 2851 static irqreturn_t gfar_interrupt(int irq, void *grp_id) 2852 { 2853 struct gfar_priv_grp *gfargrp = grp_id; 2854 2855 /* Save ievent for future reference */ 2856 u32 events = gfar_read(&gfargrp->regs->ievent); 2857 2858 /* Check for reception */ 2859 if (events & IEVENT_RX_MASK) 2860 gfar_receive(irq, grp_id); 2861 2862 /* Check for transmit completion */ 2863 if (events & IEVENT_TX_MASK) 2864 gfar_transmit(irq, grp_id); 2865 2866 /* Check for errors */ 2867 if (events & IEVENT_ERR_MASK) 2868 gfar_error(irq, grp_id); 2869 2870 return IRQ_HANDLED; 2871 } 2872 2873 #ifdef CONFIG_NET_POLL_CONTROLLER 2874 /* Polling 'interrupt' - used by things like netconsole to send skbs 2875 * without having to re-enable interrupts. It's not called while 2876 * the interrupt routine is executing. 2877 */ 2878 static void gfar_netpoll(struct net_device *dev) 2879 { 2880 struct gfar_private *priv = netdev_priv(dev); 2881 int i; 2882 2883 /* If the device has multiple interrupts, run tx/rx */ 2884 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 2885 for (i = 0; i < priv->num_grps; i++) { 2886 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 2887 2888 disable_irq(gfar_irq(grp, TX)->irq); 2889 disable_irq(gfar_irq(grp, RX)->irq); 2890 disable_irq(gfar_irq(grp, ER)->irq); 2891 gfar_interrupt(gfar_irq(grp, TX)->irq, grp); 2892 enable_irq(gfar_irq(grp, ER)->irq); 2893 enable_irq(gfar_irq(grp, RX)->irq); 2894 enable_irq(gfar_irq(grp, TX)->irq); 2895 } 2896 } else { 2897 for (i = 0; i < priv->num_grps; i++) { 2898 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 2899 2900 disable_irq(gfar_irq(grp, TX)->irq); 2901 gfar_interrupt(gfar_irq(grp, TX)->irq, grp); 2902 enable_irq(gfar_irq(grp, TX)->irq); 2903 } 2904 } 2905 } 2906 #endif 2907 2908 static void free_grp_irqs(struct gfar_priv_grp *grp) 2909 { 2910 free_irq(gfar_irq(grp, TX)->irq, grp); 2911 free_irq(gfar_irq(grp, RX)->irq, grp); 2912 free_irq(gfar_irq(grp, ER)->irq, grp); 2913 } 2914 2915 static int register_grp_irqs(struct gfar_priv_grp *grp) 2916 { 2917 struct gfar_private *priv = grp->priv; 2918 struct net_device *dev = priv->ndev; 2919 int err; 2920 2921 /* If the device has multiple interrupts, register for 2922 * them. Otherwise, only register for the one 2923 */ 2924 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 2925 /* Install our interrupt handlers for Error, 2926 * Transmit, and Receive 2927 */ 2928 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0, 2929 gfar_irq(grp, ER)->name, grp); 2930 if (err < 0) { 2931 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2932 gfar_irq(grp, ER)->irq); 2933 2934 goto err_irq_fail; 2935 } 2936 enable_irq_wake(gfar_irq(grp, ER)->irq); 2937 2938 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0, 2939 gfar_irq(grp, TX)->name, grp); 2940 if (err < 0) { 2941 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2942 gfar_irq(grp, TX)->irq); 2943 goto tx_irq_fail; 2944 } 2945 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0, 2946 gfar_irq(grp, RX)->name, grp); 2947 if (err < 0) { 2948 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2949 gfar_irq(grp, RX)->irq); 2950 goto rx_irq_fail; 2951 } 2952 enable_irq_wake(gfar_irq(grp, RX)->irq); 2953 2954 } else { 2955 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0, 2956 gfar_irq(grp, TX)->name, grp); 2957 if (err < 0) { 2958 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2959 gfar_irq(grp, TX)->irq); 2960 goto err_irq_fail; 2961 } 2962 enable_irq_wake(gfar_irq(grp, TX)->irq); 2963 } 2964 2965 return 0; 2966 2967 rx_irq_fail: 2968 free_irq(gfar_irq(grp, TX)->irq, grp); 2969 tx_irq_fail: 2970 free_irq(gfar_irq(grp, ER)->irq, grp); 2971 err_irq_fail: 2972 return err; 2973 2974 } 2975 2976 static void gfar_free_irq(struct gfar_private *priv) 2977 { 2978 int i; 2979 2980 /* Free the IRQs */ 2981 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 2982 for (i = 0; i < priv->num_grps; i++) 2983 free_grp_irqs(&priv->gfargrp[i]); 2984 } else { 2985 for (i = 0; i < priv->num_grps; i++) 2986 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq, 2987 &priv->gfargrp[i]); 2988 } 2989 } 2990 2991 static int gfar_request_irq(struct gfar_private *priv) 2992 { 2993 int err, i, j; 2994 2995 for (i = 0; i < priv->num_grps; i++) { 2996 err = register_grp_irqs(&priv->gfargrp[i]); 2997 if (err) { 2998 for (j = 0; j < i; j++) 2999 free_grp_irqs(&priv->gfargrp[j]); 3000 return err; 3001 } 3002 } 3003 3004 return 0; 3005 } 3006 3007 /* Called when something needs to use the ethernet device 3008 * Returns 0 for success. 3009 */ 3010 static int gfar_enet_open(struct net_device *dev) 3011 { 3012 struct gfar_private *priv = netdev_priv(dev); 3013 int err; 3014 3015 err = init_phy(dev); 3016 if (err) 3017 return err; 3018 3019 err = gfar_request_irq(priv); 3020 if (err) 3021 return err; 3022 3023 err = startup_gfar(dev); 3024 if (err) 3025 return err; 3026 3027 return err; 3028 } 3029 3030 /* Stops the kernel queue, and halts the controller */ 3031 static int gfar_close(struct net_device *dev) 3032 { 3033 struct gfar_private *priv = netdev_priv(dev); 3034 3035 cancel_work_sync(&priv->reset_task); 3036 stop_gfar(dev); 3037 3038 /* Disconnect from the PHY */ 3039 phy_disconnect(dev->phydev); 3040 3041 gfar_free_irq(priv); 3042 3043 return 0; 3044 } 3045 3046 /* Clears each of the exact match registers to zero, so they 3047 * don't interfere with normal reception 3048 */ 3049 static void gfar_clear_exact_match(struct net_device *dev) 3050 { 3051 int idx; 3052 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; 3053 3054 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++) 3055 gfar_set_mac_for_addr(dev, idx, zero_arr); 3056 } 3057 3058 /* Update the hash table based on the current list of multicast 3059 * addresses we subscribe to. Also, change the promiscuity of 3060 * the device based on the flags (this function is called 3061 * whenever dev->flags is changed 3062 */ 3063 static void gfar_set_multi(struct net_device *dev) 3064 { 3065 struct netdev_hw_addr *ha; 3066 struct gfar_private *priv = netdev_priv(dev); 3067 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3068 u32 tempval; 3069 3070 if (dev->flags & IFF_PROMISC) { 3071 /* Set RCTRL to PROM */ 3072 tempval = gfar_read(®s->rctrl); 3073 tempval |= RCTRL_PROM; 3074 gfar_write(®s->rctrl, tempval); 3075 } else { 3076 /* Set RCTRL to not PROM */ 3077 tempval = gfar_read(®s->rctrl); 3078 tempval &= ~(RCTRL_PROM); 3079 gfar_write(®s->rctrl, tempval); 3080 } 3081 3082 if (dev->flags & IFF_ALLMULTI) { 3083 /* Set the hash to rx all multicast frames */ 3084 gfar_write(®s->igaddr0, 0xffffffff); 3085 gfar_write(®s->igaddr1, 0xffffffff); 3086 gfar_write(®s->igaddr2, 0xffffffff); 3087 gfar_write(®s->igaddr3, 0xffffffff); 3088 gfar_write(®s->igaddr4, 0xffffffff); 3089 gfar_write(®s->igaddr5, 0xffffffff); 3090 gfar_write(®s->igaddr6, 0xffffffff); 3091 gfar_write(®s->igaddr7, 0xffffffff); 3092 gfar_write(®s->gaddr0, 0xffffffff); 3093 gfar_write(®s->gaddr1, 0xffffffff); 3094 gfar_write(®s->gaddr2, 0xffffffff); 3095 gfar_write(®s->gaddr3, 0xffffffff); 3096 gfar_write(®s->gaddr4, 0xffffffff); 3097 gfar_write(®s->gaddr5, 0xffffffff); 3098 gfar_write(®s->gaddr6, 0xffffffff); 3099 gfar_write(®s->gaddr7, 0xffffffff); 3100 } else { 3101 int em_num; 3102 int idx; 3103 3104 /* zero out the hash */ 3105 gfar_write(®s->igaddr0, 0x0); 3106 gfar_write(®s->igaddr1, 0x0); 3107 gfar_write(®s->igaddr2, 0x0); 3108 gfar_write(®s->igaddr3, 0x0); 3109 gfar_write(®s->igaddr4, 0x0); 3110 gfar_write(®s->igaddr5, 0x0); 3111 gfar_write(®s->igaddr6, 0x0); 3112 gfar_write(®s->igaddr7, 0x0); 3113 gfar_write(®s->gaddr0, 0x0); 3114 gfar_write(®s->gaddr1, 0x0); 3115 gfar_write(®s->gaddr2, 0x0); 3116 gfar_write(®s->gaddr3, 0x0); 3117 gfar_write(®s->gaddr4, 0x0); 3118 gfar_write(®s->gaddr5, 0x0); 3119 gfar_write(®s->gaddr6, 0x0); 3120 gfar_write(®s->gaddr7, 0x0); 3121 3122 /* If we have extended hash tables, we need to 3123 * clear the exact match registers to prepare for 3124 * setting them 3125 */ 3126 if (priv->extended_hash) { 3127 em_num = GFAR_EM_NUM + 1; 3128 gfar_clear_exact_match(dev); 3129 idx = 1; 3130 } else { 3131 idx = 0; 3132 em_num = 0; 3133 } 3134 3135 if (netdev_mc_empty(dev)) 3136 return; 3137 3138 /* Parse the list, and set the appropriate bits */ 3139 netdev_for_each_mc_addr(ha, dev) { 3140 if (idx < em_num) { 3141 gfar_set_mac_for_addr(dev, idx, ha->addr); 3142 idx++; 3143 } else 3144 gfar_set_hash_for_addr(dev, ha->addr); 3145 } 3146 } 3147 } 3148 3149 void gfar_mac_reset(struct gfar_private *priv) 3150 { 3151 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3152 u32 tempval; 3153 3154 /* Reset MAC layer */ 3155 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); 3156 3157 /* We need to delay at least 3 TX clocks */ 3158 udelay(3); 3159 3160 /* the soft reset bit is not self-resetting, so we need to 3161 * clear it before resuming normal operation 3162 */ 3163 gfar_write(®s->maccfg1, 0); 3164 3165 udelay(3); 3166 3167 gfar_rx_offload_en(priv); 3168 3169 /* Initialize the max receive frame/buffer lengths */ 3170 gfar_write(®s->maxfrm, GFAR_JUMBO_FRAME_SIZE); 3171 gfar_write(®s->mrblr, GFAR_RXB_SIZE); 3172 3173 /* Initialize the Minimum Frame Length Register */ 3174 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); 3175 3176 /* Initialize MACCFG2. */ 3177 tempval = MACCFG2_INIT_SETTINGS; 3178 3179 /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1 3180 * are marked as truncated. Avoid this by MACCFG2[Huge Frame]=1, 3181 * and by checking RxBD[LG] and discarding larger than MAXFRM. 3182 */ 3183 if (gfar_has_errata(priv, GFAR_ERRATA_74)) 3184 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; 3185 3186 gfar_write(®s->maccfg2, tempval); 3187 3188 /* Clear mac addr hash registers */ 3189 gfar_write(®s->igaddr0, 0); 3190 gfar_write(®s->igaddr1, 0); 3191 gfar_write(®s->igaddr2, 0); 3192 gfar_write(®s->igaddr3, 0); 3193 gfar_write(®s->igaddr4, 0); 3194 gfar_write(®s->igaddr5, 0); 3195 gfar_write(®s->igaddr6, 0); 3196 gfar_write(®s->igaddr7, 0); 3197 3198 gfar_write(®s->gaddr0, 0); 3199 gfar_write(®s->gaddr1, 0); 3200 gfar_write(®s->gaddr2, 0); 3201 gfar_write(®s->gaddr3, 0); 3202 gfar_write(®s->gaddr4, 0); 3203 gfar_write(®s->gaddr5, 0); 3204 gfar_write(®s->gaddr6, 0); 3205 gfar_write(®s->gaddr7, 0); 3206 3207 if (priv->extended_hash) 3208 gfar_clear_exact_match(priv->ndev); 3209 3210 gfar_mac_rx_config(priv); 3211 3212 gfar_mac_tx_config(priv); 3213 3214 gfar_set_mac_address(priv->ndev); 3215 3216 gfar_set_multi(priv->ndev); 3217 3218 /* clear ievent and imask before configuring coalescing */ 3219 gfar_ints_disable(priv); 3220 3221 /* Configure the coalescing support */ 3222 gfar_configure_coalescing_all(priv); 3223 } 3224 3225 static void gfar_hw_init(struct gfar_private *priv) 3226 { 3227 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3228 u32 attrs; 3229 3230 /* Stop the DMA engine now, in case it was running before 3231 * (The firmware could have used it, and left it running). 3232 */ 3233 gfar_halt(priv); 3234 3235 gfar_mac_reset(priv); 3236 3237 /* Zero out the rmon mib registers if it has them */ 3238 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { 3239 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib)); 3240 3241 /* Mask off the CAM interrupts */ 3242 gfar_write(®s->rmon.cam1, 0xffffffff); 3243 gfar_write(®s->rmon.cam2, 0xffffffff); 3244 } 3245 3246 /* Initialize ECNTRL */ 3247 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); 3248 3249 /* Set the extraction length and index */ 3250 attrs = ATTRELI_EL(priv->rx_stash_size) | 3251 ATTRELI_EI(priv->rx_stash_index); 3252 3253 gfar_write(®s->attreli, attrs); 3254 3255 /* Start with defaults, and add stashing 3256 * depending on driver parameters 3257 */ 3258 attrs = ATTR_INIT_SETTINGS; 3259 3260 if (priv->bd_stash_en) 3261 attrs |= ATTR_BDSTASH; 3262 3263 if (priv->rx_stash_size != 0) 3264 attrs |= ATTR_BUFSTASH; 3265 3266 gfar_write(®s->attr, attrs); 3267 3268 /* FIFO configs */ 3269 gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR); 3270 gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE); 3271 gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF); 3272 3273 /* Program the interrupt steering regs, only for MG devices */ 3274 if (priv->num_grps > 1) 3275 gfar_write_isrg(priv); 3276 } 3277 3278 static const struct net_device_ops gfar_netdev_ops = { 3279 .ndo_open = gfar_enet_open, 3280 .ndo_start_xmit = gfar_start_xmit, 3281 .ndo_stop = gfar_close, 3282 .ndo_change_mtu = gfar_change_mtu, 3283 .ndo_set_features = gfar_set_features, 3284 .ndo_set_rx_mode = gfar_set_multi, 3285 .ndo_tx_timeout = gfar_timeout, 3286 .ndo_do_ioctl = gfar_ioctl, 3287 .ndo_get_stats = gfar_get_stats, 3288 .ndo_change_carrier = fixed_phy_change_carrier, 3289 .ndo_set_mac_address = gfar_set_mac_addr, 3290 .ndo_validate_addr = eth_validate_addr, 3291 #ifdef CONFIG_NET_POLL_CONTROLLER 3292 .ndo_poll_controller = gfar_netpoll, 3293 #endif 3294 }; 3295 3296 /* Set up the ethernet device structure, private data, 3297 * and anything else we need before we start 3298 */ 3299 static int gfar_probe(struct platform_device *ofdev) 3300 { 3301 struct device_node *np = ofdev->dev.of_node; 3302 struct net_device *dev = NULL; 3303 struct gfar_private *priv = NULL; 3304 int err = 0, i; 3305 3306 err = gfar_of_init(ofdev, &dev); 3307 3308 if (err) 3309 return err; 3310 3311 priv = netdev_priv(dev); 3312 priv->ndev = dev; 3313 priv->ofdev = ofdev; 3314 priv->dev = &ofdev->dev; 3315 SET_NETDEV_DEV(dev, &ofdev->dev); 3316 3317 INIT_WORK(&priv->reset_task, gfar_reset_task); 3318 3319 platform_set_drvdata(ofdev, priv); 3320 3321 gfar_detect_errata(priv); 3322 3323 /* Set the dev->base_addr to the gfar reg region */ 3324 dev->base_addr = (unsigned long) priv->gfargrp[0].regs; 3325 3326 /* Fill in the dev structure */ 3327 dev->watchdog_timeo = TX_TIMEOUT; 3328 /* MTU range: 50 - 9586 */ 3329 dev->mtu = 1500; 3330 dev->min_mtu = 50; 3331 dev->max_mtu = GFAR_JUMBO_FRAME_SIZE - ETH_HLEN; 3332 dev->netdev_ops = &gfar_netdev_ops; 3333 dev->ethtool_ops = &gfar_ethtool_ops; 3334 3335 /* Register for napi ...We are registering NAPI for each grp */ 3336 for (i = 0; i < priv->num_grps; i++) { 3337 if (priv->poll_mode == GFAR_SQ_POLLING) { 3338 netif_napi_add(dev, &priv->gfargrp[i].napi_rx, 3339 gfar_poll_rx_sq, GFAR_DEV_WEIGHT); 3340 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx, 3341 gfar_poll_tx_sq, 2); 3342 } else { 3343 netif_napi_add(dev, &priv->gfargrp[i].napi_rx, 3344 gfar_poll_rx, GFAR_DEV_WEIGHT); 3345 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx, 3346 gfar_poll_tx, 2); 3347 } 3348 } 3349 3350 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { 3351 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | 3352 NETIF_F_RXCSUM; 3353 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | 3354 NETIF_F_RXCSUM | NETIF_F_HIGHDMA; 3355 } 3356 3357 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { 3358 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 3359 NETIF_F_HW_VLAN_CTAG_RX; 3360 dev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3361 } 3362 3363 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 3364 3365 gfar_init_addr_hash_table(priv); 3366 3367 /* Insert receive time stamps into padding alignment bytes, and 3368 * plus 2 bytes padding to ensure the cpu alignment. 3369 */ 3370 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) 3371 priv->padding = 8 + DEFAULT_PADDING; 3372 3373 if (dev->features & NETIF_F_IP_CSUM || 3374 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) 3375 dev->needed_headroom = GMAC_FCB_LEN; 3376 3377 /* Initializing some of the rx/tx queue level parameters */ 3378 for (i = 0; i < priv->num_tx_queues; i++) { 3379 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; 3380 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; 3381 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; 3382 priv->tx_queue[i]->txic = DEFAULT_TXIC; 3383 } 3384 3385 for (i = 0; i < priv->num_rx_queues; i++) { 3386 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; 3387 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; 3388 priv->rx_queue[i]->rxic = DEFAULT_RXIC; 3389 } 3390 3391 /* Always enable rx filer if available */ 3392 priv->rx_filer_enable = 3393 (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0; 3394 /* Enable most messages by default */ 3395 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; 3396 /* use pritority h/w tx queue scheduling for single queue devices */ 3397 if (priv->num_tx_queues == 1) 3398 priv->prio_sched_en = 1; 3399 3400 set_bit(GFAR_DOWN, &priv->state); 3401 3402 gfar_hw_init(priv); 3403 3404 /* Carrier starts down, phylib will bring it up */ 3405 netif_carrier_off(dev); 3406 3407 err = register_netdev(dev); 3408 3409 if (err) { 3410 pr_err("%s: Cannot register net device, aborting\n", dev->name); 3411 goto register_fail; 3412 } 3413 3414 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) 3415 priv->wol_supported |= GFAR_WOL_MAGIC; 3416 3417 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) && 3418 priv->rx_filer_enable) 3419 priv->wol_supported |= GFAR_WOL_FILER_UCAST; 3420 3421 device_set_wakeup_capable(&ofdev->dev, priv->wol_supported); 3422 3423 /* fill out IRQ number and name fields */ 3424 for (i = 0; i < priv->num_grps; i++) { 3425 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 3426 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 3427 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s", 3428 dev->name, "_g", '0' + i, "_tx"); 3429 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s", 3430 dev->name, "_g", '0' + i, "_rx"); 3431 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s", 3432 dev->name, "_g", '0' + i, "_er"); 3433 } else 3434 strcpy(gfar_irq(grp, TX)->name, dev->name); 3435 } 3436 3437 /* Initialize the filer table */ 3438 gfar_init_filer_table(priv); 3439 3440 /* Print out the device info */ 3441 netdev_info(dev, "mac: %pM\n", dev->dev_addr); 3442 3443 /* Even more device info helps when determining which kernel 3444 * provided which set of benchmarks. 3445 */ 3446 netdev_info(dev, "Running with NAPI enabled\n"); 3447 for (i = 0; i < priv->num_rx_queues; i++) 3448 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n", 3449 i, priv->rx_queue[i]->rx_ring_size); 3450 for (i = 0; i < priv->num_tx_queues; i++) 3451 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n", 3452 i, priv->tx_queue[i]->tx_ring_size); 3453 3454 return 0; 3455 3456 register_fail: 3457 if (of_phy_is_fixed_link(np)) 3458 of_phy_deregister_fixed_link(np); 3459 unmap_group_regs(priv); 3460 gfar_free_rx_queues(priv); 3461 gfar_free_tx_queues(priv); 3462 of_node_put(priv->phy_node); 3463 of_node_put(priv->tbi_node); 3464 free_gfar_dev(priv); 3465 return err; 3466 } 3467 3468 static int gfar_remove(struct platform_device *ofdev) 3469 { 3470 struct gfar_private *priv = platform_get_drvdata(ofdev); 3471 struct device_node *np = ofdev->dev.of_node; 3472 3473 of_node_put(priv->phy_node); 3474 of_node_put(priv->tbi_node); 3475 3476 unregister_netdev(priv->ndev); 3477 3478 if (of_phy_is_fixed_link(np)) 3479 of_phy_deregister_fixed_link(np); 3480 3481 unmap_group_regs(priv); 3482 gfar_free_rx_queues(priv); 3483 gfar_free_tx_queues(priv); 3484 free_gfar_dev(priv); 3485 3486 return 0; 3487 } 3488 3489 #ifdef CONFIG_PM 3490 3491 static void __gfar_filer_disable(struct gfar_private *priv) 3492 { 3493 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3494 u32 temp; 3495 3496 temp = gfar_read(®s->rctrl); 3497 temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT); 3498 gfar_write(®s->rctrl, temp); 3499 } 3500 3501 static void __gfar_filer_enable(struct gfar_private *priv) 3502 { 3503 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3504 u32 temp; 3505 3506 temp = gfar_read(®s->rctrl); 3507 temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT; 3508 gfar_write(®s->rctrl, temp); 3509 } 3510 3511 /* Filer rules implementing wol capabilities */ 3512 static void gfar_filer_config_wol(struct gfar_private *priv) 3513 { 3514 unsigned int i; 3515 u32 rqfcr; 3516 3517 __gfar_filer_disable(priv); 3518 3519 /* clear the filer table, reject any packet by default */ 3520 rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH; 3521 for (i = 0; i <= MAX_FILER_IDX; i++) 3522 gfar_write_filer(priv, i, rqfcr, 0); 3523 3524 i = 0; 3525 if (priv->wol_opts & GFAR_WOL_FILER_UCAST) { 3526 /* unicast packet, accept it */ 3527 struct net_device *ndev = priv->ndev; 3528 /* get the default rx queue index */ 3529 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex; 3530 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) | 3531 (ndev->dev_addr[1] << 8) | 3532 ndev->dev_addr[2]; 3533 3534 rqfcr = (qindex << 10) | RQFCR_AND | 3535 RQFCR_CMP_EXACT | RQFCR_PID_DAH; 3536 3537 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr); 3538 3539 dest_mac_addr = (ndev->dev_addr[3] << 16) | 3540 (ndev->dev_addr[4] << 8) | 3541 ndev->dev_addr[5]; 3542 rqfcr = (qindex << 10) | RQFCR_GPI | 3543 RQFCR_CMP_EXACT | RQFCR_PID_DAL; 3544 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr); 3545 } 3546 3547 __gfar_filer_enable(priv); 3548 } 3549 3550 static void gfar_filer_restore_table(struct gfar_private *priv) 3551 { 3552 u32 rqfcr, rqfpr; 3553 unsigned int i; 3554 3555 __gfar_filer_disable(priv); 3556 3557 for (i = 0; i <= MAX_FILER_IDX; i++) { 3558 rqfcr = priv->ftp_rqfcr[i]; 3559 rqfpr = priv->ftp_rqfpr[i]; 3560 gfar_write_filer(priv, i, rqfcr, rqfpr); 3561 } 3562 3563 __gfar_filer_enable(priv); 3564 } 3565 3566 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */ 3567 static void gfar_start_wol_filer(struct gfar_private *priv) 3568 { 3569 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3570 u32 tempval; 3571 int i = 0; 3572 3573 /* Enable Rx hw queues */ 3574 gfar_write(®s->rqueue, priv->rqueue); 3575 3576 /* Initialize DMACTRL to have WWR and WOP */ 3577 tempval = gfar_read(®s->dmactrl); 3578 tempval |= DMACTRL_INIT_SETTINGS; 3579 gfar_write(®s->dmactrl, tempval); 3580 3581 /* Make sure we aren't stopped */ 3582 tempval = gfar_read(®s->dmactrl); 3583 tempval &= ~DMACTRL_GRS; 3584 gfar_write(®s->dmactrl, tempval); 3585 3586 for (i = 0; i < priv->num_grps; i++) { 3587 regs = priv->gfargrp[i].regs; 3588 /* Clear RHLT, so that the DMA starts polling now */ 3589 gfar_write(®s->rstat, priv->gfargrp[i].rstat); 3590 /* enable the Filer General Purpose Interrupt */ 3591 gfar_write(®s->imask, IMASK_FGPI); 3592 } 3593 3594 /* Enable Rx DMA */ 3595 tempval = gfar_read(®s->maccfg1); 3596 tempval |= MACCFG1_RX_EN; 3597 gfar_write(®s->maccfg1, tempval); 3598 } 3599 3600 static int gfar_suspend(struct device *dev) 3601 { 3602 struct gfar_private *priv = dev_get_drvdata(dev); 3603 struct net_device *ndev = priv->ndev; 3604 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3605 u32 tempval; 3606 u16 wol = priv->wol_opts; 3607 3608 if (!netif_running(ndev)) 3609 return 0; 3610 3611 disable_napi(priv); 3612 netif_tx_lock(ndev); 3613 netif_device_detach(ndev); 3614 netif_tx_unlock(ndev); 3615 3616 gfar_halt(priv); 3617 3618 if (wol & GFAR_WOL_MAGIC) { 3619 /* Enable interrupt on Magic Packet */ 3620 gfar_write(®s->imask, IMASK_MAG); 3621 3622 /* Enable Magic Packet mode */ 3623 tempval = gfar_read(®s->maccfg2); 3624 tempval |= MACCFG2_MPEN; 3625 gfar_write(®s->maccfg2, tempval); 3626 3627 /* re-enable the Rx block */ 3628 tempval = gfar_read(®s->maccfg1); 3629 tempval |= MACCFG1_RX_EN; 3630 gfar_write(®s->maccfg1, tempval); 3631 3632 } else if (wol & GFAR_WOL_FILER_UCAST) { 3633 gfar_filer_config_wol(priv); 3634 gfar_start_wol_filer(priv); 3635 3636 } else { 3637 phy_stop(ndev->phydev); 3638 } 3639 3640 return 0; 3641 } 3642 3643 static int gfar_resume(struct device *dev) 3644 { 3645 struct gfar_private *priv = dev_get_drvdata(dev); 3646 struct net_device *ndev = priv->ndev; 3647 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3648 u32 tempval; 3649 u16 wol = priv->wol_opts; 3650 3651 if (!netif_running(ndev)) 3652 return 0; 3653 3654 if (wol & GFAR_WOL_MAGIC) { 3655 /* Disable Magic Packet mode */ 3656 tempval = gfar_read(®s->maccfg2); 3657 tempval &= ~MACCFG2_MPEN; 3658 gfar_write(®s->maccfg2, tempval); 3659 3660 } else if (wol & GFAR_WOL_FILER_UCAST) { 3661 /* need to stop rx only, tx is already down */ 3662 gfar_halt(priv); 3663 gfar_filer_restore_table(priv); 3664 3665 } else { 3666 phy_start(ndev->phydev); 3667 } 3668 3669 gfar_start(priv); 3670 3671 netif_device_attach(ndev); 3672 enable_napi(priv); 3673 3674 return 0; 3675 } 3676 3677 static int gfar_restore(struct device *dev) 3678 { 3679 struct gfar_private *priv = dev_get_drvdata(dev); 3680 struct net_device *ndev = priv->ndev; 3681 3682 if (!netif_running(ndev)) { 3683 netif_device_attach(ndev); 3684 3685 return 0; 3686 } 3687 3688 gfar_init_bds(ndev); 3689 3690 gfar_mac_reset(priv); 3691 3692 gfar_init_tx_rx_base(priv); 3693 3694 gfar_start(priv); 3695 3696 priv->oldlink = 0; 3697 priv->oldspeed = 0; 3698 priv->oldduplex = -1; 3699 3700 if (ndev->phydev) 3701 phy_start(ndev->phydev); 3702 3703 netif_device_attach(ndev); 3704 enable_napi(priv); 3705 3706 return 0; 3707 } 3708 3709 static const struct dev_pm_ops gfar_pm_ops = { 3710 .suspend = gfar_suspend, 3711 .resume = gfar_resume, 3712 .freeze = gfar_suspend, 3713 .thaw = gfar_resume, 3714 .restore = gfar_restore, 3715 }; 3716 3717 #define GFAR_PM_OPS (&gfar_pm_ops) 3718 3719 #else 3720 3721 #define GFAR_PM_OPS NULL 3722 3723 #endif 3724 3725 static const struct of_device_id gfar_match[] = 3726 { 3727 { 3728 .type = "network", 3729 .compatible = "gianfar", 3730 }, 3731 { 3732 .compatible = "fsl,etsec2", 3733 }, 3734 {}, 3735 }; 3736 MODULE_DEVICE_TABLE(of, gfar_match); 3737 3738 /* Structure for a device driver */ 3739 static struct platform_driver gfar_driver = { 3740 .driver = { 3741 .name = "fsl-gianfar", 3742 .pm = GFAR_PM_OPS, 3743 .of_match_table = gfar_match, 3744 }, 3745 .probe = gfar_probe, 3746 .remove = gfar_remove, 3747 }; 3748 3749 module_platform_driver(gfar_driver); 3750