1 /* drivers/net/ethernet/freescale/gianfar.c 2 * 3 * Gianfar Ethernet Driver 4 * This driver is designed for the non-CPM ethernet controllers 5 * on the 85xx and 83xx family of integrated processors 6 * Based on 8260_io/fcc_enet.c 7 * 8 * Author: Andy Fleming 9 * Maintainer: Kumar Gala 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 11 * 12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc. 13 * Copyright 2007 MontaVista Software, Inc. 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 * 20 * Gianfar: AKA Lambda Draconis, "Dragon" 21 * RA 11 31 24.2 22 * Dec +69 19 52 23 * V 3.84 24 * B-V +1.62 25 * 26 * Theory of operation 27 * 28 * The driver is initialized through of_device. Configuration information 29 * is therefore conveyed through an OF-style device tree. 30 * 31 * The Gianfar Ethernet Controller uses a ring of buffer 32 * descriptors. The beginning is indicated by a register 33 * pointing to the physical address of the start of the ring. 34 * The end is determined by a "wrap" bit being set in the 35 * last descriptor of the ring. 36 * 37 * When a packet is received, the RXF bit in the 38 * IEVENT register is set, triggering an interrupt when the 39 * corresponding bit in the IMASK register is also set (if 40 * interrupt coalescing is active, then the interrupt may not 41 * happen immediately, but will wait until either a set number 42 * of frames or amount of time have passed). In NAPI, the 43 * interrupt handler will signal there is work to be done, and 44 * exit. This method will start at the last known empty 45 * descriptor, and process every subsequent descriptor until there 46 * are none left with data (NAPI will stop after a set number of 47 * packets to give time to other tasks, but will eventually 48 * process all the packets). The data arrives inside a 49 * pre-allocated skb, and so after the skb is passed up to the 50 * stack, a new skb must be allocated, and the address field in 51 * the buffer descriptor must be updated to indicate this new 52 * skb. 53 * 54 * When the kernel requests that a packet be transmitted, the 55 * driver starts where it left off last time, and points the 56 * descriptor at the buffer which was passed in. The driver 57 * then informs the DMA engine that there are packets ready to 58 * be transmitted. Once the controller is finished transmitting 59 * the packet, an interrupt may be triggered (under the same 60 * conditions as for reception, but depending on the TXF bit). 61 * The driver then cleans up the buffer. 62 */ 63 64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 65 #define DEBUG 66 67 #include <linux/kernel.h> 68 #include <linux/string.h> 69 #include <linux/errno.h> 70 #include <linux/unistd.h> 71 #include <linux/slab.h> 72 #include <linux/interrupt.h> 73 #include <linux/delay.h> 74 #include <linux/netdevice.h> 75 #include <linux/etherdevice.h> 76 #include <linux/skbuff.h> 77 #include <linux/if_vlan.h> 78 #include <linux/spinlock.h> 79 #include <linux/mm.h> 80 #include <linux/of_address.h> 81 #include <linux/of_irq.h> 82 #include <linux/of_mdio.h> 83 #include <linux/of_platform.h> 84 #include <linux/ip.h> 85 #include <linux/tcp.h> 86 #include <linux/udp.h> 87 #include <linux/in.h> 88 #include <linux/net_tstamp.h> 89 90 #include <asm/io.h> 91 #ifdef CONFIG_PPC 92 #include <asm/reg.h> 93 #include <asm/mpc85xx.h> 94 #endif 95 #include <asm/irq.h> 96 #include <linux/uaccess.h> 97 #include <linux/module.h> 98 #include <linux/dma-mapping.h> 99 #include <linux/crc32.h> 100 #include <linux/mii.h> 101 #include <linux/phy.h> 102 #include <linux/phy_fixed.h> 103 #include <linux/of.h> 104 #include <linux/of_net.h> 105 106 #include "gianfar.h" 107 108 #define TX_TIMEOUT (5*HZ) 109 110 const char gfar_driver_version[] = "2.0"; 111 112 static int gfar_enet_open(struct net_device *dev); 113 static netdev_tx_t gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); 114 static void gfar_reset_task(struct work_struct *work); 115 static void gfar_timeout(struct net_device *dev); 116 static int gfar_close(struct net_device *dev); 117 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue, 118 int alloc_cnt); 119 static int gfar_set_mac_address(struct net_device *dev); 120 static int gfar_change_mtu(struct net_device *dev, int new_mtu); 121 static irqreturn_t gfar_error(int irq, void *dev_id); 122 static irqreturn_t gfar_transmit(int irq, void *dev_id); 123 static irqreturn_t gfar_interrupt(int irq, void *dev_id); 124 static void adjust_link(struct net_device *dev); 125 static noinline void gfar_update_link_state(struct gfar_private *priv); 126 static int init_phy(struct net_device *dev); 127 static int gfar_probe(struct platform_device *ofdev); 128 static int gfar_remove(struct platform_device *ofdev); 129 static void free_skb_resources(struct gfar_private *priv); 130 static void gfar_set_multi(struct net_device *dev); 131 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); 132 static void gfar_configure_serdes(struct net_device *dev); 133 static int gfar_poll_rx(struct napi_struct *napi, int budget); 134 static int gfar_poll_tx(struct napi_struct *napi, int budget); 135 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget); 136 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget); 137 #ifdef CONFIG_NET_POLL_CONTROLLER 138 static void gfar_netpoll(struct net_device *dev); 139 #endif 140 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); 141 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); 142 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb); 143 static void gfar_halt_nodisable(struct gfar_private *priv); 144 static void gfar_clear_exact_match(struct net_device *dev); 145 static void gfar_set_mac_for_addr(struct net_device *dev, int num, 146 const u8 *addr); 147 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 148 149 MODULE_AUTHOR("Freescale Semiconductor, Inc"); 150 MODULE_DESCRIPTION("Gianfar Ethernet Driver"); 151 MODULE_LICENSE("GPL"); 152 153 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, 154 dma_addr_t buf) 155 { 156 u32 lstatus; 157 158 bdp->bufPtr = cpu_to_be32(buf); 159 160 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); 161 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) 162 lstatus |= BD_LFLAG(RXBD_WRAP); 163 164 gfar_wmb(); 165 166 bdp->lstatus = cpu_to_be32(lstatus); 167 } 168 169 static void gfar_init_bds(struct net_device *ndev) 170 { 171 struct gfar_private *priv = netdev_priv(ndev); 172 struct gfar __iomem *regs = priv->gfargrp[0].regs; 173 struct gfar_priv_tx_q *tx_queue = NULL; 174 struct gfar_priv_rx_q *rx_queue = NULL; 175 struct txbd8 *txbdp; 176 u32 __iomem *rfbptr; 177 int i, j; 178 179 for (i = 0; i < priv->num_tx_queues; i++) { 180 tx_queue = priv->tx_queue[i]; 181 /* Initialize some variables in our dev structure */ 182 tx_queue->num_txbdfree = tx_queue->tx_ring_size; 183 tx_queue->dirty_tx = tx_queue->tx_bd_base; 184 tx_queue->cur_tx = tx_queue->tx_bd_base; 185 tx_queue->skb_curtx = 0; 186 tx_queue->skb_dirtytx = 0; 187 188 /* Initialize Transmit Descriptor Ring */ 189 txbdp = tx_queue->tx_bd_base; 190 for (j = 0; j < tx_queue->tx_ring_size; j++) { 191 txbdp->lstatus = 0; 192 txbdp->bufPtr = 0; 193 txbdp++; 194 } 195 196 /* Set the last descriptor in the ring to indicate wrap */ 197 txbdp--; 198 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) | 199 TXBD_WRAP); 200 } 201 202 rfbptr = ®s->rfbptr0; 203 for (i = 0; i < priv->num_rx_queues; i++) { 204 rx_queue = priv->rx_queue[i]; 205 206 rx_queue->next_to_clean = 0; 207 rx_queue->next_to_use = 0; 208 rx_queue->next_to_alloc = 0; 209 210 /* make sure next_to_clean != next_to_use after this 211 * by leaving at least 1 unused descriptor 212 */ 213 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue)); 214 215 rx_queue->rfbptr = rfbptr; 216 rfbptr += 2; 217 } 218 } 219 220 static int gfar_alloc_skb_resources(struct net_device *ndev) 221 { 222 void *vaddr; 223 dma_addr_t addr; 224 int i, j; 225 struct gfar_private *priv = netdev_priv(ndev); 226 struct device *dev = priv->dev; 227 struct gfar_priv_tx_q *tx_queue = NULL; 228 struct gfar_priv_rx_q *rx_queue = NULL; 229 230 priv->total_tx_ring_size = 0; 231 for (i = 0; i < priv->num_tx_queues; i++) 232 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; 233 234 priv->total_rx_ring_size = 0; 235 for (i = 0; i < priv->num_rx_queues; i++) 236 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; 237 238 /* Allocate memory for the buffer descriptors */ 239 vaddr = dma_alloc_coherent(dev, 240 (priv->total_tx_ring_size * 241 sizeof(struct txbd8)) + 242 (priv->total_rx_ring_size * 243 sizeof(struct rxbd8)), 244 &addr, GFP_KERNEL); 245 if (!vaddr) 246 return -ENOMEM; 247 248 for (i = 0; i < priv->num_tx_queues; i++) { 249 tx_queue = priv->tx_queue[i]; 250 tx_queue->tx_bd_base = vaddr; 251 tx_queue->tx_bd_dma_base = addr; 252 tx_queue->dev = ndev; 253 /* enet DMA only understands physical addresses */ 254 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; 255 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; 256 } 257 258 /* Start the rx descriptor ring where the tx ring leaves off */ 259 for (i = 0; i < priv->num_rx_queues; i++) { 260 rx_queue = priv->rx_queue[i]; 261 rx_queue->rx_bd_base = vaddr; 262 rx_queue->rx_bd_dma_base = addr; 263 rx_queue->ndev = ndev; 264 rx_queue->dev = dev; 265 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; 266 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; 267 } 268 269 /* Setup the skbuff rings */ 270 for (i = 0; i < priv->num_tx_queues; i++) { 271 tx_queue = priv->tx_queue[i]; 272 tx_queue->tx_skbuff = 273 kmalloc_array(tx_queue->tx_ring_size, 274 sizeof(*tx_queue->tx_skbuff), 275 GFP_KERNEL); 276 if (!tx_queue->tx_skbuff) 277 goto cleanup; 278 279 for (j = 0; j < tx_queue->tx_ring_size; j++) 280 tx_queue->tx_skbuff[j] = NULL; 281 } 282 283 for (i = 0; i < priv->num_rx_queues; i++) { 284 rx_queue = priv->rx_queue[i]; 285 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size, 286 sizeof(*rx_queue->rx_buff), 287 GFP_KERNEL); 288 if (!rx_queue->rx_buff) 289 goto cleanup; 290 } 291 292 gfar_init_bds(ndev); 293 294 return 0; 295 296 cleanup: 297 free_skb_resources(priv); 298 return -ENOMEM; 299 } 300 301 static void gfar_init_tx_rx_base(struct gfar_private *priv) 302 { 303 struct gfar __iomem *regs = priv->gfargrp[0].regs; 304 u32 __iomem *baddr; 305 int i; 306 307 baddr = ®s->tbase0; 308 for (i = 0; i < priv->num_tx_queues; i++) { 309 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); 310 baddr += 2; 311 } 312 313 baddr = ®s->rbase0; 314 for (i = 0; i < priv->num_rx_queues; i++) { 315 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); 316 baddr += 2; 317 } 318 } 319 320 static void gfar_init_rqprm(struct gfar_private *priv) 321 { 322 struct gfar __iomem *regs = priv->gfargrp[0].regs; 323 u32 __iomem *baddr; 324 int i; 325 326 baddr = ®s->rqprm0; 327 for (i = 0; i < priv->num_rx_queues; i++) { 328 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size | 329 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT)); 330 baddr++; 331 } 332 } 333 334 static void gfar_rx_offload_en(struct gfar_private *priv) 335 { 336 /* set this when rx hw offload (TOE) functions are being used */ 337 priv->uses_rxfcb = 0; 338 339 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) 340 priv->uses_rxfcb = 1; 341 342 if (priv->hwts_rx_en || priv->rx_filer_enable) 343 priv->uses_rxfcb = 1; 344 } 345 346 static void gfar_mac_rx_config(struct gfar_private *priv) 347 { 348 struct gfar __iomem *regs = priv->gfargrp[0].regs; 349 u32 rctrl = 0; 350 351 if (priv->rx_filer_enable) { 352 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT; 353 /* Program the RIR0 reg with the required distribution */ 354 if (priv->poll_mode == GFAR_SQ_POLLING) 355 gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0); 356 else /* GFAR_MQ_POLLING */ 357 gfar_write(®s->rir0, DEFAULT_8RXQ_RIR0); 358 } 359 360 /* Restore PROMISC mode */ 361 if (priv->ndev->flags & IFF_PROMISC) 362 rctrl |= RCTRL_PROM; 363 364 if (priv->ndev->features & NETIF_F_RXCSUM) 365 rctrl |= RCTRL_CHECKSUMMING; 366 367 if (priv->extended_hash) 368 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN; 369 370 if (priv->padding) { 371 rctrl &= ~RCTRL_PAL_MASK; 372 rctrl |= RCTRL_PADDING(priv->padding); 373 } 374 375 /* Enable HW time stamping if requested from user space */ 376 if (priv->hwts_rx_en) 377 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; 378 379 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) 380 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; 381 382 /* Clear the LFC bit */ 383 gfar_write(®s->rctrl, rctrl); 384 /* Init flow control threshold values */ 385 gfar_init_rqprm(priv); 386 gfar_write(®s->ptv, DEFAULT_LFC_PTVVAL); 387 rctrl |= RCTRL_LFC; 388 389 /* Init rctrl based on our settings */ 390 gfar_write(®s->rctrl, rctrl); 391 } 392 393 static void gfar_mac_tx_config(struct gfar_private *priv) 394 { 395 struct gfar __iomem *regs = priv->gfargrp[0].regs; 396 u32 tctrl = 0; 397 398 if (priv->ndev->features & NETIF_F_IP_CSUM) 399 tctrl |= TCTRL_INIT_CSUM; 400 401 if (priv->prio_sched_en) 402 tctrl |= TCTRL_TXSCHED_PRIO; 403 else { 404 tctrl |= TCTRL_TXSCHED_WRRS; 405 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT); 406 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT); 407 } 408 409 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX) 410 tctrl |= TCTRL_VLINS; 411 412 gfar_write(®s->tctrl, tctrl); 413 } 414 415 static void gfar_configure_coalescing(struct gfar_private *priv, 416 unsigned long tx_mask, unsigned long rx_mask) 417 { 418 struct gfar __iomem *regs = priv->gfargrp[0].regs; 419 u32 __iomem *baddr; 420 421 if (priv->mode == MQ_MG_MODE) { 422 int i = 0; 423 424 baddr = ®s->txic0; 425 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { 426 gfar_write(baddr + i, 0); 427 if (likely(priv->tx_queue[i]->txcoalescing)) 428 gfar_write(baddr + i, priv->tx_queue[i]->txic); 429 } 430 431 baddr = ®s->rxic0; 432 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { 433 gfar_write(baddr + i, 0); 434 if (likely(priv->rx_queue[i]->rxcoalescing)) 435 gfar_write(baddr + i, priv->rx_queue[i]->rxic); 436 } 437 } else { 438 /* Backward compatible case -- even if we enable 439 * multiple queues, there's only single reg to program 440 */ 441 gfar_write(®s->txic, 0); 442 if (likely(priv->tx_queue[0]->txcoalescing)) 443 gfar_write(®s->txic, priv->tx_queue[0]->txic); 444 445 gfar_write(®s->rxic, 0); 446 if (unlikely(priv->rx_queue[0]->rxcoalescing)) 447 gfar_write(®s->rxic, priv->rx_queue[0]->rxic); 448 } 449 } 450 451 void gfar_configure_coalescing_all(struct gfar_private *priv) 452 { 453 gfar_configure_coalescing(priv, 0xFF, 0xFF); 454 } 455 456 static struct net_device_stats *gfar_get_stats(struct net_device *dev) 457 { 458 struct gfar_private *priv = netdev_priv(dev); 459 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; 460 unsigned long tx_packets = 0, tx_bytes = 0; 461 int i; 462 463 for (i = 0; i < priv->num_rx_queues; i++) { 464 rx_packets += priv->rx_queue[i]->stats.rx_packets; 465 rx_bytes += priv->rx_queue[i]->stats.rx_bytes; 466 rx_dropped += priv->rx_queue[i]->stats.rx_dropped; 467 } 468 469 dev->stats.rx_packets = rx_packets; 470 dev->stats.rx_bytes = rx_bytes; 471 dev->stats.rx_dropped = rx_dropped; 472 473 for (i = 0; i < priv->num_tx_queues; i++) { 474 tx_bytes += priv->tx_queue[i]->stats.tx_bytes; 475 tx_packets += priv->tx_queue[i]->stats.tx_packets; 476 } 477 478 dev->stats.tx_bytes = tx_bytes; 479 dev->stats.tx_packets = tx_packets; 480 481 return &dev->stats; 482 } 483 484 static int gfar_set_mac_addr(struct net_device *dev, void *p) 485 { 486 eth_mac_addr(dev, p); 487 488 gfar_set_mac_for_addr(dev, 0, dev->dev_addr); 489 490 return 0; 491 } 492 493 static const struct net_device_ops gfar_netdev_ops = { 494 .ndo_open = gfar_enet_open, 495 .ndo_start_xmit = gfar_start_xmit, 496 .ndo_stop = gfar_close, 497 .ndo_change_mtu = gfar_change_mtu, 498 .ndo_set_features = gfar_set_features, 499 .ndo_set_rx_mode = gfar_set_multi, 500 .ndo_tx_timeout = gfar_timeout, 501 .ndo_do_ioctl = gfar_ioctl, 502 .ndo_get_stats = gfar_get_stats, 503 .ndo_set_mac_address = gfar_set_mac_addr, 504 .ndo_validate_addr = eth_validate_addr, 505 #ifdef CONFIG_NET_POLL_CONTROLLER 506 .ndo_poll_controller = gfar_netpoll, 507 #endif 508 }; 509 510 static void gfar_ints_disable(struct gfar_private *priv) 511 { 512 int i; 513 for (i = 0; i < priv->num_grps; i++) { 514 struct gfar __iomem *regs = priv->gfargrp[i].regs; 515 /* Clear IEVENT */ 516 gfar_write(®s->ievent, IEVENT_INIT_CLEAR); 517 518 /* Initialize IMASK */ 519 gfar_write(®s->imask, IMASK_INIT_CLEAR); 520 } 521 } 522 523 static void gfar_ints_enable(struct gfar_private *priv) 524 { 525 int i; 526 for (i = 0; i < priv->num_grps; i++) { 527 struct gfar __iomem *regs = priv->gfargrp[i].regs; 528 /* Unmask the interrupts we look for */ 529 gfar_write(®s->imask, IMASK_DEFAULT); 530 } 531 } 532 533 static int gfar_alloc_tx_queues(struct gfar_private *priv) 534 { 535 int i; 536 537 for (i = 0; i < priv->num_tx_queues; i++) { 538 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), 539 GFP_KERNEL); 540 if (!priv->tx_queue[i]) 541 return -ENOMEM; 542 543 priv->tx_queue[i]->tx_skbuff = NULL; 544 priv->tx_queue[i]->qindex = i; 545 priv->tx_queue[i]->dev = priv->ndev; 546 spin_lock_init(&(priv->tx_queue[i]->txlock)); 547 } 548 return 0; 549 } 550 551 static int gfar_alloc_rx_queues(struct gfar_private *priv) 552 { 553 int i; 554 555 for (i = 0; i < priv->num_rx_queues; i++) { 556 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), 557 GFP_KERNEL); 558 if (!priv->rx_queue[i]) 559 return -ENOMEM; 560 561 priv->rx_queue[i]->qindex = i; 562 priv->rx_queue[i]->ndev = priv->ndev; 563 } 564 return 0; 565 } 566 567 static void gfar_free_tx_queues(struct gfar_private *priv) 568 { 569 int i; 570 571 for (i = 0; i < priv->num_tx_queues; i++) 572 kfree(priv->tx_queue[i]); 573 } 574 575 static void gfar_free_rx_queues(struct gfar_private *priv) 576 { 577 int i; 578 579 for (i = 0; i < priv->num_rx_queues; i++) 580 kfree(priv->rx_queue[i]); 581 } 582 583 static void unmap_group_regs(struct gfar_private *priv) 584 { 585 int i; 586 587 for (i = 0; i < MAXGROUPS; i++) 588 if (priv->gfargrp[i].regs) 589 iounmap(priv->gfargrp[i].regs); 590 } 591 592 static void free_gfar_dev(struct gfar_private *priv) 593 { 594 int i, j; 595 596 for (i = 0; i < priv->num_grps; i++) 597 for (j = 0; j < GFAR_NUM_IRQS; j++) { 598 kfree(priv->gfargrp[i].irqinfo[j]); 599 priv->gfargrp[i].irqinfo[j] = NULL; 600 } 601 602 free_netdev(priv->ndev); 603 } 604 605 static void disable_napi(struct gfar_private *priv) 606 { 607 int i; 608 609 for (i = 0; i < priv->num_grps; i++) { 610 napi_disable(&priv->gfargrp[i].napi_rx); 611 napi_disable(&priv->gfargrp[i].napi_tx); 612 } 613 } 614 615 static void enable_napi(struct gfar_private *priv) 616 { 617 int i; 618 619 for (i = 0; i < priv->num_grps; i++) { 620 napi_enable(&priv->gfargrp[i].napi_rx); 621 napi_enable(&priv->gfargrp[i].napi_tx); 622 } 623 } 624 625 static int gfar_parse_group(struct device_node *np, 626 struct gfar_private *priv, const char *model) 627 { 628 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps]; 629 int i; 630 631 for (i = 0; i < GFAR_NUM_IRQS; i++) { 632 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo), 633 GFP_KERNEL); 634 if (!grp->irqinfo[i]) 635 return -ENOMEM; 636 } 637 638 grp->regs = of_iomap(np, 0); 639 if (!grp->regs) 640 return -ENOMEM; 641 642 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0); 643 644 /* If we aren't the FEC we have multiple interrupts */ 645 if (model && strcasecmp(model, "FEC")) { 646 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1); 647 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2); 648 if (!gfar_irq(grp, TX)->irq || 649 !gfar_irq(grp, RX)->irq || 650 !gfar_irq(grp, ER)->irq) 651 return -EINVAL; 652 } 653 654 grp->priv = priv; 655 spin_lock_init(&grp->grplock); 656 if (priv->mode == MQ_MG_MODE) { 657 u32 rxq_mask, txq_mask; 658 int ret; 659 660 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps); 661 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps); 662 663 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask); 664 if (!ret) { 665 grp->rx_bit_map = rxq_mask ? 666 rxq_mask : (DEFAULT_MAPPING >> priv->num_grps); 667 } 668 669 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask); 670 if (!ret) { 671 grp->tx_bit_map = txq_mask ? 672 txq_mask : (DEFAULT_MAPPING >> priv->num_grps); 673 } 674 675 if (priv->poll_mode == GFAR_SQ_POLLING) { 676 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */ 677 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps); 678 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps); 679 } 680 } else { 681 grp->rx_bit_map = 0xFF; 682 grp->tx_bit_map = 0xFF; 683 } 684 685 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses 686 * right to left, so we need to revert the 8 bits to get the q index 687 */ 688 grp->rx_bit_map = bitrev8(grp->rx_bit_map); 689 grp->tx_bit_map = bitrev8(grp->tx_bit_map); 690 691 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, 692 * also assign queues to groups 693 */ 694 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) { 695 if (!grp->rx_queue) 696 grp->rx_queue = priv->rx_queue[i]; 697 grp->num_rx_queues++; 698 grp->rstat |= (RSTAT_CLEAR_RHALT >> i); 699 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i); 700 priv->rx_queue[i]->grp = grp; 701 } 702 703 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) { 704 if (!grp->tx_queue) 705 grp->tx_queue = priv->tx_queue[i]; 706 grp->num_tx_queues++; 707 grp->tstat |= (TSTAT_CLEAR_THALT >> i); 708 priv->tqueue |= (TQUEUE_EN0 >> i); 709 priv->tx_queue[i]->grp = grp; 710 } 711 712 priv->num_grps++; 713 714 return 0; 715 } 716 717 static int gfar_of_group_count(struct device_node *np) 718 { 719 struct device_node *child; 720 int num = 0; 721 722 for_each_available_child_of_node(np, child) 723 if (of_node_name_eq(child, "queue-group")) 724 num++; 725 726 return num; 727 } 728 729 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) 730 { 731 const char *model; 732 const char *ctype; 733 const void *mac_addr; 734 int err = 0, i; 735 struct net_device *dev = NULL; 736 struct gfar_private *priv = NULL; 737 struct device_node *np = ofdev->dev.of_node; 738 struct device_node *child = NULL; 739 u32 stash_len = 0; 740 u32 stash_idx = 0; 741 unsigned int num_tx_qs, num_rx_qs; 742 unsigned short mode, poll_mode; 743 744 if (!np) 745 return -ENODEV; 746 747 if (of_device_is_compatible(np, "fsl,etsec2")) { 748 mode = MQ_MG_MODE; 749 poll_mode = GFAR_SQ_POLLING; 750 } else { 751 mode = SQ_SG_MODE; 752 poll_mode = GFAR_SQ_POLLING; 753 } 754 755 if (mode == SQ_SG_MODE) { 756 num_tx_qs = 1; 757 num_rx_qs = 1; 758 } else { /* MQ_MG_MODE */ 759 /* get the actual number of supported groups */ 760 unsigned int num_grps = gfar_of_group_count(np); 761 762 if (num_grps == 0 || num_grps > MAXGROUPS) { 763 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n", 764 num_grps); 765 pr_err("Cannot do alloc_etherdev, aborting\n"); 766 return -EINVAL; 767 } 768 769 if (poll_mode == GFAR_SQ_POLLING) { 770 num_tx_qs = num_grps; /* one txq per int group */ 771 num_rx_qs = num_grps; /* one rxq per int group */ 772 } else { /* GFAR_MQ_POLLING */ 773 u32 tx_queues, rx_queues; 774 int ret; 775 776 /* parse the num of HW tx and rx queues */ 777 ret = of_property_read_u32(np, "fsl,num_tx_queues", 778 &tx_queues); 779 num_tx_qs = ret ? 1 : tx_queues; 780 781 ret = of_property_read_u32(np, "fsl,num_rx_queues", 782 &rx_queues); 783 num_rx_qs = ret ? 1 : rx_queues; 784 } 785 } 786 787 if (num_tx_qs > MAX_TX_QS) { 788 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", 789 num_tx_qs, MAX_TX_QS); 790 pr_err("Cannot do alloc_etherdev, aborting\n"); 791 return -EINVAL; 792 } 793 794 if (num_rx_qs > MAX_RX_QS) { 795 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", 796 num_rx_qs, MAX_RX_QS); 797 pr_err("Cannot do alloc_etherdev, aborting\n"); 798 return -EINVAL; 799 } 800 801 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); 802 dev = *pdev; 803 if (NULL == dev) 804 return -ENOMEM; 805 806 priv = netdev_priv(dev); 807 priv->ndev = dev; 808 809 priv->mode = mode; 810 priv->poll_mode = poll_mode; 811 812 priv->num_tx_queues = num_tx_qs; 813 netif_set_real_num_rx_queues(dev, num_rx_qs); 814 priv->num_rx_queues = num_rx_qs; 815 816 err = gfar_alloc_tx_queues(priv); 817 if (err) 818 goto tx_alloc_failed; 819 820 err = gfar_alloc_rx_queues(priv); 821 if (err) 822 goto rx_alloc_failed; 823 824 err = of_property_read_string(np, "model", &model); 825 if (err) { 826 pr_err("Device model property missing, aborting\n"); 827 goto rx_alloc_failed; 828 } 829 830 /* Init Rx queue filer rule set linked list */ 831 INIT_LIST_HEAD(&priv->rx_list.list); 832 priv->rx_list.count = 0; 833 mutex_init(&priv->rx_queue_access); 834 835 for (i = 0; i < MAXGROUPS; i++) 836 priv->gfargrp[i].regs = NULL; 837 838 /* Parse and initialize group specific information */ 839 if (priv->mode == MQ_MG_MODE) { 840 for_each_available_child_of_node(np, child) { 841 if (!of_node_name_eq(child, "queue-group")) 842 continue; 843 844 err = gfar_parse_group(child, priv, model); 845 if (err) 846 goto err_grp_init; 847 } 848 } else { /* SQ_SG_MODE */ 849 err = gfar_parse_group(np, priv, model); 850 if (err) 851 goto err_grp_init; 852 } 853 854 if (of_property_read_bool(np, "bd-stash")) { 855 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; 856 priv->bd_stash_en = 1; 857 } 858 859 err = of_property_read_u32(np, "rx-stash-len", &stash_len); 860 861 if (err == 0) 862 priv->rx_stash_size = stash_len; 863 864 err = of_property_read_u32(np, "rx-stash-idx", &stash_idx); 865 866 if (err == 0) 867 priv->rx_stash_index = stash_idx; 868 869 if (stash_len || stash_idx) 870 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; 871 872 mac_addr = of_get_mac_address(np); 873 874 if (mac_addr) 875 memcpy(dev->dev_addr, mac_addr, ETH_ALEN); 876 877 if (model && !strcasecmp(model, "TSEC")) 878 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT | 879 FSL_GIANFAR_DEV_HAS_COALESCE | 880 FSL_GIANFAR_DEV_HAS_RMON | 881 FSL_GIANFAR_DEV_HAS_MULTI_INTR; 882 883 if (model && !strcasecmp(model, "eTSEC")) 884 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT | 885 FSL_GIANFAR_DEV_HAS_COALESCE | 886 FSL_GIANFAR_DEV_HAS_RMON | 887 FSL_GIANFAR_DEV_HAS_MULTI_INTR | 888 FSL_GIANFAR_DEV_HAS_CSUM | 889 FSL_GIANFAR_DEV_HAS_VLAN | 890 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | 891 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | 892 FSL_GIANFAR_DEV_HAS_TIMER | 893 FSL_GIANFAR_DEV_HAS_RX_FILER; 894 895 err = of_property_read_string(np, "phy-connection-type", &ctype); 896 897 /* We only care about rgmii-id. The rest are autodetected */ 898 if (err == 0 && !strcmp(ctype, "rgmii-id")) 899 priv->interface = PHY_INTERFACE_MODE_RGMII_ID; 900 else 901 priv->interface = PHY_INTERFACE_MODE_MII; 902 903 if (of_find_property(np, "fsl,magic-packet", NULL)) 904 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; 905 906 if (of_get_property(np, "fsl,wake-on-filer", NULL)) 907 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER; 908 909 priv->phy_node = of_parse_phandle(np, "phy-handle", 0); 910 911 /* In the case of a fixed PHY, the DT node associated 912 * to the PHY is the Ethernet MAC DT node. 913 */ 914 if (!priv->phy_node && of_phy_is_fixed_link(np)) { 915 err = of_phy_register_fixed_link(np); 916 if (err) 917 goto err_grp_init; 918 919 priv->phy_node = of_node_get(np); 920 } 921 922 /* Find the TBI PHY. If it's not there, we don't support SGMII */ 923 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); 924 925 return 0; 926 927 err_grp_init: 928 unmap_group_regs(priv); 929 rx_alloc_failed: 930 gfar_free_rx_queues(priv); 931 tx_alloc_failed: 932 gfar_free_tx_queues(priv); 933 free_gfar_dev(priv); 934 return err; 935 } 936 937 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 938 { 939 struct hwtstamp_config config; 940 struct gfar_private *priv = netdev_priv(netdev); 941 942 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 943 return -EFAULT; 944 945 /* reserved for future extensions */ 946 if (config.flags) 947 return -EINVAL; 948 949 switch (config.tx_type) { 950 case HWTSTAMP_TX_OFF: 951 priv->hwts_tx_en = 0; 952 break; 953 case HWTSTAMP_TX_ON: 954 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) 955 return -ERANGE; 956 priv->hwts_tx_en = 1; 957 break; 958 default: 959 return -ERANGE; 960 } 961 962 switch (config.rx_filter) { 963 case HWTSTAMP_FILTER_NONE: 964 if (priv->hwts_rx_en) { 965 priv->hwts_rx_en = 0; 966 reset_gfar(netdev); 967 } 968 break; 969 default: 970 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) 971 return -ERANGE; 972 if (!priv->hwts_rx_en) { 973 priv->hwts_rx_en = 1; 974 reset_gfar(netdev); 975 } 976 config.rx_filter = HWTSTAMP_FILTER_ALL; 977 break; 978 } 979 980 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 981 -EFAULT : 0; 982 } 983 984 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 985 { 986 struct hwtstamp_config config; 987 struct gfar_private *priv = netdev_priv(netdev); 988 989 config.flags = 0; 990 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 991 config.rx_filter = (priv->hwts_rx_en ? 992 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE); 993 994 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 995 -EFAULT : 0; 996 } 997 998 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 999 { 1000 struct phy_device *phydev = dev->phydev; 1001 1002 if (!netif_running(dev)) 1003 return -EINVAL; 1004 1005 if (cmd == SIOCSHWTSTAMP) 1006 return gfar_hwtstamp_set(dev, rq); 1007 if (cmd == SIOCGHWTSTAMP) 1008 return gfar_hwtstamp_get(dev, rq); 1009 1010 if (!phydev) 1011 return -ENODEV; 1012 1013 return phy_mii_ioctl(phydev, rq, cmd); 1014 } 1015 1016 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, 1017 u32 class) 1018 { 1019 u32 rqfpr = FPR_FILER_MASK; 1020 u32 rqfcr = 0x0; 1021 1022 rqfar--; 1023 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; 1024 priv->ftp_rqfpr[rqfar] = rqfpr; 1025 priv->ftp_rqfcr[rqfar] = rqfcr; 1026 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1027 1028 rqfar--; 1029 rqfcr = RQFCR_CMP_NOMATCH; 1030 priv->ftp_rqfpr[rqfar] = rqfpr; 1031 priv->ftp_rqfcr[rqfar] = rqfcr; 1032 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1033 1034 rqfar--; 1035 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; 1036 rqfpr = class; 1037 priv->ftp_rqfcr[rqfar] = rqfcr; 1038 priv->ftp_rqfpr[rqfar] = rqfpr; 1039 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1040 1041 rqfar--; 1042 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; 1043 rqfpr = class; 1044 priv->ftp_rqfcr[rqfar] = rqfcr; 1045 priv->ftp_rqfpr[rqfar] = rqfpr; 1046 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1047 1048 return rqfar; 1049 } 1050 1051 static void gfar_init_filer_table(struct gfar_private *priv) 1052 { 1053 int i = 0x0; 1054 u32 rqfar = MAX_FILER_IDX; 1055 u32 rqfcr = 0x0; 1056 u32 rqfpr = FPR_FILER_MASK; 1057 1058 /* Default rule */ 1059 rqfcr = RQFCR_CMP_MATCH; 1060 priv->ftp_rqfcr[rqfar] = rqfcr; 1061 priv->ftp_rqfpr[rqfar] = rqfpr; 1062 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1063 1064 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); 1065 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); 1066 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); 1067 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); 1068 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); 1069 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); 1070 1071 /* cur_filer_idx indicated the first non-masked rule */ 1072 priv->cur_filer_idx = rqfar; 1073 1074 /* Rest are masked rules */ 1075 rqfcr = RQFCR_CMP_NOMATCH; 1076 for (i = 0; i < rqfar; i++) { 1077 priv->ftp_rqfcr[i] = rqfcr; 1078 priv->ftp_rqfpr[i] = rqfpr; 1079 gfar_write_filer(priv, i, rqfcr, rqfpr); 1080 } 1081 } 1082 1083 #ifdef CONFIG_PPC 1084 static void __gfar_detect_errata_83xx(struct gfar_private *priv) 1085 { 1086 unsigned int pvr = mfspr(SPRN_PVR); 1087 unsigned int svr = mfspr(SPRN_SVR); 1088 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ 1089 unsigned int rev = svr & 0xffff; 1090 1091 /* MPC8313 Rev 2.0 and higher; All MPC837x */ 1092 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || 1093 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) 1094 priv->errata |= GFAR_ERRATA_74; 1095 1096 /* MPC8313 and MPC837x all rev */ 1097 if ((pvr == 0x80850010 && mod == 0x80b0) || 1098 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) 1099 priv->errata |= GFAR_ERRATA_76; 1100 1101 /* MPC8313 Rev < 2.0 */ 1102 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) 1103 priv->errata |= GFAR_ERRATA_12; 1104 } 1105 1106 static void __gfar_detect_errata_85xx(struct gfar_private *priv) 1107 { 1108 unsigned int svr = mfspr(SPRN_SVR); 1109 1110 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20)) 1111 priv->errata |= GFAR_ERRATA_12; 1112 /* P2020/P1010 Rev 1; MPC8548 Rev 2 */ 1113 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) || 1114 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) || 1115 ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31))) 1116 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */ 1117 } 1118 #endif 1119 1120 static void gfar_detect_errata(struct gfar_private *priv) 1121 { 1122 struct device *dev = &priv->ofdev->dev; 1123 1124 /* no plans to fix */ 1125 priv->errata |= GFAR_ERRATA_A002; 1126 1127 #ifdef CONFIG_PPC 1128 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)) 1129 __gfar_detect_errata_85xx(priv); 1130 else /* non-mpc85xx parts, i.e. e300 core based */ 1131 __gfar_detect_errata_83xx(priv); 1132 #endif 1133 1134 if (priv->errata) 1135 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", 1136 priv->errata); 1137 } 1138 1139 void gfar_mac_reset(struct gfar_private *priv) 1140 { 1141 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1142 u32 tempval; 1143 1144 /* Reset MAC layer */ 1145 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); 1146 1147 /* We need to delay at least 3 TX clocks */ 1148 udelay(3); 1149 1150 /* the soft reset bit is not self-resetting, so we need to 1151 * clear it before resuming normal operation 1152 */ 1153 gfar_write(®s->maccfg1, 0); 1154 1155 udelay(3); 1156 1157 gfar_rx_offload_en(priv); 1158 1159 /* Initialize the max receive frame/buffer lengths */ 1160 gfar_write(®s->maxfrm, GFAR_JUMBO_FRAME_SIZE); 1161 gfar_write(®s->mrblr, GFAR_RXB_SIZE); 1162 1163 /* Initialize the Minimum Frame Length Register */ 1164 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); 1165 1166 /* Initialize MACCFG2. */ 1167 tempval = MACCFG2_INIT_SETTINGS; 1168 1169 /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1 1170 * are marked as truncated. Avoid this by MACCFG2[Huge Frame]=1, 1171 * and by checking RxBD[LG] and discarding larger than MAXFRM. 1172 */ 1173 if (gfar_has_errata(priv, GFAR_ERRATA_74)) 1174 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; 1175 1176 gfar_write(®s->maccfg2, tempval); 1177 1178 /* Clear mac addr hash registers */ 1179 gfar_write(®s->igaddr0, 0); 1180 gfar_write(®s->igaddr1, 0); 1181 gfar_write(®s->igaddr2, 0); 1182 gfar_write(®s->igaddr3, 0); 1183 gfar_write(®s->igaddr4, 0); 1184 gfar_write(®s->igaddr5, 0); 1185 gfar_write(®s->igaddr6, 0); 1186 gfar_write(®s->igaddr7, 0); 1187 1188 gfar_write(®s->gaddr0, 0); 1189 gfar_write(®s->gaddr1, 0); 1190 gfar_write(®s->gaddr2, 0); 1191 gfar_write(®s->gaddr3, 0); 1192 gfar_write(®s->gaddr4, 0); 1193 gfar_write(®s->gaddr5, 0); 1194 gfar_write(®s->gaddr6, 0); 1195 gfar_write(®s->gaddr7, 0); 1196 1197 if (priv->extended_hash) 1198 gfar_clear_exact_match(priv->ndev); 1199 1200 gfar_mac_rx_config(priv); 1201 1202 gfar_mac_tx_config(priv); 1203 1204 gfar_set_mac_address(priv->ndev); 1205 1206 gfar_set_multi(priv->ndev); 1207 1208 /* clear ievent and imask before configuring coalescing */ 1209 gfar_ints_disable(priv); 1210 1211 /* Configure the coalescing support */ 1212 gfar_configure_coalescing_all(priv); 1213 } 1214 1215 static void gfar_hw_init(struct gfar_private *priv) 1216 { 1217 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1218 u32 attrs; 1219 1220 /* Stop the DMA engine now, in case it was running before 1221 * (The firmware could have used it, and left it running). 1222 */ 1223 gfar_halt(priv); 1224 1225 gfar_mac_reset(priv); 1226 1227 /* Zero out the rmon mib registers if it has them */ 1228 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { 1229 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib)); 1230 1231 /* Mask off the CAM interrupts */ 1232 gfar_write(®s->rmon.cam1, 0xffffffff); 1233 gfar_write(®s->rmon.cam2, 0xffffffff); 1234 } 1235 1236 /* Initialize ECNTRL */ 1237 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); 1238 1239 /* Set the extraction length and index */ 1240 attrs = ATTRELI_EL(priv->rx_stash_size) | 1241 ATTRELI_EI(priv->rx_stash_index); 1242 1243 gfar_write(®s->attreli, attrs); 1244 1245 /* Start with defaults, and add stashing 1246 * depending on driver parameters 1247 */ 1248 attrs = ATTR_INIT_SETTINGS; 1249 1250 if (priv->bd_stash_en) 1251 attrs |= ATTR_BDSTASH; 1252 1253 if (priv->rx_stash_size != 0) 1254 attrs |= ATTR_BUFSTASH; 1255 1256 gfar_write(®s->attr, attrs); 1257 1258 /* FIFO configs */ 1259 gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR); 1260 gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE); 1261 gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF); 1262 1263 /* Program the interrupt steering regs, only for MG devices */ 1264 if (priv->num_grps > 1) 1265 gfar_write_isrg(priv); 1266 } 1267 1268 static void gfar_init_addr_hash_table(struct gfar_private *priv) 1269 { 1270 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1271 1272 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { 1273 priv->extended_hash = 1; 1274 priv->hash_width = 9; 1275 1276 priv->hash_regs[0] = ®s->igaddr0; 1277 priv->hash_regs[1] = ®s->igaddr1; 1278 priv->hash_regs[2] = ®s->igaddr2; 1279 priv->hash_regs[3] = ®s->igaddr3; 1280 priv->hash_regs[4] = ®s->igaddr4; 1281 priv->hash_regs[5] = ®s->igaddr5; 1282 priv->hash_regs[6] = ®s->igaddr6; 1283 priv->hash_regs[7] = ®s->igaddr7; 1284 priv->hash_regs[8] = ®s->gaddr0; 1285 priv->hash_regs[9] = ®s->gaddr1; 1286 priv->hash_regs[10] = ®s->gaddr2; 1287 priv->hash_regs[11] = ®s->gaddr3; 1288 priv->hash_regs[12] = ®s->gaddr4; 1289 priv->hash_regs[13] = ®s->gaddr5; 1290 priv->hash_regs[14] = ®s->gaddr6; 1291 priv->hash_regs[15] = ®s->gaddr7; 1292 1293 } else { 1294 priv->extended_hash = 0; 1295 priv->hash_width = 8; 1296 1297 priv->hash_regs[0] = ®s->gaddr0; 1298 priv->hash_regs[1] = ®s->gaddr1; 1299 priv->hash_regs[2] = ®s->gaddr2; 1300 priv->hash_regs[3] = ®s->gaddr3; 1301 priv->hash_regs[4] = ®s->gaddr4; 1302 priv->hash_regs[5] = ®s->gaddr5; 1303 priv->hash_regs[6] = ®s->gaddr6; 1304 priv->hash_regs[7] = ®s->gaddr7; 1305 } 1306 } 1307 1308 /* Set up the ethernet device structure, private data, 1309 * and anything else we need before we start 1310 */ 1311 static int gfar_probe(struct platform_device *ofdev) 1312 { 1313 struct device_node *np = ofdev->dev.of_node; 1314 struct net_device *dev = NULL; 1315 struct gfar_private *priv = NULL; 1316 int err = 0, i; 1317 1318 err = gfar_of_init(ofdev, &dev); 1319 1320 if (err) 1321 return err; 1322 1323 priv = netdev_priv(dev); 1324 priv->ndev = dev; 1325 priv->ofdev = ofdev; 1326 priv->dev = &ofdev->dev; 1327 SET_NETDEV_DEV(dev, &ofdev->dev); 1328 1329 INIT_WORK(&priv->reset_task, gfar_reset_task); 1330 1331 platform_set_drvdata(ofdev, priv); 1332 1333 gfar_detect_errata(priv); 1334 1335 /* Set the dev->base_addr to the gfar reg region */ 1336 dev->base_addr = (unsigned long) priv->gfargrp[0].regs; 1337 1338 /* Fill in the dev structure */ 1339 dev->watchdog_timeo = TX_TIMEOUT; 1340 /* MTU range: 50 - 9586 */ 1341 dev->mtu = 1500; 1342 dev->min_mtu = 50; 1343 dev->max_mtu = GFAR_JUMBO_FRAME_SIZE - ETH_HLEN; 1344 dev->netdev_ops = &gfar_netdev_ops; 1345 dev->ethtool_ops = &gfar_ethtool_ops; 1346 1347 /* Register for napi ...We are registering NAPI for each grp */ 1348 for (i = 0; i < priv->num_grps; i++) { 1349 if (priv->poll_mode == GFAR_SQ_POLLING) { 1350 netif_napi_add(dev, &priv->gfargrp[i].napi_rx, 1351 gfar_poll_rx_sq, GFAR_DEV_WEIGHT); 1352 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx, 1353 gfar_poll_tx_sq, 2); 1354 } else { 1355 netif_napi_add(dev, &priv->gfargrp[i].napi_rx, 1356 gfar_poll_rx, GFAR_DEV_WEIGHT); 1357 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx, 1358 gfar_poll_tx, 2); 1359 } 1360 } 1361 1362 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { 1363 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | 1364 NETIF_F_RXCSUM; 1365 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | 1366 NETIF_F_RXCSUM | NETIF_F_HIGHDMA; 1367 } 1368 1369 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { 1370 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 1371 NETIF_F_HW_VLAN_CTAG_RX; 1372 dev->features |= NETIF_F_HW_VLAN_CTAG_RX; 1373 } 1374 1375 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 1376 1377 gfar_init_addr_hash_table(priv); 1378 1379 /* Insert receive time stamps into padding alignment bytes, and 1380 * plus 2 bytes padding to ensure the cpu alignment. 1381 */ 1382 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) 1383 priv->padding = 8 + DEFAULT_PADDING; 1384 1385 if (dev->features & NETIF_F_IP_CSUM || 1386 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) 1387 dev->needed_headroom = GMAC_FCB_LEN; 1388 1389 /* Initializing some of the rx/tx queue level parameters */ 1390 for (i = 0; i < priv->num_tx_queues; i++) { 1391 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; 1392 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; 1393 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; 1394 priv->tx_queue[i]->txic = DEFAULT_TXIC; 1395 } 1396 1397 for (i = 0; i < priv->num_rx_queues; i++) { 1398 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; 1399 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; 1400 priv->rx_queue[i]->rxic = DEFAULT_RXIC; 1401 } 1402 1403 /* Always enable rx filer if available */ 1404 priv->rx_filer_enable = 1405 (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0; 1406 /* Enable most messages by default */ 1407 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; 1408 /* use pritority h/w tx queue scheduling for single queue devices */ 1409 if (priv->num_tx_queues == 1) 1410 priv->prio_sched_en = 1; 1411 1412 set_bit(GFAR_DOWN, &priv->state); 1413 1414 gfar_hw_init(priv); 1415 1416 /* Carrier starts down, phylib will bring it up */ 1417 netif_carrier_off(dev); 1418 1419 err = register_netdev(dev); 1420 1421 if (err) { 1422 pr_err("%s: Cannot register net device, aborting\n", dev->name); 1423 goto register_fail; 1424 } 1425 1426 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) 1427 priv->wol_supported |= GFAR_WOL_MAGIC; 1428 1429 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) && 1430 priv->rx_filer_enable) 1431 priv->wol_supported |= GFAR_WOL_FILER_UCAST; 1432 1433 device_set_wakeup_capable(&ofdev->dev, priv->wol_supported); 1434 1435 /* fill out IRQ number and name fields */ 1436 for (i = 0; i < priv->num_grps; i++) { 1437 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 1438 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 1439 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s", 1440 dev->name, "_g", '0' + i, "_tx"); 1441 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s", 1442 dev->name, "_g", '0' + i, "_rx"); 1443 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s", 1444 dev->name, "_g", '0' + i, "_er"); 1445 } else 1446 strcpy(gfar_irq(grp, TX)->name, dev->name); 1447 } 1448 1449 /* Initialize the filer table */ 1450 gfar_init_filer_table(priv); 1451 1452 /* Print out the device info */ 1453 netdev_info(dev, "mac: %pM\n", dev->dev_addr); 1454 1455 /* Even more device info helps when determining which kernel 1456 * provided which set of benchmarks. 1457 */ 1458 netdev_info(dev, "Running with NAPI enabled\n"); 1459 for (i = 0; i < priv->num_rx_queues; i++) 1460 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n", 1461 i, priv->rx_queue[i]->rx_ring_size); 1462 for (i = 0; i < priv->num_tx_queues; i++) 1463 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n", 1464 i, priv->tx_queue[i]->tx_ring_size); 1465 1466 return 0; 1467 1468 register_fail: 1469 if (of_phy_is_fixed_link(np)) 1470 of_phy_deregister_fixed_link(np); 1471 unmap_group_regs(priv); 1472 gfar_free_rx_queues(priv); 1473 gfar_free_tx_queues(priv); 1474 of_node_put(priv->phy_node); 1475 of_node_put(priv->tbi_node); 1476 free_gfar_dev(priv); 1477 return err; 1478 } 1479 1480 static int gfar_remove(struct platform_device *ofdev) 1481 { 1482 struct gfar_private *priv = platform_get_drvdata(ofdev); 1483 struct device_node *np = ofdev->dev.of_node; 1484 1485 of_node_put(priv->phy_node); 1486 of_node_put(priv->tbi_node); 1487 1488 unregister_netdev(priv->ndev); 1489 1490 if (of_phy_is_fixed_link(np)) 1491 of_phy_deregister_fixed_link(np); 1492 1493 unmap_group_regs(priv); 1494 gfar_free_rx_queues(priv); 1495 gfar_free_tx_queues(priv); 1496 free_gfar_dev(priv); 1497 1498 return 0; 1499 } 1500 1501 #ifdef CONFIG_PM 1502 1503 static void __gfar_filer_disable(struct gfar_private *priv) 1504 { 1505 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1506 u32 temp; 1507 1508 temp = gfar_read(®s->rctrl); 1509 temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT); 1510 gfar_write(®s->rctrl, temp); 1511 } 1512 1513 static void __gfar_filer_enable(struct gfar_private *priv) 1514 { 1515 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1516 u32 temp; 1517 1518 temp = gfar_read(®s->rctrl); 1519 temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT; 1520 gfar_write(®s->rctrl, temp); 1521 } 1522 1523 /* Filer rules implementing wol capabilities */ 1524 static void gfar_filer_config_wol(struct gfar_private *priv) 1525 { 1526 unsigned int i; 1527 u32 rqfcr; 1528 1529 __gfar_filer_disable(priv); 1530 1531 /* clear the filer table, reject any packet by default */ 1532 rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH; 1533 for (i = 0; i <= MAX_FILER_IDX; i++) 1534 gfar_write_filer(priv, i, rqfcr, 0); 1535 1536 i = 0; 1537 if (priv->wol_opts & GFAR_WOL_FILER_UCAST) { 1538 /* unicast packet, accept it */ 1539 struct net_device *ndev = priv->ndev; 1540 /* get the default rx queue index */ 1541 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex; 1542 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) | 1543 (ndev->dev_addr[1] << 8) | 1544 ndev->dev_addr[2]; 1545 1546 rqfcr = (qindex << 10) | RQFCR_AND | 1547 RQFCR_CMP_EXACT | RQFCR_PID_DAH; 1548 1549 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr); 1550 1551 dest_mac_addr = (ndev->dev_addr[3] << 16) | 1552 (ndev->dev_addr[4] << 8) | 1553 ndev->dev_addr[5]; 1554 rqfcr = (qindex << 10) | RQFCR_GPI | 1555 RQFCR_CMP_EXACT | RQFCR_PID_DAL; 1556 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr); 1557 } 1558 1559 __gfar_filer_enable(priv); 1560 } 1561 1562 static void gfar_filer_restore_table(struct gfar_private *priv) 1563 { 1564 u32 rqfcr, rqfpr; 1565 unsigned int i; 1566 1567 __gfar_filer_disable(priv); 1568 1569 for (i = 0; i <= MAX_FILER_IDX; i++) { 1570 rqfcr = priv->ftp_rqfcr[i]; 1571 rqfpr = priv->ftp_rqfpr[i]; 1572 gfar_write_filer(priv, i, rqfcr, rqfpr); 1573 } 1574 1575 __gfar_filer_enable(priv); 1576 } 1577 1578 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */ 1579 static void gfar_start_wol_filer(struct gfar_private *priv) 1580 { 1581 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1582 u32 tempval; 1583 int i = 0; 1584 1585 /* Enable Rx hw queues */ 1586 gfar_write(®s->rqueue, priv->rqueue); 1587 1588 /* Initialize DMACTRL to have WWR and WOP */ 1589 tempval = gfar_read(®s->dmactrl); 1590 tempval |= DMACTRL_INIT_SETTINGS; 1591 gfar_write(®s->dmactrl, tempval); 1592 1593 /* Make sure we aren't stopped */ 1594 tempval = gfar_read(®s->dmactrl); 1595 tempval &= ~DMACTRL_GRS; 1596 gfar_write(®s->dmactrl, tempval); 1597 1598 for (i = 0; i < priv->num_grps; i++) { 1599 regs = priv->gfargrp[i].regs; 1600 /* Clear RHLT, so that the DMA starts polling now */ 1601 gfar_write(®s->rstat, priv->gfargrp[i].rstat); 1602 /* enable the Filer General Purpose Interrupt */ 1603 gfar_write(®s->imask, IMASK_FGPI); 1604 } 1605 1606 /* Enable Rx DMA */ 1607 tempval = gfar_read(®s->maccfg1); 1608 tempval |= MACCFG1_RX_EN; 1609 gfar_write(®s->maccfg1, tempval); 1610 } 1611 1612 static int gfar_suspend(struct device *dev) 1613 { 1614 struct gfar_private *priv = dev_get_drvdata(dev); 1615 struct net_device *ndev = priv->ndev; 1616 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1617 u32 tempval; 1618 u16 wol = priv->wol_opts; 1619 1620 if (!netif_running(ndev)) 1621 return 0; 1622 1623 disable_napi(priv); 1624 netif_tx_lock(ndev); 1625 netif_device_detach(ndev); 1626 netif_tx_unlock(ndev); 1627 1628 gfar_halt(priv); 1629 1630 if (wol & GFAR_WOL_MAGIC) { 1631 /* Enable interrupt on Magic Packet */ 1632 gfar_write(®s->imask, IMASK_MAG); 1633 1634 /* Enable Magic Packet mode */ 1635 tempval = gfar_read(®s->maccfg2); 1636 tempval |= MACCFG2_MPEN; 1637 gfar_write(®s->maccfg2, tempval); 1638 1639 /* re-enable the Rx block */ 1640 tempval = gfar_read(®s->maccfg1); 1641 tempval |= MACCFG1_RX_EN; 1642 gfar_write(®s->maccfg1, tempval); 1643 1644 } else if (wol & GFAR_WOL_FILER_UCAST) { 1645 gfar_filer_config_wol(priv); 1646 gfar_start_wol_filer(priv); 1647 1648 } else { 1649 phy_stop(ndev->phydev); 1650 } 1651 1652 return 0; 1653 } 1654 1655 static int gfar_resume(struct device *dev) 1656 { 1657 struct gfar_private *priv = dev_get_drvdata(dev); 1658 struct net_device *ndev = priv->ndev; 1659 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1660 u32 tempval; 1661 u16 wol = priv->wol_opts; 1662 1663 if (!netif_running(ndev)) 1664 return 0; 1665 1666 if (wol & GFAR_WOL_MAGIC) { 1667 /* Disable Magic Packet mode */ 1668 tempval = gfar_read(®s->maccfg2); 1669 tempval &= ~MACCFG2_MPEN; 1670 gfar_write(®s->maccfg2, tempval); 1671 1672 } else if (wol & GFAR_WOL_FILER_UCAST) { 1673 /* need to stop rx only, tx is already down */ 1674 gfar_halt(priv); 1675 gfar_filer_restore_table(priv); 1676 1677 } else { 1678 phy_start(ndev->phydev); 1679 } 1680 1681 gfar_start(priv); 1682 1683 netif_device_attach(ndev); 1684 enable_napi(priv); 1685 1686 return 0; 1687 } 1688 1689 static int gfar_restore(struct device *dev) 1690 { 1691 struct gfar_private *priv = dev_get_drvdata(dev); 1692 struct net_device *ndev = priv->ndev; 1693 1694 if (!netif_running(ndev)) { 1695 netif_device_attach(ndev); 1696 1697 return 0; 1698 } 1699 1700 gfar_init_bds(ndev); 1701 1702 gfar_mac_reset(priv); 1703 1704 gfar_init_tx_rx_base(priv); 1705 1706 gfar_start(priv); 1707 1708 priv->oldlink = 0; 1709 priv->oldspeed = 0; 1710 priv->oldduplex = -1; 1711 1712 if (ndev->phydev) 1713 phy_start(ndev->phydev); 1714 1715 netif_device_attach(ndev); 1716 enable_napi(priv); 1717 1718 return 0; 1719 } 1720 1721 static const struct dev_pm_ops gfar_pm_ops = { 1722 .suspend = gfar_suspend, 1723 .resume = gfar_resume, 1724 .freeze = gfar_suspend, 1725 .thaw = gfar_resume, 1726 .restore = gfar_restore, 1727 }; 1728 1729 #define GFAR_PM_OPS (&gfar_pm_ops) 1730 1731 #else 1732 1733 #define GFAR_PM_OPS NULL 1734 1735 #endif 1736 1737 /* Reads the controller's registers to determine what interface 1738 * connects it to the PHY. 1739 */ 1740 static phy_interface_t gfar_get_interface(struct net_device *dev) 1741 { 1742 struct gfar_private *priv = netdev_priv(dev); 1743 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1744 u32 ecntrl; 1745 1746 ecntrl = gfar_read(®s->ecntrl); 1747 1748 if (ecntrl & ECNTRL_SGMII_MODE) 1749 return PHY_INTERFACE_MODE_SGMII; 1750 1751 if (ecntrl & ECNTRL_TBI_MODE) { 1752 if (ecntrl & ECNTRL_REDUCED_MODE) 1753 return PHY_INTERFACE_MODE_RTBI; 1754 else 1755 return PHY_INTERFACE_MODE_TBI; 1756 } 1757 1758 if (ecntrl & ECNTRL_REDUCED_MODE) { 1759 if (ecntrl & ECNTRL_REDUCED_MII_MODE) { 1760 return PHY_INTERFACE_MODE_RMII; 1761 } 1762 else { 1763 phy_interface_t interface = priv->interface; 1764 1765 /* This isn't autodetected right now, so it must 1766 * be set by the device tree or platform code. 1767 */ 1768 if (interface == PHY_INTERFACE_MODE_RGMII_ID) 1769 return PHY_INTERFACE_MODE_RGMII_ID; 1770 1771 return PHY_INTERFACE_MODE_RGMII; 1772 } 1773 } 1774 1775 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) 1776 return PHY_INTERFACE_MODE_GMII; 1777 1778 return PHY_INTERFACE_MODE_MII; 1779 } 1780 1781 1782 /* Initializes driver's PHY state, and attaches to the PHY. 1783 * Returns 0 on success. 1784 */ 1785 static int init_phy(struct net_device *dev) 1786 { 1787 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1788 struct gfar_private *priv = netdev_priv(dev); 1789 phy_interface_t interface; 1790 struct phy_device *phydev; 1791 struct ethtool_eee edata; 1792 1793 linkmode_set_bit_array(phy_10_100_features_array, 1794 ARRAY_SIZE(phy_10_100_features_array), 1795 mask); 1796 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask); 1797 linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask); 1798 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) 1799 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mask); 1800 1801 priv->oldlink = 0; 1802 priv->oldspeed = 0; 1803 priv->oldduplex = -1; 1804 1805 interface = gfar_get_interface(dev); 1806 1807 phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, 1808 interface); 1809 if (!phydev) { 1810 dev_err(&dev->dev, "could not attach to PHY\n"); 1811 return -ENODEV; 1812 } 1813 1814 if (interface == PHY_INTERFACE_MODE_SGMII) 1815 gfar_configure_serdes(dev); 1816 1817 /* Remove any features not supported by the controller */ 1818 linkmode_and(phydev->supported, phydev->supported, mask); 1819 linkmode_copy(phydev->advertising, phydev->supported); 1820 1821 /* Add support for flow control */ 1822 phy_support_asym_pause(phydev); 1823 1824 /* disable EEE autoneg, EEE not supported by eTSEC */ 1825 memset(&edata, 0, sizeof(struct ethtool_eee)); 1826 phy_ethtool_set_eee(phydev, &edata); 1827 1828 return 0; 1829 } 1830 1831 /* Initialize TBI PHY interface for communicating with the 1832 * SERDES lynx PHY on the chip. We communicate with this PHY 1833 * through the MDIO bus on each controller, treating it as a 1834 * "normal" PHY at the address found in the TBIPA register. We assume 1835 * that the TBIPA register is valid. Either the MDIO bus code will set 1836 * it to a value that doesn't conflict with other PHYs on the bus, or the 1837 * value doesn't matter, as there are no other PHYs on the bus. 1838 */ 1839 static void gfar_configure_serdes(struct net_device *dev) 1840 { 1841 struct gfar_private *priv = netdev_priv(dev); 1842 struct phy_device *tbiphy; 1843 1844 if (!priv->tbi_node) { 1845 dev_warn(&dev->dev, "error: SGMII mode requires that the " 1846 "device tree specify a tbi-handle\n"); 1847 return; 1848 } 1849 1850 tbiphy = of_phy_find_device(priv->tbi_node); 1851 if (!tbiphy) { 1852 dev_err(&dev->dev, "error: Could not get TBI device\n"); 1853 return; 1854 } 1855 1856 /* If the link is already up, we must already be ok, and don't need to 1857 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured 1858 * everything for us? Resetting it takes the link down and requires 1859 * several seconds for it to come back. 1860 */ 1861 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) { 1862 put_device(&tbiphy->mdio.dev); 1863 return; 1864 } 1865 1866 /* Single clk mode, mii mode off(for serdes communication) */ 1867 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); 1868 1869 phy_write(tbiphy, MII_ADVERTISE, 1870 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | 1871 ADVERTISE_1000XPSE_ASYM); 1872 1873 phy_write(tbiphy, MII_BMCR, 1874 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | 1875 BMCR_SPEED1000); 1876 1877 put_device(&tbiphy->mdio.dev); 1878 } 1879 1880 static int __gfar_is_rx_idle(struct gfar_private *priv) 1881 { 1882 u32 res; 1883 1884 /* Normaly TSEC should not hang on GRS commands, so we should 1885 * actually wait for IEVENT_GRSC flag. 1886 */ 1887 if (!gfar_has_errata(priv, GFAR_ERRATA_A002)) 1888 return 0; 1889 1890 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are 1891 * the same as bits 23-30, the eTSEC Rx is assumed to be idle 1892 * and the Rx can be safely reset. 1893 */ 1894 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); 1895 res &= 0x7f807f80; 1896 if ((res & 0xffff) == (res >> 16)) 1897 return 1; 1898 1899 return 0; 1900 } 1901 1902 /* Halt the receive and transmit queues */ 1903 static void gfar_halt_nodisable(struct gfar_private *priv) 1904 { 1905 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1906 u32 tempval; 1907 unsigned int timeout; 1908 int stopped; 1909 1910 gfar_ints_disable(priv); 1911 1912 if (gfar_is_dma_stopped(priv)) 1913 return; 1914 1915 /* Stop the DMA, and wait for it to stop */ 1916 tempval = gfar_read(®s->dmactrl); 1917 tempval |= (DMACTRL_GRS | DMACTRL_GTS); 1918 gfar_write(®s->dmactrl, tempval); 1919 1920 retry: 1921 timeout = 1000; 1922 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) { 1923 cpu_relax(); 1924 timeout--; 1925 } 1926 1927 if (!timeout) 1928 stopped = gfar_is_dma_stopped(priv); 1929 1930 if (!stopped && !gfar_is_rx_dma_stopped(priv) && 1931 !__gfar_is_rx_idle(priv)) 1932 goto retry; 1933 } 1934 1935 /* Halt the receive and transmit queues */ 1936 void gfar_halt(struct gfar_private *priv) 1937 { 1938 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1939 u32 tempval; 1940 1941 /* Dissable the Rx/Tx hw queues */ 1942 gfar_write(®s->rqueue, 0); 1943 gfar_write(®s->tqueue, 0); 1944 1945 mdelay(10); 1946 1947 gfar_halt_nodisable(priv); 1948 1949 /* Disable Rx/Tx DMA */ 1950 tempval = gfar_read(®s->maccfg1); 1951 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); 1952 gfar_write(®s->maccfg1, tempval); 1953 } 1954 1955 void stop_gfar(struct net_device *dev) 1956 { 1957 struct gfar_private *priv = netdev_priv(dev); 1958 1959 netif_tx_stop_all_queues(dev); 1960 1961 smp_mb__before_atomic(); 1962 set_bit(GFAR_DOWN, &priv->state); 1963 smp_mb__after_atomic(); 1964 1965 disable_napi(priv); 1966 1967 /* disable ints and gracefully shut down Rx/Tx DMA */ 1968 gfar_halt(priv); 1969 1970 phy_stop(dev->phydev); 1971 1972 free_skb_resources(priv); 1973 } 1974 1975 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) 1976 { 1977 struct txbd8 *txbdp; 1978 struct gfar_private *priv = netdev_priv(tx_queue->dev); 1979 int i, j; 1980 1981 txbdp = tx_queue->tx_bd_base; 1982 1983 for (i = 0; i < tx_queue->tx_ring_size; i++) { 1984 if (!tx_queue->tx_skbuff[i]) 1985 continue; 1986 1987 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr), 1988 be16_to_cpu(txbdp->length), DMA_TO_DEVICE); 1989 txbdp->lstatus = 0; 1990 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; 1991 j++) { 1992 txbdp++; 1993 dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr), 1994 be16_to_cpu(txbdp->length), 1995 DMA_TO_DEVICE); 1996 } 1997 txbdp++; 1998 dev_kfree_skb_any(tx_queue->tx_skbuff[i]); 1999 tx_queue->tx_skbuff[i] = NULL; 2000 } 2001 kfree(tx_queue->tx_skbuff); 2002 tx_queue->tx_skbuff = NULL; 2003 } 2004 2005 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) 2006 { 2007 int i; 2008 2009 struct rxbd8 *rxbdp = rx_queue->rx_bd_base; 2010 2011 if (rx_queue->skb) 2012 dev_kfree_skb(rx_queue->skb); 2013 2014 for (i = 0; i < rx_queue->rx_ring_size; i++) { 2015 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[i]; 2016 2017 rxbdp->lstatus = 0; 2018 rxbdp->bufPtr = 0; 2019 rxbdp++; 2020 2021 if (!rxb->page) 2022 continue; 2023 2024 dma_unmap_page(rx_queue->dev, rxb->dma, 2025 PAGE_SIZE, DMA_FROM_DEVICE); 2026 __free_page(rxb->page); 2027 2028 rxb->page = NULL; 2029 } 2030 2031 kfree(rx_queue->rx_buff); 2032 rx_queue->rx_buff = NULL; 2033 } 2034 2035 /* If there are any tx skbs or rx skbs still around, free them. 2036 * Then free tx_skbuff and rx_skbuff 2037 */ 2038 static void free_skb_resources(struct gfar_private *priv) 2039 { 2040 struct gfar_priv_tx_q *tx_queue = NULL; 2041 struct gfar_priv_rx_q *rx_queue = NULL; 2042 int i; 2043 2044 /* Go through all the buffer descriptors and free their data buffers */ 2045 for (i = 0; i < priv->num_tx_queues; i++) { 2046 struct netdev_queue *txq; 2047 2048 tx_queue = priv->tx_queue[i]; 2049 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); 2050 if (tx_queue->tx_skbuff) 2051 free_skb_tx_queue(tx_queue); 2052 netdev_tx_reset_queue(txq); 2053 } 2054 2055 for (i = 0; i < priv->num_rx_queues; i++) { 2056 rx_queue = priv->rx_queue[i]; 2057 if (rx_queue->rx_buff) 2058 free_skb_rx_queue(rx_queue); 2059 } 2060 2061 dma_free_coherent(priv->dev, 2062 sizeof(struct txbd8) * priv->total_tx_ring_size + 2063 sizeof(struct rxbd8) * priv->total_rx_ring_size, 2064 priv->tx_queue[0]->tx_bd_base, 2065 priv->tx_queue[0]->tx_bd_dma_base); 2066 } 2067 2068 void gfar_start(struct gfar_private *priv) 2069 { 2070 struct gfar __iomem *regs = priv->gfargrp[0].regs; 2071 u32 tempval; 2072 int i = 0; 2073 2074 /* Enable Rx/Tx hw queues */ 2075 gfar_write(®s->rqueue, priv->rqueue); 2076 gfar_write(®s->tqueue, priv->tqueue); 2077 2078 /* Initialize DMACTRL to have WWR and WOP */ 2079 tempval = gfar_read(®s->dmactrl); 2080 tempval |= DMACTRL_INIT_SETTINGS; 2081 gfar_write(®s->dmactrl, tempval); 2082 2083 /* Make sure we aren't stopped */ 2084 tempval = gfar_read(®s->dmactrl); 2085 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); 2086 gfar_write(®s->dmactrl, tempval); 2087 2088 for (i = 0; i < priv->num_grps; i++) { 2089 regs = priv->gfargrp[i].regs; 2090 /* Clear THLT/RHLT, so that the DMA starts polling now */ 2091 gfar_write(®s->tstat, priv->gfargrp[i].tstat); 2092 gfar_write(®s->rstat, priv->gfargrp[i].rstat); 2093 } 2094 2095 /* Enable Rx/Tx DMA */ 2096 tempval = gfar_read(®s->maccfg1); 2097 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 2098 gfar_write(®s->maccfg1, tempval); 2099 2100 gfar_ints_enable(priv); 2101 2102 netif_trans_update(priv->ndev); /* prevent tx timeout */ 2103 } 2104 2105 static void free_grp_irqs(struct gfar_priv_grp *grp) 2106 { 2107 free_irq(gfar_irq(grp, TX)->irq, grp); 2108 free_irq(gfar_irq(grp, RX)->irq, grp); 2109 free_irq(gfar_irq(grp, ER)->irq, grp); 2110 } 2111 2112 static int register_grp_irqs(struct gfar_priv_grp *grp) 2113 { 2114 struct gfar_private *priv = grp->priv; 2115 struct net_device *dev = priv->ndev; 2116 int err; 2117 2118 /* If the device has multiple interrupts, register for 2119 * them. Otherwise, only register for the one 2120 */ 2121 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 2122 /* Install our interrupt handlers for Error, 2123 * Transmit, and Receive 2124 */ 2125 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0, 2126 gfar_irq(grp, ER)->name, grp); 2127 if (err < 0) { 2128 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2129 gfar_irq(grp, ER)->irq); 2130 2131 goto err_irq_fail; 2132 } 2133 enable_irq_wake(gfar_irq(grp, ER)->irq); 2134 2135 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0, 2136 gfar_irq(grp, TX)->name, grp); 2137 if (err < 0) { 2138 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2139 gfar_irq(grp, TX)->irq); 2140 goto tx_irq_fail; 2141 } 2142 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0, 2143 gfar_irq(grp, RX)->name, grp); 2144 if (err < 0) { 2145 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2146 gfar_irq(grp, RX)->irq); 2147 goto rx_irq_fail; 2148 } 2149 enable_irq_wake(gfar_irq(grp, RX)->irq); 2150 2151 } else { 2152 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0, 2153 gfar_irq(grp, TX)->name, grp); 2154 if (err < 0) { 2155 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2156 gfar_irq(grp, TX)->irq); 2157 goto err_irq_fail; 2158 } 2159 enable_irq_wake(gfar_irq(grp, TX)->irq); 2160 } 2161 2162 return 0; 2163 2164 rx_irq_fail: 2165 free_irq(gfar_irq(grp, TX)->irq, grp); 2166 tx_irq_fail: 2167 free_irq(gfar_irq(grp, ER)->irq, grp); 2168 err_irq_fail: 2169 return err; 2170 2171 } 2172 2173 static void gfar_free_irq(struct gfar_private *priv) 2174 { 2175 int i; 2176 2177 /* Free the IRQs */ 2178 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 2179 for (i = 0; i < priv->num_grps; i++) 2180 free_grp_irqs(&priv->gfargrp[i]); 2181 } else { 2182 for (i = 0; i < priv->num_grps; i++) 2183 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq, 2184 &priv->gfargrp[i]); 2185 } 2186 } 2187 2188 static int gfar_request_irq(struct gfar_private *priv) 2189 { 2190 int err, i, j; 2191 2192 for (i = 0; i < priv->num_grps; i++) { 2193 err = register_grp_irqs(&priv->gfargrp[i]); 2194 if (err) { 2195 for (j = 0; j < i; j++) 2196 free_grp_irqs(&priv->gfargrp[j]); 2197 return err; 2198 } 2199 } 2200 2201 return 0; 2202 } 2203 2204 /* Bring the controller up and running */ 2205 int startup_gfar(struct net_device *ndev) 2206 { 2207 struct gfar_private *priv = netdev_priv(ndev); 2208 int err; 2209 2210 gfar_mac_reset(priv); 2211 2212 err = gfar_alloc_skb_resources(ndev); 2213 if (err) 2214 return err; 2215 2216 gfar_init_tx_rx_base(priv); 2217 2218 smp_mb__before_atomic(); 2219 clear_bit(GFAR_DOWN, &priv->state); 2220 smp_mb__after_atomic(); 2221 2222 /* Start Rx/Tx DMA and enable the interrupts */ 2223 gfar_start(priv); 2224 2225 /* force link state update after mac reset */ 2226 priv->oldlink = 0; 2227 priv->oldspeed = 0; 2228 priv->oldduplex = -1; 2229 2230 phy_start(ndev->phydev); 2231 2232 enable_napi(priv); 2233 2234 netif_tx_wake_all_queues(ndev); 2235 2236 return 0; 2237 } 2238 2239 /* Called when something needs to use the ethernet device 2240 * Returns 0 for success. 2241 */ 2242 static int gfar_enet_open(struct net_device *dev) 2243 { 2244 struct gfar_private *priv = netdev_priv(dev); 2245 int err; 2246 2247 err = init_phy(dev); 2248 if (err) 2249 return err; 2250 2251 err = gfar_request_irq(priv); 2252 if (err) 2253 return err; 2254 2255 err = startup_gfar(dev); 2256 if (err) 2257 return err; 2258 2259 return err; 2260 } 2261 2262 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) 2263 { 2264 struct txfcb *fcb = skb_push(skb, GMAC_FCB_LEN); 2265 2266 memset(fcb, 0, GMAC_FCB_LEN); 2267 2268 return fcb; 2269 } 2270 2271 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb, 2272 int fcb_length) 2273 { 2274 /* If we're here, it's a IP packet with a TCP or UDP 2275 * payload. We set it to checksum, using a pseudo-header 2276 * we provide 2277 */ 2278 u8 flags = TXFCB_DEFAULT; 2279 2280 /* Tell the controller what the protocol is 2281 * And provide the already calculated phcs 2282 */ 2283 if (ip_hdr(skb)->protocol == IPPROTO_UDP) { 2284 flags |= TXFCB_UDP; 2285 fcb->phcs = (__force __be16)(udp_hdr(skb)->check); 2286 } else 2287 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check); 2288 2289 /* l3os is the distance between the start of the 2290 * frame (skb->data) and the start of the IP hdr. 2291 * l4os is the distance between the start of the 2292 * l3 hdr and the l4 hdr 2293 */ 2294 fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length); 2295 fcb->l4os = skb_network_header_len(skb); 2296 2297 fcb->flags = flags; 2298 } 2299 2300 static inline void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) 2301 { 2302 fcb->flags |= TXFCB_VLN; 2303 fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb)); 2304 } 2305 2306 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, 2307 struct txbd8 *base, int ring_size) 2308 { 2309 struct txbd8 *new_bd = bdp + stride; 2310 2311 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; 2312 } 2313 2314 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, 2315 int ring_size) 2316 { 2317 return skip_txbd(bdp, 1, base, ring_size); 2318 } 2319 2320 /* eTSEC12: csum generation not supported for some fcb offsets */ 2321 static inline bool gfar_csum_errata_12(struct gfar_private *priv, 2322 unsigned long fcb_addr) 2323 { 2324 return (gfar_has_errata(priv, GFAR_ERRATA_12) && 2325 (fcb_addr % 0x20) > 0x18); 2326 } 2327 2328 /* eTSEC76: csum generation for frames larger than 2500 may 2329 * cause excess delays before start of transmission 2330 */ 2331 static inline bool gfar_csum_errata_76(struct gfar_private *priv, 2332 unsigned int len) 2333 { 2334 return (gfar_has_errata(priv, GFAR_ERRATA_76) && 2335 (len > 2500)); 2336 } 2337 2338 /* This is called by the kernel when a frame is ready for transmission. 2339 * It is pointed to by the dev->hard_start_xmit function pointer 2340 */ 2341 static netdev_tx_t gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) 2342 { 2343 struct gfar_private *priv = netdev_priv(dev); 2344 struct gfar_priv_tx_q *tx_queue = NULL; 2345 struct netdev_queue *txq; 2346 struct gfar __iomem *regs = NULL; 2347 struct txfcb *fcb = NULL; 2348 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; 2349 u32 lstatus; 2350 skb_frag_t *frag; 2351 int i, rq = 0; 2352 int do_tstamp, do_csum, do_vlan; 2353 u32 bufaddr; 2354 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0; 2355 2356 rq = skb->queue_mapping; 2357 tx_queue = priv->tx_queue[rq]; 2358 txq = netdev_get_tx_queue(dev, rq); 2359 base = tx_queue->tx_bd_base; 2360 regs = tx_queue->grp->regs; 2361 2362 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed); 2363 do_vlan = skb_vlan_tag_present(skb); 2364 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2365 priv->hwts_tx_en; 2366 2367 if (do_csum || do_vlan) 2368 fcb_len = GMAC_FCB_LEN; 2369 2370 /* check if time stamp should be generated */ 2371 if (unlikely(do_tstamp)) 2372 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN; 2373 2374 /* make space for additional header when fcb is needed */ 2375 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) { 2376 struct sk_buff *skb_new; 2377 2378 skb_new = skb_realloc_headroom(skb, fcb_len); 2379 if (!skb_new) { 2380 dev->stats.tx_errors++; 2381 dev_kfree_skb_any(skb); 2382 return NETDEV_TX_OK; 2383 } 2384 2385 if (skb->sk) 2386 skb_set_owner_w(skb_new, skb->sk); 2387 dev_consume_skb_any(skb); 2388 skb = skb_new; 2389 } 2390 2391 /* total number of fragments in the SKB */ 2392 nr_frags = skb_shinfo(skb)->nr_frags; 2393 2394 /* calculate the required number of TxBDs for this skb */ 2395 if (unlikely(do_tstamp)) 2396 nr_txbds = nr_frags + 2; 2397 else 2398 nr_txbds = nr_frags + 1; 2399 2400 /* check if there is space to queue this packet */ 2401 if (nr_txbds > tx_queue->num_txbdfree) { 2402 /* no space, stop the queue */ 2403 netif_tx_stop_queue(txq); 2404 dev->stats.tx_fifo_errors++; 2405 return NETDEV_TX_BUSY; 2406 } 2407 2408 /* Update transmit stats */ 2409 bytes_sent = skb->len; 2410 tx_queue->stats.tx_bytes += bytes_sent; 2411 /* keep Tx bytes on wire for BQL accounting */ 2412 GFAR_CB(skb)->bytes_sent = bytes_sent; 2413 tx_queue->stats.tx_packets++; 2414 2415 txbdp = txbdp_start = tx_queue->cur_tx; 2416 lstatus = be32_to_cpu(txbdp->lstatus); 2417 2418 /* Add TxPAL between FCB and frame if required */ 2419 if (unlikely(do_tstamp)) { 2420 skb_push(skb, GMAC_TXPAL_LEN); 2421 memset(skb->data, 0, GMAC_TXPAL_LEN); 2422 } 2423 2424 /* Add TxFCB if required */ 2425 if (fcb_len) { 2426 fcb = gfar_add_fcb(skb); 2427 lstatus |= BD_LFLAG(TXBD_TOE); 2428 } 2429 2430 /* Set up checksumming */ 2431 if (do_csum) { 2432 gfar_tx_checksum(skb, fcb, fcb_len); 2433 2434 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) || 2435 unlikely(gfar_csum_errata_76(priv, skb->len))) { 2436 __skb_pull(skb, GMAC_FCB_LEN); 2437 skb_checksum_help(skb); 2438 if (do_vlan || do_tstamp) { 2439 /* put back a new fcb for vlan/tstamp TOE */ 2440 fcb = gfar_add_fcb(skb); 2441 } else { 2442 /* Tx TOE not used */ 2443 lstatus &= ~(BD_LFLAG(TXBD_TOE)); 2444 fcb = NULL; 2445 } 2446 } 2447 } 2448 2449 if (do_vlan) 2450 gfar_tx_vlan(skb, fcb); 2451 2452 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb), 2453 DMA_TO_DEVICE); 2454 if (unlikely(dma_mapping_error(priv->dev, bufaddr))) 2455 goto dma_map_err; 2456 2457 txbdp_start->bufPtr = cpu_to_be32(bufaddr); 2458 2459 /* Time stamp insertion requires one additional TxBD */ 2460 if (unlikely(do_tstamp)) 2461 txbdp_tstamp = txbdp = next_txbd(txbdp, base, 2462 tx_queue->tx_ring_size); 2463 2464 if (likely(!nr_frags)) { 2465 if (likely(!do_tstamp)) 2466 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 2467 } else { 2468 u32 lstatus_start = lstatus; 2469 2470 /* Place the fragment addresses and lengths into the TxBDs */ 2471 frag = &skb_shinfo(skb)->frags[0]; 2472 for (i = 0; i < nr_frags; i++, frag++) { 2473 unsigned int size; 2474 2475 /* Point at the next BD, wrapping as needed */ 2476 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2477 2478 size = skb_frag_size(frag); 2479 2480 lstatus = be32_to_cpu(txbdp->lstatus) | size | 2481 BD_LFLAG(TXBD_READY); 2482 2483 /* Handle the last BD specially */ 2484 if (i == nr_frags - 1) 2485 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 2486 2487 bufaddr = skb_frag_dma_map(priv->dev, frag, 0, 2488 size, DMA_TO_DEVICE); 2489 if (unlikely(dma_mapping_error(priv->dev, bufaddr))) 2490 goto dma_map_err; 2491 2492 /* set the TxBD length and buffer pointer */ 2493 txbdp->bufPtr = cpu_to_be32(bufaddr); 2494 txbdp->lstatus = cpu_to_be32(lstatus); 2495 } 2496 2497 lstatus = lstatus_start; 2498 } 2499 2500 /* If time stamping is requested one additional TxBD must be set up. The 2501 * first TxBD points to the FCB and must have a data length of 2502 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with 2503 * the full frame length. 2504 */ 2505 if (unlikely(do_tstamp)) { 2506 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus); 2507 2508 bufaddr = be32_to_cpu(txbdp_start->bufPtr); 2509 bufaddr += fcb_len; 2510 2511 lstatus_ts |= BD_LFLAG(TXBD_READY) | 2512 (skb_headlen(skb) - fcb_len); 2513 if (!nr_frags) 2514 lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 2515 2516 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr); 2517 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts); 2518 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; 2519 2520 /* Setup tx hardware time stamping */ 2521 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2522 fcb->ptp = 1; 2523 } else { 2524 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); 2525 } 2526 2527 netdev_tx_sent_queue(txq, bytes_sent); 2528 2529 gfar_wmb(); 2530 2531 txbdp_start->lstatus = cpu_to_be32(lstatus); 2532 2533 gfar_wmb(); /* force lstatus write before tx_skbuff */ 2534 2535 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; 2536 2537 /* Update the current skb pointer to the next entry we will use 2538 * (wrapping if necessary) 2539 */ 2540 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & 2541 TX_RING_MOD_MASK(tx_queue->tx_ring_size); 2542 2543 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2544 2545 /* We can work in parallel with gfar_clean_tx_ring(), except 2546 * when modifying num_txbdfree. Note that we didn't grab the lock 2547 * when we were reading the num_txbdfree and checking for available 2548 * space, that's because outside of this function it can only grow. 2549 */ 2550 spin_lock_bh(&tx_queue->txlock); 2551 /* reduce TxBD free count */ 2552 tx_queue->num_txbdfree -= (nr_txbds); 2553 spin_unlock_bh(&tx_queue->txlock); 2554 2555 /* If the next BD still needs to be cleaned up, then the bds 2556 * are full. We need to tell the kernel to stop sending us stuff. 2557 */ 2558 if (!tx_queue->num_txbdfree) { 2559 netif_tx_stop_queue(txq); 2560 2561 dev->stats.tx_fifo_errors++; 2562 } 2563 2564 /* Tell the DMA to go go go */ 2565 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); 2566 2567 return NETDEV_TX_OK; 2568 2569 dma_map_err: 2570 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size); 2571 if (do_tstamp) 2572 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2573 for (i = 0; i < nr_frags; i++) { 2574 lstatus = be32_to_cpu(txbdp->lstatus); 2575 if (!(lstatus & BD_LFLAG(TXBD_READY))) 2576 break; 2577 2578 lstatus &= ~BD_LFLAG(TXBD_READY); 2579 txbdp->lstatus = cpu_to_be32(lstatus); 2580 bufaddr = be32_to_cpu(txbdp->bufPtr); 2581 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length), 2582 DMA_TO_DEVICE); 2583 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2584 } 2585 gfar_wmb(); 2586 dev_kfree_skb_any(skb); 2587 return NETDEV_TX_OK; 2588 } 2589 2590 /* Stops the kernel queue, and halts the controller */ 2591 static int gfar_close(struct net_device *dev) 2592 { 2593 struct gfar_private *priv = netdev_priv(dev); 2594 2595 cancel_work_sync(&priv->reset_task); 2596 stop_gfar(dev); 2597 2598 /* Disconnect from the PHY */ 2599 phy_disconnect(dev->phydev); 2600 2601 gfar_free_irq(priv); 2602 2603 return 0; 2604 } 2605 2606 /* Changes the mac address if the controller is not running. */ 2607 static int gfar_set_mac_address(struct net_device *dev) 2608 { 2609 gfar_set_mac_for_addr(dev, 0, dev->dev_addr); 2610 2611 return 0; 2612 } 2613 2614 static int gfar_change_mtu(struct net_device *dev, int new_mtu) 2615 { 2616 struct gfar_private *priv = netdev_priv(dev); 2617 2618 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state)) 2619 cpu_relax(); 2620 2621 if (dev->flags & IFF_UP) 2622 stop_gfar(dev); 2623 2624 dev->mtu = new_mtu; 2625 2626 if (dev->flags & IFF_UP) 2627 startup_gfar(dev); 2628 2629 clear_bit_unlock(GFAR_RESETTING, &priv->state); 2630 2631 return 0; 2632 } 2633 2634 void reset_gfar(struct net_device *ndev) 2635 { 2636 struct gfar_private *priv = netdev_priv(ndev); 2637 2638 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state)) 2639 cpu_relax(); 2640 2641 stop_gfar(ndev); 2642 startup_gfar(ndev); 2643 2644 clear_bit_unlock(GFAR_RESETTING, &priv->state); 2645 } 2646 2647 /* gfar_reset_task gets scheduled when a packet has not been 2648 * transmitted after a set amount of time. 2649 * For now, assume that clearing out all the structures, and 2650 * starting over will fix the problem. 2651 */ 2652 static void gfar_reset_task(struct work_struct *work) 2653 { 2654 struct gfar_private *priv = container_of(work, struct gfar_private, 2655 reset_task); 2656 reset_gfar(priv->ndev); 2657 } 2658 2659 static void gfar_timeout(struct net_device *dev) 2660 { 2661 struct gfar_private *priv = netdev_priv(dev); 2662 2663 dev->stats.tx_errors++; 2664 schedule_work(&priv->reset_task); 2665 } 2666 2667 /* Interrupt Handler for Transmit complete */ 2668 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) 2669 { 2670 struct net_device *dev = tx_queue->dev; 2671 struct netdev_queue *txq; 2672 struct gfar_private *priv = netdev_priv(dev); 2673 struct txbd8 *bdp, *next = NULL; 2674 struct txbd8 *lbdp = NULL; 2675 struct txbd8 *base = tx_queue->tx_bd_base; 2676 struct sk_buff *skb; 2677 int skb_dirtytx; 2678 int tx_ring_size = tx_queue->tx_ring_size; 2679 int frags = 0, nr_txbds = 0; 2680 int i; 2681 int howmany = 0; 2682 int tqi = tx_queue->qindex; 2683 unsigned int bytes_sent = 0; 2684 u32 lstatus; 2685 size_t buflen; 2686 2687 txq = netdev_get_tx_queue(dev, tqi); 2688 bdp = tx_queue->dirty_tx; 2689 skb_dirtytx = tx_queue->skb_dirtytx; 2690 2691 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { 2692 2693 frags = skb_shinfo(skb)->nr_frags; 2694 2695 /* When time stamping, one additional TxBD must be freed. 2696 * Also, we need to dma_unmap_single() the TxPAL. 2697 */ 2698 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) 2699 nr_txbds = frags + 2; 2700 else 2701 nr_txbds = frags + 1; 2702 2703 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); 2704 2705 lstatus = be32_to_cpu(lbdp->lstatus); 2706 2707 /* Only clean completed frames */ 2708 if ((lstatus & BD_LFLAG(TXBD_READY)) && 2709 (lstatus & BD_LENGTH_MASK)) 2710 break; 2711 2712 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { 2713 next = next_txbd(bdp, base, tx_ring_size); 2714 buflen = be16_to_cpu(next->length) + 2715 GMAC_FCB_LEN + GMAC_TXPAL_LEN; 2716 } else 2717 buflen = be16_to_cpu(bdp->length); 2718 2719 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr), 2720 buflen, DMA_TO_DEVICE); 2721 2722 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { 2723 struct skb_shared_hwtstamps shhwtstamps; 2724 u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) & 2725 ~0x7UL); 2726 2727 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 2728 shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns)); 2729 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN); 2730 skb_tstamp_tx(skb, &shhwtstamps); 2731 gfar_clear_txbd_status(bdp); 2732 bdp = next; 2733 } 2734 2735 gfar_clear_txbd_status(bdp); 2736 bdp = next_txbd(bdp, base, tx_ring_size); 2737 2738 for (i = 0; i < frags; i++) { 2739 dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr), 2740 be16_to_cpu(bdp->length), 2741 DMA_TO_DEVICE); 2742 gfar_clear_txbd_status(bdp); 2743 bdp = next_txbd(bdp, base, tx_ring_size); 2744 } 2745 2746 bytes_sent += GFAR_CB(skb)->bytes_sent; 2747 2748 dev_kfree_skb_any(skb); 2749 2750 tx_queue->tx_skbuff[skb_dirtytx] = NULL; 2751 2752 skb_dirtytx = (skb_dirtytx + 1) & 2753 TX_RING_MOD_MASK(tx_ring_size); 2754 2755 howmany++; 2756 spin_lock(&tx_queue->txlock); 2757 tx_queue->num_txbdfree += nr_txbds; 2758 spin_unlock(&tx_queue->txlock); 2759 } 2760 2761 /* If we freed a buffer, we can restart transmission, if necessary */ 2762 if (tx_queue->num_txbdfree && 2763 netif_tx_queue_stopped(txq) && 2764 !(test_bit(GFAR_DOWN, &priv->state))) 2765 netif_wake_subqueue(priv->ndev, tqi); 2766 2767 /* Update dirty indicators */ 2768 tx_queue->skb_dirtytx = skb_dirtytx; 2769 tx_queue->dirty_tx = bdp; 2770 2771 netdev_tx_completed_queue(txq, howmany, bytes_sent); 2772 } 2773 2774 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb) 2775 { 2776 struct page *page; 2777 dma_addr_t addr; 2778 2779 page = dev_alloc_page(); 2780 if (unlikely(!page)) 2781 return false; 2782 2783 addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 2784 if (unlikely(dma_mapping_error(rxq->dev, addr))) { 2785 __free_page(page); 2786 2787 return false; 2788 } 2789 2790 rxb->dma = addr; 2791 rxb->page = page; 2792 rxb->page_offset = 0; 2793 2794 return true; 2795 } 2796 2797 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue) 2798 { 2799 struct gfar_private *priv = netdev_priv(rx_queue->ndev); 2800 struct gfar_extra_stats *estats = &priv->extra_stats; 2801 2802 netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n"); 2803 atomic64_inc(&estats->rx_alloc_err); 2804 } 2805 2806 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue, 2807 int alloc_cnt) 2808 { 2809 struct rxbd8 *bdp; 2810 struct gfar_rx_buff *rxb; 2811 int i; 2812 2813 i = rx_queue->next_to_use; 2814 bdp = &rx_queue->rx_bd_base[i]; 2815 rxb = &rx_queue->rx_buff[i]; 2816 2817 while (alloc_cnt--) { 2818 /* try reuse page */ 2819 if (unlikely(!rxb->page)) { 2820 if (unlikely(!gfar_new_page(rx_queue, rxb))) { 2821 gfar_rx_alloc_err(rx_queue); 2822 break; 2823 } 2824 } 2825 2826 /* Setup the new RxBD */ 2827 gfar_init_rxbdp(rx_queue, bdp, 2828 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT); 2829 2830 /* Update to the next pointer */ 2831 bdp++; 2832 rxb++; 2833 2834 if (unlikely(++i == rx_queue->rx_ring_size)) { 2835 i = 0; 2836 bdp = rx_queue->rx_bd_base; 2837 rxb = rx_queue->rx_buff; 2838 } 2839 } 2840 2841 rx_queue->next_to_use = i; 2842 rx_queue->next_to_alloc = i; 2843 } 2844 2845 static void count_errors(u32 lstatus, struct net_device *ndev) 2846 { 2847 struct gfar_private *priv = netdev_priv(ndev); 2848 struct net_device_stats *stats = &ndev->stats; 2849 struct gfar_extra_stats *estats = &priv->extra_stats; 2850 2851 /* If the packet was truncated, none of the other errors matter */ 2852 if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) { 2853 stats->rx_length_errors++; 2854 2855 atomic64_inc(&estats->rx_trunc); 2856 2857 return; 2858 } 2859 /* Count the errors, if there were any */ 2860 if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) { 2861 stats->rx_length_errors++; 2862 2863 if (lstatus & BD_LFLAG(RXBD_LARGE)) 2864 atomic64_inc(&estats->rx_large); 2865 else 2866 atomic64_inc(&estats->rx_short); 2867 } 2868 if (lstatus & BD_LFLAG(RXBD_NONOCTET)) { 2869 stats->rx_frame_errors++; 2870 atomic64_inc(&estats->rx_nonoctet); 2871 } 2872 if (lstatus & BD_LFLAG(RXBD_CRCERR)) { 2873 atomic64_inc(&estats->rx_crcerr); 2874 stats->rx_crc_errors++; 2875 } 2876 if (lstatus & BD_LFLAG(RXBD_OVERRUN)) { 2877 atomic64_inc(&estats->rx_overrun); 2878 stats->rx_over_errors++; 2879 } 2880 } 2881 2882 irqreturn_t gfar_receive(int irq, void *grp_id) 2883 { 2884 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id; 2885 unsigned long flags; 2886 u32 imask, ievent; 2887 2888 ievent = gfar_read(&grp->regs->ievent); 2889 2890 if (unlikely(ievent & IEVENT_FGPI)) { 2891 gfar_write(&grp->regs->ievent, IEVENT_FGPI); 2892 return IRQ_HANDLED; 2893 } 2894 2895 if (likely(napi_schedule_prep(&grp->napi_rx))) { 2896 spin_lock_irqsave(&grp->grplock, flags); 2897 imask = gfar_read(&grp->regs->imask); 2898 imask &= IMASK_RX_DISABLED; 2899 gfar_write(&grp->regs->imask, imask); 2900 spin_unlock_irqrestore(&grp->grplock, flags); 2901 __napi_schedule(&grp->napi_rx); 2902 } else { 2903 /* Clear IEVENT, so interrupts aren't called again 2904 * because of the packets that have already arrived. 2905 */ 2906 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK); 2907 } 2908 2909 return IRQ_HANDLED; 2910 } 2911 2912 /* Interrupt Handler for Transmit complete */ 2913 static irqreturn_t gfar_transmit(int irq, void *grp_id) 2914 { 2915 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id; 2916 unsigned long flags; 2917 u32 imask; 2918 2919 if (likely(napi_schedule_prep(&grp->napi_tx))) { 2920 spin_lock_irqsave(&grp->grplock, flags); 2921 imask = gfar_read(&grp->regs->imask); 2922 imask &= IMASK_TX_DISABLED; 2923 gfar_write(&grp->regs->imask, imask); 2924 spin_unlock_irqrestore(&grp->grplock, flags); 2925 __napi_schedule(&grp->napi_tx); 2926 } else { 2927 /* Clear IEVENT, so interrupts aren't called again 2928 * because of the packets that have already arrived. 2929 */ 2930 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK); 2931 } 2932 2933 return IRQ_HANDLED; 2934 } 2935 2936 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus, 2937 struct sk_buff *skb, bool first) 2938 { 2939 int size = lstatus & BD_LENGTH_MASK; 2940 struct page *page = rxb->page; 2941 2942 if (likely(first)) { 2943 skb_put(skb, size); 2944 } else { 2945 /* the last fragments' length contains the full frame length */ 2946 if (lstatus & BD_LFLAG(RXBD_LAST)) 2947 size -= skb->len; 2948 2949 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 2950 rxb->page_offset + RXBUF_ALIGNMENT, 2951 size, GFAR_RXB_TRUESIZE); 2952 } 2953 2954 /* try reuse page */ 2955 if (unlikely(page_count(page) != 1 || page_is_pfmemalloc(page))) 2956 return false; 2957 2958 /* change offset to the other half */ 2959 rxb->page_offset ^= GFAR_RXB_TRUESIZE; 2960 2961 page_ref_inc(page); 2962 2963 return true; 2964 } 2965 2966 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq, 2967 struct gfar_rx_buff *old_rxb) 2968 { 2969 struct gfar_rx_buff *new_rxb; 2970 u16 nta = rxq->next_to_alloc; 2971 2972 new_rxb = &rxq->rx_buff[nta]; 2973 2974 /* find next buf that can reuse a page */ 2975 nta++; 2976 rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0; 2977 2978 /* copy page reference */ 2979 *new_rxb = *old_rxb; 2980 2981 /* sync for use by the device */ 2982 dma_sync_single_range_for_device(rxq->dev, old_rxb->dma, 2983 old_rxb->page_offset, 2984 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE); 2985 } 2986 2987 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue, 2988 u32 lstatus, struct sk_buff *skb) 2989 { 2990 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean]; 2991 struct page *page = rxb->page; 2992 bool first = false; 2993 2994 if (likely(!skb)) { 2995 void *buff_addr = page_address(page) + rxb->page_offset; 2996 2997 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE); 2998 if (unlikely(!skb)) { 2999 gfar_rx_alloc_err(rx_queue); 3000 return NULL; 3001 } 3002 skb_reserve(skb, RXBUF_ALIGNMENT); 3003 first = true; 3004 } 3005 3006 dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset, 3007 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE); 3008 3009 if (gfar_add_rx_frag(rxb, lstatus, skb, first)) { 3010 /* reuse the free half of the page */ 3011 gfar_reuse_rx_page(rx_queue, rxb); 3012 } else { 3013 /* page cannot be reused, unmap it */ 3014 dma_unmap_page(rx_queue->dev, rxb->dma, 3015 PAGE_SIZE, DMA_FROM_DEVICE); 3016 } 3017 3018 /* clear rxb content */ 3019 rxb->page = NULL; 3020 3021 return skb; 3022 } 3023 3024 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) 3025 { 3026 /* If valid headers were found, and valid sums 3027 * were verified, then we tell the kernel that no 3028 * checksumming is necessary. Otherwise, it is [FIXME] 3029 */ 3030 if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) == 3031 (RXFCB_CIP | RXFCB_CTU)) 3032 skb->ip_summed = CHECKSUM_UNNECESSARY; 3033 else 3034 skb_checksum_none_assert(skb); 3035 } 3036 3037 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */ 3038 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb) 3039 { 3040 struct gfar_private *priv = netdev_priv(ndev); 3041 struct rxfcb *fcb = NULL; 3042 3043 /* fcb is at the beginning if exists */ 3044 fcb = (struct rxfcb *)skb->data; 3045 3046 /* Remove the FCB from the skb 3047 * Remove the padded bytes, if there are any 3048 */ 3049 if (priv->uses_rxfcb) 3050 skb_pull(skb, GMAC_FCB_LEN); 3051 3052 /* Get receive timestamp from the skb */ 3053 if (priv->hwts_rx_en) { 3054 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); 3055 u64 *ns = (u64 *) skb->data; 3056 3057 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 3058 shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns)); 3059 } 3060 3061 if (priv->padding) 3062 skb_pull(skb, priv->padding); 3063 3064 /* Trim off the FCS */ 3065 pskb_trim(skb, skb->len - ETH_FCS_LEN); 3066 3067 if (ndev->features & NETIF_F_RXCSUM) 3068 gfar_rx_checksum(skb, fcb); 3069 3070 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here. 3071 * Even if vlan rx accel is disabled, on some chips 3072 * RXFCB_VLN is pseudo randomly set. 3073 */ 3074 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX && 3075 be16_to_cpu(fcb->flags) & RXFCB_VLN) 3076 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 3077 be16_to_cpu(fcb->vlctl)); 3078 } 3079 3080 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring 3081 * until the budget/quota has been reached. Returns the number 3082 * of frames handled 3083 */ 3084 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit) 3085 { 3086 struct net_device *ndev = rx_queue->ndev; 3087 struct gfar_private *priv = netdev_priv(ndev); 3088 struct rxbd8 *bdp; 3089 int i, howmany = 0; 3090 struct sk_buff *skb = rx_queue->skb; 3091 int cleaned_cnt = gfar_rxbd_unused(rx_queue); 3092 unsigned int total_bytes = 0, total_pkts = 0; 3093 3094 /* Get the first full descriptor */ 3095 i = rx_queue->next_to_clean; 3096 3097 while (rx_work_limit--) { 3098 u32 lstatus; 3099 3100 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) { 3101 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt); 3102 cleaned_cnt = 0; 3103 } 3104 3105 bdp = &rx_queue->rx_bd_base[i]; 3106 lstatus = be32_to_cpu(bdp->lstatus); 3107 if (lstatus & BD_LFLAG(RXBD_EMPTY)) 3108 break; 3109 3110 /* order rx buffer descriptor reads */ 3111 rmb(); 3112 3113 /* fetch next to clean buffer from the ring */ 3114 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb); 3115 if (unlikely(!skb)) 3116 break; 3117 3118 cleaned_cnt++; 3119 howmany++; 3120 3121 if (unlikely(++i == rx_queue->rx_ring_size)) 3122 i = 0; 3123 3124 rx_queue->next_to_clean = i; 3125 3126 /* fetch next buffer if not the last in frame */ 3127 if (!(lstatus & BD_LFLAG(RXBD_LAST))) 3128 continue; 3129 3130 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) { 3131 count_errors(lstatus, ndev); 3132 3133 /* discard faulty buffer */ 3134 dev_kfree_skb(skb); 3135 skb = NULL; 3136 rx_queue->stats.rx_dropped++; 3137 continue; 3138 } 3139 3140 gfar_process_frame(ndev, skb); 3141 3142 /* Increment the number of packets */ 3143 total_pkts++; 3144 total_bytes += skb->len; 3145 3146 skb_record_rx_queue(skb, rx_queue->qindex); 3147 3148 skb->protocol = eth_type_trans(skb, ndev); 3149 3150 /* Send the packet up the stack */ 3151 napi_gro_receive(&rx_queue->grp->napi_rx, skb); 3152 3153 skb = NULL; 3154 } 3155 3156 /* Store incomplete frames for completion */ 3157 rx_queue->skb = skb; 3158 3159 rx_queue->stats.rx_packets += total_pkts; 3160 rx_queue->stats.rx_bytes += total_bytes; 3161 3162 if (cleaned_cnt) 3163 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt); 3164 3165 /* Update Last Free RxBD pointer for LFC */ 3166 if (unlikely(priv->tx_actual_en)) { 3167 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue); 3168 3169 gfar_write(rx_queue->rfbptr, bdp_dma); 3170 } 3171 3172 return howmany; 3173 } 3174 3175 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget) 3176 { 3177 struct gfar_priv_grp *gfargrp = 3178 container_of(napi, struct gfar_priv_grp, napi_rx); 3179 struct gfar __iomem *regs = gfargrp->regs; 3180 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue; 3181 int work_done = 0; 3182 3183 /* Clear IEVENT, so interrupts aren't called again 3184 * because of the packets that have already arrived 3185 */ 3186 gfar_write(®s->ievent, IEVENT_RX_MASK); 3187 3188 work_done = gfar_clean_rx_ring(rx_queue, budget); 3189 3190 if (work_done < budget) { 3191 u32 imask; 3192 napi_complete_done(napi, work_done); 3193 /* Clear the halt bit in RSTAT */ 3194 gfar_write(®s->rstat, gfargrp->rstat); 3195 3196 spin_lock_irq(&gfargrp->grplock); 3197 imask = gfar_read(®s->imask); 3198 imask |= IMASK_RX_DEFAULT; 3199 gfar_write(®s->imask, imask); 3200 spin_unlock_irq(&gfargrp->grplock); 3201 } 3202 3203 return work_done; 3204 } 3205 3206 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget) 3207 { 3208 struct gfar_priv_grp *gfargrp = 3209 container_of(napi, struct gfar_priv_grp, napi_tx); 3210 struct gfar __iomem *regs = gfargrp->regs; 3211 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue; 3212 u32 imask; 3213 3214 /* Clear IEVENT, so interrupts aren't called again 3215 * because of the packets that have already arrived 3216 */ 3217 gfar_write(®s->ievent, IEVENT_TX_MASK); 3218 3219 /* run Tx cleanup to completion */ 3220 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) 3221 gfar_clean_tx_ring(tx_queue); 3222 3223 napi_complete(napi); 3224 3225 spin_lock_irq(&gfargrp->grplock); 3226 imask = gfar_read(®s->imask); 3227 imask |= IMASK_TX_DEFAULT; 3228 gfar_write(®s->imask, imask); 3229 spin_unlock_irq(&gfargrp->grplock); 3230 3231 return 0; 3232 } 3233 3234 static int gfar_poll_rx(struct napi_struct *napi, int budget) 3235 { 3236 struct gfar_priv_grp *gfargrp = 3237 container_of(napi, struct gfar_priv_grp, napi_rx); 3238 struct gfar_private *priv = gfargrp->priv; 3239 struct gfar __iomem *regs = gfargrp->regs; 3240 struct gfar_priv_rx_q *rx_queue = NULL; 3241 int work_done = 0, work_done_per_q = 0; 3242 int i, budget_per_q = 0; 3243 unsigned long rstat_rxf; 3244 int num_act_queues; 3245 3246 /* Clear IEVENT, so interrupts aren't called again 3247 * because of the packets that have already arrived 3248 */ 3249 gfar_write(®s->ievent, IEVENT_RX_MASK); 3250 3251 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK; 3252 3253 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS); 3254 if (num_act_queues) 3255 budget_per_q = budget/num_act_queues; 3256 3257 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { 3258 /* skip queue if not active */ 3259 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i))) 3260 continue; 3261 3262 rx_queue = priv->rx_queue[i]; 3263 work_done_per_q = 3264 gfar_clean_rx_ring(rx_queue, budget_per_q); 3265 work_done += work_done_per_q; 3266 3267 /* finished processing this queue */ 3268 if (work_done_per_q < budget_per_q) { 3269 /* clear active queue hw indication */ 3270 gfar_write(®s->rstat, 3271 RSTAT_CLEAR_RXF0 >> i); 3272 num_act_queues--; 3273 3274 if (!num_act_queues) 3275 break; 3276 } 3277 } 3278 3279 if (!num_act_queues) { 3280 u32 imask; 3281 napi_complete_done(napi, work_done); 3282 3283 /* Clear the halt bit in RSTAT */ 3284 gfar_write(®s->rstat, gfargrp->rstat); 3285 3286 spin_lock_irq(&gfargrp->grplock); 3287 imask = gfar_read(®s->imask); 3288 imask |= IMASK_RX_DEFAULT; 3289 gfar_write(®s->imask, imask); 3290 spin_unlock_irq(&gfargrp->grplock); 3291 } 3292 3293 return work_done; 3294 } 3295 3296 static int gfar_poll_tx(struct napi_struct *napi, int budget) 3297 { 3298 struct gfar_priv_grp *gfargrp = 3299 container_of(napi, struct gfar_priv_grp, napi_tx); 3300 struct gfar_private *priv = gfargrp->priv; 3301 struct gfar __iomem *regs = gfargrp->regs; 3302 struct gfar_priv_tx_q *tx_queue = NULL; 3303 int has_tx_work = 0; 3304 int i; 3305 3306 /* Clear IEVENT, so interrupts aren't called again 3307 * because of the packets that have already arrived 3308 */ 3309 gfar_write(®s->ievent, IEVENT_TX_MASK); 3310 3311 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) { 3312 tx_queue = priv->tx_queue[i]; 3313 /* run Tx cleanup to completion */ 3314 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) { 3315 gfar_clean_tx_ring(tx_queue); 3316 has_tx_work = 1; 3317 } 3318 } 3319 3320 if (!has_tx_work) { 3321 u32 imask; 3322 napi_complete(napi); 3323 3324 spin_lock_irq(&gfargrp->grplock); 3325 imask = gfar_read(®s->imask); 3326 imask |= IMASK_TX_DEFAULT; 3327 gfar_write(®s->imask, imask); 3328 spin_unlock_irq(&gfargrp->grplock); 3329 } 3330 3331 return 0; 3332 } 3333 3334 3335 #ifdef CONFIG_NET_POLL_CONTROLLER 3336 /* Polling 'interrupt' - used by things like netconsole to send skbs 3337 * without having to re-enable interrupts. It's not called while 3338 * the interrupt routine is executing. 3339 */ 3340 static void gfar_netpoll(struct net_device *dev) 3341 { 3342 struct gfar_private *priv = netdev_priv(dev); 3343 int i; 3344 3345 /* If the device has multiple interrupts, run tx/rx */ 3346 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 3347 for (i = 0; i < priv->num_grps; i++) { 3348 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 3349 3350 disable_irq(gfar_irq(grp, TX)->irq); 3351 disable_irq(gfar_irq(grp, RX)->irq); 3352 disable_irq(gfar_irq(grp, ER)->irq); 3353 gfar_interrupt(gfar_irq(grp, TX)->irq, grp); 3354 enable_irq(gfar_irq(grp, ER)->irq); 3355 enable_irq(gfar_irq(grp, RX)->irq); 3356 enable_irq(gfar_irq(grp, TX)->irq); 3357 } 3358 } else { 3359 for (i = 0; i < priv->num_grps; i++) { 3360 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 3361 3362 disable_irq(gfar_irq(grp, TX)->irq); 3363 gfar_interrupt(gfar_irq(grp, TX)->irq, grp); 3364 enable_irq(gfar_irq(grp, TX)->irq); 3365 } 3366 } 3367 } 3368 #endif 3369 3370 /* The interrupt handler for devices with one interrupt */ 3371 static irqreturn_t gfar_interrupt(int irq, void *grp_id) 3372 { 3373 struct gfar_priv_grp *gfargrp = grp_id; 3374 3375 /* Save ievent for future reference */ 3376 u32 events = gfar_read(&gfargrp->regs->ievent); 3377 3378 /* Check for reception */ 3379 if (events & IEVENT_RX_MASK) 3380 gfar_receive(irq, grp_id); 3381 3382 /* Check for transmit completion */ 3383 if (events & IEVENT_TX_MASK) 3384 gfar_transmit(irq, grp_id); 3385 3386 /* Check for errors */ 3387 if (events & IEVENT_ERR_MASK) 3388 gfar_error(irq, grp_id); 3389 3390 return IRQ_HANDLED; 3391 } 3392 3393 /* Called every time the controller might need to be made 3394 * aware of new link state. The PHY code conveys this 3395 * information through variables in the phydev structure, and this 3396 * function converts those variables into the appropriate 3397 * register values, and can bring down the device if needed. 3398 */ 3399 static void adjust_link(struct net_device *dev) 3400 { 3401 struct gfar_private *priv = netdev_priv(dev); 3402 struct phy_device *phydev = dev->phydev; 3403 3404 if (unlikely(phydev->link != priv->oldlink || 3405 (phydev->link && (phydev->duplex != priv->oldduplex || 3406 phydev->speed != priv->oldspeed)))) 3407 gfar_update_link_state(priv); 3408 } 3409 3410 /* Update the hash table based on the current list of multicast 3411 * addresses we subscribe to. Also, change the promiscuity of 3412 * the device based on the flags (this function is called 3413 * whenever dev->flags is changed 3414 */ 3415 static void gfar_set_multi(struct net_device *dev) 3416 { 3417 struct netdev_hw_addr *ha; 3418 struct gfar_private *priv = netdev_priv(dev); 3419 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3420 u32 tempval; 3421 3422 if (dev->flags & IFF_PROMISC) { 3423 /* Set RCTRL to PROM */ 3424 tempval = gfar_read(®s->rctrl); 3425 tempval |= RCTRL_PROM; 3426 gfar_write(®s->rctrl, tempval); 3427 } else { 3428 /* Set RCTRL to not PROM */ 3429 tempval = gfar_read(®s->rctrl); 3430 tempval &= ~(RCTRL_PROM); 3431 gfar_write(®s->rctrl, tempval); 3432 } 3433 3434 if (dev->flags & IFF_ALLMULTI) { 3435 /* Set the hash to rx all multicast frames */ 3436 gfar_write(®s->igaddr0, 0xffffffff); 3437 gfar_write(®s->igaddr1, 0xffffffff); 3438 gfar_write(®s->igaddr2, 0xffffffff); 3439 gfar_write(®s->igaddr3, 0xffffffff); 3440 gfar_write(®s->igaddr4, 0xffffffff); 3441 gfar_write(®s->igaddr5, 0xffffffff); 3442 gfar_write(®s->igaddr6, 0xffffffff); 3443 gfar_write(®s->igaddr7, 0xffffffff); 3444 gfar_write(®s->gaddr0, 0xffffffff); 3445 gfar_write(®s->gaddr1, 0xffffffff); 3446 gfar_write(®s->gaddr2, 0xffffffff); 3447 gfar_write(®s->gaddr3, 0xffffffff); 3448 gfar_write(®s->gaddr4, 0xffffffff); 3449 gfar_write(®s->gaddr5, 0xffffffff); 3450 gfar_write(®s->gaddr6, 0xffffffff); 3451 gfar_write(®s->gaddr7, 0xffffffff); 3452 } else { 3453 int em_num; 3454 int idx; 3455 3456 /* zero out the hash */ 3457 gfar_write(®s->igaddr0, 0x0); 3458 gfar_write(®s->igaddr1, 0x0); 3459 gfar_write(®s->igaddr2, 0x0); 3460 gfar_write(®s->igaddr3, 0x0); 3461 gfar_write(®s->igaddr4, 0x0); 3462 gfar_write(®s->igaddr5, 0x0); 3463 gfar_write(®s->igaddr6, 0x0); 3464 gfar_write(®s->igaddr7, 0x0); 3465 gfar_write(®s->gaddr0, 0x0); 3466 gfar_write(®s->gaddr1, 0x0); 3467 gfar_write(®s->gaddr2, 0x0); 3468 gfar_write(®s->gaddr3, 0x0); 3469 gfar_write(®s->gaddr4, 0x0); 3470 gfar_write(®s->gaddr5, 0x0); 3471 gfar_write(®s->gaddr6, 0x0); 3472 gfar_write(®s->gaddr7, 0x0); 3473 3474 /* If we have extended hash tables, we need to 3475 * clear the exact match registers to prepare for 3476 * setting them 3477 */ 3478 if (priv->extended_hash) { 3479 em_num = GFAR_EM_NUM + 1; 3480 gfar_clear_exact_match(dev); 3481 idx = 1; 3482 } else { 3483 idx = 0; 3484 em_num = 0; 3485 } 3486 3487 if (netdev_mc_empty(dev)) 3488 return; 3489 3490 /* Parse the list, and set the appropriate bits */ 3491 netdev_for_each_mc_addr(ha, dev) { 3492 if (idx < em_num) { 3493 gfar_set_mac_for_addr(dev, idx, ha->addr); 3494 idx++; 3495 } else 3496 gfar_set_hash_for_addr(dev, ha->addr); 3497 } 3498 } 3499 } 3500 3501 3502 /* Clears each of the exact match registers to zero, so they 3503 * don't interfere with normal reception 3504 */ 3505 static void gfar_clear_exact_match(struct net_device *dev) 3506 { 3507 int idx; 3508 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; 3509 3510 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++) 3511 gfar_set_mac_for_addr(dev, idx, zero_arr); 3512 } 3513 3514 /* Set the appropriate hash bit for the given addr */ 3515 /* The algorithm works like so: 3516 * 1) Take the Destination Address (ie the multicast address), and 3517 * do a CRC on it (little endian), and reverse the bits of the 3518 * result. 3519 * 2) Use the 8 most significant bits as a hash into a 256-entry 3520 * table. The table is controlled through 8 32-bit registers: 3521 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 3522 * gaddr7. This means that the 3 most significant bits in the 3523 * hash index which gaddr register to use, and the 5 other bits 3524 * indicate which bit (assuming an IBM numbering scheme, which 3525 * for PowerPC (tm) is usually the case) in the register holds 3526 * the entry. 3527 */ 3528 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) 3529 { 3530 u32 tempval; 3531 struct gfar_private *priv = netdev_priv(dev); 3532 u32 result = ether_crc(ETH_ALEN, addr); 3533 int width = priv->hash_width; 3534 u8 whichbit = (result >> (32 - width)) & 0x1f; 3535 u8 whichreg = result >> (32 - width + 5); 3536 u32 value = (1 << (31-whichbit)); 3537 3538 tempval = gfar_read(priv->hash_regs[whichreg]); 3539 tempval |= value; 3540 gfar_write(priv->hash_regs[whichreg], tempval); 3541 } 3542 3543 3544 /* There are multiple MAC Address register pairs on some controllers 3545 * This function sets the numth pair to a given address 3546 */ 3547 static void gfar_set_mac_for_addr(struct net_device *dev, int num, 3548 const u8 *addr) 3549 { 3550 struct gfar_private *priv = netdev_priv(dev); 3551 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3552 u32 tempval; 3553 u32 __iomem *macptr = ®s->macstnaddr1; 3554 3555 macptr += num*2; 3556 3557 /* For a station address of 0x12345678ABCD in transmission 3558 * order (BE), MACnADDR1 is set to 0xCDAB7856 and 3559 * MACnADDR2 is set to 0x34120000. 3560 */ 3561 tempval = (addr[5] << 24) | (addr[4] << 16) | 3562 (addr[3] << 8) | addr[2]; 3563 3564 gfar_write(macptr, tempval); 3565 3566 tempval = (addr[1] << 24) | (addr[0] << 16); 3567 3568 gfar_write(macptr+1, tempval); 3569 } 3570 3571 /* GFAR error interrupt handler */ 3572 static irqreturn_t gfar_error(int irq, void *grp_id) 3573 { 3574 struct gfar_priv_grp *gfargrp = grp_id; 3575 struct gfar __iomem *regs = gfargrp->regs; 3576 struct gfar_private *priv= gfargrp->priv; 3577 struct net_device *dev = priv->ndev; 3578 3579 /* Save ievent for future reference */ 3580 u32 events = gfar_read(®s->ievent); 3581 3582 /* Clear IEVENT */ 3583 gfar_write(®s->ievent, events & IEVENT_ERR_MASK); 3584 3585 /* Magic Packet is not an error. */ 3586 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && 3587 (events & IEVENT_MAG)) 3588 events &= ~IEVENT_MAG; 3589 3590 /* Hmm... */ 3591 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) 3592 netdev_dbg(dev, 3593 "error interrupt (ievent=0x%08x imask=0x%08x)\n", 3594 events, gfar_read(®s->imask)); 3595 3596 /* Update the error counters */ 3597 if (events & IEVENT_TXE) { 3598 dev->stats.tx_errors++; 3599 3600 if (events & IEVENT_LC) 3601 dev->stats.tx_window_errors++; 3602 if (events & IEVENT_CRL) 3603 dev->stats.tx_aborted_errors++; 3604 if (events & IEVENT_XFUN) { 3605 netif_dbg(priv, tx_err, dev, 3606 "TX FIFO underrun, packet dropped\n"); 3607 dev->stats.tx_dropped++; 3608 atomic64_inc(&priv->extra_stats.tx_underrun); 3609 3610 schedule_work(&priv->reset_task); 3611 } 3612 netif_dbg(priv, tx_err, dev, "Transmit Error\n"); 3613 } 3614 if (events & IEVENT_BSY) { 3615 dev->stats.rx_over_errors++; 3616 atomic64_inc(&priv->extra_stats.rx_bsy); 3617 3618 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n", 3619 gfar_read(®s->rstat)); 3620 } 3621 if (events & IEVENT_BABR) { 3622 dev->stats.rx_errors++; 3623 atomic64_inc(&priv->extra_stats.rx_babr); 3624 3625 netif_dbg(priv, rx_err, dev, "babbling RX error\n"); 3626 } 3627 if (events & IEVENT_EBERR) { 3628 atomic64_inc(&priv->extra_stats.eberr); 3629 netif_dbg(priv, rx_err, dev, "bus error\n"); 3630 } 3631 if (events & IEVENT_RXC) 3632 netif_dbg(priv, rx_status, dev, "control frame\n"); 3633 3634 if (events & IEVENT_BABT) { 3635 atomic64_inc(&priv->extra_stats.tx_babt); 3636 netif_dbg(priv, tx_err, dev, "babbling TX error\n"); 3637 } 3638 return IRQ_HANDLED; 3639 } 3640 3641 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv) 3642 { 3643 struct net_device *ndev = priv->ndev; 3644 struct phy_device *phydev = ndev->phydev; 3645 u32 val = 0; 3646 3647 if (!phydev->duplex) 3648 return val; 3649 3650 if (!priv->pause_aneg_en) { 3651 if (priv->tx_pause_en) 3652 val |= MACCFG1_TX_FLOW; 3653 if (priv->rx_pause_en) 3654 val |= MACCFG1_RX_FLOW; 3655 } else { 3656 u16 lcl_adv, rmt_adv; 3657 u8 flowctrl; 3658 /* get link partner capabilities */ 3659 rmt_adv = 0; 3660 if (phydev->pause) 3661 rmt_adv = LPA_PAUSE_CAP; 3662 if (phydev->asym_pause) 3663 rmt_adv |= LPA_PAUSE_ASYM; 3664 3665 lcl_adv = linkmode_adv_to_lcl_adv_t(phydev->advertising); 3666 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 3667 if (flowctrl & FLOW_CTRL_TX) 3668 val |= MACCFG1_TX_FLOW; 3669 if (flowctrl & FLOW_CTRL_RX) 3670 val |= MACCFG1_RX_FLOW; 3671 } 3672 3673 return val; 3674 } 3675 3676 static noinline void gfar_update_link_state(struct gfar_private *priv) 3677 { 3678 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3679 struct net_device *ndev = priv->ndev; 3680 struct phy_device *phydev = ndev->phydev; 3681 struct gfar_priv_rx_q *rx_queue = NULL; 3682 int i; 3683 3684 if (unlikely(test_bit(GFAR_RESETTING, &priv->state))) 3685 return; 3686 3687 if (phydev->link) { 3688 u32 tempval1 = gfar_read(®s->maccfg1); 3689 u32 tempval = gfar_read(®s->maccfg2); 3690 u32 ecntrl = gfar_read(®s->ecntrl); 3691 u32 tx_flow_oldval = (tempval1 & MACCFG1_TX_FLOW); 3692 3693 if (phydev->duplex != priv->oldduplex) { 3694 if (!(phydev->duplex)) 3695 tempval &= ~(MACCFG2_FULL_DUPLEX); 3696 else 3697 tempval |= MACCFG2_FULL_DUPLEX; 3698 3699 priv->oldduplex = phydev->duplex; 3700 } 3701 3702 if (phydev->speed != priv->oldspeed) { 3703 switch (phydev->speed) { 3704 case 1000: 3705 tempval = 3706 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); 3707 3708 ecntrl &= ~(ECNTRL_R100); 3709 break; 3710 case 100: 3711 case 10: 3712 tempval = 3713 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); 3714 3715 /* Reduced mode distinguishes 3716 * between 10 and 100 3717 */ 3718 if (phydev->speed == SPEED_100) 3719 ecntrl |= ECNTRL_R100; 3720 else 3721 ecntrl &= ~(ECNTRL_R100); 3722 break; 3723 default: 3724 netif_warn(priv, link, priv->ndev, 3725 "Ack! Speed (%d) is not 10/100/1000!\n", 3726 phydev->speed); 3727 break; 3728 } 3729 3730 priv->oldspeed = phydev->speed; 3731 } 3732 3733 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); 3734 tempval1 |= gfar_get_flowctrl_cfg(priv); 3735 3736 /* Turn last free buffer recording on */ 3737 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) { 3738 for (i = 0; i < priv->num_rx_queues; i++) { 3739 u32 bdp_dma; 3740 3741 rx_queue = priv->rx_queue[i]; 3742 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue); 3743 gfar_write(rx_queue->rfbptr, bdp_dma); 3744 } 3745 3746 priv->tx_actual_en = 1; 3747 } 3748 3749 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval)) 3750 priv->tx_actual_en = 0; 3751 3752 gfar_write(®s->maccfg1, tempval1); 3753 gfar_write(®s->maccfg2, tempval); 3754 gfar_write(®s->ecntrl, ecntrl); 3755 3756 if (!priv->oldlink) 3757 priv->oldlink = 1; 3758 3759 } else if (priv->oldlink) { 3760 priv->oldlink = 0; 3761 priv->oldspeed = 0; 3762 priv->oldduplex = -1; 3763 } 3764 3765 if (netif_msg_link(priv)) 3766 phy_print_status(phydev); 3767 } 3768 3769 static const struct of_device_id gfar_match[] = 3770 { 3771 { 3772 .type = "network", 3773 .compatible = "gianfar", 3774 }, 3775 { 3776 .compatible = "fsl,etsec2", 3777 }, 3778 {}, 3779 }; 3780 MODULE_DEVICE_TABLE(of, gfar_match); 3781 3782 /* Structure for a device driver */ 3783 static struct platform_driver gfar_driver = { 3784 .driver = { 3785 .name = "fsl-gianfar", 3786 .pm = GFAR_PM_OPS, 3787 .of_match_table = gfar_match, 3788 }, 3789 .probe = gfar_probe, 3790 .remove = gfar_remove, 3791 }; 3792 3793 module_platform_driver(gfar_driver); 3794