1 /* drivers/net/ethernet/freescale/gianfar.c 2 * 3 * Gianfar Ethernet Driver 4 * This driver is designed for the non-CPM ethernet controllers 5 * on the 85xx and 83xx family of integrated processors 6 * Based on 8260_io/fcc_enet.c 7 * 8 * Author: Andy Fleming 9 * Maintainer: Kumar Gala 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 11 * 12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc. 13 * Copyright 2007 MontaVista Software, Inc. 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 * 20 * Gianfar: AKA Lambda Draconis, "Dragon" 21 * RA 11 31 24.2 22 * Dec +69 19 52 23 * V 3.84 24 * B-V +1.62 25 * 26 * Theory of operation 27 * 28 * The driver is initialized through of_device. Configuration information 29 * is therefore conveyed through an OF-style device tree. 30 * 31 * The Gianfar Ethernet Controller uses a ring of buffer 32 * descriptors. The beginning is indicated by a register 33 * pointing to the physical address of the start of the ring. 34 * The end is determined by a "wrap" bit being set in the 35 * last descriptor of the ring. 36 * 37 * When a packet is received, the RXF bit in the 38 * IEVENT register is set, triggering an interrupt when the 39 * corresponding bit in the IMASK register is also set (if 40 * interrupt coalescing is active, then the interrupt may not 41 * happen immediately, but will wait until either a set number 42 * of frames or amount of time have passed). In NAPI, the 43 * interrupt handler will signal there is work to be done, and 44 * exit. This method will start at the last known empty 45 * descriptor, and process every subsequent descriptor until there 46 * are none left with data (NAPI will stop after a set number of 47 * packets to give time to other tasks, but will eventually 48 * process all the packets). The data arrives inside a 49 * pre-allocated skb, and so after the skb is passed up to the 50 * stack, a new skb must be allocated, and the address field in 51 * the buffer descriptor must be updated to indicate this new 52 * skb. 53 * 54 * When the kernel requests that a packet be transmitted, the 55 * driver starts where it left off last time, and points the 56 * descriptor at the buffer which was passed in. The driver 57 * then informs the DMA engine that there are packets ready to 58 * be transmitted. Once the controller is finished transmitting 59 * the packet, an interrupt may be triggered (under the same 60 * conditions as for reception, but depending on the TXF bit). 61 * The driver then cleans up the buffer. 62 */ 63 64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 65 #define DEBUG 66 67 #include <linux/kernel.h> 68 #include <linux/string.h> 69 #include <linux/errno.h> 70 #include <linux/unistd.h> 71 #include <linux/slab.h> 72 #include <linux/interrupt.h> 73 #include <linux/delay.h> 74 #include <linux/netdevice.h> 75 #include <linux/etherdevice.h> 76 #include <linux/skbuff.h> 77 #include <linux/if_vlan.h> 78 #include <linux/spinlock.h> 79 #include <linux/mm.h> 80 #include <linux/of_address.h> 81 #include <linux/of_irq.h> 82 #include <linux/of_mdio.h> 83 #include <linux/of_platform.h> 84 #include <linux/ip.h> 85 #include <linux/tcp.h> 86 #include <linux/udp.h> 87 #include <linux/in.h> 88 #include <linux/net_tstamp.h> 89 90 #include <asm/io.h> 91 #ifdef CONFIG_PPC 92 #include <asm/reg.h> 93 #include <asm/mpc85xx.h> 94 #endif 95 #include <asm/irq.h> 96 #include <asm/uaccess.h> 97 #include <linux/module.h> 98 #include <linux/dma-mapping.h> 99 #include <linux/crc32.h> 100 #include <linux/mii.h> 101 #include <linux/phy.h> 102 #include <linux/phy_fixed.h> 103 #include <linux/of.h> 104 #include <linux/of_net.h> 105 #include <linux/of_address.h> 106 #include <linux/of_irq.h> 107 108 #include "gianfar.h" 109 110 #define TX_TIMEOUT (1*HZ) 111 112 const char gfar_driver_version[] = "1.3"; 113 114 static int gfar_enet_open(struct net_device *dev); 115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); 116 static void gfar_reset_task(struct work_struct *work); 117 static void gfar_timeout(struct net_device *dev); 118 static int gfar_close(struct net_device *dev); 119 static struct sk_buff *gfar_new_skb(struct net_device *dev, 120 dma_addr_t *bufaddr); 121 static int gfar_set_mac_address(struct net_device *dev); 122 static int gfar_change_mtu(struct net_device *dev, int new_mtu); 123 static irqreturn_t gfar_error(int irq, void *dev_id); 124 static irqreturn_t gfar_transmit(int irq, void *dev_id); 125 static irqreturn_t gfar_interrupt(int irq, void *dev_id); 126 static void adjust_link(struct net_device *dev); 127 static noinline void gfar_update_link_state(struct gfar_private *priv); 128 static int init_phy(struct net_device *dev); 129 static int gfar_probe(struct platform_device *ofdev); 130 static int gfar_remove(struct platform_device *ofdev); 131 static void free_skb_resources(struct gfar_private *priv); 132 static void gfar_set_multi(struct net_device *dev); 133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); 134 static void gfar_configure_serdes(struct net_device *dev); 135 static int gfar_poll_rx(struct napi_struct *napi, int budget); 136 static int gfar_poll_tx(struct napi_struct *napi, int budget); 137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget); 138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget); 139 #ifdef CONFIG_NET_POLL_CONTROLLER 140 static void gfar_netpoll(struct net_device *dev); 141 #endif 142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); 143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); 144 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, 145 int amount_pull, struct napi_struct *napi); 146 static void gfar_halt_nodisable(struct gfar_private *priv); 147 static void gfar_clear_exact_match(struct net_device *dev); 148 static void gfar_set_mac_for_addr(struct net_device *dev, int num, 149 const u8 *addr); 150 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 151 152 MODULE_AUTHOR("Freescale Semiconductor, Inc"); 153 MODULE_DESCRIPTION("Gianfar Ethernet Driver"); 154 MODULE_LICENSE("GPL"); 155 156 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, 157 dma_addr_t buf) 158 { 159 u32 lstatus; 160 161 bdp->bufPtr = buf; 162 163 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); 164 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) 165 lstatus |= BD_LFLAG(RXBD_WRAP); 166 167 gfar_wmb(); 168 169 bdp->lstatus = lstatus; 170 } 171 172 static int gfar_init_bds(struct net_device *ndev) 173 { 174 struct gfar_private *priv = netdev_priv(ndev); 175 struct gfar __iomem *regs = priv->gfargrp[0].regs; 176 struct gfar_priv_tx_q *tx_queue = NULL; 177 struct gfar_priv_rx_q *rx_queue = NULL; 178 struct txbd8 *txbdp; 179 struct rxbd8 *rxbdp; 180 u32 __iomem *rfbptr; 181 int i, j; 182 dma_addr_t bufaddr; 183 184 for (i = 0; i < priv->num_tx_queues; i++) { 185 tx_queue = priv->tx_queue[i]; 186 /* Initialize some variables in our dev structure */ 187 tx_queue->num_txbdfree = tx_queue->tx_ring_size; 188 tx_queue->dirty_tx = tx_queue->tx_bd_base; 189 tx_queue->cur_tx = tx_queue->tx_bd_base; 190 tx_queue->skb_curtx = 0; 191 tx_queue->skb_dirtytx = 0; 192 193 /* Initialize Transmit Descriptor Ring */ 194 txbdp = tx_queue->tx_bd_base; 195 for (j = 0; j < tx_queue->tx_ring_size; j++) { 196 txbdp->lstatus = 0; 197 txbdp->bufPtr = 0; 198 txbdp++; 199 } 200 201 /* Set the last descriptor in the ring to indicate wrap */ 202 txbdp--; 203 txbdp->status |= TXBD_WRAP; 204 } 205 206 rfbptr = ®s->rfbptr0; 207 for (i = 0; i < priv->num_rx_queues; i++) { 208 rx_queue = priv->rx_queue[i]; 209 rx_queue->cur_rx = rx_queue->rx_bd_base; 210 rx_queue->skb_currx = 0; 211 rxbdp = rx_queue->rx_bd_base; 212 213 for (j = 0; j < rx_queue->rx_ring_size; j++) { 214 struct sk_buff *skb = rx_queue->rx_skbuff[j]; 215 216 if (skb) { 217 bufaddr = rxbdp->bufPtr; 218 } else { 219 skb = gfar_new_skb(ndev, &bufaddr); 220 if (!skb) { 221 netdev_err(ndev, "Can't allocate RX buffers\n"); 222 return -ENOMEM; 223 } 224 rx_queue->rx_skbuff[j] = skb; 225 } 226 227 gfar_init_rxbdp(rx_queue, rxbdp, bufaddr); 228 rxbdp++; 229 } 230 231 rx_queue->rfbptr = rfbptr; 232 rfbptr += 2; 233 } 234 235 return 0; 236 } 237 238 static int gfar_alloc_skb_resources(struct net_device *ndev) 239 { 240 void *vaddr; 241 dma_addr_t addr; 242 int i, j, k; 243 struct gfar_private *priv = netdev_priv(ndev); 244 struct device *dev = priv->dev; 245 struct gfar_priv_tx_q *tx_queue = NULL; 246 struct gfar_priv_rx_q *rx_queue = NULL; 247 248 priv->total_tx_ring_size = 0; 249 for (i = 0; i < priv->num_tx_queues; i++) 250 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; 251 252 priv->total_rx_ring_size = 0; 253 for (i = 0; i < priv->num_rx_queues; i++) 254 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; 255 256 /* Allocate memory for the buffer descriptors */ 257 vaddr = dma_alloc_coherent(dev, 258 (priv->total_tx_ring_size * 259 sizeof(struct txbd8)) + 260 (priv->total_rx_ring_size * 261 sizeof(struct rxbd8)), 262 &addr, GFP_KERNEL); 263 if (!vaddr) 264 return -ENOMEM; 265 266 for (i = 0; i < priv->num_tx_queues; i++) { 267 tx_queue = priv->tx_queue[i]; 268 tx_queue->tx_bd_base = vaddr; 269 tx_queue->tx_bd_dma_base = addr; 270 tx_queue->dev = ndev; 271 /* enet DMA only understands physical addresses */ 272 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; 273 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; 274 } 275 276 /* Start the rx descriptor ring where the tx ring leaves off */ 277 for (i = 0; i < priv->num_rx_queues; i++) { 278 rx_queue = priv->rx_queue[i]; 279 rx_queue->rx_bd_base = vaddr; 280 rx_queue->rx_bd_dma_base = addr; 281 rx_queue->dev = ndev; 282 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; 283 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; 284 } 285 286 /* Setup the skbuff rings */ 287 for (i = 0; i < priv->num_tx_queues; i++) { 288 tx_queue = priv->tx_queue[i]; 289 tx_queue->tx_skbuff = 290 kmalloc_array(tx_queue->tx_ring_size, 291 sizeof(*tx_queue->tx_skbuff), 292 GFP_KERNEL); 293 if (!tx_queue->tx_skbuff) 294 goto cleanup; 295 296 for (k = 0; k < tx_queue->tx_ring_size; k++) 297 tx_queue->tx_skbuff[k] = NULL; 298 } 299 300 for (i = 0; i < priv->num_rx_queues; i++) { 301 rx_queue = priv->rx_queue[i]; 302 rx_queue->rx_skbuff = 303 kmalloc_array(rx_queue->rx_ring_size, 304 sizeof(*rx_queue->rx_skbuff), 305 GFP_KERNEL); 306 if (!rx_queue->rx_skbuff) 307 goto cleanup; 308 309 for (j = 0; j < rx_queue->rx_ring_size; j++) 310 rx_queue->rx_skbuff[j] = NULL; 311 } 312 313 if (gfar_init_bds(ndev)) 314 goto cleanup; 315 316 return 0; 317 318 cleanup: 319 free_skb_resources(priv); 320 return -ENOMEM; 321 } 322 323 static void gfar_init_tx_rx_base(struct gfar_private *priv) 324 { 325 struct gfar __iomem *regs = priv->gfargrp[0].regs; 326 u32 __iomem *baddr; 327 int i; 328 329 baddr = ®s->tbase0; 330 for (i = 0; i < priv->num_tx_queues; i++) { 331 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); 332 baddr += 2; 333 } 334 335 baddr = ®s->rbase0; 336 for (i = 0; i < priv->num_rx_queues; i++) { 337 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); 338 baddr += 2; 339 } 340 } 341 342 static void gfar_init_rqprm(struct gfar_private *priv) 343 { 344 struct gfar __iomem *regs = priv->gfargrp[0].regs; 345 u32 __iomem *baddr; 346 int i; 347 348 baddr = ®s->rqprm0; 349 for (i = 0; i < priv->num_rx_queues; i++) { 350 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size | 351 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT)); 352 baddr++; 353 } 354 } 355 356 static void gfar_rx_buff_size_config(struct gfar_private *priv) 357 { 358 int frame_size = priv->ndev->mtu + ETH_HLEN + ETH_FCS_LEN; 359 360 /* set this when rx hw offload (TOE) functions are being used */ 361 priv->uses_rxfcb = 0; 362 363 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) 364 priv->uses_rxfcb = 1; 365 366 if (priv->hwts_rx_en) 367 priv->uses_rxfcb = 1; 368 369 if (priv->uses_rxfcb) 370 frame_size += GMAC_FCB_LEN; 371 372 frame_size += priv->padding; 373 374 frame_size = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + 375 INCREMENTAL_BUFFER_SIZE; 376 377 priv->rx_buffer_size = frame_size; 378 } 379 380 static void gfar_mac_rx_config(struct gfar_private *priv) 381 { 382 struct gfar __iomem *regs = priv->gfargrp[0].regs; 383 u32 rctrl = 0; 384 385 if (priv->rx_filer_enable) { 386 rctrl |= RCTRL_FILREN; 387 /* Program the RIR0 reg with the required distribution */ 388 if (priv->poll_mode == GFAR_SQ_POLLING) 389 gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0); 390 else /* GFAR_MQ_POLLING */ 391 gfar_write(®s->rir0, DEFAULT_8RXQ_RIR0); 392 } 393 394 /* Restore PROMISC mode */ 395 if (priv->ndev->flags & IFF_PROMISC) 396 rctrl |= RCTRL_PROM; 397 398 if (priv->ndev->features & NETIF_F_RXCSUM) 399 rctrl |= RCTRL_CHECKSUMMING; 400 401 if (priv->extended_hash) 402 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN; 403 404 if (priv->padding) { 405 rctrl &= ~RCTRL_PAL_MASK; 406 rctrl |= RCTRL_PADDING(priv->padding); 407 } 408 409 /* Enable HW time stamping if requested from user space */ 410 if (priv->hwts_rx_en) 411 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; 412 413 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) 414 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; 415 416 /* Clear the LFC bit */ 417 gfar_write(®s->rctrl, rctrl); 418 /* Init flow control threshold values */ 419 gfar_init_rqprm(priv); 420 gfar_write(®s->ptv, DEFAULT_LFC_PTVVAL); 421 rctrl |= RCTRL_LFC; 422 423 /* Init rctrl based on our settings */ 424 gfar_write(®s->rctrl, rctrl); 425 } 426 427 static void gfar_mac_tx_config(struct gfar_private *priv) 428 { 429 struct gfar __iomem *regs = priv->gfargrp[0].regs; 430 u32 tctrl = 0; 431 432 if (priv->ndev->features & NETIF_F_IP_CSUM) 433 tctrl |= TCTRL_INIT_CSUM; 434 435 if (priv->prio_sched_en) 436 tctrl |= TCTRL_TXSCHED_PRIO; 437 else { 438 tctrl |= TCTRL_TXSCHED_WRRS; 439 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT); 440 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT); 441 } 442 443 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX) 444 tctrl |= TCTRL_VLINS; 445 446 gfar_write(®s->tctrl, tctrl); 447 } 448 449 static void gfar_configure_coalescing(struct gfar_private *priv, 450 unsigned long tx_mask, unsigned long rx_mask) 451 { 452 struct gfar __iomem *regs = priv->gfargrp[0].regs; 453 u32 __iomem *baddr; 454 455 if (priv->mode == MQ_MG_MODE) { 456 int i = 0; 457 458 baddr = ®s->txic0; 459 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { 460 gfar_write(baddr + i, 0); 461 if (likely(priv->tx_queue[i]->txcoalescing)) 462 gfar_write(baddr + i, priv->tx_queue[i]->txic); 463 } 464 465 baddr = ®s->rxic0; 466 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { 467 gfar_write(baddr + i, 0); 468 if (likely(priv->rx_queue[i]->rxcoalescing)) 469 gfar_write(baddr + i, priv->rx_queue[i]->rxic); 470 } 471 } else { 472 /* Backward compatible case -- even if we enable 473 * multiple queues, there's only single reg to program 474 */ 475 gfar_write(®s->txic, 0); 476 if (likely(priv->tx_queue[0]->txcoalescing)) 477 gfar_write(®s->txic, priv->tx_queue[0]->txic); 478 479 gfar_write(®s->rxic, 0); 480 if (unlikely(priv->rx_queue[0]->rxcoalescing)) 481 gfar_write(®s->rxic, priv->rx_queue[0]->rxic); 482 } 483 } 484 485 void gfar_configure_coalescing_all(struct gfar_private *priv) 486 { 487 gfar_configure_coalescing(priv, 0xFF, 0xFF); 488 } 489 490 static struct net_device_stats *gfar_get_stats(struct net_device *dev) 491 { 492 struct gfar_private *priv = netdev_priv(dev); 493 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; 494 unsigned long tx_packets = 0, tx_bytes = 0; 495 int i; 496 497 for (i = 0; i < priv->num_rx_queues; i++) { 498 rx_packets += priv->rx_queue[i]->stats.rx_packets; 499 rx_bytes += priv->rx_queue[i]->stats.rx_bytes; 500 rx_dropped += priv->rx_queue[i]->stats.rx_dropped; 501 } 502 503 dev->stats.rx_packets = rx_packets; 504 dev->stats.rx_bytes = rx_bytes; 505 dev->stats.rx_dropped = rx_dropped; 506 507 for (i = 0; i < priv->num_tx_queues; i++) { 508 tx_bytes += priv->tx_queue[i]->stats.tx_bytes; 509 tx_packets += priv->tx_queue[i]->stats.tx_packets; 510 } 511 512 dev->stats.tx_bytes = tx_bytes; 513 dev->stats.tx_packets = tx_packets; 514 515 return &dev->stats; 516 } 517 518 static const struct net_device_ops gfar_netdev_ops = { 519 .ndo_open = gfar_enet_open, 520 .ndo_start_xmit = gfar_start_xmit, 521 .ndo_stop = gfar_close, 522 .ndo_change_mtu = gfar_change_mtu, 523 .ndo_set_features = gfar_set_features, 524 .ndo_set_rx_mode = gfar_set_multi, 525 .ndo_tx_timeout = gfar_timeout, 526 .ndo_do_ioctl = gfar_ioctl, 527 .ndo_get_stats = gfar_get_stats, 528 .ndo_set_mac_address = eth_mac_addr, 529 .ndo_validate_addr = eth_validate_addr, 530 #ifdef CONFIG_NET_POLL_CONTROLLER 531 .ndo_poll_controller = gfar_netpoll, 532 #endif 533 }; 534 535 static void gfar_ints_disable(struct gfar_private *priv) 536 { 537 int i; 538 for (i = 0; i < priv->num_grps; i++) { 539 struct gfar __iomem *regs = priv->gfargrp[i].regs; 540 /* Clear IEVENT */ 541 gfar_write(®s->ievent, IEVENT_INIT_CLEAR); 542 543 /* Initialize IMASK */ 544 gfar_write(®s->imask, IMASK_INIT_CLEAR); 545 } 546 } 547 548 static void gfar_ints_enable(struct gfar_private *priv) 549 { 550 int i; 551 for (i = 0; i < priv->num_grps; i++) { 552 struct gfar __iomem *regs = priv->gfargrp[i].regs; 553 /* Unmask the interrupts we look for */ 554 gfar_write(®s->imask, IMASK_DEFAULT); 555 } 556 } 557 558 static void lock_tx_qs(struct gfar_private *priv) 559 { 560 int i; 561 562 for (i = 0; i < priv->num_tx_queues; i++) 563 spin_lock(&priv->tx_queue[i]->txlock); 564 } 565 566 static void unlock_tx_qs(struct gfar_private *priv) 567 { 568 int i; 569 570 for (i = 0; i < priv->num_tx_queues; i++) 571 spin_unlock(&priv->tx_queue[i]->txlock); 572 } 573 574 static int gfar_alloc_tx_queues(struct gfar_private *priv) 575 { 576 int i; 577 578 for (i = 0; i < priv->num_tx_queues; i++) { 579 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), 580 GFP_KERNEL); 581 if (!priv->tx_queue[i]) 582 return -ENOMEM; 583 584 priv->tx_queue[i]->tx_skbuff = NULL; 585 priv->tx_queue[i]->qindex = i; 586 priv->tx_queue[i]->dev = priv->ndev; 587 spin_lock_init(&(priv->tx_queue[i]->txlock)); 588 } 589 return 0; 590 } 591 592 static int gfar_alloc_rx_queues(struct gfar_private *priv) 593 { 594 int i; 595 596 for (i = 0; i < priv->num_rx_queues; i++) { 597 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), 598 GFP_KERNEL); 599 if (!priv->rx_queue[i]) 600 return -ENOMEM; 601 602 priv->rx_queue[i]->rx_skbuff = NULL; 603 priv->rx_queue[i]->qindex = i; 604 priv->rx_queue[i]->dev = priv->ndev; 605 } 606 return 0; 607 } 608 609 static void gfar_free_tx_queues(struct gfar_private *priv) 610 { 611 int i; 612 613 for (i = 0; i < priv->num_tx_queues; i++) 614 kfree(priv->tx_queue[i]); 615 } 616 617 static void gfar_free_rx_queues(struct gfar_private *priv) 618 { 619 int i; 620 621 for (i = 0; i < priv->num_rx_queues; i++) 622 kfree(priv->rx_queue[i]); 623 } 624 625 static void unmap_group_regs(struct gfar_private *priv) 626 { 627 int i; 628 629 for (i = 0; i < MAXGROUPS; i++) 630 if (priv->gfargrp[i].regs) 631 iounmap(priv->gfargrp[i].regs); 632 } 633 634 static void free_gfar_dev(struct gfar_private *priv) 635 { 636 int i, j; 637 638 for (i = 0; i < priv->num_grps; i++) 639 for (j = 0; j < GFAR_NUM_IRQS; j++) { 640 kfree(priv->gfargrp[i].irqinfo[j]); 641 priv->gfargrp[i].irqinfo[j] = NULL; 642 } 643 644 free_netdev(priv->ndev); 645 } 646 647 static void disable_napi(struct gfar_private *priv) 648 { 649 int i; 650 651 for (i = 0; i < priv->num_grps; i++) { 652 napi_disable(&priv->gfargrp[i].napi_rx); 653 napi_disable(&priv->gfargrp[i].napi_tx); 654 } 655 } 656 657 static void enable_napi(struct gfar_private *priv) 658 { 659 int i; 660 661 for (i = 0; i < priv->num_grps; i++) { 662 napi_enable(&priv->gfargrp[i].napi_rx); 663 napi_enable(&priv->gfargrp[i].napi_tx); 664 } 665 } 666 667 static int gfar_parse_group(struct device_node *np, 668 struct gfar_private *priv, const char *model) 669 { 670 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps]; 671 int i; 672 673 for (i = 0; i < GFAR_NUM_IRQS; i++) { 674 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo), 675 GFP_KERNEL); 676 if (!grp->irqinfo[i]) 677 return -ENOMEM; 678 } 679 680 grp->regs = of_iomap(np, 0); 681 if (!grp->regs) 682 return -ENOMEM; 683 684 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0); 685 686 /* If we aren't the FEC we have multiple interrupts */ 687 if (model && strcasecmp(model, "FEC")) { 688 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1); 689 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2); 690 if (gfar_irq(grp, TX)->irq == NO_IRQ || 691 gfar_irq(grp, RX)->irq == NO_IRQ || 692 gfar_irq(grp, ER)->irq == NO_IRQ) 693 return -EINVAL; 694 } 695 696 grp->priv = priv; 697 spin_lock_init(&grp->grplock); 698 if (priv->mode == MQ_MG_MODE) { 699 u32 *rxq_mask, *txq_mask; 700 rxq_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL); 701 txq_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL); 702 703 if (priv->poll_mode == GFAR_SQ_POLLING) { 704 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */ 705 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps); 706 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps); 707 } else { /* GFAR_MQ_POLLING */ 708 grp->rx_bit_map = rxq_mask ? 709 *rxq_mask : (DEFAULT_MAPPING >> priv->num_grps); 710 grp->tx_bit_map = txq_mask ? 711 *txq_mask : (DEFAULT_MAPPING >> priv->num_grps); 712 } 713 } else { 714 grp->rx_bit_map = 0xFF; 715 grp->tx_bit_map = 0xFF; 716 } 717 718 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses 719 * right to left, so we need to revert the 8 bits to get the q index 720 */ 721 grp->rx_bit_map = bitrev8(grp->rx_bit_map); 722 grp->tx_bit_map = bitrev8(grp->tx_bit_map); 723 724 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, 725 * also assign queues to groups 726 */ 727 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) { 728 if (!grp->rx_queue) 729 grp->rx_queue = priv->rx_queue[i]; 730 grp->num_rx_queues++; 731 grp->rstat |= (RSTAT_CLEAR_RHALT >> i); 732 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i); 733 priv->rx_queue[i]->grp = grp; 734 } 735 736 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) { 737 if (!grp->tx_queue) 738 grp->tx_queue = priv->tx_queue[i]; 739 grp->num_tx_queues++; 740 grp->tstat |= (TSTAT_CLEAR_THALT >> i); 741 priv->tqueue |= (TQUEUE_EN0 >> i); 742 priv->tx_queue[i]->grp = grp; 743 } 744 745 priv->num_grps++; 746 747 return 0; 748 } 749 750 static int gfar_of_group_count(struct device_node *np) 751 { 752 struct device_node *child; 753 int num = 0; 754 755 for_each_available_child_of_node(np, child) 756 if (!of_node_cmp(child->name, "queue-group")) 757 num++; 758 759 return num; 760 } 761 762 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) 763 { 764 const char *model; 765 const char *ctype; 766 const void *mac_addr; 767 int err = 0, i; 768 struct net_device *dev = NULL; 769 struct gfar_private *priv = NULL; 770 struct device_node *np = ofdev->dev.of_node; 771 struct device_node *child = NULL; 772 const u32 *stash; 773 const u32 *stash_len; 774 const u32 *stash_idx; 775 unsigned int num_tx_qs, num_rx_qs; 776 u32 *tx_queues, *rx_queues; 777 unsigned short mode, poll_mode; 778 779 if (!np) 780 return -ENODEV; 781 782 if (of_device_is_compatible(np, "fsl,etsec2")) { 783 mode = MQ_MG_MODE; 784 poll_mode = GFAR_SQ_POLLING; 785 } else { 786 mode = SQ_SG_MODE; 787 poll_mode = GFAR_SQ_POLLING; 788 } 789 790 /* parse the num of HW tx and rx queues */ 791 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL); 792 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL); 793 794 if (mode == SQ_SG_MODE) { 795 num_tx_qs = 1; 796 num_rx_qs = 1; 797 } else { /* MQ_MG_MODE */ 798 /* get the actual number of supported groups */ 799 unsigned int num_grps = gfar_of_group_count(np); 800 801 if (num_grps == 0 || num_grps > MAXGROUPS) { 802 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n", 803 num_grps); 804 pr_err("Cannot do alloc_etherdev, aborting\n"); 805 return -EINVAL; 806 } 807 808 if (poll_mode == GFAR_SQ_POLLING) { 809 num_tx_qs = num_grps; /* one txq per int group */ 810 num_rx_qs = num_grps; /* one rxq per int group */ 811 } else { /* GFAR_MQ_POLLING */ 812 num_tx_qs = tx_queues ? *tx_queues : 1; 813 num_rx_qs = rx_queues ? *rx_queues : 1; 814 } 815 } 816 817 if (num_tx_qs > MAX_TX_QS) { 818 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", 819 num_tx_qs, MAX_TX_QS); 820 pr_err("Cannot do alloc_etherdev, aborting\n"); 821 return -EINVAL; 822 } 823 824 if (num_rx_qs > MAX_RX_QS) { 825 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", 826 num_rx_qs, MAX_RX_QS); 827 pr_err("Cannot do alloc_etherdev, aborting\n"); 828 return -EINVAL; 829 } 830 831 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); 832 dev = *pdev; 833 if (NULL == dev) 834 return -ENOMEM; 835 836 priv = netdev_priv(dev); 837 priv->ndev = dev; 838 839 priv->mode = mode; 840 priv->poll_mode = poll_mode; 841 842 priv->num_tx_queues = num_tx_qs; 843 netif_set_real_num_rx_queues(dev, num_rx_qs); 844 priv->num_rx_queues = num_rx_qs; 845 846 err = gfar_alloc_tx_queues(priv); 847 if (err) 848 goto tx_alloc_failed; 849 850 err = gfar_alloc_rx_queues(priv); 851 if (err) 852 goto rx_alloc_failed; 853 854 /* Init Rx queue filer rule set linked list */ 855 INIT_LIST_HEAD(&priv->rx_list.list); 856 priv->rx_list.count = 0; 857 mutex_init(&priv->rx_queue_access); 858 859 model = of_get_property(np, "model", NULL); 860 861 for (i = 0; i < MAXGROUPS; i++) 862 priv->gfargrp[i].regs = NULL; 863 864 /* Parse and initialize group specific information */ 865 if (priv->mode == MQ_MG_MODE) { 866 for_each_available_child_of_node(np, child) { 867 if (of_node_cmp(child->name, "queue-group")) 868 continue; 869 870 err = gfar_parse_group(child, priv, model); 871 if (err) 872 goto err_grp_init; 873 } 874 } else { /* SQ_SG_MODE */ 875 err = gfar_parse_group(np, priv, model); 876 if (err) 877 goto err_grp_init; 878 } 879 880 stash = of_get_property(np, "bd-stash", NULL); 881 882 if (stash) { 883 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; 884 priv->bd_stash_en = 1; 885 } 886 887 stash_len = of_get_property(np, "rx-stash-len", NULL); 888 889 if (stash_len) 890 priv->rx_stash_size = *stash_len; 891 892 stash_idx = of_get_property(np, "rx-stash-idx", NULL); 893 894 if (stash_idx) 895 priv->rx_stash_index = *stash_idx; 896 897 if (stash_len || stash_idx) 898 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; 899 900 mac_addr = of_get_mac_address(np); 901 902 if (mac_addr) 903 memcpy(dev->dev_addr, mac_addr, ETH_ALEN); 904 905 if (model && !strcasecmp(model, "TSEC")) 906 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT | 907 FSL_GIANFAR_DEV_HAS_COALESCE | 908 FSL_GIANFAR_DEV_HAS_RMON | 909 FSL_GIANFAR_DEV_HAS_MULTI_INTR; 910 911 if (model && !strcasecmp(model, "eTSEC")) 912 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT | 913 FSL_GIANFAR_DEV_HAS_COALESCE | 914 FSL_GIANFAR_DEV_HAS_RMON | 915 FSL_GIANFAR_DEV_HAS_MULTI_INTR | 916 FSL_GIANFAR_DEV_HAS_CSUM | 917 FSL_GIANFAR_DEV_HAS_VLAN | 918 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | 919 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | 920 FSL_GIANFAR_DEV_HAS_TIMER; 921 922 ctype = of_get_property(np, "phy-connection-type", NULL); 923 924 /* We only care about rgmii-id. The rest are autodetected */ 925 if (ctype && !strcmp(ctype, "rgmii-id")) 926 priv->interface = PHY_INTERFACE_MODE_RGMII_ID; 927 else 928 priv->interface = PHY_INTERFACE_MODE_MII; 929 930 if (of_get_property(np, "fsl,magic-packet", NULL)) 931 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; 932 933 priv->phy_node = of_parse_phandle(np, "phy-handle", 0); 934 935 /* In the case of a fixed PHY, the DT node associated 936 * to the PHY is the Ethernet MAC DT node. 937 */ 938 if (!priv->phy_node && of_phy_is_fixed_link(np)) { 939 err = of_phy_register_fixed_link(np); 940 if (err) 941 goto err_grp_init; 942 943 priv->phy_node = of_node_get(np); 944 } 945 946 /* Find the TBI PHY. If it's not there, we don't support SGMII */ 947 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); 948 949 return 0; 950 951 err_grp_init: 952 unmap_group_regs(priv); 953 rx_alloc_failed: 954 gfar_free_rx_queues(priv); 955 tx_alloc_failed: 956 gfar_free_tx_queues(priv); 957 free_gfar_dev(priv); 958 return err; 959 } 960 961 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 962 { 963 struct hwtstamp_config config; 964 struct gfar_private *priv = netdev_priv(netdev); 965 966 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 967 return -EFAULT; 968 969 /* reserved for future extensions */ 970 if (config.flags) 971 return -EINVAL; 972 973 switch (config.tx_type) { 974 case HWTSTAMP_TX_OFF: 975 priv->hwts_tx_en = 0; 976 break; 977 case HWTSTAMP_TX_ON: 978 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) 979 return -ERANGE; 980 priv->hwts_tx_en = 1; 981 break; 982 default: 983 return -ERANGE; 984 } 985 986 switch (config.rx_filter) { 987 case HWTSTAMP_FILTER_NONE: 988 if (priv->hwts_rx_en) { 989 priv->hwts_rx_en = 0; 990 reset_gfar(netdev); 991 } 992 break; 993 default: 994 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) 995 return -ERANGE; 996 if (!priv->hwts_rx_en) { 997 priv->hwts_rx_en = 1; 998 reset_gfar(netdev); 999 } 1000 config.rx_filter = HWTSTAMP_FILTER_ALL; 1001 break; 1002 } 1003 1004 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1005 -EFAULT : 0; 1006 } 1007 1008 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 1009 { 1010 struct hwtstamp_config config; 1011 struct gfar_private *priv = netdev_priv(netdev); 1012 1013 config.flags = 0; 1014 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1015 config.rx_filter = (priv->hwts_rx_en ? 1016 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE); 1017 1018 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1019 -EFAULT : 0; 1020 } 1021 1022 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1023 { 1024 struct gfar_private *priv = netdev_priv(dev); 1025 1026 if (!netif_running(dev)) 1027 return -EINVAL; 1028 1029 if (cmd == SIOCSHWTSTAMP) 1030 return gfar_hwtstamp_set(dev, rq); 1031 if (cmd == SIOCGHWTSTAMP) 1032 return gfar_hwtstamp_get(dev, rq); 1033 1034 if (!priv->phydev) 1035 return -ENODEV; 1036 1037 return phy_mii_ioctl(priv->phydev, rq, cmd); 1038 } 1039 1040 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, 1041 u32 class) 1042 { 1043 u32 rqfpr = FPR_FILER_MASK; 1044 u32 rqfcr = 0x0; 1045 1046 rqfar--; 1047 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; 1048 priv->ftp_rqfpr[rqfar] = rqfpr; 1049 priv->ftp_rqfcr[rqfar] = rqfcr; 1050 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1051 1052 rqfar--; 1053 rqfcr = RQFCR_CMP_NOMATCH; 1054 priv->ftp_rqfpr[rqfar] = rqfpr; 1055 priv->ftp_rqfcr[rqfar] = rqfcr; 1056 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1057 1058 rqfar--; 1059 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; 1060 rqfpr = class; 1061 priv->ftp_rqfcr[rqfar] = rqfcr; 1062 priv->ftp_rqfpr[rqfar] = rqfpr; 1063 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1064 1065 rqfar--; 1066 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; 1067 rqfpr = class; 1068 priv->ftp_rqfcr[rqfar] = rqfcr; 1069 priv->ftp_rqfpr[rqfar] = rqfpr; 1070 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1071 1072 return rqfar; 1073 } 1074 1075 static void gfar_init_filer_table(struct gfar_private *priv) 1076 { 1077 int i = 0x0; 1078 u32 rqfar = MAX_FILER_IDX; 1079 u32 rqfcr = 0x0; 1080 u32 rqfpr = FPR_FILER_MASK; 1081 1082 /* Default rule */ 1083 rqfcr = RQFCR_CMP_MATCH; 1084 priv->ftp_rqfcr[rqfar] = rqfcr; 1085 priv->ftp_rqfpr[rqfar] = rqfpr; 1086 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1087 1088 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); 1089 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); 1090 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); 1091 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); 1092 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); 1093 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); 1094 1095 /* cur_filer_idx indicated the first non-masked rule */ 1096 priv->cur_filer_idx = rqfar; 1097 1098 /* Rest are masked rules */ 1099 rqfcr = RQFCR_CMP_NOMATCH; 1100 for (i = 0; i < rqfar; i++) { 1101 priv->ftp_rqfcr[i] = rqfcr; 1102 priv->ftp_rqfpr[i] = rqfpr; 1103 gfar_write_filer(priv, i, rqfcr, rqfpr); 1104 } 1105 } 1106 1107 #ifdef CONFIG_PPC 1108 static void __gfar_detect_errata_83xx(struct gfar_private *priv) 1109 { 1110 unsigned int pvr = mfspr(SPRN_PVR); 1111 unsigned int svr = mfspr(SPRN_SVR); 1112 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ 1113 unsigned int rev = svr & 0xffff; 1114 1115 /* MPC8313 Rev 2.0 and higher; All MPC837x */ 1116 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || 1117 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) 1118 priv->errata |= GFAR_ERRATA_74; 1119 1120 /* MPC8313 and MPC837x all rev */ 1121 if ((pvr == 0x80850010 && mod == 0x80b0) || 1122 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) 1123 priv->errata |= GFAR_ERRATA_76; 1124 1125 /* MPC8313 Rev < 2.0 */ 1126 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) 1127 priv->errata |= GFAR_ERRATA_12; 1128 } 1129 1130 static void __gfar_detect_errata_85xx(struct gfar_private *priv) 1131 { 1132 unsigned int svr = mfspr(SPRN_SVR); 1133 1134 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20)) 1135 priv->errata |= GFAR_ERRATA_12; 1136 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) || 1137 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20))) 1138 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */ 1139 } 1140 #endif 1141 1142 static void gfar_detect_errata(struct gfar_private *priv) 1143 { 1144 struct device *dev = &priv->ofdev->dev; 1145 1146 /* no plans to fix */ 1147 priv->errata |= GFAR_ERRATA_A002; 1148 1149 #ifdef CONFIG_PPC 1150 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)) 1151 __gfar_detect_errata_85xx(priv); 1152 else /* non-mpc85xx parts, i.e. e300 core based */ 1153 __gfar_detect_errata_83xx(priv); 1154 #endif 1155 1156 if (priv->errata) 1157 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", 1158 priv->errata); 1159 } 1160 1161 void gfar_mac_reset(struct gfar_private *priv) 1162 { 1163 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1164 u32 tempval; 1165 1166 /* Reset MAC layer */ 1167 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); 1168 1169 /* We need to delay at least 3 TX clocks */ 1170 udelay(3); 1171 1172 /* the soft reset bit is not self-resetting, so we need to 1173 * clear it before resuming normal operation 1174 */ 1175 gfar_write(®s->maccfg1, 0); 1176 1177 udelay(3); 1178 1179 /* Compute rx_buff_size based on config flags */ 1180 gfar_rx_buff_size_config(priv); 1181 1182 /* Initialize the max receive frame/buffer lengths */ 1183 gfar_write(®s->maxfrm, priv->rx_buffer_size); 1184 gfar_write(®s->mrblr, priv->rx_buffer_size); 1185 1186 /* Initialize the Minimum Frame Length Register */ 1187 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); 1188 1189 /* Initialize MACCFG2. */ 1190 tempval = MACCFG2_INIT_SETTINGS; 1191 1192 /* If the mtu is larger than the max size for standard 1193 * ethernet frames (ie, a jumbo frame), then set maccfg2 1194 * to allow huge frames, and to check the length 1195 */ 1196 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE || 1197 gfar_has_errata(priv, GFAR_ERRATA_74)) 1198 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; 1199 1200 gfar_write(®s->maccfg2, tempval); 1201 1202 /* Clear mac addr hash registers */ 1203 gfar_write(®s->igaddr0, 0); 1204 gfar_write(®s->igaddr1, 0); 1205 gfar_write(®s->igaddr2, 0); 1206 gfar_write(®s->igaddr3, 0); 1207 gfar_write(®s->igaddr4, 0); 1208 gfar_write(®s->igaddr5, 0); 1209 gfar_write(®s->igaddr6, 0); 1210 gfar_write(®s->igaddr7, 0); 1211 1212 gfar_write(®s->gaddr0, 0); 1213 gfar_write(®s->gaddr1, 0); 1214 gfar_write(®s->gaddr2, 0); 1215 gfar_write(®s->gaddr3, 0); 1216 gfar_write(®s->gaddr4, 0); 1217 gfar_write(®s->gaddr5, 0); 1218 gfar_write(®s->gaddr6, 0); 1219 gfar_write(®s->gaddr7, 0); 1220 1221 if (priv->extended_hash) 1222 gfar_clear_exact_match(priv->ndev); 1223 1224 gfar_mac_rx_config(priv); 1225 1226 gfar_mac_tx_config(priv); 1227 1228 gfar_set_mac_address(priv->ndev); 1229 1230 gfar_set_multi(priv->ndev); 1231 1232 /* clear ievent and imask before configuring coalescing */ 1233 gfar_ints_disable(priv); 1234 1235 /* Configure the coalescing support */ 1236 gfar_configure_coalescing_all(priv); 1237 } 1238 1239 static void gfar_hw_init(struct gfar_private *priv) 1240 { 1241 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1242 u32 attrs; 1243 1244 /* Stop the DMA engine now, in case it was running before 1245 * (The firmware could have used it, and left it running). 1246 */ 1247 gfar_halt(priv); 1248 1249 gfar_mac_reset(priv); 1250 1251 /* Zero out the rmon mib registers if it has them */ 1252 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { 1253 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib)); 1254 1255 /* Mask off the CAM interrupts */ 1256 gfar_write(®s->rmon.cam1, 0xffffffff); 1257 gfar_write(®s->rmon.cam2, 0xffffffff); 1258 } 1259 1260 /* Initialize ECNTRL */ 1261 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); 1262 1263 /* Set the extraction length and index */ 1264 attrs = ATTRELI_EL(priv->rx_stash_size) | 1265 ATTRELI_EI(priv->rx_stash_index); 1266 1267 gfar_write(®s->attreli, attrs); 1268 1269 /* Start with defaults, and add stashing 1270 * depending on driver parameters 1271 */ 1272 attrs = ATTR_INIT_SETTINGS; 1273 1274 if (priv->bd_stash_en) 1275 attrs |= ATTR_BDSTASH; 1276 1277 if (priv->rx_stash_size != 0) 1278 attrs |= ATTR_BUFSTASH; 1279 1280 gfar_write(®s->attr, attrs); 1281 1282 /* FIFO configs */ 1283 gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR); 1284 gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE); 1285 gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF); 1286 1287 /* Program the interrupt steering regs, only for MG devices */ 1288 if (priv->num_grps > 1) 1289 gfar_write_isrg(priv); 1290 } 1291 1292 static void gfar_init_addr_hash_table(struct gfar_private *priv) 1293 { 1294 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1295 1296 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { 1297 priv->extended_hash = 1; 1298 priv->hash_width = 9; 1299 1300 priv->hash_regs[0] = ®s->igaddr0; 1301 priv->hash_regs[1] = ®s->igaddr1; 1302 priv->hash_regs[2] = ®s->igaddr2; 1303 priv->hash_regs[3] = ®s->igaddr3; 1304 priv->hash_regs[4] = ®s->igaddr4; 1305 priv->hash_regs[5] = ®s->igaddr5; 1306 priv->hash_regs[6] = ®s->igaddr6; 1307 priv->hash_regs[7] = ®s->igaddr7; 1308 priv->hash_regs[8] = ®s->gaddr0; 1309 priv->hash_regs[9] = ®s->gaddr1; 1310 priv->hash_regs[10] = ®s->gaddr2; 1311 priv->hash_regs[11] = ®s->gaddr3; 1312 priv->hash_regs[12] = ®s->gaddr4; 1313 priv->hash_regs[13] = ®s->gaddr5; 1314 priv->hash_regs[14] = ®s->gaddr6; 1315 priv->hash_regs[15] = ®s->gaddr7; 1316 1317 } else { 1318 priv->extended_hash = 0; 1319 priv->hash_width = 8; 1320 1321 priv->hash_regs[0] = ®s->gaddr0; 1322 priv->hash_regs[1] = ®s->gaddr1; 1323 priv->hash_regs[2] = ®s->gaddr2; 1324 priv->hash_regs[3] = ®s->gaddr3; 1325 priv->hash_regs[4] = ®s->gaddr4; 1326 priv->hash_regs[5] = ®s->gaddr5; 1327 priv->hash_regs[6] = ®s->gaddr6; 1328 priv->hash_regs[7] = ®s->gaddr7; 1329 } 1330 } 1331 1332 /* Set up the ethernet device structure, private data, 1333 * and anything else we need before we start 1334 */ 1335 static int gfar_probe(struct platform_device *ofdev) 1336 { 1337 struct net_device *dev = NULL; 1338 struct gfar_private *priv = NULL; 1339 int err = 0, i; 1340 1341 err = gfar_of_init(ofdev, &dev); 1342 1343 if (err) 1344 return err; 1345 1346 priv = netdev_priv(dev); 1347 priv->ndev = dev; 1348 priv->ofdev = ofdev; 1349 priv->dev = &ofdev->dev; 1350 SET_NETDEV_DEV(dev, &ofdev->dev); 1351 1352 spin_lock_init(&priv->bflock); 1353 INIT_WORK(&priv->reset_task, gfar_reset_task); 1354 1355 platform_set_drvdata(ofdev, priv); 1356 1357 gfar_detect_errata(priv); 1358 1359 /* Set the dev->base_addr to the gfar reg region */ 1360 dev->base_addr = (unsigned long) priv->gfargrp[0].regs; 1361 1362 /* Fill in the dev structure */ 1363 dev->watchdog_timeo = TX_TIMEOUT; 1364 dev->mtu = 1500; 1365 dev->netdev_ops = &gfar_netdev_ops; 1366 dev->ethtool_ops = &gfar_ethtool_ops; 1367 1368 /* Register for napi ...We are registering NAPI for each grp */ 1369 for (i = 0; i < priv->num_grps; i++) { 1370 if (priv->poll_mode == GFAR_SQ_POLLING) { 1371 netif_napi_add(dev, &priv->gfargrp[i].napi_rx, 1372 gfar_poll_rx_sq, GFAR_DEV_WEIGHT); 1373 netif_napi_add(dev, &priv->gfargrp[i].napi_tx, 1374 gfar_poll_tx_sq, 2); 1375 } else { 1376 netif_napi_add(dev, &priv->gfargrp[i].napi_rx, 1377 gfar_poll_rx, GFAR_DEV_WEIGHT); 1378 netif_napi_add(dev, &priv->gfargrp[i].napi_tx, 1379 gfar_poll_tx, 2); 1380 } 1381 } 1382 1383 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { 1384 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | 1385 NETIF_F_RXCSUM; 1386 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | 1387 NETIF_F_RXCSUM | NETIF_F_HIGHDMA; 1388 } 1389 1390 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { 1391 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 1392 NETIF_F_HW_VLAN_CTAG_RX; 1393 dev->features |= NETIF_F_HW_VLAN_CTAG_RX; 1394 } 1395 1396 gfar_init_addr_hash_table(priv); 1397 1398 /* Insert receive time stamps into padding alignment bytes */ 1399 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) 1400 priv->padding = 8; 1401 1402 if (dev->features & NETIF_F_IP_CSUM || 1403 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) 1404 dev->needed_headroom = GMAC_FCB_LEN; 1405 1406 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; 1407 1408 /* Initializing some of the rx/tx queue level parameters */ 1409 for (i = 0; i < priv->num_tx_queues; i++) { 1410 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; 1411 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; 1412 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; 1413 priv->tx_queue[i]->txic = DEFAULT_TXIC; 1414 } 1415 1416 for (i = 0; i < priv->num_rx_queues; i++) { 1417 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; 1418 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; 1419 priv->rx_queue[i]->rxic = DEFAULT_RXIC; 1420 } 1421 1422 /* always enable rx filer */ 1423 priv->rx_filer_enable = 1; 1424 /* Enable most messages by default */ 1425 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; 1426 /* use pritority h/w tx queue scheduling for single queue devices */ 1427 if (priv->num_tx_queues == 1) 1428 priv->prio_sched_en = 1; 1429 1430 set_bit(GFAR_DOWN, &priv->state); 1431 1432 gfar_hw_init(priv); 1433 1434 /* Carrier starts down, phylib will bring it up */ 1435 netif_carrier_off(dev); 1436 1437 err = register_netdev(dev); 1438 1439 if (err) { 1440 pr_err("%s: Cannot register net device, aborting\n", dev->name); 1441 goto register_fail; 1442 } 1443 1444 device_init_wakeup(&dev->dev, 1445 priv->device_flags & 1446 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); 1447 1448 /* fill out IRQ number and name fields */ 1449 for (i = 0; i < priv->num_grps; i++) { 1450 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 1451 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 1452 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s", 1453 dev->name, "_g", '0' + i, "_tx"); 1454 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s", 1455 dev->name, "_g", '0' + i, "_rx"); 1456 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s", 1457 dev->name, "_g", '0' + i, "_er"); 1458 } else 1459 strcpy(gfar_irq(grp, TX)->name, dev->name); 1460 } 1461 1462 /* Initialize the filer table */ 1463 gfar_init_filer_table(priv); 1464 1465 /* Print out the device info */ 1466 netdev_info(dev, "mac: %pM\n", dev->dev_addr); 1467 1468 /* Even more device info helps when determining which kernel 1469 * provided which set of benchmarks. 1470 */ 1471 netdev_info(dev, "Running with NAPI enabled\n"); 1472 for (i = 0; i < priv->num_rx_queues; i++) 1473 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n", 1474 i, priv->rx_queue[i]->rx_ring_size); 1475 for (i = 0; i < priv->num_tx_queues; i++) 1476 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n", 1477 i, priv->tx_queue[i]->tx_ring_size); 1478 1479 return 0; 1480 1481 register_fail: 1482 unmap_group_regs(priv); 1483 gfar_free_rx_queues(priv); 1484 gfar_free_tx_queues(priv); 1485 of_node_put(priv->phy_node); 1486 of_node_put(priv->tbi_node); 1487 free_gfar_dev(priv); 1488 return err; 1489 } 1490 1491 static int gfar_remove(struct platform_device *ofdev) 1492 { 1493 struct gfar_private *priv = platform_get_drvdata(ofdev); 1494 1495 of_node_put(priv->phy_node); 1496 of_node_put(priv->tbi_node); 1497 1498 unregister_netdev(priv->ndev); 1499 unmap_group_regs(priv); 1500 gfar_free_rx_queues(priv); 1501 gfar_free_tx_queues(priv); 1502 free_gfar_dev(priv); 1503 1504 return 0; 1505 } 1506 1507 #ifdef CONFIG_PM 1508 1509 static int gfar_suspend(struct device *dev) 1510 { 1511 struct gfar_private *priv = dev_get_drvdata(dev); 1512 struct net_device *ndev = priv->ndev; 1513 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1514 unsigned long flags; 1515 u32 tempval; 1516 1517 int magic_packet = priv->wol_en && 1518 (priv->device_flags & 1519 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); 1520 1521 netif_device_detach(ndev); 1522 1523 if (netif_running(ndev)) { 1524 1525 local_irq_save(flags); 1526 lock_tx_qs(priv); 1527 1528 gfar_halt_nodisable(priv); 1529 1530 /* Disable Tx, and Rx if wake-on-LAN is disabled. */ 1531 tempval = gfar_read(®s->maccfg1); 1532 1533 tempval &= ~MACCFG1_TX_EN; 1534 1535 if (!magic_packet) 1536 tempval &= ~MACCFG1_RX_EN; 1537 1538 gfar_write(®s->maccfg1, tempval); 1539 1540 unlock_tx_qs(priv); 1541 local_irq_restore(flags); 1542 1543 disable_napi(priv); 1544 1545 if (magic_packet) { 1546 /* Enable interrupt on Magic Packet */ 1547 gfar_write(®s->imask, IMASK_MAG); 1548 1549 /* Enable Magic Packet mode */ 1550 tempval = gfar_read(®s->maccfg2); 1551 tempval |= MACCFG2_MPEN; 1552 gfar_write(®s->maccfg2, tempval); 1553 } else { 1554 phy_stop(priv->phydev); 1555 } 1556 } 1557 1558 return 0; 1559 } 1560 1561 static int gfar_resume(struct device *dev) 1562 { 1563 struct gfar_private *priv = dev_get_drvdata(dev); 1564 struct net_device *ndev = priv->ndev; 1565 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1566 unsigned long flags; 1567 u32 tempval; 1568 int magic_packet = priv->wol_en && 1569 (priv->device_flags & 1570 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); 1571 1572 if (!netif_running(ndev)) { 1573 netif_device_attach(ndev); 1574 return 0; 1575 } 1576 1577 if (!magic_packet && priv->phydev) 1578 phy_start(priv->phydev); 1579 1580 /* Disable Magic Packet mode, in case something 1581 * else woke us up. 1582 */ 1583 local_irq_save(flags); 1584 lock_tx_qs(priv); 1585 1586 tempval = gfar_read(®s->maccfg2); 1587 tempval &= ~MACCFG2_MPEN; 1588 gfar_write(®s->maccfg2, tempval); 1589 1590 gfar_start(priv); 1591 1592 unlock_tx_qs(priv); 1593 local_irq_restore(flags); 1594 1595 netif_device_attach(ndev); 1596 1597 enable_napi(priv); 1598 1599 return 0; 1600 } 1601 1602 static int gfar_restore(struct device *dev) 1603 { 1604 struct gfar_private *priv = dev_get_drvdata(dev); 1605 struct net_device *ndev = priv->ndev; 1606 1607 if (!netif_running(ndev)) { 1608 netif_device_attach(ndev); 1609 1610 return 0; 1611 } 1612 1613 if (gfar_init_bds(ndev)) { 1614 free_skb_resources(priv); 1615 return -ENOMEM; 1616 } 1617 1618 gfar_mac_reset(priv); 1619 1620 gfar_init_tx_rx_base(priv); 1621 1622 gfar_start(priv); 1623 1624 priv->oldlink = 0; 1625 priv->oldspeed = 0; 1626 priv->oldduplex = -1; 1627 1628 if (priv->phydev) 1629 phy_start(priv->phydev); 1630 1631 netif_device_attach(ndev); 1632 enable_napi(priv); 1633 1634 return 0; 1635 } 1636 1637 static struct dev_pm_ops gfar_pm_ops = { 1638 .suspend = gfar_suspend, 1639 .resume = gfar_resume, 1640 .freeze = gfar_suspend, 1641 .thaw = gfar_resume, 1642 .restore = gfar_restore, 1643 }; 1644 1645 #define GFAR_PM_OPS (&gfar_pm_ops) 1646 1647 #else 1648 1649 #define GFAR_PM_OPS NULL 1650 1651 #endif 1652 1653 /* Reads the controller's registers to determine what interface 1654 * connects it to the PHY. 1655 */ 1656 static phy_interface_t gfar_get_interface(struct net_device *dev) 1657 { 1658 struct gfar_private *priv = netdev_priv(dev); 1659 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1660 u32 ecntrl; 1661 1662 ecntrl = gfar_read(®s->ecntrl); 1663 1664 if (ecntrl & ECNTRL_SGMII_MODE) 1665 return PHY_INTERFACE_MODE_SGMII; 1666 1667 if (ecntrl & ECNTRL_TBI_MODE) { 1668 if (ecntrl & ECNTRL_REDUCED_MODE) 1669 return PHY_INTERFACE_MODE_RTBI; 1670 else 1671 return PHY_INTERFACE_MODE_TBI; 1672 } 1673 1674 if (ecntrl & ECNTRL_REDUCED_MODE) { 1675 if (ecntrl & ECNTRL_REDUCED_MII_MODE) { 1676 return PHY_INTERFACE_MODE_RMII; 1677 } 1678 else { 1679 phy_interface_t interface = priv->interface; 1680 1681 /* This isn't autodetected right now, so it must 1682 * be set by the device tree or platform code. 1683 */ 1684 if (interface == PHY_INTERFACE_MODE_RGMII_ID) 1685 return PHY_INTERFACE_MODE_RGMII_ID; 1686 1687 return PHY_INTERFACE_MODE_RGMII; 1688 } 1689 } 1690 1691 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) 1692 return PHY_INTERFACE_MODE_GMII; 1693 1694 return PHY_INTERFACE_MODE_MII; 1695 } 1696 1697 1698 /* Initializes driver's PHY state, and attaches to the PHY. 1699 * Returns 0 on success. 1700 */ 1701 static int init_phy(struct net_device *dev) 1702 { 1703 struct gfar_private *priv = netdev_priv(dev); 1704 uint gigabit_support = 1705 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? 1706 GFAR_SUPPORTED_GBIT : 0; 1707 phy_interface_t interface; 1708 1709 priv->oldlink = 0; 1710 priv->oldspeed = 0; 1711 priv->oldduplex = -1; 1712 1713 interface = gfar_get_interface(dev); 1714 1715 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, 1716 interface); 1717 if (!priv->phydev) { 1718 dev_err(&dev->dev, "could not attach to PHY\n"); 1719 return -ENODEV; 1720 } 1721 1722 if (interface == PHY_INTERFACE_MODE_SGMII) 1723 gfar_configure_serdes(dev); 1724 1725 /* Remove any features not supported by the controller */ 1726 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); 1727 priv->phydev->advertising = priv->phydev->supported; 1728 1729 /* Add support for flow control, but don't advertise it by default */ 1730 priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause); 1731 1732 return 0; 1733 } 1734 1735 /* Initialize TBI PHY interface for communicating with the 1736 * SERDES lynx PHY on the chip. We communicate with this PHY 1737 * through the MDIO bus on each controller, treating it as a 1738 * "normal" PHY at the address found in the TBIPA register. We assume 1739 * that the TBIPA register is valid. Either the MDIO bus code will set 1740 * it to a value that doesn't conflict with other PHYs on the bus, or the 1741 * value doesn't matter, as there are no other PHYs on the bus. 1742 */ 1743 static void gfar_configure_serdes(struct net_device *dev) 1744 { 1745 struct gfar_private *priv = netdev_priv(dev); 1746 struct phy_device *tbiphy; 1747 1748 if (!priv->tbi_node) { 1749 dev_warn(&dev->dev, "error: SGMII mode requires that the " 1750 "device tree specify a tbi-handle\n"); 1751 return; 1752 } 1753 1754 tbiphy = of_phy_find_device(priv->tbi_node); 1755 if (!tbiphy) { 1756 dev_err(&dev->dev, "error: Could not get TBI device\n"); 1757 return; 1758 } 1759 1760 /* If the link is already up, we must already be ok, and don't need to 1761 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured 1762 * everything for us? Resetting it takes the link down and requires 1763 * several seconds for it to come back. 1764 */ 1765 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) 1766 return; 1767 1768 /* Single clk mode, mii mode off(for serdes communication) */ 1769 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); 1770 1771 phy_write(tbiphy, MII_ADVERTISE, 1772 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | 1773 ADVERTISE_1000XPSE_ASYM); 1774 1775 phy_write(tbiphy, MII_BMCR, 1776 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | 1777 BMCR_SPEED1000); 1778 } 1779 1780 static int __gfar_is_rx_idle(struct gfar_private *priv) 1781 { 1782 u32 res; 1783 1784 /* Normaly TSEC should not hang on GRS commands, so we should 1785 * actually wait for IEVENT_GRSC flag. 1786 */ 1787 if (!gfar_has_errata(priv, GFAR_ERRATA_A002)) 1788 return 0; 1789 1790 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are 1791 * the same as bits 23-30, the eTSEC Rx is assumed to be idle 1792 * and the Rx can be safely reset. 1793 */ 1794 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); 1795 res &= 0x7f807f80; 1796 if ((res & 0xffff) == (res >> 16)) 1797 return 1; 1798 1799 return 0; 1800 } 1801 1802 /* Halt the receive and transmit queues */ 1803 static void gfar_halt_nodisable(struct gfar_private *priv) 1804 { 1805 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1806 u32 tempval; 1807 unsigned int timeout; 1808 int stopped; 1809 1810 gfar_ints_disable(priv); 1811 1812 if (gfar_is_dma_stopped(priv)) 1813 return; 1814 1815 /* Stop the DMA, and wait for it to stop */ 1816 tempval = gfar_read(®s->dmactrl); 1817 tempval |= (DMACTRL_GRS | DMACTRL_GTS); 1818 gfar_write(®s->dmactrl, tempval); 1819 1820 retry: 1821 timeout = 1000; 1822 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) { 1823 cpu_relax(); 1824 timeout--; 1825 } 1826 1827 if (!timeout) 1828 stopped = gfar_is_dma_stopped(priv); 1829 1830 if (!stopped && !gfar_is_rx_dma_stopped(priv) && 1831 !__gfar_is_rx_idle(priv)) 1832 goto retry; 1833 } 1834 1835 /* Halt the receive and transmit queues */ 1836 void gfar_halt(struct gfar_private *priv) 1837 { 1838 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1839 u32 tempval; 1840 1841 /* Dissable the Rx/Tx hw queues */ 1842 gfar_write(®s->rqueue, 0); 1843 gfar_write(®s->tqueue, 0); 1844 1845 mdelay(10); 1846 1847 gfar_halt_nodisable(priv); 1848 1849 /* Disable Rx/Tx DMA */ 1850 tempval = gfar_read(®s->maccfg1); 1851 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); 1852 gfar_write(®s->maccfg1, tempval); 1853 } 1854 1855 void stop_gfar(struct net_device *dev) 1856 { 1857 struct gfar_private *priv = netdev_priv(dev); 1858 1859 netif_tx_stop_all_queues(dev); 1860 1861 smp_mb__before_atomic(); 1862 set_bit(GFAR_DOWN, &priv->state); 1863 smp_mb__after_atomic(); 1864 1865 disable_napi(priv); 1866 1867 /* disable ints and gracefully shut down Rx/Tx DMA */ 1868 gfar_halt(priv); 1869 1870 phy_stop(priv->phydev); 1871 1872 free_skb_resources(priv); 1873 } 1874 1875 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) 1876 { 1877 struct txbd8 *txbdp; 1878 struct gfar_private *priv = netdev_priv(tx_queue->dev); 1879 int i, j; 1880 1881 txbdp = tx_queue->tx_bd_base; 1882 1883 for (i = 0; i < tx_queue->tx_ring_size; i++) { 1884 if (!tx_queue->tx_skbuff[i]) 1885 continue; 1886 1887 dma_unmap_single(priv->dev, txbdp->bufPtr, 1888 txbdp->length, DMA_TO_DEVICE); 1889 txbdp->lstatus = 0; 1890 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; 1891 j++) { 1892 txbdp++; 1893 dma_unmap_page(priv->dev, txbdp->bufPtr, 1894 txbdp->length, DMA_TO_DEVICE); 1895 } 1896 txbdp++; 1897 dev_kfree_skb_any(tx_queue->tx_skbuff[i]); 1898 tx_queue->tx_skbuff[i] = NULL; 1899 } 1900 kfree(tx_queue->tx_skbuff); 1901 tx_queue->tx_skbuff = NULL; 1902 } 1903 1904 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) 1905 { 1906 struct rxbd8 *rxbdp; 1907 struct gfar_private *priv = netdev_priv(rx_queue->dev); 1908 int i; 1909 1910 rxbdp = rx_queue->rx_bd_base; 1911 1912 for (i = 0; i < rx_queue->rx_ring_size; i++) { 1913 if (rx_queue->rx_skbuff[i]) { 1914 dma_unmap_single(priv->dev, rxbdp->bufPtr, 1915 priv->rx_buffer_size, 1916 DMA_FROM_DEVICE); 1917 dev_kfree_skb_any(rx_queue->rx_skbuff[i]); 1918 rx_queue->rx_skbuff[i] = NULL; 1919 } 1920 rxbdp->lstatus = 0; 1921 rxbdp->bufPtr = 0; 1922 rxbdp++; 1923 } 1924 kfree(rx_queue->rx_skbuff); 1925 rx_queue->rx_skbuff = NULL; 1926 } 1927 1928 /* If there are any tx skbs or rx skbs still around, free them. 1929 * Then free tx_skbuff and rx_skbuff 1930 */ 1931 static void free_skb_resources(struct gfar_private *priv) 1932 { 1933 struct gfar_priv_tx_q *tx_queue = NULL; 1934 struct gfar_priv_rx_q *rx_queue = NULL; 1935 int i; 1936 1937 /* Go through all the buffer descriptors and free their data buffers */ 1938 for (i = 0; i < priv->num_tx_queues; i++) { 1939 struct netdev_queue *txq; 1940 1941 tx_queue = priv->tx_queue[i]; 1942 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); 1943 if (tx_queue->tx_skbuff) 1944 free_skb_tx_queue(tx_queue); 1945 netdev_tx_reset_queue(txq); 1946 } 1947 1948 for (i = 0; i < priv->num_rx_queues; i++) { 1949 rx_queue = priv->rx_queue[i]; 1950 if (rx_queue->rx_skbuff) 1951 free_skb_rx_queue(rx_queue); 1952 } 1953 1954 dma_free_coherent(priv->dev, 1955 sizeof(struct txbd8) * priv->total_tx_ring_size + 1956 sizeof(struct rxbd8) * priv->total_rx_ring_size, 1957 priv->tx_queue[0]->tx_bd_base, 1958 priv->tx_queue[0]->tx_bd_dma_base); 1959 } 1960 1961 void gfar_start(struct gfar_private *priv) 1962 { 1963 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1964 u32 tempval; 1965 int i = 0; 1966 1967 /* Enable Rx/Tx hw queues */ 1968 gfar_write(®s->rqueue, priv->rqueue); 1969 gfar_write(®s->tqueue, priv->tqueue); 1970 1971 /* Initialize DMACTRL to have WWR and WOP */ 1972 tempval = gfar_read(®s->dmactrl); 1973 tempval |= DMACTRL_INIT_SETTINGS; 1974 gfar_write(®s->dmactrl, tempval); 1975 1976 /* Make sure we aren't stopped */ 1977 tempval = gfar_read(®s->dmactrl); 1978 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); 1979 gfar_write(®s->dmactrl, tempval); 1980 1981 for (i = 0; i < priv->num_grps; i++) { 1982 regs = priv->gfargrp[i].regs; 1983 /* Clear THLT/RHLT, so that the DMA starts polling now */ 1984 gfar_write(®s->tstat, priv->gfargrp[i].tstat); 1985 gfar_write(®s->rstat, priv->gfargrp[i].rstat); 1986 } 1987 1988 /* Enable Rx/Tx DMA */ 1989 tempval = gfar_read(®s->maccfg1); 1990 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 1991 gfar_write(®s->maccfg1, tempval); 1992 1993 gfar_ints_enable(priv); 1994 1995 priv->ndev->trans_start = jiffies; /* prevent tx timeout */ 1996 } 1997 1998 static void free_grp_irqs(struct gfar_priv_grp *grp) 1999 { 2000 free_irq(gfar_irq(grp, TX)->irq, grp); 2001 free_irq(gfar_irq(grp, RX)->irq, grp); 2002 free_irq(gfar_irq(grp, ER)->irq, grp); 2003 } 2004 2005 static int register_grp_irqs(struct gfar_priv_grp *grp) 2006 { 2007 struct gfar_private *priv = grp->priv; 2008 struct net_device *dev = priv->ndev; 2009 int err; 2010 2011 /* If the device has multiple interrupts, register for 2012 * them. Otherwise, only register for the one 2013 */ 2014 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 2015 /* Install our interrupt handlers for Error, 2016 * Transmit, and Receive 2017 */ 2018 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0, 2019 gfar_irq(grp, ER)->name, grp); 2020 if (err < 0) { 2021 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2022 gfar_irq(grp, ER)->irq); 2023 2024 goto err_irq_fail; 2025 } 2026 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0, 2027 gfar_irq(grp, TX)->name, grp); 2028 if (err < 0) { 2029 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2030 gfar_irq(grp, TX)->irq); 2031 goto tx_irq_fail; 2032 } 2033 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0, 2034 gfar_irq(grp, RX)->name, grp); 2035 if (err < 0) { 2036 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2037 gfar_irq(grp, RX)->irq); 2038 goto rx_irq_fail; 2039 } 2040 } else { 2041 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0, 2042 gfar_irq(grp, TX)->name, grp); 2043 if (err < 0) { 2044 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2045 gfar_irq(grp, TX)->irq); 2046 goto err_irq_fail; 2047 } 2048 } 2049 2050 return 0; 2051 2052 rx_irq_fail: 2053 free_irq(gfar_irq(grp, TX)->irq, grp); 2054 tx_irq_fail: 2055 free_irq(gfar_irq(grp, ER)->irq, grp); 2056 err_irq_fail: 2057 return err; 2058 2059 } 2060 2061 static void gfar_free_irq(struct gfar_private *priv) 2062 { 2063 int i; 2064 2065 /* Free the IRQs */ 2066 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 2067 for (i = 0; i < priv->num_grps; i++) 2068 free_grp_irqs(&priv->gfargrp[i]); 2069 } else { 2070 for (i = 0; i < priv->num_grps; i++) 2071 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq, 2072 &priv->gfargrp[i]); 2073 } 2074 } 2075 2076 static int gfar_request_irq(struct gfar_private *priv) 2077 { 2078 int err, i, j; 2079 2080 for (i = 0; i < priv->num_grps; i++) { 2081 err = register_grp_irqs(&priv->gfargrp[i]); 2082 if (err) { 2083 for (j = 0; j < i; j++) 2084 free_grp_irqs(&priv->gfargrp[j]); 2085 return err; 2086 } 2087 } 2088 2089 return 0; 2090 } 2091 2092 /* Bring the controller up and running */ 2093 int startup_gfar(struct net_device *ndev) 2094 { 2095 struct gfar_private *priv = netdev_priv(ndev); 2096 int err; 2097 2098 gfar_mac_reset(priv); 2099 2100 err = gfar_alloc_skb_resources(ndev); 2101 if (err) 2102 return err; 2103 2104 gfar_init_tx_rx_base(priv); 2105 2106 smp_mb__before_atomic(); 2107 clear_bit(GFAR_DOWN, &priv->state); 2108 smp_mb__after_atomic(); 2109 2110 /* Start Rx/Tx DMA and enable the interrupts */ 2111 gfar_start(priv); 2112 2113 phy_start(priv->phydev); 2114 2115 enable_napi(priv); 2116 2117 netif_tx_wake_all_queues(ndev); 2118 2119 return 0; 2120 } 2121 2122 /* Called when something needs to use the ethernet device 2123 * Returns 0 for success. 2124 */ 2125 static int gfar_enet_open(struct net_device *dev) 2126 { 2127 struct gfar_private *priv = netdev_priv(dev); 2128 int err; 2129 2130 err = init_phy(dev); 2131 if (err) 2132 return err; 2133 2134 err = gfar_request_irq(priv); 2135 if (err) 2136 return err; 2137 2138 err = startup_gfar(dev); 2139 if (err) 2140 return err; 2141 2142 device_set_wakeup_enable(&dev->dev, priv->wol_en); 2143 2144 return err; 2145 } 2146 2147 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) 2148 { 2149 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); 2150 2151 memset(fcb, 0, GMAC_FCB_LEN); 2152 2153 return fcb; 2154 } 2155 2156 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb, 2157 int fcb_length) 2158 { 2159 /* If we're here, it's a IP packet with a TCP or UDP 2160 * payload. We set it to checksum, using a pseudo-header 2161 * we provide 2162 */ 2163 u8 flags = TXFCB_DEFAULT; 2164 2165 /* Tell the controller what the protocol is 2166 * And provide the already calculated phcs 2167 */ 2168 if (ip_hdr(skb)->protocol == IPPROTO_UDP) { 2169 flags |= TXFCB_UDP; 2170 fcb->phcs = udp_hdr(skb)->check; 2171 } else 2172 fcb->phcs = tcp_hdr(skb)->check; 2173 2174 /* l3os is the distance between the start of the 2175 * frame (skb->data) and the start of the IP hdr. 2176 * l4os is the distance between the start of the 2177 * l3 hdr and the l4 hdr 2178 */ 2179 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length); 2180 fcb->l4os = skb_network_header_len(skb); 2181 2182 fcb->flags = flags; 2183 } 2184 2185 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) 2186 { 2187 fcb->flags |= TXFCB_VLN; 2188 fcb->vlctl = skb_vlan_tag_get(skb); 2189 } 2190 2191 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, 2192 struct txbd8 *base, int ring_size) 2193 { 2194 struct txbd8 *new_bd = bdp + stride; 2195 2196 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; 2197 } 2198 2199 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, 2200 int ring_size) 2201 { 2202 return skip_txbd(bdp, 1, base, ring_size); 2203 } 2204 2205 /* eTSEC12: csum generation not supported for some fcb offsets */ 2206 static inline bool gfar_csum_errata_12(struct gfar_private *priv, 2207 unsigned long fcb_addr) 2208 { 2209 return (gfar_has_errata(priv, GFAR_ERRATA_12) && 2210 (fcb_addr % 0x20) > 0x18); 2211 } 2212 2213 /* eTSEC76: csum generation for frames larger than 2500 may 2214 * cause excess delays before start of transmission 2215 */ 2216 static inline bool gfar_csum_errata_76(struct gfar_private *priv, 2217 unsigned int len) 2218 { 2219 return (gfar_has_errata(priv, GFAR_ERRATA_76) && 2220 (len > 2500)); 2221 } 2222 2223 /* This is called by the kernel when a frame is ready for transmission. 2224 * It is pointed to by the dev->hard_start_xmit function pointer 2225 */ 2226 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) 2227 { 2228 struct gfar_private *priv = netdev_priv(dev); 2229 struct gfar_priv_tx_q *tx_queue = NULL; 2230 struct netdev_queue *txq; 2231 struct gfar __iomem *regs = NULL; 2232 struct txfcb *fcb = NULL; 2233 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; 2234 u32 lstatus; 2235 int i, rq = 0; 2236 int do_tstamp, do_csum, do_vlan; 2237 u32 bufaddr; 2238 unsigned long flags; 2239 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0; 2240 2241 rq = skb->queue_mapping; 2242 tx_queue = priv->tx_queue[rq]; 2243 txq = netdev_get_tx_queue(dev, rq); 2244 base = tx_queue->tx_bd_base; 2245 regs = tx_queue->grp->regs; 2246 2247 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed); 2248 do_vlan = skb_vlan_tag_present(skb); 2249 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2250 priv->hwts_tx_en; 2251 2252 if (do_csum || do_vlan) 2253 fcb_len = GMAC_FCB_LEN; 2254 2255 /* check if time stamp should be generated */ 2256 if (unlikely(do_tstamp)) 2257 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN; 2258 2259 /* make space for additional header when fcb is needed */ 2260 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) { 2261 struct sk_buff *skb_new; 2262 2263 skb_new = skb_realloc_headroom(skb, fcb_len); 2264 if (!skb_new) { 2265 dev->stats.tx_errors++; 2266 dev_kfree_skb_any(skb); 2267 return NETDEV_TX_OK; 2268 } 2269 2270 if (skb->sk) 2271 skb_set_owner_w(skb_new, skb->sk); 2272 dev_consume_skb_any(skb); 2273 skb = skb_new; 2274 } 2275 2276 /* total number of fragments in the SKB */ 2277 nr_frags = skb_shinfo(skb)->nr_frags; 2278 2279 /* calculate the required number of TxBDs for this skb */ 2280 if (unlikely(do_tstamp)) 2281 nr_txbds = nr_frags + 2; 2282 else 2283 nr_txbds = nr_frags + 1; 2284 2285 /* check if there is space to queue this packet */ 2286 if (nr_txbds > tx_queue->num_txbdfree) { 2287 /* no space, stop the queue */ 2288 netif_tx_stop_queue(txq); 2289 dev->stats.tx_fifo_errors++; 2290 return NETDEV_TX_BUSY; 2291 } 2292 2293 /* Update transmit stats */ 2294 bytes_sent = skb->len; 2295 tx_queue->stats.tx_bytes += bytes_sent; 2296 /* keep Tx bytes on wire for BQL accounting */ 2297 GFAR_CB(skb)->bytes_sent = bytes_sent; 2298 tx_queue->stats.tx_packets++; 2299 2300 txbdp = txbdp_start = tx_queue->cur_tx; 2301 lstatus = txbdp->lstatus; 2302 2303 /* Time stamp insertion requires one additional TxBD */ 2304 if (unlikely(do_tstamp)) 2305 txbdp_tstamp = txbdp = next_txbd(txbdp, base, 2306 tx_queue->tx_ring_size); 2307 2308 if (nr_frags == 0) { 2309 if (unlikely(do_tstamp)) 2310 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST | 2311 TXBD_INTERRUPT); 2312 else 2313 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 2314 } else { 2315 /* Place the fragment addresses and lengths into the TxBDs */ 2316 for (i = 0; i < nr_frags; i++) { 2317 unsigned int frag_len; 2318 /* Point at the next BD, wrapping as needed */ 2319 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2320 2321 frag_len = skb_shinfo(skb)->frags[i].size; 2322 2323 lstatus = txbdp->lstatus | frag_len | 2324 BD_LFLAG(TXBD_READY); 2325 2326 /* Handle the last BD specially */ 2327 if (i == nr_frags - 1) 2328 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 2329 2330 bufaddr = skb_frag_dma_map(priv->dev, 2331 &skb_shinfo(skb)->frags[i], 2332 0, 2333 frag_len, 2334 DMA_TO_DEVICE); 2335 if (unlikely(dma_mapping_error(priv->dev, bufaddr))) 2336 goto dma_map_err; 2337 2338 /* set the TxBD length and buffer pointer */ 2339 txbdp->bufPtr = bufaddr; 2340 txbdp->lstatus = lstatus; 2341 } 2342 2343 lstatus = txbdp_start->lstatus; 2344 } 2345 2346 /* Add TxPAL between FCB and frame if required */ 2347 if (unlikely(do_tstamp)) { 2348 skb_push(skb, GMAC_TXPAL_LEN); 2349 memset(skb->data, 0, GMAC_TXPAL_LEN); 2350 } 2351 2352 /* Add TxFCB if required */ 2353 if (fcb_len) { 2354 fcb = gfar_add_fcb(skb); 2355 lstatus |= BD_LFLAG(TXBD_TOE); 2356 } 2357 2358 /* Set up checksumming */ 2359 if (do_csum) { 2360 gfar_tx_checksum(skb, fcb, fcb_len); 2361 2362 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) || 2363 unlikely(gfar_csum_errata_76(priv, skb->len))) { 2364 __skb_pull(skb, GMAC_FCB_LEN); 2365 skb_checksum_help(skb); 2366 if (do_vlan || do_tstamp) { 2367 /* put back a new fcb for vlan/tstamp TOE */ 2368 fcb = gfar_add_fcb(skb); 2369 } else { 2370 /* Tx TOE not used */ 2371 lstatus &= ~(BD_LFLAG(TXBD_TOE)); 2372 fcb = NULL; 2373 } 2374 } 2375 } 2376 2377 if (do_vlan) 2378 gfar_tx_vlan(skb, fcb); 2379 2380 /* Setup tx hardware time stamping if requested */ 2381 if (unlikely(do_tstamp)) { 2382 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2383 fcb->ptp = 1; 2384 } 2385 2386 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb), 2387 DMA_TO_DEVICE); 2388 if (unlikely(dma_mapping_error(priv->dev, bufaddr))) 2389 goto dma_map_err; 2390 2391 txbdp_start->bufPtr = bufaddr; 2392 2393 /* If time stamping is requested one additional TxBD must be set up. The 2394 * first TxBD points to the FCB and must have a data length of 2395 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with 2396 * the full frame length. 2397 */ 2398 if (unlikely(do_tstamp)) { 2399 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len; 2400 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) | 2401 (skb_headlen(skb) - fcb_len); 2402 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; 2403 } else { 2404 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); 2405 } 2406 2407 netdev_tx_sent_queue(txq, bytes_sent); 2408 2409 /* We can work in parallel with gfar_clean_tx_ring(), except 2410 * when modifying num_txbdfree. Note that we didn't grab the lock 2411 * when we were reading the num_txbdfree and checking for available 2412 * space, that's because outside of this function it can only grow, 2413 * and once we've got needed space, it cannot suddenly disappear. 2414 * 2415 * The lock also protects us from gfar_error(), which can modify 2416 * regs->tstat and thus retrigger the transfers, which is why we 2417 * also must grab the lock before setting ready bit for the first 2418 * to be transmitted BD. 2419 */ 2420 spin_lock_irqsave(&tx_queue->txlock, flags); 2421 2422 gfar_wmb(); 2423 2424 txbdp_start->lstatus = lstatus; 2425 2426 gfar_wmb(); /* force lstatus write before tx_skbuff */ 2427 2428 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; 2429 2430 /* Update the current skb pointer to the next entry we will use 2431 * (wrapping if necessary) 2432 */ 2433 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & 2434 TX_RING_MOD_MASK(tx_queue->tx_ring_size); 2435 2436 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2437 2438 /* reduce TxBD free count */ 2439 tx_queue->num_txbdfree -= (nr_txbds); 2440 2441 /* If the next BD still needs to be cleaned up, then the bds 2442 * are full. We need to tell the kernel to stop sending us stuff. 2443 */ 2444 if (!tx_queue->num_txbdfree) { 2445 netif_tx_stop_queue(txq); 2446 2447 dev->stats.tx_fifo_errors++; 2448 } 2449 2450 /* Tell the DMA to go go go */ 2451 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); 2452 2453 /* Unlock priv */ 2454 spin_unlock_irqrestore(&tx_queue->txlock, flags); 2455 2456 return NETDEV_TX_OK; 2457 2458 dma_map_err: 2459 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size); 2460 if (do_tstamp) 2461 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2462 for (i = 0; i < nr_frags; i++) { 2463 lstatus = txbdp->lstatus; 2464 if (!(lstatus & BD_LFLAG(TXBD_READY))) 2465 break; 2466 2467 txbdp->lstatus = lstatus & ~BD_LFLAG(TXBD_READY); 2468 bufaddr = txbdp->bufPtr; 2469 dma_unmap_page(priv->dev, bufaddr, txbdp->length, 2470 DMA_TO_DEVICE); 2471 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2472 } 2473 gfar_wmb(); 2474 dev_kfree_skb_any(skb); 2475 return NETDEV_TX_OK; 2476 } 2477 2478 /* Stops the kernel queue, and halts the controller */ 2479 static int gfar_close(struct net_device *dev) 2480 { 2481 struct gfar_private *priv = netdev_priv(dev); 2482 2483 cancel_work_sync(&priv->reset_task); 2484 stop_gfar(dev); 2485 2486 /* Disconnect from the PHY */ 2487 phy_disconnect(priv->phydev); 2488 priv->phydev = NULL; 2489 2490 gfar_free_irq(priv); 2491 2492 return 0; 2493 } 2494 2495 /* Changes the mac address if the controller is not running. */ 2496 static int gfar_set_mac_address(struct net_device *dev) 2497 { 2498 gfar_set_mac_for_addr(dev, 0, dev->dev_addr); 2499 2500 return 0; 2501 } 2502 2503 static int gfar_change_mtu(struct net_device *dev, int new_mtu) 2504 { 2505 struct gfar_private *priv = netdev_priv(dev); 2506 int frame_size = new_mtu + ETH_HLEN; 2507 2508 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { 2509 netif_err(priv, drv, dev, "Invalid MTU setting\n"); 2510 return -EINVAL; 2511 } 2512 2513 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state)) 2514 cpu_relax(); 2515 2516 if (dev->flags & IFF_UP) 2517 stop_gfar(dev); 2518 2519 dev->mtu = new_mtu; 2520 2521 if (dev->flags & IFF_UP) 2522 startup_gfar(dev); 2523 2524 clear_bit_unlock(GFAR_RESETTING, &priv->state); 2525 2526 return 0; 2527 } 2528 2529 void reset_gfar(struct net_device *ndev) 2530 { 2531 struct gfar_private *priv = netdev_priv(ndev); 2532 2533 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state)) 2534 cpu_relax(); 2535 2536 stop_gfar(ndev); 2537 startup_gfar(ndev); 2538 2539 clear_bit_unlock(GFAR_RESETTING, &priv->state); 2540 } 2541 2542 /* gfar_reset_task gets scheduled when a packet has not been 2543 * transmitted after a set amount of time. 2544 * For now, assume that clearing out all the structures, and 2545 * starting over will fix the problem. 2546 */ 2547 static void gfar_reset_task(struct work_struct *work) 2548 { 2549 struct gfar_private *priv = container_of(work, struct gfar_private, 2550 reset_task); 2551 reset_gfar(priv->ndev); 2552 } 2553 2554 static void gfar_timeout(struct net_device *dev) 2555 { 2556 struct gfar_private *priv = netdev_priv(dev); 2557 2558 dev->stats.tx_errors++; 2559 schedule_work(&priv->reset_task); 2560 } 2561 2562 static void gfar_align_skb(struct sk_buff *skb) 2563 { 2564 /* We need the data buffer to be aligned properly. We will reserve 2565 * as many bytes as needed to align the data properly 2566 */ 2567 skb_reserve(skb, RXBUF_ALIGNMENT - 2568 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1))); 2569 } 2570 2571 /* Interrupt Handler for Transmit complete */ 2572 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) 2573 { 2574 struct net_device *dev = tx_queue->dev; 2575 struct netdev_queue *txq; 2576 struct gfar_private *priv = netdev_priv(dev); 2577 struct txbd8 *bdp, *next = NULL; 2578 struct txbd8 *lbdp = NULL; 2579 struct txbd8 *base = tx_queue->tx_bd_base; 2580 struct sk_buff *skb; 2581 int skb_dirtytx; 2582 int tx_ring_size = tx_queue->tx_ring_size; 2583 int frags = 0, nr_txbds = 0; 2584 int i; 2585 int howmany = 0; 2586 int tqi = tx_queue->qindex; 2587 unsigned int bytes_sent = 0; 2588 u32 lstatus; 2589 size_t buflen; 2590 2591 txq = netdev_get_tx_queue(dev, tqi); 2592 bdp = tx_queue->dirty_tx; 2593 skb_dirtytx = tx_queue->skb_dirtytx; 2594 2595 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { 2596 unsigned long flags; 2597 2598 frags = skb_shinfo(skb)->nr_frags; 2599 2600 /* When time stamping, one additional TxBD must be freed. 2601 * Also, we need to dma_unmap_single() the TxPAL. 2602 */ 2603 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) 2604 nr_txbds = frags + 2; 2605 else 2606 nr_txbds = frags + 1; 2607 2608 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); 2609 2610 lstatus = lbdp->lstatus; 2611 2612 /* Only clean completed frames */ 2613 if ((lstatus & BD_LFLAG(TXBD_READY)) && 2614 (lstatus & BD_LENGTH_MASK)) 2615 break; 2616 2617 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { 2618 next = next_txbd(bdp, base, tx_ring_size); 2619 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN; 2620 } else 2621 buflen = bdp->length; 2622 2623 dma_unmap_single(priv->dev, bdp->bufPtr, 2624 buflen, DMA_TO_DEVICE); 2625 2626 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { 2627 struct skb_shared_hwtstamps shhwtstamps; 2628 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7); 2629 2630 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 2631 shhwtstamps.hwtstamp = ns_to_ktime(*ns); 2632 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN); 2633 skb_tstamp_tx(skb, &shhwtstamps); 2634 bdp->lstatus &= BD_LFLAG(TXBD_WRAP); 2635 bdp = next; 2636 } 2637 2638 bdp->lstatus &= BD_LFLAG(TXBD_WRAP); 2639 bdp = next_txbd(bdp, base, tx_ring_size); 2640 2641 for (i = 0; i < frags; i++) { 2642 dma_unmap_page(priv->dev, bdp->bufPtr, 2643 bdp->length, DMA_TO_DEVICE); 2644 bdp->lstatus &= BD_LFLAG(TXBD_WRAP); 2645 bdp = next_txbd(bdp, base, tx_ring_size); 2646 } 2647 2648 bytes_sent += GFAR_CB(skb)->bytes_sent; 2649 2650 dev_kfree_skb_any(skb); 2651 2652 tx_queue->tx_skbuff[skb_dirtytx] = NULL; 2653 2654 skb_dirtytx = (skb_dirtytx + 1) & 2655 TX_RING_MOD_MASK(tx_ring_size); 2656 2657 howmany++; 2658 spin_lock_irqsave(&tx_queue->txlock, flags); 2659 tx_queue->num_txbdfree += nr_txbds; 2660 spin_unlock_irqrestore(&tx_queue->txlock, flags); 2661 } 2662 2663 /* If we freed a buffer, we can restart transmission, if necessary */ 2664 if (tx_queue->num_txbdfree && 2665 netif_tx_queue_stopped(txq) && 2666 !(test_bit(GFAR_DOWN, &priv->state))) 2667 netif_wake_subqueue(priv->ndev, tqi); 2668 2669 /* Update dirty indicators */ 2670 tx_queue->skb_dirtytx = skb_dirtytx; 2671 tx_queue->dirty_tx = bdp; 2672 2673 netdev_tx_completed_queue(txq, howmany, bytes_sent); 2674 } 2675 2676 static struct sk_buff *gfar_alloc_skb(struct net_device *dev) 2677 { 2678 struct gfar_private *priv = netdev_priv(dev); 2679 struct sk_buff *skb; 2680 2681 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT); 2682 if (!skb) 2683 return NULL; 2684 2685 gfar_align_skb(skb); 2686 2687 return skb; 2688 } 2689 2690 static struct sk_buff *gfar_new_skb(struct net_device *dev, dma_addr_t *bufaddr) 2691 { 2692 struct gfar_private *priv = netdev_priv(dev); 2693 struct sk_buff *skb; 2694 dma_addr_t addr; 2695 2696 skb = gfar_alloc_skb(dev); 2697 if (!skb) 2698 return NULL; 2699 2700 addr = dma_map_single(priv->dev, skb->data, 2701 priv->rx_buffer_size, DMA_FROM_DEVICE); 2702 if (unlikely(dma_mapping_error(priv->dev, addr))) { 2703 dev_kfree_skb_any(skb); 2704 return NULL; 2705 } 2706 2707 *bufaddr = addr; 2708 return skb; 2709 } 2710 2711 static inline void count_errors(unsigned short status, struct net_device *dev) 2712 { 2713 struct gfar_private *priv = netdev_priv(dev); 2714 struct net_device_stats *stats = &dev->stats; 2715 struct gfar_extra_stats *estats = &priv->extra_stats; 2716 2717 /* If the packet was truncated, none of the other errors matter */ 2718 if (status & RXBD_TRUNCATED) { 2719 stats->rx_length_errors++; 2720 2721 atomic64_inc(&estats->rx_trunc); 2722 2723 return; 2724 } 2725 /* Count the errors, if there were any */ 2726 if (status & (RXBD_LARGE | RXBD_SHORT)) { 2727 stats->rx_length_errors++; 2728 2729 if (status & RXBD_LARGE) 2730 atomic64_inc(&estats->rx_large); 2731 else 2732 atomic64_inc(&estats->rx_short); 2733 } 2734 if (status & RXBD_NONOCTET) { 2735 stats->rx_frame_errors++; 2736 atomic64_inc(&estats->rx_nonoctet); 2737 } 2738 if (status & RXBD_CRCERR) { 2739 atomic64_inc(&estats->rx_crcerr); 2740 stats->rx_crc_errors++; 2741 } 2742 if (status & RXBD_OVERRUN) { 2743 atomic64_inc(&estats->rx_overrun); 2744 stats->rx_crc_errors++; 2745 } 2746 } 2747 2748 irqreturn_t gfar_receive(int irq, void *grp_id) 2749 { 2750 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id; 2751 unsigned long flags; 2752 u32 imask; 2753 2754 if (likely(napi_schedule_prep(&grp->napi_rx))) { 2755 spin_lock_irqsave(&grp->grplock, flags); 2756 imask = gfar_read(&grp->regs->imask); 2757 imask &= IMASK_RX_DISABLED; 2758 gfar_write(&grp->regs->imask, imask); 2759 spin_unlock_irqrestore(&grp->grplock, flags); 2760 __napi_schedule(&grp->napi_rx); 2761 } else { 2762 /* Clear IEVENT, so interrupts aren't called again 2763 * because of the packets that have already arrived. 2764 */ 2765 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK); 2766 } 2767 2768 return IRQ_HANDLED; 2769 } 2770 2771 /* Interrupt Handler for Transmit complete */ 2772 static irqreturn_t gfar_transmit(int irq, void *grp_id) 2773 { 2774 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id; 2775 unsigned long flags; 2776 u32 imask; 2777 2778 if (likely(napi_schedule_prep(&grp->napi_tx))) { 2779 spin_lock_irqsave(&grp->grplock, flags); 2780 imask = gfar_read(&grp->regs->imask); 2781 imask &= IMASK_TX_DISABLED; 2782 gfar_write(&grp->regs->imask, imask); 2783 spin_unlock_irqrestore(&grp->grplock, flags); 2784 __napi_schedule(&grp->napi_tx); 2785 } else { 2786 /* Clear IEVENT, so interrupts aren't called again 2787 * because of the packets that have already arrived. 2788 */ 2789 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK); 2790 } 2791 2792 return IRQ_HANDLED; 2793 } 2794 2795 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) 2796 { 2797 /* If valid headers were found, and valid sums 2798 * were verified, then we tell the kernel that no 2799 * checksumming is necessary. Otherwise, it is [FIXME] 2800 */ 2801 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) 2802 skb->ip_summed = CHECKSUM_UNNECESSARY; 2803 else 2804 skb_checksum_none_assert(skb); 2805 } 2806 2807 2808 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */ 2809 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, 2810 int amount_pull, struct napi_struct *napi) 2811 { 2812 struct gfar_private *priv = netdev_priv(dev); 2813 struct rxfcb *fcb = NULL; 2814 2815 /* fcb is at the beginning if exists */ 2816 fcb = (struct rxfcb *)skb->data; 2817 2818 /* Remove the FCB from the skb 2819 * Remove the padded bytes, if there are any 2820 */ 2821 if (amount_pull) { 2822 skb_record_rx_queue(skb, fcb->rq); 2823 skb_pull(skb, amount_pull); 2824 } 2825 2826 /* Get receive timestamp from the skb */ 2827 if (priv->hwts_rx_en) { 2828 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); 2829 u64 *ns = (u64 *) skb->data; 2830 2831 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 2832 shhwtstamps->hwtstamp = ns_to_ktime(*ns); 2833 } 2834 2835 if (priv->padding) 2836 skb_pull(skb, priv->padding); 2837 2838 if (dev->features & NETIF_F_RXCSUM) 2839 gfar_rx_checksum(skb, fcb); 2840 2841 /* Tell the skb what kind of packet this is */ 2842 skb->protocol = eth_type_trans(skb, dev); 2843 2844 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here. 2845 * Even if vlan rx accel is disabled, on some chips 2846 * RXFCB_VLN is pseudo randomly set. 2847 */ 2848 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX && 2849 fcb->flags & RXFCB_VLN) 2850 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl); 2851 2852 /* Send the packet up the stack */ 2853 napi_gro_receive(napi, skb); 2854 2855 } 2856 2857 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring 2858 * until the budget/quota has been reached. Returns the number 2859 * of frames handled 2860 */ 2861 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit) 2862 { 2863 struct net_device *dev = rx_queue->dev; 2864 struct rxbd8 *bdp, *base; 2865 struct sk_buff *skb; 2866 int pkt_len; 2867 int amount_pull; 2868 int howmany = 0; 2869 struct gfar_private *priv = netdev_priv(dev); 2870 2871 /* Get the first full descriptor */ 2872 bdp = rx_queue->cur_rx; 2873 base = rx_queue->rx_bd_base; 2874 2875 amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0; 2876 2877 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { 2878 struct sk_buff *newskb; 2879 dma_addr_t bufaddr; 2880 2881 rmb(); 2882 2883 /* Add another skb for the future */ 2884 newskb = gfar_new_skb(dev, &bufaddr); 2885 2886 skb = rx_queue->rx_skbuff[rx_queue->skb_currx]; 2887 2888 dma_unmap_single(priv->dev, bdp->bufPtr, 2889 priv->rx_buffer_size, DMA_FROM_DEVICE); 2890 2891 if (unlikely(!(bdp->status & RXBD_ERR) && 2892 bdp->length > priv->rx_buffer_size)) 2893 bdp->status = RXBD_LARGE; 2894 2895 /* We drop the frame if we failed to allocate a new buffer */ 2896 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || 2897 bdp->status & RXBD_ERR)) { 2898 count_errors(bdp->status, dev); 2899 2900 if (unlikely(!newskb)) { 2901 newskb = skb; 2902 bufaddr = bdp->bufPtr; 2903 } else if (skb) 2904 dev_kfree_skb(skb); 2905 } else { 2906 /* Increment the number of packets */ 2907 rx_queue->stats.rx_packets++; 2908 howmany++; 2909 2910 if (likely(skb)) { 2911 pkt_len = bdp->length - ETH_FCS_LEN; 2912 /* Remove the FCS from the packet length */ 2913 skb_put(skb, pkt_len); 2914 rx_queue->stats.rx_bytes += pkt_len; 2915 skb_record_rx_queue(skb, rx_queue->qindex); 2916 gfar_process_frame(dev, skb, amount_pull, 2917 &rx_queue->grp->napi_rx); 2918 2919 } else { 2920 netif_warn(priv, rx_err, dev, "Missing skb!\n"); 2921 rx_queue->stats.rx_dropped++; 2922 atomic64_inc(&priv->extra_stats.rx_skbmissing); 2923 } 2924 2925 } 2926 2927 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb; 2928 2929 /* Setup the new bdp */ 2930 gfar_init_rxbdp(rx_queue, bdp, bufaddr); 2931 2932 /* Update Last Free RxBD pointer for LFC */ 2933 if (unlikely(rx_queue->rfbptr && priv->tx_actual_en)) 2934 gfar_write(rx_queue->rfbptr, (u32)bdp); 2935 2936 /* Update to the next pointer */ 2937 bdp = next_bd(bdp, base, rx_queue->rx_ring_size); 2938 2939 /* update to point at the next skb */ 2940 rx_queue->skb_currx = (rx_queue->skb_currx + 1) & 2941 RX_RING_MOD_MASK(rx_queue->rx_ring_size); 2942 } 2943 2944 /* Update the current rxbd pointer to be the next one */ 2945 rx_queue->cur_rx = bdp; 2946 2947 return howmany; 2948 } 2949 2950 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget) 2951 { 2952 struct gfar_priv_grp *gfargrp = 2953 container_of(napi, struct gfar_priv_grp, napi_rx); 2954 struct gfar __iomem *regs = gfargrp->regs; 2955 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue; 2956 int work_done = 0; 2957 2958 /* Clear IEVENT, so interrupts aren't called again 2959 * because of the packets that have already arrived 2960 */ 2961 gfar_write(®s->ievent, IEVENT_RX_MASK); 2962 2963 work_done = gfar_clean_rx_ring(rx_queue, budget); 2964 2965 if (work_done < budget) { 2966 u32 imask; 2967 napi_complete(napi); 2968 /* Clear the halt bit in RSTAT */ 2969 gfar_write(®s->rstat, gfargrp->rstat); 2970 2971 spin_lock_irq(&gfargrp->grplock); 2972 imask = gfar_read(®s->imask); 2973 imask |= IMASK_RX_DEFAULT; 2974 gfar_write(®s->imask, imask); 2975 spin_unlock_irq(&gfargrp->grplock); 2976 } 2977 2978 return work_done; 2979 } 2980 2981 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget) 2982 { 2983 struct gfar_priv_grp *gfargrp = 2984 container_of(napi, struct gfar_priv_grp, napi_tx); 2985 struct gfar __iomem *regs = gfargrp->regs; 2986 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue; 2987 u32 imask; 2988 2989 /* Clear IEVENT, so interrupts aren't called again 2990 * because of the packets that have already arrived 2991 */ 2992 gfar_write(®s->ievent, IEVENT_TX_MASK); 2993 2994 /* run Tx cleanup to completion */ 2995 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) 2996 gfar_clean_tx_ring(tx_queue); 2997 2998 napi_complete(napi); 2999 3000 spin_lock_irq(&gfargrp->grplock); 3001 imask = gfar_read(®s->imask); 3002 imask |= IMASK_TX_DEFAULT; 3003 gfar_write(®s->imask, imask); 3004 spin_unlock_irq(&gfargrp->grplock); 3005 3006 return 0; 3007 } 3008 3009 static int gfar_poll_rx(struct napi_struct *napi, int budget) 3010 { 3011 struct gfar_priv_grp *gfargrp = 3012 container_of(napi, struct gfar_priv_grp, napi_rx); 3013 struct gfar_private *priv = gfargrp->priv; 3014 struct gfar __iomem *regs = gfargrp->regs; 3015 struct gfar_priv_rx_q *rx_queue = NULL; 3016 int work_done = 0, work_done_per_q = 0; 3017 int i, budget_per_q = 0; 3018 unsigned long rstat_rxf; 3019 int num_act_queues; 3020 3021 /* Clear IEVENT, so interrupts aren't called again 3022 * because of the packets that have already arrived 3023 */ 3024 gfar_write(®s->ievent, IEVENT_RX_MASK); 3025 3026 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK; 3027 3028 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS); 3029 if (num_act_queues) 3030 budget_per_q = budget/num_act_queues; 3031 3032 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { 3033 /* skip queue if not active */ 3034 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i))) 3035 continue; 3036 3037 rx_queue = priv->rx_queue[i]; 3038 work_done_per_q = 3039 gfar_clean_rx_ring(rx_queue, budget_per_q); 3040 work_done += work_done_per_q; 3041 3042 /* finished processing this queue */ 3043 if (work_done_per_q < budget_per_q) { 3044 /* clear active queue hw indication */ 3045 gfar_write(®s->rstat, 3046 RSTAT_CLEAR_RXF0 >> i); 3047 num_act_queues--; 3048 3049 if (!num_act_queues) 3050 break; 3051 } 3052 } 3053 3054 if (!num_act_queues) { 3055 u32 imask; 3056 napi_complete(napi); 3057 3058 /* Clear the halt bit in RSTAT */ 3059 gfar_write(®s->rstat, gfargrp->rstat); 3060 3061 spin_lock_irq(&gfargrp->grplock); 3062 imask = gfar_read(®s->imask); 3063 imask |= IMASK_RX_DEFAULT; 3064 gfar_write(®s->imask, imask); 3065 spin_unlock_irq(&gfargrp->grplock); 3066 } 3067 3068 return work_done; 3069 } 3070 3071 static int gfar_poll_tx(struct napi_struct *napi, int budget) 3072 { 3073 struct gfar_priv_grp *gfargrp = 3074 container_of(napi, struct gfar_priv_grp, napi_tx); 3075 struct gfar_private *priv = gfargrp->priv; 3076 struct gfar __iomem *regs = gfargrp->regs; 3077 struct gfar_priv_tx_q *tx_queue = NULL; 3078 int has_tx_work = 0; 3079 int i; 3080 3081 /* Clear IEVENT, so interrupts aren't called again 3082 * because of the packets that have already arrived 3083 */ 3084 gfar_write(®s->ievent, IEVENT_TX_MASK); 3085 3086 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) { 3087 tx_queue = priv->tx_queue[i]; 3088 /* run Tx cleanup to completion */ 3089 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) { 3090 gfar_clean_tx_ring(tx_queue); 3091 has_tx_work = 1; 3092 } 3093 } 3094 3095 if (!has_tx_work) { 3096 u32 imask; 3097 napi_complete(napi); 3098 3099 spin_lock_irq(&gfargrp->grplock); 3100 imask = gfar_read(®s->imask); 3101 imask |= IMASK_TX_DEFAULT; 3102 gfar_write(®s->imask, imask); 3103 spin_unlock_irq(&gfargrp->grplock); 3104 } 3105 3106 return 0; 3107 } 3108 3109 3110 #ifdef CONFIG_NET_POLL_CONTROLLER 3111 /* Polling 'interrupt' - used by things like netconsole to send skbs 3112 * without having to re-enable interrupts. It's not called while 3113 * the interrupt routine is executing. 3114 */ 3115 static void gfar_netpoll(struct net_device *dev) 3116 { 3117 struct gfar_private *priv = netdev_priv(dev); 3118 int i; 3119 3120 /* If the device has multiple interrupts, run tx/rx */ 3121 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 3122 for (i = 0; i < priv->num_grps; i++) { 3123 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 3124 3125 disable_irq(gfar_irq(grp, TX)->irq); 3126 disable_irq(gfar_irq(grp, RX)->irq); 3127 disable_irq(gfar_irq(grp, ER)->irq); 3128 gfar_interrupt(gfar_irq(grp, TX)->irq, grp); 3129 enable_irq(gfar_irq(grp, ER)->irq); 3130 enable_irq(gfar_irq(grp, RX)->irq); 3131 enable_irq(gfar_irq(grp, TX)->irq); 3132 } 3133 } else { 3134 for (i = 0; i < priv->num_grps; i++) { 3135 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 3136 3137 disable_irq(gfar_irq(grp, TX)->irq); 3138 gfar_interrupt(gfar_irq(grp, TX)->irq, grp); 3139 enable_irq(gfar_irq(grp, TX)->irq); 3140 } 3141 } 3142 } 3143 #endif 3144 3145 /* The interrupt handler for devices with one interrupt */ 3146 static irqreturn_t gfar_interrupt(int irq, void *grp_id) 3147 { 3148 struct gfar_priv_grp *gfargrp = grp_id; 3149 3150 /* Save ievent for future reference */ 3151 u32 events = gfar_read(&gfargrp->regs->ievent); 3152 3153 /* Check for reception */ 3154 if (events & IEVENT_RX_MASK) 3155 gfar_receive(irq, grp_id); 3156 3157 /* Check for transmit completion */ 3158 if (events & IEVENT_TX_MASK) 3159 gfar_transmit(irq, grp_id); 3160 3161 /* Check for errors */ 3162 if (events & IEVENT_ERR_MASK) 3163 gfar_error(irq, grp_id); 3164 3165 return IRQ_HANDLED; 3166 } 3167 3168 /* Called every time the controller might need to be made 3169 * aware of new link state. The PHY code conveys this 3170 * information through variables in the phydev structure, and this 3171 * function converts those variables into the appropriate 3172 * register values, and can bring down the device if needed. 3173 */ 3174 static void adjust_link(struct net_device *dev) 3175 { 3176 struct gfar_private *priv = netdev_priv(dev); 3177 struct phy_device *phydev = priv->phydev; 3178 3179 if (unlikely(phydev->link != priv->oldlink || 3180 (phydev->link && (phydev->duplex != priv->oldduplex || 3181 phydev->speed != priv->oldspeed)))) 3182 gfar_update_link_state(priv); 3183 } 3184 3185 /* Update the hash table based on the current list of multicast 3186 * addresses we subscribe to. Also, change the promiscuity of 3187 * the device based on the flags (this function is called 3188 * whenever dev->flags is changed 3189 */ 3190 static void gfar_set_multi(struct net_device *dev) 3191 { 3192 struct netdev_hw_addr *ha; 3193 struct gfar_private *priv = netdev_priv(dev); 3194 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3195 u32 tempval; 3196 3197 if (dev->flags & IFF_PROMISC) { 3198 /* Set RCTRL to PROM */ 3199 tempval = gfar_read(®s->rctrl); 3200 tempval |= RCTRL_PROM; 3201 gfar_write(®s->rctrl, tempval); 3202 } else { 3203 /* Set RCTRL to not PROM */ 3204 tempval = gfar_read(®s->rctrl); 3205 tempval &= ~(RCTRL_PROM); 3206 gfar_write(®s->rctrl, tempval); 3207 } 3208 3209 if (dev->flags & IFF_ALLMULTI) { 3210 /* Set the hash to rx all multicast frames */ 3211 gfar_write(®s->igaddr0, 0xffffffff); 3212 gfar_write(®s->igaddr1, 0xffffffff); 3213 gfar_write(®s->igaddr2, 0xffffffff); 3214 gfar_write(®s->igaddr3, 0xffffffff); 3215 gfar_write(®s->igaddr4, 0xffffffff); 3216 gfar_write(®s->igaddr5, 0xffffffff); 3217 gfar_write(®s->igaddr6, 0xffffffff); 3218 gfar_write(®s->igaddr7, 0xffffffff); 3219 gfar_write(®s->gaddr0, 0xffffffff); 3220 gfar_write(®s->gaddr1, 0xffffffff); 3221 gfar_write(®s->gaddr2, 0xffffffff); 3222 gfar_write(®s->gaddr3, 0xffffffff); 3223 gfar_write(®s->gaddr4, 0xffffffff); 3224 gfar_write(®s->gaddr5, 0xffffffff); 3225 gfar_write(®s->gaddr6, 0xffffffff); 3226 gfar_write(®s->gaddr7, 0xffffffff); 3227 } else { 3228 int em_num; 3229 int idx; 3230 3231 /* zero out the hash */ 3232 gfar_write(®s->igaddr0, 0x0); 3233 gfar_write(®s->igaddr1, 0x0); 3234 gfar_write(®s->igaddr2, 0x0); 3235 gfar_write(®s->igaddr3, 0x0); 3236 gfar_write(®s->igaddr4, 0x0); 3237 gfar_write(®s->igaddr5, 0x0); 3238 gfar_write(®s->igaddr6, 0x0); 3239 gfar_write(®s->igaddr7, 0x0); 3240 gfar_write(®s->gaddr0, 0x0); 3241 gfar_write(®s->gaddr1, 0x0); 3242 gfar_write(®s->gaddr2, 0x0); 3243 gfar_write(®s->gaddr3, 0x0); 3244 gfar_write(®s->gaddr4, 0x0); 3245 gfar_write(®s->gaddr5, 0x0); 3246 gfar_write(®s->gaddr6, 0x0); 3247 gfar_write(®s->gaddr7, 0x0); 3248 3249 /* If we have extended hash tables, we need to 3250 * clear the exact match registers to prepare for 3251 * setting them 3252 */ 3253 if (priv->extended_hash) { 3254 em_num = GFAR_EM_NUM + 1; 3255 gfar_clear_exact_match(dev); 3256 idx = 1; 3257 } else { 3258 idx = 0; 3259 em_num = 0; 3260 } 3261 3262 if (netdev_mc_empty(dev)) 3263 return; 3264 3265 /* Parse the list, and set the appropriate bits */ 3266 netdev_for_each_mc_addr(ha, dev) { 3267 if (idx < em_num) { 3268 gfar_set_mac_for_addr(dev, idx, ha->addr); 3269 idx++; 3270 } else 3271 gfar_set_hash_for_addr(dev, ha->addr); 3272 } 3273 } 3274 } 3275 3276 3277 /* Clears each of the exact match registers to zero, so they 3278 * don't interfere with normal reception 3279 */ 3280 static void gfar_clear_exact_match(struct net_device *dev) 3281 { 3282 int idx; 3283 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; 3284 3285 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++) 3286 gfar_set_mac_for_addr(dev, idx, zero_arr); 3287 } 3288 3289 /* Set the appropriate hash bit for the given addr */ 3290 /* The algorithm works like so: 3291 * 1) Take the Destination Address (ie the multicast address), and 3292 * do a CRC on it (little endian), and reverse the bits of the 3293 * result. 3294 * 2) Use the 8 most significant bits as a hash into a 256-entry 3295 * table. The table is controlled through 8 32-bit registers: 3296 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 3297 * gaddr7. This means that the 3 most significant bits in the 3298 * hash index which gaddr register to use, and the 5 other bits 3299 * indicate which bit (assuming an IBM numbering scheme, which 3300 * for PowerPC (tm) is usually the case) in the register holds 3301 * the entry. 3302 */ 3303 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) 3304 { 3305 u32 tempval; 3306 struct gfar_private *priv = netdev_priv(dev); 3307 u32 result = ether_crc(ETH_ALEN, addr); 3308 int width = priv->hash_width; 3309 u8 whichbit = (result >> (32 - width)) & 0x1f; 3310 u8 whichreg = result >> (32 - width + 5); 3311 u32 value = (1 << (31-whichbit)); 3312 3313 tempval = gfar_read(priv->hash_regs[whichreg]); 3314 tempval |= value; 3315 gfar_write(priv->hash_regs[whichreg], tempval); 3316 } 3317 3318 3319 /* There are multiple MAC Address register pairs on some controllers 3320 * This function sets the numth pair to a given address 3321 */ 3322 static void gfar_set_mac_for_addr(struct net_device *dev, int num, 3323 const u8 *addr) 3324 { 3325 struct gfar_private *priv = netdev_priv(dev); 3326 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3327 u32 tempval; 3328 u32 __iomem *macptr = ®s->macstnaddr1; 3329 3330 macptr += num*2; 3331 3332 /* For a station address of 0x12345678ABCD in transmission 3333 * order (BE), MACnADDR1 is set to 0xCDAB7856 and 3334 * MACnADDR2 is set to 0x34120000. 3335 */ 3336 tempval = (addr[5] << 24) | (addr[4] << 16) | 3337 (addr[3] << 8) | addr[2]; 3338 3339 gfar_write(macptr, tempval); 3340 3341 tempval = (addr[1] << 24) | (addr[0] << 16); 3342 3343 gfar_write(macptr+1, tempval); 3344 } 3345 3346 /* GFAR error interrupt handler */ 3347 static irqreturn_t gfar_error(int irq, void *grp_id) 3348 { 3349 struct gfar_priv_grp *gfargrp = grp_id; 3350 struct gfar __iomem *regs = gfargrp->regs; 3351 struct gfar_private *priv= gfargrp->priv; 3352 struct net_device *dev = priv->ndev; 3353 3354 /* Save ievent for future reference */ 3355 u32 events = gfar_read(®s->ievent); 3356 3357 /* Clear IEVENT */ 3358 gfar_write(®s->ievent, events & IEVENT_ERR_MASK); 3359 3360 /* Magic Packet is not an error. */ 3361 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && 3362 (events & IEVENT_MAG)) 3363 events &= ~IEVENT_MAG; 3364 3365 /* Hmm... */ 3366 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) 3367 netdev_dbg(dev, 3368 "error interrupt (ievent=0x%08x imask=0x%08x)\n", 3369 events, gfar_read(®s->imask)); 3370 3371 /* Update the error counters */ 3372 if (events & IEVENT_TXE) { 3373 dev->stats.tx_errors++; 3374 3375 if (events & IEVENT_LC) 3376 dev->stats.tx_window_errors++; 3377 if (events & IEVENT_CRL) 3378 dev->stats.tx_aborted_errors++; 3379 if (events & IEVENT_XFUN) { 3380 unsigned long flags; 3381 3382 netif_dbg(priv, tx_err, dev, 3383 "TX FIFO underrun, packet dropped\n"); 3384 dev->stats.tx_dropped++; 3385 atomic64_inc(&priv->extra_stats.tx_underrun); 3386 3387 local_irq_save(flags); 3388 lock_tx_qs(priv); 3389 3390 /* Reactivate the Tx Queues */ 3391 gfar_write(®s->tstat, gfargrp->tstat); 3392 3393 unlock_tx_qs(priv); 3394 local_irq_restore(flags); 3395 } 3396 netif_dbg(priv, tx_err, dev, "Transmit Error\n"); 3397 } 3398 if (events & IEVENT_BSY) { 3399 dev->stats.rx_errors++; 3400 atomic64_inc(&priv->extra_stats.rx_bsy); 3401 3402 gfar_receive(irq, grp_id); 3403 3404 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n", 3405 gfar_read(®s->rstat)); 3406 } 3407 if (events & IEVENT_BABR) { 3408 dev->stats.rx_errors++; 3409 atomic64_inc(&priv->extra_stats.rx_babr); 3410 3411 netif_dbg(priv, rx_err, dev, "babbling RX error\n"); 3412 } 3413 if (events & IEVENT_EBERR) { 3414 atomic64_inc(&priv->extra_stats.eberr); 3415 netif_dbg(priv, rx_err, dev, "bus error\n"); 3416 } 3417 if (events & IEVENT_RXC) 3418 netif_dbg(priv, rx_status, dev, "control frame\n"); 3419 3420 if (events & IEVENT_BABT) { 3421 atomic64_inc(&priv->extra_stats.tx_babt); 3422 netif_dbg(priv, tx_err, dev, "babbling TX error\n"); 3423 } 3424 return IRQ_HANDLED; 3425 } 3426 3427 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv) 3428 { 3429 struct phy_device *phydev = priv->phydev; 3430 u32 val = 0; 3431 3432 if (!phydev->duplex) 3433 return val; 3434 3435 if (!priv->pause_aneg_en) { 3436 if (priv->tx_pause_en) 3437 val |= MACCFG1_TX_FLOW; 3438 if (priv->rx_pause_en) 3439 val |= MACCFG1_RX_FLOW; 3440 } else { 3441 u16 lcl_adv, rmt_adv; 3442 u8 flowctrl; 3443 /* get link partner capabilities */ 3444 rmt_adv = 0; 3445 if (phydev->pause) 3446 rmt_adv = LPA_PAUSE_CAP; 3447 if (phydev->asym_pause) 3448 rmt_adv |= LPA_PAUSE_ASYM; 3449 3450 lcl_adv = 0; 3451 if (phydev->advertising & ADVERTISED_Pause) 3452 lcl_adv |= ADVERTISE_PAUSE_CAP; 3453 if (phydev->advertising & ADVERTISED_Asym_Pause) 3454 lcl_adv |= ADVERTISE_PAUSE_ASYM; 3455 3456 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 3457 if (flowctrl & FLOW_CTRL_TX) 3458 val |= MACCFG1_TX_FLOW; 3459 if (flowctrl & FLOW_CTRL_RX) 3460 val |= MACCFG1_RX_FLOW; 3461 } 3462 3463 return val; 3464 } 3465 3466 static noinline void gfar_update_link_state(struct gfar_private *priv) 3467 { 3468 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3469 struct phy_device *phydev = priv->phydev; 3470 struct gfar_priv_rx_q *rx_queue = NULL; 3471 int i; 3472 struct rxbd8 *bdp; 3473 3474 if (unlikely(test_bit(GFAR_RESETTING, &priv->state))) 3475 return; 3476 3477 if (phydev->link) { 3478 u32 tempval1 = gfar_read(®s->maccfg1); 3479 u32 tempval = gfar_read(®s->maccfg2); 3480 u32 ecntrl = gfar_read(®s->ecntrl); 3481 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW); 3482 3483 if (phydev->duplex != priv->oldduplex) { 3484 if (!(phydev->duplex)) 3485 tempval &= ~(MACCFG2_FULL_DUPLEX); 3486 else 3487 tempval |= MACCFG2_FULL_DUPLEX; 3488 3489 priv->oldduplex = phydev->duplex; 3490 } 3491 3492 if (phydev->speed != priv->oldspeed) { 3493 switch (phydev->speed) { 3494 case 1000: 3495 tempval = 3496 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); 3497 3498 ecntrl &= ~(ECNTRL_R100); 3499 break; 3500 case 100: 3501 case 10: 3502 tempval = 3503 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); 3504 3505 /* Reduced mode distinguishes 3506 * between 10 and 100 3507 */ 3508 if (phydev->speed == SPEED_100) 3509 ecntrl |= ECNTRL_R100; 3510 else 3511 ecntrl &= ~(ECNTRL_R100); 3512 break; 3513 default: 3514 netif_warn(priv, link, priv->ndev, 3515 "Ack! Speed (%d) is not 10/100/1000!\n", 3516 phydev->speed); 3517 break; 3518 } 3519 3520 priv->oldspeed = phydev->speed; 3521 } 3522 3523 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); 3524 tempval1 |= gfar_get_flowctrl_cfg(priv); 3525 3526 /* Turn last free buffer recording on */ 3527 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) { 3528 for (i = 0; i < priv->num_rx_queues; i++) { 3529 rx_queue = priv->rx_queue[i]; 3530 bdp = rx_queue->cur_rx; 3531 /* skip to previous bd */ 3532 bdp = skip_bd(bdp, rx_queue->rx_ring_size - 1, 3533 rx_queue->rx_bd_base, 3534 rx_queue->rx_ring_size); 3535 3536 if (rx_queue->rfbptr) 3537 gfar_write(rx_queue->rfbptr, (u32)bdp); 3538 } 3539 3540 priv->tx_actual_en = 1; 3541 } 3542 3543 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval)) 3544 priv->tx_actual_en = 0; 3545 3546 gfar_write(®s->maccfg1, tempval1); 3547 gfar_write(®s->maccfg2, tempval); 3548 gfar_write(®s->ecntrl, ecntrl); 3549 3550 if (!priv->oldlink) 3551 priv->oldlink = 1; 3552 3553 } else if (priv->oldlink) { 3554 priv->oldlink = 0; 3555 priv->oldspeed = 0; 3556 priv->oldduplex = -1; 3557 } 3558 3559 if (netif_msg_link(priv)) 3560 phy_print_status(phydev); 3561 } 3562 3563 static struct of_device_id gfar_match[] = 3564 { 3565 { 3566 .type = "network", 3567 .compatible = "gianfar", 3568 }, 3569 { 3570 .compatible = "fsl,etsec2", 3571 }, 3572 {}, 3573 }; 3574 MODULE_DEVICE_TABLE(of, gfar_match); 3575 3576 /* Structure for a device driver */ 3577 static struct platform_driver gfar_driver = { 3578 .driver = { 3579 .name = "fsl-gianfar", 3580 .pm = GFAR_PM_OPS, 3581 .of_match_table = gfar_match, 3582 }, 3583 .probe = gfar_probe, 3584 .remove = gfar_remove, 3585 }; 3586 3587 module_platform_driver(gfar_driver); 3588