1 /*
2  * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
3  * Provides Bus interface for MIIM regs
4  *
5  * Author: Andy Fleming <afleming@freescale.com>
6  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
7  *
8  * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
9  *
10  * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
11  *
12  * This program is free software; you can redistribute  it and/or modify it
13  * under  the terms of  the GNU General  Public License as published by the
14  * Free Software Foundation;  either version 2 of the  License, or (at your
15  * option) any later version.
16  *
17  */
18 
19 #include <linux/kernel.h>
20 #include <linux/string.h>
21 #include <linux/errno.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/module.h>
25 #include <linux/mii.h>
26 #include <linux/of_address.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_device.h>
29 
30 #include <asm/io.h>
31 #if IS_ENABLED(CONFIG_UCC_GETH)
32 #include <soc/fsl/qe/ucc.h>
33 #endif
34 
35 #include "gianfar.h"
36 
37 #define MIIMIND_BUSY		0x00000001
38 #define MIIMIND_NOTVALID	0x00000004
39 #define MIIMCFG_INIT_VALUE	0x00000007
40 #define MIIMCFG_RESET		0x80000000
41 
42 #define MII_READ_COMMAND	0x00000001
43 
44 struct fsl_pq_mii {
45 	u32 miimcfg;	/* MII management configuration reg */
46 	u32 miimcom;	/* MII management command reg */
47 	u32 miimadd;	/* MII management address reg */
48 	u32 miimcon;	/* MII management control reg */
49 	u32 miimstat;	/* MII management status reg */
50 	u32 miimind;	/* MII management indication reg */
51 };
52 
53 struct fsl_pq_mdio {
54 	u8 res1[16];
55 	u32 ieventm;	/* MDIO Interrupt event register (for etsec2)*/
56 	u32 imaskm;	/* MDIO Interrupt mask register (for etsec2)*/
57 	u8 res2[4];
58 	u32 emapm;	/* MDIO Event mapping register (for etsec2)*/
59 	u8 res3[1280];
60 	struct fsl_pq_mii mii;
61 	u8 res4[28];
62 	u32 utbipar;	/* TBI phy address reg (only on UCC) */
63 	u8 res5[2728];
64 } __packed;
65 
66 /* Number of microseconds to wait for an MII register to respond */
67 #define MII_TIMEOUT	1000
68 
69 struct fsl_pq_mdio_priv {
70 	void __iomem *map;
71 	struct fsl_pq_mii __iomem *regs;
72 };
73 
74 /*
75  * Per-device-type data.  Each type of device tree node that we support gets
76  * one of these.
77  *
78  * @mii_offset: the offset of the MII registers within the memory map of the
79  * node.  Some nodes define only the MII registers, and some define the whole
80  * MAC (which includes the MII registers).
81  *
82  * @get_tbipa: determines the address of the TBIPA register
83  *
84  * @ucc_configure: a special function for extra QE configuration
85  */
86 struct fsl_pq_mdio_data {
87 	unsigned int mii_offset;	/* offset of the MII registers */
88 	uint32_t __iomem * (*get_tbipa)(void __iomem *p);
89 	void (*ucc_configure)(phys_addr_t start, phys_addr_t end);
90 };
91 
92 /*
93  * Write value to the PHY at mii_id at register regnum, on the bus attached
94  * to the local interface, which may be different from the generic mdio bus
95  * (tied to a single interface), waiting until the write is done before
96  * returning. This is helpful in programming interfaces like the TBI which
97  * control interfaces like onchip SERDES and are always tied to the local
98  * mdio pins, which may not be the same as system mdio bus, used for
99  * controlling the external PHYs, for example.
100  */
101 static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
102 		u16 value)
103 {
104 	struct fsl_pq_mdio_priv *priv = bus->priv;
105 	struct fsl_pq_mii __iomem *regs = priv->regs;
106 	unsigned int timeout;
107 
108 	/* Set the PHY address and the register address we want to write */
109 	iowrite32be((mii_id << 8) | regnum, &regs->miimadd);
110 
111 	/* Write out the value we want */
112 	iowrite32be(value, &regs->miimcon);
113 
114 	/* Wait for the transaction to finish */
115 	timeout = MII_TIMEOUT;
116 	while ((ioread32be(&regs->miimind) & MIIMIND_BUSY) && timeout) {
117 		cpu_relax();
118 		timeout--;
119 	}
120 
121 	return timeout ? 0 : -ETIMEDOUT;
122 }
123 
124 /*
125  * Read the bus for PHY at addr mii_id, register regnum, and return the value.
126  * Clears miimcom first.
127  *
128  * All PHY operation done on the bus attached to the local interface, which
129  * may be different from the generic mdio bus.  This is helpful in programming
130  * interfaces like the TBI which, in turn, control interfaces like on-chip
131  * SERDES and are always tied to the local mdio pins, which may not be the
132  * same as system mdio bus, used for controlling the external PHYs, for eg.
133  */
134 static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
135 {
136 	struct fsl_pq_mdio_priv *priv = bus->priv;
137 	struct fsl_pq_mii __iomem *regs = priv->regs;
138 	unsigned int timeout;
139 	u16 value;
140 
141 	/* Set the PHY address and the register address we want to read */
142 	iowrite32be((mii_id << 8) | regnum, &regs->miimadd);
143 
144 	/* Clear miimcom, and then initiate a read */
145 	iowrite32be(0, &regs->miimcom);
146 	iowrite32be(MII_READ_COMMAND, &regs->miimcom);
147 
148 	/* Wait for the transaction to finish, normally less than 100us */
149 	timeout = MII_TIMEOUT;
150 	while ((ioread32be(&regs->miimind) &
151 	       (MIIMIND_NOTVALID | MIIMIND_BUSY)) && timeout) {
152 		cpu_relax();
153 		timeout--;
154 	}
155 
156 	if (!timeout)
157 		return -ETIMEDOUT;
158 
159 	/* Grab the value of the register from miimstat */
160 	value = ioread32be(&regs->miimstat);
161 
162 	dev_dbg(&bus->dev, "read %04x from address %x/%x\n", value, mii_id, regnum);
163 	return value;
164 }
165 
166 /* Reset the MIIM registers, and wait for the bus to free */
167 static int fsl_pq_mdio_reset(struct mii_bus *bus)
168 {
169 	struct fsl_pq_mdio_priv *priv = bus->priv;
170 	struct fsl_pq_mii __iomem *regs = priv->regs;
171 	unsigned int timeout;
172 
173 	mutex_lock(&bus->mdio_lock);
174 
175 	/* Reset the management interface */
176 	iowrite32be(MIIMCFG_RESET, &regs->miimcfg);
177 
178 	/* Setup the MII Mgmt clock speed */
179 	iowrite32be(MIIMCFG_INIT_VALUE, &regs->miimcfg);
180 
181 	/* Wait until the bus is free */
182 	timeout = MII_TIMEOUT;
183 	while ((ioread32be(&regs->miimind) & MIIMIND_BUSY) && timeout) {
184 		cpu_relax();
185 		timeout--;
186 	}
187 
188 	mutex_unlock(&bus->mdio_lock);
189 
190 	if (!timeout) {
191 		dev_err(&bus->dev, "timeout waiting for MII bus\n");
192 		return -EBUSY;
193 	}
194 
195 	return 0;
196 }
197 
198 #if IS_ENABLED(CONFIG_GIANFAR)
199 /*
200  * Return the TBIPA address, starting from the address
201  * of the mapped GFAR MDIO registers (struct gfar)
202  * This is mildly evil, but so is our hardware for doing this.
203  * Also, we have to cast back to struct gfar because of
204  * definition weirdness done in gianfar.h.
205  */
206 static uint32_t __iomem *get_gfar_tbipa_from_mdio(void __iomem *p)
207 {
208 	struct gfar __iomem *enet_regs = p;
209 
210 	return &enet_regs->tbipa;
211 }
212 
213 /*
214  * Return the TBIPA address, starting from the address
215  * of the mapped GFAR MII registers (gfar_mii_regs[] within struct gfar)
216  */
217 static uint32_t __iomem *get_gfar_tbipa_from_mii(void __iomem *p)
218 {
219 	return get_gfar_tbipa_from_mdio(container_of(p, struct gfar, gfar_mii_regs));
220 }
221 
222 /*
223  * Return the TBIPAR address for an eTSEC2 node
224  */
225 static uint32_t __iomem *get_etsec_tbipa(void __iomem *p)
226 {
227 	return p;
228 }
229 #endif
230 
231 #if IS_ENABLED(CONFIG_UCC_GETH)
232 /*
233  * Return the TBIPAR address for a QE MDIO node, starting from the address
234  * of the mapped MII registers (struct fsl_pq_mii)
235  */
236 static uint32_t __iomem *get_ucc_tbipa(void __iomem *p)
237 {
238 	struct fsl_pq_mdio __iomem *mdio = container_of(p, struct fsl_pq_mdio, mii);
239 
240 	return &mdio->utbipar;
241 }
242 
243 /*
244  * Find the UCC node that controls the given MDIO node
245  *
246  * For some reason, the QE MDIO nodes are not children of the UCC devices
247  * that control them.  Therefore, we need to scan all UCC nodes looking for
248  * the one that encompases the given MDIO node.  We do this by comparing
249  * physical addresses.  The 'start' and 'end' addresses of the MDIO node are
250  * passed, and the correct UCC node will cover the entire address range.
251  *
252  * This assumes that there is only one QE MDIO node in the entire device tree.
253  */
254 static void ucc_configure(phys_addr_t start, phys_addr_t end)
255 {
256 	static bool found_mii_master;
257 	struct device_node *np = NULL;
258 
259 	if (found_mii_master)
260 		return;
261 
262 	for_each_compatible_node(np, NULL, "ucc_geth") {
263 		struct resource res;
264 		const uint32_t *iprop;
265 		uint32_t id;
266 		int ret;
267 
268 		ret = of_address_to_resource(np, 0, &res);
269 		if (ret < 0) {
270 			pr_debug("fsl-pq-mdio: no address range in node %pOF\n",
271 				 np);
272 			continue;
273 		}
274 
275 		/* if our mdio regs fall within this UCC regs range */
276 		if ((start < res.start) || (end > res.end))
277 			continue;
278 
279 		iprop = of_get_property(np, "cell-index", NULL);
280 		if (!iprop) {
281 			iprop = of_get_property(np, "device-id", NULL);
282 			if (!iprop) {
283 				pr_debug("fsl-pq-mdio: no UCC ID in node %pOF\n",
284 					 np);
285 				continue;
286 			}
287 		}
288 
289 		id = be32_to_cpup(iprop);
290 
291 		/*
292 		 * cell-index and device-id for QE nodes are
293 		 * numbered from 1, not 0.
294 		 */
295 		if (ucc_set_qe_mux_mii_mng(id - 1) < 0) {
296 			pr_debug("fsl-pq-mdio: invalid UCC ID in node %pOF\n",
297 				 np);
298 			continue;
299 		}
300 
301 		pr_debug("fsl-pq-mdio: setting node UCC%u to MII master\n", id);
302 		found_mii_master = true;
303 	}
304 }
305 
306 #endif
307 
308 static const struct of_device_id fsl_pq_mdio_match[] = {
309 #if IS_ENABLED(CONFIG_GIANFAR)
310 	{
311 		.compatible = "fsl,gianfar-tbi",
312 		.data = &(struct fsl_pq_mdio_data) {
313 			.mii_offset = 0,
314 			.get_tbipa = get_gfar_tbipa_from_mii,
315 		},
316 	},
317 	{
318 		.compatible = "fsl,gianfar-mdio",
319 		.data = &(struct fsl_pq_mdio_data) {
320 			.mii_offset = 0,
321 			.get_tbipa = get_gfar_tbipa_from_mii,
322 		},
323 	},
324 	{
325 		.type = "mdio",
326 		.compatible = "gianfar",
327 		.data = &(struct fsl_pq_mdio_data) {
328 			.mii_offset = offsetof(struct fsl_pq_mdio, mii),
329 			.get_tbipa = get_gfar_tbipa_from_mdio,
330 		},
331 	},
332 	{
333 		.compatible = "fsl,etsec2-tbi",
334 		.data = &(struct fsl_pq_mdio_data) {
335 			.mii_offset = offsetof(struct fsl_pq_mdio, mii),
336 			.get_tbipa = get_etsec_tbipa,
337 		},
338 	},
339 	{
340 		.compatible = "fsl,etsec2-mdio",
341 		.data = &(struct fsl_pq_mdio_data) {
342 			.mii_offset = offsetof(struct fsl_pq_mdio, mii),
343 			.get_tbipa = get_etsec_tbipa,
344 		},
345 	},
346 #endif
347 #if IS_ENABLED(CONFIG_UCC_GETH)
348 	{
349 		.compatible = "fsl,ucc-mdio",
350 		.data = &(struct fsl_pq_mdio_data) {
351 			.mii_offset = 0,
352 			.get_tbipa = get_ucc_tbipa,
353 			.ucc_configure = ucc_configure,
354 		},
355 	},
356 	{
357 		/* Legacy UCC MDIO node */
358 		.type = "mdio",
359 		.compatible = "ucc_geth_phy",
360 		.data = &(struct fsl_pq_mdio_data) {
361 			.mii_offset = 0,
362 			.get_tbipa = get_ucc_tbipa,
363 			.ucc_configure = ucc_configure,
364 		},
365 	},
366 #endif
367 	/* No Kconfig option for Fman support yet */
368 	{
369 		.compatible = "fsl,fman-mdio",
370 		.data = &(struct fsl_pq_mdio_data) {
371 			.mii_offset = 0,
372 			/* Fman TBI operations are handled elsewhere */
373 		},
374 	},
375 
376 	{},
377 };
378 MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
379 
380 static void set_tbipa(const u32 tbipa_val, struct platform_device *pdev,
381 		      uint32_t __iomem * (*get_tbipa)(void __iomem *),
382 		      void __iomem *reg_map, struct resource *reg_res)
383 {
384 	struct device_node *np = pdev->dev.of_node;
385 	uint32_t __iomem *tbipa;
386 	bool tbipa_mapped;
387 
388 	tbipa = of_iomap(np, 1);
389 	if (tbipa) {
390 		tbipa_mapped = true;
391 	} else {
392 		tbipa_mapped = false;
393 		tbipa = (*get_tbipa)(reg_map);
394 
395 		/*
396 		 * Add consistency check to make sure TBI is contained within
397 		 * the mapped range (not because we would get a segfault,
398 		 * rather to catch bugs in computing TBI address). Print error
399 		 * message but continue anyway.
400 		 */
401 		if ((void *)tbipa > reg_map + resource_size(reg_res) - 4)
402 			dev_err(&pdev->dev, "invalid register map (should be at least 0x%04zx to contain TBI address)\n",
403 				((void *)tbipa - reg_map) + 4);
404 	}
405 
406 	iowrite32be(be32_to_cpu(tbipa_val), tbipa);
407 
408 	if (tbipa_mapped)
409 		iounmap(tbipa);
410 }
411 
412 static int fsl_pq_mdio_probe(struct platform_device *pdev)
413 {
414 	const struct of_device_id *id =
415 		of_match_device(fsl_pq_mdio_match, &pdev->dev);
416 	const struct fsl_pq_mdio_data *data;
417 	struct device_node *np = pdev->dev.of_node;
418 	struct resource res;
419 	struct device_node *tbi;
420 	struct fsl_pq_mdio_priv *priv;
421 	struct mii_bus *new_bus;
422 	int err;
423 
424 	if (!id) {
425 		dev_err(&pdev->dev, "Failed to match device\n");
426 		return -ENODEV;
427 	}
428 
429 	data = id->data;
430 
431 	dev_dbg(&pdev->dev, "found %s compatible node\n", id->compatible);
432 
433 	new_bus = mdiobus_alloc_size(sizeof(*priv));
434 	if (!new_bus)
435 		return -ENOMEM;
436 
437 	priv = new_bus->priv;
438 	new_bus->name = "Freescale PowerQUICC MII Bus",
439 	new_bus->read = &fsl_pq_mdio_read;
440 	new_bus->write = &fsl_pq_mdio_write;
441 	new_bus->reset = &fsl_pq_mdio_reset;
442 
443 	err = of_address_to_resource(np, 0, &res);
444 	if (err < 0) {
445 		dev_err(&pdev->dev, "could not obtain address information\n");
446 		goto error;
447 	}
448 
449 	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%pOFn@%llx", np,
450 		 (unsigned long long)res.start);
451 
452 	priv->map = of_iomap(np, 0);
453 	if (!priv->map) {
454 		err = -ENOMEM;
455 		goto error;
456 	}
457 
458 	/*
459 	 * Some device tree nodes represent only the MII registers, and
460 	 * others represent the MAC and MII registers.  The 'mii_offset' field
461 	 * contains the offset of the MII registers inside the mapped register
462 	 * space.
463 	 */
464 	if (data->mii_offset > resource_size(&res)) {
465 		dev_err(&pdev->dev, "invalid register map\n");
466 		err = -EINVAL;
467 		goto error;
468 	}
469 	priv->regs = priv->map + data->mii_offset;
470 
471 	new_bus->parent = &pdev->dev;
472 	platform_set_drvdata(pdev, new_bus);
473 
474 	if (data->get_tbipa) {
475 		for_each_child_of_node(np, tbi) {
476 			if (of_node_is_type(tbi, "tbi-phy")) {
477 				dev_dbg(&pdev->dev, "found TBI PHY node %pOFP\n",
478 					tbi);
479 				break;
480 			}
481 		}
482 
483 		if (tbi) {
484 			const u32 *prop = of_get_property(tbi, "reg", NULL);
485 			if (!prop) {
486 				dev_err(&pdev->dev,
487 					"missing 'reg' property in node %pOF\n",
488 					tbi);
489 				err = -EBUSY;
490 				goto error;
491 			}
492 			set_tbipa(*prop, pdev,
493 				  data->get_tbipa, priv->map, &res);
494 		}
495 	}
496 
497 	if (data->ucc_configure)
498 		data->ucc_configure(res.start, res.end);
499 
500 	err = of_mdiobus_register(new_bus, np);
501 	if (err) {
502 		dev_err(&pdev->dev, "cannot register %s as MDIO bus\n",
503 			new_bus->name);
504 		goto error;
505 	}
506 
507 	return 0;
508 
509 error:
510 	if (priv->map)
511 		iounmap(priv->map);
512 
513 	kfree(new_bus);
514 
515 	return err;
516 }
517 
518 
519 static int fsl_pq_mdio_remove(struct platform_device *pdev)
520 {
521 	struct device *device = &pdev->dev;
522 	struct mii_bus *bus = dev_get_drvdata(device);
523 	struct fsl_pq_mdio_priv *priv = bus->priv;
524 
525 	mdiobus_unregister(bus);
526 
527 	iounmap(priv->map);
528 	mdiobus_free(bus);
529 
530 	return 0;
531 }
532 
533 static struct platform_driver fsl_pq_mdio_driver = {
534 	.driver = {
535 		.name = "fsl-pq_mdio",
536 		.of_match_table = fsl_pq_mdio_match,
537 	},
538 	.probe = fsl_pq_mdio_probe,
539 	.remove = fsl_pq_mdio_remove,
540 };
541 
542 module_platform_driver(fsl_pq_mdio_driver);
543 
544 MODULE_LICENSE("GPL");
545