1 /* 2 * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation 3 * Provides Bus interface for MIIM regs 4 * 5 * Author: Andy Fleming <afleming@freescale.com> 6 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 7 * 8 * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc. 9 * 10 * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips) 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms of the GNU General Public License as published by the 14 * Free Software Foundation; either version 2 of the License, or (at your 15 * option) any later version. 16 * 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/string.h> 21 #include <linux/errno.h> 22 #include <linux/slab.h> 23 #include <linux/delay.h> 24 #include <linux/module.h> 25 #include <linux/mii.h> 26 #include <linux/of_address.h> 27 #include <linux/of_mdio.h> 28 #include <linux/of_device.h> 29 30 #include <asm/io.h> 31 #if IS_ENABLED(CONFIG_UCC_GETH) 32 #include <asm/ucc.h> /* for ucc_set_qe_mux_mii_mng() */ 33 #endif 34 35 #include "gianfar.h" 36 37 #define MIIMIND_BUSY 0x00000001 38 #define MIIMIND_NOTVALID 0x00000004 39 #define MIIMCFG_INIT_VALUE 0x00000007 40 #define MIIMCFG_RESET 0x80000000 41 42 #define MII_READ_COMMAND 0x00000001 43 44 struct fsl_pq_mii { 45 u32 miimcfg; /* MII management configuration reg */ 46 u32 miimcom; /* MII management command reg */ 47 u32 miimadd; /* MII management address reg */ 48 u32 miimcon; /* MII management control reg */ 49 u32 miimstat; /* MII management status reg */ 50 u32 miimind; /* MII management indication reg */ 51 }; 52 53 struct fsl_pq_mdio { 54 u8 res1[16]; 55 u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/ 56 u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/ 57 u8 res2[4]; 58 u32 emapm; /* MDIO Event mapping register (for etsec2)*/ 59 u8 res3[1280]; 60 struct fsl_pq_mii mii; 61 u8 res4[28]; 62 u32 utbipar; /* TBI phy address reg (only on UCC) */ 63 u8 res5[2728]; 64 } __packed; 65 66 /* Number of microseconds to wait for an MII register to respond */ 67 #define MII_TIMEOUT 1000 68 69 struct fsl_pq_mdio_priv { 70 void __iomem *map; 71 struct fsl_pq_mii __iomem *regs; 72 int irqs[PHY_MAX_ADDR]; 73 }; 74 75 /* 76 * Per-device-type data. Each type of device tree node that we support gets 77 * one of these. 78 * 79 * @mii_offset: the offset of the MII registers within the memory map of the 80 * node. Some nodes define only the MII registers, and some define the whole 81 * MAC (which includes the MII registers). 82 * 83 * @get_tbipa: determines the address of the TBIPA register 84 * 85 * @ucc_configure: a special function for extra QE configuration 86 */ 87 struct fsl_pq_mdio_data { 88 unsigned int mii_offset; /* offset of the MII registers */ 89 uint32_t __iomem * (*get_tbipa)(void __iomem *p); 90 void (*ucc_configure)(phys_addr_t start, phys_addr_t end); 91 }; 92 93 /* 94 * Write value to the PHY at mii_id at register regnum, on the bus attached 95 * to the local interface, which may be different from the generic mdio bus 96 * (tied to a single interface), waiting until the write is done before 97 * returning. This is helpful in programming interfaces like the TBI which 98 * control interfaces like onchip SERDES and are always tied to the local 99 * mdio pins, which may not be the same as system mdio bus, used for 100 * controlling the external PHYs, for example. 101 */ 102 static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 103 u16 value) 104 { 105 struct fsl_pq_mdio_priv *priv = bus->priv; 106 struct fsl_pq_mii __iomem *regs = priv->regs; 107 u32 status; 108 109 /* Set the PHY address and the register address we want to write */ 110 out_be32(®s->miimadd, (mii_id << 8) | regnum); 111 112 /* Write out the value we want */ 113 out_be32(®s->miimcon, value); 114 115 /* Wait for the transaction to finish */ 116 status = spin_event_timeout(!(in_be32(®s->miimind) & MIIMIND_BUSY), 117 MII_TIMEOUT, 0); 118 119 return status ? 0 : -ETIMEDOUT; 120 } 121 122 /* 123 * Read the bus for PHY at addr mii_id, register regnum, and return the value. 124 * Clears miimcom first. 125 * 126 * All PHY operation done on the bus attached to the local interface, which 127 * may be different from the generic mdio bus. This is helpful in programming 128 * interfaces like the TBI which, in turn, control interfaces like on-chip 129 * SERDES and are always tied to the local mdio pins, which may not be the 130 * same as system mdio bus, used for controlling the external PHYs, for eg. 131 */ 132 static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 133 { 134 struct fsl_pq_mdio_priv *priv = bus->priv; 135 struct fsl_pq_mii __iomem *regs = priv->regs; 136 u32 status; 137 u16 value; 138 139 /* Set the PHY address and the register address we want to read */ 140 out_be32(®s->miimadd, (mii_id << 8) | regnum); 141 142 /* Clear miimcom, and then initiate a read */ 143 out_be32(®s->miimcom, 0); 144 out_be32(®s->miimcom, MII_READ_COMMAND); 145 146 /* Wait for the transaction to finish, normally less than 100us */ 147 status = spin_event_timeout(!(in_be32(®s->miimind) & 148 (MIIMIND_NOTVALID | MIIMIND_BUSY)), 149 MII_TIMEOUT, 0); 150 if (!status) 151 return -ETIMEDOUT; 152 153 /* Grab the value of the register from miimstat */ 154 value = in_be32(®s->miimstat); 155 156 dev_dbg(&bus->dev, "read %04x from address %x/%x\n", value, mii_id, regnum); 157 return value; 158 } 159 160 /* Reset the MIIM registers, and wait for the bus to free */ 161 static int fsl_pq_mdio_reset(struct mii_bus *bus) 162 { 163 struct fsl_pq_mdio_priv *priv = bus->priv; 164 struct fsl_pq_mii __iomem *regs = priv->regs; 165 u32 status; 166 167 mutex_lock(&bus->mdio_lock); 168 169 /* Reset the management interface */ 170 out_be32(®s->miimcfg, MIIMCFG_RESET); 171 172 /* Setup the MII Mgmt clock speed */ 173 out_be32(®s->miimcfg, MIIMCFG_INIT_VALUE); 174 175 /* Wait until the bus is free */ 176 status = spin_event_timeout(!(in_be32(®s->miimind) & MIIMIND_BUSY), 177 MII_TIMEOUT, 0); 178 179 mutex_unlock(&bus->mdio_lock); 180 181 if (!status) { 182 dev_err(&bus->dev, "timeout waiting for MII bus\n"); 183 return -EBUSY; 184 } 185 186 return 0; 187 } 188 189 #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE) 190 /* 191 * This is mildly evil, but so is our hardware for doing this. 192 * Also, we have to cast back to struct gfar because of 193 * definition weirdness done in gianfar.h. 194 */ 195 static uint32_t __iomem *get_gfar_tbipa(void __iomem *p) 196 { 197 struct gfar __iomem *enet_regs = p; 198 199 return &enet_regs->tbipa; 200 } 201 202 /* 203 * Return the TBIPAR address for an eTSEC2 node 204 */ 205 static uint32_t __iomem *get_etsec_tbipa(void __iomem *p) 206 { 207 return p; 208 } 209 #endif 210 211 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE) 212 /* 213 * Return the TBIPAR address for a QE MDIO node 214 */ 215 static uint32_t __iomem *get_ucc_tbipa(void __iomem *p) 216 { 217 struct fsl_pq_mdio __iomem *mdio = p; 218 219 return &mdio->utbipar; 220 } 221 222 /* 223 * Find the UCC node that controls the given MDIO node 224 * 225 * For some reason, the QE MDIO nodes are not children of the UCC devices 226 * that control them. Therefore, we need to scan all UCC nodes looking for 227 * the one that encompases the given MDIO node. We do this by comparing 228 * physical addresses. The 'start' and 'end' addresses of the MDIO node are 229 * passed, and the correct UCC node will cover the entire address range. 230 * 231 * This assumes that there is only one QE MDIO node in the entire device tree. 232 */ 233 static void ucc_configure(phys_addr_t start, phys_addr_t end) 234 { 235 static bool found_mii_master; 236 struct device_node *np = NULL; 237 238 if (found_mii_master) 239 return; 240 241 for_each_compatible_node(np, NULL, "ucc_geth") { 242 struct resource res; 243 const uint32_t *iprop; 244 uint32_t id; 245 int ret; 246 247 ret = of_address_to_resource(np, 0, &res); 248 if (ret < 0) { 249 pr_debug("fsl-pq-mdio: no address range in node %s\n", 250 np->full_name); 251 continue; 252 } 253 254 /* if our mdio regs fall within this UCC regs range */ 255 if ((start < res.start) || (end > res.end)) 256 continue; 257 258 iprop = of_get_property(np, "cell-index", NULL); 259 if (!iprop) { 260 iprop = of_get_property(np, "device-id", NULL); 261 if (!iprop) { 262 pr_debug("fsl-pq-mdio: no UCC ID in node %s\n", 263 np->full_name); 264 continue; 265 } 266 } 267 268 id = be32_to_cpup(iprop); 269 270 /* 271 * cell-index and device-id for QE nodes are 272 * numbered from 1, not 0. 273 */ 274 if (ucc_set_qe_mux_mii_mng(id - 1) < 0) { 275 pr_debug("fsl-pq-mdio: invalid UCC ID in node %s\n", 276 np->full_name); 277 continue; 278 } 279 280 pr_debug("fsl-pq-mdio: setting node UCC%u to MII master\n", id); 281 found_mii_master = true; 282 } 283 } 284 285 #endif 286 287 static struct of_device_id fsl_pq_mdio_match[] = { 288 #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE) 289 { 290 .compatible = "fsl,gianfar-tbi", 291 .data = &(struct fsl_pq_mdio_data) { 292 .mii_offset = 0, 293 .get_tbipa = get_gfar_tbipa, 294 }, 295 }, 296 { 297 .compatible = "fsl,gianfar-mdio", 298 .data = &(struct fsl_pq_mdio_data) { 299 .mii_offset = 0, 300 .get_tbipa = get_gfar_tbipa, 301 }, 302 }, 303 { 304 .type = "mdio", 305 .compatible = "gianfar", 306 .data = &(struct fsl_pq_mdio_data) { 307 .mii_offset = offsetof(struct fsl_pq_mdio, mii), 308 .get_tbipa = get_gfar_tbipa, 309 }, 310 }, 311 { 312 .compatible = "fsl,etsec2-tbi", 313 .data = &(struct fsl_pq_mdio_data) { 314 .mii_offset = offsetof(struct fsl_pq_mdio, mii), 315 .get_tbipa = get_etsec_tbipa, 316 }, 317 }, 318 { 319 .compatible = "fsl,etsec2-mdio", 320 .data = &(struct fsl_pq_mdio_data) { 321 .mii_offset = offsetof(struct fsl_pq_mdio, mii), 322 .get_tbipa = get_etsec_tbipa, 323 }, 324 }, 325 #endif 326 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE) 327 { 328 .compatible = "fsl,ucc-mdio", 329 .data = &(struct fsl_pq_mdio_data) { 330 .mii_offset = 0, 331 .get_tbipa = get_ucc_tbipa, 332 .ucc_configure = ucc_configure, 333 }, 334 }, 335 { 336 /* Legacy UCC MDIO node */ 337 .type = "mdio", 338 .compatible = "ucc_geth_phy", 339 .data = &(struct fsl_pq_mdio_data) { 340 .mii_offset = 0, 341 .get_tbipa = get_ucc_tbipa, 342 .ucc_configure = ucc_configure, 343 }, 344 }, 345 #endif 346 /* No Kconfig option for Fman support yet */ 347 { 348 .compatible = "fsl,fman-mdio", 349 .data = &(struct fsl_pq_mdio_data) { 350 .mii_offset = 0, 351 /* Fman TBI operations are handled elsewhere */ 352 }, 353 }, 354 355 {}, 356 }; 357 MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match); 358 359 static int fsl_pq_mdio_probe(struct platform_device *pdev) 360 { 361 const struct of_device_id *id = 362 of_match_device(fsl_pq_mdio_match, &pdev->dev); 363 const struct fsl_pq_mdio_data *data = id->data; 364 struct device_node *np = pdev->dev.of_node; 365 struct resource res; 366 struct device_node *tbi; 367 struct fsl_pq_mdio_priv *priv; 368 struct mii_bus *new_bus; 369 int err; 370 371 dev_dbg(&pdev->dev, "found %s compatible node\n", id->compatible); 372 373 new_bus = mdiobus_alloc_size(sizeof(*priv)); 374 if (!new_bus) 375 return -ENOMEM; 376 377 priv = new_bus->priv; 378 new_bus->name = "Freescale PowerQUICC MII Bus", 379 new_bus->read = &fsl_pq_mdio_read; 380 new_bus->write = &fsl_pq_mdio_write; 381 new_bus->reset = &fsl_pq_mdio_reset; 382 new_bus->irq = priv->irqs; 383 384 err = of_address_to_resource(np, 0, &res); 385 if (err < 0) { 386 dev_err(&pdev->dev, "could not obtain address information\n"); 387 goto error; 388 } 389 390 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s@%llx", np->name, 391 (unsigned long long)res.start); 392 393 priv->map = of_iomap(np, 0); 394 if (!priv->map) { 395 err = -ENOMEM; 396 goto error; 397 } 398 399 /* 400 * Some device tree nodes represent only the MII registers, and 401 * others represent the MAC and MII registers. The 'mii_offset' field 402 * contains the offset of the MII registers inside the mapped register 403 * space. 404 */ 405 if (data->mii_offset > resource_size(&res)) { 406 dev_err(&pdev->dev, "invalid register map\n"); 407 err = -EINVAL; 408 goto error; 409 } 410 priv->regs = priv->map + data->mii_offset; 411 412 new_bus->parent = &pdev->dev; 413 platform_set_drvdata(pdev, new_bus); 414 415 if (data->get_tbipa) { 416 for_each_child_of_node(np, tbi) { 417 if (strcmp(tbi->type, "tbi-phy") == 0) { 418 dev_dbg(&pdev->dev, "found TBI PHY node %s\n", 419 strrchr(tbi->full_name, '/') + 1); 420 break; 421 } 422 } 423 424 if (tbi) { 425 const u32 *prop = of_get_property(tbi, "reg", NULL); 426 uint32_t __iomem *tbipa; 427 428 if (!prop) { 429 dev_err(&pdev->dev, 430 "missing 'reg' property in node %s\n", 431 tbi->full_name); 432 err = -EBUSY; 433 goto error; 434 } 435 436 tbipa = data->get_tbipa(priv->map); 437 438 out_be32(tbipa, be32_to_cpup(prop)); 439 } 440 } 441 442 if (data->ucc_configure) 443 data->ucc_configure(res.start, res.end); 444 445 err = of_mdiobus_register(new_bus, np); 446 if (err) { 447 dev_err(&pdev->dev, "cannot register %s as MDIO bus\n", 448 new_bus->name); 449 goto error; 450 } 451 452 return 0; 453 454 error: 455 if (priv->map) 456 iounmap(priv->map); 457 458 kfree(new_bus); 459 460 return err; 461 } 462 463 464 static int fsl_pq_mdio_remove(struct platform_device *pdev) 465 { 466 struct device *device = &pdev->dev; 467 struct mii_bus *bus = dev_get_drvdata(device); 468 struct fsl_pq_mdio_priv *priv = bus->priv; 469 470 mdiobus_unregister(bus); 471 472 iounmap(priv->map); 473 mdiobus_free(bus); 474 475 return 0; 476 } 477 478 static struct platform_driver fsl_pq_mdio_driver = { 479 .driver = { 480 .name = "fsl-pq_mdio", 481 .owner = THIS_MODULE, 482 .of_match_table = fsl_pq_mdio_match, 483 }, 484 .probe = fsl_pq_mdio_probe, 485 .remove = fsl_pq_mdio_remove, 486 }; 487 488 module_platform_driver(fsl_pq_mdio_driver); 489 490 MODULE_LICENSE("GPL"); 491