12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2ec21e2ecSJeff Kirsher /* 3ec21e2ecSJeff Kirsher * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation 4ec21e2ecSJeff Kirsher * Provides Bus interface for MIIM regs 5ec21e2ecSJeff Kirsher * 6ec21e2ecSJeff Kirsher * Author: Andy Fleming <afleming@freescale.com> 7ec21e2ecSJeff Kirsher * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 8ec21e2ecSJeff Kirsher * 9ec21e2ecSJeff Kirsher * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc. 10ec21e2ecSJeff Kirsher * 11ec21e2ecSJeff Kirsher * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips) 12ec21e2ecSJeff Kirsher */ 13ec21e2ecSJeff Kirsher 14ec21e2ecSJeff Kirsher #include <linux/kernel.h> 15ec21e2ecSJeff Kirsher #include <linux/string.h> 16ec21e2ecSJeff Kirsher #include <linux/errno.h> 17ec21e2ecSJeff Kirsher #include <linux/slab.h> 18ec21e2ecSJeff Kirsher #include <linux/delay.h> 19ec21e2ecSJeff Kirsher #include <linux/module.h> 20ec21e2ecSJeff Kirsher #include <linux/mii.h> 21ec21e2ecSJeff Kirsher #include <linux/of_address.h> 22ec21e2ecSJeff Kirsher #include <linux/of_mdio.h> 23afae5ad7STimur Tabi #include <linux/of_device.h> 24ec21e2ecSJeff Kirsher 25ec21e2ecSJeff Kirsher #include <asm/io.h> 269a4cbd53SClaudiu Manoil #if IS_ENABLED(CONFIG_UCC_GETH) 277aa1aa6eSZhao Qiang #include <soc/fsl/qe/ucc.h> 289a4cbd53SClaudiu Manoil #endif 29ec21e2ecSJeff Kirsher 30ec21e2ecSJeff Kirsher #include "gianfar.h" 3119bcd6c6STimur Tabi 3219bcd6c6STimur Tabi #define MIIMIND_BUSY 0x00000001 3319bcd6c6STimur Tabi #define MIIMIND_NOTVALID 0x00000004 3419bcd6c6STimur Tabi #define MIIMCFG_INIT_VALUE 0x00000007 3519bcd6c6STimur Tabi #define MIIMCFG_RESET 0x80000000 3619bcd6c6STimur Tabi 3719bcd6c6STimur Tabi #define MII_READ_COMMAND 0x00000001 3819bcd6c6STimur Tabi 39afae5ad7STimur Tabi struct fsl_pq_mii { 40afae5ad7STimur Tabi u32 miimcfg; /* MII management configuration reg */ 41afae5ad7STimur Tabi u32 miimcom; /* MII management command reg */ 42afae5ad7STimur Tabi u32 miimadd; /* MII management address reg */ 43afae5ad7STimur Tabi u32 miimcon; /* MII management control reg */ 44afae5ad7STimur Tabi u32 miimstat; /* MII management status reg */ 45afae5ad7STimur Tabi u32 miimind; /* MII management indication reg */ 46afae5ad7STimur Tabi }; 47afae5ad7STimur Tabi 4819bcd6c6STimur Tabi struct fsl_pq_mdio { 4919bcd6c6STimur Tabi u8 res1[16]; 5019bcd6c6STimur Tabi u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/ 5119bcd6c6STimur Tabi u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/ 5219bcd6c6STimur Tabi u8 res2[4]; 5319bcd6c6STimur Tabi u32 emapm; /* MDIO Event mapping register (for etsec2)*/ 5419bcd6c6STimur Tabi u8 res3[1280]; 55afae5ad7STimur Tabi struct fsl_pq_mii mii; 5619bcd6c6STimur Tabi u8 res4[28]; 5719bcd6c6STimur Tabi u32 utbipar; /* TBI phy address reg (only on UCC) */ 5819bcd6c6STimur Tabi u8 res5[2728]; 5919bcd6c6STimur Tabi } __packed; 60ec21e2ecSJeff Kirsher 6159399c59STimur Tabi /* Number of microseconds to wait for an MII register to respond */ 6259399c59STimur Tabi #define MII_TIMEOUT 1000 6359399c59STimur Tabi 64ec21e2ecSJeff Kirsher struct fsl_pq_mdio_priv { 65ec21e2ecSJeff Kirsher void __iomem *map; 66afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs; 67afae5ad7STimur Tabi }; 68afae5ad7STimur Tabi 69afae5ad7STimur Tabi /* 70afae5ad7STimur Tabi * Per-device-type data. Each type of device tree node that we support gets 71afae5ad7STimur Tabi * one of these. 72afae5ad7STimur Tabi * 73afae5ad7STimur Tabi * @mii_offset: the offset of the MII registers within the memory map of the 74afae5ad7STimur Tabi * node. Some nodes define only the MII registers, and some define the whole 75afae5ad7STimur Tabi * MAC (which includes the MII registers). 76afae5ad7STimur Tabi * 77afae5ad7STimur Tabi * @get_tbipa: determines the address of the TBIPA register 78afae5ad7STimur Tabi * 79afae5ad7STimur Tabi * @ucc_configure: a special function for extra QE configuration 80afae5ad7STimur Tabi */ 81afae5ad7STimur Tabi struct fsl_pq_mdio_data { 82afae5ad7STimur Tabi unsigned int mii_offset; /* offset of the MII registers */ 83afae5ad7STimur Tabi uint32_t __iomem * (*get_tbipa)(void __iomem *p); 84afae5ad7STimur Tabi void (*ucc_configure)(phys_addr_t start, phys_addr_t end); 85ec21e2ecSJeff Kirsher }; 86ec21e2ecSJeff Kirsher 87ec21e2ecSJeff Kirsher /* 8869cfb419STimur Tabi * Write value to the PHY at mii_id at register regnum, on the bus attached 8969cfb419STimur Tabi * to the local interface, which may be different from the generic mdio bus 9069cfb419STimur Tabi * (tied to a single interface), waiting until the write is done before 9169cfb419STimur Tabi * returning. This is helpful in programming interfaces like the TBI which 9269cfb419STimur Tabi * control interfaces like onchip SERDES and are always tied to the local 9369cfb419STimur Tabi * mdio pins, which may not be the same as system mdio bus, used for 94ec21e2ecSJeff Kirsher * controlling the external PHYs, for example. 95ec21e2ecSJeff Kirsher */ 9669cfb419STimur Tabi static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 9769cfb419STimur Tabi u16 value) 98ec21e2ecSJeff Kirsher { 9969cfb419STimur Tabi struct fsl_pq_mdio_priv *priv = bus->priv; 100afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs = priv->regs; 101e4b081f5SClaudiu Manoil unsigned int timeout; 10259399c59STimur Tabi 103ec21e2ecSJeff Kirsher /* Set the PHY address and the register address we want to write */ 104f5bbd262SClaudiu Manoil iowrite32be((mii_id << 8) | regnum, ®s->miimadd); 105ec21e2ecSJeff Kirsher 106ec21e2ecSJeff Kirsher /* Write out the value we want */ 107f5bbd262SClaudiu Manoil iowrite32be(value, ®s->miimcon); 108ec21e2ecSJeff Kirsher 109ec21e2ecSJeff Kirsher /* Wait for the transaction to finish */ 110e4b081f5SClaudiu Manoil timeout = MII_TIMEOUT; 111e4b081f5SClaudiu Manoil while ((ioread32be(®s->miimind) & MIIMIND_BUSY) && timeout) { 112e4b081f5SClaudiu Manoil cpu_relax(); 113e4b081f5SClaudiu Manoil timeout--; 114e4b081f5SClaudiu Manoil } 115ec21e2ecSJeff Kirsher 116e4b081f5SClaudiu Manoil return timeout ? 0 : -ETIMEDOUT; 117ec21e2ecSJeff Kirsher } 118ec21e2ecSJeff Kirsher 119ec21e2ecSJeff Kirsher /* 12069cfb419STimur Tabi * Read the bus for PHY at addr mii_id, register regnum, and return the value. 12169cfb419STimur Tabi * Clears miimcom first. 12269cfb419STimur Tabi * 12369cfb419STimur Tabi * All PHY operation done on the bus attached to the local interface, which 12469cfb419STimur Tabi * may be different from the generic mdio bus. This is helpful in programming 12569cfb419STimur Tabi * interfaces like the TBI which, in turn, control interfaces like on-chip 12669cfb419STimur Tabi * SERDES and are always tied to the local mdio pins, which may not be the 127ec21e2ecSJeff Kirsher * same as system mdio bus, used for controlling the external PHYs, for eg. 128ec21e2ecSJeff Kirsher */ 12969cfb419STimur Tabi static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 130ec21e2ecSJeff Kirsher { 13169cfb419STimur Tabi struct fsl_pq_mdio_priv *priv = bus->priv; 132afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs = priv->regs; 133e4b081f5SClaudiu Manoil unsigned int timeout; 13469cfb419STimur Tabi u16 value; 135ec21e2ecSJeff Kirsher 136ec21e2ecSJeff Kirsher /* Set the PHY address and the register address we want to read */ 137f5bbd262SClaudiu Manoil iowrite32be((mii_id << 8) | regnum, ®s->miimadd); 138ec21e2ecSJeff Kirsher 139ec21e2ecSJeff Kirsher /* Clear miimcom, and then initiate a read */ 140f5bbd262SClaudiu Manoil iowrite32be(0, ®s->miimcom); 141f5bbd262SClaudiu Manoil iowrite32be(MII_READ_COMMAND, ®s->miimcom); 142ec21e2ecSJeff Kirsher 14359399c59STimur Tabi /* Wait for the transaction to finish, normally less than 100us */ 144e4b081f5SClaudiu Manoil timeout = MII_TIMEOUT; 145e4b081f5SClaudiu Manoil while ((ioread32be(®s->miimind) & 146e4b081f5SClaudiu Manoil (MIIMIND_NOTVALID | MIIMIND_BUSY)) && timeout) { 147e4b081f5SClaudiu Manoil cpu_relax(); 148e4b081f5SClaudiu Manoil timeout--; 149e4b081f5SClaudiu Manoil } 150e4b081f5SClaudiu Manoil 151e4b081f5SClaudiu Manoil if (!timeout) 15259399c59STimur Tabi return -ETIMEDOUT; 153ec21e2ecSJeff Kirsher 154ec21e2ecSJeff Kirsher /* Grab the value of the register from miimstat */ 155f5bbd262SClaudiu Manoil value = ioread32be(®s->miimstat); 156ec21e2ecSJeff Kirsher 157afae5ad7STimur Tabi dev_dbg(&bus->dev, "read %04x from address %x/%x\n", value, mii_id, regnum); 158ec21e2ecSJeff Kirsher return value; 159ec21e2ecSJeff Kirsher } 160ec21e2ecSJeff Kirsher 161ec21e2ecSJeff Kirsher /* Reset the MIIM registers, and wait for the bus to free */ 162ec21e2ecSJeff Kirsher static int fsl_pq_mdio_reset(struct mii_bus *bus) 163ec21e2ecSJeff Kirsher { 16469cfb419STimur Tabi struct fsl_pq_mdio_priv *priv = bus->priv; 165afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs = priv->regs; 166e4b081f5SClaudiu Manoil unsigned int timeout; 167ec21e2ecSJeff Kirsher 168ec21e2ecSJeff Kirsher mutex_lock(&bus->mdio_lock); 169ec21e2ecSJeff Kirsher 170ec21e2ecSJeff Kirsher /* Reset the management interface */ 171f5bbd262SClaudiu Manoil iowrite32be(MIIMCFG_RESET, ®s->miimcfg); 172ec21e2ecSJeff Kirsher 173ec21e2ecSJeff Kirsher /* Setup the MII Mgmt clock speed */ 174f5bbd262SClaudiu Manoil iowrite32be(MIIMCFG_INIT_VALUE, ®s->miimcfg); 175ec21e2ecSJeff Kirsher 176ec21e2ecSJeff Kirsher /* Wait until the bus is free */ 177e4b081f5SClaudiu Manoil timeout = MII_TIMEOUT; 178e4b081f5SClaudiu Manoil while ((ioread32be(®s->miimind) & MIIMIND_BUSY) && timeout) { 179e4b081f5SClaudiu Manoil cpu_relax(); 180e4b081f5SClaudiu Manoil timeout--; 181e4b081f5SClaudiu Manoil } 182ec21e2ecSJeff Kirsher 183ec21e2ecSJeff Kirsher mutex_unlock(&bus->mdio_lock); 184ec21e2ecSJeff Kirsher 185e4b081f5SClaudiu Manoil if (!timeout) { 1865078ac79STimur Tabi dev_err(&bus->dev, "timeout waiting for MII bus\n"); 187ec21e2ecSJeff Kirsher return -EBUSY; 188ec21e2ecSJeff Kirsher } 189ec21e2ecSJeff Kirsher 190ec21e2ecSJeff Kirsher return 0; 191ec21e2ecSJeff Kirsher } 192ec21e2ecSJeff Kirsher 193504e76e5SJavier Martinez Canillas #if IS_ENABLED(CONFIG_GIANFAR) 194ec21e2ecSJeff Kirsher /* 1953bb35ac4SGerlando Falauto * Return the TBIPA address, starting from the address 1963bb35ac4SGerlando Falauto * of the mapped GFAR MDIO registers (struct gfar) 197ec21e2ecSJeff Kirsher * This is mildly evil, but so is our hardware for doing this. 198ec21e2ecSJeff Kirsher * Also, we have to cast back to struct gfar because of 199ec21e2ecSJeff Kirsher * definition weirdness done in gianfar.h. 200ec21e2ecSJeff Kirsher */ 2013bb35ac4SGerlando Falauto static uint32_t __iomem *get_gfar_tbipa_from_mdio(void __iomem *p) 202afae5ad7STimur Tabi { 203afae5ad7STimur Tabi struct gfar __iomem *enet_regs = p; 204afae5ad7STimur Tabi 205ec21e2ecSJeff Kirsher return &enet_regs->tbipa; 206afae5ad7STimur Tabi } 207afae5ad7STimur Tabi 208afae5ad7STimur Tabi /* 2093bb35ac4SGerlando Falauto * Return the TBIPA address, starting from the address 2103bb35ac4SGerlando Falauto * of the mapped GFAR MII registers (gfar_mii_regs[] within struct gfar) 2113bb35ac4SGerlando Falauto */ 2123bb35ac4SGerlando Falauto static uint32_t __iomem *get_gfar_tbipa_from_mii(void __iomem *p) 2133bb35ac4SGerlando Falauto { 2143bb35ac4SGerlando Falauto return get_gfar_tbipa_from_mdio(container_of(p, struct gfar, gfar_mii_regs)); 2153bb35ac4SGerlando Falauto } 2163bb35ac4SGerlando Falauto 2173bb35ac4SGerlando Falauto /* 218afae5ad7STimur Tabi * Return the TBIPAR address for an eTSEC2 node 219afae5ad7STimur Tabi */ 220afae5ad7STimur Tabi static uint32_t __iomem *get_etsec_tbipa(void __iomem *p) 221afae5ad7STimur Tabi { 222afae5ad7STimur Tabi return p; 223ec21e2ecSJeff Kirsher } 224ec21e2ecSJeff Kirsher #endif 225afae5ad7STimur Tabi 226504e76e5SJavier Martinez Canillas #if IS_ENABLED(CONFIG_UCC_GETH) 227afae5ad7STimur Tabi /* 2283bb35ac4SGerlando Falauto * Return the TBIPAR address for a QE MDIO node, starting from the address 2293bb35ac4SGerlando Falauto * of the mapped MII registers (struct fsl_pq_mii) 230afae5ad7STimur Tabi */ 231afae5ad7STimur Tabi static uint32_t __iomem *get_ucc_tbipa(void __iomem *p) 232afae5ad7STimur Tabi { 2333bb35ac4SGerlando Falauto struct fsl_pq_mdio __iomem *mdio = container_of(p, struct fsl_pq_mdio, mii); 234afae5ad7STimur Tabi 235afae5ad7STimur Tabi return &mdio->utbipar; 236952c5ca1SAndy Fleming } 237ec21e2ecSJeff Kirsher 238afae5ad7STimur Tabi /* 239afae5ad7STimur Tabi * Find the UCC node that controls the given MDIO node 240afae5ad7STimur Tabi * 241afae5ad7STimur Tabi * For some reason, the QE MDIO nodes are not children of the UCC devices 242afae5ad7STimur Tabi * that control them. Therefore, we need to scan all UCC nodes looking for 243afae5ad7STimur Tabi * the one that encompases the given MDIO node. We do this by comparing 244afae5ad7STimur Tabi * physical addresses. The 'start' and 'end' addresses of the MDIO node are 245afae5ad7STimur Tabi * passed, and the correct UCC node will cover the entire address range. 246afae5ad7STimur Tabi * 247afae5ad7STimur Tabi * This assumes that there is only one QE MDIO node in the entire device tree. 248afae5ad7STimur Tabi */ 249afae5ad7STimur Tabi static void ucc_configure(phys_addr_t start, phys_addr_t end) 250ec21e2ecSJeff Kirsher { 251afae5ad7STimur Tabi static bool found_mii_master; 252ec21e2ecSJeff Kirsher struct device_node *np = NULL; 253afae5ad7STimur Tabi 254afae5ad7STimur Tabi if (found_mii_master) 255afae5ad7STimur Tabi return; 256ec21e2ecSJeff Kirsher 257ec21e2ecSJeff Kirsher for_each_compatible_node(np, NULL, "ucc_geth") { 258afae5ad7STimur Tabi struct resource res; 259afae5ad7STimur Tabi const uint32_t *iprop; 260afae5ad7STimur Tabi uint32_t id; 261afae5ad7STimur Tabi int ret; 262ec21e2ecSJeff Kirsher 263afae5ad7STimur Tabi ret = of_address_to_resource(np, 0, &res); 264afae5ad7STimur Tabi if (ret < 0) { 265f7ce9103SRob Herring pr_debug("fsl-pq-mdio: no address range in node %pOF\n", 266f7ce9103SRob Herring np); 267ec21e2ecSJeff Kirsher continue; 268afae5ad7STimur Tabi } 269ec21e2ecSJeff Kirsher 270ec21e2ecSJeff Kirsher /* if our mdio regs fall within this UCC regs range */ 271afae5ad7STimur Tabi if ((start < res.start) || (end > res.end)) 272afae5ad7STimur Tabi continue; 273ec21e2ecSJeff Kirsher 274afae5ad7STimur Tabi iprop = of_get_property(np, "cell-index", NULL); 275afae5ad7STimur Tabi if (!iprop) { 276afae5ad7STimur Tabi iprop = of_get_property(np, "device-id", NULL); 277afae5ad7STimur Tabi if (!iprop) { 278f7ce9103SRob Herring pr_debug("fsl-pq-mdio: no UCC ID in node %pOF\n", 279f7ce9103SRob Herring np); 280afae5ad7STimur Tabi continue; 281afae5ad7STimur Tabi } 282afae5ad7STimur Tabi } 283afae5ad7STimur Tabi 284afae5ad7STimur Tabi id = be32_to_cpup(iprop); 285afae5ad7STimur Tabi 286afae5ad7STimur Tabi /* 287afae5ad7STimur Tabi * cell-index and device-id for QE nodes are 288afae5ad7STimur Tabi * numbered from 1, not 0. 289afae5ad7STimur Tabi */ 290afae5ad7STimur Tabi if (ucc_set_qe_mux_mii_mng(id - 1) < 0) { 291f7ce9103SRob Herring pr_debug("fsl-pq-mdio: invalid UCC ID in node %pOF\n", 292f7ce9103SRob Herring np); 293ec21e2ecSJeff Kirsher continue; 294ec21e2ecSJeff Kirsher } 295ec21e2ecSJeff Kirsher 296afae5ad7STimur Tabi pr_debug("fsl-pq-mdio: setting node UCC%u to MII master\n", id); 297afae5ad7STimur Tabi found_mii_master = true; 298ec21e2ecSJeff Kirsher } 299ec21e2ecSJeff Kirsher } 300ec21e2ecSJeff Kirsher 301ec21e2ecSJeff Kirsher #endif 302afae5ad7STimur Tabi 30394e5a2a8SFabian Frederick static const struct of_device_id fsl_pq_mdio_match[] = { 304504e76e5SJavier Martinez Canillas #if IS_ENABLED(CONFIG_GIANFAR) 305afae5ad7STimur Tabi { 306afae5ad7STimur Tabi .compatible = "fsl,gianfar-tbi", 307afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 308afae5ad7STimur Tabi .mii_offset = 0, 3093bb35ac4SGerlando Falauto .get_tbipa = get_gfar_tbipa_from_mii, 310afae5ad7STimur Tabi }, 311afae5ad7STimur Tabi }, 312afae5ad7STimur Tabi { 313afae5ad7STimur Tabi .compatible = "fsl,gianfar-mdio", 314afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 315afae5ad7STimur Tabi .mii_offset = 0, 3163bb35ac4SGerlando Falauto .get_tbipa = get_gfar_tbipa_from_mii, 317afae5ad7STimur Tabi }, 318afae5ad7STimur Tabi }, 319afae5ad7STimur Tabi { 320afae5ad7STimur Tabi .type = "mdio", 321afae5ad7STimur Tabi .compatible = "gianfar", 322afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 323afae5ad7STimur Tabi .mii_offset = offsetof(struct fsl_pq_mdio, mii), 3243bb35ac4SGerlando Falauto .get_tbipa = get_gfar_tbipa_from_mdio, 325afae5ad7STimur Tabi }, 326afae5ad7STimur Tabi }, 327afae5ad7STimur Tabi { 328afae5ad7STimur Tabi .compatible = "fsl,etsec2-tbi", 329afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 330afae5ad7STimur Tabi .mii_offset = offsetof(struct fsl_pq_mdio, mii), 331afae5ad7STimur Tabi .get_tbipa = get_etsec_tbipa, 332afae5ad7STimur Tabi }, 333afae5ad7STimur Tabi }, 334afae5ad7STimur Tabi { 335afae5ad7STimur Tabi .compatible = "fsl,etsec2-mdio", 336afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 337afae5ad7STimur Tabi .mii_offset = offsetof(struct fsl_pq_mdio, mii), 338afae5ad7STimur Tabi .get_tbipa = get_etsec_tbipa, 339afae5ad7STimur Tabi }, 340afae5ad7STimur Tabi }, 341afae5ad7STimur Tabi #endif 342504e76e5SJavier Martinez Canillas #if IS_ENABLED(CONFIG_UCC_GETH) 343afae5ad7STimur Tabi { 344afae5ad7STimur Tabi .compatible = "fsl,ucc-mdio", 345afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 346afae5ad7STimur Tabi .mii_offset = 0, 347afae5ad7STimur Tabi .get_tbipa = get_ucc_tbipa, 348afae5ad7STimur Tabi .ucc_configure = ucc_configure, 349afae5ad7STimur Tabi }, 350afae5ad7STimur Tabi }, 351afae5ad7STimur Tabi { 352afae5ad7STimur Tabi /* Legacy UCC MDIO node */ 353afae5ad7STimur Tabi .type = "mdio", 354afae5ad7STimur Tabi .compatible = "ucc_geth_phy", 355afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 356afae5ad7STimur Tabi .mii_offset = 0, 357afae5ad7STimur Tabi .get_tbipa = get_ucc_tbipa, 358afae5ad7STimur Tabi .ucc_configure = ucc_configure, 359afae5ad7STimur Tabi }, 360afae5ad7STimur Tabi }, 361afae5ad7STimur Tabi #endif 362761743ebSTimur Tabi /* No Kconfig option for Fman support yet */ 363761743ebSTimur Tabi { 364761743ebSTimur Tabi .compatible = "fsl,fman-mdio", 365761743ebSTimur Tabi .data = &(struct fsl_pq_mdio_data) { 366761743ebSTimur Tabi .mii_offset = 0, 367761743ebSTimur Tabi /* Fman TBI operations are handled elsewhere */ 368761743ebSTimur Tabi }, 369761743ebSTimur Tabi }, 370761743ebSTimur Tabi 371afae5ad7STimur Tabi {}, 372afae5ad7STimur Tabi }; 373afae5ad7STimur Tabi MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match); 374ec21e2ecSJeff Kirsher 37521481189SEsben Haabendal static void set_tbipa(const u32 tbipa_val, struct platform_device *pdev, 37621481189SEsben Haabendal uint32_t __iomem * (*get_tbipa)(void __iomem *), 37721481189SEsben Haabendal void __iomem *reg_map, struct resource *reg_res) 37821481189SEsben Haabendal { 37921481189SEsben Haabendal struct device_node *np = pdev->dev.of_node; 38021481189SEsben Haabendal uint32_t __iomem *tbipa; 38121481189SEsben Haabendal bool tbipa_mapped; 38221481189SEsben Haabendal 38321481189SEsben Haabendal tbipa = of_iomap(np, 1); 38421481189SEsben Haabendal if (tbipa) { 38521481189SEsben Haabendal tbipa_mapped = true; 38621481189SEsben Haabendal } else { 38721481189SEsben Haabendal tbipa_mapped = false; 38821481189SEsben Haabendal tbipa = (*get_tbipa)(reg_map); 38921481189SEsben Haabendal 39021481189SEsben Haabendal /* 39121481189SEsben Haabendal * Add consistency check to make sure TBI is contained within 39221481189SEsben Haabendal * the mapped range (not because we would get a segfault, 39321481189SEsben Haabendal * rather to catch bugs in computing TBI address). Print error 39421481189SEsben Haabendal * message but continue anyway. 39521481189SEsben Haabendal */ 39621481189SEsben Haabendal if ((void *)tbipa > reg_map + resource_size(reg_res) - 4) 39721481189SEsben Haabendal dev_err(&pdev->dev, "invalid register map (should be at least 0x%04zx to contain TBI address)\n", 39821481189SEsben Haabendal ((void *)tbipa - reg_map) + 4); 39921481189SEsben Haabendal } 40021481189SEsben Haabendal 40121481189SEsben Haabendal iowrite32be(be32_to_cpu(tbipa_val), tbipa); 40221481189SEsben Haabendal 40321481189SEsben Haabendal if (tbipa_mapped) 40421481189SEsben Haabendal iounmap(tbipa); 40521481189SEsben Haabendal } 40621481189SEsben Haabendal 4075078ac79STimur Tabi static int fsl_pq_mdio_probe(struct platform_device *pdev) 408ec21e2ecSJeff Kirsher { 409afae5ad7STimur Tabi const struct of_device_id *id = 410afae5ad7STimur Tabi of_match_device(fsl_pq_mdio_match, &pdev->dev); 41106d2d643SGustavo A. R. Silva const struct fsl_pq_mdio_data *data; 4125078ac79STimur Tabi struct device_node *np = pdev->dev.of_node; 413afae5ad7STimur Tabi struct resource res; 414ec21e2ecSJeff Kirsher struct device_node *tbi; 415ec21e2ecSJeff Kirsher struct fsl_pq_mdio_priv *priv; 416ec21e2ecSJeff Kirsher struct mii_bus *new_bus; 417ec21e2ecSJeff Kirsher int err; 418ec21e2ecSJeff Kirsher 41906d2d643SGustavo A. R. Silva if (!id) { 42006d2d643SGustavo A. R. Silva dev_err(&pdev->dev, "Failed to match device\n"); 42106d2d643SGustavo A. R. Silva return -ENODEV; 42206d2d643SGustavo A. R. Silva } 42306d2d643SGustavo A. R. Silva 42406d2d643SGustavo A. R. Silva data = id->data; 42506d2d643SGustavo A. R. Silva 426afae5ad7STimur Tabi dev_dbg(&pdev->dev, "found %s compatible node\n", id->compatible); 427afae5ad7STimur Tabi 428dd3b8a32STimur Tabi new_bus = mdiobus_alloc_size(sizeof(*priv)); 429dd3b8a32STimur Tabi if (!new_bus) 430ec21e2ecSJeff Kirsher return -ENOMEM; 431ec21e2ecSJeff Kirsher 432dd3b8a32STimur Tabi priv = new_bus->priv; 433af89784eSZheng Yongjun new_bus->name = "Freescale PowerQUICC MII Bus"; 4345078ac79STimur Tabi new_bus->read = &fsl_pq_mdio_read; 4355078ac79STimur Tabi new_bus->write = &fsl_pq_mdio_write; 4365078ac79STimur Tabi new_bus->reset = &fsl_pq_mdio_reset; 437ec21e2ecSJeff Kirsher 438afae5ad7STimur Tabi err = of_address_to_resource(np, 0, &res); 439afae5ad7STimur Tabi if (err < 0) { 440afae5ad7STimur Tabi dev_err(&pdev->dev, "could not obtain address information\n"); 441dd3b8a32STimur Tabi goto error; 442ec21e2ecSJeff Kirsher } 443ec21e2ecSJeff Kirsher 44421c328dcSRob Herring snprintf(new_bus->id, MII_BUS_ID_SIZE, "%pOFn@%llx", np, 445afae5ad7STimur Tabi (unsigned long long)res.start); 44669cfb419STimur Tabi 447afae5ad7STimur Tabi priv->map = of_iomap(np, 0); 448afae5ad7STimur Tabi if (!priv->map) { 449ec21e2ecSJeff Kirsher err = -ENOMEM; 450dd3b8a32STimur Tabi goto error; 451ec21e2ecSJeff Kirsher } 452ec21e2ecSJeff Kirsher 453afae5ad7STimur Tabi /* 454afae5ad7STimur Tabi * Some device tree nodes represent only the MII registers, and 455afae5ad7STimur Tabi * others represent the MAC and MII registers. The 'mii_offset' field 456afae5ad7STimur Tabi * contains the offset of the MII registers inside the mapped register 457afae5ad7STimur Tabi * space. 458afae5ad7STimur Tabi */ 459afae5ad7STimur Tabi if (data->mii_offset > resource_size(&res)) { 460afae5ad7STimur Tabi dev_err(&pdev->dev, "invalid register map\n"); 461afae5ad7STimur Tabi err = -EINVAL; 462dd3b8a32STimur Tabi goto error; 463afae5ad7STimur Tabi } 464afae5ad7STimur Tabi priv->regs = priv->map + data->mii_offset; 465ec21e2ecSJeff Kirsher 4665078ac79STimur Tabi new_bus->parent = &pdev->dev; 467a0e18600SLibo Chen platform_set_drvdata(pdev, new_bus); 468ec21e2ecSJeff Kirsher 469afae5ad7STimur Tabi if (data->get_tbipa) { 470ec21e2ecSJeff Kirsher for_each_child_of_node(np, tbi) { 471d7b4a2f2SRob Herring if (of_node_is_type(tbi, "tbi-phy")) { 472f7ce9103SRob Herring dev_dbg(&pdev->dev, "found TBI PHY node %pOFP\n", 473f7ce9103SRob Herring tbi); 474ec21e2ecSJeff Kirsher break; 475ec21e2ecSJeff Kirsher } 476afae5ad7STimur Tabi } 477ec21e2ecSJeff Kirsher 478ec21e2ecSJeff Kirsher if (tbi) { 479ec21e2ecSJeff Kirsher const u32 *prop = of_get_property(tbi, "reg", NULL); 480afae5ad7STimur Tabi if (!prop) { 481afae5ad7STimur Tabi dev_err(&pdev->dev, 482f7ce9103SRob Herring "missing 'reg' property in node %pOF\n", 483f7ce9103SRob Herring tbi); 484ec21e2ecSJeff Kirsher err = -EBUSY; 485afae5ad7STimur Tabi goto error; 486afae5ad7STimur Tabi } 48721481189SEsben Haabendal set_tbipa(*prop, pdev, 48821481189SEsben Haabendal data->get_tbipa, priv->map, &res); 489c3e072f8SBaruch Siach } 490464b57daSKenth Eriksson } 491ec21e2ecSJeff Kirsher 492afae5ad7STimur Tabi if (data->ucc_configure) 493afae5ad7STimur Tabi data->ucc_configure(res.start, res.end); 494afae5ad7STimur Tabi 495ec21e2ecSJeff Kirsher err = of_mdiobus_register(new_bus, np); 496ec21e2ecSJeff Kirsher if (err) { 4975078ac79STimur Tabi dev_err(&pdev->dev, "cannot register %s as MDIO bus\n", 498ec21e2ecSJeff Kirsher new_bus->name); 499dd3b8a32STimur Tabi goto error; 500ec21e2ecSJeff Kirsher } 501ec21e2ecSJeff Kirsher 502ec21e2ecSJeff Kirsher return 0; 503ec21e2ecSJeff Kirsher 504dd3b8a32STimur Tabi error: 505dd3b8a32STimur Tabi if (priv->map) 506ec21e2ecSJeff Kirsher iounmap(priv->map); 507dd3b8a32STimur Tabi 508ec21e2ecSJeff Kirsher kfree(new_bus); 509dd3b8a32STimur Tabi 510ec21e2ecSJeff Kirsher return err; 511ec21e2ecSJeff Kirsher } 512ec21e2ecSJeff Kirsher 513ec21e2ecSJeff Kirsher 514*f8336355SUwe Kleine-König static void fsl_pq_mdio_remove(struct platform_device *pdev) 515ec21e2ecSJeff Kirsher { 5165078ac79STimur Tabi struct device *device = &pdev->dev; 517ec21e2ecSJeff Kirsher struct mii_bus *bus = dev_get_drvdata(device); 518ec21e2ecSJeff Kirsher struct fsl_pq_mdio_priv *priv = bus->priv; 519ec21e2ecSJeff Kirsher 520ec21e2ecSJeff Kirsher mdiobus_unregister(bus); 521ec21e2ecSJeff Kirsher 522ec21e2ecSJeff Kirsher iounmap(priv->map); 523ec21e2ecSJeff Kirsher mdiobus_free(bus); 524ec21e2ecSJeff Kirsher } 525ec21e2ecSJeff Kirsher 526ec21e2ecSJeff Kirsher static struct platform_driver fsl_pq_mdio_driver = { 527ec21e2ecSJeff Kirsher .driver = { 528ec21e2ecSJeff Kirsher .name = "fsl-pq_mdio", 529ec21e2ecSJeff Kirsher .of_match_table = fsl_pq_mdio_match, 530ec21e2ecSJeff Kirsher }, 531ec21e2ecSJeff Kirsher .probe = fsl_pq_mdio_probe, 532*f8336355SUwe Kleine-König .remove_new = fsl_pq_mdio_remove, 533ec21e2ecSJeff Kirsher }; 534ec21e2ecSJeff Kirsher 535db62f684SAxel Lin module_platform_driver(fsl_pq_mdio_driver); 536ec21e2ecSJeff Kirsher 537ec21e2ecSJeff Kirsher MODULE_LICENSE("GPL"); 538