1ec21e2ecSJeff Kirsher /* 2ec21e2ecSJeff Kirsher * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation 3ec21e2ecSJeff Kirsher * Provides Bus interface for MIIM regs 4ec21e2ecSJeff Kirsher * 5ec21e2ecSJeff Kirsher * Author: Andy Fleming <afleming@freescale.com> 6ec21e2ecSJeff Kirsher * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 7ec21e2ecSJeff Kirsher * 8ec21e2ecSJeff Kirsher * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc. 9ec21e2ecSJeff Kirsher * 10ec21e2ecSJeff Kirsher * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips) 11ec21e2ecSJeff Kirsher * 12ec21e2ecSJeff Kirsher * This program is free software; you can redistribute it and/or modify it 13ec21e2ecSJeff Kirsher * under the terms of the GNU General Public License as published by the 14ec21e2ecSJeff Kirsher * Free Software Foundation; either version 2 of the License, or (at your 15ec21e2ecSJeff Kirsher * option) any later version. 16ec21e2ecSJeff Kirsher * 17ec21e2ecSJeff Kirsher */ 18ec21e2ecSJeff Kirsher 19ec21e2ecSJeff Kirsher #include <linux/kernel.h> 20ec21e2ecSJeff Kirsher #include <linux/string.h> 21ec21e2ecSJeff Kirsher #include <linux/errno.h> 22ec21e2ecSJeff Kirsher #include <linux/slab.h> 23ec21e2ecSJeff Kirsher #include <linux/delay.h> 24ec21e2ecSJeff Kirsher #include <linux/module.h> 25ec21e2ecSJeff Kirsher #include <linux/mii.h> 26ec21e2ecSJeff Kirsher #include <linux/of_address.h> 27ec21e2ecSJeff Kirsher #include <linux/of_mdio.h> 28afae5ad7STimur Tabi #include <linux/of_device.h> 29ec21e2ecSJeff Kirsher 30ec21e2ecSJeff Kirsher #include <asm/io.h> 319a4cbd53SClaudiu Manoil #if IS_ENABLED(CONFIG_UCC_GETH) 321aa06d42STimur Tabi #include <asm/ucc.h> /* for ucc_set_qe_mux_mii_mng() */ 339a4cbd53SClaudiu Manoil #endif 34ec21e2ecSJeff Kirsher 35ec21e2ecSJeff Kirsher #include "gianfar.h" 3619bcd6c6STimur Tabi 3719bcd6c6STimur Tabi #define MIIMIND_BUSY 0x00000001 3819bcd6c6STimur Tabi #define MIIMIND_NOTVALID 0x00000004 3919bcd6c6STimur Tabi #define MIIMCFG_INIT_VALUE 0x00000007 4019bcd6c6STimur Tabi #define MIIMCFG_RESET 0x80000000 4119bcd6c6STimur Tabi 4219bcd6c6STimur Tabi #define MII_READ_COMMAND 0x00000001 4319bcd6c6STimur Tabi 44afae5ad7STimur Tabi struct fsl_pq_mii { 45afae5ad7STimur Tabi u32 miimcfg; /* MII management configuration reg */ 46afae5ad7STimur Tabi u32 miimcom; /* MII management command reg */ 47afae5ad7STimur Tabi u32 miimadd; /* MII management address reg */ 48afae5ad7STimur Tabi u32 miimcon; /* MII management control reg */ 49afae5ad7STimur Tabi u32 miimstat; /* MII management status reg */ 50afae5ad7STimur Tabi u32 miimind; /* MII management indication reg */ 51afae5ad7STimur Tabi }; 52afae5ad7STimur Tabi 5319bcd6c6STimur Tabi struct fsl_pq_mdio { 5419bcd6c6STimur Tabi u8 res1[16]; 5519bcd6c6STimur Tabi u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/ 5619bcd6c6STimur Tabi u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/ 5719bcd6c6STimur Tabi u8 res2[4]; 5819bcd6c6STimur Tabi u32 emapm; /* MDIO Event mapping register (for etsec2)*/ 5919bcd6c6STimur Tabi u8 res3[1280]; 60afae5ad7STimur Tabi struct fsl_pq_mii mii; 6119bcd6c6STimur Tabi u8 res4[28]; 6219bcd6c6STimur Tabi u32 utbipar; /* TBI phy address reg (only on UCC) */ 6319bcd6c6STimur Tabi u8 res5[2728]; 6419bcd6c6STimur Tabi } __packed; 65ec21e2ecSJeff Kirsher 6659399c59STimur Tabi /* Number of microseconds to wait for an MII register to respond */ 6759399c59STimur Tabi #define MII_TIMEOUT 1000 6859399c59STimur Tabi 69ec21e2ecSJeff Kirsher struct fsl_pq_mdio_priv { 70ec21e2ecSJeff Kirsher void __iomem *map; 71afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs; 72dd3b8a32STimur Tabi int irqs[PHY_MAX_ADDR]; 73afae5ad7STimur Tabi }; 74afae5ad7STimur Tabi 75afae5ad7STimur Tabi /* 76afae5ad7STimur Tabi * Per-device-type data. Each type of device tree node that we support gets 77afae5ad7STimur Tabi * one of these. 78afae5ad7STimur Tabi * 79afae5ad7STimur Tabi * @mii_offset: the offset of the MII registers within the memory map of the 80afae5ad7STimur Tabi * node. Some nodes define only the MII registers, and some define the whole 81afae5ad7STimur Tabi * MAC (which includes the MII registers). 82afae5ad7STimur Tabi * 83afae5ad7STimur Tabi * @get_tbipa: determines the address of the TBIPA register 84afae5ad7STimur Tabi * 85afae5ad7STimur Tabi * @ucc_configure: a special function for extra QE configuration 86afae5ad7STimur Tabi */ 87afae5ad7STimur Tabi struct fsl_pq_mdio_data { 88afae5ad7STimur Tabi unsigned int mii_offset; /* offset of the MII registers */ 89afae5ad7STimur Tabi uint32_t __iomem * (*get_tbipa)(void __iomem *p); 90afae5ad7STimur Tabi void (*ucc_configure)(phys_addr_t start, phys_addr_t end); 91ec21e2ecSJeff Kirsher }; 92ec21e2ecSJeff Kirsher 93ec21e2ecSJeff Kirsher /* 9469cfb419STimur Tabi * Write value to the PHY at mii_id at register regnum, on the bus attached 9569cfb419STimur Tabi * to the local interface, which may be different from the generic mdio bus 9669cfb419STimur Tabi * (tied to a single interface), waiting until the write is done before 9769cfb419STimur Tabi * returning. This is helpful in programming interfaces like the TBI which 9869cfb419STimur Tabi * control interfaces like onchip SERDES and are always tied to the local 9969cfb419STimur Tabi * mdio pins, which may not be the same as system mdio bus, used for 100ec21e2ecSJeff Kirsher * controlling the external PHYs, for example. 101ec21e2ecSJeff Kirsher */ 10269cfb419STimur Tabi static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 10369cfb419STimur Tabi u16 value) 104ec21e2ecSJeff Kirsher { 10569cfb419STimur Tabi struct fsl_pq_mdio_priv *priv = bus->priv; 106afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs = priv->regs; 10759399c59STimur Tabi u32 status; 10859399c59STimur Tabi 109ec21e2ecSJeff Kirsher /* Set the PHY address and the register address we want to write */ 110ec21e2ecSJeff Kirsher out_be32(®s->miimadd, (mii_id << 8) | regnum); 111ec21e2ecSJeff Kirsher 112ec21e2ecSJeff Kirsher /* Write out the value we want */ 113ec21e2ecSJeff Kirsher out_be32(®s->miimcon, value); 114ec21e2ecSJeff Kirsher 115ec21e2ecSJeff Kirsher /* Wait for the transaction to finish */ 11659399c59STimur Tabi status = spin_event_timeout(!(in_be32(®s->miimind) & MIIMIND_BUSY), 11759399c59STimur Tabi MII_TIMEOUT, 0); 118ec21e2ecSJeff Kirsher 11959399c59STimur Tabi return status ? 0 : -ETIMEDOUT; 120ec21e2ecSJeff Kirsher } 121ec21e2ecSJeff Kirsher 122ec21e2ecSJeff Kirsher /* 12369cfb419STimur Tabi * Read the bus for PHY at addr mii_id, register regnum, and return the value. 12469cfb419STimur Tabi * Clears miimcom first. 12569cfb419STimur Tabi * 12669cfb419STimur Tabi * All PHY operation done on the bus attached to the local interface, which 12769cfb419STimur Tabi * may be different from the generic mdio bus. This is helpful in programming 12869cfb419STimur Tabi * interfaces like the TBI which, in turn, control interfaces like on-chip 12969cfb419STimur Tabi * SERDES and are always tied to the local mdio pins, which may not be the 130ec21e2ecSJeff Kirsher * same as system mdio bus, used for controlling the external PHYs, for eg. 131ec21e2ecSJeff Kirsher */ 13269cfb419STimur Tabi static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 133ec21e2ecSJeff Kirsher { 13469cfb419STimur Tabi struct fsl_pq_mdio_priv *priv = bus->priv; 135afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs = priv->regs; 13659399c59STimur Tabi u32 status; 13769cfb419STimur Tabi u16 value; 138ec21e2ecSJeff Kirsher 139ec21e2ecSJeff Kirsher /* Set the PHY address and the register address we want to read */ 140ec21e2ecSJeff Kirsher out_be32(®s->miimadd, (mii_id << 8) | regnum); 141ec21e2ecSJeff Kirsher 142ec21e2ecSJeff Kirsher /* Clear miimcom, and then initiate a read */ 143ec21e2ecSJeff Kirsher out_be32(®s->miimcom, 0); 144ec21e2ecSJeff Kirsher out_be32(®s->miimcom, MII_READ_COMMAND); 145ec21e2ecSJeff Kirsher 14659399c59STimur Tabi /* Wait for the transaction to finish, normally less than 100us */ 14759399c59STimur Tabi status = spin_event_timeout(!(in_be32(®s->miimind) & 14859399c59STimur Tabi (MIIMIND_NOTVALID | MIIMIND_BUSY)), 14959399c59STimur Tabi MII_TIMEOUT, 0); 15059399c59STimur Tabi if (!status) 15159399c59STimur Tabi return -ETIMEDOUT; 152ec21e2ecSJeff Kirsher 153ec21e2ecSJeff Kirsher /* Grab the value of the register from miimstat */ 154ec21e2ecSJeff Kirsher value = in_be32(®s->miimstat); 155ec21e2ecSJeff Kirsher 156afae5ad7STimur Tabi dev_dbg(&bus->dev, "read %04x from address %x/%x\n", value, mii_id, regnum); 157ec21e2ecSJeff Kirsher return value; 158ec21e2ecSJeff Kirsher } 159ec21e2ecSJeff Kirsher 160ec21e2ecSJeff Kirsher /* Reset the MIIM registers, and wait for the bus to free */ 161ec21e2ecSJeff Kirsher static int fsl_pq_mdio_reset(struct mii_bus *bus) 162ec21e2ecSJeff Kirsher { 16369cfb419STimur Tabi struct fsl_pq_mdio_priv *priv = bus->priv; 164afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs = priv->regs; 16559399c59STimur Tabi u32 status; 166ec21e2ecSJeff Kirsher 167ec21e2ecSJeff Kirsher mutex_lock(&bus->mdio_lock); 168ec21e2ecSJeff Kirsher 169ec21e2ecSJeff Kirsher /* Reset the management interface */ 170ec21e2ecSJeff Kirsher out_be32(®s->miimcfg, MIIMCFG_RESET); 171ec21e2ecSJeff Kirsher 172ec21e2ecSJeff Kirsher /* Setup the MII Mgmt clock speed */ 173ec21e2ecSJeff Kirsher out_be32(®s->miimcfg, MIIMCFG_INIT_VALUE); 174ec21e2ecSJeff Kirsher 175ec21e2ecSJeff Kirsher /* Wait until the bus is free */ 17659399c59STimur Tabi status = spin_event_timeout(!(in_be32(®s->miimind) & MIIMIND_BUSY), 17759399c59STimur Tabi MII_TIMEOUT, 0); 178ec21e2ecSJeff Kirsher 179ec21e2ecSJeff Kirsher mutex_unlock(&bus->mdio_lock); 180ec21e2ecSJeff Kirsher 18159399c59STimur Tabi if (!status) { 1825078ac79STimur Tabi dev_err(&bus->dev, "timeout waiting for MII bus\n"); 183ec21e2ecSJeff Kirsher return -EBUSY; 184ec21e2ecSJeff Kirsher } 185ec21e2ecSJeff Kirsher 186ec21e2ecSJeff Kirsher return 0; 187ec21e2ecSJeff Kirsher } 188ec21e2ecSJeff Kirsher 189952c5ca1SAndy Fleming #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE) 190ec21e2ecSJeff Kirsher /* 191ec21e2ecSJeff Kirsher * This is mildly evil, but so is our hardware for doing this. 192ec21e2ecSJeff Kirsher * Also, we have to cast back to struct gfar because of 193ec21e2ecSJeff Kirsher * definition weirdness done in gianfar.h. 194ec21e2ecSJeff Kirsher */ 195afae5ad7STimur Tabi static uint32_t __iomem *get_gfar_tbipa(void __iomem *p) 196afae5ad7STimur Tabi { 197afae5ad7STimur Tabi struct gfar __iomem *enet_regs = p; 198afae5ad7STimur Tabi 199ec21e2ecSJeff Kirsher return &enet_regs->tbipa; 200afae5ad7STimur Tabi } 201afae5ad7STimur Tabi 202afae5ad7STimur Tabi /* 203afae5ad7STimur Tabi * Return the TBIPAR address for an eTSEC2 node 204afae5ad7STimur Tabi */ 205afae5ad7STimur Tabi static uint32_t __iomem *get_etsec_tbipa(void __iomem *p) 206afae5ad7STimur Tabi { 207afae5ad7STimur Tabi return p; 208ec21e2ecSJeff Kirsher } 209ec21e2ecSJeff Kirsher #endif 210afae5ad7STimur Tabi 211afae5ad7STimur Tabi #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE) 212afae5ad7STimur Tabi /* 213afae5ad7STimur Tabi * Return the TBIPAR address for a QE MDIO node 214afae5ad7STimur Tabi */ 215afae5ad7STimur Tabi static uint32_t __iomem *get_ucc_tbipa(void __iomem *p) 216afae5ad7STimur Tabi { 217afae5ad7STimur Tabi struct fsl_pq_mdio __iomem *mdio = p; 218afae5ad7STimur Tabi 219afae5ad7STimur Tabi return &mdio->utbipar; 220952c5ca1SAndy Fleming } 221ec21e2ecSJeff Kirsher 222afae5ad7STimur Tabi /* 223afae5ad7STimur Tabi * Find the UCC node that controls the given MDIO node 224afae5ad7STimur Tabi * 225afae5ad7STimur Tabi * For some reason, the QE MDIO nodes are not children of the UCC devices 226afae5ad7STimur Tabi * that control them. Therefore, we need to scan all UCC nodes looking for 227afae5ad7STimur Tabi * the one that encompases the given MDIO node. We do this by comparing 228afae5ad7STimur Tabi * physical addresses. The 'start' and 'end' addresses of the MDIO node are 229afae5ad7STimur Tabi * passed, and the correct UCC node will cover the entire address range. 230afae5ad7STimur Tabi * 231afae5ad7STimur Tabi * This assumes that there is only one QE MDIO node in the entire device tree. 232afae5ad7STimur Tabi */ 233afae5ad7STimur Tabi static void ucc_configure(phys_addr_t start, phys_addr_t end) 234ec21e2ecSJeff Kirsher { 235afae5ad7STimur Tabi static bool found_mii_master; 236ec21e2ecSJeff Kirsher struct device_node *np = NULL; 237afae5ad7STimur Tabi 238afae5ad7STimur Tabi if (found_mii_master) 239afae5ad7STimur Tabi return; 240ec21e2ecSJeff Kirsher 241ec21e2ecSJeff Kirsher for_each_compatible_node(np, NULL, "ucc_geth") { 242afae5ad7STimur Tabi struct resource res; 243afae5ad7STimur Tabi const uint32_t *iprop; 244afae5ad7STimur Tabi uint32_t id; 245afae5ad7STimur Tabi int ret; 246ec21e2ecSJeff Kirsher 247afae5ad7STimur Tabi ret = of_address_to_resource(np, 0, &res); 248afae5ad7STimur Tabi if (ret < 0) { 249afae5ad7STimur Tabi pr_debug("fsl-pq-mdio: no address range in node %s\n", 250afae5ad7STimur Tabi np->full_name); 251ec21e2ecSJeff Kirsher continue; 252afae5ad7STimur Tabi } 253ec21e2ecSJeff Kirsher 254ec21e2ecSJeff Kirsher /* if our mdio regs fall within this UCC regs range */ 255afae5ad7STimur Tabi if ((start < res.start) || (end > res.end)) 256afae5ad7STimur Tabi continue; 257ec21e2ecSJeff Kirsher 258afae5ad7STimur Tabi iprop = of_get_property(np, "cell-index", NULL); 259afae5ad7STimur Tabi if (!iprop) { 260afae5ad7STimur Tabi iprop = of_get_property(np, "device-id", NULL); 261afae5ad7STimur Tabi if (!iprop) { 262afae5ad7STimur Tabi pr_debug("fsl-pq-mdio: no UCC ID in node %s\n", 263afae5ad7STimur Tabi np->full_name); 264afae5ad7STimur Tabi continue; 265afae5ad7STimur Tabi } 266afae5ad7STimur Tabi } 267afae5ad7STimur Tabi 268afae5ad7STimur Tabi id = be32_to_cpup(iprop); 269afae5ad7STimur Tabi 270afae5ad7STimur Tabi /* 271afae5ad7STimur Tabi * cell-index and device-id for QE nodes are 272afae5ad7STimur Tabi * numbered from 1, not 0. 273afae5ad7STimur Tabi */ 274afae5ad7STimur Tabi if (ucc_set_qe_mux_mii_mng(id - 1) < 0) { 275afae5ad7STimur Tabi pr_debug("fsl-pq-mdio: invalid UCC ID in node %s\n", 276afae5ad7STimur Tabi np->full_name); 277ec21e2ecSJeff Kirsher continue; 278ec21e2ecSJeff Kirsher } 279ec21e2ecSJeff Kirsher 280afae5ad7STimur Tabi pr_debug("fsl-pq-mdio: setting node UCC%u to MII master\n", id); 281afae5ad7STimur Tabi found_mii_master = true; 282ec21e2ecSJeff Kirsher } 283ec21e2ecSJeff Kirsher } 284ec21e2ecSJeff Kirsher 285ec21e2ecSJeff Kirsher #endif 286afae5ad7STimur Tabi 287afae5ad7STimur Tabi static struct of_device_id fsl_pq_mdio_match[] = { 288afae5ad7STimur Tabi #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE) 289afae5ad7STimur Tabi { 290afae5ad7STimur Tabi .compatible = "fsl,gianfar-tbi", 291afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 292afae5ad7STimur Tabi .mii_offset = 0, 293afae5ad7STimur Tabi .get_tbipa = get_gfar_tbipa, 294afae5ad7STimur Tabi }, 295afae5ad7STimur Tabi }, 296afae5ad7STimur Tabi { 297afae5ad7STimur Tabi .compatible = "fsl,gianfar-mdio", 298afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 299afae5ad7STimur Tabi .mii_offset = 0, 300afae5ad7STimur Tabi .get_tbipa = get_gfar_tbipa, 301afae5ad7STimur Tabi }, 302afae5ad7STimur Tabi }, 303afae5ad7STimur Tabi { 304afae5ad7STimur Tabi .type = "mdio", 305afae5ad7STimur Tabi .compatible = "gianfar", 306afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 307afae5ad7STimur Tabi .mii_offset = offsetof(struct fsl_pq_mdio, mii), 308afae5ad7STimur Tabi .get_tbipa = get_gfar_tbipa, 309afae5ad7STimur Tabi }, 310afae5ad7STimur Tabi }, 311afae5ad7STimur Tabi { 312afae5ad7STimur Tabi .compatible = "fsl,etsec2-tbi", 313afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 314afae5ad7STimur Tabi .mii_offset = offsetof(struct fsl_pq_mdio, mii), 315afae5ad7STimur Tabi .get_tbipa = get_etsec_tbipa, 316afae5ad7STimur Tabi }, 317afae5ad7STimur Tabi }, 318afae5ad7STimur Tabi { 319afae5ad7STimur Tabi .compatible = "fsl,etsec2-mdio", 320afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 321afae5ad7STimur Tabi .mii_offset = offsetof(struct fsl_pq_mdio, mii), 322afae5ad7STimur Tabi .get_tbipa = get_etsec_tbipa, 323afae5ad7STimur Tabi }, 324afae5ad7STimur Tabi }, 325afae5ad7STimur Tabi #endif 326afae5ad7STimur Tabi #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE) 327afae5ad7STimur Tabi { 328afae5ad7STimur Tabi .compatible = "fsl,ucc-mdio", 329afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 330afae5ad7STimur Tabi .mii_offset = 0, 331afae5ad7STimur Tabi .get_tbipa = get_ucc_tbipa, 332afae5ad7STimur Tabi .ucc_configure = ucc_configure, 333afae5ad7STimur Tabi }, 334afae5ad7STimur Tabi }, 335afae5ad7STimur Tabi { 336afae5ad7STimur Tabi /* Legacy UCC MDIO node */ 337afae5ad7STimur Tabi .type = "mdio", 338afae5ad7STimur Tabi .compatible = "ucc_geth_phy", 339afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 340afae5ad7STimur Tabi .mii_offset = 0, 341afae5ad7STimur Tabi .get_tbipa = get_ucc_tbipa, 342afae5ad7STimur Tabi .ucc_configure = ucc_configure, 343afae5ad7STimur Tabi }, 344afae5ad7STimur Tabi }, 345afae5ad7STimur Tabi #endif 346761743ebSTimur Tabi /* No Kconfig option for Fman support yet */ 347761743ebSTimur Tabi { 348761743ebSTimur Tabi .compatible = "fsl,fman-mdio", 349761743ebSTimur Tabi .data = &(struct fsl_pq_mdio_data) { 350761743ebSTimur Tabi .mii_offset = 0, 351761743ebSTimur Tabi /* Fman TBI operations are handled elsewhere */ 352761743ebSTimur Tabi }, 353761743ebSTimur Tabi }, 354761743ebSTimur Tabi 355afae5ad7STimur Tabi {}, 356afae5ad7STimur Tabi }; 357afae5ad7STimur Tabi MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match); 358ec21e2ecSJeff Kirsher 3595078ac79STimur Tabi static int fsl_pq_mdio_probe(struct platform_device *pdev) 360ec21e2ecSJeff Kirsher { 361afae5ad7STimur Tabi const struct of_device_id *id = 362afae5ad7STimur Tabi of_match_device(fsl_pq_mdio_match, &pdev->dev); 363afae5ad7STimur Tabi const struct fsl_pq_mdio_data *data = id->data; 3645078ac79STimur Tabi struct device_node *np = pdev->dev.of_node; 365afae5ad7STimur Tabi struct resource res; 366ec21e2ecSJeff Kirsher struct device_node *tbi; 367ec21e2ecSJeff Kirsher struct fsl_pq_mdio_priv *priv; 368ec21e2ecSJeff Kirsher struct mii_bus *new_bus; 369ec21e2ecSJeff Kirsher int err; 370ec21e2ecSJeff Kirsher 371afae5ad7STimur Tabi dev_dbg(&pdev->dev, "found %s compatible node\n", id->compatible); 372afae5ad7STimur Tabi 373dd3b8a32STimur Tabi new_bus = mdiobus_alloc_size(sizeof(*priv)); 374dd3b8a32STimur Tabi if (!new_bus) 375ec21e2ecSJeff Kirsher return -ENOMEM; 376ec21e2ecSJeff Kirsher 377dd3b8a32STimur Tabi priv = new_bus->priv; 378ec21e2ecSJeff Kirsher new_bus->name = "Freescale PowerQUICC MII Bus", 3795078ac79STimur Tabi new_bus->read = &fsl_pq_mdio_read; 3805078ac79STimur Tabi new_bus->write = &fsl_pq_mdio_write; 3815078ac79STimur Tabi new_bus->reset = &fsl_pq_mdio_reset; 382dd3b8a32STimur Tabi new_bus->irq = priv->irqs; 383ec21e2ecSJeff Kirsher 384afae5ad7STimur Tabi err = of_address_to_resource(np, 0, &res); 385afae5ad7STimur Tabi if (err < 0) { 386afae5ad7STimur Tabi dev_err(&pdev->dev, "could not obtain address information\n"); 387dd3b8a32STimur Tabi goto error; 388ec21e2ecSJeff Kirsher } 389ec21e2ecSJeff Kirsher 39069cfb419STimur Tabi snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s@%llx", np->name, 391afae5ad7STimur Tabi (unsigned long long)res.start); 39269cfb419STimur Tabi 393afae5ad7STimur Tabi priv->map = of_iomap(np, 0); 394afae5ad7STimur Tabi if (!priv->map) { 395ec21e2ecSJeff Kirsher err = -ENOMEM; 396dd3b8a32STimur Tabi goto error; 397ec21e2ecSJeff Kirsher } 398ec21e2ecSJeff Kirsher 399afae5ad7STimur Tabi /* 400afae5ad7STimur Tabi * Some device tree nodes represent only the MII registers, and 401afae5ad7STimur Tabi * others represent the MAC and MII registers. The 'mii_offset' field 402afae5ad7STimur Tabi * contains the offset of the MII registers inside the mapped register 403afae5ad7STimur Tabi * space. 404afae5ad7STimur Tabi */ 405afae5ad7STimur Tabi if (data->mii_offset > resource_size(&res)) { 406afae5ad7STimur Tabi dev_err(&pdev->dev, "invalid register map\n"); 407afae5ad7STimur Tabi err = -EINVAL; 408dd3b8a32STimur Tabi goto error; 409afae5ad7STimur Tabi } 410afae5ad7STimur Tabi priv->regs = priv->map + data->mii_offset; 411ec21e2ecSJeff Kirsher 4125078ac79STimur Tabi new_bus->parent = &pdev->dev; 413a0e18600SLibo Chen platform_set_drvdata(pdev, new_bus); 414ec21e2ecSJeff Kirsher 415afae5ad7STimur Tabi if (data->get_tbipa) { 416ec21e2ecSJeff Kirsher for_each_child_of_node(np, tbi) { 417afae5ad7STimur Tabi if (strcmp(tbi->type, "tbi-phy") == 0) { 418afae5ad7STimur Tabi dev_dbg(&pdev->dev, "found TBI PHY node %s\n", 419afae5ad7STimur Tabi strrchr(tbi->full_name, '/') + 1); 420ec21e2ecSJeff Kirsher break; 421ec21e2ecSJeff Kirsher } 422afae5ad7STimur Tabi } 423ec21e2ecSJeff Kirsher 424ec21e2ecSJeff Kirsher if (tbi) { 425ec21e2ecSJeff Kirsher const u32 *prop = of_get_property(tbi, "reg", NULL); 426afae5ad7STimur Tabi uint32_t __iomem *tbipa; 427ec21e2ecSJeff Kirsher 428afae5ad7STimur Tabi if (!prop) { 429afae5ad7STimur Tabi dev_err(&pdev->dev, 430afae5ad7STimur Tabi "missing 'reg' property in node %s\n", 431afae5ad7STimur Tabi tbi->full_name); 432ec21e2ecSJeff Kirsher err = -EBUSY; 433afae5ad7STimur Tabi goto error; 434afae5ad7STimur Tabi } 435afae5ad7STimur Tabi 436afae5ad7STimur Tabi tbipa = data->get_tbipa(priv->map); 437afae5ad7STimur Tabi 438afae5ad7STimur Tabi out_be32(tbipa, be32_to_cpup(prop)); 439c3e072f8SBaruch Siach } 440464b57daSKenth Eriksson } 441ec21e2ecSJeff Kirsher 442afae5ad7STimur Tabi if (data->ucc_configure) 443afae5ad7STimur Tabi data->ucc_configure(res.start, res.end); 444afae5ad7STimur Tabi 445ec21e2ecSJeff Kirsher err = of_mdiobus_register(new_bus, np); 446ec21e2ecSJeff Kirsher if (err) { 4475078ac79STimur Tabi dev_err(&pdev->dev, "cannot register %s as MDIO bus\n", 448ec21e2ecSJeff Kirsher new_bus->name); 449dd3b8a32STimur Tabi goto error; 450ec21e2ecSJeff Kirsher } 451ec21e2ecSJeff Kirsher 452ec21e2ecSJeff Kirsher return 0; 453ec21e2ecSJeff Kirsher 454dd3b8a32STimur Tabi error: 455dd3b8a32STimur Tabi if (priv->map) 456ec21e2ecSJeff Kirsher iounmap(priv->map); 457dd3b8a32STimur Tabi 458ec21e2ecSJeff Kirsher kfree(new_bus); 459dd3b8a32STimur Tabi 460ec21e2ecSJeff Kirsher return err; 461ec21e2ecSJeff Kirsher } 462ec21e2ecSJeff Kirsher 463ec21e2ecSJeff Kirsher 4645078ac79STimur Tabi static int fsl_pq_mdio_remove(struct platform_device *pdev) 465ec21e2ecSJeff Kirsher { 4665078ac79STimur Tabi struct device *device = &pdev->dev; 467ec21e2ecSJeff Kirsher struct mii_bus *bus = dev_get_drvdata(device); 468ec21e2ecSJeff Kirsher struct fsl_pq_mdio_priv *priv = bus->priv; 469ec21e2ecSJeff Kirsher 470ec21e2ecSJeff Kirsher mdiobus_unregister(bus); 471ec21e2ecSJeff Kirsher 472ec21e2ecSJeff Kirsher iounmap(priv->map); 473ec21e2ecSJeff Kirsher mdiobus_free(bus); 474ec21e2ecSJeff Kirsher 475ec21e2ecSJeff Kirsher return 0; 476ec21e2ecSJeff Kirsher } 477ec21e2ecSJeff Kirsher 478ec21e2ecSJeff Kirsher static struct platform_driver fsl_pq_mdio_driver = { 479ec21e2ecSJeff Kirsher .driver = { 480ec21e2ecSJeff Kirsher .name = "fsl-pq_mdio", 481ec21e2ecSJeff Kirsher .owner = THIS_MODULE, 482ec21e2ecSJeff Kirsher .of_match_table = fsl_pq_mdio_match, 483ec21e2ecSJeff Kirsher }, 484ec21e2ecSJeff Kirsher .probe = fsl_pq_mdio_probe, 485ec21e2ecSJeff Kirsher .remove = fsl_pq_mdio_remove, 486ec21e2ecSJeff Kirsher }; 487ec21e2ecSJeff Kirsher 488db62f684SAxel Lin module_platform_driver(fsl_pq_mdio_driver); 489ec21e2ecSJeff Kirsher 490ec21e2ecSJeff Kirsher MODULE_LICENSE("GPL"); 491