1ec21e2ecSJeff Kirsher /* 2ec21e2ecSJeff Kirsher * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation 3ec21e2ecSJeff Kirsher * Provides Bus interface for MIIM regs 4ec21e2ecSJeff Kirsher * 5ec21e2ecSJeff Kirsher * Author: Andy Fleming <afleming@freescale.com> 6ec21e2ecSJeff Kirsher * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 7ec21e2ecSJeff Kirsher * 8ec21e2ecSJeff Kirsher * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc. 9ec21e2ecSJeff Kirsher * 10ec21e2ecSJeff Kirsher * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips) 11ec21e2ecSJeff Kirsher * 12ec21e2ecSJeff Kirsher * This program is free software; you can redistribute it and/or modify it 13ec21e2ecSJeff Kirsher * under the terms of the GNU General Public License as published by the 14ec21e2ecSJeff Kirsher * Free Software Foundation; either version 2 of the License, or (at your 15ec21e2ecSJeff Kirsher * option) any later version. 16ec21e2ecSJeff Kirsher * 17ec21e2ecSJeff Kirsher */ 18ec21e2ecSJeff Kirsher 19ec21e2ecSJeff Kirsher #include <linux/kernel.h> 20ec21e2ecSJeff Kirsher #include <linux/string.h> 21ec21e2ecSJeff Kirsher #include <linux/errno.h> 22ec21e2ecSJeff Kirsher #include <linux/slab.h> 23ec21e2ecSJeff Kirsher #include <linux/init.h> 24ec21e2ecSJeff Kirsher #include <linux/delay.h> 25ec21e2ecSJeff Kirsher #include <linux/module.h> 26ec21e2ecSJeff Kirsher #include <linux/mii.h> 27ec21e2ecSJeff Kirsher #include <linux/of_address.h> 28ec21e2ecSJeff Kirsher #include <linux/of_mdio.h> 29afae5ad7STimur Tabi #include <linux/of_device.h> 30ec21e2ecSJeff Kirsher 31ec21e2ecSJeff Kirsher #include <asm/io.h> 321aa06d42STimur Tabi #include <asm/ucc.h> /* for ucc_set_qe_mux_mii_mng() */ 33ec21e2ecSJeff Kirsher 34ec21e2ecSJeff Kirsher #include "gianfar.h" 3519bcd6c6STimur Tabi 3619bcd6c6STimur Tabi #define MIIMIND_BUSY 0x00000001 3719bcd6c6STimur Tabi #define MIIMIND_NOTVALID 0x00000004 3819bcd6c6STimur Tabi #define MIIMCFG_INIT_VALUE 0x00000007 3919bcd6c6STimur Tabi #define MIIMCFG_RESET 0x80000000 4019bcd6c6STimur Tabi 4119bcd6c6STimur Tabi #define MII_READ_COMMAND 0x00000001 4219bcd6c6STimur Tabi 43afae5ad7STimur Tabi struct fsl_pq_mii { 44afae5ad7STimur Tabi u32 miimcfg; /* MII management configuration reg */ 45afae5ad7STimur Tabi u32 miimcom; /* MII management command reg */ 46afae5ad7STimur Tabi u32 miimadd; /* MII management address reg */ 47afae5ad7STimur Tabi u32 miimcon; /* MII management control reg */ 48afae5ad7STimur Tabi u32 miimstat; /* MII management status reg */ 49afae5ad7STimur Tabi u32 miimind; /* MII management indication reg */ 50afae5ad7STimur Tabi }; 51afae5ad7STimur Tabi 5219bcd6c6STimur Tabi struct fsl_pq_mdio { 5319bcd6c6STimur Tabi u8 res1[16]; 5419bcd6c6STimur Tabi u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/ 5519bcd6c6STimur Tabi u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/ 5619bcd6c6STimur Tabi u8 res2[4]; 5719bcd6c6STimur Tabi u32 emapm; /* MDIO Event mapping register (for etsec2)*/ 5819bcd6c6STimur Tabi u8 res3[1280]; 59afae5ad7STimur Tabi struct fsl_pq_mii mii; 6019bcd6c6STimur Tabi u8 res4[28]; 6119bcd6c6STimur Tabi u32 utbipar; /* TBI phy address reg (only on UCC) */ 6219bcd6c6STimur Tabi u8 res5[2728]; 6319bcd6c6STimur Tabi } __packed; 64ec21e2ecSJeff Kirsher 6559399c59STimur Tabi /* Number of microseconds to wait for an MII register to respond */ 6659399c59STimur Tabi #define MII_TIMEOUT 1000 6759399c59STimur Tabi 68ec21e2ecSJeff Kirsher struct fsl_pq_mdio_priv { 69ec21e2ecSJeff Kirsher void __iomem *map; 70afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs; 71dd3b8a32STimur Tabi int irqs[PHY_MAX_ADDR]; 72afae5ad7STimur Tabi }; 73afae5ad7STimur Tabi 74afae5ad7STimur Tabi /* 75afae5ad7STimur Tabi * Per-device-type data. Each type of device tree node that we support gets 76afae5ad7STimur Tabi * one of these. 77afae5ad7STimur Tabi * 78afae5ad7STimur Tabi * @mii_offset: the offset of the MII registers within the memory map of the 79afae5ad7STimur Tabi * node. Some nodes define only the MII registers, and some define the whole 80afae5ad7STimur Tabi * MAC (which includes the MII registers). 81afae5ad7STimur Tabi * 82afae5ad7STimur Tabi * @get_tbipa: determines the address of the TBIPA register 83afae5ad7STimur Tabi * 84afae5ad7STimur Tabi * @ucc_configure: a special function for extra QE configuration 85afae5ad7STimur Tabi */ 86afae5ad7STimur Tabi struct fsl_pq_mdio_data { 87afae5ad7STimur Tabi unsigned int mii_offset; /* offset of the MII registers */ 88afae5ad7STimur Tabi uint32_t __iomem * (*get_tbipa)(void __iomem *p); 89afae5ad7STimur Tabi void (*ucc_configure)(phys_addr_t start, phys_addr_t end); 90ec21e2ecSJeff Kirsher }; 91ec21e2ecSJeff Kirsher 92ec21e2ecSJeff Kirsher /* 9369cfb419STimur Tabi * Write value to the PHY at mii_id at register regnum, on the bus attached 9469cfb419STimur Tabi * to the local interface, which may be different from the generic mdio bus 9569cfb419STimur Tabi * (tied to a single interface), waiting until the write is done before 9669cfb419STimur Tabi * returning. This is helpful in programming interfaces like the TBI which 9769cfb419STimur Tabi * control interfaces like onchip SERDES and are always tied to the local 9869cfb419STimur Tabi * mdio pins, which may not be the same as system mdio bus, used for 99ec21e2ecSJeff Kirsher * controlling the external PHYs, for example. 100ec21e2ecSJeff Kirsher */ 10169cfb419STimur Tabi static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 10269cfb419STimur Tabi u16 value) 103ec21e2ecSJeff Kirsher { 10469cfb419STimur Tabi struct fsl_pq_mdio_priv *priv = bus->priv; 105afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs = priv->regs; 10659399c59STimur Tabi u32 status; 10759399c59STimur Tabi 108ec21e2ecSJeff Kirsher /* Set the PHY address and the register address we want to write */ 109ec21e2ecSJeff Kirsher out_be32(®s->miimadd, (mii_id << 8) | regnum); 110ec21e2ecSJeff Kirsher 111ec21e2ecSJeff Kirsher /* Write out the value we want */ 112ec21e2ecSJeff Kirsher out_be32(®s->miimcon, value); 113ec21e2ecSJeff Kirsher 114ec21e2ecSJeff Kirsher /* Wait for the transaction to finish */ 11559399c59STimur Tabi status = spin_event_timeout(!(in_be32(®s->miimind) & MIIMIND_BUSY), 11659399c59STimur Tabi MII_TIMEOUT, 0); 117ec21e2ecSJeff Kirsher 11859399c59STimur Tabi return status ? 0 : -ETIMEDOUT; 119ec21e2ecSJeff Kirsher } 120ec21e2ecSJeff Kirsher 121ec21e2ecSJeff Kirsher /* 12269cfb419STimur Tabi * Read the bus for PHY at addr mii_id, register regnum, and return the value. 12369cfb419STimur Tabi * Clears miimcom first. 12469cfb419STimur Tabi * 12569cfb419STimur Tabi * All PHY operation done on the bus attached to the local interface, which 12669cfb419STimur Tabi * may be different from the generic mdio bus. This is helpful in programming 12769cfb419STimur Tabi * interfaces like the TBI which, in turn, control interfaces like on-chip 12869cfb419STimur Tabi * SERDES and are always tied to the local mdio pins, which may not be the 129ec21e2ecSJeff Kirsher * same as system mdio bus, used for controlling the external PHYs, for eg. 130ec21e2ecSJeff Kirsher */ 13169cfb419STimur Tabi static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 132ec21e2ecSJeff Kirsher { 13369cfb419STimur Tabi struct fsl_pq_mdio_priv *priv = bus->priv; 134afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs = priv->regs; 13559399c59STimur Tabi u32 status; 13669cfb419STimur Tabi u16 value; 137ec21e2ecSJeff Kirsher 138ec21e2ecSJeff Kirsher /* Set the PHY address and the register address we want to read */ 139ec21e2ecSJeff Kirsher out_be32(®s->miimadd, (mii_id << 8) | regnum); 140ec21e2ecSJeff Kirsher 141ec21e2ecSJeff Kirsher /* Clear miimcom, and then initiate a read */ 142ec21e2ecSJeff Kirsher out_be32(®s->miimcom, 0); 143ec21e2ecSJeff Kirsher out_be32(®s->miimcom, MII_READ_COMMAND); 144ec21e2ecSJeff Kirsher 14559399c59STimur Tabi /* Wait for the transaction to finish, normally less than 100us */ 14659399c59STimur Tabi status = spin_event_timeout(!(in_be32(®s->miimind) & 14759399c59STimur Tabi (MIIMIND_NOTVALID | MIIMIND_BUSY)), 14859399c59STimur Tabi MII_TIMEOUT, 0); 14959399c59STimur Tabi if (!status) 15059399c59STimur Tabi return -ETIMEDOUT; 151ec21e2ecSJeff Kirsher 152ec21e2ecSJeff Kirsher /* Grab the value of the register from miimstat */ 153ec21e2ecSJeff Kirsher value = in_be32(®s->miimstat); 154ec21e2ecSJeff Kirsher 155afae5ad7STimur Tabi dev_dbg(&bus->dev, "read %04x from address %x/%x\n", value, mii_id, regnum); 156ec21e2ecSJeff Kirsher return value; 157ec21e2ecSJeff Kirsher } 158ec21e2ecSJeff Kirsher 159ec21e2ecSJeff Kirsher /* Reset the MIIM registers, and wait for the bus to free */ 160ec21e2ecSJeff Kirsher static int fsl_pq_mdio_reset(struct mii_bus *bus) 161ec21e2ecSJeff Kirsher { 16269cfb419STimur Tabi struct fsl_pq_mdio_priv *priv = bus->priv; 163afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs = priv->regs; 16459399c59STimur Tabi u32 status; 165ec21e2ecSJeff Kirsher 166ec21e2ecSJeff Kirsher mutex_lock(&bus->mdio_lock); 167ec21e2ecSJeff Kirsher 168ec21e2ecSJeff Kirsher /* Reset the management interface */ 169ec21e2ecSJeff Kirsher out_be32(®s->miimcfg, MIIMCFG_RESET); 170ec21e2ecSJeff Kirsher 171ec21e2ecSJeff Kirsher /* Setup the MII Mgmt clock speed */ 172ec21e2ecSJeff Kirsher out_be32(®s->miimcfg, MIIMCFG_INIT_VALUE); 173ec21e2ecSJeff Kirsher 174ec21e2ecSJeff Kirsher /* Wait until the bus is free */ 17559399c59STimur Tabi status = spin_event_timeout(!(in_be32(®s->miimind) & MIIMIND_BUSY), 17659399c59STimur Tabi MII_TIMEOUT, 0); 177ec21e2ecSJeff Kirsher 178ec21e2ecSJeff Kirsher mutex_unlock(&bus->mdio_lock); 179ec21e2ecSJeff Kirsher 18059399c59STimur Tabi if (!status) { 1815078ac79STimur Tabi dev_err(&bus->dev, "timeout waiting for MII bus\n"); 182ec21e2ecSJeff Kirsher return -EBUSY; 183ec21e2ecSJeff Kirsher } 184ec21e2ecSJeff Kirsher 185ec21e2ecSJeff Kirsher return 0; 186ec21e2ecSJeff Kirsher } 187ec21e2ecSJeff Kirsher 188952c5ca1SAndy Fleming #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE) 189ec21e2ecSJeff Kirsher /* 190ec21e2ecSJeff Kirsher * This is mildly evil, but so is our hardware for doing this. 191ec21e2ecSJeff Kirsher * Also, we have to cast back to struct gfar because of 192ec21e2ecSJeff Kirsher * definition weirdness done in gianfar.h. 193ec21e2ecSJeff Kirsher */ 194afae5ad7STimur Tabi static uint32_t __iomem *get_gfar_tbipa(void __iomem *p) 195afae5ad7STimur Tabi { 196afae5ad7STimur Tabi struct gfar __iomem *enet_regs = p; 197afae5ad7STimur Tabi 198ec21e2ecSJeff Kirsher return &enet_regs->tbipa; 199afae5ad7STimur Tabi } 200afae5ad7STimur Tabi 201afae5ad7STimur Tabi /* 202afae5ad7STimur Tabi * Return the TBIPAR address for an eTSEC2 node 203afae5ad7STimur Tabi */ 204afae5ad7STimur Tabi static uint32_t __iomem *get_etsec_tbipa(void __iomem *p) 205afae5ad7STimur Tabi { 206afae5ad7STimur Tabi return p; 207ec21e2ecSJeff Kirsher } 208ec21e2ecSJeff Kirsher #endif 209afae5ad7STimur Tabi 210afae5ad7STimur Tabi #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE) 211afae5ad7STimur Tabi /* 212afae5ad7STimur Tabi * Return the TBIPAR address for a QE MDIO node 213afae5ad7STimur Tabi */ 214afae5ad7STimur Tabi static uint32_t __iomem *get_ucc_tbipa(void __iomem *p) 215afae5ad7STimur Tabi { 216afae5ad7STimur Tabi struct fsl_pq_mdio __iomem *mdio = p; 217afae5ad7STimur Tabi 218afae5ad7STimur Tabi return &mdio->utbipar; 219952c5ca1SAndy Fleming } 220ec21e2ecSJeff Kirsher 221afae5ad7STimur Tabi /* 222afae5ad7STimur Tabi * Find the UCC node that controls the given MDIO node 223afae5ad7STimur Tabi * 224afae5ad7STimur Tabi * For some reason, the QE MDIO nodes are not children of the UCC devices 225afae5ad7STimur Tabi * that control them. Therefore, we need to scan all UCC nodes looking for 226afae5ad7STimur Tabi * the one that encompases the given MDIO node. We do this by comparing 227afae5ad7STimur Tabi * physical addresses. The 'start' and 'end' addresses of the MDIO node are 228afae5ad7STimur Tabi * passed, and the correct UCC node will cover the entire address range. 229afae5ad7STimur Tabi * 230afae5ad7STimur Tabi * This assumes that there is only one QE MDIO node in the entire device tree. 231afae5ad7STimur Tabi */ 232afae5ad7STimur Tabi static void ucc_configure(phys_addr_t start, phys_addr_t end) 233ec21e2ecSJeff Kirsher { 234afae5ad7STimur Tabi static bool found_mii_master; 235ec21e2ecSJeff Kirsher struct device_node *np = NULL; 236afae5ad7STimur Tabi 237afae5ad7STimur Tabi if (found_mii_master) 238afae5ad7STimur Tabi return; 239ec21e2ecSJeff Kirsher 240ec21e2ecSJeff Kirsher for_each_compatible_node(np, NULL, "ucc_geth") { 241afae5ad7STimur Tabi struct resource res; 242afae5ad7STimur Tabi const uint32_t *iprop; 243afae5ad7STimur Tabi uint32_t id; 244afae5ad7STimur Tabi int ret; 245ec21e2ecSJeff Kirsher 246afae5ad7STimur Tabi ret = of_address_to_resource(np, 0, &res); 247afae5ad7STimur Tabi if (ret < 0) { 248afae5ad7STimur Tabi pr_debug("fsl-pq-mdio: no address range in node %s\n", 249afae5ad7STimur Tabi np->full_name); 250ec21e2ecSJeff Kirsher continue; 251afae5ad7STimur Tabi } 252ec21e2ecSJeff Kirsher 253ec21e2ecSJeff Kirsher /* if our mdio regs fall within this UCC regs range */ 254afae5ad7STimur Tabi if ((start < res.start) || (end > res.end)) 255afae5ad7STimur Tabi continue; 256ec21e2ecSJeff Kirsher 257afae5ad7STimur Tabi iprop = of_get_property(np, "cell-index", NULL); 258afae5ad7STimur Tabi if (!iprop) { 259afae5ad7STimur Tabi iprop = of_get_property(np, "device-id", NULL); 260afae5ad7STimur Tabi if (!iprop) { 261afae5ad7STimur Tabi pr_debug("fsl-pq-mdio: no UCC ID in node %s\n", 262afae5ad7STimur Tabi np->full_name); 263afae5ad7STimur Tabi continue; 264afae5ad7STimur Tabi } 265afae5ad7STimur Tabi } 266afae5ad7STimur Tabi 267afae5ad7STimur Tabi id = be32_to_cpup(iprop); 268afae5ad7STimur Tabi 269afae5ad7STimur Tabi /* 270afae5ad7STimur Tabi * cell-index and device-id for QE nodes are 271afae5ad7STimur Tabi * numbered from 1, not 0. 272afae5ad7STimur Tabi */ 273afae5ad7STimur Tabi if (ucc_set_qe_mux_mii_mng(id - 1) < 0) { 274afae5ad7STimur Tabi pr_debug("fsl-pq-mdio: invalid UCC ID in node %s\n", 275afae5ad7STimur Tabi np->full_name); 276ec21e2ecSJeff Kirsher continue; 277ec21e2ecSJeff Kirsher } 278ec21e2ecSJeff Kirsher 279afae5ad7STimur Tabi pr_debug("fsl-pq-mdio: setting node UCC%u to MII master\n", id); 280afae5ad7STimur Tabi found_mii_master = true; 281ec21e2ecSJeff Kirsher } 282ec21e2ecSJeff Kirsher } 283ec21e2ecSJeff Kirsher 284ec21e2ecSJeff Kirsher #endif 285afae5ad7STimur Tabi 286afae5ad7STimur Tabi static struct of_device_id fsl_pq_mdio_match[] = { 287afae5ad7STimur Tabi #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE) 288afae5ad7STimur Tabi { 289afae5ad7STimur Tabi .compatible = "fsl,gianfar-tbi", 290afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 291afae5ad7STimur Tabi .mii_offset = 0, 292afae5ad7STimur Tabi .get_tbipa = get_gfar_tbipa, 293afae5ad7STimur Tabi }, 294afae5ad7STimur Tabi }, 295afae5ad7STimur Tabi { 296afae5ad7STimur Tabi .compatible = "fsl,gianfar-mdio", 297afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 298afae5ad7STimur Tabi .mii_offset = 0, 299afae5ad7STimur Tabi .get_tbipa = get_gfar_tbipa, 300afae5ad7STimur Tabi }, 301afae5ad7STimur Tabi }, 302afae5ad7STimur Tabi { 303afae5ad7STimur Tabi .type = "mdio", 304afae5ad7STimur Tabi .compatible = "gianfar", 305afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 306afae5ad7STimur Tabi .mii_offset = offsetof(struct fsl_pq_mdio, mii), 307afae5ad7STimur Tabi .get_tbipa = get_gfar_tbipa, 308afae5ad7STimur Tabi }, 309afae5ad7STimur Tabi }, 310afae5ad7STimur Tabi { 311afae5ad7STimur Tabi .compatible = "fsl,etsec2-tbi", 312afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 313afae5ad7STimur Tabi .mii_offset = offsetof(struct fsl_pq_mdio, mii), 314afae5ad7STimur Tabi .get_tbipa = get_etsec_tbipa, 315afae5ad7STimur Tabi }, 316afae5ad7STimur Tabi }, 317afae5ad7STimur Tabi { 318afae5ad7STimur Tabi .compatible = "fsl,etsec2-mdio", 319afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 320afae5ad7STimur Tabi .mii_offset = offsetof(struct fsl_pq_mdio, mii), 321afae5ad7STimur Tabi .get_tbipa = get_etsec_tbipa, 322afae5ad7STimur Tabi }, 323afae5ad7STimur Tabi }, 324afae5ad7STimur Tabi #endif 325afae5ad7STimur Tabi #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE) 326afae5ad7STimur Tabi { 327afae5ad7STimur Tabi .compatible = "fsl,ucc-mdio", 328afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 329afae5ad7STimur Tabi .mii_offset = 0, 330afae5ad7STimur Tabi .get_tbipa = get_ucc_tbipa, 331afae5ad7STimur Tabi .ucc_configure = ucc_configure, 332afae5ad7STimur Tabi }, 333afae5ad7STimur Tabi }, 334afae5ad7STimur Tabi { 335afae5ad7STimur Tabi /* Legacy UCC MDIO node */ 336afae5ad7STimur Tabi .type = "mdio", 337afae5ad7STimur Tabi .compatible = "ucc_geth_phy", 338afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 339afae5ad7STimur Tabi .mii_offset = 0, 340afae5ad7STimur Tabi .get_tbipa = get_ucc_tbipa, 341afae5ad7STimur Tabi .ucc_configure = ucc_configure, 342afae5ad7STimur Tabi }, 343afae5ad7STimur Tabi }, 344afae5ad7STimur Tabi #endif 345761743ebSTimur Tabi /* No Kconfig option for Fman support yet */ 346761743ebSTimur Tabi { 347761743ebSTimur Tabi .compatible = "fsl,fman-mdio", 348761743ebSTimur Tabi .data = &(struct fsl_pq_mdio_data) { 349761743ebSTimur Tabi .mii_offset = 0, 350761743ebSTimur Tabi /* Fman TBI operations are handled elsewhere */ 351761743ebSTimur Tabi }, 352761743ebSTimur Tabi }, 353761743ebSTimur Tabi 354afae5ad7STimur Tabi {}, 355afae5ad7STimur Tabi }; 356afae5ad7STimur Tabi MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match); 357ec21e2ecSJeff Kirsher 3585078ac79STimur Tabi static int fsl_pq_mdio_probe(struct platform_device *pdev) 359ec21e2ecSJeff Kirsher { 360afae5ad7STimur Tabi const struct of_device_id *id = 361afae5ad7STimur Tabi of_match_device(fsl_pq_mdio_match, &pdev->dev); 362afae5ad7STimur Tabi const struct fsl_pq_mdio_data *data = id->data; 3635078ac79STimur Tabi struct device_node *np = pdev->dev.of_node; 364afae5ad7STimur Tabi struct resource res; 365ec21e2ecSJeff Kirsher struct device_node *tbi; 366ec21e2ecSJeff Kirsher struct fsl_pq_mdio_priv *priv; 367ec21e2ecSJeff Kirsher struct mii_bus *new_bus; 368ec21e2ecSJeff Kirsher int err; 369ec21e2ecSJeff Kirsher 370afae5ad7STimur Tabi dev_dbg(&pdev->dev, "found %s compatible node\n", id->compatible); 371afae5ad7STimur Tabi 372dd3b8a32STimur Tabi new_bus = mdiobus_alloc_size(sizeof(*priv)); 373dd3b8a32STimur Tabi if (!new_bus) 374ec21e2ecSJeff Kirsher return -ENOMEM; 375ec21e2ecSJeff Kirsher 376dd3b8a32STimur Tabi priv = new_bus->priv; 377ec21e2ecSJeff Kirsher new_bus->name = "Freescale PowerQUICC MII Bus", 3785078ac79STimur Tabi new_bus->read = &fsl_pq_mdio_read; 3795078ac79STimur Tabi new_bus->write = &fsl_pq_mdio_write; 3805078ac79STimur Tabi new_bus->reset = &fsl_pq_mdio_reset; 381dd3b8a32STimur Tabi new_bus->irq = priv->irqs; 382ec21e2ecSJeff Kirsher 383afae5ad7STimur Tabi err = of_address_to_resource(np, 0, &res); 384afae5ad7STimur Tabi if (err < 0) { 385afae5ad7STimur Tabi dev_err(&pdev->dev, "could not obtain address information\n"); 386dd3b8a32STimur Tabi goto error; 387ec21e2ecSJeff Kirsher } 388ec21e2ecSJeff Kirsher 38969cfb419STimur Tabi snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s@%llx", np->name, 390afae5ad7STimur Tabi (unsigned long long)res.start); 39169cfb419STimur Tabi 392afae5ad7STimur Tabi priv->map = of_iomap(np, 0); 393afae5ad7STimur Tabi if (!priv->map) { 394ec21e2ecSJeff Kirsher err = -ENOMEM; 395dd3b8a32STimur Tabi goto error; 396ec21e2ecSJeff Kirsher } 397ec21e2ecSJeff Kirsher 398afae5ad7STimur Tabi /* 399afae5ad7STimur Tabi * Some device tree nodes represent only the MII registers, and 400afae5ad7STimur Tabi * others represent the MAC and MII registers. The 'mii_offset' field 401afae5ad7STimur Tabi * contains the offset of the MII registers inside the mapped register 402afae5ad7STimur Tabi * space. 403afae5ad7STimur Tabi */ 404afae5ad7STimur Tabi if (data->mii_offset > resource_size(&res)) { 405afae5ad7STimur Tabi dev_err(&pdev->dev, "invalid register map\n"); 406afae5ad7STimur Tabi err = -EINVAL; 407dd3b8a32STimur Tabi goto error; 408afae5ad7STimur Tabi } 409afae5ad7STimur Tabi priv->regs = priv->map + data->mii_offset; 410ec21e2ecSJeff Kirsher 4115078ac79STimur Tabi new_bus->parent = &pdev->dev; 4125078ac79STimur Tabi dev_set_drvdata(&pdev->dev, new_bus); 413ec21e2ecSJeff Kirsher 414afae5ad7STimur Tabi if (data->get_tbipa) { 415ec21e2ecSJeff Kirsher for_each_child_of_node(np, tbi) { 416afae5ad7STimur Tabi if (strcmp(tbi->type, "tbi-phy") == 0) { 417afae5ad7STimur Tabi dev_dbg(&pdev->dev, "found TBI PHY node %s\n", 418afae5ad7STimur Tabi strrchr(tbi->full_name, '/') + 1); 419ec21e2ecSJeff Kirsher break; 420ec21e2ecSJeff Kirsher } 421afae5ad7STimur Tabi } 422ec21e2ecSJeff Kirsher 423ec21e2ecSJeff Kirsher if (tbi) { 424ec21e2ecSJeff Kirsher const u32 *prop = of_get_property(tbi, "reg", NULL); 425afae5ad7STimur Tabi uint32_t __iomem *tbipa; 426ec21e2ecSJeff Kirsher 427afae5ad7STimur Tabi if (!prop) { 428afae5ad7STimur Tabi dev_err(&pdev->dev, 429afae5ad7STimur Tabi "missing 'reg' property in node %s\n", 430afae5ad7STimur Tabi tbi->full_name); 431ec21e2ecSJeff Kirsher err = -EBUSY; 432afae5ad7STimur Tabi goto error; 433afae5ad7STimur Tabi } 434afae5ad7STimur Tabi 435afae5ad7STimur Tabi tbipa = data->get_tbipa(priv->map); 436afae5ad7STimur Tabi 437afae5ad7STimur Tabi out_be32(tbipa, be32_to_cpup(prop)); 438c3e072f8SBaruch Siach } 439464b57daSKenth Eriksson } 440ec21e2ecSJeff Kirsher 441afae5ad7STimur Tabi if (data->ucc_configure) 442afae5ad7STimur Tabi data->ucc_configure(res.start, res.end); 443afae5ad7STimur Tabi 444ec21e2ecSJeff Kirsher err = of_mdiobus_register(new_bus, np); 445ec21e2ecSJeff Kirsher if (err) { 4465078ac79STimur Tabi dev_err(&pdev->dev, "cannot register %s as MDIO bus\n", 447ec21e2ecSJeff Kirsher new_bus->name); 448dd3b8a32STimur Tabi goto error; 449ec21e2ecSJeff Kirsher } 450ec21e2ecSJeff Kirsher 451ec21e2ecSJeff Kirsher return 0; 452ec21e2ecSJeff Kirsher 453dd3b8a32STimur Tabi error: 454dd3b8a32STimur Tabi if (priv->map) 455ec21e2ecSJeff Kirsher iounmap(priv->map); 456dd3b8a32STimur Tabi 457ec21e2ecSJeff Kirsher kfree(new_bus); 458dd3b8a32STimur Tabi 459ec21e2ecSJeff Kirsher return err; 460ec21e2ecSJeff Kirsher } 461ec21e2ecSJeff Kirsher 462ec21e2ecSJeff Kirsher 4635078ac79STimur Tabi static int fsl_pq_mdio_remove(struct platform_device *pdev) 464ec21e2ecSJeff Kirsher { 4655078ac79STimur Tabi struct device *device = &pdev->dev; 466ec21e2ecSJeff Kirsher struct mii_bus *bus = dev_get_drvdata(device); 467ec21e2ecSJeff Kirsher struct fsl_pq_mdio_priv *priv = bus->priv; 468ec21e2ecSJeff Kirsher 469ec21e2ecSJeff Kirsher mdiobus_unregister(bus); 470ec21e2ecSJeff Kirsher 471ec21e2ecSJeff Kirsher dev_set_drvdata(device, NULL); 472ec21e2ecSJeff Kirsher 473ec21e2ecSJeff Kirsher iounmap(priv->map); 474ec21e2ecSJeff Kirsher mdiobus_free(bus); 475ec21e2ecSJeff Kirsher 476ec21e2ecSJeff Kirsher return 0; 477ec21e2ecSJeff Kirsher } 478ec21e2ecSJeff Kirsher 479ec21e2ecSJeff Kirsher static struct platform_driver fsl_pq_mdio_driver = { 480ec21e2ecSJeff Kirsher .driver = { 481ec21e2ecSJeff Kirsher .name = "fsl-pq_mdio", 482ec21e2ecSJeff Kirsher .owner = THIS_MODULE, 483ec21e2ecSJeff Kirsher .of_match_table = fsl_pq_mdio_match, 484ec21e2ecSJeff Kirsher }, 485ec21e2ecSJeff Kirsher .probe = fsl_pq_mdio_probe, 486ec21e2ecSJeff Kirsher .remove = fsl_pq_mdio_remove, 487ec21e2ecSJeff Kirsher }; 488ec21e2ecSJeff Kirsher 489db62f684SAxel Lin module_platform_driver(fsl_pq_mdio_driver); 490ec21e2ecSJeff Kirsher 491ec21e2ecSJeff Kirsher MODULE_LICENSE("GPL"); 492