1ec21e2ecSJeff Kirsher /* 2ec21e2ecSJeff Kirsher * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation 3ec21e2ecSJeff Kirsher * Provides Bus interface for MIIM regs 4ec21e2ecSJeff Kirsher * 5ec21e2ecSJeff Kirsher * Author: Andy Fleming <afleming@freescale.com> 6ec21e2ecSJeff Kirsher * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 7ec21e2ecSJeff Kirsher * 8ec21e2ecSJeff Kirsher * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc. 9ec21e2ecSJeff Kirsher * 10ec21e2ecSJeff Kirsher * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips) 11ec21e2ecSJeff Kirsher * 12ec21e2ecSJeff Kirsher * This program is free software; you can redistribute it and/or modify it 13ec21e2ecSJeff Kirsher * under the terms of the GNU General Public License as published by the 14ec21e2ecSJeff Kirsher * Free Software Foundation; either version 2 of the License, or (at your 15ec21e2ecSJeff Kirsher * option) any later version. 16ec21e2ecSJeff Kirsher * 17ec21e2ecSJeff Kirsher */ 18ec21e2ecSJeff Kirsher 19ec21e2ecSJeff Kirsher #include <linux/kernel.h> 20ec21e2ecSJeff Kirsher #include <linux/string.h> 21ec21e2ecSJeff Kirsher #include <linux/errno.h> 22ec21e2ecSJeff Kirsher #include <linux/slab.h> 23ec21e2ecSJeff Kirsher #include <linux/init.h> 24ec21e2ecSJeff Kirsher #include <linux/delay.h> 25ec21e2ecSJeff Kirsher #include <linux/module.h> 26ec21e2ecSJeff Kirsher #include <linux/platform_device.h> 27ec21e2ecSJeff Kirsher #include <linux/mii.h> 28ec21e2ecSJeff Kirsher #include <linux/of_address.h> 29ec21e2ecSJeff Kirsher #include <linux/of_mdio.h> 30ec21e2ecSJeff Kirsher #include <linux/of_platform.h> 31ec21e2ecSJeff Kirsher 32ec21e2ecSJeff Kirsher #include <asm/io.h> 331aa06d42STimur Tabi #include <asm/ucc.h> /* for ucc_set_qe_mux_mii_mng() */ 34ec21e2ecSJeff Kirsher 35ec21e2ecSJeff Kirsher #include "gianfar.h" 3619bcd6c6STimur Tabi 3719bcd6c6STimur Tabi #define MIIMIND_BUSY 0x00000001 3819bcd6c6STimur Tabi #define MIIMIND_NOTVALID 0x00000004 3919bcd6c6STimur Tabi #define MIIMCFG_INIT_VALUE 0x00000007 4019bcd6c6STimur Tabi #define MIIMCFG_RESET 0x80000000 4119bcd6c6STimur Tabi 4219bcd6c6STimur Tabi #define MII_READ_COMMAND 0x00000001 4319bcd6c6STimur Tabi 4419bcd6c6STimur Tabi struct fsl_pq_mdio { 4519bcd6c6STimur Tabi u8 res1[16]; 4619bcd6c6STimur Tabi u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/ 4719bcd6c6STimur Tabi u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/ 4819bcd6c6STimur Tabi u8 res2[4]; 4919bcd6c6STimur Tabi u32 emapm; /* MDIO Event mapping register (for etsec2)*/ 5019bcd6c6STimur Tabi u8 res3[1280]; 5119bcd6c6STimur Tabi u32 miimcfg; /* MII management configuration reg */ 5219bcd6c6STimur Tabi u32 miimcom; /* MII management command reg */ 5319bcd6c6STimur Tabi u32 miimadd; /* MII management address reg */ 5419bcd6c6STimur Tabi u32 miimcon; /* MII management control reg */ 5519bcd6c6STimur Tabi u32 miimstat; /* MII management status reg */ 5619bcd6c6STimur Tabi u32 miimind; /* MII management indication reg */ 5719bcd6c6STimur Tabi u8 res4[28]; 5819bcd6c6STimur Tabi u32 utbipar; /* TBI phy address reg (only on UCC) */ 5919bcd6c6STimur Tabi u8 res5[2728]; 6019bcd6c6STimur Tabi } __packed; 61ec21e2ecSJeff Kirsher 6259399c59STimur Tabi /* Number of microseconds to wait for an MII register to respond */ 6359399c59STimur Tabi #define MII_TIMEOUT 1000 6459399c59STimur Tabi 65ec21e2ecSJeff Kirsher struct fsl_pq_mdio_priv { 66ec21e2ecSJeff Kirsher void __iomem *map; 67ec21e2ecSJeff Kirsher struct fsl_pq_mdio __iomem *regs; 68ec21e2ecSJeff Kirsher }; 69ec21e2ecSJeff Kirsher 70ec21e2ecSJeff Kirsher /* 7169cfb419STimur Tabi * Write value to the PHY at mii_id at register regnum, on the bus attached 7269cfb419STimur Tabi * to the local interface, which may be different from the generic mdio bus 7369cfb419STimur Tabi * (tied to a single interface), waiting until the write is done before 7469cfb419STimur Tabi * returning. This is helpful in programming interfaces like the TBI which 7569cfb419STimur Tabi * control interfaces like onchip SERDES and are always tied to the local 7669cfb419STimur Tabi * mdio pins, which may not be the same as system mdio bus, used for 77ec21e2ecSJeff Kirsher * controlling the external PHYs, for example. 78ec21e2ecSJeff Kirsher */ 7969cfb419STimur Tabi static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 8069cfb419STimur Tabi u16 value) 81ec21e2ecSJeff Kirsher { 8269cfb419STimur Tabi struct fsl_pq_mdio_priv *priv = bus->priv; 8369cfb419STimur Tabi struct fsl_pq_mdio __iomem *regs = priv->regs; 8459399c59STimur Tabi u32 status; 8559399c59STimur Tabi 86ec21e2ecSJeff Kirsher /* Set the PHY address and the register address we want to write */ 87ec21e2ecSJeff Kirsher out_be32(®s->miimadd, (mii_id << 8) | regnum); 88ec21e2ecSJeff Kirsher 89ec21e2ecSJeff Kirsher /* Write out the value we want */ 90ec21e2ecSJeff Kirsher out_be32(®s->miimcon, value); 91ec21e2ecSJeff Kirsher 92ec21e2ecSJeff Kirsher /* Wait for the transaction to finish */ 9359399c59STimur Tabi status = spin_event_timeout(!(in_be32(®s->miimind) & MIIMIND_BUSY), 9459399c59STimur Tabi MII_TIMEOUT, 0); 95ec21e2ecSJeff Kirsher 9659399c59STimur Tabi return status ? 0 : -ETIMEDOUT; 97ec21e2ecSJeff Kirsher } 98ec21e2ecSJeff Kirsher 99ec21e2ecSJeff Kirsher /* 10069cfb419STimur Tabi * Read the bus for PHY at addr mii_id, register regnum, and return the value. 10169cfb419STimur Tabi * Clears miimcom first. 10269cfb419STimur Tabi * 10369cfb419STimur Tabi * All PHY operation done on the bus attached to the local interface, which 10469cfb419STimur Tabi * may be different from the generic mdio bus. This is helpful in programming 10569cfb419STimur Tabi * interfaces like the TBI which, in turn, control interfaces like on-chip 10669cfb419STimur Tabi * SERDES and are always tied to the local mdio pins, which may not be the 107ec21e2ecSJeff Kirsher * same as system mdio bus, used for controlling the external PHYs, for eg. 108ec21e2ecSJeff Kirsher */ 10969cfb419STimur Tabi static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 110ec21e2ecSJeff Kirsher { 11169cfb419STimur Tabi struct fsl_pq_mdio_priv *priv = bus->priv; 11269cfb419STimur Tabi struct fsl_pq_mdio __iomem *regs = priv->regs; 11359399c59STimur Tabi u32 status; 11469cfb419STimur Tabi u16 value; 115ec21e2ecSJeff Kirsher 116ec21e2ecSJeff Kirsher /* Set the PHY address and the register address we want to read */ 117ec21e2ecSJeff Kirsher out_be32(®s->miimadd, (mii_id << 8) | regnum); 118ec21e2ecSJeff Kirsher 119ec21e2ecSJeff Kirsher /* Clear miimcom, and then initiate a read */ 120ec21e2ecSJeff Kirsher out_be32(®s->miimcom, 0); 121ec21e2ecSJeff Kirsher out_be32(®s->miimcom, MII_READ_COMMAND); 122ec21e2ecSJeff Kirsher 12359399c59STimur Tabi /* Wait for the transaction to finish, normally less than 100us */ 12459399c59STimur Tabi status = spin_event_timeout(!(in_be32(®s->miimind) & 12559399c59STimur Tabi (MIIMIND_NOTVALID | MIIMIND_BUSY)), 12659399c59STimur Tabi MII_TIMEOUT, 0); 12759399c59STimur Tabi if (!status) 12859399c59STimur Tabi return -ETIMEDOUT; 129ec21e2ecSJeff Kirsher 130ec21e2ecSJeff Kirsher /* Grab the value of the register from miimstat */ 131ec21e2ecSJeff Kirsher value = in_be32(®s->miimstat); 132ec21e2ecSJeff Kirsher 133ec21e2ecSJeff Kirsher return value; 134ec21e2ecSJeff Kirsher } 135ec21e2ecSJeff Kirsher 136ec21e2ecSJeff Kirsher /* Reset the MIIM registers, and wait for the bus to free */ 137ec21e2ecSJeff Kirsher static int fsl_pq_mdio_reset(struct mii_bus *bus) 138ec21e2ecSJeff Kirsher { 13969cfb419STimur Tabi struct fsl_pq_mdio_priv *priv = bus->priv; 14069cfb419STimur Tabi struct fsl_pq_mdio __iomem *regs = priv->regs; 14159399c59STimur Tabi u32 status; 142ec21e2ecSJeff Kirsher 143ec21e2ecSJeff Kirsher mutex_lock(&bus->mdio_lock); 144ec21e2ecSJeff Kirsher 145ec21e2ecSJeff Kirsher /* Reset the management interface */ 146ec21e2ecSJeff Kirsher out_be32(®s->miimcfg, MIIMCFG_RESET); 147ec21e2ecSJeff Kirsher 148ec21e2ecSJeff Kirsher /* Setup the MII Mgmt clock speed */ 149ec21e2ecSJeff Kirsher out_be32(®s->miimcfg, MIIMCFG_INIT_VALUE); 150ec21e2ecSJeff Kirsher 151ec21e2ecSJeff Kirsher /* Wait until the bus is free */ 15259399c59STimur Tabi status = spin_event_timeout(!(in_be32(®s->miimind) & MIIMIND_BUSY), 15359399c59STimur Tabi MII_TIMEOUT, 0); 154ec21e2ecSJeff Kirsher 155ec21e2ecSJeff Kirsher mutex_unlock(&bus->mdio_lock); 156ec21e2ecSJeff Kirsher 15759399c59STimur Tabi if (!status) { 1585078ac79STimur Tabi dev_err(&bus->dev, "timeout waiting for MII bus\n"); 159ec21e2ecSJeff Kirsher return -EBUSY; 160ec21e2ecSJeff Kirsher } 161ec21e2ecSJeff Kirsher 162ec21e2ecSJeff Kirsher return 0; 163ec21e2ecSJeff Kirsher } 164ec21e2ecSJeff Kirsher 165ec21e2ecSJeff Kirsher static u32 __iomem *get_gfar_tbipa(struct fsl_pq_mdio __iomem *regs, struct device_node *np) 166ec21e2ecSJeff Kirsher { 167952c5ca1SAndy Fleming #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE) 168ec21e2ecSJeff Kirsher struct gfar __iomem *enet_regs; 169ec21e2ecSJeff Kirsher 170ec21e2ecSJeff Kirsher /* 171ec21e2ecSJeff Kirsher * This is mildly evil, but so is our hardware for doing this. 172ec21e2ecSJeff Kirsher * Also, we have to cast back to struct gfar because of 173ec21e2ecSJeff Kirsher * definition weirdness done in gianfar.h. 174ec21e2ecSJeff Kirsher */ 175ec21e2ecSJeff Kirsher if (of_device_is_compatible(np, "fsl,gianfar-mdio") || 176ec21e2ecSJeff Kirsher of_device_is_compatible(np, "fsl,gianfar-tbi") || 177ec21e2ecSJeff Kirsher of_device_is_compatible(np, "gianfar")) { 178ec21e2ecSJeff Kirsher enet_regs = (struct gfar __iomem *)regs; 179ec21e2ecSJeff Kirsher return &enet_regs->tbipa; 180ec21e2ecSJeff Kirsher } else if (of_device_is_compatible(np, "fsl,etsec2-mdio") || 181ec21e2ecSJeff Kirsher of_device_is_compatible(np, "fsl,etsec2-tbi")) { 182ec21e2ecSJeff Kirsher return of_iomap(np, 1); 183ec21e2ecSJeff Kirsher } 184ec21e2ecSJeff Kirsher #endif 185952c5ca1SAndy Fleming return NULL; 186952c5ca1SAndy Fleming } 187ec21e2ecSJeff Kirsher 188ec21e2ecSJeff Kirsher 189ec21e2ecSJeff Kirsher static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id) 190ec21e2ecSJeff Kirsher { 191952c5ca1SAndy Fleming #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE) 192ec21e2ecSJeff Kirsher struct device_node *np = NULL; 193ec21e2ecSJeff Kirsher int err = 0; 194ec21e2ecSJeff Kirsher 195ec21e2ecSJeff Kirsher for_each_compatible_node(np, NULL, "ucc_geth") { 196ec21e2ecSJeff Kirsher struct resource tempres; 197ec21e2ecSJeff Kirsher 198ec21e2ecSJeff Kirsher err = of_address_to_resource(np, 0, &tempres); 199ec21e2ecSJeff Kirsher if (err) 200ec21e2ecSJeff Kirsher continue; 201ec21e2ecSJeff Kirsher 202ec21e2ecSJeff Kirsher /* if our mdio regs fall within this UCC regs range */ 203ec21e2ecSJeff Kirsher if ((start >= tempres.start) && (end <= tempres.end)) { 204ec21e2ecSJeff Kirsher /* Find the id of the UCC */ 205ec21e2ecSJeff Kirsher const u32 *id; 206ec21e2ecSJeff Kirsher 207ec21e2ecSJeff Kirsher id = of_get_property(np, "cell-index", NULL); 208ec21e2ecSJeff Kirsher if (!id) { 209ec21e2ecSJeff Kirsher id = of_get_property(np, "device-id", NULL); 210ec21e2ecSJeff Kirsher if (!id) 211ec21e2ecSJeff Kirsher continue; 212ec21e2ecSJeff Kirsher } 213ec21e2ecSJeff Kirsher 214ec21e2ecSJeff Kirsher *ucc_id = *id; 215ec21e2ecSJeff Kirsher 216ec21e2ecSJeff Kirsher return 0; 217ec21e2ecSJeff Kirsher } 218ec21e2ecSJeff Kirsher } 219ec21e2ecSJeff Kirsher 220ec21e2ecSJeff Kirsher if (err) 221ec21e2ecSJeff Kirsher return err; 222ec21e2ecSJeff Kirsher else 223ec21e2ecSJeff Kirsher return -EINVAL; 224952c5ca1SAndy Fleming #else 225952c5ca1SAndy Fleming return -ENODEV; 226ec21e2ecSJeff Kirsher #endif 227952c5ca1SAndy Fleming } 228ec21e2ecSJeff Kirsher 2295078ac79STimur Tabi static int fsl_pq_mdio_probe(struct platform_device *pdev) 230ec21e2ecSJeff Kirsher { 2315078ac79STimur Tabi struct device_node *np = pdev->dev.of_node; 232ec21e2ecSJeff Kirsher struct device_node *tbi; 233ec21e2ecSJeff Kirsher struct fsl_pq_mdio_priv *priv; 234ec21e2ecSJeff Kirsher struct fsl_pq_mdio __iomem *regs = NULL; 235ec21e2ecSJeff Kirsher void __iomem *map; 236ec21e2ecSJeff Kirsher u32 __iomem *tbipa; 237ec21e2ecSJeff Kirsher struct mii_bus *new_bus; 238ec21e2ecSJeff Kirsher int tbiaddr = -1; 239ec21e2ecSJeff Kirsher const u32 *addrp; 240ec21e2ecSJeff Kirsher u64 addr = 0, size = 0; 241ec21e2ecSJeff Kirsher int err; 242ec21e2ecSJeff Kirsher 243ec21e2ecSJeff Kirsher priv = kzalloc(sizeof(*priv), GFP_KERNEL); 244ec21e2ecSJeff Kirsher if (!priv) 245ec21e2ecSJeff Kirsher return -ENOMEM; 246ec21e2ecSJeff Kirsher 247ec21e2ecSJeff Kirsher new_bus = mdiobus_alloc(); 248ec21e2ecSJeff Kirsher if (!new_bus) { 249ec21e2ecSJeff Kirsher err = -ENOMEM; 250ec21e2ecSJeff Kirsher goto err_free_priv; 251ec21e2ecSJeff Kirsher } 252ec21e2ecSJeff Kirsher 253ec21e2ecSJeff Kirsher new_bus->name = "Freescale PowerQUICC MII Bus", 2545078ac79STimur Tabi new_bus->read = &fsl_pq_mdio_read; 2555078ac79STimur Tabi new_bus->write = &fsl_pq_mdio_write; 2565078ac79STimur Tabi new_bus->reset = &fsl_pq_mdio_reset; 257ec21e2ecSJeff Kirsher new_bus->priv = priv; 258ec21e2ecSJeff Kirsher 259ec21e2ecSJeff Kirsher addrp = of_get_address(np, 0, &size, NULL); 260ec21e2ecSJeff Kirsher if (!addrp) { 261ec21e2ecSJeff Kirsher err = -EINVAL; 262ec21e2ecSJeff Kirsher goto err_free_bus; 263ec21e2ecSJeff Kirsher } 264ec21e2ecSJeff Kirsher 265ec21e2ecSJeff Kirsher /* Set the PHY base address */ 266ec21e2ecSJeff Kirsher addr = of_translate_address(np, addrp); 267ec21e2ecSJeff Kirsher if (addr == OF_BAD_ADDR) { 268ec21e2ecSJeff Kirsher err = -EINVAL; 269ec21e2ecSJeff Kirsher goto err_free_bus; 270ec21e2ecSJeff Kirsher } 271ec21e2ecSJeff Kirsher 27269cfb419STimur Tabi snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s@%llx", np->name, 27369cfb419STimur Tabi (unsigned long long)addr); 27469cfb419STimur Tabi 275ec21e2ecSJeff Kirsher map = ioremap(addr, size); 276ec21e2ecSJeff Kirsher if (!map) { 277ec21e2ecSJeff Kirsher err = -ENOMEM; 278ec21e2ecSJeff Kirsher goto err_free_bus; 279ec21e2ecSJeff Kirsher } 280ec21e2ecSJeff Kirsher priv->map = map; 281ec21e2ecSJeff Kirsher 282ec21e2ecSJeff Kirsher if (of_device_is_compatible(np, "fsl,gianfar-mdio") || 283ec21e2ecSJeff Kirsher of_device_is_compatible(np, "fsl,gianfar-tbi") || 284ec21e2ecSJeff Kirsher of_device_is_compatible(np, "fsl,ucc-mdio") || 285ec21e2ecSJeff Kirsher of_device_is_compatible(np, "ucc_geth_phy")) 286ec21e2ecSJeff Kirsher map -= offsetof(struct fsl_pq_mdio, miimcfg); 287ec21e2ecSJeff Kirsher regs = map; 288ec21e2ecSJeff Kirsher priv->regs = regs; 289ec21e2ecSJeff Kirsher 290ec21e2ecSJeff Kirsher new_bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL); 291ec21e2ecSJeff Kirsher 292ec21e2ecSJeff Kirsher if (NULL == new_bus->irq) { 293ec21e2ecSJeff Kirsher err = -ENOMEM; 294ec21e2ecSJeff Kirsher goto err_unmap_regs; 295ec21e2ecSJeff Kirsher } 296ec21e2ecSJeff Kirsher 2975078ac79STimur Tabi new_bus->parent = &pdev->dev; 2985078ac79STimur Tabi dev_set_drvdata(&pdev->dev, new_bus); 299ec21e2ecSJeff Kirsher 300ec21e2ecSJeff Kirsher if (of_device_is_compatible(np, "fsl,gianfar-mdio") || 301ec21e2ecSJeff Kirsher of_device_is_compatible(np, "fsl,gianfar-tbi") || 302ec21e2ecSJeff Kirsher of_device_is_compatible(np, "fsl,etsec2-mdio") || 303ec21e2ecSJeff Kirsher of_device_is_compatible(np, "fsl,etsec2-tbi") || 304ec21e2ecSJeff Kirsher of_device_is_compatible(np, "gianfar")) { 305ec21e2ecSJeff Kirsher tbipa = get_gfar_tbipa(regs, np); 306ec21e2ecSJeff Kirsher if (!tbipa) { 307ec21e2ecSJeff Kirsher err = -EINVAL; 308ec21e2ecSJeff Kirsher goto err_free_irqs; 309ec21e2ecSJeff Kirsher } 310ec21e2ecSJeff Kirsher } else if (of_device_is_compatible(np, "fsl,ucc-mdio") || 311ec21e2ecSJeff Kirsher of_device_is_compatible(np, "ucc_geth_phy")) { 312ec21e2ecSJeff Kirsher u32 id; 313ec21e2ecSJeff Kirsher static u32 mii_mng_master; 314ec21e2ecSJeff Kirsher 315ec21e2ecSJeff Kirsher tbipa = ®s->utbipar; 316ec21e2ecSJeff Kirsher 317ec21e2ecSJeff Kirsher if ((err = get_ucc_id_for_range(addr, addr + size, &id))) 318ec21e2ecSJeff Kirsher goto err_free_irqs; 319ec21e2ecSJeff Kirsher 320ec21e2ecSJeff Kirsher if (!mii_mng_master) { 321ec21e2ecSJeff Kirsher mii_mng_master = id; 322ec21e2ecSJeff Kirsher ucc_set_qe_mux_mii_mng(id - 1); 323ec21e2ecSJeff Kirsher } 324ec21e2ecSJeff Kirsher } else { 325ec21e2ecSJeff Kirsher err = -ENODEV; 326ec21e2ecSJeff Kirsher goto err_free_irqs; 327ec21e2ecSJeff Kirsher } 328ec21e2ecSJeff Kirsher 329ec21e2ecSJeff Kirsher for_each_child_of_node(np, tbi) { 330ec21e2ecSJeff Kirsher if (!strncmp(tbi->type, "tbi-phy", 8)) 331ec21e2ecSJeff Kirsher break; 332ec21e2ecSJeff Kirsher } 333ec21e2ecSJeff Kirsher 334ec21e2ecSJeff Kirsher if (tbi) { 335ec21e2ecSJeff Kirsher const u32 *prop = of_get_property(tbi, "reg", NULL); 336ec21e2ecSJeff Kirsher 337ec21e2ecSJeff Kirsher if (prop) 338ec21e2ecSJeff Kirsher tbiaddr = *prop; 339ec21e2ecSJeff Kirsher 340ec21e2ecSJeff Kirsher if (tbiaddr == -1) { 341ec21e2ecSJeff Kirsher err = -EBUSY; 342ec21e2ecSJeff Kirsher goto err_free_irqs; 343c3e072f8SBaruch Siach } else { 344ec21e2ecSJeff Kirsher out_be32(tbipa, tbiaddr); 345c3e072f8SBaruch Siach } 346464b57daSKenth Eriksson } 347ec21e2ecSJeff Kirsher 348ec21e2ecSJeff Kirsher err = of_mdiobus_register(new_bus, np); 349ec21e2ecSJeff Kirsher if (err) { 3505078ac79STimur Tabi dev_err(&pdev->dev, "cannot register %s as MDIO bus\n", 351ec21e2ecSJeff Kirsher new_bus->name); 352ec21e2ecSJeff Kirsher goto err_free_irqs; 353ec21e2ecSJeff Kirsher } 354ec21e2ecSJeff Kirsher 355ec21e2ecSJeff Kirsher return 0; 356ec21e2ecSJeff Kirsher 357ec21e2ecSJeff Kirsher err_free_irqs: 358ec21e2ecSJeff Kirsher kfree(new_bus->irq); 359ec21e2ecSJeff Kirsher err_unmap_regs: 360ec21e2ecSJeff Kirsher iounmap(priv->map); 361ec21e2ecSJeff Kirsher err_free_bus: 362ec21e2ecSJeff Kirsher kfree(new_bus); 363ec21e2ecSJeff Kirsher err_free_priv: 364ec21e2ecSJeff Kirsher kfree(priv); 365ec21e2ecSJeff Kirsher return err; 366ec21e2ecSJeff Kirsher } 367ec21e2ecSJeff Kirsher 368ec21e2ecSJeff Kirsher 3695078ac79STimur Tabi static int fsl_pq_mdio_remove(struct platform_device *pdev) 370ec21e2ecSJeff Kirsher { 3715078ac79STimur Tabi struct device *device = &pdev->dev; 372ec21e2ecSJeff Kirsher struct mii_bus *bus = dev_get_drvdata(device); 373ec21e2ecSJeff Kirsher struct fsl_pq_mdio_priv *priv = bus->priv; 374ec21e2ecSJeff Kirsher 375ec21e2ecSJeff Kirsher mdiobus_unregister(bus); 376ec21e2ecSJeff Kirsher 377ec21e2ecSJeff Kirsher dev_set_drvdata(device, NULL); 378ec21e2ecSJeff Kirsher 379ec21e2ecSJeff Kirsher iounmap(priv->map); 380ec21e2ecSJeff Kirsher bus->priv = NULL; 381ec21e2ecSJeff Kirsher mdiobus_free(bus); 382ec21e2ecSJeff Kirsher kfree(priv); 383ec21e2ecSJeff Kirsher 384ec21e2ecSJeff Kirsher return 0; 385ec21e2ecSJeff Kirsher } 386ec21e2ecSJeff Kirsher 387ec21e2ecSJeff Kirsher static struct of_device_id fsl_pq_mdio_match[] = { 388ec21e2ecSJeff Kirsher { 389ec21e2ecSJeff Kirsher .type = "mdio", 390ec21e2ecSJeff Kirsher .compatible = "ucc_geth_phy", 391ec21e2ecSJeff Kirsher }, 392ec21e2ecSJeff Kirsher { 393ec21e2ecSJeff Kirsher .type = "mdio", 394ec21e2ecSJeff Kirsher .compatible = "gianfar", 395ec21e2ecSJeff Kirsher }, 396ec21e2ecSJeff Kirsher { 397ec21e2ecSJeff Kirsher .compatible = "fsl,ucc-mdio", 398ec21e2ecSJeff Kirsher }, 399ec21e2ecSJeff Kirsher { 400ec21e2ecSJeff Kirsher .compatible = "fsl,gianfar-tbi", 401ec21e2ecSJeff Kirsher }, 402ec21e2ecSJeff Kirsher { 403ec21e2ecSJeff Kirsher .compatible = "fsl,gianfar-mdio", 404ec21e2ecSJeff Kirsher }, 405ec21e2ecSJeff Kirsher { 406ec21e2ecSJeff Kirsher .compatible = "fsl,etsec2-tbi", 407ec21e2ecSJeff Kirsher }, 408ec21e2ecSJeff Kirsher { 409ec21e2ecSJeff Kirsher .compatible = "fsl,etsec2-mdio", 410ec21e2ecSJeff Kirsher }, 411ec21e2ecSJeff Kirsher {}, 412ec21e2ecSJeff Kirsher }; 413ec21e2ecSJeff Kirsher MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match); 414ec21e2ecSJeff Kirsher 415ec21e2ecSJeff Kirsher static struct platform_driver fsl_pq_mdio_driver = { 416ec21e2ecSJeff Kirsher .driver = { 417ec21e2ecSJeff Kirsher .name = "fsl-pq_mdio", 418ec21e2ecSJeff Kirsher .owner = THIS_MODULE, 419ec21e2ecSJeff Kirsher .of_match_table = fsl_pq_mdio_match, 420ec21e2ecSJeff Kirsher }, 421ec21e2ecSJeff Kirsher .probe = fsl_pq_mdio_probe, 422ec21e2ecSJeff Kirsher .remove = fsl_pq_mdio_remove, 423ec21e2ecSJeff Kirsher }; 424ec21e2ecSJeff Kirsher 425db62f684SAxel Lin module_platform_driver(fsl_pq_mdio_driver); 426ec21e2ecSJeff Kirsher 427ec21e2ecSJeff Kirsher MODULE_LICENSE("GPL"); 428