1ec21e2ecSJeff Kirsher /* 2ec21e2ecSJeff Kirsher * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation 3ec21e2ecSJeff Kirsher * Provides Bus interface for MIIM regs 4ec21e2ecSJeff Kirsher * 5ec21e2ecSJeff Kirsher * Author: Andy Fleming <afleming@freescale.com> 6ec21e2ecSJeff Kirsher * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 7ec21e2ecSJeff Kirsher * 8ec21e2ecSJeff Kirsher * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc. 9ec21e2ecSJeff Kirsher * 10ec21e2ecSJeff Kirsher * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips) 11ec21e2ecSJeff Kirsher * 12ec21e2ecSJeff Kirsher * This program is free software; you can redistribute it and/or modify it 13ec21e2ecSJeff Kirsher * under the terms of the GNU General Public License as published by the 14ec21e2ecSJeff Kirsher * Free Software Foundation; either version 2 of the License, or (at your 15ec21e2ecSJeff Kirsher * option) any later version. 16ec21e2ecSJeff Kirsher * 17ec21e2ecSJeff Kirsher */ 18ec21e2ecSJeff Kirsher 19ec21e2ecSJeff Kirsher #include <linux/kernel.h> 20ec21e2ecSJeff Kirsher #include <linux/string.h> 21ec21e2ecSJeff Kirsher #include <linux/errno.h> 22ec21e2ecSJeff Kirsher #include <linux/slab.h> 23ec21e2ecSJeff Kirsher #include <linux/delay.h> 24ec21e2ecSJeff Kirsher #include <linux/module.h> 25ec21e2ecSJeff Kirsher #include <linux/mii.h> 26ec21e2ecSJeff Kirsher #include <linux/of_address.h> 27ec21e2ecSJeff Kirsher #include <linux/of_mdio.h> 28afae5ad7STimur Tabi #include <linux/of_device.h> 29ec21e2ecSJeff Kirsher 30ec21e2ecSJeff Kirsher #include <asm/io.h> 319a4cbd53SClaudiu Manoil #if IS_ENABLED(CONFIG_UCC_GETH) 327aa1aa6eSZhao Qiang #include <soc/fsl/qe/ucc.h> 339a4cbd53SClaudiu Manoil #endif 34ec21e2ecSJeff Kirsher 35ec21e2ecSJeff Kirsher #include "gianfar.h" 3619bcd6c6STimur Tabi 3719bcd6c6STimur Tabi #define MIIMIND_BUSY 0x00000001 3819bcd6c6STimur Tabi #define MIIMIND_NOTVALID 0x00000004 3919bcd6c6STimur Tabi #define MIIMCFG_INIT_VALUE 0x00000007 4019bcd6c6STimur Tabi #define MIIMCFG_RESET 0x80000000 4119bcd6c6STimur Tabi 4219bcd6c6STimur Tabi #define MII_READ_COMMAND 0x00000001 4319bcd6c6STimur Tabi 44afae5ad7STimur Tabi struct fsl_pq_mii { 45afae5ad7STimur Tabi u32 miimcfg; /* MII management configuration reg */ 46afae5ad7STimur Tabi u32 miimcom; /* MII management command reg */ 47afae5ad7STimur Tabi u32 miimadd; /* MII management address reg */ 48afae5ad7STimur Tabi u32 miimcon; /* MII management control reg */ 49afae5ad7STimur Tabi u32 miimstat; /* MII management status reg */ 50afae5ad7STimur Tabi u32 miimind; /* MII management indication reg */ 51afae5ad7STimur Tabi }; 52afae5ad7STimur Tabi 5319bcd6c6STimur Tabi struct fsl_pq_mdio { 5419bcd6c6STimur Tabi u8 res1[16]; 5519bcd6c6STimur Tabi u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/ 5619bcd6c6STimur Tabi u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/ 5719bcd6c6STimur Tabi u8 res2[4]; 5819bcd6c6STimur Tabi u32 emapm; /* MDIO Event mapping register (for etsec2)*/ 5919bcd6c6STimur Tabi u8 res3[1280]; 60afae5ad7STimur Tabi struct fsl_pq_mii mii; 6119bcd6c6STimur Tabi u8 res4[28]; 6219bcd6c6STimur Tabi u32 utbipar; /* TBI phy address reg (only on UCC) */ 6319bcd6c6STimur Tabi u8 res5[2728]; 6419bcd6c6STimur Tabi } __packed; 65ec21e2ecSJeff Kirsher 6659399c59STimur Tabi /* Number of microseconds to wait for an MII register to respond */ 6759399c59STimur Tabi #define MII_TIMEOUT 1000 6859399c59STimur Tabi 69ec21e2ecSJeff Kirsher struct fsl_pq_mdio_priv { 70ec21e2ecSJeff Kirsher void __iomem *map; 71afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs; 72afae5ad7STimur Tabi }; 73afae5ad7STimur Tabi 74afae5ad7STimur Tabi /* 75afae5ad7STimur Tabi * Per-device-type data. Each type of device tree node that we support gets 76afae5ad7STimur Tabi * one of these. 77afae5ad7STimur Tabi * 78afae5ad7STimur Tabi * @mii_offset: the offset of the MII registers within the memory map of the 79afae5ad7STimur Tabi * node. Some nodes define only the MII registers, and some define the whole 80afae5ad7STimur Tabi * MAC (which includes the MII registers). 81afae5ad7STimur Tabi * 82afae5ad7STimur Tabi * @get_tbipa: determines the address of the TBIPA register 83afae5ad7STimur Tabi * 84afae5ad7STimur Tabi * @ucc_configure: a special function for extra QE configuration 85afae5ad7STimur Tabi */ 86afae5ad7STimur Tabi struct fsl_pq_mdio_data { 87afae5ad7STimur Tabi unsigned int mii_offset; /* offset of the MII registers */ 88afae5ad7STimur Tabi uint32_t __iomem * (*get_tbipa)(void __iomem *p); 89afae5ad7STimur Tabi void (*ucc_configure)(phys_addr_t start, phys_addr_t end); 90ec21e2ecSJeff Kirsher }; 91ec21e2ecSJeff Kirsher 92ec21e2ecSJeff Kirsher /* 9369cfb419STimur Tabi * Write value to the PHY at mii_id at register regnum, on the bus attached 9469cfb419STimur Tabi * to the local interface, which may be different from the generic mdio bus 9569cfb419STimur Tabi * (tied to a single interface), waiting until the write is done before 9669cfb419STimur Tabi * returning. This is helpful in programming interfaces like the TBI which 9769cfb419STimur Tabi * control interfaces like onchip SERDES and are always tied to the local 9869cfb419STimur Tabi * mdio pins, which may not be the same as system mdio bus, used for 99ec21e2ecSJeff Kirsher * controlling the external PHYs, for example. 100ec21e2ecSJeff Kirsher */ 10169cfb419STimur Tabi static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 10269cfb419STimur Tabi u16 value) 103ec21e2ecSJeff Kirsher { 10469cfb419STimur Tabi struct fsl_pq_mdio_priv *priv = bus->priv; 105afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs = priv->regs; 106e4b081f5SClaudiu Manoil unsigned int timeout; 10759399c59STimur Tabi 108ec21e2ecSJeff Kirsher /* Set the PHY address and the register address we want to write */ 109f5bbd262SClaudiu Manoil iowrite32be((mii_id << 8) | regnum, ®s->miimadd); 110ec21e2ecSJeff Kirsher 111ec21e2ecSJeff Kirsher /* Write out the value we want */ 112f5bbd262SClaudiu Manoil iowrite32be(value, ®s->miimcon); 113ec21e2ecSJeff Kirsher 114ec21e2ecSJeff Kirsher /* Wait for the transaction to finish */ 115e4b081f5SClaudiu Manoil timeout = MII_TIMEOUT; 116e4b081f5SClaudiu Manoil while ((ioread32be(®s->miimind) & MIIMIND_BUSY) && timeout) { 117e4b081f5SClaudiu Manoil cpu_relax(); 118e4b081f5SClaudiu Manoil timeout--; 119e4b081f5SClaudiu Manoil } 120ec21e2ecSJeff Kirsher 121e4b081f5SClaudiu Manoil return timeout ? 0 : -ETIMEDOUT; 122ec21e2ecSJeff Kirsher } 123ec21e2ecSJeff Kirsher 124ec21e2ecSJeff Kirsher /* 12569cfb419STimur Tabi * Read the bus for PHY at addr mii_id, register regnum, and return the value. 12669cfb419STimur Tabi * Clears miimcom first. 12769cfb419STimur Tabi * 12869cfb419STimur Tabi * All PHY operation done on the bus attached to the local interface, which 12969cfb419STimur Tabi * may be different from the generic mdio bus. This is helpful in programming 13069cfb419STimur Tabi * interfaces like the TBI which, in turn, control interfaces like on-chip 13169cfb419STimur Tabi * SERDES and are always tied to the local mdio pins, which may not be the 132ec21e2ecSJeff Kirsher * same as system mdio bus, used for controlling the external PHYs, for eg. 133ec21e2ecSJeff Kirsher */ 13469cfb419STimur Tabi static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 135ec21e2ecSJeff Kirsher { 13669cfb419STimur Tabi struct fsl_pq_mdio_priv *priv = bus->priv; 137afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs = priv->regs; 138e4b081f5SClaudiu Manoil unsigned int timeout; 13969cfb419STimur Tabi u16 value; 140ec21e2ecSJeff Kirsher 141ec21e2ecSJeff Kirsher /* Set the PHY address and the register address we want to read */ 142f5bbd262SClaudiu Manoil iowrite32be((mii_id << 8) | regnum, ®s->miimadd); 143ec21e2ecSJeff Kirsher 144ec21e2ecSJeff Kirsher /* Clear miimcom, and then initiate a read */ 145f5bbd262SClaudiu Manoil iowrite32be(0, ®s->miimcom); 146f5bbd262SClaudiu Manoil iowrite32be(MII_READ_COMMAND, ®s->miimcom); 147ec21e2ecSJeff Kirsher 14859399c59STimur Tabi /* Wait for the transaction to finish, normally less than 100us */ 149e4b081f5SClaudiu Manoil timeout = MII_TIMEOUT; 150e4b081f5SClaudiu Manoil while ((ioread32be(®s->miimind) & 151e4b081f5SClaudiu Manoil (MIIMIND_NOTVALID | MIIMIND_BUSY)) && timeout) { 152e4b081f5SClaudiu Manoil cpu_relax(); 153e4b081f5SClaudiu Manoil timeout--; 154e4b081f5SClaudiu Manoil } 155e4b081f5SClaudiu Manoil 156e4b081f5SClaudiu Manoil if (!timeout) 15759399c59STimur Tabi return -ETIMEDOUT; 158ec21e2ecSJeff Kirsher 159ec21e2ecSJeff Kirsher /* Grab the value of the register from miimstat */ 160f5bbd262SClaudiu Manoil value = ioread32be(®s->miimstat); 161ec21e2ecSJeff Kirsher 162afae5ad7STimur Tabi dev_dbg(&bus->dev, "read %04x from address %x/%x\n", value, mii_id, regnum); 163ec21e2ecSJeff Kirsher return value; 164ec21e2ecSJeff Kirsher } 165ec21e2ecSJeff Kirsher 166ec21e2ecSJeff Kirsher /* Reset the MIIM registers, and wait for the bus to free */ 167ec21e2ecSJeff Kirsher static int fsl_pq_mdio_reset(struct mii_bus *bus) 168ec21e2ecSJeff Kirsher { 16969cfb419STimur Tabi struct fsl_pq_mdio_priv *priv = bus->priv; 170afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs = priv->regs; 171e4b081f5SClaudiu Manoil unsigned int timeout; 172ec21e2ecSJeff Kirsher 173ec21e2ecSJeff Kirsher mutex_lock(&bus->mdio_lock); 174ec21e2ecSJeff Kirsher 175ec21e2ecSJeff Kirsher /* Reset the management interface */ 176f5bbd262SClaudiu Manoil iowrite32be(MIIMCFG_RESET, ®s->miimcfg); 177ec21e2ecSJeff Kirsher 178ec21e2ecSJeff Kirsher /* Setup the MII Mgmt clock speed */ 179f5bbd262SClaudiu Manoil iowrite32be(MIIMCFG_INIT_VALUE, ®s->miimcfg); 180ec21e2ecSJeff Kirsher 181ec21e2ecSJeff Kirsher /* Wait until the bus is free */ 182e4b081f5SClaudiu Manoil timeout = MII_TIMEOUT; 183e4b081f5SClaudiu Manoil while ((ioread32be(®s->miimind) & MIIMIND_BUSY) && timeout) { 184e4b081f5SClaudiu Manoil cpu_relax(); 185e4b081f5SClaudiu Manoil timeout--; 186e4b081f5SClaudiu Manoil } 187ec21e2ecSJeff Kirsher 188ec21e2ecSJeff Kirsher mutex_unlock(&bus->mdio_lock); 189ec21e2ecSJeff Kirsher 190e4b081f5SClaudiu Manoil if (!timeout) { 1915078ac79STimur Tabi dev_err(&bus->dev, "timeout waiting for MII bus\n"); 192ec21e2ecSJeff Kirsher return -EBUSY; 193ec21e2ecSJeff Kirsher } 194ec21e2ecSJeff Kirsher 195ec21e2ecSJeff Kirsher return 0; 196ec21e2ecSJeff Kirsher } 197ec21e2ecSJeff Kirsher 198504e76e5SJavier Martinez Canillas #if IS_ENABLED(CONFIG_GIANFAR) 199ec21e2ecSJeff Kirsher /* 2003bb35ac4SGerlando Falauto * Return the TBIPA address, starting from the address 2013bb35ac4SGerlando Falauto * of the mapped GFAR MDIO registers (struct gfar) 202ec21e2ecSJeff Kirsher * This is mildly evil, but so is our hardware for doing this. 203ec21e2ecSJeff Kirsher * Also, we have to cast back to struct gfar because of 204ec21e2ecSJeff Kirsher * definition weirdness done in gianfar.h. 205ec21e2ecSJeff Kirsher */ 2063bb35ac4SGerlando Falauto static uint32_t __iomem *get_gfar_tbipa_from_mdio(void __iomem *p) 207afae5ad7STimur Tabi { 208afae5ad7STimur Tabi struct gfar __iomem *enet_regs = p; 209afae5ad7STimur Tabi 210ec21e2ecSJeff Kirsher return &enet_regs->tbipa; 211afae5ad7STimur Tabi } 212afae5ad7STimur Tabi 213afae5ad7STimur Tabi /* 2143bb35ac4SGerlando Falauto * Return the TBIPA address, starting from the address 2153bb35ac4SGerlando Falauto * of the mapped GFAR MII registers (gfar_mii_regs[] within struct gfar) 2163bb35ac4SGerlando Falauto */ 2173bb35ac4SGerlando Falauto static uint32_t __iomem *get_gfar_tbipa_from_mii(void __iomem *p) 2183bb35ac4SGerlando Falauto { 2193bb35ac4SGerlando Falauto return get_gfar_tbipa_from_mdio(container_of(p, struct gfar, gfar_mii_regs)); 2203bb35ac4SGerlando Falauto } 2213bb35ac4SGerlando Falauto 2223bb35ac4SGerlando Falauto /* 223afae5ad7STimur Tabi * Return the TBIPAR address for an eTSEC2 node 224afae5ad7STimur Tabi */ 225afae5ad7STimur Tabi static uint32_t __iomem *get_etsec_tbipa(void __iomem *p) 226afae5ad7STimur Tabi { 227afae5ad7STimur Tabi return p; 228ec21e2ecSJeff Kirsher } 229ec21e2ecSJeff Kirsher #endif 230afae5ad7STimur Tabi 231504e76e5SJavier Martinez Canillas #if IS_ENABLED(CONFIG_UCC_GETH) 232afae5ad7STimur Tabi /* 2333bb35ac4SGerlando Falauto * Return the TBIPAR address for a QE MDIO node, starting from the address 2343bb35ac4SGerlando Falauto * of the mapped MII registers (struct fsl_pq_mii) 235afae5ad7STimur Tabi */ 236afae5ad7STimur Tabi static uint32_t __iomem *get_ucc_tbipa(void __iomem *p) 237afae5ad7STimur Tabi { 2383bb35ac4SGerlando Falauto struct fsl_pq_mdio __iomem *mdio = container_of(p, struct fsl_pq_mdio, mii); 239afae5ad7STimur Tabi 240afae5ad7STimur Tabi return &mdio->utbipar; 241952c5ca1SAndy Fleming } 242ec21e2ecSJeff Kirsher 243afae5ad7STimur Tabi /* 244afae5ad7STimur Tabi * Find the UCC node that controls the given MDIO node 245afae5ad7STimur Tabi * 246afae5ad7STimur Tabi * For some reason, the QE MDIO nodes are not children of the UCC devices 247afae5ad7STimur Tabi * that control them. Therefore, we need to scan all UCC nodes looking for 248afae5ad7STimur Tabi * the one that encompases the given MDIO node. We do this by comparing 249afae5ad7STimur Tabi * physical addresses. The 'start' and 'end' addresses of the MDIO node are 250afae5ad7STimur Tabi * passed, and the correct UCC node will cover the entire address range. 251afae5ad7STimur Tabi * 252afae5ad7STimur Tabi * This assumes that there is only one QE MDIO node in the entire device tree. 253afae5ad7STimur Tabi */ 254afae5ad7STimur Tabi static void ucc_configure(phys_addr_t start, phys_addr_t end) 255ec21e2ecSJeff Kirsher { 256afae5ad7STimur Tabi static bool found_mii_master; 257ec21e2ecSJeff Kirsher struct device_node *np = NULL; 258afae5ad7STimur Tabi 259afae5ad7STimur Tabi if (found_mii_master) 260afae5ad7STimur Tabi return; 261ec21e2ecSJeff Kirsher 262ec21e2ecSJeff Kirsher for_each_compatible_node(np, NULL, "ucc_geth") { 263afae5ad7STimur Tabi struct resource res; 264afae5ad7STimur Tabi const uint32_t *iprop; 265afae5ad7STimur Tabi uint32_t id; 266afae5ad7STimur Tabi int ret; 267ec21e2ecSJeff Kirsher 268afae5ad7STimur Tabi ret = of_address_to_resource(np, 0, &res); 269afae5ad7STimur Tabi if (ret < 0) { 270afae5ad7STimur Tabi pr_debug("fsl-pq-mdio: no address range in node %s\n", 271afae5ad7STimur Tabi np->full_name); 272ec21e2ecSJeff Kirsher continue; 273afae5ad7STimur Tabi } 274ec21e2ecSJeff Kirsher 275ec21e2ecSJeff Kirsher /* if our mdio regs fall within this UCC regs range */ 276afae5ad7STimur Tabi if ((start < res.start) || (end > res.end)) 277afae5ad7STimur Tabi continue; 278ec21e2ecSJeff Kirsher 279afae5ad7STimur Tabi iprop = of_get_property(np, "cell-index", NULL); 280afae5ad7STimur Tabi if (!iprop) { 281afae5ad7STimur Tabi iprop = of_get_property(np, "device-id", NULL); 282afae5ad7STimur Tabi if (!iprop) { 283afae5ad7STimur Tabi pr_debug("fsl-pq-mdio: no UCC ID in node %s\n", 284afae5ad7STimur Tabi np->full_name); 285afae5ad7STimur Tabi continue; 286afae5ad7STimur Tabi } 287afae5ad7STimur Tabi } 288afae5ad7STimur Tabi 289afae5ad7STimur Tabi id = be32_to_cpup(iprop); 290afae5ad7STimur Tabi 291afae5ad7STimur Tabi /* 292afae5ad7STimur Tabi * cell-index and device-id for QE nodes are 293afae5ad7STimur Tabi * numbered from 1, not 0. 294afae5ad7STimur Tabi */ 295afae5ad7STimur Tabi if (ucc_set_qe_mux_mii_mng(id - 1) < 0) { 296afae5ad7STimur Tabi pr_debug("fsl-pq-mdio: invalid UCC ID in node %s\n", 297afae5ad7STimur Tabi np->full_name); 298ec21e2ecSJeff Kirsher continue; 299ec21e2ecSJeff Kirsher } 300ec21e2ecSJeff Kirsher 301afae5ad7STimur Tabi pr_debug("fsl-pq-mdio: setting node UCC%u to MII master\n", id); 302afae5ad7STimur Tabi found_mii_master = true; 303ec21e2ecSJeff Kirsher } 304ec21e2ecSJeff Kirsher } 305ec21e2ecSJeff Kirsher 306ec21e2ecSJeff Kirsher #endif 307afae5ad7STimur Tabi 30894e5a2a8SFabian Frederick static const struct of_device_id fsl_pq_mdio_match[] = { 309504e76e5SJavier Martinez Canillas #if IS_ENABLED(CONFIG_GIANFAR) 310afae5ad7STimur Tabi { 311afae5ad7STimur Tabi .compatible = "fsl,gianfar-tbi", 312afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 313afae5ad7STimur Tabi .mii_offset = 0, 3143bb35ac4SGerlando Falauto .get_tbipa = get_gfar_tbipa_from_mii, 315afae5ad7STimur Tabi }, 316afae5ad7STimur Tabi }, 317afae5ad7STimur Tabi { 318afae5ad7STimur Tabi .compatible = "fsl,gianfar-mdio", 319afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 320afae5ad7STimur Tabi .mii_offset = 0, 3213bb35ac4SGerlando Falauto .get_tbipa = get_gfar_tbipa_from_mii, 322afae5ad7STimur Tabi }, 323afae5ad7STimur Tabi }, 324afae5ad7STimur Tabi { 325afae5ad7STimur Tabi .type = "mdio", 326afae5ad7STimur Tabi .compatible = "gianfar", 327afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 328afae5ad7STimur Tabi .mii_offset = offsetof(struct fsl_pq_mdio, mii), 3293bb35ac4SGerlando Falauto .get_tbipa = get_gfar_tbipa_from_mdio, 330afae5ad7STimur Tabi }, 331afae5ad7STimur Tabi }, 332afae5ad7STimur Tabi { 333afae5ad7STimur Tabi .compatible = "fsl,etsec2-tbi", 334afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 335afae5ad7STimur Tabi .mii_offset = offsetof(struct fsl_pq_mdio, mii), 336afae5ad7STimur Tabi .get_tbipa = get_etsec_tbipa, 337afae5ad7STimur Tabi }, 338afae5ad7STimur Tabi }, 339afae5ad7STimur Tabi { 340afae5ad7STimur Tabi .compatible = "fsl,etsec2-mdio", 341afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 342afae5ad7STimur Tabi .mii_offset = offsetof(struct fsl_pq_mdio, mii), 343afae5ad7STimur Tabi .get_tbipa = get_etsec_tbipa, 344afae5ad7STimur Tabi }, 345afae5ad7STimur Tabi }, 346afae5ad7STimur Tabi #endif 347504e76e5SJavier Martinez Canillas #if IS_ENABLED(CONFIG_UCC_GETH) 348afae5ad7STimur Tabi { 349afae5ad7STimur Tabi .compatible = "fsl,ucc-mdio", 350afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 351afae5ad7STimur Tabi .mii_offset = 0, 352afae5ad7STimur Tabi .get_tbipa = get_ucc_tbipa, 353afae5ad7STimur Tabi .ucc_configure = ucc_configure, 354afae5ad7STimur Tabi }, 355afae5ad7STimur Tabi }, 356afae5ad7STimur Tabi { 357afae5ad7STimur Tabi /* Legacy UCC MDIO node */ 358afae5ad7STimur Tabi .type = "mdio", 359afae5ad7STimur Tabi .compatible = "ucc_geth_phy", 360afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) { 361afae5ad7STimur Tabi .mii_offset = 0, 362afae5ad7STimur Tabi .get_tbipa = get_ucc_tbipa, 363afae5ad7STimur Tabi .ucc_configure = ucc_configure, 364afae5ad7STimur Tabi }, 365afae5ad7STimur Tabi }, 366afae5ad7STimur Tabi #endif 367761743ebSTimur Tabi /* No Kconfig option for Fman support yet */ 368761743ebSTimur Tabi { 369761743ebSTimur Tabi .compatible = "fsl,fman-mdio", 370761743ebSTimur Tabi .data = &(struct fsl_pq_mdio_data) { 371761743ebSTimur Tabi .mii_offset = 0, 372761743ebSTimur Tabi /* Fman TBI operations are handled elsewhere */ 373761743ebSTimur Tabi }, 374761743ebSTimur Tabi }, 375761743ebSTimur Tabi 376afae5ad7STimur Tabi {}, 377afae5ad7STimur Tabi }; 378afae5ad7STimur Tabi MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match); 379ec21e2ecSJeff Kirsher 3805078ac79STimur Tabi static int fsl_pq_mdio_probe(struct platform_device *pdev) 381ec21e2ecSJeff Kirsher { 382afae5ad7STimur Tabi const struct of_device_id *id = 383afae5ad7STimur Tabi of_match_device(fsl_pq_mdio_match, &pdev->dev); 384afae5ad7STimur Tabi const struct fsl_pq_mdio_data *data = id->data; 3855078ac79STimur Tabi struct device_node *np = pdev->dev.of_node; 386afae5ad7STimur Tabi struct resource res; 387ec21e2ecSJeff Kirsher struct device_node *tbi; 388ec21e2ecSJeff Kirsher struct fsl_pq_mdio_priv *priv; 389ec21e2ecSJeff Kirsher struct mii_bus *new_bus; 390ec21e2ecSJeff Kirsher int err; 391ec21e2ecSJeff Kirsher 392afae5ad7STimur Tabi dev_dbg(&pdev->dev, "found %s compatible node\n", id->compatible); 393afae5ad7STimur Tabi 394dd3b8a32STimur Tabi new_bus = mdiobus_alloc_size(sizeof(*priv)); 395dd3b8a32STimur Tabi if (!new_bus) 396ec21e2ecSJeff Kirsher return -ENOMEM; 397ec21e2ecSJeff Kirsher 398dd3b8a32STimur Tabi priv = new_bus->priv; 399ec21e2ecSJeff Kirsher new_bus->name = "Freescale PowerQUICC MII Bus", 4005078ac79STimur Tabi new_bus->read = &fsl_pq_mdio_read; 4015078ac79STimur Tabi new_bus->write = &fsl_pq_mdio_write; 4025078ac79STimur Tabi new_bus->reset = &fsl_pq_mdio_reset; 403ec21e2ecSJeff Kirsher 404afae5ad7STimur Tabi err = of_address_to_resource(np, 0, &res); 405afae5ad7STimur Tabi if (err < 0) { 406afae5ad7STimur Tabi dev_err(&pdev->dev, "could not obtain address information\n"); 407dd3b8a32STimur Tabi goto error; 408ec21e2ecSJeff Kirsher } 409ec21e2ecSJeff Kirsher 41069cfb419STimur Tabi snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s@%llx", np->name, 411afae5ad7STimur Tabi (unsigned long long)res.start); 41269cfb419STimur Tabi 413afae5ad7STimur Tabi priv->map = of_iomap(np, 0); 414afae5ad7STimur Tabi if (!priv->map) { 415ec21e2ecSJeff Kirsher err = -ENOMEM; 416dd3b8a32STimur Tabi goto error; 417ec21e2ecSJeff Kirsher } 418ec21e2ecSJeff Kirsher 419afae5ad7STimur Tabi /* 420afae5ad7STimur Tabi * Some device tree nodes represent only the MII registers, and 421afae5ad7STimur Tabi * others represent the MAC and MII registers. The 'mii_offset' field 422afae5ad7STimur Tabi * contains the offset of the MII registers inside the mapped register 423afae5ad7STimur Tabi * space. 424afae5ad7STimur Tabi */ 425afae5ad7STimur Tabi if (data->mii_offset > resource_size(&res)) { 426afae5ad7STimur Tabi dev_err(&pdev->dev, "invalid register map\n"); 427afae5ad7STimur Tabi err = -EINVAL; 428dd3b8a32STimur Tabi goto error; 429afae5ad7STimur Tabi } 430afae5ad7STimur Tabi priv->regs = priv->map + data->mii_offset; 431ec21e2ecSJeff Kirsher 4325078ac79STimur Tabi new_bus->parent = &pdev->dev; 433a0e18600SLibo Chen platform_set_drvdata(pdev, new_bus); 434ec21e2ecSJeff Kirsher 435afae5ad7STimur Tabi if (data->get_tbipa) { 436ec21e2ecSJeff Kirsher for_each_child_of_node(np, tbi) { 437afae5ad7STimur Tabi if (strcmp(tbi->type, "tbi-phy") == 0) { 438afae5ad7STimur Tabi dev_dbg(&pdev->dev, "found TBI PHY node %s\n", 439afae5ad7STimur Tabi strrchr(tbi->full_name, '/') + 1); 440ec21e2ecSJeff Kirsher break; 441ec21e2ecSJeff Kirsher } 442afae5ad7STimur Tabi } 443ec21e2ecSJeff Kirsher 444ec21e2ecSJeff Kirsher if (tbi) { 445ec21e2ecSJeff Kirsher const u32 *prop = of_get_property(tbi, "reg", NULL); 446afae5ad7STimur Tabi uint32_t __iomem *tbipa; 447ec21e2ecSJeff Kirsher 448afae5ad7STimur Tabi if (!prop) { 449afae5ad7STimur Tabi dev_err(&pdev->dev, 450afae5ad7STimur Tabi "missing 'reg' property in node %s\n", 451afae5ad7STimur Tabi tbi->full_name); 452ec21e2ecSJeff Kirsher err = -EBUSY; 453afae5ad7STimur Tabi goto error; 454afae5ad7STimur Tabi } 455afae5ad7STimur Tabi 456afae5ad7STimur Tabi tbipa = data->get_tbipa(priv->map); 457afae5ad7STimur Tabi 4583dd03e52SGerlando Falauto /* 4593dd03e52SGerlando Falauto * Add consistency check to make sure TBI is contained 4603dd03e52SGerlando Falauto * within the mapped range (not because we would get a 4613dd03e52SGerlando Falauto * segfault, rather to catch bugs in computing TBI 4623dd03e52SGerlando Falauto * address). Print error message but continue anyway. 4633dd03e52SGerlando Falauto */ 4643dd03e52SGerlando Falauto if ((void *)tbipa > priv->map + resource_size(&res) - 4) 4658cde3e44SArnd Bergmann dev_err(&pdev->dev, "invalid register map (should be at least 0x%04zx to contain TBI address)\n", 4663dd03e52SGerlando Falauto ((void *)tbipa - priv->map) + 4); 4673dd03e52SGerlando Falauto 468f5bbd262SClaudiu Manoil iowrite32be(be32_to_cpup(prop), tbipa); 469c3e072f8SBaruch Siach } 470464b57daSKenth Eriksson } 471ec21e2ecSJeff Kirsher 472afae5ad7STimur Tabi if (data->ucc_configure) 473afae5ad7STimur Tabi data->ucc_configure(res.start, res.end); 474afae5ad7STimur Tabi 475ec21e2ecSJeff Kirsher err = of_mdiobus_register(new_bus, np); 476ec21e2ecSJeff Kirsher if (err) { 4775078ac79STimur Tabi dev_err(&pdev->dev, "cannot register %s as MDIO bus\n", 478ec21e2ecSJeff Kirsher new_bus->name); 479dd3b8a32STimur Tabi goto error; 480ec21e2ecSJeff Kirsher } 481ec21e2ecSJeff Kirsher 482ec21e2ecSJeff Kirsher return 0; 483ec21e2ecSJeff Kirsher 484dd3b8a32STimur Tabi error: 485dd3b8a32STimur Tabi if (priv->map) 486ec21e2ecSJeff Kirsher iounmap(priv->map); 487dd3b8a32STimur Tabi 488ec21e2ecSJeff Kirsher kfree(new_bus); 489dd3b8a32STimur Tabi 490ec21e2ecSJeff Kirsher return err; 491ec21e2ecSJeff Kirsher } 492ec21e2ecSJeff Kirsher 493ec21e2ecSJeff Kirsher 4945078ac79STimur Tabi static int fsl_pq_mdio_remove(struct platform_device *pdev) 495ec21e2ecSJeff Kirsher { 4965078ac79STimur Tabi struct device *device = &pdev->dev; 497ec21e2ecSJeff Kirsher struct mii_bus *bus = dev_get_drvdata(device); 498ec21e2ecSJeff Kirsher struct fsl_pq_mdio_priv *priv = bus->priv; 499ec21e2ecSJeff Kirsher 500ec21e2ecSJeff Kirsher mdiobus_unregister(bus); 501ec21e2ecSJeff Kirsher 502ec21e2ecSJeff Kirsher iounmap(priv->map); 503ec21e2ecSJeff Kirsher mdiobus_free(bus); 504ec21e2ecSJeff Kirsher 505ec21e2ecSJeff Kirsher return 0; 506ec21e2ecSJeff Kirsher } 507ec21e2ecSJeff Kirsher 508ec21e2ecSJeff Kirsher static struct platform_driver fsl_pq_mdio_driver = { 509ec21e2ecSJeff Kirsher .driver = { 510ec21e2ecSJeff Kirsher .name = "fsl-pq_mdio", 511ec21e2ecSJeff Kirsher .of_match_table = fsl_pq_mdio_match, 512ec21e2ecSJeff Kirsher }, 513ec21e2ecSJeff Kirsher .probe = fsl_pq_mdio_probe, 514ec21e2ecSJeff Kirsher .remove = fsl_pq_mdio_remove, 515ec21e2ecSJeff Kirsher }; 516ec21e2ecSJeff Kirsher 517db62f684SAxel Lin module_platform_driver(fsl_pq_mdio_driver); 518ec21e2ecSJeff Kirsher 519ec21e2ecSJeff Kirsher MODULE_LICENSE("GPL"); 520