1 /* 2 * Ethernet on Serial Communications Controller (SCC) driver for Motorola MPC8xx and MPC82xx. 3 * 4 * Copyright (c) 2003 Intracom S.A. 5 * by Pantelis Antoniou <panto@intracom.gr> 6 * 7 * 2005 (c) MontaVista Software, Inc. 8 * Vitaly Bordug <vbordug@ru.mvista.com> 9 * 10 * This file is licensed under the terms of the GNU General Public License 11 * version 2. This program is licensed "as is" without any warranty of any 12 * kind, whether express or implied. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/types.h> 18 #include <linux/string.h> 19 #include <linux/ptrace.h> 20 #include <linux/errno.h> 21 #include <linux/ioport.h> 22 #include <linux/interrupt.h> 23 #include <linux/delay.h> 24 #include <linux/netdevice.h> 25 #include <linux/etherdevice.h> 26 #include <linux/skbuff.h> 27 #include <linux/spinlock.h> 28 #include <linux/mii.h> 29 #include <linux/ethtool.h> 30 #include <linux/bitops.h> 31 #include <linux/fs.h> 32 #include <linux/platform_device.h> 33 #include <linux/of_address.h> 34 #include <linux/of_irq.h> 35 #include <linux/of_platform.h> 36 37 #include <asm/irq.h> 38 #include <asm/uaccess.h> 39 40 #ifdef CONFIG_8xx 41 #include <asm/8xx_immap.h> 42 #include <asm/pgtable.h> 43 #include <asm/mpc8xx.h> 44 #include <asm/cpm1.h> 45 #endif 46 47 #include "fs_enet.h" 48 49 /*************************************************/ 50 #if defined(CONFIG_CPM1) 51 /* for a 8xx __raw_xxx's are sufficient */ 52 #define __fs_out32(addr, x) __raw_writel(x, addr) 53 #define __fs_out16(addr, x) __raw_writew(x, addr) 54 #define __fs_out8(addr, x) __raw_writeb(x, addr) 55 #define __fs_in32(addr) __raw_readl(addr) 56 #define __fs_in16(addr) __raw_readw(addr) 57 #define __fs_in8(addr) __raw_readb(addr) 58 #else 59 /* for others play it safe */ 60 #define __fs_out32(addr, x) out_be32(addr, x) 61 #define __fs_out16(addr, x) out_be16(addr, x) 62 #define __fs_in32(addr) in_be32(addr) 63 #define __fs_in16(addr) in_be16(addr) 64 #define __fs_out8(addr, x) out_8(addr, x) 65 #define __fs_in8(addr) in_8(addr) 66 #endif 67 68 /* write, read, set bits, clear bits */ 69 #define W32(_p, _m, _v) __fs_out32(&(_p)->_m, (_v)) 70 #define R32(_p, _m) __fs_in32(&(_p)->_m) 71 #define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) | (_v)) 72 #define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v)) 73 74 #define W16(_p, _m, _v) __fs_out16(&(_p)->_m, (_v)) 75 #define R16(_p, _m) __fs_in16(&(_p)->_m) 76 #define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) | (_v)) 77 #define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v)) 78 79 #define W8(_p, _m, _v) __fs_out8(&(_p)->_m, (_v)) 80 #define R8(_p, _m) __fs_in8(&(_p)->_m) 81 #define S8(_p, _m, _v) W8(_p, _m, R8(_p, _m) | (_v)) 82 #define C8(_p, _m, _v) W8(_p, _m, R8(_p, _m) & ~(_v)) 83 84 #define SCC_MAX_MULTICAST_ADDRS 64 85 86 /* 87 * Delay to wait for SCC reset command to complete (in us) 88 */ 89 #define SCC_RESET_DELAY 50 90 91 static inline int scc_cr_cmd(struct fs_enet_private *fep, u32 op) 92 { 93 const struct fs_platform_info *fpi = fep->fpi; 94 95 return cpm_command(fpi->cp_command, op); 96 } 97 98 static int do_pd_setup(struct fs_enet_private *fep) 99 { 100 struct platform_device *ofdev = to_platform_device(fep->dev); 101 102 fep->interrupt = irq_of_parse_and_map(ofdev->dev.of_node, 0); 103 if (fep->interrupt == NO_IRQ) 104 return -EINVAL; 105 106 fep->scc.sccp = of_iomap(ofdev->dev.of_node, 0); 107 if (!fep->scc.sccp) 108 return -EINVAL; 109 110 fep->scc.ep = of_iomap(ofdev->dev.of_node, 1); 111 if (!fep->scc.ep) { 112 iounmap(fep->scc.sccp); 113 return -EINVAL; 114 } 115 116 return 0; 117 } 118 119 #define SCC_NAPI_RX_EVENT_MSK (SCCE_ENET_RXF | SCCE_ENET_RXB) 120 #define SCC_RX_EVENT (SCCE_ENET_RXF) 121 #define SCC_TX_EVENT (SCCE_ENET_TXB) 122 #define SCC_ERR_EVENT_MSK (SCCE_ENET_TXE | SCCE_ENET_BSY) 123 124 static int setup_data(struct net_device *dev) 125 { 126 struct fs_enet_private *fep = netdev_priv(dev); 127 128 do_pd_setup(fep); 129 130 fep->scc.hthi = 0; 131 fep->scc.htlo = 0; 132 133 fep->ev_napi_rx = SCC_NAPI_RX_EVENT_MSK; 134 fep->ev_rx = SCC_RX_EVENT; 135 fep->ev_tx = SCC_TX_EVENT | SCCE_ENET_TXE; 136 fep->ev_err = SCC_ERR_EVENT_MSK; 137 138 return 0; 139 } 140 141 static int allocate_bd(struct net_device *dev) 142 { 143 struct fs_enet_private *fep = netdev_priv(dev); 144 const struct fs_platform_info *fpi = fep->fpi; 145 146 fep->ring_mem_addr = cpm_dpalloc((fpi->tx_ring + fpi->rx_ring) * 147 sizeof(cbd_t), 8); 148 if (IS_ERR_VALUE(fep->ring_mem_addr)) 149 return -ENOMEM; 150 151 fep->ring_base = (void __iomem __force*) 152 cpm_dpram_addr(fep->ring_mem_addr); 153 154 return 0; 155 } 156 157 static void free_bd(struct net_device *dev) 158 { 159 struct fs_enet_private *fep = netdev_priv(dev); 160 161 if (fep->ring_base) 162 cpm_dpfree(fep->ring_mem_addr); 163 } 164 165 static void cleanup_data(struct net_device *dev) 166 { 167 /* nothing */ 168 } 169 170 static void set_promiscuous_mode(struct net_device *dev) 171 { 172 struct fs_enet_private *fep = netdev_priv(dev); 173 scc_t __iomem *sccp = fep->scc.sccp; 174 175 S16(sccp, scc_psmr, SCC_PSMR_PRO); 176 } 177 178 static void set_multicast_start(struct net_device *dev) 179 { 180 struct fs_enet_private *fep = netdev_priv(dev); 181 scc_enet_t __iomem *ep = fep->scc.ep; 182 183 W16(ep, sen_gaddr1, 0); 184 W16(ep, sen_gaddr2, 0); 185 W16(ep, sen_gaddr3, 0); 186 W16(ep, sen_gaddr4, 0); 187 } 188 189 static void set_multicast_one(struct net_device *dev, const u8 * mac) 190 { 191 struct fs_enet_private *fep = netdev_priv(dev); 192 scc_enet_t __iomem *ep = fep->scc.ep; 193 u16 taddrh, taddrm, taddrl; 194 195 taddrh = ((u16) mac[5] << 8) | mac[4]; 196 taddrm = ((u16) mac[3] << 8) | mac[2]; 197 taddrl = ((u16) mac[1] << 8) | mac[0]; 198 199 W16(ep, sen_taddrh, taddrh); 200 W16(ep, sen_taddrm, taddrm); 201 W16(ep, sen_taddrl, taddrl); 202 scc_cr_cmd(fep, CPM_CR_SET_GADDR); 203 } 204 205 static void set_multicast_finish(struct net_device *dev) 206 { 207 struct fs_enet_private *fep = netdev_priv(dev); 208 scc_t __iomem *sccp = fep->scc.sccp; 209 scc_enet_t __iomem *ep = fep->scc.ep; 210 211 /* clear promiscuous always */ 212 C16(sccp, scc_psmr, SCC_PSMR_PRO); 213 214 /* if all multi or too many multicasts; just enable all */ 215 if ((dev->flags & IFF_ALLMULTI) != 0 || 216 netdev_mc_count(dev) > SCC_MAX_MULTICAST_ADDRS) { 217 218 W16(ep, sen_gaddr1, 0xffff); 219 W16(ep, sen_gaddr2, 0xffff); 220 W16(ep, sen_gaddr3, 0xffff); 221 W16(ep, sen_gaddr4, 0xffff); 222 } 223 } 224 225 static void set_multicast_list(struct net_device *dev) 226 { 227 struct netdev_hw_addr *ha; 228 229 if ((dev->flags & IFF_PROMISC) == 0) { 230 set_multicast_start(dev); 231 netdev_for_each_mc_addr(ha, dev) 232 set_multicast_one(dev, ha->addr); 233 set_multicast_finish(dev); 234 } else 235 set_promiscuous_mode(dev); 236 } 237 238 /* 239 * This function is called to start or restart the FEC during a link 240 * change. This only happens when switching between half and full 241 * duplex. 242 */ 243 static void restart(struct net_device *dev) 244 { 245 struct fs_enet_private *fep = netdev_priv(dev); 246 scc_t __iomem *sccp = fep->scc.sccp; 247 scc_enet_t __iomem *ep = fep->scc.ep; 248 const struct fs_platform_info *fpi = fep->fpi; 249 u16 paddrh, paddrm, paddrl; 250 const unsigned char *mac; 251 int i; 252 253 C32(sccp, scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 254 255 /* clear everything (slow & steady does it) */ 256 for (i = 0; i < sizeof(*ep); i++) 257 __fs_out8((u8 __iomem *)ep + i, 0); 258 259 /* point to bds */ 260 W16(ep, sen_genscc.scc_rbase, fep->ring_mem_addr); 261 W16(ep, sen_genscc.scc_tbase, 262 fep->ring_mem_addr + sizeof(cbd_t) * fpi->rx_ring); 263 264 /* Initialize function code registers for big-endian. 265 */ 266 #ifndef CONFIG_NOT_COHERENT_CACHE 267 W8(ep, sen_genscc.scc_rfcr, SCC_EB | SCC_GBL); 268 W8(ep, sen_genscc.scc_tfcr, SCC_EB | SCC_GBL); 269 #else 270 W8(ep, sen_genscc.scc_rfcr, SCC_EB); 271 W8(ep, sen_genscc.scc_tfcr, SCC_EB); 272 #endif 273 274 /* Set maximum bytes per receive buffer. 275 * This appears to be an Ethernet frame size, not the buffer 276 * fragment size. It must be a multiple of four. 277 */ 278 W16(ep, sen_genscc.scc_mrblr, 0x5f0); 279 280 /* Set CRC preset and mask. 281 */ 282 W32(ep, sen_cpres, 0xffffffff); 283 W32(ep, sen_cmask, 0xdebb20e3); 284 285 W32(ep, sen_crcec, 0); /* CRC Error counter */ 286 W32(ep, sen_alec, 0); /* alignment error counter */ 287 W32(ep, sen_disfc, 0); /* discard frame counter */ 288 289 W16(ep, sen_pads, 0x8888); /* Tx short frame pad character */ 290 W16(ep, sen_retlim, 15); /* Retry limit threshold */ 291 292 W16(ep, sen_maxflr, 0x5ee); /* maximum frame length register */ 293 294 W16(ep, sen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */ 295 296 W16(ep, sen_maxd1, 0x000005f0); /* maximum DMA1 length */ 297 W16(ep, sen_maxd2, 0x000005f0); /* maximum DMA2 length */ 298 299 /* Clear hash tables. 300 */ 301 W16(ep, sen_gaddr1, 0); 302 W16(ep, sen_gaddr2, 0); 303 W16(ep, sen_gaddr3, 0); 304 W16(ep, sen_gaddr4, 0); 305 W16(ep, sen_iaddr1, 0); 306 W16(ep, sen_iaddr2, 0); 307 W16(ep, sen_iaddr3, 0); 308 W16(ep, sen_iaddr4, 0); 309 310 /* set address 311 */ 312 mac = dev->dev_addr; 313 paddrh = ((u16) mac[5] << 8) | mac[4]; 314 paddrm = ((u16) mac[3] << 8) | mac[2]; 315 paddrl = ((u16) mac[1] << 8) | mac[0]; 316 317 W16(ep, sen_paddrh, paddrh); 318 W16(ep, sen_paddrm, paddrm); 319 W16(ep, sen_paddrl, paddrl); 320 321 W16(ep, sen_pper, 0); 322 W16(ep, sen_taddrl, 0); 323 W16(ep, sen_taddrm, 0); 324 W16(ep, sen_taddrh, 0); 325 326 fs_init_bds(dev); 327 328 scc_cr_cmd(fep, CPM_CR_INIT_TRX); 329 330 W16(sccp, scc_scce, 0xffff); 331 332 /* Enable interrupts we wish to service. 333 */ 334 W16(sccp, scc_sccm, SCCE_ENET_TXE | SCCE_ENET_RXF | SCCE_ENET_TXB); 335 336 /* Set GSMR_H to enable all normal operating modes. 337 * Set GSMR_L to enable Ethernet to MC68160. 338 */ 339 W32(sccp, scc_gsmrh, 0); 340 W32(sccp, scc_gsmrl, 341 SCC_GSMRL_TCI | SCC_GSMRL_TPL_48 | SCC_GSMRL_TPP_10 | 342 SCC_GSMRL_MODE_ENET); 343 344 /* Set sync/delimiters. 345 */ 346 W16(sccp, scc_dsr, 0xd555); 347 348 /* Set processing mode. Use Ethernet CRC, catch broadcast, and 349 * start frame search 22 bit times after RENA. 350 */ 351 W16(sccp, scc_psmr, SCC_PSMR_ENCRC | SCC_PSMR_NIB22); 352 353 /* Set full duplex mode if needed */ 354 if (fep->phydev->duplex) 355 S16(sccp, scc_psmr, SCC_PSMR_LPB | SCC_PSMR_FDE); 356 357 S32(sccp, scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 358 } 359 360 static void stop(struct net_device *dev) 361 { 362 struct fs_enet_private *fep = netdev_priv(dev); 363 scc_t __iomem *sccp = fep->scc.sccp; 364 int i; 365 366 for (i = 0; (R16(sccp, scc_sccm) == 0) && i < SCC_RESET_DELAY; i++) 367 udelay(1); 368 369 if (i == SCC_RESET_DELAY) 370 dev_warn(fep->dev, "SCC timeout on graceful transmit stop\n"); 371 372 W16(sccp, scc_sccm, 0); 373 C32(sccp, scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 374 375 fs_cleanup_bds(dev); 376 } 377 378 static void napi_clear_rx_event(struct net_device *dev) 379 { 380 struct fs_enet_private *fep = netdev_priv(dev); 381 scc_t __iomem *sccp = fep->scc.sccp; 382 383 W16(sccp, scc_scce, SCC_NAPI_RX_EVENT_MSK); 384 } 385 386 static void napi_enable_rx(struct net_device *dev) 387 { 388 struct fs_enet_private *fep = netdev_priv(dev); 389 scc_t __iomem *sccp = fep->scc.sccp; 390 391 S16(sccp, scc_sccm, SCC_NAPI_RX_EVENT_MSK); 392 } 393 394 static void napi_disable_rx(struct net_device *dev) 395 { 396 struct fs_enet_private *fep = netdev_priv(dev); 397 scc_t __iomem *sccp = fep->scc.sccp; 398 399 C16(sccp, scc_sccm, SCC_NAPI_RX_EVENT_MSK); 400 } 401 402 static void rx_bd_done(struct net_device *dev) 403 { 404 /* nothing */ 405 } 406 407 static void tx_kickstart(struct net_device *dev) 408 { 409 /* nothing */ 410 } 411 412 static u32 get_int_events(struct net_device *dev) 413 { 414 struct fs_enet_private *fep = netdev_priv(dev); 415 scc_t __iomem *sccp = fep->scc.sccp; 416 417 return (u32) R16(sccp, scc_scce); 418 } 419 420 static void clear_int_events(struct net_device *dev, u32 int_events) 421 { 422 struct fs_enet_private *fep = netdev_priv(dev); 423 scc_t __iomem *sccp = fep->scc.sccp; 424 425 W16(sccp, scc_scce, int_events & 0xffff); 426 } 427 428 static void ev_error(struct net_device *dev, u32 int_events) 429 { 430 struct fs_enet_private *fep = netdev_priv(dev); 431 432 dev_warn(fep->dev, "SCC ERROR(s) 0x%x\n", int_events); 433 } 434 435 static int get_regs(struct net_device *dev, void *p, int *sizep) 436 { 437 struct fs_enet_private *fep = netdev_priv(dev); 438 439 if (*sizep < sizeof(scc_t) + sizeof(scc_enet_t __iomem *)) 440 return -EINVAL; 441 442 memcpy_fromio(p, fep->scc.sccp, sizeof(scc_t)); 443 p = (char *)p + sizeof(scc_t); 444 445 memcpy_fromio(p, fep->scc.ep, sizeof(scc_enet_t __iomem *)); 446 447 return 0; 448 } 449 450 static int get_regs_len(struct net_device *dev) 451 { 452 return sizeof(scc_t) + sizeof(scc_enet_t __iomem *); 453 } 454 455 static void tx_restart(struct net_device *dev) 456 { 457 struct fs_enet_private *fep = netdev_priv(dev); 458 459 scc_cr_cmd(fep, CPM_CR_RESTART_TX); 460 } 461 462 463 464 /*************************************************************************/ 465 466 const struct fs_ops fs_scc_ops = { 467 .setup_data = setup_data, 468 .cleanup_data = cleanup_data, 469 .set_multicast_list = set_multicast_list, 470 .restart = restart, 471 .stop = stop, 472 .napi_clear_rx_event = napi_clear_rx_event, 473 .napi_enable_rx = napi_enable_rx, 474 .napi_disable_rx = napi_disable_rx, 475 .rx_bd_done = rx_bd_done, 476 .tx_kickstart = tx_kickstart, 477 .get_int_events = get_int_events, 478 .clear_int_events = clear_int_events, 479 .ev_error = ev_error, 480 .get_regs = get_regs, 481 .get_regs_len = get_regs_len, 482 .tx_restart = tx_restart, 483 .allocate_bd = allocate_bd, 484 .free_bd = free_bd, 485 }; 486