1 /* 2 * FCC driver for Motorola MPC82xx (PQ2). 3 * 4 * Copyright (c) 2003 Intracom S.A. 5 * by Pantelis Antoniou <panto@intracom.gr> 6 * 7 * 2005 (c) MontaVista Software, Inc. 8 * Vitaly Bordug <vbordug@ru.mvista.com> 9 * 10 * This file is licensed under the terms of the GNU General Public License 11 * version 2. This program is licensed "as is" without any warranty of any 12 * kind, whether express or implied. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/types.h> 18 #include <linux/string.h> 19 #include <linux/ptrace.h> 20 #include <linux/errno.h> 21 #include <linux/ioport.h> 22 #include <linux/interrupt.h> 23 #include <linux/delay.h> 24 #include <linux/netdevice.h> 25 #include <linux/etherdevice.h> 26 #include <linux/skbuff.h> 27 #include <linux/spinlock.h> 28 #include <linux/mii.h> 29 #include <linux/ethtool.h> 30 #include <linux/bitops.h> 31 #include <linux/fs.h> 32 #include <linux/platform_device.h> 33 #include <linux/phy.h> 34 #include <linux/of_address.h> 35 #include <linux/of_irq.h> 36 #include <linux/gfp.h> 37 #include <linux/pgtable.h> 38 39 #include <asm/immap_cpm2.h> 40 #include <asm/mpc8260.h> 41 #include <asm/cpm2.h> 42 43 #include <asm/irq.h> 44 #include <linux/uaccess.h> 45 46 #include "fs_enet.h" 47 48 /*************************************************/ 49 50 /* FCC access macros */ 51 52 /* write, read, set bits, clear bits */ 53 #define W32(_p, _m, _v) out_be32(&(_p)->_m, (_v)) 54 #define R32(_p, _m) in_be32(&(_p)->_m) 55 #define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) | (_v)) 56 #define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v)) 57 58 #define W16(_p, _m, _v) out_be16(&(_p)->_m, (_v)) 59 #define R16(_p, _m) in_be16(&(_p)->_m) 60 #define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) | (_v)) 61 #define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v)) 62 63 #define W8(_p, _m, _v) out_8(&(_p)->_m, (_v)) 64 #define R8(_p, _m) in_8(&(_p)->_m) 65 #define S8(_p, _m, _v) W8(_p, _m, R8(_p, _m) | (_v)) 66 #define C8(_p, _m, _v) W8(_p, _m, R8(_p, _m) & ~(_v)) 67 68 /*************************************************/ 69 70 #define FCC_MAX_MULTICAST_ADDRS 64 71 72 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) 73 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) 74 #define mk_mii_end 0 75 76 #define MAX_CR_CMD_LOOPS 10000 77 78 static inline int fcc_cr_cmd(struct fs_enet_private *fep, u32 op) 79 { 80 const struct fs_platform_info *fpi = fep->fpi; 81 82 return cpm_command(fpi->cp_command, op); 83 } 84 85 static int do_pd_setup(struct fs_enet_private *fep) 86 { 87 struct platform_device *ofdev = to_platform_device(fep->dev); 88 struct fs_platform_info *fpi = fep->fpi; 89 int ret = -EINVAL; 90 91 fep->interrupt = irq_of_parse_and_map(ofdev->dev.of_node, 0); 92 if (!fep->interrupt) 93 goto out; 94 95 fep->fcc.fccp = of_iomap(ofdev->dev.of_node, 0); 96 if (!fep->fcc.fccp) 97 goto out; 98 99 fep->fcc.ep = of_iomap(ofdev->dev.of_node, 1); 100 if (!fep->fcc.ep) 101 goto out_fccp; 102 103 fep->fcc.fcccp = of_iomap(ofdev->dev.of_node, 2); 104 if (!fep->fcc.fcccp) 105 goto out_ep; 106 107 fep->fcc.mem = (void __iomem *)cpm2_immr; 108 fpi->dpram_offset = cpm_muram_alloc(128, 32); 109 if (IS_ERR_VALUE(fpi->dpram_offset)) { 110 ret = fpi->dpram_offset; 111 goto out_fcccp; 112 } 113 114 return 0; 115 116 out_fcccp: 117 iounmap(fep->fcc.fcccp); 118 out_ep: 119 iounmap(fep->fcc.ep); 120 out_fccp: 121 iounmap(fep->fcc.fccp); 122 out: 123 return ret; 124 } 125 126 #define FCC_NAPI_EVENT_MSK (FCC_ENET_RXF | FCC_ENET_RXB | FCC_ENET_TXB) 127 #define FCC_EVENT (FCC_ENET_RXF | FCC_ENET_TXB) 128 #define FCC_ERR_EVENT_MSK (FCC_ENET_TXE) 129 130 static int setup_data(struct net_device *dev) 131 { 132 struct fs_enet_private *fep = netdev_priv(dev); 133 134 if (do_pd_setup(fep) != 0) 135 return -EINVAL; 136 137 fep->ev_napi = FCC_NAPI_EVENT_MSK; 138 fep->ev = FCC_EVENT; 139 fep->ev_err = FCC_ERR_EVENT_MSK; 140 141 return 0; 142 } 143 144 static int allocate_bd(struct net_device *dev) 145 { 146 struct fs_enet_private *fep = netdev_priv(dev); 147 const struct fs_platform_info *fpi = fep->fpi; 148 149 fep->ring_base = (void __iomem __force *)dma_alloc_coherent(fep->dev, 150 (fpi->tx_ring + fpi->rx_ring) * 151 sizeof(cbd_t), &fep->ring_mem_addr, 152 GFP_KERNEL); 153 if (fep->ring_base == NULL) 154 return -ENOMEM; 155 156 return 0; 157 } 158 159 static void free_bd(struct net_device *dev) 160 { 161 struct fs_enet_private *fep = netdev_priv(dev); 162 const struct fs_platform_info *fpi = fep->fpi; 163 164 if (fep->ring_base) 165 dma_free_coherent(fep->dev, 166 (fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t), 167 (void __force *)fep->ring_base, fep->ring_mem_addr); 168 } 169 170 static void cleanup_data(struct net_device *dev) 171 { 172 /* nothing */ 173 } 174 175 static void set_promiscuous_mode(struct net_device *dev) 176 { 177 struct fs_enet_private *fep = netdev_priv(dev); 178 fcc_t __iomem *fccp = fep->fcc.fccp; 179 180 S32(fccp, fcc_fpsmr, FCC_PSMR_PRO); 181 } 182 183 static void set_multicast_start(struct net_device *dev) 184 { 185 struct fs_enet_private *fep = netdev_priv(dev); 186 fcc_enet_t __iomem *ep = fep->fcc.ep; 187 188 W32(ep, fen_gaddrh, 0); 189 W32(ep, fen_gaddrl, 0); 190 } 191 192 static void set_multicast_one(struct net_device *dev, const u8 *mac) 193 { 194 struct fs_enet_private *fep = netdev_priv(dev); 195 fcc_enet_t __iomem *ep = fep->fcc.ep; 196 u16 taddrh, taddrm, taddrl; 197 198 taddrh = ((u16)mac[5] << 8) | mac[4]; 199 taddrm = ((u16)mac[3] << 8) | mac[2]; 200 taddrl = ((u16)mac[1] << 8) | mac[0]; 201 202 W16(ep, fen_taddrh, taddrh); 203 W16(ep, fen_taddrm, taddrm); 204 W16(ep, fen_taddrl, taddrl); 205 fcc_cr_cmd(fep, CPM_CR_SET_GADDR); 206 } 207 208 static void set_multicast_finish(struct net_device *dev) 209 { 210 struct fs_enet_private *fep = netdev_priv(dev); 211 fcc_t __iomem *fccp = fep->fcc.fccp; 212 fcc_enet_t __iomem *ep = fep->fcc.ep; 213 214 /* clear promiscuous always */ 215 C32(fccp, fcc_fpsmr, FCC_PSMR_PRO); 216 217 /* if all multi or too many multicasts; just enable all */ 218 if ((dev->flags & IFF_ALLMULTI) != 0 || 219 netdev_mc_count(dev) > FCC_MAX_MULTICAST_ADDRS) { 220 221 W32(ep, fen_gaddrh, 0xffffffff); 222 W32(ep, fen_gaddrl, 0xffffffff); 223 } 224 225 /* read back */ 226 fep->fcc.gaddrh = R32(ep, fen_gaddrh); 227 fep->fcc.gaddrl = R32(ep, fen_gaddrl); 228 } 229 230 static void set_multicast_list(struct net_device *dev) 231 { 232 struct netdev_hw_addr *ha; 233 234 if ((dev->flags & IFF_PROMISC) == 0) { 235 set_multicast_start(dev); 236 netdev_for_each_mc_addr(ha, dev) 237 set_multicast_one(dev, ha->addr); 238 set_multicast_finish(dev); 239 } else 240 set_promiscuous_mode(dev); 241 } 242 243 static void restart(struct net_device *dev) 244 { 245 struct fs_enet_private *fep = netdev_priv(dev); 246 const struct fs_platform_info *fpi = fep->fpi; 247 fcc_t __iomem *fccp = fep->fcc.fccp; 248 fcc_c_t __iomem *fcccp = fep->fcc.fcccp; 249 fcc_enet_t __iomem *ep = fep->fcc.ep; 250 dma_addr_t rx_bd_base_phys, tx_bd_base_phys; 251 u16 paddrh, paddrm, paddrl; 252 const unsigned char *mac; 253 int i; 254 255 C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); 256 257 /* clear everything (slow & steady does it) */ 258 for (i = 0; i < sizeof(*ep); i++) 259 out_8((u8 __iomem *)ep + i, 0); 260 261 /* get physical address */ 262 rx_bd_base_phys = fep->ring_mem_addr; 263 tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring; 264 265 /* point to bds */ 266 W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys); 267 W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys); 268 269 /* Set maximum bytes per receive buffer. 270 * It must be a multiple of 32. 271 */ 272 W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE); 273 274 W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL | CPMFCR_EB) << 24); 275 W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL | CPMFCR_EB) << 24); 276 277 /* Allocate space in the reserved FCC area of DPRAM for the 278 * internal buffers. No one uses this space (yet), so we 279 * can do this. Later, we will add resource management for 280 * this area. 281 */ 282 283 W16(ep, fen_genfcc.fcc_riptr, fpi->dpram_offset); 284 W16(ep, fen_genfcc.fcc_tiptr, fpi->dpram_offset + 32); 285 286 W16(ep, fen_padptr, fpi->dpram_offset + 64); 287 288 /* fill with special symbol... */ 289 memset_io(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32); 290 291 W32(ep, fen_genfcc.fcc_rbptr, 0); 292 W32(ep, fen_genfcc.fcc_tbptr, 0); 293 W32(ep, fen_genfcc.fcc_rcrc, 0); 294 W32(ep, fen_genfcc.fcc_tcrc, 0); 295 W16(ep, fen_genfcc.fcc_res1, 0); 296 W32(ep, fen_genfcc.fcc_res2, 0); 297 298 /* no CAM */ 299 W32(ep, fen_camptr, 0); 300 301 /* Set CRC preset and mask */ 302 W32(ep, fen_cmask, 0xdebb20e3); 303 W32(ep, fen_cpres, 0xffffffff); 304 305 W32(ep, fen_crcec, 0); /* CRC Error counter */ 306 W32(ep, fen_alec, 0); /* alignment error counter */ 307 W32(ep, fen_disfc, 0); /* discard frame counter */ 308 W16(ep, fen_retlim, 15); /* Retry limit threshold */ 309 W16(ep, fen_pper, 0); /* Normal persistence */ 310 311 /* set group address */ 312 W32(ep, fen_gaddrh, fep->fcc.gaddrh); 313 W32(ep, fen_gaddrl, fep->fcc.gaddrh); 314 315 /* Clear hash filter tables */ 316 W32(ep, fen_iaddrh, 0); 317 W32(ep, fen_iaddrl, 0); 318 319 /* Clear the Out-of-sequence TxBD */ 320 W16(ep, fen_tfcstat, 0); 321 W16(ep, fen_tfclen, 0); 322 W32(ep, fen_tfcptr, 0); 323 324 W16(ep, fen_mflr, PKT_MAXBUF_SIZE); /* maximum frame length register */ 325 W16(ep, fen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */ 326 327 /* set address */ 328 mac = dev->dev_addr; 329 paddrh = ((u16)mac[5] << 8) | mac[4]; 330 paddrm = ((u16)mac[3] << 8) | mac[2]; 331 paddrl = ((u16)mac[1] << 8) | mac[0]; 332 333 W16(ep, fen_paddrh, paddrh); 334 W16(ep, fen_paddrm, paddrm); 335 W16(ep, fen_paddrl, paddrl); 336 337 W16(ep, fen_taddrh, 0); 338 W16(ep, fen_taddrm, 0); 339 W16(ep, fen_taddrl, 0); 340 341 W16(ep, fen_maxd1, 1520); /* maximum DMA1 length */ 342 W16(ep, fen_maxd2, 1520); /* maximum DMA2 length */ 343 344 /* Clear stat counters, in case we ever enable RMON */ 345 W32(ep, fen_octc, 0); 346 W32(ep, fen_colc, 0); 347 W32(ep, fen_broc, 0); 348 W32(ep, fen_mulc, 0); 349 W32(ep, fen_uspc, 0); 350 W32(ep, fen_frgc, 0); 351 W32(ep, fen_ospc, 0); 352 W32(ep, fen_jbrc, 0); 353 W32(ep, fen_p64c, 0); 354 W32(ep, fen_p65c, 0); 355 W32(ep, fen_p128c, 0); 356 W32(ep, fen_p256c, 0); 357 W32(ep, fen_p512c, 0); 358 W32(ep, fen_p1024c, 0); 359 360 W16(ep, fen_rfthr, 0); /* Suggested by manual */ 361 W16(ep, fen_rfcnt, 0); 362 W16(ep, fen_cftype, 0); 363 364 fs_init_bds(dev); 365 366 /* adjust to speed (for RMII mode) */ 367 if (fpi->use_rmii) { 368 if (dev->phydev->speed == 100) 369 C8(fcccp, fcc_gfemr, 0x20); 370 else 371 S8(fcccp, fcc_gfemr, 0x20); 372 } 373 374 fcc_cr_cmd(fep, CPM_CR_INIT_TRX); 375 376 /* clear events */ 377 W16(fccp, fcc_fcce, 0xffff); 378 379 /* Enable interrupts we wish to service */ 380 W16(fccp, fcc_fccm, FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB); 381 382 /* Set GFMR to enable Ethernet operating mode */ 383 W32(fccp, fcc_gfmr, FCC_GFMR_TCI | FCC_GFMR_MODE_ENET); 384 385 /* set sync/delimiters */ 386 W16(fccp, fcc_fdsr, 0xd555); 387 388 W32(fccp, fcc_fpsmr, FCC_PSMR_ENCRC); 389 390 if (fpi->use_rmii) 391 S32(fccp, fcc_fpsmr, FCC_PSMR_RMII); 392 393 /* adjust to duplex mode */ 394 if (dev->phydev->duplex) 395 S32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB); 396 else 397 C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB); 398 399 /* Restore multicast and promiscuous settings */ 400 set_multicast_list(dev); 401 402 S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); 403 } 404 405 static void stop(struct net_device *dev) 406 { 407 struct fs_enet_private *fep = netdev_priv(dev); 408 fcc_t __iomem *fccp = fep->fcc.fccp; 409 410 /* stop ethernet */ 411 C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); 412 413 /* clear events */ 414 W16(fccp, fcc_fcce, 0xffff); 415 416 /* clear interrupt mask */ 417 W16(fccp, fcc_fccm, 0); 418 419 fs_cleanup_bds(dev); 420 } 421 422 static void napi_clear_event_fs(struct net_device *dev) 423 { 424 struct fs_enet_private *fep = netdev_priv(dev); 425 fcc_t __iomem *fccp = fep->fcc.fccp; 426 427 W16(fccp, fcc_fcce, FCC_NAPI_EVENT_MSK); 428 } 429 430 static void napi_enable_fs(struct net_device *dev) 431 { 432 struct fs_enet_private *fep = netdev_priv(dev); 433 fcc_t __iomem *fccp = fep->fcc.fccp; 434 435 S16(fccp, fcc_fccm, FCC_NAPI_EVENT_MSK); 436 } 437 438 static void napi_disable_fs(struct net_device *dev) 439 { 440 struct fs_enet_private *fep = netdev_priv(dev); 441 fcc_t __iomem *fccp = fep->fcc.fccp; 442 443 C16(fccp, fcc_fccm, FCC_NAPI_EVENT_MSK); 444 } 445 446 static void rx_bd_done(struct net_device *dev) 447 { 448 /* nothing */ 449 } 450 451 static void tx_kickstart(struct net_device *dev) 452 { 453 struct fs_enet_private *fep = netdev_priv(dev); 454 fcc_t __iomem *fccp = fep->fcc.fccp; 455 456 S16(fccp, fcc_ftodr, 0x8000); 457 } 458 459 static u32 get_int_events(struct net_device *dev) 460 { 461 struct fs_enet_private *fep = netdev_priv(dev); 462 fcc_t __iomem *fccp = fep->fcc.fccp; 463 464 return (u32)R16(fccp, fcc_fcce); 465 } 466 467 static void clear_int_events(struct net_device *dev, u32 int_events) 468 { 469 struct fs_enet_private *fep = netdev_priv(dev); 470 fcc_t __iomem *fccp = fep->fcc.fccp; 471 472 W16(fccp, fcc_fcce, int_events & 0xffff); 473 } 474 475 static void ev_error(struct net_device *dev, u32 int_events) 476 { 477 struct fs_enet_private *fep = netdev_priv(dev); 478 479 dev_warn(fep->dev, "FS_ENET ERROR(s) 0x%x\n", int_events); 480 } 481 482 static int get_regs(struct net_device *dev, void *p, int *sizep) 483 { 484 struct fs_enet_private *fep = netdev_priv(dev); 485 486 if (*sizep < sizeof(fcc_t) + sizeof(fcc_enet_t) + 1) 487 return -EINVAL; 488 489 memcpy_fromio(p, fep->fcc.fccp, sizeof(fcc_t)); 490 p = (char *)p + sizeof(fcc_t); 491 492 memcpy_fromio(p, fep->fcc.ep, sizeof(fcc_enet_t)); 493 p = (char *)p + sizeof(fcc_enet_t); 494 495 memcpy_fromio(p, fep->fcc.fcccp, 1); 496 return 0; 497 } 498 499 static int get_regs_len(struct net_device *dev) 500 { 501 return sizeof(fcc_t) + sizeof(fcc_enet_t) + 1; 502 } 503 504 /* Some transmit errors cause the transmitter to shut 505 * down. We now issue a restart transmit. 506 * Also, to workaround 8260 device erratum CPM37, we must 507 * disable and then re-enable the transmitterfollowing a 508 * Late Collision, Underrun, or Retry Limit error. 509 * In addition, tbptr may point beyond BDs beyond still marked 510 * as ready due to internal pipelining, so we need to look back 511 * through the BDs and adjust tbptr to point to the last BD 512 * marked as ready. This may result in some buffers being 513 * retransmitted. 514 */ 515 static void tx_restart(struct net_device *dev) 516 { 517 struct fs_enet_private *fep = netdev_priv(dev); 518 fcc_t __iomem *fccp = fep->fcc.fccp; 519 const struct fs_platform_info *fpi = fep->fpi; 520 fcc_enet_t __iomem *ep = fep->fcc.ep; 521 cbd_t __iomem *curr_tbptr; 522 cbd_t __iomem *recheck_bd; 523 cbd_t __iomem *prev_bd; 524 cbd_t __iomem *last_tx_bd; 525 526 last_tx_bd = fep->tx_bd_base + (fpi->tx_ring - 1); 527 528 /* get the current bd held in TBPTR and scan back from this point */ 529 recheck_bd = curr_tbptr = (cbd_t __iomem *) 530 ((R32(ep, fen_genfcc.fcc_tbptr) - fep->ring_mem_addr) + 531 fep->ring_base); 532 533 prev_bd = (recheck_bd == fep->tx_bd_base) ? last_tx_bd : recheck_bd - 1; 534 535 /* Move through the bds in reverse, look for the earliest buffer 536 * that is not ready. Adjust TBPTR to the following buffer */ 537 while ((CBDR_SC(prev_bd) & BD_ENET_TX_READY) != 0) { 538 /* Go back one buffer */ 539 recheck_bd = prev_bd; 540 541 /* update the previous buffer */ 542 prev_bd = (prev_bd == fep->tx_bd_base) ? last_tx_bd : prev_bd - 1; 543 544 /* We should never see all bds marked as ready, check anyway */ 545 if (recheck_bd == curr_tbptr) 546 break; 547 } 548 /* Now update the TBPTR and dirty flag to the current buffer */ 549 W32(ep, fen_genfcc.fcc_tbptr, 550 (uint)(((void __iomem *)recheck_bd - fep->ring_base) + 551 fep->ring_mem_addr)); 552 fep->dirty_tx = recheck_bd; 553 554 C32(fccp, fcc_gfmr, FCC_GFMR_ENT); 555 udelay(10); 556 S32(fccp, fcc_gfmr, FCC_GFMR_ENT); 557 558 fcc_cr_cmd(fep, CPM_CR_RESTART_TX); 559 } 560 561 /*************************************************************************/ 562 563 const struct fs_ops fs_fcc_ops = { 564 .setup_data = setup_data, 565 .cleanup_data = cleanup_data, 566 .set_multicast_list = set_multicast_list, 567 .restart = restart, 568 .stop = stop, 569 .napi_clear_event = napi_clear_event_fs, 570 .napi_enable = napi_enable_fs, 571 .napi_disable = napi_disable_fs, 572 .rx_bd_done = rx_bd_done, 573 .tx_kickstart = tx_kickstart, 574 .get_int_events = get_int_events, 575 .clear_int_events = clear_int_events, 576 .ev_error = ev_error, 577 .get_regs = get_regs, 578 .get_regs_len = get_regs_len, 579 .tx_restart = tx_restart, 580 .allocate_bd = allocate_bd, 581 .free_bd = free_bd, 582 }; 583