1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef FS_ENET_H 3 #define FS_ENET_H 4 5 #include <linux/clk.h> 6 #include <linux/mii.h> 7 #include <linux/netdevice.h> 8 #include <linux/types.h> 9 #include <linux/list.h> 10 #include <linux/phy.h> 11 #include <linux/dma-mapping.h> 12 13 #include <asm/fs_pd.h> 14 15 #ifdef CONFIG_CPM1 16 #include <asm/cpm1.h> 17 #endif 18 19 #if defined(CONFIG_FS_ENET_HAS_FEC) 20 #include <asm/cpm.h> 21 22 #if defined(CONFIG_FS_ENET_MPC5121_FEC) 23 /* MPC5121 FEC has different register layout */ 24 struct fec { 25 u32 fec_reserved0; 26 u32 fec_ievent; /* Interrupt event reg */ 27 u32 fec_imask; /* Interrupt mask reg */ 28 u32 fec_reserved1; 29 u32 fec_r_des_active; /* Receive descriptor reg */ 30 u32 fec_x_des_active; /* Transmit descriptor reg */ 31 u32 fec_reserved2[3]; 32 u32 fec_ecntrl; /* Ethernet control reg */ 33 u32 fec_reserved3[6]; 34 u32 fec_mii_data; /* MII manage frame reg */ 35 u32 fec_mii_speed; /* MII speed control reg */ 36 u32 fec_reserved4[7]; 37 u32 fec_mib_ctrlstat; /* MIB control/status reg */ 38 u32 fec_reserved5[7]; 39 u32 fec_r_cntrl; /* Receive control reg */ 40 u32 fec_reserved6[15]; 41 u32 fec_x_cntrl; /* Transmit Control reg */ 42 u32 fec_reserved7[7]; 43 u32 fec_addr_low; /* Low 32bits MAC address */ 44 u32 fec_addr_high; /* High 16bits MAC address */ 45 u32 fec_opd; /* Opcode + Pause duration */ 46 u32 fec_reserved8[10]; 47 u32 fec_hash_table_high; /* High 32bits hash table */ 48 u32 fec_hash_table_low; /* Low 32bits hash table */ 49 u32 fec_grp_hash_table_high; /* High 32bits hash table */ 50 u32 fec_grp_hash_table_low; /* Low 32bits hash table */ 51 u32 fec_reserved9[7]; 52 u32 fec_x_wmrk; /* FIFO transmit water mark */ 53 u32 fec_reserved10; 54 u32 fec_r_bound; /* FIFO receive bound reg */ 55 u32 fec_r_fstart; /* FIFO receive start reg */ 56 u32 fec_reserved11[11]; 57 u32 fec_r_des_start; /* Receive descriptor ring */ 58 u32 fec_x_des_start; /* Transmit descriptor ring */ 59 u32 fec_r_buff_size; /* Maximum receive buff size */ 60 u32 fec_reserved12[26]; 61 u32 fec_dma_control; /* DMA Endian and other ctrl */ 62 }; 63 #endif 64 65 struct fec_info { 66 struct fec __iomem *fecp; 67 u32 mii_speed; 68 }; 69 #endif 70 71 #ifdef CONFIG_CPM2 72 #include <asm/cpm2.h> 73 #endif 74 75 /* hw driver ops */ 76 struct fs_ops { 77 int (*setup_data)(struct net_device *dev); 78 int (*allocate_bd)(struct net_device *dev); 79 void (*free_bd)(struct net_device *dev); 80 void (*cleanup_data)(struct net_device *dev); 81 void (*set_multicast_list)(struct net_device *dev); 82 void (*adjust_link)(struct net_device *dev); 83 void (*restart)(struct net_device *dev); 84 void (*stop)(struct net_device *dev); 85 void (*napi_clear_event)(struct net_device *dev); 86 void (*napi_enable)(struct net_device *dev); 87 void (*napi_disable)(struct net_device *dev); 88 void (*rx_bd_done)(struct net_device *dev); 89 void (*tx_kickstart)(struct net_device *dev); 90 u32 (*get_int_events)(struct net_device *dev); 91 void (*clear_int_events)(struct net_device *dev, u32 int_events); 92 void (*ev_error)(struct net_device *dev, u32 int_events); 93 int (*get_regs)(struct net_device *dev, void *p, int *sizep); 94 int (*get_regs_len)(struct net_device *dev); 95 void (*tx_restart)(struct net_device *dev); 96 }; 97 98 struct phy_info { 99 unsigned int id; 100 const char *name; 101 void (*startup) (struct net_device * dev); 102 void (*shutdown) (struct net_device * dev); 103 void (*ack_int) (struct net_device * dev); 104 }; 105 106 /* The FEC stores dest/src/type, data, and checksum for receive packets. 107 */ 108 #define MAX_MTU 1508 /* Allow fullsized pppoe packets over VLAN */ 109 #define MIN_MTU 46 /* this is data size */ 110 #define CRC_LEN 4 111 112 #define PKT_MAXBUF_SIZE (MAX_MTU+ETH_HLEN+CRC_LEN) 113 #define PKT_MINBUF_SIZE (MIN_MTU+ETH_HLEN+CRC_LEN) 114 115 /* Must be a multiple of 32 (to cover both FEC & FCC) */ 116 #define PKT_MAXBLR_SIZE ((PKT_MAXBUF_SIZE + 31) & ~31) 117 /* This is needed so that invalidate_xxx wont invalidate too much */ 118 #define ENET_RX_ALIGN 16 119 #define ENET_RX_FRSIZE L1_CACHE_ALIGN(PKT_MAXBUF_SIZE + ENET_RX_ALIGN - 1) 120 121 struct fs_platform_info { 122 /* device specific information */ 123 u32 cp_command; /* CPM page/sblock/mcn */ 124 125 u32 dpram_offset; 126 127 struct device_node *phy_node; 128 129 int rx_ring, tx_ring; /* number of buffers on rx */ 130 int rx_copybreak; /* limit we copy small frames */ 131 int napi_weight; /* NAPI weight */ 132 133 int use_rmii; /* use RMII mode */ 134 135 struct clk *clk_per; /* 'per' clock for register access */ 136 }; 137 138 struct fs_enet_private { 139 struct napi_struct napi; 140 struct device *dev; /* pointer back to the device (must be initialized first) */ 141 struct net_device *ndev; 142 spinlock_t lock; /* during all ops except TX pckt processing */ 143 spinlock_t tx_lock; /* during fs_start_xmit and fs_tx */ 144 struct fs_platform_info *fpi; 145 struct work_struct timeout_work; 146 const struct fs_ops *ops; 147 int rx_ring, tx_ring; 148 dma_addr_t ring_mem_addr; 149 void __iomem *ring_base; 150 struct sk_buff **rx_skbuff; 151 struct sk_buff **tx_skbuff; 152 char *mapped_as_page; 153 cbd_t __iomem *rx_bd_base; /* Address of Rx and Tx buffers. */ 154 cbd_t __iomem *tx_bd_base; 155 cbd_t __iomem *dirty_tx; /* ring entries to be free()ed. */ 156 cbd_t __iomem *cur_rx; 157 cbd_t __iomem *cur_tx; 158 int tx_free; 159 const struct phy_info *phy; 160 u32 msg_enable; 161 struct mii_if_info mii_if; 162 unsigned int last_mii_status; 163 int interrupt; 164 165 int oldduplex, oldspeed, oldlink; /* current settings */ 166 167 /* event masks */ 168 u32 ev_napi; /* mask of NAPI events */ 169 u32 ev; /* event mask */ 170 u32 ev_err; /* error event mask */ 171 172 u16 bd_rx_empty; /* mask of BD rx empty */ 173 u16 bd_rx_err; /* mask of BD rx errors */ 174 175 union { 176 struct { 177 int idx; /* FEC1 = 0, FEC2 = 1 */ 178 void __iomem *fecp; /* hw registers */ 179 u32 hthi, htlo; /* state for multicast */ 180 } fec; 181 182 struct { 183 int idx; /* FCC1-3 = 0-2 */ 184 void __iomem *fccp; /* hw registers */ 185 void __iomem *ep; /* parameter ram */ 186 void __iomem *fcccp; /* hw registers cont. */ 187 void __iomem *mem; /* FCC DPRAM */ 188 u32 gaddrh, gaddrl; /* group address */ 189 } fcc; 190 191 struct { 192 int idx; /* FEC1 = 0, FEC2 = 1 */ 193 void __iomem *sccp; /* hw registers */ 194 void __iomem *ep; /* parameter ram */ 195 u32 hthi, htlo; /* state for multicast */ 196 } scc; 197 198 }; 199 }; 200 201 /***************************************************************************/ 202 203 void fs_init_bds(struct net_device *dev); 204 void fs_cleanup_bds(struct net_device *dev); 205 206 /***************************************************************************/ 207 208 #define DRV_MODULE_NAME "fs_enet" 209 #define PFX DRV_MODULE_NAME ": " 210 211 /***************************************************************************/ 212 /* buffer descriptor access macros */ 213 214 /* access macros */ 215 #if defined(CONFIG_CPM1) 216 /* for a CPM1 __raw_xxx's are sufficient */ 217 #define __cbd_out32(addr, x) __raw_writel(x, addr) 218 #define __cbd_out16(addr, x) __raw_writew(x, addr) 219 #define __cbd_in32(addr) __raw_readl(addr) 220 #define __cbd_in16(addr) __raw_readw(addr) 221 #else 222 /* for others play it safe */ 223 #define __cbd_out32(addr, x) out_be32(addr, x) 224 #define __cbd_out16(addr, x) out_be16(addr, x) 225 #define __cbd_in32(addr) in_be32(addr) 226 #define __cbd_in16(addr) in_be16(addr) 227 #endif 228 229 /* write */ 230 #define CBDW_SC(_cbd, _sc) __cbd_out16(&(_cbd)->cbd_sc, (_sc)) 231 #define CBDW_DATLEN(_cbd, _datlen) __cbd_out16(&(_cbd)->cbd_datlen, (_datlen)) 232 #define CBDW_BUFADDR(_cbd, _bufaddr) __cbd_out32(&(_cbd)->cbd_bufaddr, (_bufaddr)) 233 234 /* read */ 235 #define CBDR_SC(_cbd) __cbd_in16(&(_cbd)->cbd_sc) 236 #define CBDR_DATLEN(_cbd) __cbd_in16(&(_cbd)->cbd_datlen) 237 #define CBDR_BUFADDR(_cbd) __cbd_in32(&(_cbd)->cbd_bufaddr) 238 239 /* set bits */ 240 #define CBDS_SC(_cbd, _sc) CBDW_SC(_cbd, CBDR_SC(_cbd) | (_sc)) 241 242 /* clear bits */ 243 #define CBDC_SC(_cbd, _sc) CBDW_SC(_cbd, CBDR_SC(_cbd) & ~(_sc)) 244 245 /*******************************************************************/ 246 247 extern const struct fs_ops fs_fec_ops; 248 extern const struct fs_ops fs_fcc_ops; 249 extern const struct fs_ops fs_scc_ops; 250 251 /*******************************************************************/ 252 253 #endif 254