1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later 2 /* 3 * Copyright 2008 - 2015 Freescale Semiconductor Inc. 4 */ 5 6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 7 8 #include "fman_tgec.h" 9 #include "fman.h" 10 11 #include <linux/slab.h> 12 #include <linux/bitrev.h> 13 #include <linux/io.h> 14 #include <linux/crc32.h> 15 16 /* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */ 17 #define TGEC_TX_IPG_LENGTH_MASK 0x000003ff 18 19 /* Command and Configuration Register (COMMAND_CONFIG) */ 20 #define CMD_CFG_EN_TIMESTAMP 0x00100000 21 #define CMD_CFG_NO_LEN_CHK 0x00020000 22 #define CMD_CFG_PAUSE_IGNORE 0x00000100 23 #define CMF_CFG_CRC_FWD 0x00000040 24 #define CMD_CFG_PROMIS_EN 0x00000010 25 #define CMD_CFG_RX_EN 0x00000002 26 #define CMD_CFG_TX_EN 0x00000001 27 28 /* Interrupt Mask Register (IMASK) */ 29 #define TGEC_IMASK_MDIO_SCAN_EVENT 0x00010000 30 #define TGEC_IMASK_MDIO_CMD_CMPL 0x00008000 31 #define TGEC_IMASK_REM_FAULT 0x00004000 32 #define TGEC_IMASK_LOC_FAULT 0x00002000 33 #define TGEC_IMASK_TX_ECC_ER 0x00001000 34 #define TGEC_IMASK_TX_FIFO_UNFL 0x00000800 35 #define TGEC_IMASK_TX_FIFO_OVFL 0x00000400 36 #define TGEC_IMASK_TX_ER 0x00000200 37 #define TGEC_IMASK_RX_FIFO_OVFL 0x00000100 38 #define TGEC_IMASK_RX_ECC_ER 0x00000080 39 #define TGEC_IMASK_RX_JAB_FRM 0x00000040 40 #define TGEC_IMASK_RX_OVRSZ_FRM 0x00000020 41 #define TGEC_IMASK_RX_RUNT_FRM 0x00000010 42 #define TGEC_IMASK_RX_FRAG_FRM 0x00000008 43 #define TGEC_IMASK_RX_LEN_ER 0x00000004 44 #define TGEC_IMASK_RX_CRC_ER 0x00000002 45 #define TGEC_IMASK_RX_ALIGN_ER 0x00000001 46 47 /* Hashtable Control Register (HASHTABLE_CTRL) */ 48 #define TGEC_HASH_MCAST_SHIFT 23 49 #define TGEC_HASH_MCAST_EN 0x00000200 50 #define TGEC_HASH_ADR_MSK 0x000001ff 51 52 #define DEFAULT_TX_IPG_LENGTH 12 53 #define DEFAULT_MAX_FRAME_LENGTH 0x600 54 #define DEFAULT_PAUSE_QUANT 0xf000 55 56 /* number of pattern match registers (entries) */ 57 #define TGEC_NUM_OF_PADDRS 1 58 59 /* Group address bit indication */ 60 #define GROUP_ADDRESS 0x0000010000000000LL 61 62 /* Hash table size (= 32 bits*8 regs) */ 63 #define TGEC_HASH_TABLE_SIZE 512 64 65 /* tGEC memory map */ 66 struct tgec_regs { 67 u32 tgec_id; /* 0x000 Controller ID */ 68 u32 reserved001[1]; /* 0x004 */ 69 u32 command_config; /* 0x008 Control and configuration */ 70 u32 mac_addr_0; /* 0x00c Lower 32 bits of the MAC adr */ 71 u32 mac_addr_1; /* 0x010 Upper 16 bits of the MAC adr */ 72 u32 maxfrm; /* 0x014 Maximum frame length */ 73 u32 pause_quant; /* 0x018 Pause quanta */ 74 u32 rx_fifo_sections; /* 0x01c */ 75 u32 tx_fifo_sections; /* 0x020 */ 76 u32 rx_fifo_almost_f_e; /* 0x024 */ 77 u32 tx_fifo_almost_f_e; /* 0x028 */ 78 u32 hashtable_ctrl; /* 0x02c Hash table control */ 79 u32 mdio_cfg_status; /* 0x030 */ 80 u32 mdio_command; /* 0x034 */ 81 u32 mdio_data; /* 0x038 */ 82 u32 mdio_regaddr; /* 0x03c */ 83 u32 status; /* 0x040 */ 84 u32 tx_ipg_len; /* 0x044 Transmitter inter-packet-gap */ 85 u32 mac_addr_2; /* 0x048 Lower 32 bits of 2nd MAC adr */ 86 u32 mac_addr_3; /* 0x04c Upper 16 bits of 2nd MAC adr */ 87 u32 rx_fifo_ptr_rd; /* 0x050 */ 88 u32 rx_fifo_ptr_wr; /* 0x054 */ 89 u32 tx_fifo_ptr_rd; /* 0x058 */ 90 u32 tx_fifo_ptr_wr; /* 0x05c */ 91 u32 imask; /* 0x060 Interrupt mask */ 92 u32 ievent; /* 0x064 Interrupt event */ 93 u32 udp_port; /* 0x068 Defines a UDP Port number */ 94 u32 type_1588v2; /* 0x06c Type field for 1588v2 */ 95 u32 reserved070[4]; /* 0x070 */ 96 /* 10Ge Statistics Counter */ 97 u32 tfrm_u; /* 80 aFramesTransmittedOK */ 98 u32 tfrm_l; /* 84 aFramesTransmittedOK */ 99 u32 rfrm_u; /* 88 aFramesReceivedOK */ 100 u32 rfrm_l; /* 8c aFramesReceivedOK */ 101 u32 rfcs_u; /* 90 aFrameCheckSequenceErrors */ 102 u32 rfcs_l; /* 94 aFrameCheckSequenceErrors */ 103 u32 raln_u; /* 98 aAlignmentErrors */ 104 u32 raln_l; /* 9c aAlignmentErrors */ 105 u32 txpf_u; /* A0 aPAUSEMACCtrlFramesTransmitted */ 106 u32 txpf_l; /* A4 aPAUSEMACCtrlFramesTransmitted */ 107 u32 rxpf_u; /* A8 aPAUSEMACCtrlFramesReceived */ 108 u32 rxpf_l; /* Ac aPAUSEMACCtrlFramesReceived */ 109 u32 rlong_u; /* B0 aFrameTooLongErrors */ 110 u32 rlong_l; /* B4 aFrameTooLongErrors */ 111 u32 rflr_u; /* B8 aInRangeLengthErrors */ 112 u32 rflr_l; /* Bc aInRangeLengthErrors */ 113 u32 tvlan_u; /* C0 VLANTransmittedOK */ 114 u32 tvlan_l; /* C4 VLANTransmittedOK */ 115 u32 rvlan_u; /* C8 VLANReceivedOK */ 116 u32 rvlan_l; /* Cc VLANReceivedOK */ 117 u32 toct_u; /* D0 if_out_octets */ 118 u32 toct_l; /* D4 if_out_octets */ 119 u32 roct_u; /* D8 if_in_octets */ 120 u32 roct_l; /* Dc if_in_octets */ 121 u32 ruca_u; /* E0 if_in_ucast_pkts */ 122 u32 ruca_l; /* E4 if_in_ucast_pkts */ 123 u32 rmca_u; /* E8 ifInMulticastPkts */ 124 u32 rmca_l; /* Ec ifInMulticastPkts */ 125 u32 rbca_u; /* F0 ifInBroadcastPkts */ 126 u32 rbca_l; /* F4 ifInBroadcastPkts */ 127 u32 terr_u; /* F8 if_out_errors */ 128 u32 terr_l; /* Fc if_out_errors */ 129 u32 reserved100[2]; /* 100-108 */ 130 u32 tuca_u; /* 108 if_out_ucast_pkts */ 131 u32 tuca_l; /* 10c if_out_ucast_pkts */ 132 u32 tmca_u; /* 110 ifOutMulticastPkts */ 133 u32 tmca_l; /* 114 ifOutMulticastPkts */ 134 u32 tbca_u; /* 118 ifOutBroadcastPkts */ 135 u32 tbca_l; /* 11c ifOutBroadcastPkts */ 136 u32 rdrp_u; /* 120 etherStatsDropEvents */ 137 u32 rdrp_l; /* 124 etherStatsDropEvents */ 138 u32 reoct_u; /* 128 etherStatsOctets */ 139 u32 reoct_l; /* 12c etherStatsOctets */ 140 u32 rpkt_u; /* 130 etherStatsPkts */ 141 u32 rpkt_l; /* 134 etherStatsPkts */ 142 u32 trund_u; /* 138 etherStatsUndersizePkts */ 143 u32 trund_l; /* 13c etherStatsUndersizePkts */ 144 u32 r64_u; /* 140 etherStatsPkts64Octets */ 145 u32 r64_l; /* 144 etherStatsPkts64Octets */ 146 u32 r127_u; /* 148 etherStatsPkts65to127Octets */ 147 u32 r127_l; /* 14c etherStatsPkts65to127Octets */ 148 u32 r255_u; /* 150 etherStatsPkts128to255Octets */ 149 u32 r255_l; /* 154 etherStatsPkts128to255Octets */ 150 u32 r511_u; /* 158 etherStatsPkts256to511Octets */ 151 u32 r511_l; /* 15c etherStatsPkts256to511Octets */ 152 u32 r1023_u; /* 160 etherStatsPkts512to1023Octets */ 153 u32 r1023_l; /* 164 etherStatsPkts512to1023Octets */ 154 u32 r1518_u; /* 168 etherStatsPkts1024to1518Octets */ 155 u32 r1518_l; /* 16c etherStatsPkts1024to1518Octets */ 156 u32 r1519x_u; /* 170 etherStatsPkts1519toX */ 157 u32 r1519x_l; /* 174 etherStatsPkts1519toX */ 158 u32 trovr_u; /* 178 etherStatsOversizePkts */ 159 u32 trovr_l; /* 17c etherStatsOversizePkts */ 160 u32 trjbr_u; /* 180 etherStatsJabbers */ 161 u32 trjbr_l; /* 184 etherStatsJabbers */ 162 u32 trfrg_u; /* 188 etherStatsFragments */ 163 u32 trfrg_l; /* 18C etherStatsFragments */ 164 u32 rerr_u; /* 190 if_in_errors */ 165 u32 rerr_l; /* 194 if_in_errors */ 166 }; 167 168 struct tgec_cfg { 169 bool pause_ignore; 170 bool promiscuous_mode_enable; 171 u16 max_frame_length; 172 u16 pause_quant; 173 u32 tx_ipg_length; 174 }; 175 176 struct fman_mac { 177 /* Pointer to the memory mapped registers. */ 178 struct tgec_regs __iomem *regs; 179 /* MAC address of device; */ 180 u64 addr; 181 u16 max_speed; 182 void *dev_id; /* device cookie used by the exception cbs */ 183 fman_mac_exception_cb *exception_cb; 184 fman_mac_exception_cb *event_cb; 185 /* pointer to driver's global address hash table */ 186 struct eth_hash_t *multicast_addr_hash; 187 /* pointer to driver's individual address hash table */ 188 struct eth_hash_t *unicast_addr_hash; 189 u8 mac_id; 190 u32 exceptions; 191 struct tgec_cfg *cfg; 192 void *fm; 193 struct fman_rev_info fm_rev_info; 194 bool allmulti_enabled; 195 }; 196 197 static void set_mac_address(struct tgec_regs __iomem *regs, const u8 *adr) 198 { 199 u32 tmp0, tmp1; 200 201 tmp0 = (u32)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24); 202 tmp1 = (u32)(adr[4] | adr[5] << 8); 203 iowrite32be(tmp0, ®s->mac_addr_0); 204 iowrite32be(tmp1, ®s->mac_addr_1); 205 } 206 207 static void set_dflts(struct tgec_cfg *cfg) 208 { 209 cfg->promiscuous_mode_enable = false; 210 cfg->pause_ignore = false; 211 cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH; 212 cfg->max_frame_length = DEFAULT_MAX_FRAME_LENGTH; 213 cfg->pause_quant = DEFAULT_PAUSE_QUANT; 214 } 215 216 static int init(struct tgec_regs __iomem *regs, struct tgec_cfg *cfg, 217 u32 exception_mask) 218 { 219 u32 tmp; 220 221 /* Config */ 222 tmp = CMF_CFG_CRC_FWD; 223 if (cfg->promiscuous_mode_enable) 224 tmp |= CMD_CFG_PROMIS_EN; 225 if (cfg->pause_ignore) 226 tmp |= CMD_CFG_PAUSE_IGNORE; 227 /* Payload length check disable */ 228 tmp |= CMD_CFG_NO_LEN_CHK; 229 iowrite32be(tmp, ®s->command_config); 230 231 /* Max Frame Length */ 232 iowrite32be((u32)cfg->max_frame_length, ®s->maxfrm); 233 /* Pause Time */ 234 iowrite32be(cfg->pause_quant, ®s->pause_quant); 235 236 /* clear all pending events and set-up interrupts */ 237 iowrite32be(0xffffffff, ®s->ievent); 238 iowrite32be(ioread32be(®s->imask) | exception_mask, ®s->imask); 239 240 return 0; 241 } 242 243 static int check_init_parameters(struct fman_mac *tgec) 244 { 245 if (tgec->max_speed < SPEED_10000) { 246 pr_err("10G MAC driver only support 10G speed\n"); 247 return -EINVAL; 248 } 249 if (!tgec->exception_cb) { 250 pr_err("uninitialized exception_cb\n"); 251 return -EINVAL; 252 } 253 if (!tgec->event_cb) { 254 pr_err("uninitialized event_cb\n"); 255 return -EINVAL; 256 } 257 258 return 0; 259 } 260 261 static int get_exception_flag(enum fman_mac_exceptions exception) 262 { 263 u32 bit_mask; 264 265 switch (exception) { 266 case FM_MAC_EX_10G_MDIO_SCAN_EVENT: 267 bit_mask = TGEC_IMASK_MDIO_SCAN_EVENT; 268 break; 269 case FM_MAC_EX_10G_MDIO_CMD_CMPL: 270 bit_mask = TGEC_IMASK_MDIO_CMD_CMPL; 271 break; 272 case FM_MAC_EX_10G_REM_FAULT: 273 bit_mask = TGEC_IMASK_REM_FAULT; 274 break; 275 case FM_MAC_EX_10G_LOC_FAULT: 276 bit_mask = TGEC_IMASK_LOC_FAULT; 277 break; 278 case FM_MAC_EX_10G_TX_ECC_ER: 279 bit_mask = TGEC_IMASK_TX_ECC_ER; 280 break; 281 case FM_MAC_EX_10G_TX_FIFO_UNFL: 282 bit_mask = TGEC_IMASK_TX_FIFO_UNFL; 283 break; 284 case FM_MAC_EX_10G_TX_FIFO_OVFL: 285 bit_mask = TGEC_IMASK_TX_FIFO_OVFL; 286 break; 287 case FM_MAC_EX_10G_TX_ER: 288 bit_mask = TGEC_IMASK_TX_ER; 289 break; 290 case FM_MAC_EX_10G_RX_FIFO_OVFL: 291 bit_mask = TGEC_IMASK_RX_FIFO_OVFL; 292 break; 293 case FM_MAC_EX_10G_RX_ECC_ER: 294 bit_mask = TGEC_IMASK_RX_ECC_ER; 295 break; 296 case FM_MAC_EX_10G_RX_JAB_FRM: 297 bit_mask = TGEC_IMASK_RX_JAB_FRM; 298 break; 299 case FM_MAC_EX_10G_RX_OVRSZ_FRM: 300 bit_mask = TGEC_IMASK_RX_OVRSZ_FRM; 301 break; 302 case FM_MAC_EX_10G_RX_RUNT_FRM: 303 bit_mask = TGEC_IMASK_RX_RUNT_FRM; 304 break; 305 case FM_MAC_EX_10G_RX_FRAG_FRM: 306 bit_mask = TGEC_IMASK_RX_FRAG_FRM; 307 break; 308 case FM_MAC_EX_10G_RX_LEN_ER: 309 bit_mask = TGEC_IMASK_RX_LEN_ER; 310 break; 311 case FM_MAC_EX_10G_RX_CRC_ER: 312 bit_mask = TGEC_IMASK_RX_CRC_ER; 313 break; 314 case FM_MAC_EX_10G_RX_ALIGN_ER: 315 bit_mask = TGEC_IMASK_RX_ALIGN_ER; 316 break; 317 default: 318 bit_mask = 0; 319 break; 320 } 321 322 return bit_mask; 323 } 324 325 static void tgec_err_exception(void *handle) 326 { 327 struct fman_mac *tgec = (struct fman_mac *)handle; 328 struct tgec_regs __iomem *regs = tgec->regs; 329 u32 event; 330 331 /* do not handle MDIO events */ 332 event = ioread32be(®s->ievent) & 333 ~(TGEC_IMASK_MDIO_SCAN_EVENT | 334 TGEC_IMASK_MDIO_CMD_CMPL); 335 336 event &= ioread32be(®s->imask); 337 338 iowrite32be(event, ®s->ievent); 339 340 if (event & TGEC_IMASK_REM_FAULT) 341 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_REM_FAULT); 342 if (event & TGEC_IMASK_LOC_FAULT) 343 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_LOC_FAULT); 344 if (event & TGEC_IMASK_TX_ECC_ER) 345 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_TX_ECC_ER); 346 if (event & TGEC_IMASK_TX_FIFO_UNFL) 347 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_TX_FIFO_UNFL); 348 if (event & TGEC_IMASK_TX_FIFO_OVFL) 349 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_TX_FIFO_OVFL); 350 if (event & TGEC_IMASK_TX_ER) 351 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_TX_ER); 352 if (event & TGEC_IMASK_RX_FIFO_OVFL) 353 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_FIFO_OVFL); 354 if (event & TGEC_IMASK_RX_ECC_ER) 355 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_ECC_ER); 356 if (event & TGEC_IMASK_RX_JAB_FRM) 357 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_JAB_FRM); 358 if (event & TGEC_IMASK_RX_OVRSZ_FRM) 359 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_OVRSZ_FRM); 360 if (event & TGEC_IMASK_RX_RUNT_FRM) 361 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_RUNT_FRM); 362 if (event & TGEC_IMASK_RX_FRAG_FRM) 363 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_FRAG_FRM); 364 if (event & TGEC_IMASK_RX_LEN_ER) 365 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_LEN_ER); 366 if (event & TGEC_IMASK_RX_CRC_ER) 367 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_CRC_ER); 368 if (event & TGEC_IMASK_RX_ALIGN_ER) 369 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_ALIGN_ER); 370 } 371 372 static void free_init_resources(struct fman_mac *tgec) 373 { 374 fman_unregister_intr(tgec->fm, FMAN_MOD_MAC, tgec->mac_id, 375 FMAN_INTR_TYPE_ERR); 376 377 /* release the driver's group hash table */ 378 free_hash_table(tgec->multicast_addr_hash); 379 tgec->multicast_addr_hash = NULL; 380 381 /* release the driver's individual hash table */ 382 free_hash_table(tgec->unicast_addr_hash); 383 tgec->unicast_addr_hash = NULL; 384 } 385 386 static bool is_init_done(struct tgec_cfg *cfg) 387 { 388 /* Checks if tGEC driver parameters were initialized */ 389 if (!cfg) 390 return true; 391 392 return false; 393 } 394 395 int tgec_enable(struct fman_mac *tgec) 396 { 397 struct tgec_regs __iomem *regs = tgec->regs; 398 u32 tmp; 399 400 if (!is_init_done(tgec->cfg)) 401 return -EINVAL; 402 403 tmp = ioread32be(®s->command_config); 404 tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN; 405 iowrite32be(tmp, ®s->command_config); 406 407 return 0; 408 } 409 410 int tgec_disable(struct fman_mac *tgec) 411 { 412 struct tgec_regs __iomem *regs = tgec->regs; 413 u32 tmp; 414 415 if (!is_init_done(tgec->cfg)) 416 return -EINVAL; 417 418 tmp = ioread32be(®s->command_config); 419 tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN); 420 iowrite32be(tmp, ®s->command_config); 421 422 return 0; 423 } 424 425 int tgec_set_promiscuous(struct fman_mac *tgec, bool new_val) 426 { 427 struct tgec_regs __iomem *regs = tgec->regs; 428 u32 tmp; 429 430 if (!is_init_done(tgec->cfg)) 431 return -EINVAL; 432 433 tmp = ioread32be(®s->command_config); 434 if (new_val) 435 tmp |= CMD_CFG_PROMIS_EN; 436 else 437 tmp &= ~CMD_CFG_PROMIS_EN; 438 iowrite32be(tmp, ®s->command_config); 439 440 return 0; 441 } 442 443 int tgec_cfg_max_frame_len(struct fman_mac *tgec, u16 new_val) 444 { 445 if (is_init_done(tgec->cfg)) 446 return -EINVAL; 447 448 tgec->cfg->max_frame_length = new_val; 449 450 return 0; 451 } 452 453 int tgec_set_tx_pause_frames(struct fman_mac *tgec, u8 __maybe_unused priority, 454 u16 pause_time, u16 __maybe_unused thresh_time) 455 { 456 struct tgec_regs __iomem *regs = tgec->regs; 457 458 if (!is_init_done(tgec->cfg)) 459 return -EINVAL; 460 461 iowrite32be((u32)pause_time, ®s->pause_quant); 462 463 return 0; 464 } 465 466 int tgec_accept_rx_pause_frames(struct fman_mac *tgec, bool en) 467 { 468 struct tgec_regs __iomem *regs = tgec->regs; 469 u32 tmp; 470 471 if (!is_init_done(tgec->cfg)) 472 return -EINVAL; 473 474 tmp = ioread32be(®s->command_config); 475 if (!en) 476 tmp |= CMD_CFG_PAUSE_IGNORE; 477 else 478 tmp &= ~CMD_CFG_PAUSE_IGNORE; 479 iowrite32be(tmp, ®s->command_config); 480 481 return 0; 482 } 483 484 int tgec_modify_mac_address(struct fman_mac *tgec, const enet_addr_t *p_enet_addr) 485 { 486 if (!is_init_done(tgec->cfg)) 487 return -EINVAL; 488 489 tgec->addr = ENET_ADDR_TO_UINT64(*p_enet_addr); 490 set_mac_address(tgec->regs, (const u8 *)(*p_enet_addr)); 491 492 return 0; 493 } 494 495 int tgec_add_hash_mac_address(struct fman_mac *tgec, enet_addr_t *eth_addr) 496 { 497 struct tgec_regs __iomem *regs = tgec->regs; 498 struct eth_hash_entry *hash_entry; 499 u32 crc = 0xFFFFFFFF, hash; 500 u64 addr; 501 502 if (!is_init_done(tgec->cfg)) 503 return -EINVAL; 504 505 addr = ENET_ADDR_TO_UINT64(*eth_addr); 506 507 if (!(addr & GROUP_ADDRESS)) { 508 /* Unicast addresses not supported in hash */ 509 pr_err("Unicast Address\n"); 510 return -EINVAL; 511 } 512 /* CRC calculation */ 513 crc = crc32_le(crc, (u8 *)eth_addr, ETH_ALEN); 514 crc = bitrev32(crc); 515 /* Take 9 MSB bits */ 516 hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK; 517 518 /* Create element to be added to the driver hash table */ 519 hash_entry = kmalloc(sizeof(*hash_entry), GFP_ATOMIC); 520 if (!hash_entry) 521 return -ENOMEM; 522 hash_entry->addr = addr; 523 INIT_LIST_HEAD(&hash_entry->node); 524 525 list_add_tail(&hash_entry->node, 526 &tgec->multicast_addr_hash->lsts[hash]); 527 iowrite32be((hash | TGEC_HASH_MCAST_EN), ®s->hashtable_ctrl); 528 529 return 0; 530 } 531 532 int tgec_set_allmulti(struct fman_mac *tgec, bool enable) 533 { 534 u32 entry; 535 struct tgec_regs __iomem *regs = tgec->regs; 536 537 if (!is_init_done(tgec->cfg)) 538 return -EINVAL; 539 540 if (enable) { 541 for (entry = 0; entry < TGEC_HASH_TABLE_SIZE; entry++) 542 iowrite32be(entry | TGEC_HASH_MCAST_EN, 543 ®s->hashtable_ctrl); 544 } else { 545 for (entry = 0; entry < TGEC_HASH_TABLE_SIZE; entry++) 546 iowrite32be(entry & ~TGEC_HASH_MCAST_EN, 547 ®s->hashtable_ctrl); 548 } 549 550 tgec->allmulti_enabled = enable; 551 552 return 0; 553 } 554 555 int tgec_set_tstamp(struct fman_mac *tgec, bool enable) 556 { 557 struct tgec_regs __iomem *regs = tgec->regs; 558 u32 tmp; 559 560 if (!is_init_done(tgec->cfg)) 561 return -EINVAL; 562 563 tmp = ioread32be(®s->command_config); 564 565 if (enable) 566 tmp |= CMD_CFG_EN_TIMESTAMP; 567 else 568 tmp &= ~CMD_CFG_EN_TIMESTAMP; 569 570 iowrite32be(tmp, ®s->command_config); 571 572 return 0; 573 } 574 575 int tgec_del_hash_mac_address(struct fman_mac *tgec, enet_addr_t *eth_addr) 576 { 577 struct tgec_regs __iomem *regs = tgec->regs; 578 struct eth_hash_entry *hash_entry = NULL; 579 struct list_head *pos; 580 u32 crc = 0xFFFFFFFF, hash; 581 u64 addr; 582 583 if (!is_init_done(tgec->cfg)) 584 return -EINVAL; 585 586 addr = ((*(u64 *)eth_addr) >> 16); 587 588 /* CRC calculation */ 589 crc = crc32_le(crc, (u8 *)eth_addr, ETH_ALEN); 590 crc = bitrev32(crc); 591 /* Take 9 MSB bits */ 592 hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK; 593 594 list_for_each(pos, &tgec->multicast_addr_hash->lsts[hash]) { 595 hash_entry = ETH_HASH_ENTRY_OBJ(pos); 596 if (hash_entry && hash_entry->addr == addr) { 597 list_del_init(&hash_entry->node); 598 kfree(hash_entry); 599 break; 600 } 601 } 602 603 if (!tgec->allmulti_enabled) { 604 if (list_empty(&tgec->multicast_addr_hash->lsts[hash])) 605 iowrite32be((hash & ~TGEC_HASH_MCAST_EN), 606 ®s->hashtable_ctrl); 607 } 608 609 return 0; 610 } 611 612 int tgec_get_version(struct fman_mac *tgec, u32 *mac_version) 613 { 614 struct tgec_regs __iomem *regs = tgec->regs; 615 616 if (!is_init_done(tgec->cfg)) 617 return -EINVAL; 618 619 *mac_version = ioread32be(®s->tgec_id); 620 621 return 0; 622 } 623 624 int tgec_set_exception(struct fman_mac *tgec, 625 enum fman_mac_exceptions exception, bool enable) 626 { 627 struct tgec_regs __iomem *regs = tgec->regs; 628 u32 bit_mask = 0; 629 630 if (!is_init_done(tgec->cfg)) 631 return -EINVAL; 632 633 bit_mask = get_exception_flag(exception); 634 if (bit_mask) { 635 if (enable) 636 tgec->exceptions |= bit_mask; 637 else 638 tgec->exceptions &= ~bit_mask; 639 } else { 640 pr_err("Undefined exception\n"); 641 return -EINVAL; 642 } 643 if (enable) 644 iowrite32be(ioread32be(®s->imask) | bit_mask, ®s->imask); 645 else 646 iowrite32be(ioread32be(®s->imask) & ~bit_mask, ®s->imask); 647 648 return 0; 649 } 650 651 int tgec_init(struct fman_mac *tgec) 652 { 653 struct tgec_cfg *cfg; 654 enet_addr_t eth_addr; 655 int err; 656 657 if (is_init_done(tgec->cfg)) 658 return -EINVAL; 659 660 if (DEFAULT_RESET_ON_INIT && 661 (fman_reset_mac(tgec->fm, tgec->mac_id) != 0)) { 662 pr_err("Can't reset MAC!\n"); 663 return -EINVAL; 664 } 665 666 err = check_init_parameters(tgec); 667 if (err) 668 return err; 669 670 cfg = tgec->cfg; 671 672 if (tgec->addr) { 673 MAKE_ENET_ADDR_FROM_UINT64(tgec->addr, eth_addr); 674 set_mac_address(tgec->regs, (const u8 *)eth_addr); 675 } 676 677 /* interrupts */ 678 /* FM_10G_REM_N_LCL_FLT_EX_10GMAC_ERRATA_SW005 Errata workaround */ 679 if (tgec->fm_rev_info.major <= 2) 680 tgec->exceptions &= ~(TGEC_IMASK_REM_FAULT | 681 TGEC_IMASK_LOC_FAULT); 682 683 err = init(tgec->regs, cfg, tgec->exceptions); 684 if (err) { 685 free_init_resources(tgec); 686 pr_err("TGEC version doesn't support this i/f mode\n"); 687 return err; 688 } 689 690 /* Max Frame Length */ 691 err = fman_set_mac_max_frame(tgec->fm, tgec->mac_id, 692 cfg->max_frame_length); 693 if (err) { 694 pr_err("Setting max frame length FAILED\n"); 695 free_init_resources(tgec); 696 return -EINVAL; 697 } 698 699 /* FM_TX_FIFO_CORRUPTION_ERRATA_10GMAC_A007 Errata workaround */ 700 if (tgec->fm_rev_info.major == 2) { 701 struct tgec_regs __iomem *regs = tgec->regs; 702 u32 tmp; 703 704 /* restore the default tx ipg Length */ 705 tmp = (ioread32be(®s->tx_ipg_len) & 706 ~TGEC_TX_IPG_LENGTH_MASK) | 12; 707 708 iowrite32be(tmp, ®s->tx_ipg_len); 709 } 710 711 tgec->multicast_addr_hash = alloc_hash_table(TGEC_HASH_TABLE_SIZE); 712 if (!tgec->multicast_addr_hash) { 713 free_init_resources(tgec); 714 pr_err("allocation hash table is FAILED\n"); 715 return -ENOMEM; 716 } 717 718 tgec->unicast_addr_hash = alloc_hash_table(TGEC_HASH_TABLE_SIZE); 719 if (!tgec->unicast_addr_hash) { 720 free_init_resources(tgec); 721 pr_err("allocation hash table is FAILED\n"); 722 return -ENOMEM; 723 } 724 725 fman_register_intr(tgec->fm, FMAN_MOD_MAC, tgec->mac_id, 726 FMAN_INTR_TYPE_ERR, tgec_err_exception, tgec); 727 728 kfree(cfg); 729 tgec->cfg = NULL; 730 731 return 0; 732 } 733 734 int tgec_free(struct fman_mac *tgec) 735 { 736 free_init_resources(tgec); 737 738 kfree(tgec->cfg); 739 kfree(tgec); 740 741 return 0; 742 } 743 744 struct fman_mac *tgec_config(struct fman_mac_params *params) 745 { 746 struct fman_mac *tgec; 747 struct tgec_cfg *cfg; 748 void __iomem *base_addr; 749 750 base_addr = params->base_addr; 751 /* allocate memory for the UCC GETH data structure. */ 752 tgec = kzalloc(sizeof(*tgec), GFP_KERNEL); 753 if (!tgec) 754 return NULL; 755 756 /* allocate memory for the 10G MAC driver parameters data structure. */ 757 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); 758 if (!cfg) { 759 tgec_free(tgec); 760 return NULL; 761 } 762 763 /* Plant parameter structure pointer */ 764 tgec->cfg = cfg; 765 766 set_dflts(cfg); 767 768 tgec->regs = base_addr; 769 tgec->addr = ENET_ADDR_TO_UINT64(params->addr); 770 tgec->max_speed = params->max_speed; 771 tgec->mac_id = params->mac_id; 772 tgec->exceptions = (TGEC_IMASK_MDIO_SCAN_EVENT | 773 TGEC_IMASK_REM_FAULT | 774 TGEC_IMASK_LOC_FAULT | 775 TGEC_IMASK_TX_ECC_ER | 776 TGEC_IMASK_TX_FIFO_UNFL | 777 TGEC_IMASK_TX_FIFO_OVFL | 778 TGEC_IMASK_TX_ER | 779 TGEC_IMASK_RX_FIFO_OVFL | 780 TGEC_IMASK_RX_ECC_ER | 781 TGEC_IMASK_RX_JAB_FRM | 782 TGEC_IMASK_RX_OVRSZ_FRM | 783 TGEC_IMASK_RX_RUNT_FRM | 784 TGEC_IMASK_RX_FRAG_FRM | 785 TGEC_IMASK_RX_CRC_ER | 786 TGEC_IMASK_RX_ALIGN_ER); 787 tgec->exception_cb = params->exception_cb; 788 tgec->event_cb = params->event_cb; 789 tgec->dev_id = params->dev_id; 790 tgec->fm = params->fm; 791 792 /* Save FMan revision */ 793 fman_get_revision(tgec->fm, &tgec->fm_rev_info); 794 795 return tgec; 796 } 797