1 /* 2 * Copyright 2008 - 2015 Freescale Semiconductor Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 34 35 #include <linux/io.h> 36 #include <linux/slab.h> 37 #include <linux/module.h> 38 #include <linux/interrupt.h> 39 #include <linux/of_platform.h> 40 #include <linux/of_address.h> 41 #include <linux/delay.h> 42 #include <linux/libfdt_env.h> 43 44 #include "fman.h" 45 #include "fman_port.h" 46 #include "fman_sp.h" 47 #include "fman_keygen.h" 48 49 /* Queue ID */ 50 #define DFLT_FQ_ID 0x00FFFFFF 51 52 /* General defines */ 53 #define PORT_BMI_FIFO_UNITS 0x100 54 55 #define MAX_PORT_FIFO_SIZE(bmi_max_fifo_size) \ 56 min((u32)bmi_max_fifo_size, (u32)1024 * FMAN_BMI_FIFO_UNITS) 57 58 #define PORT_CG_MAP_NUM 8 59 #define PORT_PRS_RESULT_WORDS_NUM 8 60 #define PORT_IC_OFFSET_UNITS 0x10 61 62 #define MIN_EXT_BUF_SIZE 64 63 64 #define BMI_PORT_REGS_OFFSET 0 65 #define QMI_PORT_REGS_OFFSET 0x400 66 #define HWP_PORT_REGS_OFFSET 0x800 67 68 /* Default values */ 69 #define DFLT_PORT_BUFFER_PREFIX_CONTEXT_DATA_ALIGN \ 70 DFLT_FM_SP_BUFFER_PREFIX_CONTEXT_DATA_ALIGN 71 72 #define DFLT_PORT_CUT_BYTES_FROM_END 4 73 74 #define DFLT_PORT_ERRORS_TO_DISCARD FM_PORT_FRM_ERR_CLS_DISCARD 75 #define DFLT_PORT_MAX_FRAME_LENGTH 9600 76 77 #define DFLT_PORT_RX_FIFO_PRI_ELEVATION_LEV(bmi_max_fifo_size) \ 78 MAX_PORT_FIFO_SIZE(bmi_max_fifo_size) 79 80 #define DFLT_PORT_RX_FIFO_THRESHOLD(major, bmi_max_fifo_size) \ 81 (major == 6 ? \ 82 MAX_PORT_FIFO_SIZE(bmi_max_fifo_size) : \ 83 (MAX_PORT_FIFO_SIZE(bmi_max_fifo_size) * 3 / 4)) \ 84 85 #define DFLT_PORT_EXTRA_NUM_OF_FIFO_BUFS 0 86 87 /* QMI defines */ 88 #define QMI_DEQ_CFG_SUBPORTAL_MASK 0x1f 89 90 #define QMI_PORT_CFG_EN 0x80000000 91 #define QMI_PORT_STATUS_DEQ_FD_BSY 0x20000000 92 93 #define QMI_DEQ_CFG_PRI 0x80000000 94 #define QMI_DEQ_CFG_TYPE1 0x10000000 95 #define QMI_DEQ_CFG_TYPE2 0x20000000 96 #define QMI_DEQ_CFG_TYPE3 0x30000000 97 #define QMI_DEQ_CFG_PREFETCH_PARTIAL 0x01000000 98 #define QMI_DEQ_CFG_PREFETCH_FULL 0x03000000 99 #define QMI_DEQ_CFG_SP_MASK 0xf 100 #define QMI_DEQ_CFG_SP_SHIFT 20 101 102 #define QMI_BYTE_COUNT_LEVEL_CONTROL(_type) \ 103 (_type == FMAN_PORT_TYPE_TX ? 0x1400 : 0x400) 104 105 /* BMI defins */ 106 #define BMI_EBD_EN 0x80000000 107 108 #define BMI_PORT_CFG_EN 0x80000000 109 110 #define BMI_PORT_STATUS_BSY 0x80000000 111 112 #define BMI_DMA_ATTR_SWP_SHIFT FMAN_SP_DMA_ATTR_SWP_SHIFT 113 #define BMI_DMA_ATTR_WRITE_OPTIMIZE FMAN_SP_DMA_ATTR_WRITE_OPTIMIZE 114 115 #define BMI_RX_FIFO_PRI_ELEVATION_SHIFT 16 116 #define BMI_RX_FIFO_THRESHOLD_ETHE 0x80000000 117 118 #define BMI_FRAME_END_CS_IGNORE_SHIFT 24 119 #define BMI_FRAME_END_CS_IGNORE_MASK 0x0000001f 120 121 #define BMI_RX_FRAME_END_CUT_SHIFT 16 122 #define BMI_RX_FRAME_END_CUT_MASK 0x0000001f 123 124 #define BMI_IC_TO_EXT_SHIFT FMAN_SP_IC_TO_EXT_SHIFT 125 #define BMI_IC_TO_EXT_MASK 0x0000001f 126 #define BMI_IC_FROM_INT_SHIFT FMAN_SP_IC_FROM_INT_SHIFT 127 #define BMI_IC_FROM_INT_MASK 0x0000000f 128 #define BMI_IC_SIZE_MASK 0x0000001f 129 130 #define BMI_INT_BUF_MARG_SHIFT 28 131 #define BMI_INT_BUF_MARG_MASK 0x0000000f 132 #define BMI_EXT_BUF_MARG_START_SHIFT FMAN_SP_EXT_BUF_MARG_START_SHIFT 133 #define BMI_EXT_BUF_MARG_START_MASK 0x000001ff 134 #define BMI_EXT_BUF_MARG_END_MASK 0x000001ff 135 136 #define BMI_CMD_MR_LEAC 0x00200000 137 #define BMI_CMD_MR_SLEAC 0x00100000 138 #define BMI_CMD_MR_MA 0x00080000 139 #define BMI_CMD_MR_DEAS 0x00040000 140 #define BMI_CMD_RX_MR_DEF (BMI_CMD_MR_LEAC | \ 141 BMI_CMD_MR_SLEAC | \ 142 BMI_CMD_MR_MA | \ 143 BMI_CMD_MR_DEAS) 144 #define BMI_CMD_TX_MR_DEF 0 145 146 #define BMI_CMD_ATTR_ORDER 0x80000000 147 #define BMI_CMD_ATTR_SYNC 0x02000000 148 #define BMI_CMD_ATTR_COLOR_SHIFT 26 149 150 #define BMI_FIFO_PIPELINE_DEPTH_SHIFT 12 151 #define BMI_FIFO_PIPELINE_DEPTH_MASK 0x0000000f 152 #define BMI_NEXT_ENG_FD_BITS_SHIFT 24 153 154 #define BMI_EXT_BUF_POOL_VALID FMAN_SP_EXT_BUF_POOL_VALID 155 #define BMI_EXT_BUF_POOL_EN_COUNTER FMAN_SP_EXT_BUF_POOL_EN_COUNTER 156 #define BMI_EXT_BUF_POOL_BACKUP FMAN_SP_EXT_BUF_POOL_BACKUP 157 #define BMI_EXT_BUF_POOL_ID_SHIFT 16 158 #define BMI_EXT_BUF_POOL_ID_MASK 0x003F0000 159 #define BMI_POOL_DEP_NUM_OF_POOLS_SHIFT 16 160 161 #define BMI_TX_FIFO_MIN_FILL_SHIFT 16 162 163 #define BMI_PRIORITY_ELEVATION_LEVEL ((0x3FF + 1) * PORT_BMI_FIFO_UNITS) 164 #define BMI_FIFO_THRESHOLD ((0x3FF + 1) * PORT_BMI_FIFO_UNITS) 165 166 #define BMI_DEQUEUE_PIPELINE_DEPTH(_type, _speed) \ 167 ((_type == FMAN_PORT_TYPE_TX && _speed == 10000) ? 4 : 1) 168 169 #define RX_ERRS_TO_ENQ \ 170 (FM_PORT_FRM_ERR_DMA | \ 171 FM_PORT_FRM_ERR_PHYSICAL | \ 172 FM_PORT_FRM_ERR_SIZE | \ 173 FM_PORT_FRM_ERR_EXTRACTION | \ 174 FM_PORT_FRM_ERR_NO_SCHEME | \ 175 FM_PORT_FRM_ERR_PRS_TIMEOUT | \ 176 FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT | \ 177 FM_PORT_FRM_ERR_BLOCK_LIMIT_EXCEEDED | \ 178 FM_PORT_FRM_ERR_PRS_HDR_ERR | \ 179 FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW | \ 180 FM_PORT_FRM_ERR_IPRE) 181 182 /* NIA defines */ 183 #define NIA_ORDER_RESTOR 0x00800000 184 #define NIA_ENG_BMI 0x00500000 185 #define NIA_ENG_QMI_ENQ 0x00540000 186 #define NIA_ENG_QMI_DEQ 0x00580000 187 #define NIA_ENG_HWP 0x00440000 188 #define NIA_ENG_HWK 0x00480000 189 #define NIA_BMI_AC_ENQ_FRAME 0x00000002 190 #define NIA_BMI_AC_TX_RELEASE 0x000002C0 191 #define NIA_BMI_AC_RELEASE 0x000000C0 192 #define NIA_BMI_AC_TX 0x00000274 193 #define NIA_BMI_AC_FETCH_ALL_FRAME 0x0000020c 194 195 /* Port IDs */ 196 #define TX_10G_PORT_BASE 0x30 197 #define RX_10G_PORT_BASE 0x10 198 199 /* BMI Rx port register map */ 200 struct fman_port_rx_bmi_regs { 201 u32 fmbm_rcfg; /* Rx Configuration */ 202 u32 fmbm_rst; /* Rx Status */ 203 u32 fmbm_rda; /* Rx DMA attributes */ 204 u32 fmbm_rfp; /* Rx FIFO Parameters */ 205 u32 fmbm_rfed; /* Rx Frame End Data */ 206 u32 fmbm_ricp; /* Rx Internal Context Parameters */ 207 u32 fmbm_rim; /* Rx Internal Buffer Margins */ 208 u32 fmbm_rebm; /* Rx External Buffer Margins */ 209 u32 fmbm_rfne; /* Rx Frame Next Engine */ 210 u32 fmbm_rfca; /* Rx Frame Command Attributes. */ 211 u32 fmbm_rfpne; /* Rx Frame Parser Next Engine */ 212 u32 fmbm_rpso; /* Rx Parse Start Offset */ 213 u32 fmbm_rpp; /* Rx Policer Profile */ 214 u32 fmbm_rccb; /* Rx Coarse Classification Base */ 215 u32 fmbm_reth; /* Rx Excessive Threshold */ 216 u32 reserved003c[1]; /* (0x03C 0x03F) */ 217 u32 fmbm_rprai[PORT_PRS_RESULT_WORDS_NUM]; 218 /* Rx Parse Results Array Init */ 219 u32 fmbm_rfqid; /* Rx Frame Queue ID */ 220 u32 fmbm_refqid; /* Rx Error Frame Queue ID */ 221 u32 fmbm_rfsdm; /* Rx Frame Status Discard Mask */ 222 u32 fmbm_rfsem; /* Rx Frame Status Error Mask */ 223 u32 fmbm_rfene; /* Rx Frame Enqueue Next Engine */ 224 u32 reserved0074[0x2]; /* (0x074-0x07C) */ 225 u32 fmbm_rcmne; /* Rx Frame Continuous Mode Next Engine */ 226 u32 reserved0080[0x20]; /* (0x080 0x0FF) */ 227 u32 fmbm_ebmpi[FMAN_PORT_MAX_EXT_POOLS_NUM]; 228 /* Buffer Manager pool Information- */ 229 u32 fmbm_acnt[FMAN_PORT_MAX_EXT_POOLS_NUM]; /* Allocate Counter- */ 230 u32 reserved0130[8]; /* 0x130/0x140 - 0x15F reserved - */ 231 u32 fmbm_rcgm[PORT_CG_MAP_NUM]; /* Congestion Group Map */ 232 u32 fmbm_mpd; /* BM Pool Depletion */ 233 u32 reserved0184[0x1F]; /* (0x184 0x1FF) */ 234 u32 fmbm_rstc; /* Rx Statistics Counters */ 235 u32 fmbm_rfrc; /* Rx Frame Counter */ 236 u32 fmbm_rfbc; /* Rx Bad Frames Counter */ 237 u32 fmbm_rlfc; /* Rx Large Frames Counter */ 238 u32 fmbm_rffc; /* Rx Filter Frames Counter */ 239 u32 fmbm_rfdc; /* Rx Frame Discard Counter */ 240 u32 fmbm_rfldec; /* Rx Frames List DMA Error Counter */ 241 u32 fmbm_rodc; /* Rx Out of Buffers Discard nntr */ 242 u32 fmbm_rbdc; /* Rx Buffers Deallocate Counter */ 243 u32 fmbm_rpec; /* RX Prepare to enqueue Counte */ 244 u32 reserved0224[0x16]; /* (0x224 0x27F) */ 245 u32 fmbm_rpc; /* Rx Performance Counters */ 246 u32 fmbm_rpcp; /* Rx Performance Count Parameters */ 247 u32 fmbm_rccn; /* Rx Cycle Counter */ 248 u32 fmbm_rtuc; /* Rx Tasks Utilization Counter */ 249 u32 fmbm_rrquc; /* Rx Receive Queue Utilization cntr */ 250 u32 fmbm_rduc; /* Rx DMA Utilization Counter */ 251 u32 fmbm_rfuc; /* Rx FIFO Utilization Counter */ 252 u32 fmbm_rpac; /* Rx Pause Activation Counter */ 253 u32 reserved02a0[0x18]; /* (0x2A0 0x2FF) */ 254 u32 fmbm_rdcfg[0x3]; /* Rx Debug Configuration */ 255 u32 fmbm_rgpr; /* Rx General Purpose Register */ 256 u32 reserved0310[0x3a]; 257 }; 258 259 /* BMI Tx port register map */ 260 struct fman_port_tx_bmi_regs { 261 u32 fmbm_tcfg; /* Tx Configuration */ 262 u32 fmbm_tst; /* Tx Status */ 263 u32 fmbm_tda; /* Tx DMA attributes */ 264 u32 fmbm_tfp; /* Tx FIFO Parameters */ 265 u32 fmbm_tfed; /* Tx Frame End Data */ 266 u32 fmbm_ticp; /* Tx Internal Context Parameters */ 267 u32 fmbm_tfdne; /* Tx Frame Dequeue Next Engine. */ 268 u32 fmbm_tfca; /* Tx Frame Command attribute. */ 269 u32 fmbm_tcfqid; /* Tx Confirmation Frame Queue ID. */ 270 u32 fmbm_tefqid; /* Tx Frame Error Queue ID */ 271 u32 fmbm_tfene; /* Tx Frame Enqueue Next Engine */ 272 u32 fmbm_trlmts; /* Tx Rate Limiter Scale */ 273 u32 fmbm_trlmt; /* Tx Rate Limiter */ 274 u32 reserved0034[0x0e]; /* (0x034-0x6c) */ 275 u32 fmbm_tccb; /* Tx Coarse Classification base */ 276 u32 fmbm_tfne; /* Tx Frame Next Engine */ 277 u32 fmbm_tpfcm[0x02]; 278 /* Tx Priority based Flow Control (PFC) Mapping */ 279 u32 fmbm_tcmne; /* Tx Frame Continuous Mode Next Engine */ 280 u32 reserved0080[0x60]; /* (0x080-0x200) */ 281 u32 fmbm_tstc; /* Tx Statistics Counters */ 282 u32 fmbm_tfrc; /* Tx Frame Counter */ 283 u32 fmbm_tfdc; /* Tx Frames Discard Counter */ 284 u32 fmbm_tfledc; /* Tx Frame len error discard cntr */ 285 u32 fmbm_tfufdc; /* Tx Frame unsprt frmt discard cntr */ 286 u32 fmbm_tbdc; /* Tx Buffers Deallocate Counter */ 287 u32 reserved0218[0x1A]; /* (0x218-0x280) */ 288 u32 fmbm_tpc; /* Tx Performance Counters */ 289 u32 fmbm_tpcp; /* Tx Performance Count Parameters */ 290 u32 fmbm_tccn; /* Tx Cycle Counter */ 291 u32 fmbm_ttuc; /* Tx Tasks Utilization Counter */ 292 u32 fmbm_ttcquc; /* Tx Transmit conf Q util Counter */ 293 u32 fmbm_tduc; /* Tx DMA Utilization Counter */ 294 u32 fmbm_tfuc; /* Tx FIFO Utilization Counter */ 295 u32 reserved029c[16]; /* (0x29C-0x2FF) */ 296 u32 fmbm_tdcfg[0x3]; /* Tx Debug Configuration */ 297 u32 fmbm_tgpr; /* Tx General Purpose Register */ 298 u32 reserved0310[0x3a]; /* (0x310-0x3FF) */ 299 }; 300 301 /* BMI port register map */ 302 union fman_port_bmi_regs { 303 struct fman_port_rx_bmi_regs rx; 304 struct fman_port_tx_bmi_regs tx; 305 }; 306 307 /* QMI port register map */ 308 struct fman_port_qmi_regs { 309 u32 fmqm_pnc; /* PortID n Configuration Register */ 310 u32 fmqm_pns; /* PortID n Status Register */ 311 u32 fmqm_pnts; /* PortID n Task Status Register */ 312 u32 reserved00c[4]; /* 0xn00C - 0xn01B */ 313 u32 fmqm_pnen; /* PortID n Enqueue NIA Register */ 314 u32 fmqm_pnetfc; /* PortID n Enq Total Frame Counter */ 315 u32 reserved024[2]; /* 0xn024 - 0x02B */ 316 u32 fmqm_pndn; /* PortID n Dequeue NIA Register */ 317 u32 fmqm_pndc; /* PortID n Dequeue Config Register */ 318 u32 fmqm_pndtfc; /* PortID n Dequeue tot Frame cntr */ 319 u32 fmqm_pndfdc; /* PortID n Dequeue FQID Dflt Cntr */ 320 u32 fmqm_pndcc; /* PortID n Dequeue Confirm Counter */ 321 }; 322 323 #define HWP_HXS_COUNT 16 324 #define HWP_HXS_PHE_REPORT 0x00000800 325 #define HWP_HXS_PCAC_PSTAT 0x00000100 326 #define HWP_HXS_PCAC_PSTOP 0x00000001 327 #define HWP_HXS_TCP_OFFSET 0xA 328 #define HWP_HXS_UDP_OFFSET 0xB 329 #define HWP_HXS_SH_PAD_REM 0x80000000 330 331 struct fman_port_hwp_regs { 332 struct { 333 u32 ssa; /* Soft Sequence Attachment */ 334 u32 lcv; /* Line-up Enable Confirmation Mask */ 335 } pmda[HWP_HXS_COUNT]; /* Parse Memory Direct Access Registers */ 336 u32 reserved080[(0x3f8 - 0x080) / 4]; /* (0x080-0x3f7) */ 337 u32 fmpr_pcac; /* Configuration Access Control */ 338 }; 339 340 /* QMI dequeue prefetch modes */ 341 enum fman_port_deq_prefetch { 342 FMAN_PORT_DEQ_NO_PREFETCH, /* No prefetch mode */ 343 FMAN_PORT_DEQ_PART_PREFETCH, /* Partial prefetch mode */ 344 FMAN_PORT_DEQ_FULL_PREFETCH /* Full prefetch mode */ 345 }; 346 347 /* A structure for defining FM port resources */ 348 struct fman_port_rsrc { 349 u32 num; /* Committed required resource */ 350 u32 extra; /* Extra (not committed) required resource */ 351 }; 352 353 enum fman_port_dma_swap { 354 FMAN_PORT_DMA_NO_SWAP, /* No swap, transfer data as is */ 355 FMAN_PORT_DMA_SWAP_LE, 356 /* The transferred data should be swapped in PPC Little Endian mode */ 357 FMAN_PORT_DMA_SWAP_BE 358 /* The transferred data should be swapped in Big Endian mode */ 359 }; 360 361 /* Default port color */ 362 enum fman_port_color { 363 FMAN_PORT_COLOR_GREEN, /* Default port color is green */ 364 FMAN_PORT_COLOR_YELLOW, /* Default port color is yellow */ 365 FMAN_PORT_COLOR_RED, /* Default port color is red */ 366 FMAN_PORT_COLOR_OVERRIDE /* Ignore color */ 367 }; 368 369 /* QMI dequeue from the SP channel - types */ 370 enum fman_port_deq_type { 371 FMAN_PORT_DEQ_BY_PRI, 372 /* Priority precedence and Intra-Class scheduling */ 373 FMAN_PORT_DEQ_ACTIVE_FQ, 374 /* Active FQ precedence and Intra-Class scheduling */ 375 FMAN_PORT_DEQ_ACTIVE_FQ_NO_ICS 376 /* Active FQ precedence and override Intra-Class scheduling */ 377 }; 378 379 /* External buffer pools configuration */ 380 struct fman_port_bpools { 381 u8 count; /* Num of pools to set up */ 382 bool counters_enable; /* Enable allocate counters */ 383 u8 grp_bp_depleted_num; 384 /* Number of depleted pools - if reached the BMI indicates 385 * the MAC to send a pause frame 386 */ 387 struct { 388 u8 bpid; /* BM pool ID */ 389 u16 size; 390 /* Pool's size - must be in ascending order */ 391 bool is_backup; 392 /* If this is a backup pool */ 393 bool grp_bp_depleted; 394 /* Consider this buffer in multiple pools depletion criteria */ 395 bool single_bp_depleted; 396 /* Consider this buffer in single pool depletion criteria */ 397 } bpool[FMAN_PORT_MAX_EXT_POOLS_NUM]; 398 }; 399 400 struct fman_port_cfg { 401 u32 dflt_fqid; 402 u32 err_fqid; 403 u32 pcd_base_fqid; 404 u32 pcd_fqs_count; 405 u8 deq_sp; 406 bool deq_high_priority; 407 enum fman_port_deq_type deq_type; 408 enum fman_port_deq_prefetch deq_prefetch_option; 409 u16 deq_byte_cnt; 410 u8 cheksum_last_bytes_ignore; 411 u8 rx_cut_end_bytes; 412 struct fman_buf_pool_depletion buf_pool_depletion; 413 struct fman_ext_pools ext_buf_pools; 414 u32 tx_fifo_min_level; 415 u32 tx_fifo_low_comf_level; 416 u32 rx_pri_elevation; 417 u32 rx_fifo_thr; 418 struct fman_sp_buf_margins buf_margins; 419 u32 int_buf_start_margin; 420 struct fman_sp_int_context_data_copy int_context; 421 u32 discard_mask; 422 u32 err_mask; 423 struct fman_buffer_prefix_content buffer_prefix_content; 424 bool dont_release_buf; 425 426 u8 rx_fd_bits; 427 u32 tx_fifo_deq_pipeline_depth; 428 bool errata_A006320; 429 bool excessive_threshold_register; 430 bool fmbm_tfne_has_features; 431 432 enum fman_port_dma_swap dma_swap_data; 433 enum fman_port_color color; 434 }; 435 436 struct fman_port_rx_pools_params { 437 u8 num_of_pools; 438 u16 largest_buf_size; 439 }; 440 441 struct fman_port_dts_params { 442 void __iomem *base_addr; /* FMan port virtual memory */ 443 enum fman_port_type type; /* Port type */ 444 u16 speed; /* Port speed */ 445 u8 id; /* HW Port Id */ 446 u32 qman_channel_id; /* QMan channel id (non RX only) */ 447 struct fman *fman; /* FMan Handle */ 448 }; 449 450 struct fman_port { 451 void *fm; 452 struct device *dev; 453 struct fman_rev_info rev_info; 454 u8 port_id; 455 enum fman_port_type port_type; 456 u16 port_speed; 457 458 union fman_port_bmi_regs __iomem *bmi_regs; 459 struct fman_port_qmi_regs __iomem *qmi_regs; 460 struct fman_port_hwp_regs __iomem *hwp_regs; 461 462 struct fman_sp_buffer_offsets buffer_offsets; 463 464 u8 internal_buf_offset; 465 struct fman_ext_pools ext_buf_pools; 466 467 u16 max_frame_length; 468 struct fman_port_rsrc open_dmas; 469 struct fman_port_rsrc tasks; 470 struct fman_port_rsrc fifo_bufs; 471 struct fman_port_rx_pools_params rx_pools_params; 472 473 struct fman_port_cfg *cfg; 474 struct fman_port_dts_params dts_params; 475 476 u8 ext_pools_num; 477 u32 max_port_fifo_size; 478 u32 max_num_of_ext_pools; 479 u32 max_num_of_sub_portals; 480 u32 bm_max_num_of_pools; 481 }; 482 483 static int init_bmi_rx(struct fman_port *port) 484 { 485 struct fman_port_rx_bmi_regs __iomem *regs = &port->bmi_regs->rx; 486 struct fman_port_cfg *cfg = port->cfg; 487 u32 tmp; 488 489 /* DMA attributes */ 490 tmp = (u32)cfg->dma_swap_data << BMI_DMA_ATTR_SWP_SHIFT; 491 /* Enable write optimization */ 492 tmp |= BMI_DMA_ATTR_WRITE_OPTIMIZE; 493 iowrite32be(tmp, ®s->fmbm_rda); 494 495 /* Rx FIFO parameters */ 496 tmp = (cfg->rx_pri_elevation / PORT_BMI_FIFO_UNITS - 1) << 497 BMI_RX_FIFO_PRI_ELEVATION_SHIFT; 498 tmp |= cfg->rx_fifo_thr / PORT_BMI_FIFO_UNITS - 1; 499 iowrite32be(tmp, ®s->fmbm_rfp); 500 501 if (cfg->excessive_threshold_register) 502 /* always allow access to the extra resources */ 503 iowrite32be(BMI_RX_FIFO_THRESHOLD_ETHE, ®s->fmbm_reth); 504 505 /* Frame end data */ 506 tmp = (cfg->cheksum_last_bytes_ignore & BMI_FRAME_END_CS_IGNORE_MASK) << 507 BMI_FRAME_END_CS_IGNORE_SHIFT; 508 tmp |= (cfg->rx_cut_end_bytes & BMI_RX_FRAME_END_CUT_MASK) << 509 BMI_RX_FRAME_END_CUT_SHIFT; 510 if (cfg->errata_A006320) 511 tmp &= 0xffe0ffff; 512 iowrite32be(tmp, ®s->fmbm_rfed); 513 514 /* Internal context parameters */ 515 tmp = ((cfg->int_context.ext_buf_offset / PORT_IC_OFFSET_UNITS) & 516 BMI_IC_TO_EXT_MASK) << BMI_IC_TO_EXT_SHIFT; 517 tmp |= ((cfg->int_context.int_context_offset / PORT_IC_OFFSET_UNITS) & 518 BMI_IC_FROM_INT_MASK) << BMI_IC_FROM_INT_SHIFT; 519 tmp |= (cfg->int_context.size / PORT_IC_OFFSET_UNITS) & 520 BMI_IC_SIZE_MASK; 521 iowrite32be(tmp, ®s->fmbm_ricp); 522 523 /* Internal buffer offset */ 524 tmp = ((cfg->int_buf_start_margin / PORT_IC_OFFSET_UNITS) & 525 BMI_INT_BUF_MARG_MASK) << BMI_INT_BUF_MARG_SHIFT; 526 iowrite32be(tmp, ®s->fmbm_rim); 527 528 /* External buffer margins */ 529 tmp = (cfg->buf_margins.start_margins & BMI_EXT_BUF_MARG_START_MASK) << 530 BMI_EXT_BUF_MARG_START_SHIFT; 531 tmp |= cfg->buf_margins.end_margins & BMI_EXT_BUF_MARG_END_MASK; 532 iowrite32be(tmp, ®s->fmbm_rebm); 533 534 /* Frame attributes */ 535 tmp = BMI_CMD_RX_MR_DEF; 536 tmp |= BMI_CMD_ATTR_ORDER; 537 tmp |= (u32)cfg->color << BMI_CMD_ATTR_COLOR_SHIFT; 538 /* Synchronization request */ 539 tmp |= BMI_CMD_ATTR_SYNC; 540 541 iowrite32be(tmp, ®s->fmbm_rfca); 542 543 /* NIA */ 544 tmp = (u32)cfg->rx_fd_bits << BMI_NEXT_ENG_FD_BITS_SHIFT; 545 546 tmp |= NIA_ENG_HWP; 547 iowrite32be(tmp, ®s->fmbm_rfne); 548 549 /* Parser Next Engine NIA */ 550 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME, ®s->fmbm_rfpne); 551 552 /* Enqueue NIA */ 553 iowrite32be(NIA_ENG_QMI_ENQ | NIA_ORDER_RESTOR, ®s->fmbm_rfene); 554 555 /* Default/error queues */ 556 iowrite32be((cfg->dflt_fqid & DFLT_FQ_ID), ®s->fmbm_rfqid); 557 iowrite32be((cfg->err_fqid & DFLT_FQ_ID), ®s->fmbm_refqid); 558 559 /* Discard/error masks */ 560 iowrite32be(cfg->discard_mask, ®s->fmbm_rfsdm); 561 iowrite32be(cfg->err_mask, ®s->fmbm_rfsem); 562 563 return 0; 564 } 565 566 static int init_bmi_tx(struct fman_port *port) 567 { 568 struct fman_port_tx_bmi_regs __iomem *regs = &port->bmi_regs->tx; 569 struct fman_port_cfg *cfg = port->cfg; 570 u32 tmp; 571 572 /* Tx Configuration register */ 573 tmp = 0; 574 iowrite32be(tmp, ®s->fmbm_tcfg); 575 576 /* DMA attributes */ 577 tmp = (u32)cfg->dma_swap_data << BMI_DMA_ATTR_SWP_SHIFT; 578 iowrite32be(tmp, ®s->fmbm_tda); 579 580 /* Tx FIFO parameters */ 581 tmp = (cfg->tx_fifo_min_level / PORT_BMI_FIFO_UNITS) << 582 BMI_TX_FIFO_MIN_FILL_SHIFT; 583 tmp |= ((cfg->tx_fifo_deq_pipeline_depth - 1) & 584 BMI_FIFO_PIPELINE_DEPTH_MASK) << BMI_FIFO_PIPELINE_DEPTH_SHIFT; 585 tmp |= (cfg->tx_fifo_low_comf_level / PORT_BMI_FIFO_UNITS) - 1; 586 iowrite32be(tmp, ®s->fmbm_tfp); 587 588 /* Frame end data */ 589 tmp = (cfg->cheksum_last_bytes_ignore & BMI_FRAME_END_CS_IGNORE_MASK) << 590 BMI_FRAME_END_CS_IGNORE_SHIFT; 591 iowrite32be(tmp, ®s->fmbm_tfed); 592 593 /* Internal context parameters */ 594 tmp = ((cfg->int_context.ext_buf_offset / PORT_IC_OFFSET_UNITS) & 595 BMI_IC_TO_EXT_MASK) << BMI_IC_TO_EXT_SHIFT; 596 tmp |= ((cfg->int_context.int_context_offset / PORT_IC_OFFSET_UNITS) & 597 BMI_IC_FROM_INT_MASK) << BMI_IC_FROM_INT_SHIFT; 598 tmp |= (cfg->int_context.size / PORT_IC_OFFSET_UNITS) & 599 BMI_IC_SIZE_MASK; 600 iowrite32be(tmp, ®s->fmbm_ticp); 601 602 /* Frame attributes */ 603 tmp = BMI_CMD_TX_MR_DEF; 604 tmp |= BMI_CMD_ATTR_ORDER; 605 tmp |= (u32)cfg->color << BMI_CMD_ATTR_COLOR_SHIFT; 606 iowrite32be(tmp, ®s->fmbm_tfca); 607 608 /* Dequeue NIA + enqueue NIA */ 609 iowrite32be(NIA_ENG_QMI_DEQ, ®s->fmbm_tfdne); 610 iowrite32be(NIA_ENG_QMI_ENQ | NIA_ORDER_RESTOR, ®s->fmbm_tfene); 611 if (cfg->fmbm_tfne_has_features) 612 iowrite32be(!cfg->dflt_fqid ? 613 BMI_EBD_EN | NIA_BMI_AC_FETCH_ALL_FRAME : 614 NIA_BMI_AC_FETCH_ALL_FRAME, ®s->fmbm_tfne); 615 if (!cfg->dflt_fqid && cfg->dont_release_buf) { 616 iowrite32be(DFLT_FQ_ID, ®s->fmbm_tcfqid); 617 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE, 618 ®s->fmbm_tfene); 619 if (cfg->fmbm_tfne_has_features) 620 iowrite32be(ioread32be(®s->fmbm_tfne) & ~BMI_EBD_EN, 621 ®s->fmbm_tfne); 622 } 623 624 /* Confirmation/error queues */ 625 if (cfg->dflt_fqid || !cfg->dont_release_buf) 626 iowrite32be(cfg->dflt_fqid & DFLT_FQ_ID, ®s->fmbm_tcfqid); 627 iowrite32be((cfg->err_fqid & DFLT_FQ_ID), ®s->fmbm_tefqid); 628 629 return 0; 630 } 631 632 static int init_qmi(struct fman_port *port) 633 { 634 struct fman_port_qmi_regs __iomem *regs = port->qmi_regs; 635 struct fman_port_cfg *cfg = port->cfg; 636 u32 tmp; 637 638 /* Rx port configuration */ 639 if (port->port_type == FMAN_PORT_TYPE_RX) { 640 /* Enqueue NIA */ 641 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_RELEASE, ®s->fmqm_pnen); 642 return 0; 643 } 644 645 /* Continue with Tx port configuration */ 646 if (port->port_type == FMAN_PORT_TYPE_TX) { 647 /* Enqueue NIA */ 648 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE, 649 ®s->fmqm_pnen); 650 /* Dequeue NIA */ 651 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX, ®s->fmqm_pndn); 652 } 653 654 /* Dequeue Configuration register */ 655 tmp = 0; 656 if (cfg->deq_high_priority) 657 tmp |= QMI_DEQ_CFG_PRI; 658 659 switch (cfg->deq_type) { 660 case FMAN_PORT_DEQ_BY_PRI: 661 tmp |= QMI_DEQ_CFG_TYPE1; 662 break; 663 case FMAN_PORT_DEQ_ACTIVE_FQ: 664 tmp |= QMI_DEQ_CFG_TYPE2; 665 break; 666 case FMAN_PORT_DEQ_ACTIVE_FQ_NO_ICS: 667 tmp |= QMI_DEQ_CFG_TYPE3; 668 break; 669 default: 670 return -EINVAL; 671 } 672 673 switch (cfg->deq_prefetch_option) { 674 case FMAN_PORT_DEQ_NO_PREFETCH: 675 break; 676 case FMAN_PORT_DEQ_PART_PREFETCH: 677 tmp |= QMI_DEQ_CFG_PREFETCH_PARTIAL; 678 break; 679 case FMAN_PORT_DEQ_FULL_PREFETCH: 680 tmp |= QMI_DEQ_CFG_PREFETCH_FULL; 681 break; 682 default: 683 return -EINVAL; 684 } 685 686 tmp |= (cfg->deq_sp & QMI_DEQ_CFG_SP_MASK) << QMI_DEQ_CFG_SP_SHIFT; 687 tmp |= cfg->deq_byte_cnt; 688 iowrite32be(tmp, ®s->fmqm_pndc); 689 690 return 0; 691 } 692 693 static void stop_port_hwp(struct fman_port *port) 694 { 695 struct fman_port_hwp_regs __iomem *regs = port->hwp_regs; 696 int cnt = 100; 697 698 iowrite32be(HWP_HXS_PCAC_PSTOP, ®s->fmpr_pcac); 699 700 while (cnt-- > 0 && 701 (ioread32be(®s->fmpr_pcac) & HWP_HXS_PCAC_PSTAT)) 702 udelay(10); 703 if (!cnt) 704 pr_err("Timeout stopping HW Parser\n"); 705 } 706 707 static void start_port_hwp(struct fman_port *port) 708 { 709 struct fman_port_hwp_regs __iomem *regs = port->hwp_regs; 710 int cnt = 100; 711 712 iowrite32be(0, ®s->fmpr_pcac); 713 714 while (cnt-- > 0 && 715 !(ioread32be(®s->fmpr_pcac) & HWP_HXS_PCAC_PSTAT)) 716 udelay(10); 717 if (!cnt) 718 pr_err("Timeout starting HW Parser\n"); 719 } 720 721 static void init_hwp(struct fman_port *port) 722 { 723 struct fman_port_hwp_regs __iomem *regs = port->hwp_regs; 724 int i; 725 726 stop_port_hwp(port); 727 728 for (i = 0; i < HWP_HXS_COUNT; i++) { 729 /* enable HXS error reporting into FD[STATUS] PHE */ 730 iowrite32be(0x00000000, ®s->pmda[i].ssa); 731 iowrite32be(0xffffffff, ®s->pmda[i].lcv); 732 } 733 734 /* Short packet padding removal from checksum calculation */ 735 iowrite32be(HWP_HXS_SH_PAD_REM, ®s->pmda[HWP_HXS_TCP_OFFSET].ssa); 736 iowrite32be(HWP_HXS_SH_PAD_REM, ®s->pmda[HWP_HXS_UDP_OFFSET].ssa); 737 738 start_port_hwp(port); 739 } 740 741 static int init(struct fman_port *port) 742 { 743 int err; 744 745 /* Init BMI registers */ 746 switch (port->port_type) { 747 case FMAN_PORT_TYPE_RX: 748 err = init_bmi_rx(port); 749 if (!err) 750 init_hwp(port); 751 break; 752 case FMAN_PORT_TYPE_TX: 753 err = init_bmi_tx(port); 754 break; 755 default: 756 return -EINVAL; 757 } 758 759 if (err) 760 return err; 761 762 /* Init QMI registers */ 763 err = init_qmi(port); 764 if (err) 765 return err; 766 767 return 0; 768 } 769 770 static int set_bpools(const struct fman_port *port, 771 const struct fman_port_bpools *bp) 772 { 773 u32 __iomem *bp_reg, *bp_depl_reg; 774 u32 tmp; 775 u8 i, max_bp_num; 776 bool grp_depl_used = false, rx_port; 777 778 switch (port->port_type) { 779 case FMAN_PORT_TYPE_RX: 780 max_bp_num = port->ext_pools_num; 781 rx_port = true; 782 bp_reg = port->bmi_regs->rx.fmbm_ebmpi; 783 bp_depl_reg = &port->bmi_regs->rx.fmbm_mpd; 784 break; 785 default: 786 return -EINVAL; 787 } 788 789 if (rx_port) { 790 /* Check buffers are provided in ascending order */ 791 for (i = 0; (i < (bp->count - 1) && 792 (i < FMAN_PORT_MAX_EXT_POOLS_NUM - 1)); i++) { 793 if (bp->bpool[i].size > bp->bpool[i + 1].size) 794 return -EINVAL; 795 } 796 } 797 798 /* Set up external buffers pools */ 799 for (i = 0; i < bp->count; i++) { 800 tmp = BMI_EXT_BUF_POOL_VALID; 801 tmp |= ((u32)bp->bpool[i].bpid << 802 BMI_EXT_BUF_POOL_ID_SHIFT) & BMI_EXT_BUF_POOL_ID_MASK; 803 804 if (rx_port) { 805 if (bp->counters_enable) 806 tmp |= BMI_EXT_BUF_POOL_EN_COUNTER; 807 808 if (bp->bpool[i].is_backup) 809 tmp |= BMI_EXT_BUF_POOL_BACKUP; 810 811 tmp |= (u32)bp->bpool[i].size; 812 } 813 814 iowrite32be(tmp, &bp_reg[i]); 815 } 816 817 /* Clear unused pools */ 818 for (i = bp->count; i < max_bp_num; i++) 819 iowrite32be(0, &bp_reg[i]); 820 821 /* Pools depletion */ 822 tmp = 0; 823 for (i = 0; i < FMAN_PORT_MAX_EXT_POOLS_NUM; i++) { 824 if (bp->bpool[i].grp_bp_depleted) { 825 grp_depl_used = true; 826 tmp |= 0x80000000 >> i; 827 } 828 829 if (bp->bpool[i].single_bp_depleted) 830 tmp |= 0x80 >> i; 831 } 832 833 if (grp_depl_used) 834 tmp |= ((u32)bp->grp_bp_depleted_num - 1) << 835 BMI_POOL_DEP_NUM_OF_POOLS_SHIFT; 836 837 iowrite32be(tmp, bp_depl_reg); 838 return 0; 839 } 840 841 static bool is_init_done(struct fman_port_cfg *cfg) 842 { 843 /* Checks if FMan port driver parameters were initialized */ 844 if (!cfg) 845 return true; 846 847 return false; 848 } 849 850 static int verify_size_of_fifo(struct fman_port *port) 851 { 852 u32 min_fifo_size_required = 0, opt_fifo_size_for_b2b = 0; 853 854 /* TX Ports */ 855 if (port->port_type == FMAN_PORT_TYPE_TX) { 856 min_fifo_size_required = (u32) 857 (roundup(port->max_frame_length, 858 FMAN_BMI_FIFO_UNITS) + (3 * FMAN_BMI_FIFO_UNITS)); 859 860 min_fifo_size_required += 861 port->cfg->tx_fifo_deq_pipeline_depth * 862 FMAN_BMI_FIFO_UNITS; 863 864 opt_fifo_size_for_b2b = min_fifo_size_required; 865 866 /* Add some margin for back-to-back capability to improve 867 * performance, allows the hardware to pipeline new frame dma 868 * while the previous frame not yet transmitted. 869 */ 870 if (port->port_speed == 10000) 871 opt_fifo_size_for_b2b += 3 * FMAN_BMI_FIFO_UNITS; 872 else 873 opt_fifo_size_for_b2b += 2 * FMAN_BMI_FIFO_UNITS; 874 } 875 876 /* RX Ports */ 877 else if (port->port_type == FMAN_PORT_TYPE_RX) { 878 if (port->rev_info.major >= 6) 879 min_fifo_size_required = (u32) 880 (roundup(port->max_frame_length, 881 FMAN_BMI_FIFO_UNITS) + 882 (5 * FMAN_BMI_FIFO_UNITS)); 883 /* 4 according to spec + 1 for FOF>0 */ 884 else 885 min_fifo_size_required = (u32) 886 (roundup(min(port->max_frame_length, 887 port->rx_pools_params.largest_buf_size), 888 FMAN_BMI_FIFO_UNITS) + 889 (7 * FMAN_BMI_FIFO_UNITS)); 890 891 opt_fifo_size_for_b2b = min_fifo_size_required; 892 893 /* Add some margin for back-to-back capability to improve 894 * performance,allows the hardware to pipeline new frame dma 895 * while the previous frame not yet transmitted. 896 */ 897 if (port->port_speed == 10000) 898 opt_fifo_size_for_b2b += 8 * FMAN_BMI_FIFO_UNITS; 899 else 900 opt_fifo_size_for_b2b += 3 * FMAN_BMI_FIFO_UNITS; 901 } 902 903 WARN_ON(min_fifo_size_required <= 0); 904 WARN_ON(opt_fifo_size_for_b2b < min_fifo_size_required); 905 906 /* Verify the size */ 907 if (port->fifo_bufs.num < min_fifo_size_required) 908 dev_dbg(port->dev, "%s: FIFO size should be enlarged to %d bytes\n", 909 __func__, min_fifo_size_required); 910 else if (port->fifo_bufs.num < opt_fifo_size_for_b2b) 911 dev_dbg(port->dev, "%s: For b2b processing,FIFO may be enlarged to %d bytes\n", 912 __func__, opt_fifo_size_for_b2b); 913 914 return 0; 915 } 916 917 static int set_ext_buffer_pools(struct fman_port *port) 918 { 919 struct fman_ext_pools *ext_buf_pools = &port->cfg->ext_buf_pools; 920 struct fman_buf_pool_depletion *buf_pool_depletion = 921 &port->cfg->buf_pool_depletion; 922 u8 ordered_array[FMAN_PORT_MAX_EXT_POOLS_NUM]; 923 u16 sizes_array[BM_MAX_NUM_OF_POOLS]; 924 int i = 0, j = 0, err; 925 struct fman_port_bpools bpools; 926 927 memset(&ordered_array, 0, sizeof(u8) * FMAN_PORT_MAX_EXT_POOLS_NUM); 928 memset(&sizes_array, 0, sizeof(u16) * BM_MAX_NUM_OF_POOLS); 929 memcpy(&port->ext_buf_pools, ext_buf_pools, 930 sizeof(struct fman_ext_pools)); 931 932 fman_sp_set_buf_pools_in_asc_order_of_buf_sizes(ext_buf_pools, 933 ordered_array, 934 sizes_array); 935 936 memset(&bpools, 0, sizeof(struct fman_port_bpools)); 937 bpools.count = ext_buf_pools->num_of_pools_used; 938 bpools.counters_enable = true; 939 for (i = 0; i < ext_buf_pools->num_of_pools_used; i++) { 940 bpools.bpool[i].bpid = ordered_array[i]; 941 bpools.bpool[i].size = sizes_array[ordered_array[i]]; 942 } 943 944 /* save pools parameters for later use */ 945 port->rx_pools_params.num_of_pools = ext_buf_pools->num_of_pools_used; 946 port->rx_pools_params.largest_buf_size = 947 sizes_array[ordered_array[ext_buf_pools->num_of_pools_used - 1]]; 948 949 /* FMBM_RMPD reg. - pool depletion */ 950 if (buf_pool_depletion->pools_grp_mode_enable) { 951 bpools.grp_bp_depleted_num = buf_pool_depletion->num_of_pools; 952 for (i = 0; i < port->bm_max_num_of_pools; i++) { 953 if (buf_pool_depletion->pools_to_consider[i]) { 954 for (j = 0; j < ext_buf_pools-> 955 num_of_pools_used; j++) { 956 if (i == ordered_array[j]) { 957 bpools.bpool[j]. 958 grp_bp_depleted = true; 959 break; 960 } 961 } 962 } 963 } 964 } 965 966 if (buf_pool_depletion->single_pool_mode_enable) { 967 for (i = 0; i < port->bm_max_num_of_pools; i++) { 968 if (buf_pool_depletion-> 969 pools_to_consider_for_single_mode[i]) { 970 for (j = 0; j < ext_buf_pools-> 971 num_of_pools_used; j++) { 972 if (i == ordered_array[j]) { 973 bpools.bpool[j]. 974 single_bp_depleted = true; 975 break; 976 } 977 } 978 } 979 } 980 } 981 982 err = set_bpools(port, &bpools); 983 if (err != 0) { 984 dev_err(port->dev, "%s: set_bpools() failed\n", __func__); 985 return -EINVAL; 986 } 987 988 return 0; 989 } 990 991 static int init_low_level_driver(struct fman_port *port) 992 { 993 struct fman_port_cfg *cfg = port->cfg; 994 u32 tmp_val; 995 996 switch (port->port_type) { 997 case FMAN_PORT_TYPE_RX: 998 cfg->err_mask = (RX_ERRS_TO_ENQ & ~cfg->discard_mask); 999 break; 1000 default: 1001 break; 1002 } 1003 1004 tmp_val = (u32)((port->internal_buf_offset % OFFSET_UNITS) ? 1005 (port->internal_buf_offset / OFFSET_UNITS + 1) : 1006 (port->internal_buf_offset / OFFSET_UNITS)); 1007 port->internal_buf_offset = (u8)(tmp_val * OFFSET_UNITS); 1008 port->cfg->int_buf_start_margin = port->internal_buf_offset; 1009 1010 if (init(port) != 0) { 1011 dev_err(port->dev, "%s: fman port initialization failed\n", 1012 __func__); 1013 return -ENODEV; 1014 } 1015 1016 /* The code bellow is a trick so the FM will not release the buffer 1017 * to BM nor will try to enqueue the frame to QM 1018 */ 1019 if (port->port_type == FMAN_PORT_TYPE_TX) { 1020 if (!cfg->dflt_fqid && cfg->dont_release_buf) { 1021 /* override fmbm_tcfqid 0 with a false non-0 value. 1022 * This will force FM to act according to tfene. 1023 * Otherwise, if fmbm_tcfqid is 0 the FM will release 1024 * buffers to BM regardless of fmbm_tfene 1025 */ 1026 iowrite32be(0xFFFFFF, &port->bmi_regs->tx.fmbm_tcfqid); 1027 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE, 1028 &port->bmi_regs->tx.fmbm_tfene); 1029 } 1030 } 1031 1032 return 0; 1033 } 1034 1035 static int fill_soc_specific_params(struct fman_port *port) 1036 { 1037 u32 bmi_max_fifo_size; 1038 1039 bmi_max_fifo_size = fman_get_bmi_max_fifo_size(port->fm); 1040 port->max_port_fifo_size = MAX_PORT_FIFO_SIZE(bmi_max_fifo_size); 1041 port->bm_max_num_of_pools = 64; 1042 1043 /* P4080 - Major 2 1044 * P2041/P3041/P5020/P5040 - Major 3 1045 * Tx/Bx - Major 6 1046 */ 1047 switch (port->rev_info.major) { 1048 case 2: 1049 case 3: 1050 port->max_num_of_ext_pools = 4; 1051 port->max_num_of_sub_portals = 12; 1052 break; 1053 1054 case 6: 1055 port->max_num_of_ext_pools = 8; 1056 port->max_num_of_sub_portals = 16; 1057 break; 1058 1059 default: 1060 dev_err(port->dev, "%s: Unsupported FMan version\n", __func__); 1061 return -EINVAL; 1062 } 1063 1064 return 0; 1065 } 1066 1067 static int get_dflt_fifo_deq_pipeline_depth(u8 major, enum fman_port_type type, 1068 u16 speed) 1069 { 1070 switch (type) { 1071 case FMAN_PORT_TYPE_RX: 1072 case FMAN_PORT_TYPE_TX: 1073 switch (speed) { 1074 case 10000: 1075 return 4; 1076 case 1000: 1077 if (major >= 6) 1078 return 2; 1079 else 1080 return 1; 1081 default: 1082 return 0; 1083 } 1084 default: 1085 return 0; 1086 } 1087 } 1088 1089 static int get_dflt_num_of_tasks(u8 major, enum fman_port_type type, 1090 u16 speed) 1091 { 1092 switch (type) { 1093 case FMAN_PORT_TYPE_RX: 1094 case FMAN_PORT_TYPE_TX: 1095 switch (speed) { 1096 case 10000: 1097 return 16; 1098 case 1000: 1099 if (major >= 6) 1100 return 4; 1101 else 1102 return 3; 1103 default: 1104 return 0; 1105 } 1106 default: 1107 return 0; 1108 } 1109 } 1110 1111 static int get_dflt_extra_num_of_tasks(u8 major, enum fman_port_type type, 1112 u16 speed) 1113 { 1114 switch (type) { 1115 case FMAN_PORT_TYPE_RX: 1116 /* FMan V3 */ 1117 if (major >= 6) 1118 return 0; 1119 1120 /* FMan V2 */ 1121 if (speed == 10000) 1122 return 8; 1123 else 1124 return 2; 1125 case FMAN_PORT_TYPE_TX: 1126 default: 1127 return 0; 1128 } 1129 } 1130 1131 static int get_dflt_num_of_open_dmas(u8 major, enum fman_port_type type, 1132 u16 speed) 1133 { 1134 int val; 1135 1136 if (major >= 6) { 1137 switch (type) { 1138 case FMAN_PORT_TYPE_TX: 1139 if (speed == 10000) 1140 val = 12; 1141 else 1142 val = 3; 1143 break; 1144 case FMAN_PORT_TYPE_RX: 1145 if (speed == 10000) 1146 val = 8; 1147 else 1148 val = 2; 1149 break; 1150 default: 1151 return 0; 1152 } 1153 } else { 1154 switch (type) { 1155 case FMAN_PORT_TYPE_TX: 1156 case FMAN_PORT_TYPE_RX: 1157 if (speed == 10000) 1158 val = 8; 1159 else 1160 val = 1; 1161 break; 1162 default: 1163 val = 0; 1164 } 1165 } 1166 1167 return val; 1168 } 1169 1170 static int get_dflt_extra_num_of_open_dmas(u8 major, enum fman_port_type type, 1171 u16 speed) 1172 { 1173 /* FMan V3 */ 1174 if (major >= 6) 1175 return 0; 1176 1177 /* FMan V2 */ 1178 switch (type) { 1179 case FMAN_PORT_TYPE_RX: 1180 case FMAN_PORT_TYPE_TX: 1181 if (speed == 10000) 1182 return 8; 1183 else 1184 return 1; 1185 default: 1186 return 0; 1187 } 1188 } 1189 1190 static int get_dflt_num_of_fifo_bufs(u8 major, enum fman_port_type type, 1191 u16 speed) 1192 { 1193 int val; 1194 1195 if (major >= 6) { 1196 switch (type) { 1197 case FMAN_PORT_TYPE_TX: 1198 if (speed == 10000) 1199 val = 64; 1200 else 1201 val = 50; 1202 break; 1203 case FMAN_PORT_TYPE_RX: 1204 if (speed == 10000) 1205 val = 96; 1206 else 1207 val = 50; 1208 break; 1209 default: 1210 val = 0; 1211 } 1212 } else { 1213 switch (type) { 1214 case FMAN_PORT_TYPE_TX: 1215 if (speed == 10000) 1216 val = 48; 1217 else 1218 val = 44; 1219 break; 1220 case FMAN_PORT_TYPE_RX: 1221 if (speed == 10000) 1222 val = 48; 1223 else 1224 val = 45; 1225 break; 1226 default: 1227 val = 0; 1228 } 1229 } 1230 1231 return val; 1232 } 1233 1234 static void set_dflt_cfg(struct fman_port *port, 1235 struct fman_port_params *port_params) 1236 { 1237 struct fman_port_cfg *cfg = port->cfg; 1238 1239 cfg->dma_swap_data = FMAN_PORT_DMA_NO_SWAP; 1240 cfg->color = FMAN_PORT_COLOR_GREEN; 1241 cfg->rx_cut_end_bytes = DFLT_PORT_CUT_BYTES_FROM_END; 1242 cfg->rx_pri_elevation = BMI_PRIORITY_ELEVATION_LEVEL; 1243 cfg->rx_fifo_thr = BMI_FIFO_THRESHOLD; 1244 cfg->tx_fifo_low_comf_level = (5 * 1024); 1245 cfg->deq_type = FMAN_PORT_DEQ_BY_PRI; 1246 cfg->deq_prefetch_option = FMAN_PORT_DEQ_FULL_PREFETCH; 1247 cfg->tx_fifo_deq_pipeline_depth = 1248 BMI_DEQUEUE_PIPELINE_DEPTH(port->port_type, port->port_speed); 1249 cfg->deq_byte_cnt = QMI_BYTE_COUNT_LEVEL_CONTROL(port->port_type); 1250 1251 cfg->rx_pri_elevation = 1252 DFLT_PORT_RX_FIFO_PRI_ELEVATION_LEV(port->max_port_fifo_size); 1253 port->cfg->rx_fifo_thr = 1254 DFLT_PORT_RX_FIFO_THRESHOLD(port->rev_info.major, 1255 port->max_port_fifo_size); 1256 1257 if ((port->rev_info.major == 6) && 1258 ((port->rev_info.minor == 0) || (port->rev_info.minor == 3))) 1259 cfg->errata_A006320 = true; 1260 1261 /* Excessive Threshold register - exists for pre-FMv3 chips only */ 1262 if (port->rev_info.major < 6) 1263 cfg->excessive_threshold_register = true; 1264 else 1265 cfg->fmbm_tfne_has_features = true; 1266 1267 cfg->buffer_prefix_content.data_align = 1268 DFLT_PORT_BUFFER_PREFIX_CONTEXT_DATA_ALIGN; 1269 } 1270 1271 static void set_rx_dflt_cfg(struct fman_port *port, 1272 struct fman_port_params *port_params) 1273 { 1274 port->cfg->discard_mask = DFLT_PORT_ERRORS_TO_DISCARD; 1275 1276 memcpy(&port->cfg->ext_buf_pools, 1277 &port_params->specific_params.rx_params.ext_buf_pools, 1278 sizeof(struct fman_ext_pools)); 1279 port->cfg->err_fqid = 1280 port_params->specific_params.rx_params.err_fqid; 1281 port->cfg->dflt_fqid = 1282 port_params->specific_params.rx_params.dflt_fqid; 1283 port->cfg->pcd_base_fqid = 1284 port_params->specific_params.rx_params.pcd_base_fqid; 1285 port->cfg->pcd_fqs_count = 1286 port_params->specific_params.rx_params.pcd_fqs_count; 1287 } 1288 1289 static void set_tx_dflt_cfg(struct fman_port *port, 1290 struct fman_port_params *port_params, 1291 struct fman_port_dts_params *dts_params) 1292 { 1293 port->cfg->tx_fifo_deq_pipeline_depth = 1294 get_dflt_fifo_deq_pipeline_depth(port->rev_info.major, 1295 port->port_type, 1296 port->port_speed); 1297 port->cfg->err_fqid = 1298 port_params->specific_params.non_rx_params.err_fqid; 1299 port->cfg->deq_sp = 1300 (u8)(dts_params->qman_channel_id & QMI_DEQ_CFG_SUBPORTAL_MASK); 1301 port->cfg->dflt_fqid = 1302 port_params->specific_params.non_rx_params.dflt_fqid; 1303 port->cfg->deq_high_priority = true; 1304 } 1305 1306 /** 1307 * fman_port_config 1308 * @port: Pointer to the port structure 1309 * @params: Pointer to data structure of parameters 1310 * 1311 * Creates a descriptor for the FM PORT module. 1312 * The routine returns a pointer to the FM PORT object. 1313 * This descriptor must be passed as first parameter to all other FM PORT 1314 * function calls. 1315 * No actual initialization or configuration of FM hardware is done by this 1316 * routine. 1317 * 1318 * Return: 0 on success; Error code otherwise. 1319 */ 1320 int fman_port_config(struct fman_port *port, struct fman_port_params *params) 1321 { 1322 void __iomem *base_addr = port->dts_params.base_addr; 1323 int err; 1324 1325 /* Allocate the FM driver's parameters structure */ 1326 port->cfg = kzalloc(sizeof(*port->cfg), GFP_KERNEL); 1327 if (!port->cfg) 1328 return -EINVAL; 1329 1330 /* Initialize FM port parameters which will be kept by the driver */ 1331 port->port_type = port->dts_params.type; 1332 port->port_speed = port->dts_params.speed; 1333 port->port_id = port->dts_params.id; 1334 port->fm = port->dts_params.fman; 1335 port->ext_pools_num = (u8)8; 1336 1337 /* get FM revision */ 1338 fman_get_revision(port->fm, &port->rev_info); 1339 1340 err = fill_soc_specific_params(port); 1341 if (err) 1342 goto err_port_cfg; 1343 1344 switch (port->port_type) { 1345 case FMAN_PORT_TYPE_RX: 1346 set_rx_dflt_cfg(port, params); 1347 fallthrough; 1348 case FMAN_PORT_TYPE_TX: 1349 set_tx_dflt_cfg(port, params, &port->dts_params); 1350 fallthrough; 1351 default: 1352 set_dflt_cfg(port, params); 1353 } 1354 1355 /* Continue with other parameters */ 1356 /* set memory map pointers */ 1357 port->bmi_regs = base_addr + BMI_PORT_REGS_OFFSET; 1358 port->qmi_regs = base_addr + QMI_PORT_REGS_OFFSET; 1359 port->hwp_regs = base_addr + HWP_PORT_REGS_OFFSET; 1360 1361 port->max_frame_length = DFLT_PORT_MAX_FRAME_LENGTH; 1362 /* resource distribution. */ 1363 1364 port->fifo_bufs.num = 1365 get_dflt_num_of_fifo_bufs(port->rev_info.major, port->port_type, 1366 port->port_speed) * FMAN_BMI_FIFO_UNITS; 1367 port->fifo_bufs.extra = 1368 DFLT_PORT_EXTRA_NUM_OF_FIFO_BUFS * FMAN_BMI_FIFO_UNITS; 1369 1370 port->open_dmas.num = 1371 get_dflt_num_of_open_dmas(port->rev_info.major, 1372 port->port_type, port->port_speed); 1373 port->open_dmas.extra = 1374 get_dflt_extra_num_of_open_dmas(port->rev_info.major, 1375 port->port_type, port->port_speed); 1376 port->tasks.num = 1377 get_dflt_num_of_tasks(port->rev_info.major, 1378 port->port_type, port->port_speed); 1379 port->tasks.extra = 1380 get_dflt_extra_num_of_tasks(port->rev_info.major, 1381 port->port_type, port->port_speed); 1382 1383 /* FM_HEAVY_TRAFFIC_SEQUENCER_HANG_ERRATA_FMAN_A006981 errata 1384 * workaround 1385 */ 1386 if ((port->rev_info.major == 6) && (port->rev_info.minor == 0) && 1387 (((port->port_type == FMAN_PORT_TYPE_TX) && 1388 (port->port_speed == 1000)))) { 1389 port->open_dmas.num = 16; 1390 port->open_dmas.extra = 0; 1391 } 1392 1393 if (port->rev_info.major >= 6 && 1394 port->port_type == FMAN_PORT_TYPE_TX && 1395 port->port_speed == 1000) { 1396 /* FM_WRONG_RESET_VALUES_ERRATA_FMAN_A005127 Errata 1397 * workaround 1398 */ 1399 u32 reg; 1400 1401 reg = 0x00001013; 1402 iowrite32be(reg, &port->bmi_regs->tx.fmbm_tfp); 1403 } 1404 1405 return 0; 1406 1407 err_port_cfg: 1408 kfree(port->cfg); 1409 return -EINVAL; 1410 } 1411 EXPORT_SYMBOL(fman_port_config); 1412 1413 /** 1414 * fman_port_use_kg_hash 1415 * port: A pointer to a FM Port module. 1416 * Sets the HW KeyGen or the BMI as HW Parser next engine, enabling 1417 * or bypassing the KeyGen hashing of Rx traffic 1418 */ 1419 void fman_port_use_kg_hash(struct fman_port *port, bool enable) 1420 { 1421 if (enable) 1422 /* After the Parser frames go to KeyGen */ 1423 iowrite32be(NIA_ENG_HWK, &port->bmi_regs->rx.fmbm_rfpne); 1424 else 1425 /* After the Parser frames go to BMI */ 1426 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME, 1427 &port->bmi_regs->rx.fmbm_rfpne); 1428 } 1429 EXPORT_SYMBOL(fman_port_use_kg_hash); 1430 1431 /** 1432 * fman_port_init 1433 * port: A pointer to a FM Port module. 1434 * Initializes the FM PORT module by defining the software structure and 1435 * configuring the hardware registers. 1436 * 1437 * Return: 0 on success; Error code otherwise. 1438 */ 1439 int fman_port_init(struct fman_port *port) 1440 { 1441 struct fman_port_init_params params; 1442 struct fman_keygen *keygen; 1443 struct fman_port_cfg *cfg; 1444 int err; 1445 1446 if (is_init_done(port->cfg)) 1447 return -EINVAL; 1448 1449 err = fman_sp_build_buffer_struct(&port->cfg->int_context, 1450 &port->cfg->buffer_prefix_content, 1451 &port->cfg->buf_margins, 1452 &port->buffer_offsets, 1453 &port->internal_buf_offset); 1454 if (err) 1455 return err; 1456 1457 cfg = port->cfg; 1458 1459 if (port->port_type == FMAN_PORT_TYPE_RX) { 1460 /* Call the external Buffer routine which also checks fifo 1461 * size and updates it if necessary 1462 */ 1463 /* define external buffer pools and pool depletion */ 1464 err = set_ext_buffer_pools(port); 1465 if (err) 1466 return err; 1467 /* check if the largest external buffer pool is large enough */ 1468 if (cfg->buf_margins.start_margins + MIN_EXT_BUF_SIZE + 1469 cfg->buf_margins.end_margins > 1470 port->rx_pools_params.largest_buf_size) { 1471 dev_err(port->dev, "%s: buf_margins.start_margins (%d) + minimum buf size (64) + buf_margins.end_margins (%d) is larger than maximum external buffer size (%d)\n", 1472 __func__, cfg->buf_margins.start_margins, 1473 cfg->buf_margins.end_margins, 1474 port->rx_pools_params.largest_buf_size); 1475 return -EINVAL; 1476 } 1477 } 1478 1479 /* Call FM module routine for communicating parameters */ 1480 memset(¶ms, 0, sizeof(params)); 1481 params.port_id = port->port_id; 1482 params.port_type = port->port_type; 1483 params.port_speed = port->port_speed; 1484 params.num_of_tasks = (u8)port->tasks.num; 1485 params.num_of_extra_tasks = (u8)port->tasks.extra; 1486 params.num_of_open_dmas = (u8)port->open_dmas.num; 1487 params.num_of_extra_open_dmas = (u8)port->open_dmas.extra; 1488 1489 if (port->fifo_bufs.num) { 1490 err = verify_size_of_fifo(port); 1491 if (err) 1492 return err; 1493 } 1494 params.size_of_fifo = port->fifo_bufs.num; 1495 params.extra_size_of_fifo = port->fifo_bufs.extra; 1496 params.deq_pipeline_depth = port->cfg->tx_fifo_deq_pipeline_depth; 1497 params.max_frame_length = port->max_frame_length; 1498 1499 err = fman_set_port_params(port->fm, ¶ms); 1500 if (err) 1501 return err; 1502 1503 err = init_low_level_driver(port); 1504 if (err) 1505 return err; 1506 1507 if (port->cfg->pcd_fqs_count) { 1508 keygen = port->dts_params.fman->keygen; 1509 err = keygen_port_hashing_init(keygen, port->port_id, 1510 port->cfg->pcd_base_fqid, 1511 port->cfg->pcd_fqs_count); 1512 if (err) 1513 return err; 1514 1515 fman_port_use_kg_hash(port, true); 1516 } 1517 1518 kfree(port->cfg); 1519 port->cfg = NULL; 1520 1521 return 0; 1522 } 1523 EXPORT_SYMBOL(fman_port_init); 1524 1525 /** 1526 * fman_port_cfg_buf_prefix_content 1527 * @port A pointer to a FM Port module. 1528 * @buffer_prefix_content A structure of parameters describing 1529 * the structure of the buffer. 1530 * Out parameter: 1531 * Start margin - offset of data from 1532 * start of external buffer. 1533 * Defines the structure, size and content of the application buffer. 1534 * The prefix, in Tx ports, if 'pass_prs_result', the application should set 1535 * a value to their offsets in the prefix of the FM will save the first 1536 * 'priv_data_size', than, depending on 'pass_prs_result' and 1537 * 'pass_time_stamp', copy parse result and timeStamp, and the packet itself 1538 * (in this order), to the application buffer, and to offset. 1539 * Calling this routine changes the buffer margins definitions in the internal 1540 * driver data base from its default configuration: 1541 * Data size: [DEFAULT_PORT_BUFFER_PREFIX_CONTENT_PRIV_DATA_SIZE] 1542 * Pass Parser result: [DEFAULT_PORT_BUFFER_PREFIX_CONTENT_PASS_PRS_RESULT]. 1543 * Pass timestamp: [DEFAULT_PORT_BUFFER_PREFIX_CONTENT_PASS_TIME_STAMP]. 1544 * May be used for all ports 1545 * 1546 * Allowed only following fman_port_config() and before fman_port_init(). 1547 * 1548 * Return: 0 on success; Error code otherwise. 1549 */ 1550 int fman_port_cfg_buf_prefix_content(struct fman_port *port, 1551 struct fman_buffer_prefix_content * 1552 buffer_prefix_content) 1553 { 1554 if (is_init_done(port->cfg)) 1555 return -EINVAL; 1556 1557 memcpy(&port->cfg->buffer_prefix_content, 1558 buffer_prefix_content, 1559 sizeof(struct fman_buffer_prefix_content)); 1560 /* if data_align was not initialized by user, 1561 * we return to driver's default 1562 */ 1563 if (!port->cfg->buffer_prefix_content.data_align) 1564 port->cfg->buffer_prefix_content.data_align = 1565 DFLT_PORT_BUFFER_PREFIX_CONTEXT_DATA_ALIGN; 1566 1567 return 0; 1568 } 1569 EXPORT_SYMBOL(fman_port_cfg_buf_prefix_content); 1570 1571 /** 1572 * fman_port_disable 1573 * port: A pointer to a FM Port module. 1574 * 1575 * Gracefully disable an FM port. The port will not start new tasks after all 1576 * tasks associated with the port are terminated. 1577 * 1578 * This is a blocking routine, it returns after port is gracefully stopped, 1579 * i.e. the port will not except new frames, but it will finish all frames 1580 * or tasks which were already began. 1581 * Allowed only following fman_port_init(). 1582 * 1583 * Return: 0 on success; Error code otherwise. 1584 */ 1585 int fman_port_disable(struct fman_port *port) 1586 { 1587 u32 __iomem *bmi_cfg_reg, *bmi_status_reg; 1588 u32 tmp; 1589 bool rx_port, failure = false; 1590 int count; 1591 1592 if (!is_init_done(port->cfg)) 1593 return -EINVAL; 1594 1595 switch (port->port_type) { 1596 case FMAN_PORT_TYPE_RX: 1597 bmi_cfg_reg = &port->bmi_regs->rx.fmbm_rcfg; 1598 bmi_status_reg = &port->bmi_regs->rx.fmbm_rst; 1599 rx_port = true; 1600 break; 1601 case FMAN_PORT_TYPE_TX: 1602 bmi_cfg_reg = &port->bmi_regs->tx.fmbm_tcfg; 1603 bmi_status_reg = &port->bmi_regs->tx.fmbm_tst; 1604 rx_port = false; 1605 break; 1606 default: 1607 return -EINVAL; 1608 } 1609 1610 /* Disable QMI */ 1611 if (!rx_port) { 1612 tmp = ioread32be(&port->qmi_regs->fmqm_pnc) & ~QMI_PORT_CFG_EN; 1613 iowrite32be(tmp, &port->qmi_regs->fmqm_pnc); 1614 1615 /* Wait for QMI to finish FD handling */ 1616 count = 100; 1617 do { 1618 udelay(10); 1619 tmp = ioread32be(&port->qmi_regs->fmqm_pns); 1620 } while ((tmp & QMI_PORT_STATUS_DEQ_FD_BSY) && --count); 1621 1622 if (count == 0) { 1623 /* Timeout */ 1624 failure = true; 1625 } 1626 } 1627 1628 /* Disable BMI */ 1629 tmp = ioread32be(bmi_cfg_reg) & ~BMI_PORT_CFG_EN; 1630 iowrite32be(tmp, bmi_cfg_reg); 1631 1632 /* Wait for graceful stop end */ 1633 count = 500; 1634 do { 1635 udelay(10); 1636 tmp = ioread32be(bmi_status_reg); 1637 } while ((tmp & BMI_PORT_STATUS_BSY) && --count); 1638 1639 if (count == 0) { 1640 /* Timeout */ 1641 failure = true; 1642 } 1643 1644 if (failure) 1645 dev_dbg(port->dev, "%s: FMan Port[%d]: BMI or QMI is Busy. Port forced down\n", 1646 __func__, port->port_id); 1647 1648 return 0; 1649 } 1650 EXPORT_SYMBOL(fman_port_disable); 1651 1652 /** 1653 * fman_port_enable 1654 * port: A pointer to a FM Port module. 1655 * 1656 * A runtime routine provided to allow disable/enable of port. 1657 * 1658 * Allowed only following fman_port_init(). 1659 * 1660 * Return: 0 on success; Error code otherwise. 1661 */ 1662 int fman_port_enable(struct fman_port *port) 1663 { 1664 u32 __iomem *bmi_cfg_reg; 1665 u32 tmp; 1666 bool rx_port; 1667 1668 if (!is_init_done(port->cfg)) 1669 return -EINVAL; 1670 1671 switch (port->port_type) { 1672 case FMAN_PORT_TYPE_RX: 1673 bmi_cfg_reg = &port->bmi_regs->rx.fmbm_rcfg; 1674 rx_port = true; 1675 break; 1676 case FMAN_PORT_TYPE_TX: 1677 bmi_cfg_reg = &port->bmi_regs->tx.fmbm_tcfg; 1678 rx_port = false; 1679 break; 1680 default: 1681 return -EINVAL; 1682 } 1683 1684 /* Enable QMI */ 1685 if (!rx_port) { 1686 tmp = ioread32be(&port->qmi_regs->fmqm_pnc) | QMI_PORT_CFG_EN; 1687 iowrite32be(tmp, &port->qmi_regs->fmqm_pnc); 1688 } 1689 1690 /* Enable BMI */ 1691 tmp = ioread32be(bmi_cfg_reg) | BMI_PORT_CFG_EN; 1692 iowrite32be(tmp, bmi_cfg_reg); 1693 1694 return 0; 1695 } 1696 EXPORT_SYMBOL(fman_port_enable); 1697 1698 /** 1699 * fman_port_bind 1700 * dev: FMan Port OF device pointer 1701 * 1702 * Bind to a specific FMan Port. 1703 * 1704 * Allowed only after the port was created. 1705 * 1706 * Return: A pointer to the FMan port device. 1707 */ 1708 struct fman_port *fman_port_bind(struct device *dev) 1709 { 1710 return (struct fman_port *)(dev_get_drvdata(get_device(dev))); 1711 } 1712 EXPORT_SYMBOL(fman_port_bind); 1713 1714 /** 1715 * fman_port_get_qman_channel_id 1716 * port: Pointer to the FMan port devuce 1717 * 1718 * Get the QMan channel ID for the specific port 1719 * 1720 * Return: QMan channel ID 1721 */ 1722 u32 fman_port_get_qman_channel_id(struct fman_port *port) 1723 { 1724 return port->dts_params.qman_channel_id; 1725 } 1726 EXPORT_SYMBOL(fman_port_get_qman_channel_id); 1727 1728 /** 1729 * fman_port_get_device 1730 * port: Pointer to the FMan port device 1731 * 1732 * Get the 'struct device' associated to the specified FMan port device 1733 * 1734 * Return: pointer to associated 'struct device' 1735 */ 1736 struct device *fman_port_get_device(struct fman_port *port) 1737 { 1738 return port->dev; 1739 } 1740 EXPORT_SYMBOL(fman_port_get_device); 1741 1742 int fman_port_get_hash_result_offset(struct fman_port *port, u32 *offset) 1743 { 1744 if (port->buffer_offsets.hash_result_offset == ILLEGAL_BASE) 1745 return -EINVAL; 1746 1747 *offset = port->buffer_offsets.hash_result_offset; 1748 1749 return 0; 1750 } 1751 EXPORT_SYMBOL(fman_port_get_hash_result_offset); 1752 1753 int fman_port_get_tstamp(struct fman_port *port, const void *data, u64 *tstamp) 1754 { 1755 if (port->buffer_offsets.time_stamp_offset == ILLEGAL_BASE) 1756 return -EINVAL; 1757 1758 *tstamp = be64_to_cpu(*(__be64 *)(data + 1759 port->buffer_offsets.time_stamp_offset)); 1760 1761 return 0; 1762 } 1763 EXPORT_SYMBOL(fman_port_get_tstamp); 1764 1765 static int fman_port_probe(struct platform_device *of_dev) 1766 { 1767 struct fman_port *port; 1768 struct fman *fman; 1769 struct device_node *fm_node, *port_node; 1770 struct platform_device *fm_pdev; 1771 struct resource res; 1772 struct resource *dev_res; 1773 u32 val; 1774 int err = 0, lenp; 1775 enum fman_port_type port_type; 1776 u16 port_speed; 1777 u8 port_id; 1778 1779 port = kzalloc(sizeof(*port), GFP_KERNEL); 1780 if (!port) 1781 return -ENOMEM; 1782 1783 port->dev = &of_dev->dev; 1784 1785 port_node = of_node_get(of_dev->dev.of_node); 1786 1787 /* Get the FM node */ 1788 fm_node = of_get_parent(port_node); 1789 if (!fm_node) { 1790 dev_err(port->dev, "%s: of_get_parent() failed\n", __func__); 1791 err = -ENODEV; 1792 goto return_err; 1793 } 1794 1795 fm_pdev = of_find_device_by_node(fm_node); 1796 of_node_put(fm_node); 1797 if (!fm_pdev) { 1798 err = -EINVAL; 1799 goto return_err; 1800 } 1801 1802 fman = dev_get_drvdata(&fm_pdev->dev); 1803 if (!fman) { 1804 err = -EINVAL; 1805 goto return_err; 1806 } 1807 1808 err = of_property_read_u32(port_node, "cell-index", &val); 1809 if (err) { 1810 dev_err(port->dev, "%s: reading cell-index for %pOF failed\n", 1811 __func__, port_node); 1812 err = -EINVAL; 1813 goto return_err; 1814 } 1815 port_id = (u8)val; 1816 port->dts_params.id = port_id; 1817 1818 if (of_device_is_compatible(port_node, "fsl,fman-v3-port-tx")) { 1819 port_type = FMAN_PORT_TYPE_TX; 1820 port_speed = 1000; 1821 if (of_find_property(port_node, "fsl,fman-10g-port", &lenp)) 1822 port_speed = 10000; 1823 1824 } else if (of_device_is_compatible(port_node, "fsl,fman-v2-port-tx")) { 1825 if (port_id >= TX_10G_PORT_BASE) 1826 port_speed = 10000; 1827 else 1828 port_speed = 1000; 1829 port_type = FMAN_PORT_TYPE_TX; 1830 1831 } else if (of_device_is_compatible(port_node, "fsl,fman-v3-port-rx")) { 1832 port_type = FMAN_PORT_TYPE_RX; 1833 port_speed = 1000; 1834 if (of_find_property(port_node, "fsl,fman-10g-port", &lenp)) 1835 port_speed = 10000; 1836 1837 } else if (of_device_is_compatible(port_node, "fsl,fman-v2-port-rx")) { 1838 if (port_id >= RX_10G_PORT_BASE) 1839 port_speed = 10000; 1840 else 1841 port_speed = 1000; 1842 port_type = FMAN_PORT_TYPE_RX; 1843 1844 } else { 1845 dev_err(port->dev, "%s: Illegal port type\n", __func__); 1846 err = -EINVAL; 1847 goto return_err; 1848 } 1849 1850 port->dts_params.type = port_type; 1851 port->dts_params.speed = port_speed; 1852 1853 if (port_type == FMAN_PORT_TYPE_TX) { 1854 u32 qman_channel_id; 1855 1856 qman_channel_id = fman_get_qman_channel_id(fman, port_id); 1857 if (qman_channel_id == 0) { 1858 dev_err(port->dev, "%s: incorrect qman-channel-id\n", 1859 __func__); 1860 err = -EINVAL; 1861 goto return_err; 1862 } 1863 port->dts_params.qman_channel_id = qman_channel_id; 1864 } 1865 1866 err = of_address_to_resource(port_node, 0, &res); 1867 if (err < 0) { 1868 dev_err(port->dev, "%s: of_address_to_resource() failed\n", 1869 __func__); 1870 err = -ENOMEM; 1871 goto return_err; 1872 } 1873 1874 port->dts_params.fman = fman; 1875 1876 of_node_put(port_node); 1877 1878 dev_res = __devm_request_region(port->dev, &res, res.start, 1879 resource_size(&res), "fman-port"); 1880 if (!dev_res) { 1881 dev_err(port->dev, "%s: __devm_request_region() failed\n", 1882 __func__); 1883 err = -EINVAL; 1884 goto free_port; 1885 } 1886 1887 port->dts_params.base_addr = devm_ioremap(port->dev, res.start, 1888 resource_size(&res)); 1889 if (!port->dts_params.base_addr) 1890 dev_err(port->dev, "%s: devm_ioremap() failed\n", __func__); 1891 1892 dev_set_drvdata(&of_dev->dev, port); 1893 1894 return 0; 1895 1896 return_err: 1897 of_node_put(port_node); 1898 free_port: 1899 kfree(port); 1900 return err; 1901 } 1902 1903 static const struct of_device_id fman_port_match[] = { 1904 {.compatible = "fsl,fman-v3-port-rx"}, 1905 {.compatible = "fsl,fman-v2-port-rx"}, 1906 {.compatible = "fsl,fman-v3-port-tx"}, 1907 {.compatible = "fsl,fman-v2-port-tx"}, 1908 {} 1909 }; 1910 1911 MODULE_DEVICE_TABLE(of, fman_port_match); 1912 1913 static struct platform_driver fman_port_driver = { 1914 .driver = { 1915 .name = "fsl-fman-port", 1916 .of_match_table = fman_port_match, 1917 }, 1918 .probe = fman_port_probe, 1919 }; 1920 1921 static int __init fman_port_load(void) 1922 { 1923 int err; 1924 1925 pr_debug("FSL DPAA FMan driver\n"); 1926 1927 err = platform_driver_register(&fman_port_driver); 1928 if (err < 0) 1929 pr_err("Error, platform_driver_register() = %d\n", err); 1930 1931 return err; 1932 } 1933 module_init(fman_port_load); 1934 1935 static void __exit fman_port_unload(void) 1936 { 1937 platform_driver_unregister(&fman_port_driver); 1938 } 1939 module_exit(fman_port_unload); 1940 1941 MODULE_LICENSE("Dual BSD/GPL"); 1942 MODULE_DESCRIPTION("Freescale DPAA Frame Manager Port driver"); 1943