1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later 2 /* 3 * Copyright 2008 - 2015 Freescale Semiconductor Inc. 4 */ 5 6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 7 8 #include <linux/io.h> 9 #include <linux/slab.h> 10 #include <linux/module.h> 11 #include <linux/interrupt.h> 12 #include <linux/of_platform.h> 13 #include <linux/of_address.h> 14 #include <linux/delay.h> 15 #include <linux/libfdt_env.h> 16 17 #include "fman.h" 18 #include "fman_port.h" 19 #include "fman_sp.h" 20 #include "fman_keygen.h" 21 22 /* Queue ID */ 23 #define DFLT_FQ_ID 0x00FFFFFF 24 25 /* General defines */ 26 #define PORT_BMI_FIFO_UNITS 0x100 27 28 #define MAX_PORT_FIFO_SIZE(bmi_max_fifo_size) \ 29 min((u32)bmi_max_fifo_size, (u32)1024 * FMAN_BMI_FIFO_UNITS) 30 31 #define PORT_CG_MAP_NUM 8 32 #define PORT_PRS_RESULT_WORDS_NUM 8 33 #define PORT_IC_OFFSET_UNITS 0x10 34 35 #define MIN_EXT_BUF_SIZE 64 36 37 #define BMI_PORT_REGS_OFFSET 0 38 #define QMI_PORT_REGS_OFFSET 0x400 39 #define HWP_PORT_REGS_OFFSET 0x800 40 41 /* Default values */ 42 #define DFLT_PORT_BUFFER_PREFIX_CONTEXT_DATA_ALIGN \ 43 DFLT_FM_SP_BUFFER_PREFIX_CONTEXT_DATA_ALIGN 44 45 #define DFLT_PORT_CUT_BYTES_FROM_END 4 46 47 #define DFLT_PORT_ERRORS_TO_DISCARD FM_PORT_FRM_ERR_CLS_DISCARD 48 #define DFLT_PORT_MAX_FRAME_LENGTH 9600 49 50 #define DFLT_PORT_RX_FIFO_PRI_ELEVATION_LEV(bmi_max_fifo_size) \ 51 MAX_PORT_FIFO_SIZE(bmi_max_fifo_size) 52 53 #define DFLT_PORT_RX_FIFO_THRESHOLD(major, bmi_max_fifo_size) \ 54 (major == 6 ? \ 55 MAX_PORT_FIFO_SIZE(bmi_max_fifo_size) : \ 56 (MAX_PORT_FIFO_SIZE(bmi_max_fifo_size) * 3 / 4)) \ 57 58 #define DFLT_PORT_EXTRA_NUM_OF_FIFO_BUFS 0 59 60 /* QMI defines */ 61 #define QMI_DEQ_CFG_SUBPORTAL_MASK 0x1f 62 63 #define QMI_PORT_CFG_EN 0x80000000 64 #define QMI_PORT_STATUS_DEQ_FD_BSY 0x20000000 65 66 #define QMI_DEQ_CFG_PRI 0x80000000 67 #define QMI_DEQ_CFG_TYPE1 0x10000000 68 #define QMI_DEQ_CFG_TYPE2 0x20000000 69 #define QMI_DEQ_CFG_TYPE3 0x30000000 70 #define QMI_DEQ_CFG_PREFETCH_PARTIAL 0x01000000 71 #define QMI_DEQ_CFG_PREFETCH_FULL 0x03000000 72 #define QMI_DEQ_CFG_SP_MASK 0xf 73 #define QMI_DEQ_CFG_SP_SHIFT 20 74 75 #define QMI_BYTE_COUNT_LEVEL_CONTROL(_type) \ 76 (_type == FMAN_PORT_TYPE_TX ? 0x1400 : 0x400) 77 78 /* BMI defins */ 79 #define BMI_EBD_EN 0x80000000 80 81 #define BMI_PORT_CFG_EN 0x80000000 82 83 #define BMI_PORT_STATUS_BSY 0x80000000 84 85 #define BMI_DMA_ATTR_SWP_SHIFT FMAN_SP_DMA_ATTR_SWP_SHIFT 86 #define BMI_DMA_ATTR_WRITE_OPTIMIZE FMAN_SP_DMA_ATTR_WRITE_OPTIMIZE 87 88 #define BMI_RX_FIFO_PRI_ELEVATION_SHIFT 16 89 #define BMI_RX_FIFO_THRESHOLD_ETHE 0x80000000 90 91 #define BMI_FRAME_END_CS_IGNORE_SHIFT 24 92 #define BMI_FRAME_END_CS_IGNORE_MASK 0x0000001f 93 94 #define BMI_RX_FRAME_END_CUT_SHIFT 16 95 #define BMI_RX_FRAME_END_CUT_MASK 0x0000001f 96 97 #define BMI_IC_TO_EXT_SHIFT FMAN_SP_IC_TO_EXT_SHIFT 98 #define BMI_IC_TO_EXT_MASK 0x0000001f 99 #define BMI_IC_FROM_INT_SHIFT FMAN_SP_IC_FROM_INT_SHIFT 100 #define BMI_IC_FROM_INT_MASK 0x0000000f 101 #define BMI_IC_SIZE_MASK 0x0000001f 102 103 #define BMI_INT_BUF_MARG_SHIFT 28 104 #define BMI_INT_BUF_MARG_MASK 0x0000000f 105 #define BMI_EXT_BUF_MARG_START_SHIFT FMAN_SP_EXT_BUF_MARG_START_SHIFT 106 #define BMI_EXT_BUF_MARG_START_MASK 0x000001ff 107 #define BMI_EXT_BUF_MARG_END_MASK 0x000001ff 108 109 #define BMI_CMD_MR_LEAC 0x00200000 110 #define BMI_CMD_MR_SLEAC 0x00100000 111 #define BMI_CMD_MR_MA 0x00080000 112 #define BMI_CMD_MR_DEAS 0x00040000 113 #define BMI_CMD_RX_MR_DEF (BMI_CMD_MR_LEAC | \ 114 BMI_CMD_MR_SLEAC | \ 115 BMI_CMD_MR_MA | \ 116 BMI_CMD_MR_DEAS) 117 #define BMI_CMD_TX_MR_DEF 0 118 119 #define BMI_CMD_ATTR_ORDER 0x80000000 120 #define BMI_CMD_ATTR_SYNC 0x02000000 121 #define BMI_CMD_ATTR_COLOR_SHIFT 26 122 123 #define BMI_FIFO_PIPELINE_DEPTH_SHIFT 12 124 #define BMI_FIFO_PIPELINE_DEPTH_MASK 0x0000000f 125 #define BMI_NEXT_ENG_FD_BITS_SHIFT 24 126 127 #define BMI_EXT_BUF_POOL_VALID FMAN_SP_EXT_BUF_POOL_VALID 128 #define BMI_EXT_BUF_POOL_EN_COUNTER FMAN_SP_EXT_BUF_POOL_EN_COUNTER 129 #define BMI_EXT_BUF_POOL_BACKUP FMAN_SP_EXT_BUF_POOL_BACKUP 130 #define BMI_EXT_BUF_POOL_ID_SHIFT 16 131 #define BMI_EXT_BUF_POOL_ID_MASK 0x003F0000 132 #define BMI_POOL_DEP_NUM_OF_POOLS_SHIFT 16 133 134 #define BMI_TX_FIFO_MIN_FILL_SHIFT 16 135 136 #define BMI_PRIORITY_ELEVATION_LEVEL ((0x3FF + 1) * PORT_BMI_FIFO_UNITS) 137 #define BMI_FIFO_THRESHOLD ((0x3FF + 1) * PORT_BMI_FIFO_UNITS) 138 139 #define BMI_DEQUEUE_PIPELINE_DEPTH(_type, _speed) \ 140 ((_type == FMAN_PORT_TYPE_TX && _speed == 10000) ? 4 : 1) 141 142 #define RX_ERRS_TO_ENQ \ 143 (FM_PORT_FRM_ERR_DMA | \ 144 FM_PORT_FRM_ERR_PHYSICAL | \ 145 FM_PORT_FRM_ERR_SIZE | \ 146 FM_PORT_FRM_ERR_EXTRACTION | \ 147 FM_PORT_FRM_ERR_NO_SCHEME | \ 148 FM_PORT_FRM_ERR_PRS_TIMEOUT | \ 149 FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT | \ 150 FM_PORT_FRM_ERR_BLOCK_LIMIT_EXCEEDED | \ 151 FM_PORT_FRM_ERR_PRS_HDR_ERR | \ 152 FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW | \ 153 FM_PORT_FRM_ERR_IPRE) 154 155 /* NIA defines */ 156 #define NIA_ORDER_RESTOR 0x00800000 157 #define NIA_ENG_BMI 0x00500000 158 #define NIA_ENG_QMI_ENQ 0x00540000 159 #define NIA_ENG_QMI_DEQ 0x00580000 160 #define NIA_ENG_HWP 0x00440000 161 #define NIA_ENG_HWK 0x00480000 162 #define NIA_BMI_AC_ENQ_FRAME 0x00000002 163 #define NIA_BMI_AC_TX_RELEASE 0x000002C0 164 #define NIA_BMI_AC_RELEASE 0x000000C0 165 #define NIA_BMI_AC_TX 0x00000274 166 #define NIA_BMI_AC_FETCH_ALL_FRAME 0x0000020c 167 168 /* Port IDs */ 169 #define TX_10G_PORT_BASE 0x30 170 #define RX_10G_PORT_BASE 0x10 171 172 /* BMI Rx port register map */ 173 struct fman_port_rx_bmi_regs { 174 u32 fmbm_rcfg; /* Rx Configuration */ 175 u32 fmbm_rst; /* Rx Status */ 176 u32 fmbm_rda; /* Rx DMA attributes */ 177 u32 fmbm_rfp; /* Rx FIFO Parameters */ 178 u32 fmbm_rfed; /* Rx Frame End Data */ 179 u32 fmbm_ricp; /* Rx Internal Context Parameters */ 180 u32 fmbm_rim; /* Rx Internal Buffer Margins */ 181 u32 fmbm_rebm; /* Rx External Buffer Margins */ 182 u32 fmbm_rfne; /* Rx Frame Next Engine */ 183 u32 fmbm_rfca; /* Rx Frame Command Attributes. */ 184 u32 fmbm_rfpne; /* Rx Frame Parser Next Engine */ 185 u32 fmbm_rpso; /* Rx Parse Start Offset */ 186 u32 fmbm_rpp; /* Rx Policer Profile */ 187 u32 fmbm_rccb; /* Rx Coarse Classification Base */ 188 u32 fmbm_reth; /* Rx Excessive Threshold */ 189 u32 reserved003c[1]; /* (0x03C 0x03F) */ 190 u32 fmbm_rprai[PORT_PRS_RESULT_WORDS_NUM]; 191 /* Rx Parse Results Array Init */ 192 u32 fmbm_rfqid; /* Rx Frame Queue ID */ 193 u32 fmbm_refqid; /* Rx Error Frame Queue ID */ 194 u32 fmbm_rfsdm; /* Rx Frame Status Discard Mask */ 195 u32 fmbm_rfsem; /* Rx Frame Status Error Mask */ 196 u32 fmbm_rfene; /* Rx Frame Enqueue Next Engine */ 197 u32 reserved0074[0x2]; /* (0x074-0x07C) */ 198 u32 fmbm_rcmne; /* Rx Frame Continuous Mode Next Engine */ 199 u32 reserved0080[0x20]; /* (0x080 0x0FF) */ 200 u32 fmbm_ebmpi[FMAN_PORT_MAX_EXT_POOLS_NUM]; 201 /* Buffer Manager pool Information- */ 202 u32 fmbm_acnt[FMAN_PORT_MAX_EXT_POOLS_NUM]; /* Allocate Counter- */ 203 u32 reserved0130[8]; /* 0x130/0x140 - 0x15F reserved - */ 204 u32 fmbm_rcgm[PORT_CG_MAP_NUM]; /* Congestion Group Map */ 205 u32 fmbm_mpd; /* BM Pool Depletion */ 206 u32 reserved0184[0x1F]; /* (0x184 0x1FF) */ 207 u32 fmbm_rstc; /* Rx Statistics Counters */ 208 u32 fmbm_rfrc; /* Rx Frame Counter */ 209 u32 fmbm_rfbc; /* Rx Bad Frames Counter */ 210 u32 fmbm_rlfc; /* Rx Large Frames Counter */ 211 u32 fmbm_rffc; /* Rx Filter Frames Counter */ 212 u32 fmbm_rfdc; /* Rx Frame Discard Counter */ 213 u32 fmbm_rfldec; /* Rx Frames List DMA Error Counter */ 214 u32 fmbm_rodc; /* Rx Out of Buffers Discard nntr */ 215 u32 fmbm_rbdc; /* Rx Buffers Deallocate Counter */ 216 u32 fmbm_rpec; /* RX Prepare to enqueue Counte */ 217 u32 reserved0224[0x16]; /* (0x224 0x27F) */ 218 u32 fmbm_rpc; /* Rx Performance Counters */ 219 u32 fmbm_rpcp; /* Rx Performance Count Parameters */ 220 u32 fmbm_rccn; /* Rx Cycle Counter */ 221 u32 fmbm_rtuc; /* Rx Tasks Utilization Counter */ 222 u32 fmbm_rrquc; /* Rx Receive Queue Utilization cntr */ 223 u32 fmbm_rduc; /* Rx DMA Utilization Counter */ 224 u32 fmbm_rfuc; /* Rx FIFO Utilization Counter */ 225 u32 fmbm_rpac; /* Rx Pause Activation Counter */ 226 u32 reserved02a0[0x18]; /* (0x2A0 0x2FF) */ 227 u32 fmbm_rdcfg[0x3]; /* Rx Debug Configuration */ 228 u32 fmbm_rgpr; /* Rx General Purpose Register */ 229 u32 reserved0310[0x3a]; 230 }; 231 232 /* BMI Tx port register map */ 233 struct fman_port_tx_bmi_regs { 234 u32 fmbm_tcfg; /* Tx Configuration */ 235 u32 fmbm_tst; /* Tx Status */ 236 u32 fmbm_tda; /* Tx DMA attributes */ 237 u32 fmbm_tfp; /* Tx FIFO Parameters */ 238 u32 fmbm_tfed; /* Tx Frame End Data */ 239 u32 fmbm_ticp; /* Tx Internal Context Parameters */ 240 u32 fmbm_tfdne; /* Tx Frame Dequeue Next Engine. */ 241 u32 fmbm_tfca; /* Tx Frame Command attribute. */ 242 u32 fmbm_tcfqid; /* Tx Confirmation Frame Queue ID. */ 243 u32 fmbm_tefqid; /* Tx Frame Error Queue ID */ 244 u32 fmbm_tfene; /* Tx Frame Enqueue Next Engine */ 245 u32 fmbm_trlmts; /* Tx Rate Limiter Scale */ 246 u32 fmbm_trlmt; /* Tx Rate Limiter */ 247 u32 reserved0034[0x0e]; /* (0x034-0x6c) */ 248 u32 fmbm_tccb; /* Tx Coarse Classification base */ 249 u32 fmbm_tfne; /* Tx Frame Next Engine */ 250 u32 fmbm_tpfcm[0x02]; 251 /* Tx Priority based Flow Control (PFC) Mapping */ 252 u32 fmbm_tcmne; /* Tx Frame Continuous Mode Next Engine */ 253 u32 reserved0080[0x60]; /* (0x080-0x200) */ 254 u32 fmbm_tstc; /* Tx Statistics Counters */ 255 u32 fmbm_tfrc; /* Tx Frame Counter */ 256 u32 fmbm_tfdc; /* Tx Frames Discard Counter */ 257 u32 fmbm_tfledc; /* Tx Frame len error discard cntr */ 258 u32 fmbm_tfufdc; /* Tx Frame unsprt frmt discard cntr */ 259 u32 fmbm_tbdc; /* Tx Buffers Deallocate Counter */ 260 u32 reserved0218[0x1A]; /* (0x218-0x280) */ 261 u32 fmbm_tpc; /* Tx Performance Counters */ 262 u32 fmbm_tpcp; /* Tx Performance Count Parameters */ 263 u32 fmbm_tccn; /* Tx Cycle Counter */ 264 u32 fmbm_ttuc; /* Tx Tasks Utilization Counter */ 265 u32 fmbm_ttcquc; /* Tx Transmit conf Q util Counter */ 266 u32 fmbm_tduc; /* Tx DMA Utilization Counter */ 267 u32 fmbm_tfuc; /* Tx FIFO Utilization Counter */ 268 u32 reserved029c[16]; /* (0x29C-0x2FF) */ 269 u32 fmbm_tdcfg[0x3]; /* Tx Debug Configuration */ 270 u32 fmbm_tgpr; /* Tx General Purpose Register */ 271 u32 reserved0310[0x3a]; /* (0x310-0x3FF) */ 272 }; 273 274 /* BMI port register map */ 275 union fman_port_bmi_regs { 276 struct fman_port_rx_bmi_regs rx; 277 struct fman_port_tx_bmi_regs tx; 278 }; 279 280 /* QMI port register map */ 281 struct fman_port_qmi_regs { 282 u32 fmqm_pnc; /* PortID n Configuration Register */ 283 u32 fmqm_pns; /* PortID n Status Register */ 284 u32 fmqm_pnts; /* PortID n Task Status Register */ 285 u32 reserved00c[4]; /* 0xn00C - 0xn01B */ 286 u32 fmqm_pnen; /* PortID n Enqueue NIA Register */ 287 u32 fmqm_pnetfc; /* PortID n Enq Total Frame Counter */ 288 u32 reserved024[2]; /* 0xn024 - 0x02B */ 289 u32 fmqm_pndn; /* PortID n Dequeue NIA Register */ 290 u32 fmqm_pndc; /* PortID n Dequeue Config Register */ 291 u32 fmqm_pndtfc; /* PortID n Dequeue tot Frame cntr */ 292 u32 fmqm_pndfdc; /* PortID n Dequeue FQID Dflt Cntr */ 293 u32 fmqm_pndcc; /* PortID n Dequeue Confirm Counter */ 294 }; 295 296 #define HWP_HXS_COUNT 16 297 #define HWP_HXS_PHE_REPORT 0x00000800 298 #define HWP_HXS_PCAC_PSTAT 0x00000100 299 #define HWP_HXS_PCAC_PSTOP 0x00000001 300 #define HWP_HXS_TCP_OFFSET 0xA 301 #define HWP_HXS_UDP_OFFSET 0xB 302 #define HWP_HXS_SH_PAD_REM 0x80000000 303 304 struct fman_port_hwp_regs { 305 struct { 306 u32 ssa; /* Soft Sequence Attachment */ 307 u32 lcv; /* Line-up Enable Confirmation Mask */ 308 } pmda[HWP_HXS_COUNT]; /* Parse Memory Direct Access Registers */ 309 u32 reserved080[(0x3f8 - 0x080) / 4]; /* (0x080-0x3f7) */ 310 u32 fmpr_pcac; /* Configuration Access Control */ 311 }; 312 313 /* QMI dequeue prefetch modes */ 314 enum fman_port_deq_prefetch { 315 FMAN_PORT_DEQ_NO_PREFETCH, /* No prefetch mode */ 316 FMAN_PORT_DEQ_PART_PREFETCH, /* Partial prefetch mode */ 317 FMAN_PORT_DEQ_FULL_PREFETCH /* Full prefetch mode */ 318 }; 319 320 /* A structure for defining FM port resources */ 321 struct fman_port_rsrc { 322 u32 num; /* Committed required resource */ 323 u32 extra; /* Extra (not committed) required resource */ 324 }; 325 326 enum fman_port_dma_swap { 327 FMAN_PORT_DMA_NO_SWAP, /* No swap, transfer data as is */ 328 FMAN_PORT_DMA_SWAP_LE, 329 /* The transferred data should be swapped in PPC Little Endian mode */ 330 FMAN_PORT_DMA_SWAP_BE 331 /* The transferred data should be swapped in Big Endian mode */ 332 }; 333 334 /* Default port color */ 335 enum fman_port_color { 336 FMAN_PORT_COLOR_GREEN, /* Default port color is green */ 337 FMAN_PORT_COLOR_YELLOW, /* Default port color is yellow */ 338 FMAN_PORT_COLOR_RED, /* Default port color is red */ 339 FMAN_PORT_COLOR_OVERRIDE /* Ignore color */ 340 }; 341 342 /* QMI dequeue from the SP channel - types */ 343 enum fman_port_deq_type { 344 FMAN_PORT_DEQ_BY_PRI, 345 /* Priority precedence and Intra-Class scheduling */ 346 FMAN_PORT_DEQ_ACTIVE_FQ, 347 /* Active FQ precedence and Intra-Class scheduling */ 348 FMAN_PORT_DEQ_ACTIVE_FQ_NO_ICS 349 /* Active FQ precedence and override Intra-Class scheduling */ 350 }; 351 352 /* External buffer pools configuration */ 353 struct fman_port_bpools { 354 u8 count; /* Num of pools to set up */ 355 bool counters_enable; /* Enable allocate counters */ 356 u8 grp_bp_depleted_num; 357 /* Number of depleted pools - if reached the BMI indicates 358 * the MAC to send a pause frame 359 */ 360 struct { 361 u8 bpid; /* BM pool ID */ 362 u16 size; 363 /* Pool's size - must be in ascending order */ 364 bool is_backup; 365 /* If this is a backup pool */ 366 bool grp_bp_depleted; 367 /* Consider this buffer in multiple pools depletion criteria */ 368 bool single_bp_depleted; 369 /* Consider this buffer in single pool depletion criteria */ 370 } bpool[FMAN_PORT_MAX_EXT_POOLS_NUM]; 371 }; 372 373 struct fman_port_cfg { 374 u32 dflt_fqid; 375 u32 err_fqid; 376 u32 pcd_base_fqid; 377 u32 pcd_fqs_count; 378 u8 deq_sp; 379 bool deq_high_priority; 380 enum fman_port_deq_type deq_type; 381 enum fman_port_deq_prefetch deq_prefetch_option; 382 u16 deq_byte_cnt; 383 u8 cheksum_last_bytes_ignore; 384 u8 rx_cut_end_bytes; 385 struct fman_buf_pool_depletion buf_pool_depletion; 386 struct fman_ext_pools ext_buf_pools; 387 u32 tx_fifo_min_level; 388 u32 tx_fifo_low_comf_level; 389 u32 rx_pri_elevation; 390 u32 rx_fifo_thr; 391 struct fman_sp_buf_margins buf_margins; 392 u32 int_buf_start_margin; 393 struct fman_sp_int_context_data_copy int_context; 394 u32 discard_mask; 395 u32 err_mask; 396 struct fman_buffer_prefix_content buffer_prefix_content; 397 bool dont_release_buf; 398 399 u8 rx_fd_bits; 400 u32 tx_fifo_deq_pipeline_depth; 401 bool errata_A006320; 402 bool excessive_threshold_register; 403 bool fmbm_tfne_has_features; 404 405 enum fman_port_dma_swap dma_swap_data; 406 enum fman_port_color color; 407 }; 408 409 struct fman_port_rx_pools_params { 410 u8 num_of_pools; 411 u16 largest_buf_size; 412 }; 413 414 struct fman_port_dts_params { 415 void __iomem *base_addr; /* FMan port virtual memory */ 416 enum fman_port_type type; /* Port type */ 417 u16 speed; /* Port speed */ 418 u8 id; /* HW Port Id */ 419 u32 qman_channel_id; /* QMan channel id (non RX only) */ 420 struct fman *fman; /* FMan Handle */ 421 }; 422 423 struct fman_port { 424 void *fm; 425 struct device *dev; 426 struct fman_rev_info rev_info; 427 u8 port_id; 428 enum fman_port_type port_type; 429 u16 port_speed; 430 431 union fman_port_bmi_regs __iomem *bmi_regs; 432 struct fman_port_qmi_regs __iomem *qmi_regs; 433 struct fman_port_hwp_regs __iomem *hwp_regs; 434 435 struct fman_sp_buffer_offsets buffer_offsets; 436 437 u8 internal_buf_offset; 438 struct fman_ext_pools ext_buf_pools; 439 440 u16 max_frame_length; 441 struct fman_port_rsrc open_dmas; 442 struct fman_port_rsrc tasks; 443 struct fman_port_rsrc fifo_bufs; 444 struct fman_port_rx_pools_params rx_pools_params; 445 446 struct fman_port_cfg *cfg; 447 struct fman_port_dts_params dts_params; 448 449 u8 ext_pools_num; 450 u32 max_port_fifo_size; 451 u32 max_num_of_ext_pools; 452 u32 max_num_of_sub_portals; 453 u32 bm_max_num_of_pools; 454 }; 455 456 static int init_bmi_rx(struct fman_port *port) 457 { 458 struct fman_port_rx_bmi_regs __iomem *regs = &port->bmi_regs->rx; 459 struct fman_port_cfg *cfg = port->cfg; 460 u32 tmp; 461 462 /* DMA attributes */ 463 tmp = (u32)cfg->dma_swap_data << BMI_DMA_ATTR_SWP_SHIFT; 464 /* Enable write optimization */ 465 tmp |= BMI_DMA_ATTR_WRITE_OPTIMIZE; 466 iowrite32be(tmp, ®s->fmbm_rda); 467 468 /* Rx FIFO parameters */ 469 tmp = (cfg->rx_pri_elevation / PORT_BMI_FIFO_UNITS - 1) << 470 BMI_RX_FIFO_PRI_ELEVATION_SHIFT; 471 tmp |= cfg->rx_fifo_thr / PORT_BMI_FIFO_UNITS - 1; 472 iowrite32be(tmp, ®s->fmbm_rfp); 473 474 if (cfg->excessive_threshold_register) 475 /* always allow access to the extra resources */ 476 iowrite32be(BMI_RX_FIFO_THRESHOLD_ETHE, ®s->fmbm_reth); 477 478 /* Frame end data */ 479 tmp = (cfg->cheksum_last_bytes_ignore & BMI_FRAME_END_CS_IGNORE_MASK) << 480 BMI_FRAME_END_CS_IGNORE_SHIFT; 481 tmp |= (cfg->rx_cut_end_bytes & BMI_RX_FRAME_END_CUT_MASK) << 482 BMI_RX_FRAME_END_CUT_SHIFT; 483 if (cfg->errata_A006320) 484 tmp &= 0xffe0ffff; 485 iowrite32be(tmp, ®s->fmbm_rfed); 486 487 /* Internal context parameters */ 488 tmp = ((cfg->int_context.ext_buf_offset / PORT_IC_OFFSET_UNITS) & 489 BMI_IC_TO_EXT_MASK) << BMI_IC_TO_EXT_SHIFT; 490 tmp |= ((cfg->int_context.int_context_offset / PORT_IC_OFFSET_UNITS) & 491 BMI_IC_FROM_INT_MASK) << BMI_IC_FROM_INT_SHIFT; 492 tmp |= (cfg->int_context.size / PORT_IC_OFFSET_UNITS) & 493 BMI_IC_SIZE_MASK; 494 iowrite32be(tmp, ®s->fmbm_ricp); 495 496 /* Internal buffer offset */ 497 tmp = ((cfg->int_buf_start_margin / PORT_IC_OFFSET_UNITS) & 498 BMI_INT_BUF_MARG_MASK) << BMI_INT_BUF_MARG_SHIFT; 499 iowrite32be(tmp, ®s->fmbm_rim); 500 501 /* External buffer margins */ 502 tmp = (cfg->buf_margins.start_margins & BMI_EXT_BUF_MARG_START_MASK) << 503 BMI_EXT_BUF_MARG_START_SHIFT; 504 tmp |= cfg->buf_margins.end_margins & BMI_EXT_BUF_MARG_END_MASK; 505 iowrite32be(tmp, ®s->fmbm_rebm); 506 507 /* Frame attributes */ 508 tmp = BMI_CMD_RX_MR_DEF; 509 tmp |= BMI_CMD_ATTR_ORDER; 510 tmp |= (u32)cfg->color << BMI_CMD_ATTR_COLOR_SHIFT; 511 /* Synchronization request */ 512 tmp |= BMI_CMD_ATTR_SYNC; 513 514 iowrite32be(tmp, ®s->fmbm_rfca); 515 516 /* NIA */ 517 tmp = (u32)cfg->rx_fd_bits << BMI_NEXT_ENG_FD_BITS_SHIFT; 518 519 tmp |= NIA_ENG_HWP; 520 iowrite32be(tmp, ®s->fmbm_rfne); 521 522 /* Parser Next Engine NIA */ 523 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME, ®s->fmbm_rfpne); 524 525 /* Enqueue NIA */ 526 iowrite32be(NIA_ENG_QMI_ENQ | NIA_ORDER_RESTOR, ®s->fmbm_rfene); 527 528 /* Default/error queues */ 529 iowrite32be((cfg->dflt_fqid & DFLT_FQ_ID), ®s->fmbm_rfqid); 530 iowrite32be((cfg->err_fqid & DFLT_FQ_ID), ®s->fmbm_refqid); 531 532 /* Discard/error masks */ 533 iowrite32be(cfg->discard_mask, ®s->fmbm_rfsdm); 534 iowrite32be(cfg->err_mask, ®s->fmbm_rfsem); 535 536 return 0; 537 } 538 539 static int init_bmi_tx(struct fman_port *port) 540 { 541 struct fman_port_tx_bmi_regs __iomem *regs = &port->bmi_regs->tx; 542 struct fman_port_cfg *cfg = port->cfg; 543 u32 tmp; 544 545 /* Tx Configuration register */ 546 tmp = 0; 547 iowrite32be(tmp, ®s->fmbm_tcfg); 548 549 /* DMA attributes */ 550 tmp = (u32)cfg->dma_swap_data << BMI_DMA_ATTR_SWP_SHIFT; 551 iowrite32be(tmp, ®s->fmbm_tda); 552 553 /* Tx FIFO parameters */ 554 tmp = (cfg->tx_fifo_min_level / PORT_BMI_FIFO_UNITS) << 555 BMI_TX_FIFO_MIN_FILL_SHIFT; 556 tmp |= ((cfg->tx_fifo_deq_pipeline_depth - 1) & 557 BMI_FIFO_PIPELINE_DEPTH_MASK) << BMI_FIFO_PIPELINE_DEPTH_SHIFT; 558 tmp |= (cfg->tx_fifo_low_comf_level / PORT_BMI_FIFO_UNITS) - 1; 559 iowrite32be(tmp, ®s->fmbm_tfp); 560 561 /* Frame end data */ 562 tmp = (cfg->cheksum_last_bytes_ignore & BMI_FRAME_END_CS_IGNORE_MASK) << 563 BMI_FRAME_END_CS_IGNORE_SHIFT; 564 iowrite32be(tmp, ®s->fmbm_tfed); 565 566 /* Internal context parameters */ 567 tmp = ((cfg->int_context.ext_buf_offset / PORT_IC_OFFSET_UNITS) & 568 BMI_IC_TO_EXT_MASK) << BMI_IC_TO_EXT_SHIFT; 569 tmp |= ((cfg->int_context.int_context_offset / PORT_IC_OFFSET_UNITS) & 570 BMI_IC_FROM_INT_MASK) << BMI_IC_FROM_INT_SHIFT; 571 tmp |= (cfg->int_context.size / PORT_IC_OFFSET_UNITS) & 572 BMI_IC_SIZE_MASK; 573 iowrite32be(tmp, ®s->fmbm_ticp); 574 575 /* Frame attributes */ 576 tmp = BMI_CMD_TX_MR_DEF; 577 tmp |= BMI_CMD_ATTR_ORDER; 578 tmp |= (u32)cfg->color << BMI_CMD_ATTR_COLOR_SHIFT; 579 iowrite32be(tmp, ®s->fmbm_tfca); 580 581 /* Dequeue NIA + enqueue NIA */ 582 iowrite32be(NIA_ENG_QMI_DEQ, ®s->fmbm_tfdne); 583 iowrite32be(NIA_ENG_QMI_ENQ | NIA_ORDER_RESTOR, ®s->fmbm_tfene); 584 if (cfg->fmbm_tfne_has_features) 585 iowrite32be(!cfg->dflt_fqid ? 586 BMI_EBD_EN | NIA_BMI_AC_FETCH_ALL_FRAME : 587 NIA_BMI_AC_FETCH_ALL_FRAME, ®s->fmbm_tfne); 588 if (!cfg->dflt_fqid && cfg->dont_release_buf) { 589 iowrite32be(DFLT_FQ_ID, ®s->fmbm_tcfqid); 590 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE, 591 ®s->fmbm_tfene); 592 if (cfg->fmbm_tfne_has_features) 593 iowrite32be(ioread32be(®s->fmbm_tfne) & ~BMI_EBD_EN, 594 ®s->fmbm_tfne); 595 } 596 597 /* Confirmation/error queues */ 598 if (cfg->dflt_fqid || !cfg->dont_release_buf) 599 iowrite32be(cfg->dflt_fqid & DFLT_FQ_ID, ®s->fmbm_tcfqid); 600 iowrite32be((cfg->err_fqid & DFLT_FQ_ID), ®s->fmbm_tefqid); 601 602 return 0; 603 } 604 605 static int init_qmi(struct fman_port *port) 606 { 607 struct fman_port_qmi_regs __iomem *regs = port->qmi_regs; 608 struct fman_port_cfg *cfg = port->cfg; 609 u32 tmp; 610 611 /* Rx port configuration */ 612 if (port->port_type == FMAN_PORT_TYPE_RX) { 613 /* Enqueue NIA */ 614 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_RELEASE, ®s->fmqm_pnen); 615 return 0; 616 } 617 618 /* Continue with Tx port configuration */ 619 if (port->port_type == FMAN_PORT_TYPE_TX) { 620 /* Enqueue NIA */ 621 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE, 622 ®s->fmqm_pnen); 623 /* Dequeue NIA */ 624 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX, ®s->fmqm_pndn); 625 } 626 627 /* Dequeue Configuration register */ 628 tmp = 0; 629 if (cfg->deq_high_priority) 630 tmp |= QMI_DEQ_CFG_PRI; 631 632 switch (cfg->deq_type) { 633 case FMAN_PORT_DEQ_BY_PRI: 634 tmp |= QMI_DEQ_CFG_TYPE1; 635 break; 636 case FMAN_PORT_DEQ_ACTIVE_FQ: 637 tmp |= QMI_DEQ_CFG_TYPE2; 638 break; 639 case FMAN_PORT_DEQ_ACTIVE_FQ_NO_ICS: 640 tmp |= QMI_DEQ_CFG_TYPE3; 641 break; 642 default: 643 return -EINVAL; 644 } 645 646 switch (cfg->deq_prefetch_option) { 647 case FMAN_PORT_DEQ_NO_PREFETCH: 648 break; 649 case FMAN_PORT_DEQ_PART_PREFETCH: 650 tmp |= QMI_DEQ_CFG_PREFETCH_PARTIAL; 651 break; 652 case FMAN_PORT_DEQ_FULL_PREFETCH: 653 tmp |= QMI_DEQ_CFG_PREFETCH_FULL; 654 break; 655 default: 656 return -EINVAL; 657 } 658 659 tmp |= (cfg->deq_sp & QMI_DEQ_CFG_SP_MASK) << QMI_DEQ_CFG_SP_SHIFT; 660 tmp |= cfg->deq_byte_cnt; 661 iowrite32be(tmp, ®s->fmqm_pndc); 662 663 return 0; 664 } 665 666 static void stop_port_hwp(struct fman_port *port) 667 { 668 struct fman_port_hwp_regs __iomem *regs = port->hwp_regs; 669 int cnt = 100; 670 671 iowrite32be(HWP_HXS_PCAC_PSTOP, ®s->fmpr_pcac); 672 673 while (cnt-- > 0 && 674 (ioread32be(®s->fmpr_pcac) & HWP_HXS_PCAC_PSTAT)) 675 udelay(10); 676 if (!cnt) 677 pr_err("Timeout stopping HW Parser\n"); 678 } 679 680 static void start_port_hwp(struct fman_port *port) 681 { 682 struct fman_port_hwp_regs __iomem *regs = port->hwp_regs; 683 int cnt = 100; 684 685 iowrite32be(0, ®s->fmpr_pcac); 686 687 while (cnt-- > 0 && 688 !(ioread32be(®s->fmpr_pcac) & HWP_HXS_PCAC_PSTAT)) 689 udelay(10); 690 if (!cnt) 691 pr_err("Timeout starting HW Parser\n"); 692 } 693 694 static void init_hwp(struct fman_port *port) 695 { 696 struct fman_port_hwp_regs __iomem *regs = port->hwp_regs; 697 int i; 698 699 stop_port_hwp(port); 700 701 for (i = 0; i < HWP_HXS_COUNT; i++) { 702 /* enable HXS error reporting into FD[STATUS] PHE */ 703 iowrite32be(0x00000000, ®s->pmda[i].ssa); 704 iowrite32be(0xffffffff, ®s->pmda[i].lcv); 705 } 706 707 /* Short packet padding removal from checksum calculation */ 708 iowrite32be(HWP_HXS_SH_PAD_REM, ®s->pmda[HWP_HXS_TCP_OFFSET].ssa); 709 iowrite32be(HWP_HXS_SH_PAD_REM, ®s->pmda[HWP_HXS_UDP_OFFSET].ssa); 710 711 start_port_hwp(port); 712 } 713 714 static int init(struct fman_port *port) 715 { 716 int err; 717 718 /* Init BMI registers */ 719 switch (port->port_type) { 720 case FMAN_PORT_TYPE_RX: 721 err = init_bmi_rx(port); 722 if (!err) 723 init_hwp(port); 724 break; 725 case FMAN_PORT_TYPE_TX: 726 err = init_bmi_tx(port); 727 break; 728 default: 729 return -EINVAL; 730 } 731 732 if (err) 733 return err; 734 735 /* Init QMI registers */ 736 err = init_qmi(port); 737 if (err) 738 return err; 739 740 return 0; 741 } 742 743 static int set_bpools(const struct fman_port *port, 744 const struct fman_port_bpools *bp) 745 { 746 u32 __iomem *bp_reg, *bp_depl_reg; 747 u32 tmp; 748 u8 i, max_bp_num; 749 bool grp_depl_used = false, rx_port; 750 751 switch (port->port_type) { 752 case FMAN_PORT_TYPE_RX: 753 max_bp_num = port->ext_pools_num; 754 rx_port = true; 755 bp_reg = port->bmi_regs->rx.fmbm_ebmpi; 756 bp_depl_reg = &port->bmi_regs->rx.fmbm_mpd; 757 break; 758 default: 759 return -EINVAL; 760 } 761 762 if (rx_port) { 763 /* Check buffers are provided in ascending order */ 764 for (i = 0; (i < (bp->count - 1) && 765 (i < FMAN_PORT_MAX_EXT_POOLS_NUM - 1)); i++) { 766 if (bp->bpool[i].size > bp->bpool[i + 1].size) 767 return -EINVAL; 768 } 769 } 770 771 /* Set up external buffers pools */ 772 for (i = 0; i < bp->count; i++) { 773 tmp = BMI_EXT_BUF_POOL_VALID; 774 tmp |= ((u32)bp->bpool[i].bpid << 775 BMI_EXT_BUF_POOL_ID_SHIFT) & BMI_EXT_BUF_POOL_ID_MASK; 776 777 if (rx_port) { 778 if (bp->counters_enable) 779 tmp |= BMI_EXT_BUF_POOL_EN_COUNTER; 780 781 if (bp->bpool[i].is_backup) 782 tmp |= BMI_EXT_BUF_POOL_BACKUP; 783 784 tmp |= (u32)bp->bpool[i].size; 785 } 786 787 iowrite32be(tmp, &bp_reg[i]); 788 } 789 790 /* Clear unused pools */ 791 for (i = bp->count; i < max_bp_num; i++) 792 iowrite32be(0, &bp_reg[i]); 793 794 /* Pools depletion */ 795 tmp = 0; 796 for (i = 0; i < FMAN_PORT_MAX_EXT_POOLS_NUM; i++) { 797 if (bp->bpool[i].grp_bp_depleted) { 798 grp_depl_used = true; 799 tmp |= 0x80000000 >> i; 800 } 801 802 if (bp->bpool[i].single_bp_depleted) 803 tmp |= 0x80 >> i; 804 } 805 806 if (grp_depl_used) 807 tmp |= ((u32)bp->grp_bp_depleted_num - 1) << 808 BMI_POOL_DEP_NUM_OF_POOLS_SHIFT; 809 810 iowrite32be(tmp, bp_depl_reg); 811 return 0; 812 } 813 814 static bool is_init_done(struct fman_port_cfg *cfg) 815 { 816 /* Checks if FMan port driver parameters were initialized */ 817 if (!cfg) 818 return true; 819 820 return false; 821 } 822 823 static int verify_size_of_fifo(struct fman_port *port) 824 { 825 u32 min_fifo_size_required = 0, opt_fifo_size_for_b2b = 0; 826 827 /* TX Ports */ 828 if (port->port_type == FMAN_PORT_TYPE_TX) { 829 min_fifo_size_required = (u32) 830 (roundup(port->max_frame_length, 831 FMAN_BMI_FIFO_UNITS) + (3 * FMAN_BMI_FIFO_UNITS)); 832 833 min_fifo_size_required += 834 port->cfg->tx_fifo_deq_pipeline_depth * 835 FMAN_BMI_FIFO_UNITS; 836 837 opt_fifo_size_for_b2b = min_fifo_size_required; 838 839 /* Add some margin for back-to-back capability to improve 840 * performance, allows the hardware to pipeline new frame dma 841 * while the previous frame not yet transmitted. 842 */ 843 if (port->port_speed == 10000) 844 opt_fifo_size_for_b2b += 3 * FMAN_BMI_FIFO_UNITS; 845 else 846 opt_fifo_size_for_b2b += 2 * FMAN_BMI_FIFO_UNITS; 847 } 848 849 /* RX Ports */ 850 else if (port->port_type == FMAN_PORT_TYPE_RX) { 851 if (port->rev_info.major >= 6) 852 min_fifo_size_required = (u32) 853 (roundup(port->max_frame_length, 854 FMAN_BMI_FIFO_UNITS) + 855 (5 * FMAN_BMI_FIFO_UNITS)); 856 /* 4 according to spec + 1 for FOF>0 */ 857 else 858 min_fifo_size_required = (u32) 859 (roundup(min(port->max_frame_length, 860 port->rx_pools_params.largest_buf_size), 861 FMAN_BMI_FIFO_UNITS) + 862 (7 * FMAN_BMI_FIFO_UNITS)); 863 864 opt_fifo_size_for_b2b = min_fifo_size_required; 865 866 /* Add some margin for back-to-back capability to improve 867 * performance,allows the hardware to pipeline new frame dma 868 * while the previous frame not yet transmitted. 869 */ 870 if (port->port_speed == 10000) 871 opt_fifo_size_for_b2b += 8 * FMAN_BMI_FIFO_UNITS; 872 else 873 opt_fifo_size_for_b2b += 3 * FMAN_BMI_FIFO_UNITS; 874 } 875 876 WARN_ON(min_fifo_size_required <= 0); 877 WARN_ON(opt_fifo_size_for_b2b < min_fifo_size_required); 878 879 /* Verify the size */ 880 if (port->fifo_bufs.num < min_fifo_size_required) 881 dev_dbg(port->dev, "%s: FIFO size should be enlarged to %d bytes\n", 882 __func__, min_fifo_size_required); 883 else if (port->fifo_bufs.num < opt_fifo_size_for_b2b) 884 dev_dbg(port->dev, "%s: For b2b processing,FIFO may be enlarged to %d bytes\n", 885 __func__, opt_fifo_size_for_b2b); 886 887 return 0; 888 } 889 890 static int set_ext_buffer_pools(struct fman_port *port) 891 { 892 struct fman_ext_pools *ext_buf_pools = &port->cfg->ext_buf_pools; 893 struct fman_buf_pool_depletion *buf_pool_depletion = 894 &port->cfg->buf_pool_depletion; 895 u8 ordered_array[FMAN_PORT_MAX_EXT_POOLS_NUM]; 896 u16 sizes_array[BM_MAX_NUM_OF_POOLS]; 897 int i = 0, j = 0, err; 898 struct fman_port_bpools bpools; 899 900 memset(&ordered_array, 0, sizeof(u8) * FMAN_PORT_MAX_EXT_POOLS_NUM); 901 memset(&sizes_array, 0, sizeof(u16) * BM_MAX_NUM_OF_POOLS); 902 memcpy(&port->ext_buf_pools, ext_buf_pools, 903 sizeof(struct fman_ext_pools)); 904 905 fman_sp_set_buf_pools_in_asc_order_of_buf_sizes(ext_buf_pools, 906 ordered_array, 907 sizes_array); 908 909 memset(&bpools, 0, sizeof(struct fman_port_bpools)); 910 bpools.count = ext_buf_pools->num_of_pools_used; 911 bpools.counters_enable = true; 912 for (i = 0; i < ext_buf_pools->num_of_pools_used; i++) { 913 bpools.bpool[i].bpid = ordered_array[i]; 914 bpools.bpool[i].size = sizes_array[ordered_array[i]]; 915 } 916 917 /* save pools parameters for later use */ 918 port->rx_pools_params.num_of_pools = ext_buf_pools->num_of_pools_used; 919 port->rx_pools_params.largest_buf_size = 920 sizes_array[ordered_array[ext_buf_pools->num_of_pools_used - 1]]; 921 922 /* FMBM_RMPD reg. - pool depletion */ 923 if (buf_pool_depletion->pools_grp_mode_enable) { 924 bpools.grp_bp_depleted_num = buf_pool_depletion->num_of_pools; 925 for (i = 0; i < port->bm_max_num_of_pools; i++) { 926 if (buf_pool_depletion->pools_to_consider[i]) { 927 for (j = 0; j < ext_buf_pools-> 928 num_of_pools_used; j++) { 929 if (i == ordered_array[j]) { 930 bpools.bpool[j]. 931 grp_bp_depleted = true; 932 break; 933 } 934 } 935 } 936 } 937 } 938 939 if (buf_pool_depletion->single_pool_mode_enable) { 940 for (i = 0; i < port->bm_max_num_of_pools; i++) { 941 if (buf_pool_depletion-> 942 pools_to_consider_for_single_mode[i]) { 943 for (j = 0; j < ext_buf_pools-> 944 num_of_pools_used; j++) { 945 if (i == ordered_array[j]) { 946 bpools.bpool[j]. 947 single_bp_depleted = true; 948 break; 949 } 950 } 951 } 952 } 953 } 954 955 err = set_bpools(port, &bpools); 956 if (err != 0) { 957 dev_err(port->dev, "%s: set_bpools() failed\n", __func__); 958 return -EINVAL; 959 } 960 961 return 0; 962 } 963 964 static int init_low_level_driver(struct fman_port *port) 965 { 966 struct fman_port_cfg *cfg = port->cfg; 967 u32 tmp_val; 968 969 switch (port->port_type) { 970 case FMAN_PORT_TYPE_RX: 971 cfg->err_mask = (RX_ERRS_TO_ENQ & ~cfg->discard_mask); 972 break; 973 default: 974 break; 975 } 976 977 tmp_val = (u32)((port->internal_buf_offset % OFFSET_UNITS) ? 978 (port->internal_buf_offset / OFFSET_UNITS + 1) : 979 (port->internal_buf_offset / OFFSET_UNITS)); 980 port->internal_buf_offset = (u8)(tmp_val * OFFSET_UNITS); 981 port->cfg->int_buf_start_margin = port->internal_buf_offset; 982 983 if (init(port) != 0) { 984 dev_err(port->dev, "%s: fman port initialization failed\n", 985 __func__); 986 return -ENODEV; 987 } 988 989 /* The code bellow is a trick so the FM will not release the buffer 990 * to BM nor will try to enqueue the frame to QM 991 */ 992 if (port->port_type == FMAN_PORT_TYPE_TX) { 993 if (!cfg->dflt_fqid && cfg->dont_release_buf) { 994 /* override fmbm_tcfqid 0 with a false non-0 value. 995 * This will force FM to act according to tfene. 996 * Otherwise, if fmbm_tcfqid is 0 the FM will release 997 * buffers to BM regardless of fmbm_tfene 998 */ 999 iowrite32be(0xFFFFFF, &port->bmi_regs->tx.fmbm_tcfqid); 1000 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE, 1001 &port->bmi_regs->tx.fmbm_tfene); 1002 } 1003 } 1004 1005 return 0; 1006 } 1007 1008 static int fill_soc_specific_params(struct fman_port *port) 1009 { 1010 u32 bmi_max_fifo_size; 1011 1012 bmi_max_fifo_size = fman_get_bmi_max_fifo_size(port->fm); 1013 port->max_port_fifo_size = MAX_PORT_FIFO_SIZE(bmi_max_fifo_size); 1014 port->bm_max_num_of_pools = 64; 1015 1016 /* P4080 - Major 2 1017 * P2041/P3041/P5020/P5040 - Major 3 1018 * Tx/Bx - Major 6 1019 */ 1020 switch (port->rev_info.major) { 1021 case 2: 1022 case 3: 1023 port->max_num_of_ext_pools = 4; 1024 port->max_num_of_sub_portals = 12; 1025 break; 1026 1027 case 6: 1028 port->max_num_of_ext_pools = 8; 1029 port->max_num_of_sub_portals = 16; 1030 break; 1031 1032 default: 1033 dev_err(port->dev, "%s: Unsupported FMan version\n", __func__); 1034 return -EINVAL; 1035 } 1036 1037 return 0; 1038 } 1039 1040 static int get_dflt_fifo_deq_pipeline_depth(u8 major, enum fman_port_type type, 1041 u16 speed) 1042 { 1043 switch (type) { 1044 case FMAN_PORT_TYPE_RX: 1045 case FMAN_PORT_TYPE_TX: 1046 switch (speed) { 1047 case 10000: 1048 return 4; 1049 case 1000: 1050 if (major >= 6) 1051 return 2; 1052 else 1053 return 1; 1054 default: 1055 return 0; 1056 } 1057 default: 1058 return 0; 1059 } 1060 } 1061 1062 static int get_dflt_num_of_tasks(u8 major, enum fman_port_type type, 1063 u16 speed) 1064 { 1065 switch (type) { 1066 case FMAN_PORT_TYPE_RX: 1067 case FMAN_PORT_TYPE_TX: 1068 switch (speed) { 1069 case 10000: 1070 return 16; 1071 case 1000: 1072 if (major >= 6) 1073 return 4; 1074 else 1075 return 3; 1076 default: 1077 return 0; 1078 } 1079 default: 1080 return 0; 1081 } 1082 } 1083 1084 static int get_dflt_extra_num_of_tasks(u8 major, enum fman_port_type type, 1085 u16 speed) 1086 { 1087 switch (type) { 1088 case FMAN_PORT_TYPE_RX: 1089 /* FMan V3 */ 1090 if (major >= 6) 1091 return 0; 1092 1093 /* FMan V2 */ 1094 if (speed == 10000) 1095 return 8; 1096 else 1097 return 2; 1098 case FMAN_PORT_TYPE_TX: 1099 default: 1100 return 0; 1101 } 1102 } 1103 1104 static int get_dflt_num_of_open_dmas(u8 major, enum fman_port_type type, 1105 u16 speed) 1106 { 1107 int val; 1108 1109 if (major >= 6) { 1110 switch (type) { 1111 case FMAN_PORT_TYPE_TX: 1112 if (speed == 10000) 1113 val = 12; 1114 else 1115 val = 3; 1116 break; 1117 case FMAN_PORT_TYPE_RX: 1118 if (speed == 10000) 1119 val = 8; 1120 else 1121 val = 2; 1122 break; 1123 default: 1124 return 0; 1125 } 1126 } else { 1127 switch (type) { 1128 case FMAN_PORT_TYPE_TX: 1129 case FMAN_PORT_TYPE_RX: 1130 if (speed == 10000) 1131 val = 8; 1132 else 1133 val = 1; 1134 break; 1135 default: 1136 val = 0; 1137 } 1138 } 1139 1140 return val; 1141 } 1142 1143 static int get_dflt_extra_num_of_open_dmas(u8 major, enum fman_port_type type, 1144 u16 speed) 1145 { 1146 /* FMan V3 */ 1147 if (major >= 6) 1148 return 0; 1149 1150 /* FMan V2 */ 1151 switch (type) { 1152 case FMAN_PORT_TYPE_RX: 1153 case FMAN_PORT_TYPE_TX: 1154 if (speed == 10000) 1155 return 8; 1156 else 1157 return 1; 1158 default: 1159 return 0; 1160 } 1161 } 1162 1163 static int get_dflt_num_of_fifo_bufs(u8 major, enum fman_port_type type, 1164 u16 speed) 1165 { 1166 int val; 1167 1168 if (major >= 6) { 1169 switch (type) { 1170 case FMAN_PORT_TYPE_TX: 1171 if (speed == 10000) 1172 val = 64; 1173 else 1174 val = 50; 1175 break; 1176 case FMAN_PORT_TYPE_RX: 1177 if (speed == 10000) 1178 val = 96; 1179 else 1180 val = 50; 1181 break; 1182 default: 1183 val = 0; 1184 } 1185 } else { 1186 switch (type) { 1187 case FMAN_PORT_TYPE_TX: 1188 if (speed == 10000) 1189 val = 48; 1190 else 1191 val = 44; 1192 break; 1193 case FMAN_PORT_TYPE_RX: 1194 if (speed == 10000) 1195 val = 48; 1196 else 1197 val = 45; 1198 break; 1199 default: 1200 val = 0; 1201 } 1202 } 1203 1204 return val; 1205 } 1206 1207 static void set_dflt_cfg(struct fman_port *port, 1208 struct fman_port_params *port_params) 1209 { 1210 struct fman_port_cfg *cfg = port->cfg; 1211 1212 cfg->dma_swap_data = FMAN_PORT_DMA_NO_SWAP; 1213 cfg->color = FMAN_PORT_COLOR_GREEN; 1214 cfg->rx_cut_end_bytes = DFLT_PORT_CUT_BYTES_FROM_END; 1215 cfg->rx_pri_elevation = BMI_PRIORITY_ELEVATION_LEVEL; 1216 cfg->rx_fifo_thr = BMI_FIFO_THRESHOLD; 1217 cfg->tx_fifo_low_comf_level = (5 * 1024); 1218 cfg->deq_type = FMAN_PORT_DEQ_BY_PRI; 1219 cfg->deq_prefetch_option = FMAN_PORT_DEQ_FULL_PREFETCH; 1220 cfg->tx_fifo_deq_pipeline_depth = 1221 BMI_DEQUEUE_PIPELINE_DEPTH(port->port_type, port->port_speed); 1222 cfg->deq_byte_cnt = QMI_BYTE_COUNT_LEVEL_CONTROL(port->port_type); 1223 1224 cfg->rx_pri_elevation = 1225 DFLT_PORT_RX_FIFO_PRI_ELEVATION_LEV(port->max_port_fifo_size); 1226 port->cfg->rx_fifo_thr = 1227 DFLT_PORT_RX_FIFO_THRESHOLD(port->rev_info.major, 1228 port->max_port_fifo_size); 1229 1230 if ((port->rev_info.major == 6) && 1231 ((port->rev_info.minor == 0) || (port->rev_info.minor == 3))) 1232 cfg->errata_A006320 = true; 1233 1234 /* Excessive Threshold register - exists for pre-FMv3 chips only */ 1235 if (port->rev_info.major < 6) 1236 cfg->excessive_threshold_register = true; 1237 else 1238 cfg->fmbm_tfne_has_features = true; 1239 1240 cfg->buffer_prefix_content.data_align = 1241 DFLT_PORT_BUFFER_PREFIX_CONTEXT_DATA_ALIGN; 1242 } 1243 1244 static void set_rx_dflt_cfg(struct fman_port *port, 1245 struct fman_port_params *port_params) 1246 { 1247 port->cfg->discard_mask = DFLT_PORT_ERRORS_TO_DISCARD; 1248 1249 memcpy(&port->cfg->ext_buf_pools, 1250 &port_params->specific_params.rx_params.ext_buf_pools, 1251 sizeof(struct fman_ext_pools)); 1252 port->cfg->err_fqid = 1253 port_params->specific_params.rx_params.err_fqid; 1254 port->cfg->dflt_fqid = 1255 port_params->specific_params.rx_params.dflt_fqid; 1256 port->cfg->pcd_base_fqid = 1257 port_params->specific_params.rx_params.pcd_base_fqid; 1258 port->cfg->pcd_fqs_count = 1259 port_params->specific_params.rx_params.pcd_fqs_count; 1260 } 1261 1262 static void set_tx_dflt_cfg(struct fman_port *port, 1263 struct fman_port_params *port_params, 1264 struct fman_port_dts_params *dts_params) 1265 { 1266 port->cfg->tx_fifo_deq_pipeline_depth = 1267 get_dflt_fifo_deq_pipeline_depth(port->rev_info.major, 1268 port->port_type, 1269 port->port_speed); 1270 port->cfg->err_fqid = 1271 port_params->specific_params.non_rx_params.err_fqid; 1272 port->cfg->deq_sp = 1273 (u8)(dts_params->qman_channel_id & QMI_DEQ_CFG_SUBPORTAL_MASK); 1274 port->cfg->dflt_fqid = 1275 port_params->specific_params.non_rx_params.dflt_fqid; 1276 port->cfg->deq_high_priority = true; 1277 } 1278 1279 /** 1280 * fman_port_config 1281 * @port: Pointer to the port structure 1282 * @params: Pointer to data structure of parameters 1283 * 1284 * Creates a descriptor for the FM PORT module. 1285 * The routine returns a pointer to the FM PORT object. 1286 * This descriptor must be passed as first parameter to all other FM PORT 1287 * function calls. 1288 * No actual initialization or configuration of FM hardware is done by this 1289 * routine. 1290 * 1291 * Return: 0 on success; Error code otherwise. 1292 */ 1293 int fman_port_config(struct fman_port *port, struct fman_port_params *params) 1294 { 1295 void __iomem *base_addr = port->dts_params.base_addr; 1296 int err; 1297 1298 /* Allocate the FM driver's parameters structure */ 1299 port->cfg = kzalloc(sizeof(*port->cfg), GFP_KERNEL); 1300 if (!port->cfg) 1301 return -EINVAL; 1302 1303 /* Initialize FM port parameters which will be kept by the driver */ 1304 port->port_type = port->dts_params.type; 1305 port->port_speed = port->dts_params.speed; 1306 port->port_id = port->dts_params.id; 1307 port->fm = port->dts_params.fman; 1308 port->ext_pools_num = (u8)8; 1309 1310 /* get FM revision */ 1311 fman_get_revision(port->fm, &port->rev_info); 1312 1313 err = fill_soc_specific_params(port); 1314 if (err) 1315 goto err_port_cfg; 1316 1317 switch (port->port_type) { 1318 case FMAN_PORT_TYPE_RX: 1319 set_rx_dflt_cfg(port, params); 1320 fallthrough; 1321 case FMAN_PORT_TYPE_TX: 1322 set_tx_dflt_cfg(port, params, &port->dts_params); 1323 fallthrough; 1324 default: 1325 set_dflt_cfg(port, params); 1326 } 1327 1328 /* Continue with other parameters */ 1329 /* set memory map pointers */ 1330 port->bmi_regs = base_addr + BMI_PORT_REGS_OFFSET; 1331 port->qmi_regs = base_addr + QMI_PORT_REGS_OFFSET; 1332 port->hwp_regs = base_addr + HWP_PORT_REGS_OFFSET; 1333 1334 port->max_frame_length = DFLT_PORT_MAX_FRAME_LENGTH; 1335 /* resource distribution. */ 1336 1337 port->fifo_bufs.num = 1338 get_dflt_num_of_fifo_bufs(port->rev_info.major, port->port_type, 1339 port->port_speed) * FMAN_BMI_FIFO_UNITS; 1340 port->fifo_bufs.extra = 1341 DFLT_PORT_EXTRA_NUM_OF_FIFO_BUFS * FMAN_BMI_FIFO_UNITS; 1342 1343 port->open_dmas.num = 1344 get_dflt_num_of_open_dmas(port->rev_info.major, 1345 port->port_type, port->port_speed); 1346 port->open_dmas.extra = 1347 get_dflt_extra_num_of_open_dmas(port->rev_info.major, 1348 port->port_type, port->port_speed); 1349 port->tasks.num = 1350 get_dflt_num_of_tasks(port->rev_info.major, 1351 port->port_type, port->port_speed); 1352 port->tasks.extra = 1353 get_dflt_extra_num_of_tasks(port->rev_info.major, 1354 port->port_type, port->port_speed); 1355 1356 /* FM_HEAVY_TRAFFIC_SEQUENCER_HANG_ERRATA_FMAN_A006981 errata 1357 * workaround 1358 */ 1359 if ((port->rev_info.major == 6) && (port->rev_info.minor == 0) && 1360 (((port->port_type == FMAN_PORT_TYPE_TX) && 1361 (port->port_speed == 1000)))) { 1362 port->open_dmas.num = 16; 1363 port->open_dmas.extra = 0; 1364 } 1365 1366 if (port->rev_info.major >= 6 && 1367 port->port_type == FMAN_PORT_TYPE_TX && 1368 port->port_speed == 1000) { 1369 /* FM_WRONG_RESET_VALUES_ERRATA_FMAN_A005127 Errata 1370 * workaround 1371 */ 1372 u32 reg; 1373 1374 reg = 0x00001013; 1375 iowrite32be(reg, &port->bmi_regs->tx.fmbm_tfp); 1376 } 1377 1378 return 0; 1379 1380 err_port_cfg: 1381 kfree(port->cfg); 1382 return -EINVAL; 1383 } 1384 EXPORT_SYMBOL(fman_port_config); 1385 1386 /* 1387 * fman_port_use_kg_hash 1388 * @port: A pointer to a FM Port module. 1389 * @enable: enable or disable 1390 * 1391 * Sets the HW KeyGen or the BMI as HW Parser next engine, enabling 1392 * or bypassing the KeyGen hashing of Rx traffic 1393 */ 1394 void fman_port_use_kg_hash(struct fman_port *port, bool enable) 1395 { 1396 if (enable) 1397 /* After the Parser frames go to KeyGen */ 1398 iowrite32be(NIA_ENG_HWK, &port->bmi_regs->rx.fmbm_rfpne); 1399 else 1400 /* After the Parser frames go to BMI */ 1401 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME, 1402 &port->bmi_regs->rx.fmbm_rfpne); 1403 } 1404 EXPORT_SYMBOL(fman_port_use_kg_hash); 1405 1406 /** 1407 * fman_port_init 1408 * @port: A pointer to a FM Port module. 1409 * 1410 * Initializes the FM PORT module by defining the software structure and 1411 * configuring the hardware registers. 1412 * 1413 * Return: 0 on success; Error code otherwise. 1414 */ 1415 int fman_port_init(struct fman_port *port) 1416 { 1417 struct fman_port_init_params params; 1418 struct fman_keygen *keygen; 1419 struct fman_port_cfg *cfg; 1420 int err; 1421 1422 if (is_init_done(port->cfg)) 1423 return -EINVAL; 1424 1425 err = fman_sp_build_buffer_struct(&port->cfg->int_context, 1426 &port->cfg->buffer_prefix_content, 1427 &port->cfg->buf_margins, 1428 &port->buffer_offsets, 1429 &port->internal_buf_offset); 1430 if (err) 1431 return err; 1432 1433 cfg = port->cfg; 1434 1435 if (port->port_type == FMAN_PORT_TYPE_RX) { 1436 /* Call the external Buffer routine which also checks fifo 1437 * size and updates it if necessary 1438 */ 1439 /* define external buffer pools and pool depletion */ 1440 err = set_ext_buffer_pools(port); 1441 if (err) 1442 return err; 1443 /* check if the largest external buffer pool is large enough */ 1444 if (cfg->buf_margins.start_margins + MIN_EXT_BUF_SIZE + 1445 cfg->buf_margins.end_margins > 1446 port->rx_pools_params.largest_buf_size) { 1447 dev_err(port->dev, "%s: buf_margins.start_margins (%d) + minimum buf size (64) + buf_margins.end_margins (%d) is larger than maximum external buffer size (%d)\n", 1448 __func__, cfg->buf_margins.start_margins, 1449 cfg->buf_margins.end_margins, 1450 port->rx_pools_params.largest_buf_size); 1451 return -EINVAL; 1452 } 1453 } 1454 1455 /* Call FM module routine for communicating parameters */ 1456 memset(¶ms, 0, sizeof(params)); 1457 params.port_id = port->port_id; 1458 params.port_type = port->port_type; 1459 params.port_speed = port->port_speed; 1460 params.num_of_tasks = (u8)port->tasks.num; 1461 params.num_of_extra_tasks = (u8)port->tasks.extra; 1462 params.num_of_open_dmas = (u8)port->open_dmas.num; 1463 params.num_of_extra_open_dmas = (u8)port->open_dmas.extra; 1464 1465 if (port->fifo_bufs.num) { 1466 err = verify_size_of_fifo(port); 1467 if (err) 1468 return err; 1469 } 1470 params.size_of_fifo = port->fifo_bufs.num; 1471 params.extra_size_of_fifo = port->fifo_bufs.extra; 1472 params.deq_pipeline_depth = port->cfg->tx_fifo_deq_pipeline_depth; 1473 params.max_frame_length = port->max_frame_length; 1474 1475 err = fman_set_port_params(port->fm, ¶ms); 1476 if (err) 1477 return err; 1478 1479 err = init_low_level_driver(port); 1480 if (err) 1481 return err; 1482 1483 if (port->cfg->pcd_fqs_count) { 1484 keygen = port->dts_params.fman->keygen; 1485 err = keygen_port_hashing_init(keygen, port->port_id, 1486 port->cfg->pcd_base_fqid, 1487 port->cfg->pcd_fqs_count); 1488 if (err) 1489 return err; 1490 1491 fman_port_use_kg_hash(port, true); 1492 } 1493 1494 kfree(port->cfg); 1495 port->cfg = NULL; 1496 1497 return 0; 1498 } 1499 EXPORT_SYMBOL(fman_port_init); 1500 1501 /** 1502 * fman_port_cfg_buf_prefix_content 1503 * @port: A pointer to a FM Port module. 1504 * @buffer_prefix_content: A structure of parameters describing 1505 * the structure of the buffer. 1506 * Out parameter: 1507 * Start margin - offset of data from 1508 * start of external buffer. 1509 * Defines the structure, size and content of the application buffer. 1510 * The prefix, in Tx ports, if 'pass_prs_result', the application should set 1511 * a value to their offsets in the prefix of the FM will save the first 1512 * 'priv_data_size', than, depending on 'pass_prs_result' and 1513 * 'pass_time_stamp', copy parse result and timeStamp, and the packet itself 1514 * (in this order), to the application buffer, and to offset. 1515 * Calling this routine changes the buffer margins definitions in the internal 1516 * driver data base from its default configuration: 1517 * Data size: [DEFAULT_PORT_BUFFER_PREFIX_CONTENT_PRIV_DATA_SIZE] 1518 * Pass Parser result: [DEFAULT_PORT_BUFFER_PREFIX_CONTENT_PASS_PRS_RESULT]. 1519 * Pass timestamp: [DEFAULT_PORT_BUFFER_PREFIX_CONTENT_PASS_TIME_STAMP]. 1520 * May be used for all ports 1521 * 1522 * Allowed only following fman_port_config() and before fman_port_init(). 1523 * 1524 * Return: 0 on success; Error code otherwise. 1525 */ 1526 int fman_port_cfg_buf_prefix_content(struct fman_port *port, 1527 struct fman_buffer_prefix_content * 1528 buffer_prefix_content) 1529 { 1530 if (is_init_done(port->cfg)) 1531 return -EINVAL; 1532 1533 memcpy(&port->cfg->buffer_prefix_content, 1534 buffer_prefix_content, 1535 sizeof(struct fman_buffer_prefix_content)); 1536 /* if data_align was not initialized by user, 1537 * we return to driver's default 1538 */ 1539 if (!port->cfg->buffer_prefix_content.data_align) 1540 port->cfg->buffer_prefix_content.data_align = 1541 DFLT_PORT_BUFFER_PREFIX_CONTEXT_DATA_ALIGN; 1542 1543 return 0; 1544 } 1545 EXPORT_SYMBOL(fman_port_cfg_buf_prefix_content); 1546 1547 /** 1548 * fman_port_disable 1549 * @port: A pointer to a FM Port module. 1550 * 1551 * Gracefully disable an FM port. The port will not start new tasks after all 1552 * tasks associated with the port are terminated. 1553 * 1554 * This is a blocking routine, it returns after port is gracefully stopped, 1555 * i.e. the port will not except new frames, but it will finish all frames 1556 * or tasks which were already began. 1557 * Allowed only following fman_port_init(). 1558 * 1559 * Return: 0 on success; Error code otherwise. 1560 */ 1561 int fman_port_disable(struct fman_port *port) 1562 { 1563 u32 __iomem *bmi_cfg_reg, *bmi_status_reg; 1564 u32 tmp; 1565 bool rx_port, failure = false; 1566 int count; 1567 1568 if (!is_init_done(port->cfg)) 1569 return -EINVAL; 1570 1571 switch (port->port_type) { 1572 case FMAN_PORT_TYPE_RX: 1573 bmi_cfg_reg = &port->bmi_regs->rx.fmbm_rcfg; 1574 bmi_status_reg = &port->bmi_regs->rx.fmbm_rst; 1575 rx_port = true; 1576 break; 1577 case FMAN_PORT_TYPE_TX: 1578 bmi_cfg_reg = &port->bmi_regs->tx.fmbm_tcfg; 1579 bmi_status_reg = &port->bmi_regs->tx.fmbm_tst; 1580 rx_port = false; 1581 break; 1582 default: 1583 return -EINVAL; 1584 } 1585 1586 /* Disable QMI */ 1587 if (!rx_port) { 1588 tmp = ioread32be(&port->qmi_regs->fmqm_pnc) & ~QMI_PORT_CFG_EN; 1589 iowrite32be(tmp, &port->qmi_regs->fmqm_pnc); 1590 1591 /* Wait for QMI to finish FD handling */ 1592 count = 100; 1593 do { 1594 udelay(10); 1595 tmp = ioread32be(&port->qmi_regs->fmqm_pns); 1596 } while ((tmp & QMI_PORT_STATUS_DEQ_FD_BSY) && --count); 1597 1598 if (count == 0) { 1599 /* Timeout */ 1600 failure = true; 1601 } 1602 } 1603 1604 /* Disable BMI */ 1605 tmp = ioread32be(bmi_cfg_reg) & ~BMI_PORT_CFG_EN; 1606 iowrite32be(tmp, bmi_cfg_reg); 1607 1608 /* Wait for graceful stop end */ 1609 count = 500; 1610 do { 1611 udelay(10); 1612 tmp = ioread32be(bmi_status_reg); 1613 } while ((tmp & BMI_PORT_STATUS_BSY) && --count); 1614 1615 if (count == 0) { 1616 /* Timeout */ 1617 failure = true; 1618 } 1619 1620 if (failure) 1621 dev_dbg(port->dev, "%s: FMan Port[%d]: BMI or QMI is Busy. Port forced down\n", 1622 __func__, port->port_id); 1623 1624 return 0; 1625 } 1626 EXPORT_SYMBOL(fman_port_disable); 1627 1628 /** 1629 * fman_port_enable 1630 * @port: A pointer to a FM Port module. 1631 * 1632 * A runtime routine provided to allow disable/enable of port. 1633 * 1634 * Allowed only following fman_port_init(). 1635 * 1636 * Return: 0 on success; Error code otherwise. 1637 */ 1638 int fman_port_enable(struct fman_port *port) 1639 { 1640 u32 __iomem *bmi_cfg_reg; 1641 u32 tmp; 1642 bool rx_port; 1643 1644 if (!is_init_done(port->cfg)) 1645 return -EINVAL; 1646 1647 switch (port->port_type) { 1648 case FMAN_PORT_TYPE_RX: 1649 bmi_cfg_reg = &port->bmi_regs->rx.fmbm_rcfg; 1650 rx_port = true; 1651 break; 1652 case FMAN_PORT_TYPE_TX: 1653 bmi_cfg_reg = &port->bmi_regs->tx.fmbm_tcfg; 1654 rx_port = false; 1655 break; 1656 default: 1657 return -EINVAL; 1658 } 1659 1660 /* Enable QMI */ 1661 if (!rx_port) { 1662 tmp = ioread32be(&port->qmi_regs->fmqm_pnc) | QMI_PORT_CFG_EN; 1663 iowrite32be(tmp, &port->qmi_regs->fmqm_pnc); 1664 } 1665 1666 /* Enable BMI */ 1667 tmp = ioread32be(bmi_cfg_reg) | BMI_PORT_CFG_EN; 1668 iowrite32be(tmp, bmi_cfg_reg); 1669 1670 return 0; 1671 } 1672 EXPORT_SYMBOL(fman_port_enable); 1673 1674 /** 1675 * fman_port_bind 1676 * @dev: FMan Port OF device pointer 1677 * 1678 * Bind to a specific FMan Port. 1679 * 1680 * Allowed only after the port was created. 1681 * 1682 * Return: A pointer to the FMan port device. 1683 */ 1684 struct fman_port *fman_port_bind(struct device *dev) 1685 { 1686 return (struct fman_port *)(dev_get_drvdata(get_device(dev))); 1687 } 1688 EXPORT_SYMBOL(fman_port_bind); 1689 1690 /** 1691 * fman_port_get_qman_channel_id 1692 * @port: Pointer to the FMan port devuce 1693 * 1694 * Get the QMan channel ID for the specific port 1695 * 1696 * Return: QMan channel ID 1697 */ 1698 u32 fman_port_get_qman_channel_id(struct fman_port *port) 1699 { 1700 return port->dts_params.qman_channel_id; 1701 } 1702 EXPORT_SYMBOL(fman_port_get_qman_channel_id); 1703 1704 /** 1705 * fman_port_get_device 1706 * @port: Pointer to the FMan port device 1707 * 1708 * Get the 'struct device' associated to the specified FMan port device 1709 * 1710 * Return: pointer to associated 'struct device' 1711 */ 1712 struct device *fman_port_get_device(struct fman_port *port) 1713 { 1714 return port->dev; 1715 } 1716 EXPORT_SYMBOL(fman_port_get_device); 1717 1718 int fman_port_get_hash_result_offset(struct fman_port *port, u32 *offset) 1719 { 1720 if (port->buffer_offsets.hash_result_offset == ILLEGAL_BASE) 1721 return -EINVAL; 1722 1723 *offset = port->buffer_offsets.hash_result_offset; 1724 1725 return 0; 1726 } 1727 EXPORT_SYMBOL(fman_port_get_hash_result_offset); 1728 1729 int fman_port_get_tstamp(struct fman_port *port, const void *data, u64 *tstamp) 1730 { 1731 if (port->buffer_offsets.time_stamp_offset == ILLEGAL_BASE) 1732 return -EINVAL; 1733 1734 *tstamp = be64_to_cpu(*(__be64 *)(data + 1735 port->buffer_offsets.time_stamp_offset)); 1736 1737 return 0; 1738 } 1739 EXPORT_SYMBOL(fman_port_get_tstamp); 1740 1741 static int fman_port_probe(struct platform_device *of_dev) 1742 { 1743 struct fman_port *port; 1744 struct fman *fman; 1745 struct device_node *fm_node, *port_node; 1746 struct platform_device *fm_pdev; 1747 struct resource res; 1748 struct resource *dev_res; 1749 u32 val; 1750 int err = 0, lenp; 1751 enum fman_port_type port_type; 1752 u16 port_speed; 1753 u8 port_id; 1754 1755 port = kzalloc(sizeof(*port), GFP_KERNEL); 1756 if (!port) 1757 return -ENOMEM; 1758 1759 port->dev = &of_dev->dev; 1760 1761 port_node = of_node_get(of_dev->dev.of_node); 1762 1763 /* Get the FM node */ 1764 fm_node = of_get_parent(port_node); 1765 if (!fm_node) { 1766 dev_err(port->dev, "%s: of_get_parent() failed\n", __func__); 1767 err = -ENODEV; 1768 goto return_err; 1769 } 1770 1771 fm_pdev = of_find_device_by_node(fm_node); 1772 of_node_put(fm_node); 1773 if (!fm_pdev) { 1774 err = -EINVAL; 1775 goto return_err; 1776 } 1777 1778 fman = dev_get_drvdata(&fm_pdev->dev); 1779 if (!fman) { 1780 err = -EINVAL; 1781 goto put_device; 1782 } 1783 1784 err = of_property_read_u32(port_node, "cell-index", &val); 1785 if (err) { 1786 dev_err(port->dev, "%s: reading cell-index for %pOF failed\n", 1787 __func__, port_node); 1788 err = -EINVAL; 1789 goto put_device; 1790 } 1791 port_id = (u8)val; 1792 port->dts_params.id = port_id; 1793 1794 if (of_device_is_compatible(port_node, "fsl,fman-v3-port-tx")) { 1795 port_type = FMAN_PORT_TYPE_TX; 1796 port_speed = 1000; 1797 if (of_find_property(port_node, "fsl,fman-10g-port", &lenp)) 1798 port_speed = 10000; 1799 1800 } else if (of_device_is_compatible(port_node, "fsl,fman-v2-port-tx")) { 1801 if (port_id >= TX_10G_PORT_BASE) 1802 port_speed = 10000; 1803 else 1804 port_speed = 1000; 1805 port_type = FMAN_PORT_TYPE_TX; 1806 1807 } else if (of_device_is_compatible(port_node, "fsl,fman-v3-port-rx")) { 1808 port_type = FMAN_PORT_TYPE_RX; 1809 port_speed = 1000; 1810 if (of_find_property(port_node, "fsl,fman-10g-port", &lenp)) 1811 port_speed = 10000; 1812 1813 } else if (of_device_is_compatible(port_node, "fsl,fman-v2-port-rx")) { 1814 if (port_id >= RX_10G_PORT_BASE) 1815 port_speed = 10000; 1816 else 1817 port_speed = 1000; 1818 port_type = FMAN_PORT_TYPE_RX; 1819 1820 } else { 1821 dev_err(port->dev, "%s: Illegal port type\n", __func__); 1822 err = -EINVAL; 1823 goto put_device; 1824 } 1825 1826 port->dts_params.type = port_type; 1827 port->dts_params.speed = port_speed; 1828 1829 if (port_type == FMAN_PORT_TYPE_TX) { 1830 u32 qman_channel_id; 1831 1832 qman_channel_id = fman_get_qman_channel_id(fman, port_id); 1833 if (qman_channel_id == 0) { 1834 dev_err(port->dev, "%s: incorrect qman-channel-id\n", 1835 __func__); 1836 err = -EINVAL; 1837 goto put_device; 1838 } 1839 port->dts_params.qman_channel_id = qman_channel_id; 1840 } 1841 1842 err = of_address_to_resource(port_node, 0, &res); 1843 if (err < 0) { 1844 dev_err(port->dev, "%s: of_address_to_resource() failed\n", 1845 __func__); 1846 err = -ENOMEM; 1847 goto put_device; 1848 } 1849 1850 port->dts_params.fman = fman; 1851 1852 of_node_put(port_node); 1853 1854 dev_res = __devm_request_region(port->dev, &res, res.start, 1855 resource_size(&res), "fman-port"); 1856 if (!dev_res) { 1857 dev_err(port->dev, "%s: __devm_request_region() failed\n", 1858 __func__); 1859 err = -EINVAL; 1860 goto free_port; 1861 } 1862 1863 port->dts_params.base_addr = devm_ioremap(port->dev, res.start, 1864 resource_size(&res)); 1865 if (!port->dts_params.base_addr) 1866 dev_err(port->dev, "%s: devm_ioremap() failed\n", __func__); 1867 1868 dev_set_drvdata(&of_dev->dev, port); 1869 1870 return 0; 1871 1872 put_device: 1873 put_device(&fm_pdev->dev); 1874 return_err: 1875 of_node_put(port_node); 1876 free_port: 1877 kfree(port); 1878 return err; 1879 } 1880 1881 static const struct of_device_id fman_port_match[] = { 1882 {.compatible = "fsl,fman-v3-port-rx"}, 1883 {.compatible = "fsl,fman-v2-port-rx"}, 1884 {.compatible = "fsl,fman-v3-port-tx"}, 1885 {.compatible = "fsl,fman-v2-port-tx"}, 1886 {} 1887 }; 1888 1889 MODULE_DEVICE_TABLE(of, fman_port_match); 1890 1891 static struct platform_driver fman_port_driver = { 1892 .driver = { 1893 .name = "fsl-fman-port", 1894 .of_match_table = fman_port_match, 1895 }, 1896 .probe = fman_port_probe, 1897 }; 1898 1899 static int __init fman_port_load(void) 1900 { 1901 int err; 1902 1903 pr_debug("FSL DPAA FMan driver\n"); 1904 1905 err = platform_driver_register(&fman_port_driver); 1906 if (err < 0) 1907 pr_err("Error, platform_driver_register() = %d\n", err); 1908 1909 return err; 1910 } 1911 module_init(fman_port_load); 1912 1913 static void __exit fman_port_unload(void) 1914 { 1915 platform_driver_unregister(&fman_port_driver); 1916 } 1917 module_exit(fman_port_unload); 1918 1919 MODULE_LICENSE("Dual BSD/GPL"); 1920 MODULE_DESCRIPTION("Freescale DPAA Frame Manager Port driver"); 1921