1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later 2 /* 3 * Copyright 2008 - 2015 Freescale Semiconductor Inc. 4 */ 5 6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 7 8 #include "fman_memac.h" 9 #include "fman.h" 10 11 #include <linux/slab.h> 12 #include <linux/io.h> 13 #include <linux/phy.h> 14 #include <linux/phy_fixed.h> 15 #include <linux/of_mdio.h> 16 17 /* PCS registers */ 18 #define MDIO_SGMII_CR 0x00 19 #define MDIO_SGMII_DEV_ABIL_SGMII 0x04 20 #define MDIO_SGMII_LINK_TMR_L 0x12 21 #define MDIO_SGMII_LINK_TMR_H 0x13 22 #define MDIO_SGMII_IF_MODE 0x14 23 24 /* SGMII Control defines */ 25 #define SGMII_CR_AN_EN 0x1000 26 #define SGMII_CR_RESTART_AN 0x0200 27 #define SGMII_CR_FD 0x0100 28 #define SGMII_CR_SPEED_SEL1_1G 0x0040 29 #define SGMII_CR_DEF_VAL (SGMII_CR_AN_EN | SGMII_CR_FD | \ 30 SGMII_CR_SPEED_SEL1_1G) 31 32 /* SGMII Device Ability for SGMII defines */ 33 #define MDIO_SGMII_DEV_ABIL_SGMII_MODE 0x4001 34 #define MDIO_SGMII_DEV_ABIL_BASEX_MODE 0x01A0 35 36 /* Link timer define */ 37 #define LINK_TMR_L 0xa120 38 #define LINK_TMR_H 0x0007 39 #define LINK_TMR_L_BASEX 0xaf08 40 #define LINK_TMR_H_BASEX 0x002f 41 42 /* SGMII IF Mode defines */ 43 #define IF_MODE_USE_SGMII_AN 0x0002 44 #define IF_MODE_SGMII_EN 0x0001 45 #define IF_MODE_SGMII_SPEED_100M 0x0004 46 #define IF_MODE_SGMII_SPEED_1G 0x0008 47 #define IF_MODE_SGMII_DUPLEX_HALF 0x0010 48 49 /* Num of additional exact match MAC adr regs */ 50 #define MEMAC_NUM_OF_PADDRS 7 51 52 /* Control and Configuration Register (COMMAND_CONFIG) */ 53 #define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */ 54 #define CMD_CFG_TX_LOWP_ENA 0x00800000 /* 08 Tx Low Power Idle Enable */ 55 #define CMD_CFG_PFC_MODE 0x00080000 /* 12 Enable PFC */ 56 #define CMD_CFG_NO_LEN_CHK 0x00020000 /* 14 Payload length check disable */ 57 #define CMD_CFG_SW_RESET 0x00001000 /* 19 S/W Reset, self clearing bit */ 58 #define CMD_CFG_TX_PAD_EN 0x00000800 /* 20 Enable Tx padding of frames */ 59 #define CMD_CFG_PAUSE_IGNORE 0x00000100 /* 23 Ignore Pause frame quanta */ 60 #define CMD_CFG_CRC_FWD 0x00000040 /* 25 Terminate/frwd CRC of frames */ 61 #define CMD_CFG_PAD_EN 0x00000020 /* 26 Frame padding removal */ 62 #define CMD_CFG_PROMIS_EN 0x00000010 /* 27 Promiscuous operation enable */ 63 #define CMD_CFG_RX_EN 0x00000002 /* 30 MAC receive path enable */ 64 #define CMD_CFG_TX_EN 0x00000001 /* 31 MAC transmit path enable */ 65 66 /* Transmit FIFO Sections Register (TX_FIFO_SECTIONS) */ 67 #define TX_FIFO_SECTIONS_TX_EMPTY_MASK 0xFFFF0000 68 #define TX_FIFO_SECTIONS_TX_AVAIL_MASK 0x0000FFFF 69 #define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G 0x00400000 70 #define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G 0x00100000 71 #define TX_FIFO_SECTIONS_TX_AVAIL_10G 0x00000019 72 #define TX_FIFO_SECTIONS_TX_AVAIL_1G 0x00000020 73 #define TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G 0x00000060 74 75 #define GET_TX_EMPTY_DEFAULT_VALUE(_val) \ 76 do { \ 77 _val &= ~TX_FIFO_SECTIONS_TX_EMPTY_MASK; \ 78 ((_val == TX_FIFO_SECTIONS_TX_AVAIL_10G) ? \ 79 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G) :\ 80 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G));\ 81 } while (0) 82 83 /* Interface Mode Register (IF_MODE) */ 84 85 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */ 86 #define IF_MODE_10G 0x00000000 /* 30-31 10G interface */ 87 #define IF_MODE_MII 0x00000001 /* 30-31 MII interface */ 88 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */ 89 #define IF_MODE_RGMII 0x00000004 90 #define IF_MODE_RGMII_AUTO 0x00008000 91 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */ 92 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */ 93 #define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */ 94 #define IF_MODE_RGMII_SP_MASK 0x00006000 /* Setsp mask bits */ 95 #define IF_MODE_RGMII_FD 0x00001000 /* Full duplex RGMII */ 96 #define IF_MODE_HD 0x00000040 /* Half duplex operation */ 97 98 /* Hash table Control Register (HASHTABLE_CTRL) */ 99 #define HASH_CTRL_MCAST_EN 0x00000100 100 /* 26-31 Hash table address code */ 101 #define HASH_CTRL_ADDR_MASK 0x0000003F 102 /* MAC mcast indication */ 103 #define GROUP_ADDRESS 0x0000010000000000LL 104 #define HASH_TABLE_SIZE 64 /* Hash tbl size */ 105 106 /* Interrupt Mask Register (IMASK) */ 107 #define MEMAC_IMASK_MGI 0x40000000 /* 1 Magic pkt detect indication */ 108 #define MEMAC_IMASK_TSECC_ER 0x20000000 /* 2 Timestamp FIFO ECC error evnt */ 109 #define MEMAC_IMASK_TECC_ER 0x02000000 /* 6 Transmit frame ECC error evnt */ 110 #define MEMAC_IMASK_RECC_ER 0x01000000 /* 7 Receive frame ECC error evnt */ 111 112 #define MEMAC_ALL_ERRS_IMASK \ 113 ((u32)(MEMAC_IMASK_TSECC_ER | \ 114 MEMAC_IMASK_TECC_ER | \ 115 MEMAC_IMASK_RECC_ER | \ 116 MEMAC_IMASK_MGI)) 117 118 #define MEMAC_IEVNT_PCS 0x80000000 /* PCS (XG). Link sync (G) */ 119 #define MEMAC_IEVNT_AN 0x40000000 /* Auto-negotiation */ 120 #define MEMAC_IEVNT_LT 0x20000000 /* Link Training/New page */ 121 #define MEMAC_IEVNT_MGI 0x00004000 /* Magic pkt detection */ 122 #define MEMAC_IEVNT_TS_ECC_ER 0x00002000 /* Timestamp FIFO ECC error*/ 123 #define MEMAC_IEVNT_RX_FIFO_OVFL 0x00001000 /* Rx FIFO overflow */ 124 #define MEMAC_IEVNT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */ 125 #define MEMAC_IEVNT_TX_FIFO_OVFL 0x00000400 /* Tx FIFO overflow */ 126 #define MEMAC_IEVNT_TX_ECC_ER 0x00000200 /* Tx frame ECC error */ 127 #define MEMAC_IEVNT_RX_ECC_ER 0x00000100 /* Rx frame ECC error */ 128 #define MEMAC_IEVNT_LI_FAULT 0x00000080 /* Link Interruption flt */ 129 #define MEMAC_IEVNT_RX_EMPTY 0x00000040 /* Rx FIFO empty */ 130 #define MEMAC_IEVNT_TX_EMPTY 0x00000020 /* Tx FIFO empty */ 131 #define MEMAC_IEVNT_RX_LOWP 0x00000010 /* Low Power Idle */ 132 #define MEMAC_IEVNT_PHY_LOS 0x00000004 /* Phy loss of signal */ 133 #define MEMAC_IEVNT_REM_FAULT 0x00000002 /* Remote fault (XGMII) */ 134 #define MEMAC_IEVNT_LOC_FAULT 0x00000001 /* Local fault (XGMII) */ 135 136 #define DEFAULT_PAUSE_QUANTA 0xf000 137 #define DEFAULT_FRAME_LENGTH 0x600 138 #define DEFAULT_TX_IPG_LENGTH 12 139 140 #define CLXY_PAUSE_QUANTA_CLX_PQNT 0x0000FFFF 141 #define CLXY_PAUSE_QUANTA_CLY_PQNT 0xFFFF0000 142 #define CLXY_PAUSE_THRESH_CLX_QTH 0x0000FFFF 143 #define CLXY_PAUSE_THRESH_CLY_QTH 0xFFFF0000 144 145 struct mac_addr { 146 /* Lower 32 bits of 48-bit MAC address */ 147 u32 mac_addr_l; 148 /* Upper 16 bits of 48-bit MAC address */ 149 u32 mac_addr_u; 150 }; 151 152 /* memory map */ 153 struct memac_regs { 154 u32 res0000[2]; /* General Control and Status */ 155 u32 command_config; /* 0x008 Ctrl and cfg */ 156 struct mac_addr mac_addr0; /* 0x00C-0x010 MAC_ADDR_0...1 */ 157 u32 maxfrm; /* 0x014 Max frame length */ 158 u32 res0018[1]; 159 u32 rx_fifo_sections; /* Receive FIFO configuration reg */ 160 u32 tx_fifo_sections; /* Transmit FIFO configuration reg */ 161 u32 res0024[2]; 162 u32 hashtable_ctrl; /* 0x02C Hash table control */ 163 u32 res0030[4]; 164 u32 ievent; /* 0x040 Interrupt event */ 165 u32 tx_ipg_length; /* 0x044 Transmitter inter-packet-gap */ 166 u32 res0048; 167 u32 imask; /* 0x04C Interrupt mask */ 168 u32 res0050; 169 u32 pause_quanta[4]; /* 0x054 Pause quanta */ 170 u32 pause_thresh[4]; /* 0x064 Pause quanta threshold */ 171 u32 rx_pause_status; /* 0x074 Receive pause status */ 172 u32 res0078[2]; 173 struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS];/* 0x80-0x0B4 mac padr */ 174 u32 lpwake_timer; /* 0x0B8 Low Power Wakeup Timer */ 175 u32 sleep_timer; /* 0x0BC Transmit EEE Low Power Timer */ 176 u32 res00c0[8]; 177 u32 statn_config; /* 0x0E0 Statistics configuration */ 178 u32 res00e4[7]; 179 /* Rx Statistics Counter */ 180 u32 reoct_l; 181 u32 reoct_u; 182 u32 roct_l; 183 u32 roct_u; 184 u32 raln_l; 185 u32 raln_u; 186 u32 rxpf_l; 187 u32 rxpf_u; 188 u32 rfrm_l; 189 u32 rfrm_u; 190 u32 rfcs_l; 191 u32 rfcs_u; 192 u32 rvlan_l; 193 u32 rvlan_u; 194 u32 rerr_l; 195 u32 rerr_u; 196 u32 ruca_l; 197 u32 ruca_u; 198 u32 rmca_l; 199 u32 rmca_u; 200 u32 rbca_l; 201 u32 rbca_u; 202 u32 rdrp_l; 203 u32 rdrp_u; 204 u32 rpkt_l; 205 u32 rpkt_u; 206 u32 rund_l; 207 u32 rund_u; 208 u32 r64_l; 209 u32 r64_u; 210 u32 r127_l; 211 u32 r127_u; 212 u32 r255_l; 213 u32 r255_u; 214 u32 r511_l; 215 u32 r511_u; 216 u32 r1023_l; 217 u32 r1023_u; 218 u32 r1518_l; 219 u32 r1518_u; 220 u32 r1519x_l; 221 u32 r1519x_u; 222 u32 rovr_l; 223 u32 rovr_u; 224 u32 rjbr_l; 225 u32 rjbr_u; 226 u32 rfrg_l; 227 u32 rfrg_u; 228 u32 rcnp_l; 229 u32 rcnp_u; 230 u32 rdrntp_l; 231 u32 rdrntp_u; 232 u32 res01d0[12]; 233 /* Tx Statistics Counter */ 234 u32 teoct_l; 235 u32 teoct_u; 236 u32 toct_l; 237 u32 toct_u; 238 u32 res0210[2]; 239 u32 txpf_l; 240 u32 txpf_u; 241 u32 tfrm_l; 242 u32 tfrm_u; 243 u32 tfcs_l; 244 u32 tfcs_u; 245 u32 tvlan_l; 246 u32 tvlan_u; 247 u32 terr_l; 248 u32 terr_u; 249 u32 tuca_l; 250 u32 tuca_u; 251 u32 tmca_l; 252 u32 tmca_u; 253 u32 tbca_l; 254 u32 tbca_u; 255 u32 res0258[2]; 256 u32 tpkt_l; 257 u32 tpkt_u; 258 u32 tund_l; 259 u32 tund_u; 260 u32 t64_l; 261 u32 t64_u; 262 u32 t127_l; 263 u32 t127_u; 264 u32 t255_l; 265 u32 t255_u; 266 u32 t511_l; 267 u32 t511_u; 268 u32 t1023_l; 269 u32 t1023_u; 270 u32 t1518_l; 271 u32 t1518_u; 272 u32 t1519x_l; 273 u32 t1519x_u; 274 u32 res02a8[6]; 275 u32 tcnp_l; 276 u32 tcnp_u; 277 u32 res02c8[14]; 278 /* Line Interface Control */ 279 u32 if_mode; /* 0x300 Interface Mode Control */ 280 u32 if_status; /* 0x304 Interface Status */ 281 u32 res0308[14]; 282 /* HiGig/2 */ 283 u32 hg_config; /* 0x340 Control and cfg */ 284 u32 res0344[3]; 285 u32 hg_pause_quanta; /* 0x350 Pause quanta */ 286 u32 res0354[3]; 287 u32 hg_pause_thresh; /* 0x360 Pause quanta threshold */ 288 u32 res0364[3]; 289 u32 hgrx_pause_status; /* 0x370 Receive pause status */ 290 u32 hg_fifos_status; /* 0x374 fifos status */ 291 u32 rhm; /* 0x378 rx messages counter */ 292 u32 thm; /* 0x37C tx messages counter */ 293 }; 294 295 struct memac_cfg { 296 bool reset_on_init; 297 bool pause_ignore; 298 bool promiscuous_mode_enable; 299 struct fixed_phy_status *fixed_link; 300 u16 max_frame_length; 301 u16 pause_quanta; 302 u32 tx_ipg_length; 303 }; 304 305 struct fman_mac { 306 /* Pointer to MAC memory mapped registers */ 307 struct memac_regs __iomem *regs; 308 /* MAC address of device */ 309 u64 addr; 310 /* Ethernet physical interface */ 311 phy_interface_t phy_if; 312 u16 max_speed; 313 void *dev_id; /* device cookie used by the exception cbs */ 314 fman_mac_exception_cb *exception_cb; 315 fman_mac_exception_cb *event_cb; 316 /* Pointer to driver's global address hash table */ 317 struct eth_hash_t *multicast_addr_hash; 318 /* Pointer to driver's individual address hash table */ 319 struct eth_hash_t *unicast_addr_hash; 320 u8 mac_id; 321 u32 exceptions; 322 struct memac_cfg *memac_drv_param; 323 void *fm; 324 struct fman_rev_info fm_rev_info; 325 bool basex_if; 326 struct phy_device *pcsphy; 327 bool allmulti_enabled; 328 }; 329 330 static void add_addr_in_paddr(struct memac_regs __iomem *regs, const u8 *adr, 331 u8 paddr_num) 332 { 333 u32 tmp0, tmp1; 334 335 tmp0 = (u32)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24); 336 tmp1 = (u32)(adr[4] | adr[5] << 8); 337 338 if (paddr_num == 0) { 339 iowrite32be(tmp0, ®s->mac_addr0.mac_addr_l); 340 iowrite32be(tmp1, ®s->mac_addr0.mac_addr_u); 341 } else { 342 iowrite32be(tmp0, ®s->mac_addr[paddr_num - 1].mac_addr_l); 343 iowrite32be(tmp1, ®s->mac_addr[paddr_num - 1].mac_addr_u); 344 } 345 } 346 347 static int reset(struct memac_regs __iomem *regs) 348 { 349 u32 tmp; 350 int count; 351 352 tmp = ioread32be(®s->command_config); 353 354 tmp |= CMD_CFG_SW_RESET; 355 356 iowrite32be(tmp, ®s->command_config); 357 358 count = 100; 359 do { 360 udelay(1); 361 } while ((ioread32be(®s->command_config) & CMD_CFG_SW_RESET) && 362 --count); 363 364 if (count == 0) 365 return -EBUSY; 366 367 return 0; 368 } 369 370 static void set_exception(struct memac_regs __iomem *regs, u32 val, 371 bool enable) 372 { 373 u32 tmp; 374 375 tmp = ioread32be(®s->imask); 376 if (enable) 377 tmp |= val; 378 else 379 tmp &= ~val; 380 381 iowrite32be(tmp, ®s->imask); 382 } 383 384 static int init(struct memac_regs __iomem *regs, struct memac_cfg *cfg, 385 phy_interface_t phy_if, u16 speed, bool slow_10g_if, 386 u32 exceptions) 387 { 388 u32 tmp; 389 390 /* Config */ 391 tmp = 0; 392 if (cfg->promiscuous_mode_enable) 393 tmp |= CMD_CFG_PROMIS_EN; 394 if (cfg->pause_ignore) 395 tmp |= CMD_CFG_PAUSE_IGNORE; 396 397 /* Payload length check disable */ 398 tmp |= CMD_CFG_NO_LEN_CHK; 399 /* Enable padding of frames in transmit direction */ 400 tmp |= CMD_CFG_TX_PAD_EN; 401 402 tmp |= CMD_CFG_CRC_FWD; 403 404 iowrite32be(tmp, ®s->command_config); 405 406 /* Max Frame Length */ 407 iowrite32be((u32)cfg->max_frame_length, ®s->maxfrm); 408 409 /* Pause Time */ 410 iowrite32be((u32)cfg->pause_quanta, ®s->pause_quanta[0]); 411 iowrite32be((u32)0, ®s->pause_thresh[0]); 412 413 /* IF_MODE */ 414 tmp = 0; 415 switch (phy_if) { 416 case PHY_INTERFACE_MODE_XGMII: 417 tmp |= IF_MODE_10G; 418 break; 419 case PHY_INTERFACE_MODE_MII: 420 tmp |= IF_MODE_MII; 421 break; 422 default: 423 tmp |= IF_MODE_GMII; 424 if (phy_if == PHY_INTERFACE_MODE_RGMII || 425 phy_if == PHY_INTERFACE_MODE_RGMII_ID || 426 phy_if == PHY_INTERFACE_MODE_RGMII_RXID || 427 phy_if == PHY_INTERFACE_MODE_RGMII_TXID) 428 tmp |= IF_MODE_RGMII | IF_MODE_RGMII_AUTO; 429 } 430 iowrite32be(tmp, ®s->if_mode); 431 432 /* TX_FIFO_SECTIONS */ 433 tmp = 0; 434 if (phy_if == PHY_INTERFACE_MODE_XGMII) { 435 if (slow_10g_if) { 436 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G | 437 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G); 438 } else { 439 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_10G | 440 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G); 441 } 442 } else { 443 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_1G | 444 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G); 445 } 446 iowrite32be(tmp, ®s->tx_fifo_sections); 447 448 /* clear all pending events and set-up interrupts */ 449 iowrite32be(0xffffffff, ®s->ievent); 450 set_exception(regs, exceptions, true); 451 452 return 0; 453 } 454 455 static void set_dflts(struct memac_cfg *cfg) 456 { 457 cfg->reset_on_init = false; 458 cfg->promiscuous_mode_enable = false; 459 cfg->pause_ignore = false; 460 cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH; 461 cfg->max_frame_length = DEFAULT_FRAME_LENGTH; 462 cfg->pause_quanta = DEFAULT_PAUSE_QUANTA; 463 } 464 465 static u32 get_mac_addr_hash_code(u64 eth_addr) 466 { 467 u64 mask1, mask2; 468 u32 xor_val = 0; 469 u8 i, j; 470 471 for (i = 0; i < 6; i++) { 472 mask1 = eth_addr & (u64)0x01; 473 eth_addr >>= 1; 474 475 for (j = 0; j < 7; j++) { 476 mask2 = eth_addr & (u64)0x01; 477 mask1 ^= mask2; 478 eth_addr >>= 1; 479 } 480 481 xor_val |= (mask1 << (5 - i)); 482 } 483 484 return xor_val; 485 } 486 487 static void setup_sgmii_internal_phy(struct fman_mac *memac, 488 struct fixed_phy_status *fixed_link) 489 { 490 u16 tmp_reg16; 491 492 if (WARN_ON(!memac->pcsphy)) 493 return; 494 495 /* SGMII mode */ 496 tmp_reg16 = IF_MODE_SGMII_EN; 497 if (!fixed_link) 498 /* AN enable */ 499 tmp_reg16 |= IF_MODE_USE_SGMII_AN; 500 else { 501 switch (fixed_link->speed) { 502 case 10: 503 /* For 10M: IF_MODE[SPEED_10M] = 0 */ 504 break; 505 case 100: 506 tmp_reg16 |= IF_MODE_SGMII_SPEED_100M; 507 break; 508 case 1000: 509 default: 510 tmp_reg16 |= IF_MODE_SGMII_SPEED_1G; 511 break; 512 } 513 if (!fixed_link->duplex) 514 tmp_reg16 |= IF_MODE_SGMII_DUPLEX_HALF; 515 } 516 phy_write(memac->pcsphy, MDIO_SGMII_IF_MODE, tmp_reg16); 517 518 /* Device ability according to SGMII specification */ 519 tmp_reg16 = MDIO_SGMII_DEV_ABIL_SGMII_MODE; 520 phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16); 521 522 /* Adjust link timer for SGMII - 523 * According to Cisco SGMII specification the timer should be 1.6 ms. 524 * The link_timer register is configured in units of the clock. 525 * - When running as 1G SGMII, Serdes clock is 125 MHz, so 526 * unit = 1 / (125*10^6 Hz) = 8 ns. 527 * 1.6 ms in units of 8 ns = 1.6ms / 8ns = 2*10^5 = 0x30d40 528 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so 529 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns. 530 * 1.6 ms in units of 3.2 ns = 1.6ms / 3.2ns = 5*10^5 = 0x7a120. 531 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII, 532 * we always set up here a value of 2.5 SGMII. 533 */ 534 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H); 535 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L); 536 537 if (!fixed_link) 538 /* Restart AN */ 539 tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN; 540 else 541 /* AN disabled */ 542 tmp_reg16 = SGMII_CR_DEF_VAL & ~SGMII_CR_AN_EN; 543 phy_write(memac->pcsphy, 0x0, tmp_reg16); 544 } 545 546 static void setup_sgmii_internal_phy_base_x(struct fman_mac *memac) 547 { 548 u16 tmp_reg16; 549 550 /* AN Device capability */ 551 tmp_reg16 = MDIO_SGMII_DEV_ABIL_BASEX_MODE; 552 phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16); 553 554 /* Adjust link timer for SGMII - 555 * For Serdes 1000BaseX auto-negotiation the timer should be 10 ms. 556 * The link_timer register is configured in units of the clock. 557 * - When running as 1G SGMII, Serdes clock is 125 MHz, so 558 * unit = 1 / (125*10^6 Hz) = 8 ns. 559 * 10 ms in units of 8 ns = 10ms / 8ns = 1250000 = 0x1312d0 560 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so 561 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns. 562 * 10 ms in units of 3.2 ns = 10ms / 3.2ns = 3125000 = 0x2faf08. 563 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII, 564 * we always set up here a value of 2.5 SGMII. 565 */ 566 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H_BASEX); 567 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L_BASEX); 568 569 /* Restart AN */ 570 tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN; 571 phy_write(memac->pcsphy, 0x0, tmp_reg16); 572 } 573 574 static int check_init_parameters(struct fman_mac *memac) 575 { 576 if (!memac->exception_cb) { 577 pr_err("Uninitialized exception handler\n"); 578 return -EINVAL; 579 } 580 if (!memac->event_cb) { 581 pr_warn("Uninitialize event handler\n"); 582 return -EINVAL; 583 } 584 585 return 0; 586 } 587 588 static int get_exception_flag(enum fman_mac_exceptions exception) 589 { 590 u32 bit_mask; 591 592 switch (exception) { 593 case FM_MAC_EX_10G_TX_ECC_ER: 594 bit_mask = MEMAC_IMASK_TECC_ER; 595 break; 596 case FM_MAC_EX_10G_RX_ECC_ER: 597 bit_mask = MEMAC_IMASK_RECC_ER; 598 break; 599 case FM_MAC_EX_TS_FIFO_ECC_ERR: 600 bit_mask = MEMAC_IMASK_TSECC_ER; 601 break; 602 case FM_MAC_EX_MAGIC_PACKET_INDICATION: 603 bit_mask = MEMAC_IMASK_MGI; 604 break; 605 default: 606 bit_mask = 0; 607 break; 608 } 609 610 return bit_mask; 611 } 612 613 static void memac_err_exception(void *handle) 614 { 615 struct fman_mac *memac = (struct fman_mac *)handle; 616 struct memac_regs __iomem *regs = memac->regs; 617 u32 event, imask; 618 619 event = ioread32be(®s->ievent); 620 imask = ioread32be(®s->imask); 621 622 /* Imask include both error and notification/event bits. 623 * Leaving only error bits enabled by imask. 624 * The imask error bits are shifted by 16 bits offset from 625 * their corresponding location in the ievent - hence the >> 16 626 */ 627 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16); 628 629 iowrite32be(event, ®s->ievent); 630 631 if (event & MEMAC_IEVNT_TS_ECC_ER) 632 memac->exception_cb(memac->dev_id, FM_MAC_EX_TS_FIFO_ECC_ERR); 633 if (event & MEMAC_IEVNT_TX_ECC_ER) 634 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_TX_ECC_ER); 635 if (event & MEMAC_IEVNT_RX_ECC_ER) 636 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_RX_ECC_ER); 637 } 638 639 static void memac_exception(void *handle) 640 { 641 struct fman_mac *memac = (struct fman_mac *)handle; 642 struct memac_regs __iomem *regs = memac->regs; 643 u32 event, imask; 644 645 event = ioread32be(®s->ievent); 646 imask = ioread32be(®s->imask); 647 648 /* Imask include both error and notification/event bits. 649 * Leaving only error bits enabled by imask. 650 * The imask error bits are shifted by 16 bits offset from 651 * their corresponding location in the ievent - hence the >> 16 652 */ 653 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16); 654 655 iowrite32be(event, ®s->ievent); 656 657 if (event & MEMAC_IEVNT_MGI) 658 memac->exception_cb(memac->dev_id, 659 FM_MAC_EX_MAGIC_PACKET_INDICATION); 660 } 661 662 static void free_init_resources(struct fman_mac *memac) 663 { 664 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 665 FMAN_INTR_TYPE_ERR); 666 667 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 668 FMAN_INTR_TYPE_NORMAL); 669 670 /* release the driver's group hash table */ 671 free_hash_table(memac->multicast_addr_hash); 672 memac->multicast_addr_hash = NULL; 673 674 /* release the driver's individual hash table */ 675 free_hash_table(memac->unicast_addr_hash); 676 memac->unicast_addr_hash = NULL; 677 } 678 679 static bool is_init_done(struct memac_cfg *memac_drv_params) 680 { 681 /* Checks if mEMAC driver parameters were initialized */ 682 if (!memac_drv_params) 683 return true; 684 685 return false; 686 } 687 688 int memac_enable(struct fman_mac *memac) 689 { 690 struct memac_regs __iomem *regs = memac->regs; 691 u32 tmp; 692 693 if (!is_init_done(memac->memac_drv_param)) 694 return -EINVAL; 695 696 tmp = ioread32be(®s->command_config); 697 tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN; 698 iowrite32be(tmp, ®s->command_config); 699 700 return 0; 701 } 702 703 int memac_disable(struct fman_mac *memac) 704 { 705 struct memac_regs __iomem *regs = memac->regs; 706 u32 tmp; 707 708 if (!is_init_done(memac->memac_drv_param)) 709 return -EINVAL; 710 711 tmp = ioread32be(®s->command_config); 712 tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN); 713 iowrite32be(tmp, ®s->command_config); 714 715 return 0; 716 } 717 718 int memac_set_promiscuous(struct fman_mac *memac, bool new_val) 719 { 720 struct memac_regs __iomem *regs = memac->regs; 721 u32 tmp; 722 723 if (!is_init_done(memac->memac_drv_param)) 724 return -EINVAL; 725 726 tmp = ioread32be(®s->command_config); 727 if (new_val) 728 tmp |= CMD_CFG_PROMIS_EN; 729 else 730 tmp &= ~CMD_CFG_PROMIS_EN; 731 732 iowrite32be(tmp, ®s->command_config); 733 734 return 0; 735 } 736 737 int memac_adjust_link(struct fman_mac *memac, u16 speed) 738 { 739 struct memac_regs __iomem *regs = memac->regs; 740 u32 tmp; 741 742 if (!is_init_done(memac->memac_drv_param)) 743 return -EINVAL; 744 745 tmp = ioread32be(®s->if_mode); 746 747 /* Set full duplex */ 748 tmp &= ~IF_MODE_HD; 749 750 if (phy_interface_mode_is_rgmii(memac->phy_if)) { 751 /* Configure RGMII in manual mode */ 752 tmp &= ~IF_MODE_RGMII_AUTO; 753 tmp &= ~IF_MODE_RGMII_SP_MASK; 754 /* Full duplex */ 755 tmp |= IF_MODE_RGMII_FD; 756 757 switch (speed) { 758 case SPEED_1000: 759 tmp |= IF_MODE_RGMII_1000; 760 break; 761 case SPEED_100: 762 tmp |= IF_MODE_RGMII_100; 763 break; 764 case SPEED_10: 765 tmp |= IF_MODE_RGMII_10; 766 break; 767 default: 768 break; 769 } 770 } 771 772 iowrite32be(tmp, ®s->if_mode); 773 774 return 0; 775 } 776 777 int memac_cfg_max_frame_len(struct fman_mac *memac, u16 new_val) 778 { 779 if (is_init_done(memac->memac_drv_param)) 780 return -EINVAL; 781 782 memac->memac_drv_param->max_frame_length = new_val; 783 784 return 0; 785 } 786 787 int memac_cfg_reset_on_init(struct fman_mac *memac, bool enable) 788 { 789 if (is_init_done(memac->memac_drv_param)) 790 return -EINVAL; 791 792 memac->memac_drv_param->reset_on_init = enable; 793 794 return 0; 795 } 796 797 int memac_cfg_fixed_link(struct fman_mac *memac, 798 struct fixed_phy_status *fixed_link) 799 { 800 if (is_init_done(memac->memac_drv_param)) 801 return -EINVAL; 802 803 memac->memac_drv_param->fixed_link = fixed_link; 804 805 return 0; 806 } 807 808 int memac_set_tx_pause_frames(struct fman_mac *memac, u8 priority, 809 u16 pause_time, u16 thresh_time) 810 { 811 struct memac_regs __iomem *regs = memac->regs; 812 u32 tmp; 813 814 if (!is_init_done(memac->memac_drv_param)) 815 return -EINVAL; 816 817 tmp = ioread32be(®s->tx_fifo_sections); 818 819 GET_TX_EMPTY_DEFAULT_VALUE(tmp); 820 iowrite32be(tmp, ®s->tx_fifo_sections); 821 822 tmp = ioread32be(®s->command_config); 823 tmp &= ~CMD_CFG_PFC_MODE; 824 825 iowrite32be(tmp, ®s->command_config); 826 827 tmp = ioread32be(®s->pause_quanta[priority / 2]); 828 if (priority % 2) 829 tmp &= CLXY_PAUSE_QUANTA_CLX_PQNT; 830 else 831 tmp &= CLXY_PAUSE_QUANTA_CLY_PQNT; 832 tmp |= ((u32)pause_time << (16 * (priority % 2))); 833 iowrite32be(tmp, ®s->pause_quanta[priority / 2]); 834 835 tmp = ioread32be(®s->pause_thresh[priority / 2]); 836 if (priority % 2) 837 tmp &= CLXY_PAUSE_THRESH_CLX_QTH; 838 else 839 tmp &= CLXY_PAUSE_THRESH_CLY_QTH; 840 tmp |= ((u32)thresh_time << (16 * (priority % 2))); 841 iowrite32be(tmp, ®s->pause_thresh[priority / 2]); 842 843 return 0; 844 } 845 846 int memac_accept_rx_pause_frames(struct fman_mac *memac, bool en) 847 { 848 struct memac_regs __iomem *regs = memac->regs; 849 u32 tmp; 850 851 if (!is_init_done(memac->memac_drv_param)) 852 return -EINVAL; 853 854 tmp = ioread32be(®s->command_config); 855 if (en) 856 tmp &= ~CMD_CFG_PAUSE_IGNORE; 857 else 858 tmp |= CMD_CFG_PAUSE_IGNORE; 859 860 iowrite32be(tmp, ®s->command_config); 861 862 return 0; 863 } 864 865 int memac_modify_mac_address(struct fman_mac *memac, const enet_addr_t *enet_addr) 866 { 867 if (!is_init_done(memac->memac_drv_param)) 868 return -EINVAL; 869 870 add_addr_in_paddr(memac->regs, (const u8 *)(*enet_addr), 0); 871 872 return 0; 873 } 874 875 int memac_add_hash_mac_address(struct fman_mac *memac, enet_addr_t *eth_addr) 876 { 877 struct memac_regs __iomem *regs = memac->regs; 878 struct eth_hash_entry *hash_entry; 879 u32 hash; 880 u64 addr; 881 882 if (!is_init_done(memac->memac_drv_param)) 883 return -EINVAL; 884 885 addr = ENET_ADDR_TO_UINT64(*eth_addr); 886 887 if (!(addr & GROUP_ADDRESS)) { 888 /* Unicast addresses not supported in hash */ 889 pr_err("Unicast Address\n"); 890 return -EINVAL; 891 } 892 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK; 893 894 /* Create element to be added to the driver hash table */ 895 hash_entry = kmalloc(sizeof(*hash_entry), GFP_ATOMIC); 896 if (!hash_entry) 897 return -ENOMEM; 898 hash_entry->addr = addr; 899 INIT_LIST_HEAD(&hash_entry->node); 900 901 list_add_tail(&hash_entry->node, 902 &memac->multicast_addr_hash->lsts[hash]); 903 iowrite32be(hash | HASH_CTRL_MCAST_EN, ®s->hashtable_ctrl); 904 905 return 0; 906 } 907 908 int memac_set_allmulti(struct fman_mac *memac, bool enable) 909 { 910 u32 entry; 911 struct memac_regs __iomem *regs = memac->regs; 912 913 if (!is_init_done(memac->memac_drv_param)) 914 return -EINVAL; 915 916 if (enable) { 917 for (entry = 0; entry < HASH_TABLE_SIZE; entry++) 918 iowrite32be(entry | HASH_CTRL_MCAST_EN, 919 ®s->hashtable_ctrl); 920 } else { 921 for (entry = 0; entry < HASH_TABLE_SIZE; entry++) 922 iowrite32be(entry & ~HASH_CTRL_MCAST_EN, 923 ®s->hashtable_ctrl); 924 } 925 926 memac->allmulti_enabled = enable; 927 928 return 0; 929 } 930 931 int memac_set_tstamp(struct fman_mac *memac, bool enable) 932 { 933 return 0; /* Always enabled. */ 934 } 935 936 int memac_del_hash_mac_address(struct fman_mac *memac, enet_addr_t *eth_addr) 937 { 938 struct memac_regs __iomem *regs = memac->regs; 939 struct eth_hash_entry *hash_entry = NULL; 940 struct list_head *pos; 941 u32 hash; 942 u64 addr; 943 944 if (!is_init_done(memac->memac_drv_param)) 945 return -EINVAL; 946 947 addr = ENET_ADDR_TO_UINT64(*eth_addr); 948 949 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK; 950 951 list_for_each(pos, &memac->multicast_addr_hash->lsts[hash]) { 952 hash_entry = ETH_HASH_ENTRY_OBJ(pos); 953 if (hash_entry && hash_entry->addr == addr) { 954 list_del_init(&hash_entry->node); 955 kfree(hash_entry); 956 break; 957 } 958 } 959 960 if (!memac->allmulti_enabled) { 961 if (list_empty(&memac->multicast_addr_hash->lsts[hash])) 962 iowrite32be(hash & ~HASH_CTRL_MCAST_EN, 963 ®s->hashtable_ctrl); 964 } 965 966 return 0; 967 } 968 969 int memac_set_exception(struct fman_mac *memac, 970 enum fman_mac_exceptions exception, bool enable) 971 { 972 u32 bit_mask = 0; 973 974 if (!is_init_done(memac->memac_drv_param)) 975 return -EINVAL; 976 977 bit_mask = get_exception_flag(exception); 978 if (bit_mask) { 979 if (enable) 980 memac->exceptions |= bit_mask; 981 else 982 memac->exceptions &= ~bit_mask; 983 } else { 984 pr_err("Undefined exception\n"); 985 return -EINVAL; 986 } 987 set_exception(memac->regs, bit_mask, enable); 988 989 return 0; 990 } 991 992 int memac_init(struct fman_mac *memac) 993 { 994 struct memac_cfg *memac_drv_param; 995 u8 i; 996 enet_addr_t eth_addr; 997 bool slow_10g_if = false; 998 struct fixed_phy_status *fixed_link; 999 int err; 1000 u32 reg32 = 0; 1001 1002 if (is_init_done(memac->memac_drv_param)) 1003 return -EINVAL; 1004 1005 err = check_init_parameters(memac); 1006 if (err) 1007 return err; 1008 1009 memac_drv_param = memac->memac_drv_param; 1010 1011 if (memac->fm_rev_info.major == 6 && memac->fm_rev_info.minor == 4) 1012 slow_10g_if = true; 1013 1014 /* First, reset the MAC if desired. */ 1015 if (memac_drv_param->reset_on_init) { 1016 err = reset(memac->regs); 1017 if (err) { 1018 pr_err("mEMAC reset failed\n"); 1019 return err; 1020 } 1021 } 1022 1023 /* MAC Address */ 1024 if (memac->addr != 0) { 1025 MAKE_ENET_ADDR_FROM_UINT64(memac->addr, eth_addr); 1026 add_addr_in_paddr(memac->regs, (const u8 *)eth_addr, 0); 1027 } 1028 1029 fixed_link = memac_drv_param->fixed_link; 1030 1031 init(memac->regs, memac->memac_drv_param, memac->phy_if, 1032 memac->max_speed, slow_10g_if, memac->exceptions); 1033 1034 /* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 errata workaround 1035 * Exists only in FMan 6.0 and 6.3. 1036 */ 1037 if ((memac->fm_rev_info.major == 6) && 1038 ((memac->fm_rev_info.minor == 0) || 1039 (memac->fm_rev_info.minor == 3))) { 1040 /* MAC strips CRC from received frames - this workaround 1041 * should decrease the likelihood of bug appearance 1042 */ 1043 reg32 = ioread32be(&memac->regs->command_config); 1044 reg32 &= ~CMD_CFG_CRC_FWD; 1045 iowrite32be(reg32, &memac->regs->command_config); 1046 } 1047 1048 if (memac->phy_if == PHY_INTERFACE_MODE_SGMII) { 1049 /* Configure internal SGMII PHY */ 1050 if (memac->basex_if) 1051 setup_sgmii_internal_phy_base_x(memac); 1052 else 1053 setup_sgmii_internal_phy(memac, fixed_link); 1054 } else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII) { 1055 /* Configure 4 internal SGMII PHYs */ 1056 for (i = 0; i < 4; i++) { 1057 u8 qsmgii_phy_addr, phy_addr; 1058 /* QSGMII PHY address occupies 3 upper bits of 5-bit 1059 * phy_address; the lower 2 bits are used to extend 1060 * register address space and access each one of 4 1061 * ports inside QSGMII. 1062 */ 1063 phy_addr = memac->pcsphy->mdio.addr; 1064 qsmgii_phy_addr = (u8)((phy_addr << 2) | i); 1065 memac->pcsphy->mdio.addr = qsmgii_phy_addr; 1066 if (memac->basex_if) 1067 setup_sgmii_internal_phy_base_x(memac); 1068 else 1069 setup_sgmii_internal_phy(memac, fixed_link); 1070 1071 memac->pcsphy->mdio.addr = phy_addr; 1072 } 1073 } 1074 1075 /* Max Frame Length */ 1076 err = fman_set_mac_max_frame(memac->fm, memac->mac_id, 1077 memac_drv_param->max_frame_length); 1078 if (err) { 1079 pr_err("settings Mac max frame length is FAILED\n"); 1080 return err; 1081 } 1082 1083 memac->multicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE); 1084 if (!memac->multicast_addr_hash) { 1085 free_init_resources(memac); 1086 pr_err("allocation hash table is FAILED\n"); 1087 return -ENOMEM; 1088 } 1089 1090 memac->unicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE); 1091 if (!memac->unicast_addr_hash) { 1092 free_init_resources(memac); 1093 pr_err("allocation hash table is FAILED\n"); 1094 return -ENOMEM; 1095 } 1096 1097 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 1098 FMAN_INTR_TYPE_ERR, memac_err_exception, memac); 1099 1100 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 1101 FMAN_INTR_TYPE_NORMAL, memac_exception, memac); 1102 1103 kfree(memac_drv_param); 1104 memac->memac_drv_param = NULL; 1105 1106 return 0; 1107 } 1108 1109 int memac_free(struct fman_mac *memac) 1110 { 1111 free_init_resources(memac); 1112 1113 if (memac->pcsphy) 1114 put_device(&memac->pcsphy->mdio.dev); 1115 1116 kfree(memac->memac_drv_param); 1117 kfree(memac); 1118 1119 return 0; 1120 } 1121 1122 struct fman_mac *memac_config(struct fman_mac_params *params) 1123 { 1124 struct fman_mac *memac; 1125 struct memac_cfg *memac_drv_param; 1126 void __iomem *base_addr; 1127 1128 base_addr = params->base_addr; 1129 /* allocate memory for the m_emac data structure */ 1130 memac = kzalloc(sizeof(*memac), GFP_KERNEL); 1131 if (!memac) 1132 return NULL; 1133 1134 /* allocate memory for the m_emac driver parameters data structure */ 1135 memac_drv_param = kzalloc(sizeof(*memac_drv_param), GFP_KERNEL); 1136 if (!memac_drv_param) { 1137 memac_free(memac); 1138 return NULL; 1139 } 1140 1141 /* Plant parameter structure pointer */ 1142 memac->memac_drv_param = memac_drv_param; 1143 1144 set_dflts(memac_drv_param); 1145 1146 memac->addr = ENET_ADDR_TO_UINT64(params->addr); 1147 1148 memac->regs = base_addr; 1149 memac->max_speed = params->max_speed; 1150 memac->phy_if = params->phy_if; 1151 memac->mac_id = params->mac_id; 1152 memac->exceptions = (MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER | 1153 MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI); 1154 memac->exception_cb = params->exception_cb; 1155 memac->event_cb = params->event_cb; 1156 memac->dev_id = params->dev_id; 1157 memac->fm = params->fm; 1158 memac->basex_if = params->basex_if; 1159 1160 /* Save FMan revision */ 1161 fman_get_revision(memac->fm, &memac->fm_rev_info); 1162 1163 if (memac->phy_if == PHY_INTERFACE_MODE_SGMII || 1164 memac->phy_if == PHY_INTERFACE_MODE_QSGMII) { 1165 if (!params->internal_phy_node) { 1166 pr_err("PCS PHY node is not available\n"); 1167 memac_free(memac); 1168 return NULL; 1169 } 1170 1171 memac->pcsphy = of_phy_find_device(params->internal_phy_node); 1172 if (!memac->pcsphy) { 1173 pr_err("of_phy_find_device (PCS PHY) failed\n"); 1174 memac_free(memac); 1175 return NULL; 1176 } 1177 } 1178 1179 return memac; 1180 } 1181