1 /* 2 * Copyright 2008-2015 Freescale Semiconductor Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 34 35 #include "fman_memac.h" 36 #include "fman.h" 37 38 #include <linux/slab.h> 39 #include <linux/io.h> 40 #include <linux/phy.h> 41 #include <linux/phy_fixed.h> 42 #include <linux/of_mdio.h> 43 44 /* PCS registers */ 45 #define MDIO_SGMII_CR 0x00 46 #define MDIO_SGMII_DEV_ABIL_SGMII 0x04 47 #define MDIO_SGMII_LINK_TMR_L 0x12 48 #define MDIO_SGMII_LINK_TMR_H 0x13 49 #define MDIO_SGMII_IF_MODE 0x14 50 51 /* SGMII Control defines */ 52 #define SGMII_CR_AN_EN 0x1000 53 #define SGMII_CR_RESTART_AN 0x0200 54 #define SGMII_CR_FD 0x0100 55 #define SGMII_CR_SPEED_SEL1_1G 0x0040 56 #define SGMII_CR_DEF_VAL (SGMII_CR_AN_EN | SGMII_CR_FD | \ 57 SGMII_CR_SPEED_SEL1_1G) 58 59 /* SGMII Device Ability for SGMII defines */ 60 #define MDIO_SGMII_DEV_ABIL_SGMII_MODE 0x4001 61 #define MDIO_SGMII_DEV_ABIL_BASEX_MODE 0x01A0 62 63 /* Link timer define */ 64 #define LINK_TMR_L 0xa120 65 #define LINK_TMR_H 0x0007 66 #define LINK_TMR_L_BASEX 0xaf08 67 #define LINK_TMR_H_BASEX 0x002f 68 69 /* SGMII IF Mode defines */ 70 #define IF_MODE_USE_SGMII_AN 0x0002 71 #define IF_MODE_SGMII_EN 0x0001 72 #define IF_MODE_SGMII_SPEED_100M 0x0004 73 #define IF_MODE_SGMII_SPEED_1G 0x0008 74 #define IF_MODE_SGMII_DUPLEX_HALF 0x0010 75 76 /* Num of additional exact match MAC adr regs */ 77 #define MEMAC_NUM_OF_PADDRS 7 78 79 /* Control and Configuration Register (COMMAND_CONFIG) */ 80 #define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */ 81 #define CMD_CFG_TX_LOWP_ENA 0x00800000 /* 08 Tx Low Power Idle Enable */ 82 #define CMD_CFG_PFC_MODE 0x00080000 /* 12 Enable PFC */ 83 #define CMD_CFG_NO_LEN_CHK 0x00020000 /* 14 Payload length check disable */ 84 #define CMD_CFG_SW_RESET 0x00001000 /* 19 S/W Reset, self clearing bit */ 85 #define CMD_CFG_TX_PAD_EN 0x00000800 /* 20 Enable Tx padding of frames */ 86 #define CMD_CFG_PAUSE_IGNORE 0x00000100 /* 23 Ignore Pause frame quanta */ 87 #define CMD_CFG_CRC_FWD 0x00000040 /* 25 Terminate/frwd CRC of frames */ 88 #define CMD_CFG_PAD_EN 0x00000020 /* 26 Frame padding removal */ 89 #define CMD_CFG_PROMIS_EN 0x00000010 /* 27 Promiscuous operation enable */ 90 #define CMD_CFG_RX_EN 0x00000002 /* 30 MAC receive path enable */ 91 #define CMD_CFG_TX_EN 0x00000001 /* 31 MAC transmit path enable */ 92 93 /* Transmit FIFO Sections Register (TX_FIFO_SECTIONS) */ 94 #define TX_FIFO_SECTIONS_TX_EMPTY_MASK 0xFFFF0000 95 #define TX_FIFO_SECTIONS_TX_AVAIL_MASK 0x0000FFFF 96 #define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G 0x00400000 97 #define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G 0x00100000 98 #define TX_FIFO_SECTIONS_TX_AVAIL_10G 0x00000019 99 #define TX_FIFO_SECTIONS_TX_AVAIL_1G 0x00000020 100 #define TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G 0x00000060 101 102 #define GET_TX_EMPTY_DEFAULT_VALUE(_val) \ 103 do { \ 104 _val &= ~TX_FIFO_SECTIONS_TX_EMPTY_MASK; \ 105 ((_val == TX_FIFO_SECTIONS_TX_AVAIL_10G) ? \ 106 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G) :\ 107 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G));\ 108 } while (0) 109 110 /* Interface Mode Register (IF_MODE) */ 111 112 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */ 113 #define IF_MODE_XGMII 0x00000000 /* 30-31 XGMII (10G) interface */ 114 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */ 115 #define IF_MODE_RGMII 0x00000004 116 #define IF_MODE_RGMII_AUTO 0x00008000 117 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */ 118 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */ 119 #define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */ 120 #define IF_MODE_RGMII_SP_MASK 0x00006000 /* Setsp mask bits */ 121 #define IF_MODE_RGMII_FD 0x00001000 /* Full duplex RGMII */ 122 #define IF_MODE_HD 0x00000040 /* Half duplex operation */ 123 124 /* Hash table Control Register (HASHTABLE_CTRL) */ 125 #define HASH_CTRL_MCAST_EN 0x00000100 126 /* 26-31 Hash table address code */ 127 #define HASH_CTRL_ADDR_MASK 0x0000003F 128 /* MAC mcast indication */ 129 #define GROUP_ADDRESS 0x0000010000000000LL 130 #define HASH_TABLE_SIZE 64 /* Hash tbl size */ 131 132 /* Interrupt Mask Register (IMASK) */ 133 #define MEMAC_IMASK_MGI 0x40000000 /* 1 Magic pkt detect indication */ 134 #define MEMAC_IMASK_TSECC_ER 0x20000000 /* 2 Timestamp FIFO ECC error evnt */ 135 #define MEMAC_IMASK_TECC_ER 0x02000000 /* 6 Transmit frame ECC error evnt */ 136 #define MEMAC_IMASK_RECC_ER 0x01000000 /* 7 Receive frame ECC error evnt */ 137 138 #define MEMAC_ALL_ERRS_IMASK \ 139 ((u32)(MEMAC_IMASK_TSECC_ER | \ 140 MEMAC_IMASK_TECC_ER | \ 141 MEMAC_IMASK_RECC_ER | \ 142 MEMAC_IMASK_MGI)) 143 144 #define MEMAC_IEVNT_PCS 0x80000000 /* PCS (XG). Link sync (G) */ 145 #define MEMAC_IEVNT_AN 0x40000000 /* Auto-negotiation */ 146 #define MEMAC_IEVNT_LT 0x20000000 /* Link Training/New page */ 147 #define MEMAC_IEVNT_MGI 0x00004000 /* Magic pkt detection */ 148 #define MEMAC_IEVNT_TS_ECC_ER 0x00002000 /* Timestamp FIFO ECC error*/ 149 #define MEMAC_IEVNT_RX_FIFO_OVFL 0x00001000 /* Rx FIFO overflow */ 150 #define MEMAC_IEVNT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */ 151 #define MEMAC_IEVNT_TX_FIFO_OVFL 0x00000400 /* Tx FIFO overflow */ 152 #define MEMAC_IEVNT_TX_ECC_ER 0x00000200 /* Tx frame ECC error */ 153 #define MEMAC_IEVNT_RX_ECC_ER 0x00000100 /* Rx frame ECC error */ 154 #define MEMAC_IEVNT_LI_FAULT 0x00000080 /* Link Interruption flt */ 155 #define MEMAC_IEVNT_RX_EMPTY 0x00000040 /* Rx FIFO empty */ 156 #define MEMAC_IEVNT_TX_EMPTY 0x00000020 /* Tx FIFO empty */ 157 #define MEMAC_IEVNT_RX_LOWP 0x00000010 /* Low Power Idle */ 158 #define MEMAC_IEVNT_PHY_LOS 0x00000004 /* Phy loss of signal */ 159 #define MEMAC_IEVNT_REM_FAULT 0x00000002 /* Remote fault (XGMII) */ 160 #define MEMAC_IEVNT_LOC_FAULT 0x00000001 /* Local fault (XGMII) */ 161 162 #define DEFAULT_PAUSE_QUANTA 0xf000 163 #define DEFAULT_FRAME_LENGTH 0x600 164 #define DEFAULT_TX_IPG_LENGTH 12 165 166 #define CLXY_PAUSE_QUANTA_CLX_PQNT 0x0000FFFF 167 #define CLXY_PAUSE_QUANTA_CLY_PQNT 0xFFFF0000 168 #define CLXY_PAUSE_THRESH_CLX_QTH 0x0000FFFF 169 #define CLXY_PAUSE_THRESH_CLY_QTH 0xFFFF0000 170 171 struct mac_addr { 172 /* Lower 32 bits of 48-bit MAC address */ 173 u32 mac_addr_l; 174 /* Upper 16 bits of 48-bit MAC address */ 175 u32 mac_addr_u; 176 }; 177 178 /* memory map */ 179 struct memac_regs { 180 u32 res0000[2]; /* General Control and Status */ 181 u32 command_config; /* 0x008 Ctrl and cfg */ 182 struct mac_addr mac_addr0; /* 0x00C-0x010 MAC_ADDR_0...1 */ 183 u32 maxfrm; /* 0x014 Max frame length */ 184 u32 res0018[1]; 185 u32 rx_fifo_sections; /* Receive FIFO configuration reg */ 186 u32 tx_fifo_sections; /* Transmit FIFO configuration reg */ 187 u32 res0024[2]; 188 u32 hashtable_ctrl; /* 0x02C Hash table control */ 189 u32 res0030[4]; 190 u32 ievent; /* 0x040 Interrupt event */ 191 u32 tx_ipg_length; /* 0x044 Transmitter inter-packet-gap */ 192 u32 res0048; 193 u32 imask; /* 0x04C Interrupt mask */ 194 u32 res0050; 195 u32 pause_quanta[4]; /* 0x054 Pause quanta */ 196 u32 pause_thresh[4]; /* 0x064 Pause quanta threshold */ 197 u32 rx_pause_status; /* 0x074 Receive pause status */ 198 u32 res0078[2]; 199 struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS];/* 0x80-0x0B4 mac padr */ 200 u32 lpwake_timer; /* 0x0B8 Low Power Wakeup Timer */ 201 u32 sleep_timer; /* 0x0BC Transmit EEE Low Power Timer */ 202 u32 res00c0[8]; 203 u32 statn_config; /* 0x0E0 Statistics configuration */ 204 u32 res00e4[7]; 205 /* Rx Statistics Counter */ 206 u32 reoct_l; 207 u32 reoct_u; 208 u32 roct_l; 209 u32 roct_u; 210 u32 raln_l; 211 u32 raln_u; 212 u32 rxpf_l; 213 u32 rxpf_u; 214 u32 rfrm_l; 215 u32 rfrm_u; 216 u32 rfcs_l; 217 u32 rfcs_u; 218 u32 rvlan_l; 219 u32 rvlan_u; 220 u32 rerr_l; 221 u32 rerr_u; 222 u32 ruca_l; 223 u32 ruca_u; 224 u32 rmca_l; 225 u32 rmca_u; 226 u32 rbca_l; 227 u32 rbca_u; 228 u32 rdrp_l; 229 u32 rdrp_u; 230 u32 rpkt_l; 231 u32 rpkt_u; 232 u32 rund_l; 233 u32 rund_u; 234 u32 r64_l; 235 u32 r64_u; 236 u32 r127_l; 237 u32 r127_u; 238 u32 r255_l; 239 u32 r255_u; 240 u32 r511_l; 241 u32 r511_u; 242 u32 r1023_l; 243 u32 r1023_u; 244 u32 r1518_l; 245 u32 r1518_u; 246 u32 r1519x_l; 247 u32 r1519x_u; 248 u32 rovr_l; 249 u32 rovr_u; 250 u32 rjbr_l; 251 u32 rjbr_u; 252 u32 rfrg_l; 253 u32 rfrg_u; 254 u32 rcnp_l; 255 u32 rcnp_u; 256 u32 rdrntp_l; 257 u32 rdrntp_u; 258 u32 res01d0[12]; 259 /* Tx Statistics Counter */ 260 u32 teoct_l; 261 u32 teoct_u; 262 u32 toct_l; 263 u32 toct_u; 264 u32 res0210[2]; 265 u32 txpf_l; 266 u32 txpf_u; 267 u32 tfrm_l; 268 u32 tfrm_u; 269 u32 tfcs_l; 270 u32 tfcs_u; 271 u32 tvlan_l; 272 u32 tvlan_u; 273 u32 terr_l; 274 u32 terr_u; 275 u32 tuca_l; 276 u32 tuca_u; 277 u32 tmca_l; 278 u32 tmca_u; 279 u32 tbca_l; 280 u32 tbca_u; 281 u32 res0258[2]; 282 u32 tpkt_l; 283 u32 tpkt_u; 284 u32 tund_l; 285 u32 tund_u; 286 u32 t64_l; 287 u32 t64_u; 288 u32 t127_l; 289 u32 t127_u; 290 u32 t255_l; 291 u32 t255_u; 292 u32 t511_l; 293 u32 t511_u; 294 u32 t1023_l; 295 u32 t1023_u; 296 u32 t1518_l; 297 u32 t1518_u; 298 u32 t1519x_l; 299 u32 t1519x_u; 300 u32 res02a8[6]; 301 u32 tcnp_l; 302 u32 tcnp_u; 303 u32 res02c8[14]; 304 /* Line Interface Control */ 305 u32 if_mode; /* 0x300 Interface Mode Control */ 306 u32 if_status; /* 0x304 Interface Status */ 307 u32 res0308[14]; 308 /* HiGig/2 */ 309 u32 hg_config; /* 0x340 Control and cfg */ 310 u32 res0344[3]; 311 u32 hg_pause_quanta; /* 0x350 Pause quanta */ 312 u32 res0354[3]; 313 u32 hg_pause_thresh; /* 0x360 Pause quanta threshold */ 314 u32 res0364[3]; 315 u32 hgrx_pause_status; /* 0x370 Receive pause status */ 316 u32 hg_fifos_status; /* 0x374 fifos status */ 317 u32 rhm; /* 0x378 rx messages counter */ 318 u32 thm; /* 0x37C tx messages counter */ 319 }; 320 321 struct memac_cfg { 322 bool reset_on_init; 323 bool pause_ignore; 324 bool promiscuous_mode_enable; 325 struct fixed_phy_status *fixed_link; 326 u16 max_frame_length; 327 u16 pause_quanta; 328 u32 tx_ipg_length; 329 }; 330 331 struct fman_mac { 332 /* Pointer to MAC memory mapped registers */ 333 struct memac_regs __iomem *regs; 334 /* MAC address of device */ 335 u64 addr; 336 /* Ethernet physical interface */ 337 phy_interface_t phy_if; 338 u16 max_speed; 339 void *dev_id; /* device cookie used by the exception cbs */ 340 fman_mac_exception_cb *exception_cb; 341 fman_mac_exception_cb *event_cb; 342 /* Pointer to driver's global address hash table */ 343 struct eth_hash_t *multicast_addr_hash; 344 /* Pointer to driver's individual address hash table */ 345 struct eth_hash_t *unicast_addr_hash; 346 u8 mac_id; 347 u32 exceptions; 348 struct memac_cfg *memac_drv_param; 349 void *fm; 350 struct fman_rev_info fm_rev_info; 351 bool basex_if; 352 struct phy_device *pcsphy; 353 }; 354 355 static void add_addr_in_paddr(struct memac_regs __iomem *regs, u8 *adr, 356 u8 paddr_num) 357 { 358 u32 tmp0, tmp1; 359 360 tmp0 = (u32)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24); 361 tmp1 = (u32)(adr[4] | adr[5] << 8); 362 363 if (paddr_num == 0) { 364 iowrite32be(tmp0, ®s->mac_addr0.mac_addr_l); 365 iowrite32be(tmp1, ®s->mac_addr0.mac_addr_u); 366 } else { 367 iowrite32be(tmp0, ®s->mac_addr[paddr_num - 1].mac_addr_l); 368 iowrite32be(tmp1, ®s->mac_addr[paddr_num - 1].mac_addr_u); 369 } 370 } 371 372 static int reset(struct memac_regs __iomem *regs) 373 { 374 u32 tmp; 375 int count; 376 377 tmp = ioread32be(®s->command_config); 378 379 tmp |= CMD_CFG_SW_RESET; 380 381 iowrite32be(tmp, ®s->command_config); 382 383 count = 100; 384 do { 385 udelay(1); 386 } while ((ioread32be(®s->command_config) & CMD_CFG_SW_RESET) && 387 --count); 388 389 if (count == 0) 390 return -EBUSY; 391 392 return 0; 393 } 394 395 static void set_exception(struct memac_regs __iomem *regs, u32 val, 396 bool enable) 397 { 398 u32 tmp; 399 400 tmp = ioread32be(®s->imask); 401 if (enable) 402 tmp |= val; 403 else 404 tmp &= ~val; 405 406 iowrite32be(tmp, ®s->imask); 407 } 408 409 static int init(struct memac_regs __iomem *regs, struct memac_cfg *cfg, 410 phy_interface_t phy_if, u16 speed, bool slow_10g_if, 411 u32 exceptions) 412 { 413 u32 tmp; 414 415 /* Config */ 416 tmp = 0; 417 if (cfg->promiscuous_mode_enable) 418 tmp |= CMD_CFG_PROMIS_EN; 419 if (cfg->pause_ignore) 420 tmp |= CMD_CFG_PAUSE_IGNORE; 421 422 /* Payload length check disable */ 423 tmp |= CMD_CFG_NO_LEN_CHK; 424 /* Enable padding of frames in transmit direction */ 425 tmp |= CMD_CFG_TX_PAD_EN; 426 427 tmp |= CMD_CFG_CRC_FWD; 428 429 iowrite32be(tmp, ®s->command_config); 430 431 /* Max Frame Length */ 432 iowrite32be((u32)cfg->max_frame_length, ®s->maxfrm); 433 434 /* Pause Time */ 435 iowrite32be((u32)cfg->pause_quanta, ®s->pause_quanta[0]); 436 iowrite32be((u32)0, ®s->pause_thresh[0]); 437 438 /* IF_MODE */ 439 tmp = 0; 440 switch (phy_if) { 441 case PHY_INTERFACE_MODE_XGMII: 442 tmp |= IF_MODE_XGMII; 443 break; 444 default: 445 tmp |= IF_MODE_GMII; 446 if (phy_if == PHY_INTERFACE_MODE_RGMII || 447 phy_if == PHY_INTERFACE_MODE_RGMII_ID || 448 phy_if == PHY_INTERFACE_MODE_RGMII_RXID || 449 phy_if == PHY_INTERFACE_MODE_RGMII_TXID) 450 tmp |= IF_MODE_RGMII | IF_MODE_RGMII_AUTO; 451 } 452 iowrite32be(tmp, ®s->if_mode); 453 454 /* TX_FIFO_SECTIONS */ 455 tmp = 0; 456 if (phy_if == PHY_INTERFACE_MODE_XGMII) { 457 if (slow_10g_if) { 458 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G | 459 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G); 460 } else { 461 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_10G | 462 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G); 463 } 464 } else { 465 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_1G | 466 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G); 467 } 468 iowrite32be(tmp, ®s->tx_fifo_sections); 469 470 /* clear all pending events and set-up interrupts */ 471 iowrite32be(0xffffffff, ®s->ievent); 472 set_exception(regs, exceptions, true); 473 474 return 0; 475 } 476 477 static void set_dflts(struct memac_cfg *cfg) 478 { 479 cfg->reset_on_init = false; 480 cfg->promiscuous_mode_enable = false; 481 cfg->pause_ignore = false; 482 cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH; 483 cfg->max_frame_length = DEFAULT_FRAME_LENGTH; 484 cfg->pause_quanta = DEFAULT_PAUSE_QUANTA; 485 } 486 487 static u32 get_mac_addr_hash_code(u64 eth_addr) 488 { 489 u64 mask1, mask2; 490 u32 xor_val = 0; 491 u8 i, j; 492 493 for (i = 0; i < 6; i++) { 494 mask1 = eth_addr & (u64)0x01; 495 eth_addr >>= 1; 496 497 for (j = 0; j < 7; j++) { 498 mask2 = eth_addr & (u64)0x01; 499 mask1 ^= mask2; 500 eth_addr >>= 1; 501 } 502 503 xor_val |= (mask1 << (5 - i)); 504 } 505 506 return xor_val; 507 } 508 509 static void setup_sgmii_internal_phy(struct fman_mac *memac, 510 struct fixed_phy_status *fixed_link) 511 { 512 u16 tmp_reg16; 513 514 if (WARN_ON(!memac->pcsphy)) 515 return; 516 517 /* SGMII mode */ 518 tmp_reg16 = IF_MODE_SGMII_EN; 519 if (!fixed_link) 520 /* AN enable */ 521 tmp_reg16 |= IF_MODE_USE_SGMII_AN; 522 else { 523 switch (fixed_link->speed) { 524 case 10: 525 /* For 10M: IF_MODE[SPEED_10M] = 0 */ 526 break; 527 case 100: 528 tmp_reg16 |= IF_MODE_SGMII_SPEED_100M; 529 break; 530 case 1000: /* fallthrough */ 531 default: 532 tmp_reg16 |= IF_MODE_SGMII_SPEED_1G; 533 break; 534 } 535 if (!fixed_link->duplex) 536 tmp_reg16 |= IF_MODE_SGMII_DUPLEX_HALF; 537 } 538 phy_write(memac->pcsphy, MDIO_SGMII_IF_MODE, tmp_reg16); 539 540 /* Device ability according to SGMII specification */ 541 tmp_reg16 = MDIO_SGMII_DEV_ABIL_SGMII_MODE; 542 phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16); 543 544 /* Adjust link timer for SGMII - 545 * According to Cisco SGMII specification the timer should be 1.6 ms. 546 * The link_timer register is configured in units of the clock. 547 * - When running as 1G SGMII, Serdes clock is 125 MHz, so 548 * unit = 1 / (125*10^6 Hz) = 8 ns. 549 * 1.6 ms in units of 8 ns = 1.6ms / 8ns = 2*10^5 = 0x30d40 550 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so 551 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns. 552 * 1.6 ms in units of 3.2 ns = 1.6ms / 3.2ns = 5*10^5 = 0x7a120. 553 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII, 554 * we always set up here a value of 2.5 SGMII. 555 */ 556 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H); 557 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L); 558 559 if (!fixed_link) 560 /* Restart AN */ 561 tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN; 562 else 563 /* AN disabled */ 564 tmp_reg16 = SGMII_CR_DEF_VAL & ~SGMII_CR_AN_EN; 565 phy_write(memac->pcsphy, 0x0, tmp_reg16); 566 } 567 568 static void setup_sgmii_internal_phy_base_x(struct fman_mac *memac) 569 { 570 u16 tmp_reg16; 571 572 /* AN Device capability */ 573 tmp_reg16 = MDIO_SGMII_DEV_ABIL_BASEX_MODE; 574 phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16); 575 576 /* Adjust link timer for SGMII - 577 * For Serdes 1000BaseX auto-negotiation the timer should be 10 ms. 578 * The link_timer register is configured in units of the clock. 579 * - When running as 1G SGMII, Serdes clock is 125 MHz, so 580 * unit = 1 / (125*10^6 Hz) = 8 ns. 581 * 10 ms in units of 8 ns = 10ms / 8ns = 1250000 = 0x1312d0 582 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so 583 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns. 584 * 10 ms in units of 3.2 ns = 10ms / 3.2ns = 3125000 = 0x2faf08. 585 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII, 586 * we always set up here a value of 2.5 SGMII. 587 */ 588 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H_BASEX); 589 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L_BASEX); 590 591 /* Restart AN */ 592 tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN; 593 phy_write(memac->pcsphy, 0x0, tmp_reg16); 594 } 595 596 static int check_init_parameters(struct fman_mac *memac) 597 { 598 if (memac->addr == 0) { 599 pr_err("Ethernet MAC must have a valid MAC address\n"); 600 return -EINVAL; 601 } 602 if (!memac->exception_cb) { 603 pr_err("Uninitialized exception handler\n"); 604 return -EINVAL; 605 } 606 if (!memac->event_cb) { 607 pr_warn("Uninitialize event handler\n"); 608 return -EINVAL; 609 } 610 611 return 0; 612 } 613 614 static int get_exception_flag(enum fman_mac_exceptions exception) 615 { 616 u32 bit_mask; 617 618 switch (exception) { 619 case FM_MAC_EX_10G_TX_ECC_ER: 620 bit_mask = MEMAC_IMASK_TECC_ER; 621 break; 622 case FM_MAC_EX_10G_RX_ECC_ER: 623 bit_mask = MEMAC_IMASK_RECC_ER; 624 break; 625 case FM_MAC_EX_TS_FIFO_ECC_ERR: 626 bit_mask = MEMAC_IMASK_TSECC_ER; 627 break; 628 case FM_MAC_EX_MAGIC_PACKET_INDICATION: 629 bit_mask = MEMAC_IMASK_MGI; 630 break; 631 default: 632 bit_mask = 0; 633 break; 634 } 635 636 return bit_mask; 637 } 638 639 static void memac_err_exception(void *handle) 640 { 641 struct fman_mac *memac = (struct fman_mac *)handle; 642 struct memac_regs __iomem *regs = memac->regs; 643 u32 event, imask; 644 645 event = ioread32be(®s->ievent); 646 imask = ioread32be(®s->imask); 647 648 /* Imask include both error and notification/event bits. 649 * Leaving only error bits enabled by imask. 650 * The imask error bits are shifted by 16 bits offset from 651 * their corresponding location in the ievent - hence the >> 16 652 */ 653 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16); 654 655 iowrite32be(event, ®s->ievent); 656 657 if (event & MEMAC_IEVNT_TS_ECC_ER) 658 memac->exception_cb(memac->dev_id, FM_MAC_EX_TS_FIFO_ECC_ERR); 659 if (event & MEMAC_IEVNT_TX_ECC_ER) 660 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_TX_ECC_ER); 661 if (event & MEMAC_IEVNT_RX_ECC_ER) 662 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_RX_ECC_ER); 663 } 664 665 static void memac_exception(void *handle) 666 { 667 struct fman_mac *memac = (struct fman_mac *)handle; 668 struct memac_regs __iomem *regs = memac->regs; 669 u32 event, imask; 670 671 event = ioread32be(®s->ievent); 672 imask = ioread32be(®s->imask); 673 674 /* Imask include both error and notification/event bits. 675 * Leaving only error bits enabled by imask. 676 * The imask error bits are shifted by 16 bits offset from 677 * their corresponding location in the ievent - hence the >> 16 678 */ 679 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16); 680 681 iowrite32be(event, ®s->ievent); 682 683 if (event & MEMAC_IEVNT_MGI) 684 memac->exception_cb(memac->dev_id, 685 FM_MAC_EX_MAGIC_PACKET_INDICATION); 686 } 687 688 static void free_init_resources(struct fman_mac *memac) 689 { 690 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 691 FMAN_INTR_TYPE_ERR); 692 693 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 694 FMAN_INTR_TYPE_NORMAL); 695 696 /* release the driver's group hash table */ 697 free_hash_table(memac->multicast_addr_hash); 698 memac->multicast_addr_hash = NULL; 699 700 /* release the driver's individual hash table */ 701 free_hash_table(memac->unicast_addr_hash); 702 memac->unicast_addr_hash = NULL; 703 } 704 705 static bool is_init_done(struct memac_cfg *memac_drv_params) 706 { 707 /* Checks if mEMAC driver parameters were initialized */ 708 if (!memac_drv_params) 709 return true; 710 711 return false; 712 } 713 714 int memac_enable(struct fman_mac *memac, enum comm_mode mode) 715 { 716 struct memac_regs __iomem *regs = memac->regs; 717 u32 tmp; 718 719 if (!is_init_done(memac->memac_drv_param)) 720 return -EINVAL; 721 722 tmp = ioread32be(®s->command_config); 723 if (mode & COMM_MODE_RX) 724 tmp |= CMD_CFG_RX_EN; 725 if (mode & COMM_MODE_TX) 726 tmp |= CMD_CFG_TX_EN; 727 728 iowrite32be(tmp, ®s->command_config); 729 730 return 0; 731 } 732 733 int memac_disable(struct fman_mac *memac, enum comm_mode mode) 734 { 735 struct memac_regs __iomem *regs = memac->regs; 736 u32 tmp; 737 738 if (!is_init_done(memac->memac_drv_param)) 739 return -EINVAL; 740 741 tmp = ioread32be(®s->command_config); 742 if (mode & COMM_MODE_RX) 743 tmp &= ~CMD_CFG_RX_EN; 744 if (mode & COMM_MODE_TX) 745 tmp &= ~CMD_CFG_TX_EN; 746 747 iowrite32be(tmp, ®s->command_config); 748 749 return 0; 750 } 751 752 int memac_set_promiscuous(struct fman_mac *memac, bool new_val) 753 { 754 struct memac_regs __iomem *regs = memac->regs; 755 u32 tmp; 756 757 if (!is_init_done(memac->memac_drv_param)) 758 return -EINVAL; 759 760 tmp = ioread32be(®s->command_config); 761 if (new_val) 762 tmp |= CMD_CFG_PROMIS_EN; 763 else 764 tmp &= ~CMD_CFG_PROMIS_EN; 765 766 iowrite32be(tmp, ®s->command_config); 767 768 return 0; 769 } 770 771 int memac_adjust_link(struct fman_mac *memac, u16 speed) 772 { 773 struct memac_regs __iomem *regs = memac->regs; 774 u32 tmp; 775 776 if (!is_init_done(memac->memac_drv_param)) 777 return -EINVAL; 778 779 tmp = ioread32be(®s->if_mode); 780 781 /* Set full duplex */ 782 tmp &= ~IF_MODE_HD; 783 784 if (memac->phy_if == PHY_INTERFACE_MODE_RGMII) { 785 /* Configure RGMII in manual mode */ 786 tmp &= ~IF_MODE_RGMII_AUTO; 787 tmp &= ~IF_MODE_RGMII_SP_MASK; 788 /* Full duplex */ 789 tmp |= IF_MODE_RGMII_FD; 790 791 switch (speed) { 792 case SPEED_1000: 793 tmp |= IF_MODE_RGMII_1000; 794 break; 795 case SPEED_100: 796 tmp |= IF_MODE_RGMII_100; 797 break; 798 case SPEED_10: 799 tmp |= IF_MODE_RGMII_10; 800 break; 801 default: 802 break; 803 } 804 } 805 806 iowrite32be(tmp, ®s->if_mode); 807 808 return 0; 809 } 810 811 int memac_cfg_max_frame_len(struct fman_mac *memac, u16 new_val) 812 { 813 if (is_init_done(memac->memac_drv_param)) 814 return -EINVAL; 815 816 memac->memac_drv_param->max_frame_length = new_val; 817 818 return 0; 819 } 820 821 int memac_cfg_reset_on_init(struct fman_mac *memac, bool enable) 822 { 823 if (is_init_done(memac->memac_drv_param)) 824 return -EINVAL; 825 826 memac->memac_drv_param->reset_on_init = enable; 827 828 return 0; 829 } 830 831 int memac_cfg_fixed_link(struct fman_mac *memac, 832 struct fixed_phy_status *fixed_link) 833 { 834 if (is_init_done(memac->memac_drv_param)) 835 return -EINVAL; 836 837 memac->memac_drv_param->fixed_link = fixed_link; 838 839 return 0; 840 } 841 842 int memac_set_tx_pause_frames(struct fman_mac *memac, u8 priority, 843 u16 pause_time, u16 thresh_time) 844 { 845 struct memac_regs __iomem *regs = memac->regs; 846 u32 tmp; 847 848 if (!is_init_done(memac->memac_drv_param)) 849 return -EINVAL; 850 851 tmp = ioread32be(®s->tx_fifo_sections); 852 853 GET_TX_EMPTY_DEFAULT_VALUE(tmp); 854 iowrite32be(tmp, ®s->tx_fifo_sections); 855 856 tmp = ioread32be(®s->command_config); 857 tmp &= ~CMD_CFG_PFC_MODE; 858 priority = 0; 859 860 iowrite32be(tmp, ®s->command_config); 861 862 tmp = ioread32be(®s->pause_quanta[priority / 2]); 863 if (priority % 2) 864 tmp &= CLXY_PAUSE_QUANTA_CLX_PQNT; 865 else 866 tmp &= CLXY_PAUSE_QUANTA_CLY_PQNT; 867 tmp |= ((u32)pause_time << (16 * (priority % 2))); 868 iowrite32be(tmp, ®s->pause_quanta[priority / 2]); 869 870 tmp = ioread32be(®s->pause_thresh[priority / 2]); 871 if (priority % 2) 872 tmp &= CLXY_PAUSE_THRESH_CLX_QTH; 873 else 874 tmp &= CLXY_PAUSE_THRESH_CLY_QTH; 875 tmp |= ((u32)thresh_time << (16 * (priority % 2))); 876 iowrite32be(tmp, ®s->pause_thresh[priority / 2]); 877 878 return 0; 879 } 880 881 int memac_accept_rx_pause_frames(struct fman_mac *memac, bool en) 882 { 883 struct memac_regs __iomem *regs = memac->regs; 884 u32 tmp; 885 886 if (!is_init_done(memac->memac_drv_param)) 887 return -EINVAL; 888 889 tmp = ioread32be(®s->command_config); 890 if (en) 891 tmp &= ~CMD_CFG_PAUSE_IGNORE; 892 else 893 tmp |= CMD_CFG_PAUSE_IGNORE; 894 895 iowrite32be(tmp, ®s->command_config); 896 897 return 0; 898 } 899 900 int memac_modify_mac_address(struct fman_mac *memac, enet_addr_t *enet_addr) 901 { 902 if (!is_init_done(memac->memac_drv_param)) 903 return -EINVAL; 904 905 add_addr_in_paddr(memac->regs, (u8 *)(*enet_addr), 0); 906 907 return 0; 908 } 909 910 int memac_add_hash_mac_address(struct fman_mac *memac, enet_addr_t *eth_addr) 911 { 912 struct memac_regs __iomem *regs = memac->regs; 913 struct eth_hash_entry *hash_entry; 914 u32 hash; 915 u64 addr; 916 917 if (!is_init_done(memac->memac_drv_param)) 918 return -EINVAL; 919 920 addr = ENET_ADDR_TO_UINT64(*eth_addr); 921 922 if (!(addr & GROUP_ADDRESS)) { 923 /* Unicast addresses not supported in hash */ 924 pr_err("Unicast Address\n"); 925 return -EINVAL; 926 } 927 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK; 928 929 /* Create element to be added to the driver hash table */ 930 hash_entry = kmalloc(sizeof(*hash_entry), GFP_KERNEL); 931 if (!hash_entry) 932 return -ENOMEM; 933 hash_entry->addr = addr; 934 INIT_LIST_HEAD(&hash_entry->node); 935 936 list_add_tail(&hash_entry->node, 937 &memac->multicast_addr_hash->lsts[hash]); 938 iowrite32be(hash | HASH_CTRL_MCAST_EN, ®s->hashtable_ctrl); 939 940 return 0; 941 } 942 943 int memac_del_hash_mac_address(struct fman_mac *memac, enet_addr_t *eth_addr) 944 { 945 struct memac_regs __iomem *regs = memac->regs; 946 struct eth_hash_entry *hash_entry = NULL; 947 struct list_head *pos; 948 u32 hash; 949 u64 addr; 950 951 if (!is_init_done(memac->memac_drv_param)) 952 return -EINVAL; 953 954 addr = ENET_ADDR_TO_UINT64(*eth_addr); 955 956 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK; 957 958 list_for_each(pos, &memac->multicast_addr_hash->lsts[hash]) { 959 hash_entry = ETH_HASH_ENTRY_OBJ(pos); 960 if (hash_entry->addr == addr) { 961 list_del_init(&hash_entry->node); 962 kfree(hash_entry); 963 break; 964 } 965 } 966 if (list_empty(&memac->multicast_addr_hash->lsts[hash])) 967 iowrite32be(hash & ~HASH_CTRL_MCAST_EN, ®s->hashtable_ctrl); 968 969 return 0; 970 } 971 972 int memac_set_exception(struct fman_mac *memac, 973 enum fman_mac_exceptions exception, bool enable) 974 { 975 u32 bit_mask = 0; 976 977 if (!is_init_done(memac->memac_drv_param)) 978 return -EINVAL; 979 980 bit_mask = get_exception_flag(exception); 981 if (bit_mask) { 982 if (enable) 983 memac->exceptions |= bit_mask; 984 else 985 memac->exceptions &= ~bit_mask; 986 } else { 987 pr_err("Undefined exception\n"); 988 return -EINVAL; 989 } 990 set_exception(memac->regs, bit_mask, enable); 991 992 return 0; 993 } 994 995 int memac_init(struct fman_mac *memac) 996 { 997 struct memac_cfg *memac_drv_param; 998 u8 i; 999 enet_addr_t eth_addr; 1000 bool slow_10g_if = false; 1001 struct fixed_phy_status *fixed_link; 1002 int err; 1003 u32 reg32 = 0; 1004 1005 if (is_init_done(memac->memac_drv_param)) 1006 return -EINVAL; 1007 1008 err = check_init_parameters(memac); 1009 if (err) 1010 return err; 1011 1012 memac_drv_param = memac->memac_drv_param; 1013 1014 if (memac->fm_rev_info.major == 6 && memac->fm_rev_info.minor == 4) 1015 slow_10g_if = true; 1016 1017 /* First, reset the MAC if desired. */ 1018 if (memac_drv_param->reset_on_init) { 1019 err = reset(memac->regs); 1020 if (err) { 1021 pr_err("mEMAC reset failed\n"); 1022 return err; 1023 } 1024 } 1025 1026 /* MAC Address */ 1027 MAKE_ENET_ADDR_FROM_UINT64(memac->addr, eth_addr); 1028 add_addr_in_paddr(memac->regs, (u8 *)eth_addr, 0); 1029 1030 fixed_link = memac_drv_param->fixed_link; 1031 1032 init(memac->regs, memac->memac_drv_param, memac->phy_if, 1033 memac->max_speed, slow_10g_if, memac->exceptions); 1034 1035 /* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 errata workaround 1036 * Exists only in FMan 6.0 and 6.3. 1037 */ 1038 if ((memac->fm_rev_info.major == 6) && 1039 ((memac->fm_rev_info.minor == 0) || 1040 (memac->fm_rev_info.minor == 3))) { 1041 /* MAC strips CRC from received frames - this workaround 1042 * should decrease the likelihood of bug appearance 1043 */ 1044 reg32 = ioread32be(&memac->regs->command_config); 1045 reg32 &= ~CMD_CFG_CRC_FWD; 1046 iowrite32be(reg32, &memac->regs->command_config); 1047 } 1048 1049 if (memac->phy_if == PHY_INTERFACE_MODE_SGMII) { 1050 /* Configure internal SGMII PHY */ 1051 if (memac->basex_if) 1052 setup_sgmii_internal_phy_base_x(memac); 1053 else 1054 setup_sgmii_internal_phy(memac, fixed_link); 1055 } else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII) { 1056 /* Configure 4 internal SGMII PHYs */ 1057 for (i = 0; i < 4; i++) { 1058 u8 qsmgii_phy_addr, phy_addr; 1059 /* QSGMII PHY address occupies 3 upper bits of 5-bit 1060 * phy_address; the lower 2 bits are used to extend 1061 * register address space and access each one of 4 1062 * ports inside QSGMII. 1063 */ 1064 phy_addr = memac->pcsphy->mdio.addr; 1065 qsmgii_phy_addr = (u8)((phy_addr << 2) | i); 1066 memac->pcsphy->mdio.addr = qsmgii_phy_addr; 1067 if (memac->basex_if) 1068 setup_sgmii_internal_phy_base_x(memac); 1069 else 1070 setup_sgmii_internal_phy(memac, fixed_link); 1071 1072 memac->pcsphy->mdio.addr = phy_addr; 1073 } 1074 } 1075 1076 /* Max Frame Length */ 1077 err = fman_set_mac_max_frame(memac->fm, memac->mac_id, 1078 memac_drv_param->max_frame_length); 1079 if (err) { 1080 pr_err("settings Mac max frame length is FAILED\n"); 1081 return err; 1082 } 1083 1084 memac->multicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE); 1085 if (!memac->multicast_addr_hash) { 1086 free_init_resources(memac); 1087 pr_err("allocation hash table is FAILED\n"); 1088 return -ENOMEM; 1089 } 1090 1091 memac->unicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE); 1092 if (!memac->unicast_addr_hash) { 1093 free_init_resources(memac); 1094 pr_err("allocation hash table is FAILED\n"); 1095 return -ENOMEM; 1096 } 1097 1098 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 1099 FMAN_INTR_TYPE_ERR, memac_err_exception, memac); 1100 1101 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 1102 FMAN_INTR_TYPE_NORMAL, memac_exception, memac); 1103 1104 kfree(memac_drv_param); 1105 memac->memac_drv_param = NULL; 1106 1107 return 0; 1108 } 1109 1110 int memac_free(struct fman_mac *memac) 1111 { 1112 free_init_resources(memac); 1113 1114 if (memac->pcsphy) 1115 put_device(&memac->pcsphy->mdio.dev); 1116 1117 kfree(memac->memac_drv_param); 1118 kfree(memac); 1119 1120 return 0; 1121 } 1122 1123 struct fman_mac *memac_config(struct fman_mac_params *params) 1124 { 1125 struct fman_mac *memac; 1126 struct memac_cfg *memac_drv_param; 1127 void __iomem *base_addr; 1128 1129 base_addr = params->base_addr; 1130 /* allocate memory for the m_emac data structure */ 1131 memac = kzalloc(sizeof(*memac), GFP_KERNEL); 1132 if (!memac) 1133 return NULL; 1134 1135 /* allocate memory for the m_emac driver parameters data structure */ 1136 memac_drv_param = kzalloc(sizeof(*memac_drv_param), GFP_KERNEL); 1137 if (!memac_drv_param) { 1138 memac_free(memac); 1139 return NULL; 1140 } 1141 1142 /* Plant parameter structure pointer */ 1143 memac->memac_drv_param = memac_drv_param; 1144 1145 set_dflts(memac_drv_param); 1146 1147 memac->addr = ENET_ADDR_TO_UINT64(params->addr); 1148 1149 memac->regs = base_addr; 1150 memac->max_speed = params->max_speed; 1151 memac->phy_if = params->phy_if; 1152 memac->mac_id = params->mac_id; 1153 memac->exceptions = (MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER | 1154 MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI); 1155 memac->exception_cb = params->exception_cb; 1156 memac->event_cb = params->event_cb; 1157 memac->dev_id = params->dev_id; 1158 memac->fm = params->fm; 1159 memac->basex_if = params->basex_if; 1160 1161 /* Save FMan revision */ 1162 fman_get_revision(memac->fm, &memac->fm_rev_info); 1163 1164 if (memac->phy_if == PHY_INTERFACE_MODE_SGMII || 1165 memac->phy_if == PHY_INTERFACE_MODE_QSGMII) { 1166 if (!params->internal_phy_node) { 1167 pr_err("PCS PHY node is not available\n"); 1168 memac_free(memac); 1169 return NULL; 1170 } 1171 1172 memac->pcsphy = of_phy_find_device(params->internal_phy_node); 1173 if (!memac->pcsphy) { 1174 pr_err("of_phy_find_device (PCS PHY) failed\n"); 1175 memac_free(memac); 1176 return NULL; 1177 } 1178 } 1179 1180 return memac; 1181 } 1182