1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later 2 /* 3 * Copyright 2008 - 2015 Freescale Semiconductor Inc. 4 */ 5 6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 7 8 #include "fman_memac.h" 9 #include "fman.h" 10 #include "mac.h" 11 12 #include <linux/slab.h> 13 #include <linux/io.h> 14 #include <linux/phy.h> 15 #include <linux/phy_fixed.h> 16 #include <linux/of_mdio.h> 17 18 /* PCS registers */ 19 #define MDIO_SGMII_CR 0x00 20 #define MDIO_SGMII_DEV_ABIL_SGMII 0x04 21 #define MDIO_SGMII_LINK_TMR_L 0x12 22 #define MDIO_SGMII_LINK_TMR_H 0x13 23 #define MDIO_SGMII_IF_MODE 0x14 24 25 /* SGMII Control defines */ 26 #define SGMII_CR_AN_EN 0x1000 27 #define SGMII_CR_RESTART_AN 0x0200 28 #define SGMII_CR_FD 0x0100 29 #define SGMII_CR_SPEED_SEL1_1G 0x0040 30 #define SGMII_CR_DEF_VAL (SGMII_CR_AN_EN | SGMII_CR_FD | \ 31 SGMII_CR_SPEED_SEL1_1G) 32 33 /* SGMII Device Ability for SGMII defines */ 34 #define MDIO_SGMII_DEV_ABIL_SGMII_MODE 0x4001 35 #define MDIO_SGMII_DEV_ABIL_BASEX_MODE 0x01A0 36 37 /* Link timer define */ 38 #define LINK_TMR_L 0xa120 39 #define LINK_TMR_H 0x0007 40 #define LINK_TMR_L_BASEX 0xaf08 41 #define LINK_TMR_H_BASEX 0x002f 42 43 /* SGMII IF Mode defines */ 44 #define IF_MODE_USE_SGMII_AN 0x0002 45 #define IF_MODE_SGMII_EN 0x0001 46 #define IF_MODE_SGMII_SPEED_100M 0x0004 47 #define IF_MODE_SGMII_SPEED_1G 0x0008 48 #define IF_MODE_SGMII_DUPLEX_HALF 0x0010 49 50 /* Num of additional exact match MAC adr regs */ 51 #define MEMAC_NUM_OF_PADDRS 7 52 53 /* Control and Configuration Register (COMMAND_CONFIG) */ 54 #define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */ 55 #define CMD_CFG_TX_LOWP_ENA 0x00800000 /* 08 Tx Low Power Idle Enable */ 56 #define CMD_CFG_PFC_MODE 0x00080000 /* 12 Enable PFC */ 57 #define CMD_CFG_NO_LEN_CHK 0x00020000 /* 14 Payload length check disable */ 58 #define CMD_CFG_SW_RESET 0x00001000 /* 19 S/W Reset, self clearing bit */ 59 #define CMD_CFG_TX_PAD_EN 0x00000800 /* 20 Enable Tx padding of frames */ 60 #define CMD_CFG_PAUSE_IGNORE 0x00000100 /* 23 Ignore Pause frame quanta */ 61 #define CMD_CFG_CRC_FWD 0x00000040 /* 25 Terminate/frwd CRC of frames */ 62 #define CMD_CFG_PAD_EN 0x00000020 /* 26 Frame padding removal */ 63 #define CMD_CFG_PROMIS_EN 0x00000010 /* 27 Promiscuous operation enable */ 64 #define CMD_CFG_RX_EN 0x00000002 /* 30 MAC receive path enable */ 65 #define CMD_CFG_TX_EN 0x00000001 /* 31 MAC transmit path enable */ 66 67 /* Transmit FIFO Sections Register (TX_FIFO_SECTIONS) */ 68 #define TX_FIFO_SECTIONS_TX_EMPTY_MASK 0xFFFF0000 69 #define TX_FIFO_SECTIONS_TX_AVAIL_MASK 0x0000FFFF 70 #define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G 0x00400000 71 #define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G 0x00100000 72 #define TX_FIFO_SECTIONS_TX_AVAIL_10G 0x00000019 73 #define TX_FIFO_SECTIONS_TX_AVAIL_1G 0x00000020 74 #define TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G 0x00000060 75 76 #define GET_TX_EMPTY_DEFAULT_VALUE(_val) \ 77 do { \ 78 _val &= ~TX_FIFO_SECTIONS_TX_EMPTY_MASK; \ 79 ((_val == TX_FIFO_SECTIONS_TX_AVAIL_10G) ? \ 80 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G) :\ 81 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G));\ 82 } while (0) 83 84 /* Interface Mode Register (IF_MODE) */ 85 86 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */ 87 #define IF_MODE_10G 0x00000000 /* 30-31 10G interface */ 88 #define IF_MODE_MII 0x00000001 /* 30-31 MII interface */ 89 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */ 90 #define IF_MODE_RGMII 0x00000004 91 #define IF_MODE_RGMII_AUTO 0x00008000 92 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */ 93 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */ 94 #define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */ 95 #define IF_MODE_RGMII_SP_MASK 0x00006000 /* Setsp mask bits */ 96 #define IF_MODE_RGMII_FD 0x00001000 /* Full duplex RGMII */ 97 #define IF_MODE_HD 0x00000040 /* Half duplex operation */ 98 99 /* Hash table Control Register (HASHTABLE_CTRL) */ 100 #define HASH_CTRL_MCAST_EN 0x00000100 101 /* 26-31 Hash table address code */ 102 #define HASH_CTRL_ADDR_MASK 0x0000003F 103 /* MAC mcast indication */ 104 #define GROUP_ADDRESS 0x0000010000000000LL 105 #define HASH_TABLE_SIZE 64 /* Hash tbl size */ 106 107 /* Interrupt Mask Register (IMASK) */ 108 #define MEMAC_IMASK_MGI 0x40000000 /* 1 Magic pkt detect indication */ 109 #define MEMAC_IMASK_TSECC_ER 0x20000000 /* 2 Timestamp FIFO ECC error evnt */ 110 #define MEMAC_IMASK_TECC_ER 0x02000000 /* 6 Transmit frame ECC error evnt */ 111 #define MEMAC_IMASK_RECC_ER 0x01000000 /* 7 Receive frame ECC error evnt */ 112 113 #define MEMAC_ALL_ERRS_IMASK \ 114 ((u32)(MEMAC_IMASK_TSECC_ER | \ 115 MEMAC_IMASK_TECC_ER | \ 116 MEMAC_IMASK_RECC_ER | \ 117 MEMAC_IMASK_MGI)) 118 119 #define MEMAC_IEVNT_PCS 0x80000000 /* PCS (XG). Link sync (G) */ 120 #define MEMAC_IEVNT_AN 0x40000000 /* Auto-negotiation */ 121 #define MEMAC_IEVNT_LT 0x20000000 /* Link Training/New page */ 122 #define MEMAC_IEVNT_MGI 0x00004000 /* Magic pkt detection */ 123 #define MEMAC_IEVNT_TS_ECC_ER 0x00002000 /* Timestamp FIFO ECC error*/ 124 #define MEMAC_IEVNT_RX_FIFO_OVFL 0x00001000 /* Rx FIFO overflow */ 125 #define MEMAC_IEVNT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */ 126 #define MEMAC_IEVNT_TX_FIFO_OVFL 0x00000400 /* Tx FIFO overflow */ 127 #define MEMAC_IEVNT_TX_ECC_ER 0x00000200 /* Tx frame ECC error */ 128 #define MEMAC_IEVNT_RX_ECC_ER 0x00000100 /* Rx frame ECC error */ 129 #define MEMAC_IEVNT_LI_FAULT 0x00000080 /* Link Interruption flt */ 130 #define MEMAC_IEVNT_RX_EMPTY 0x00000040 /* Rx FIFO empty */ 131 #define MEMAC_IEVNT_TX_EMPTY 0x00000020 /* Tx FIFO empty */ 132 #define MEMAC_IEVNT_RX_LOWP 0x00000010 /* Low Power Idle */ 133 #define MEMAC_IEVNT_PHY_LOS 0x00000004 /* Phy loss of signal */ 134 #define MEMAC_IEVNT_REM_FAULT 0x00000002 /* Remote fault (XGMII) */ 135 #define MEMAC_IEVNT_LOC_FAULT 0x00000001 /* Local fault (XGMII) */ 136 137 #define DEFAULT_PAUSE_QUANTA 0xf000 138 #define DEFAULT_FRAME_LENGTH 0x600 139 #define DEFAULT_TX_IPG_LENGTH 12 140 141 #define CLXY_PAUSE_QUANTA_CLX_PQNT 0x0000FFFF 142 #define CLXY_PAUSE_QUANTA_CLY_PQNT 0xFFFF0000 143 #define CLXY_PAUSE_THRESH_CLX_QTH 0x0000FFFF 144 #define CLXY_PAUSE_THRESH_CLY_QTH 0xFFFF0000 145 146 struct mac_addr { 147 /* Lower 32 bits of 48-bit MAC address */ 148 u32 mac_addr_l; 149 /* Upper 16 bits of 48-bit MAC address */ 150 u32 mac_addr_u; 151 }; 152 153 /* memory map */ 154 struct memac_regs { 155 u32 res0000[2]; /* General Control and Status */ 156 u32 command_config; /* 0x008 Ctrl and cfg */ 157 struct mac_addr mac_addr0; /* 0x00C-0x010 MAC_ADDR_0...1 */ 158 u32 maxfrm; /* 0x014 Max frame length */ 159 u32 res0018[1]; 160 u32 rx_fifo_sections; /* Receive FIFO configuration reg */ 161 u32 tx_fifo_sections; /* Transmit FIFO configuration reg */ 162 u32 res0024[2]; 163 u32 hashtable_ctrl; /* 0x02C Hash table control */ 164 u32 res0030[4]; 165 u32 ievent; /* 0x040 Interrupt event */ 166 u32 tx_ipg_length; /* 0x044 Transmitter inter-packet-gap */ 167 u32 res0048; 168 u32 imask; /* 0x04C Interrupt mask */ 169 u32 res0050; 170 u32 pause_quanta[4]; /* 0x054 Pause quanta */ 171 u32 pause_thresh[4]; /* 0x064 Pause quanta threshold */ 172 u32 rx_pause_status; /* 0x074 Receive pause status */ 173 u32 res0078[2]; 174 struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS];/* 0x80-0x0B4 mac padr */ 175 u32 lpwake_timer; /* 0x0B8 Low Power Wakeup Timer */ 176 u32 sleep_timer; /* 0x0BC Transmit EEE Low Power Timer */ 177 u32 res00c0[8]; 178 u32 statn_config; /* 0x0E0 Statistics configuration */ 179 u32 res00e4[7]; 180 /* Rx Statistics Counter */ 181 u32 reoct_l; 182 u32 reoct_u; 183 u32 roct_l; 184 u32 roct_u; 185 u32 raln_l; 186 u32 raln_u; 187 u32 rxpf_l; 188 u32 rxpf_u; 189 u32 rfrm_l; 190 u32 rfrm_u; 191 u32 rfcs_l; 192 u32 rfcs_u; 193 u32 rvlan_l; 194 u32 rvlan_u; 195 u32 rerr_l; 196 u32 rerr_u; 197 u32 ruca_l; 198 u32 ruca_u; 199 u32 rmca_l; 200 u32 rmca_u; 201 u32 rbca_l; 202 u32 rbca_u; 203 u32 rdrp_l; 204 u32 rdrp_u; 205 u32 rpkt_l; 206 u32 rpkt_u; 207 u32 rund_l; 208 u32 rund_u; 209 u32 r64_l; 210 u32 r64_u; 211 u32 r127_l; 212 u32 r127_u; 213 u32 r255_l; 214 u32 r255_u; 215 u32 r511_l; 216 u32 r511_u; 217 u32 r1023_l; 218 u32 r1023_u; 219 u32 r1518_l; 220 u32 r1518_u; 221 u32 r1519x_l; 222 u32 r1519x_u; 223 u32 rovr_l; 224 u32 rovr_u; 225 u32 rjbr_l; 226 u32 rjbr_u; 227 u32 rfrg_l; 228 u32 rfrg_u; 229 u32 rcnp_l; 230 u32 rcnp_u; 231 u32 rdrntp_l; 232 u32 rdrntp_u; 233 u32 res01d0[12]; 234 /* Tx Statistics Counter */ 235 u32 teoct_l; 236 u32 teoct_u; 237 u32 toct_l; 238 u32 toct_u; 239 u32 res0210[2]; 240 u32 txpf_l; 241 u32 txpf_u; 242 u32 tfrm_l; 243 u32 tfrm_u; 244 u32 tfcs_l; 245 u32 tfcs_u; 246 u32 tvlan_l; 247 u32 tvlan_u; 248 u32 terr_l; 249 u32 terr_u; 250 u32 tuca_l; 251 u32 tuca_u; 252 u32 tmca_l; 253 u32 tmca_u; 254 u32 tbca_l; 255 u32 tbca_u; 256 u32 res0258[2]; 257 u32 tpkt_l; 258 u32 tpkt_u; 259 u32 tund_l; 260 u32 tund_u; 261 u32 t64_l; 262 u32 t64_u; 263 u32 t127_l; 264 u32 t127_u; 265 u32 t255_l; 266 u32 t255_u; 267 u32 t511_l; 268 u32 t511_u; 269 u32 t1023_l; 270 u32 t1023_u; 271 u32 t1518_l; 272 u32 t1518_u; 273 u32 t1519x_l; 274 u32 t1519x_u; 275 u32 res02a8[6]; 276 u32 tcnp_l; 277 u32 tcnp_u; 278 u32 res02c8[14]; 279 /* Line Interface Control */ 280 u32 if_mode; /* 0x300 Interface Mode Control */ 281 u32 if_status; /* 0x304 Interface Status */ 282 u32 res0308[14]; 283 /* HiGig/2 */ 284 u32 hg_config; /* 0x340 Control and cfg */ 285 u32 res0344[3]; 286 u32 hg_pause_quanta; /* 0x350 Pause quanta */ 287 u32 res0354[3]; 288 u32 hg_pause_thresh; /* 0x360 Pause quanta threshold */ 289 u32 res0364[3]; 290 u32 hgrx_pause_status; /* 0x370 Receive pause status */ 291 u32 hg_fifos_status; /* 0x374 fifos status */ 292 u32 rhm; /* 0x378 rx messages counter */ 293 u32 thm; /* 0x37C tx messages counter */ 294 }; 295 296 struct memac_cfg { 297 bool reset_on_init; 298 bool pause_ignore; 299 bool promiscuous_mode_enable; 300 struct fixed_phy_status *fixed_link; 301 u16 max_frame_length; 302 u16 pause_quanta; 303 u32 tx_ipg_length; 304 }; 305 306 struct fman_mac { 307 /* Pointer to MAC memory mapped registers */ 308 struct memac_regs __iomem *regs; 309 /* MAC address of device */ 310 u64 addr; 311 /* Ethernet physical interface */ 312 phy_interface_t phy_if; 313 u16 max_speed; 314 struct mac_device *dev_id; /* device cookie used by the exception cbs */ 315 fman_mac_exception_cb *exception_cb; 316 fman_mac_exception_cb *event_cb; 317 /* Pointer to driver's global address hash table */ 318 struct eth_hash_t *multicast_addr_hash; 319 /* Pointer to driver's individual address hash table */ 320 struct eth_hash_t *unicast_addr_hash; 321 u8 mac_id; 322 u32 exceptions; 323 struct memac_cfg *memac_drv_param; 324 void *fm; 325 struct fman_rev_info fm_rev_info; 326 bool basex_if; 327 struct phy_device *pcsphy; 328 bool allmulti_enabled; 329 }; 330 331 static void add_addr_in_paddr(struct memac_regs __iomem *regs, const u8 *adr, 332 u8 paddr_num) 333 { 334 u32 tmp0, tmp1; 335 336 tmp0 = (u32)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24); 337 tmp1 = (u32)(adr[4] | adr[5] << 8); 338 339 if (paddr_num == 0) { 340 iowrite32be(tmp0, ®s->mac_addr0.mac_addr_l); 341 iowrite32be(tmp1, ®s->mac_addr0.mac_addr_u); 342 } else { 343 iowrite32be(tmp0, ®s->mac_addr[paddr_num - 1].mac_addr_l); 344 iowrite32be(tmp1, ®s->mac_addr[paddr_num - 1].mac_addr_u); 345 } 346 } 347 348 static int reset(struct memac_regs __iomem *regs) 349 { 350 u32 tmp; 351 int count; 352 353 tmp = ioread32be(®s->command_config); 354 355 tmp |= CMD_CFG_SW_RESET; 356 357 iowrite32be(tmp, ®s->command_config); 358 359 count = 100; 360 do { 361 udelay(1); 362 } while ((ioread32be(®s->command_config) & CMD_CFG_SW_RESET) && 363 --count); 364 365 if (count == 0) 366 return -EBUSY; 367 368 return 0; 369 } 370 371 static void set_exception(struct memac_regs __iomem *regs, u32 val, 372 bool enable) 373 { 374 u32 tmp; 375 376 tmp = ioread32be(®s->imask); 377 if (enable) 378 tmp |= val; 379 else 380 tmp &= ~val; 381 382 iowrite32be(tmp, ®s->imask); 383 } 384 385 static int init(struct memac_regs __iomem *regs, struct memac_cfg *cfg, 386 phy_interface_t phy_if, u16 speed, bool slow_10g_if, 387 u32 exceptions) 388 { 389 u32 tmp; 390 391 /* Config */ 392 tmp = 0; 393 if (cfg->promiscuous_mode_enable) 394 tmp |= CMD_CFG_PROMIS_EN; 395 if (cfg->pause_ignore) 396 tmp |= CMD_CFG_PAUSE_IGNORE; 397 398 /* Payload length check disable */ 399 tmp |= CMD_CFG_NO_LEN_CHK; 400 /* Enable padding of frames in transmit direction */ 401 tmp |= CMD_CFG_TX_PAD_EN; 402 403 tmp |= CMD_CFG_CRC_FWD; 404 405 iowrite32be(tmp, ®s->command_config); 406 407 /* Max Frame Length */ 408 iowrite32be((u32)cfg->max_frame_length, ®s->maxfrm); 409 410 /* Pause Time */ 411 iowrite32be((u32)cfg->pause_quanta, ®s->pause_quanta[0]); 412 iowrite32be((u32)0, ®s->pause_thresh[0]); 413 414 /* IF_MODE */ 415 tmp = 0; 416 switch (phy_if) { 417 case PHY_INTERFACE_MODE_XGMII: 418 tmp |= IF_MODE_10G; 419 break; 420 case PHY_INTERFACE_MODE_MII: 421 tmp |= IF_MODE_MII; 422 break; 423 default: 424 tmp |= IF_MODE_GMII; 425 if (phy_if == PHY_INTERFACE_MODE_RGMII || 426 phy_if == PHY_INTERFACE_MODE_RGMII_ID || 427 phy_if == PHY_INTERFACE_MODE_RGMII_RXID || 428 phy_if == PHY_INTERFACE_MODE_RGMII_TXID) 429 tmp |= IF_MODE_RGMII | IF_MODE_RGMII_AUTO; 430 } 431 iowrite32be(tmp, ®s->if_mode); 432 433 /* TX_FIFO_SECTIONS */ 434 tmp = 0; 435 if (phy_if == PHY_INTERFACE_MODE_XGMII) { 436 if (slow_10g_if) { 437 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G | 438 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G); 439 } else { 440 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_10G | 441 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G); 442 } 443 } else { 444 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_1G | 445 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G); 446 } 447 iowrite32be(tmp, ®s->tx_fifo_sections); 448 449 /* clear all pending events and set-up interrupts */ 450 iowrite32be(0xffffffff, ®s->ievent); 451 set_exception(regs, exceptions, true); 452 453 return 0; 454 } 455 456 static void set_dflts(struct memac_cfg *cfg) 457 { 458 cfg->reset_on_init = false; 459 cfg->promiscuous_mode_enable = false; 460 cfg->pause_ignore = false; 461 cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH; 462 cfg->max_frame_length = DEFAULT_FRAME_LENGTH; 463 cfg->pause_quanta = DEFAULT_PAUSE_QUANTA; 464 } 465 466 static u32 get_mac_addr_hash_code(u64 eth_addr) 467 { 468 u64 mask1, mask2; 469 u32 xor_val = 0; 470 u8 i, j; 471 472 for (i = 0; i < 6; i++) { 473 mask1 = eth_addr & (u64)0x01; 474 eth_addr >>= 1; 475 476 for (j = 0; j < 7; j++) { 477 mask2 = eth_addr & (u64)0x01; 478 mask1 ^= mask2; 479 eth_addr >>= 1; 480 } 481 482 xor_val |= (mask1 << (5 - i)); 483 } 484 485 return xor_val; 486 } 487 488 static void setup_sgmii_internal_phy(struct fman_mac *memac, 489 struct fixed_phy_status *fixed_link) 490 { 491 u16 tmp_reg16; 492 493 if (WARN_ON(!memac->pcsphy)) 494 return; 495 496 /* SGMII mode */ 497 tmp_reg16 = IF_MODE_SGMII_EN; 498 if (!fixed_link) 499 /* AN enable */ 500 tmp_reg16 |= IF_MODE_USE_SGMII_AN; 501 else { 502 switch (fixed_link->speed) { 503 case 10: 504 /* For 10M: IF_MODE[SPEED_10M] = 0 */ 505 break; 506 case 100: 507 tmp_reg16 |= IF_MODE_SGMII_SPEED_100M; 508 break; 509 case 1000: 510 default: 511 tmp_reg16 |= IF_MODE_SGMII_SPEED_1G; 512 break; 513 } 514 if (!fixed_link->duplex) 515 tmp_reg16 |= IF_MODE_SGMII_DUPLEX_HALF; 516 } 517 phy_write(memac->pcsphy, MDIO_SGMII_IF_MODE, tmp_reg16); 518 519 /* Device ability according to SGMII specification */ 520 tmp_reg16 = MDIO_SGMII_DEV_ABIL_SGMII_MODE; 521 phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16); 522 523 /* Adjust link timer for SGMII - 524 * According to Cisco SGMII specification the timer should be 1.6 ms. 525 * The link_timer register is configured in units of the clock. 526 * - When running as 1G SGMII, Serdes clock is 125 MHz, so 527 * unit = 1 / (125*10^6 Hz) = 8 ns. 528 * 1.6 ms in units of 8 ns = 1.6ms / 8ns = 2*10^5 = 0x30d40 529 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so 530 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns. 531 * 1.6 ms in units of 3.2 ns = 1.6ms / 3.2ns = 5*10^5 = 0x7a120. 532 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII, 533 * we always set up here a value of 2.5 SGMII. 534 */ 535 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H); 536 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L); 537 538 if (!fixed_link) 539 /* Restart AN */ 540 tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN; 541 else 542 /* AN disabled */ 543 tmp_reg16 = SGMII_CR_DEF_VAL & ~SGMII_CR_AN_EN; 544 phy_write(memac->pcsphy, 0x0, tmp_reg16); 545 } 546 547 static void setup_sgmii_internal_phy_base_x(struct fman_mac *memac) 548 { 549 u16 tmp_reg16; 550 551 /* AN Device capability */ 552 tmp_reg16 = MDIO_SGMII_DEV_ABIL_BASEX_MODE; 553 phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16); 554 555 /* Adjust link timer for SGMII - 556 * For Serdes 1000BaseX auto-negotiation the timer should be 10 ms. 557 * The link_timer register is configured in units of the clock. 558 * - When running as 1G SGMII, Serdes clock is 125 MHz, so 559 * unit = 1 / (125*10^6 Hz) = 8 ns. 560 * 10 ms in units of 8 ns = 10ms / 8ns = 1250000 = 0x1312d0 561 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so 562 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns. 563 * 10 ms in units of 3.2 ns = 10ms / 3.2ns = 3125000 = 0x2faf08. 564 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII, 565 * we always set up here a value of 2.5 SGMII. 566 */ 567 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H_BASEX); 568 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L_BASEX); 569 570 /* Restart AN */ 571 tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN; 572 phy_write(memac->pcsphy, 0x0, tmp_reg16); 573 } 574 575 static int check_init_parameters(struct fman_mac *memac) 576 { 577 if (!memac->exception_cb) { 578 pr_err("Uninitialized exception handler\n"); 579 return -EINVAL; 580 } 581 if (!memac->event_cb) { 582 pr_warn("Uninitialize event handler\n"); 583 return -EINVAL; 584 } 585 586 return 0; 587 } 588 589 static int get_exception_flag(enum fman_mac_exceptions exception) 590 { 591 u32 bit_mask; 592 593 switch (exception) { 594 case FM_MAC_EX_10G_TX_ECC_ER: 595 bit_mask = MEMAC_IMASK_TECC_ER; 596 break; 597 case FM_MAC_EX_10G_RX_ECC_ER: 598 bit_mask = MEMAC_IMASK_RECC_ER; 599 break; 600 case FM_MAC_EX_TS_FIFO_ECC_ERR: 601 bit_mask = MEMAC_IMASK_TSECC_ER; 602 break; 603 case FM_MAC_EX_MAGIC_PACKET_INDICATION: 604 bit_mask = MEMAC_IMASK_MGI; 605 break; 606 default: 607 bit_mask = 0; 608 break; 609 } 610 611 return bit_mask; 612 } 613 614 static void memac_err_exception(void *handle) 615 { 616 struct fman_mac *memac = (struct fman_mac *)handle; 617 struct memac_regs __iomem *regs = memac->regs; 618 u32 event, imask; 619 620 event = ioread32be(®s->ievent); 621 imask = ioread32be(®s->imask); 622 623 /* Imask include both error and notification/event bits. 624 * Leaving only error bits enabled by imask. 625 * The imask error bits are shifted by 16 bits offset from 626 * their corresponding location in the ievent - hence the >> 16 627 */ 628 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16); 629 630 iowrite32be(event, ®s->ievent); 631 632 if (event & MEMAC_IEVNT_TS_ECC_ER) 633 memac->exception_cb(memac->dev_id, FM_MAC_EX_TS_FIFO_ECC_ERR); 634 if (event & MEMAC_IEVNT_TX_ECC_ER) 635 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_TX_ECC_ER); 636 if (event & MEMAC_IEVNT_RX_ECC_ER) 637 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_RX_ECC_ER); 638 } 639 640 static void memac_exception(void *handle) 641 { 642 struct fman_mac *memac = (struct fman_mac *)handle; 643 struct memac_regs __iomem *regs = memac->regs; 644 u32 event, imask; 645 646 event = ioread32be(®s->ievent); 647 imask = ioread32be(®s->imask); 648 649 /* Imask include both error and notification/event bits. 650 * Leaving only error bits enabled by imask. 651 * The imask error bits are shifted by 16 bits offset from 652 * their corresponding location in the ievent - hence the >> 16 653 */ 654 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16); 655 656 iowrite32be(event, ®s->ievent); 657 658 if (event & MEMAC_IEVNT_MGI) 659 memac->exception_cb(memac->dev_id, 660 FM_MAC_EX_MAGIC_PACKET_INDICATION); 661 } 662 663 static void free_init_resources(struct fman_mac *memac) 664 { 665 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 666 FMAN_INTR_TYPE_ERR); 667 668 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 669 FMAN_INTR_TYPE_NORMAL); 670 671 /* release the driver's group hash table */ 672 free_hash_table(memac->multicast_addr_hash); 673 memac->multicast_addr_hash = NULL; 674 675 /* release the driver's individual hash table */ 676 free_hash_table(memac->unicast_addr_hash); 677 memac->unicast_addr_hash = NULL; 678 } 679 680 static bool is_init_done(struct memac_cfg *memac_drv_params) 681 { 682 /* Checks if mEMAC driver parameters were initialized */ 683 if (!memac_drv_params) 684 return true; 685 686 return false; 687 } 688 689 static int memac_enable(struct fman_mac *memac) 690 { 691 struct memac_regs __iomem *regs = memac->regs; 692 u32 tmp; 693 694 if (!is_init_done(memac->memac_drv_param)) 695 return -EINVAL; 696 697 tmp = ioread32be(®s->command_config); 698 tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN; 699 iowrite32be(tmp, ®s->command_config); 700 701 return 0; 702 } 703 704 static void memac_disable(struct fman_mac *memac) 705 706 { 707 struct memac_regs __iomem *regs = memac->regs; 708 u32 tmp; 709 710 WARN_ON_ONCE(!is_init_done(memac->memac_drv_param)); 711 712 tmp = ioread32be(®s->command_config); 713 tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN); 714 iowrite32be(tmp, ®s->command_config); 715 } 716 717 static int memac_set_promiscuous(struct fman_mac *memac, bool new_val) 718 { 719 struct memac_regs __iomem *regs = memac->regs; 720 u32 tmp; 721 722 if (!is_init_done(memac->memac_drv_param)) 723 return -EINVAL; 724 725 tmp = ioread32be(®s->command_config); 726 if (new_val) 727 tmp |= CMD_CFG_PROMIS_EN; 728 else 729 tmp &= ~CMD_CFG_PROMIS_EN; 730 731 iowrite32be(tmp, ®s->command_config); 732 733 return 0; 734 } 735 736 static int memac_adjust_link(struct fman_mac *memac, u16 speed) 737 { 738 struct memac_regs __iomem *regs = memac->regs; 739 u32 tmp; 740 741 if (!is_init_done(memac->memac_drv_param)) 742 return -EINVAL; 743 744 tmp = ioread32be(®s->if_mode); 745 746 /* Set full duplex */ 747 tmp &= ~IF_MODE_HD; 748 749 if (phy_interface_mode_is_rgmii(memac->phy_if)) { 750 /* Configure RGMII in manual mode */ 751 tmp &= ~IF_MODE_RGMII_AUTO; 752 tmp &= ~IF_MODE_RGMII_SP_MASK; 753 /* Full duplex */ 754 tmp |= IF_MODE_RGMII_FD; 755 756 switch (speed) { 757 case SPEED_1000: 758 tmp |= IF_MODE_RGMII_1000; 759 break; 760 case SPEED_100: 761 tmp |= IF_MODE_RGMII_100; 762 break; 763 case SPEED_10: 764 tmp |= IF_MODE_RGMII_10; 765 break; 766 default: 767 break; 768 } 769 } 770 771 iowrite32be(tmp, ®s->if_mode); 772 773 return 0; 774 } 775 776 static void adjust_link_memac(struct mac_device *mac_dev) 777 { 778 struct phy_device *phy_dev = mac_dev->phy_dev; 779 struct fman_mac *fman_mac; 780 bool rx_pause, tx_pause; 781 int err; 782 783 fman_mac = mac_dev->fman_mac; 784 memac_adjust_link(fman_mac, phy_dev->speed); 785 mac_dev->update_speed(mac_dev, phy_dev->speed); 786 787 fman_get_pause_cfg(mac_dev, &rx_pause, &tx_pause); 788 err = fman_set_mac_active_pause(mac_dev, rx_pause, tx_pause); 789 if (err < 0) 790 dev_err(mac_dev->dev, "fman_set_mac_active_pause() = %d\n", 791 err); 792 } 793 794 static int memac_set_tx_pause_frames(struct fman_mac *memac, u8 priority, 795 u16 pause_time, u16 thresh_time) 796 { 797 struct memac_regs __iomem *regs = memac->regs; 798 u32 tmp; 799 800 if (!is_init_done(memac->memac_drv_param)) 801 return -EINVAL; 802 803 tmp = ioread32be(®s->tx_fifo_sections); 804 805 GET_TX_EMPTY_DEFAULT_VALUE(tmp); 806 iowrite32be(tmp, ®s->tx_fifo_sections); 807 808 tmp = ioread32be(®s->command_config); 809 tmp &= ~CMD_CFG_PFC_MODE; 810 811 iowrite32be(tmp, ®s->command_config); 812 813 tmp = ioread32be(®s->pause_quanta[priority / 2]); 814 if (priority % 2) 815 tmp &= CLXY_PAUSE_QUANTA_CLX_PQNT; 816 else 817 tmp &= CLXY_PAUSE_QUANTA_CLY_PQNT; 818 tmp |= ((u32)pause_time << (16 * (priority % 2))); 819 iowrite32be(tmp, ®s->pause_quanta[priority / 2]); 820 821 tmp = ioread32be(®s->pause_thresh[priority / 2]); 822 if (priority % 2) 823 tmp &= CLXY_PAUSE_THRESH_CLX_QTH; 824 else 825 tmp &= CLXY_PAUSE_THRESH_CLY_QTH; 826 tmp |= ((u32)thresh_time << (16 * (priority % 2))); 827 iowrite32be(tmp, ®s->pause_thresh[priority / 2]); 828 829 return 0; 830 } 831 832 static int memac_accept_rx_pause_frames(struct fman_mac *memac, bool en) 833 { 834 struct memac_regs __iomem *regs = memac->regs; 835 u32 tmp; 836 837 if (!is_init_done(memac->memac_drv_param)) 838 return -EINVAL; 839 840 tmp = ioread32be(®s->command_config); 841 if (en) 842 tmp &= ~CMD_CFG_PAUSE_IGNORE; 843 else 844 tmp |= CMD_CFG_PAUSE_IGNORE; 845 846 iowrite32be(tmp, ®s->command_config); 847 848 return 0; 849 } 850 851 static int memac_modify_mac_address(struct fman_mac *memac, 852 const enet_addr_t *enet_addr) 853 { 854 if (!is_init_done(memac->memac_drv_param)) 855 return -EINVAL; 856 857 add_addr_in_paddr(memac->regs, (const u8 *)(*enet_addr), 0); 858 859 return 0; 860 } 861 862 static int memac_add_hash_mac_address(struct fman_mac *memac, 863 enet_addr_t *eth_addr) 864 { 865 struct memac_regs __iomem *regs = memac->regs; 866 struct eth_hash_entry *hash_entry; 867 u32 hash; 868 u64 addr; 869 870 if (!is_init_done(memac->memac_drv_param)) 871 return -EINVAL; 872 873 addr = ENET_ADDR_TO_UINT64(*eth_addr); 874 875 if (!(addr & GROUP_ADDRESS)) { 876 /* Unicast addresses not supported in hash */ 877 pr_err("Unicast Address\n"); 878 return -EINVAL; 879 } 880 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK; 881 882 /* Create element to be added to the driver hash table */ 883 hash_entry = kmalloc(sizeof(*hash_entry), GFP_ATOMIC); 884 if (!hash_entry) 885 return -ENOMEM; 886 hash_entry->addr = addr; 887 INIT_LIST_HEAD(&hash_entry->node); 888 889 list_add_tail(&hash_entry->node, 890 &memac->multicast_addr_hash->lsts[hash]); 891 iowrite32be(hash | HASH_CTRL_MCAST_EN, ®s->hashtable_ctrl); 892 893 return 0; 894 } 895 896 static int memac_set_allmulti(struct fman_mac *memac, bool enable) 897 { 898 u32 entry; 899 struct memac_regs __iomem *regs = memac->regs; 900 901 if (!is_init_done(memac->memac_drv_param)) 902 return -EINVAL; 903 904 if (enable) { 905 for (entry = 0; entry < HASH_TABLE_SIZE; entry++) 906 iowrite32be(entry | HASH_CTRL_MCAST_EN, 907 ®s->hashtable_ctrl); 908 } else { 909 for (entry = 0; entry < HASH_TABLE_SIZE; entry++) 910 iowrite32be(entry & ~HASH_CTRL_MCAST_EN, 911 ®s->hashtable_ctrl); 912 } 913 914 memac->allmulti_enabled = enable; 915 916 return 0; 917 } 918 919 static int memac_set_tstamp(struct fman_mac *memac, bool enable) 920 { 921 return 0; /* Always enabled. */ 922 } 923 924 static int memac_del_hash_mac_address(struct fman_mac *memac, 925 enet_addr_t *eth_addr) 926 { 927 struct memac_regs __iomem *regs = memac->regs; 928 struct eth_hash_entry *hash_entry = NULL; 929 struct list_head *pos; 930 u32 hash; 931 u64 addr; 932 933 if (!is_init_done(memac->memac_drv_param)) 934 return -EINVAL; 935 936 addr = ENET_ADDR_TO_UINT64(*eth_addr); 937 938 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK; 939 940 list_for_each(pos, &memac->multicast_addr_hash->lsts[hash]) { 941 hash_entry = ETH_HASH_ENTRY_OBJ(pos); 942 if (hash_entry && hash_entry->addr == addr) { 943 list_del_init(&hash_entry->node); 944 kfree(hash_entry); 945 break; 946 } 947 } 948 949 if (!memac->allmulti_enabled) { 950 if (list_empty(&memac->multicast_addr_hash->lsts[hash])) 951 iowrite32be(hash & ~HASH_CTRL_MCAST_EN, 952 ®s->hashtable_ctrl); 953 } 954 955 return 0; 956 } 957 958 static int memac_set_exception(struct fman_mac *memac, 959 enum fman_mac_exceptions exception, bool enable) 960 { 961 u32 bit_mask = 0; 962 963 if (!is_init_done(memac->memac_drv_param)) 964 return -EINVAL; 965 966 bit_mask = get_exception_flag(exception); 967 if (bit_mask) { 968 if (enable) 969 memac->exceptions |= bit_mask; 970 else 971 memac->exceptions &= ~bit_mask; 972 } else { 973 pr_err("Undefined exception\n"); 974 return -EINVAL; 975 } 976 set_exception(memac->regs, bit_mask, enable); 977 978 return 0; 979 } 980 981 static int memac_init(struct fman_mac *memac) 982 { 983 struct memac_cfg *memac_drv_param; 984 u8 i; 985 enet_addr_t eth_addr; 986 bool slow_10g_if = false; 987 struct fixed_phy_status *fixed_link = NULL; 988 int err; 989 u32 reg32 = 0; 990 991 if (is_init_done(memac->memac_drv_param)) 992 return -EINVAL; 993 994 err = check_init_parameters(memac); 995 if (err) 996 return err; 997 998 memac_drv_param = memac->memac_drv_param; 999 1000 if (memac->fm_rev_info.major == 6 && memac->fm_rev_info.minor == 4) 1001 slow_10g_if = true; 1002 1003 /* First, reset the MAC if desired. */ 1004 if (memac_drv_param->reset_on_init) { 1005 err = reset(memac->regs); 1006 if (err) { 1007 pr_err("mEMAC reset failed\n"); 1008 return err; 1009 } 1010 } 1011 1012 /* MAC Address */ 1013 if (memac->addr != 0) { 1014 MAKE_ENET_ADDR_FROM_UINT64(memac->addr, eth_addr); 1015 add_addr_in_paddr(memac->regs, (const u8 *)eth_addr, 0); 1016 } 1017 1018 fixed_link = memac_drv_param->fixed_link; 1019 1020 init(memac->regs, memac->memac_drv_param, memac->phy_if, 1021 memac->max_speed, slow_10g_if, memac->exceptions); 1022 1023 /* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 errata workaround 1024 * Exists only in FMan 6.0 and 6.3. 1025 */ 1026 if ((memac->fm_rev_info.major == 6) && 1027 ((memac->fm_rev_info.minor == 0) || 1028 (memac->fm_rev_info.minor == 3))) { 1029 /* MAC strips CRC from received frames - this workaround 1030 * should decrease the likelihood of bug appearance 1031 */ 1032 reg32 = ioread32be(&memac->regs->command_config); 1033 reg32 &= ~CMD_CFG_CRC_FWD; 1034 iowrite32be(reg32, &memac->regs->command_config); 1035 } 1036 1037 if (memac->phy_if == PHY_INTERFACE_MODE_SGMII) { 1038 /* Configure internal SGMII PHY */ 1039 if (memac->basex_if) 1040 setup_sgmii_internal_phy_base_x(memac); 1041 else 1042 setup_sgmii_internal_phy(memac, fixed_link); 1043 } else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII) { 1044 /* Configure 4 internal SGMII PHYs */ 1045 for (i = 0; i < 4; i++) { 1046 u8 qsmgii_phy_addr, phy_addr; 1047 /* QSGMII PHY address occupies 3 upper bits of 5-bit 1048 * phy_address; the lower 2 bits are used to extend 1049 * register address space and access each one of 4 1050 * ports inside QSGMII. 1051 */ 1052 phy_addr = memac->pcsphy->mdio.addr; 1053 qsmgii_phy_addr = (u8)((phy_addr << 2) | i); 1054 memac->pcsphy->mdio.addr = qsmgii_phy_addr; 1055 if (memac->basex_if) 1056 setup_sgmii_internal_phy_base_x(memac); 1057 else 1058 setup_sgmii_internal_phy(memac, fixed_link); 1059 1060 memac->pcsphy->mdio.addr = phy_addr; 1061 } 1062 } 1063 1064 /* Max Frame Length */ 1065 err = fman_set_mac_max_frame(memac->fm, memac->mac_id, 1066 memac_drv_param->max_frame_length); 1067 if (err) { 1068 pr_err("settings Mac max frame length is FAILED\n"); 1069 return err; 1070 } 1071 1072 memac->multicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE); 1073 if (!memac->multicast_addr_hash) { 1074 free_init_resources(memac); 1075 pr_err("allocation hash table is FAILED\n"); 1076 return -ENOMEM; 1077 } 1078 1079 memac->unicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE); 1080 if (!memac->unicast_addr_hash) { 1081 free_init_resources(memac); 1082 pr_err("allocation hash table is FAILED\n"); 1083 return -ENOMEM; 1084 } 1085 1086 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 1087 FMAN_INTR_TYPE_ERR, memac_err_exception, memac); 1088 1089 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 1090 FMAN_INTR_TYPE_NORMAL, memac_exception, memac); 1091 1092 kfree(memac_drv_param); 1093 memac->memac_drv_param = NULL; 1094 1095 return 0; 1096 } 1097 1098 static int memac_free(struct fman_mac *memac) 1099 { 1100 free_init_resources(memac); 1101 1102 if (memac->pcsphy) 1103 put_device(&memac->pcsphy->mdio.dev); 1104 1105 kfree(memac->memac_drv_param); 1106 kfree(memac); 1107 1108 return 0; 1109 } 1110 1111 static struct fman_mac *memac_config(struct mac_device *mac_dev, 1112 struct fman_mac_params *params) 1113 { 1114 struct fman_mac *memac; 1115 struct memac_cfg *memac_drv_param; 1116 1117 /* allocate memory for the m_emac data structure */ 1118 memac = kzalloc(sizeof(*memac), GFP_KERNEL); 1119 if (!memac) 1120 return NULL; 1121 1122 /* allocate memory for the m_emac driver parameters data structure */ 1123 memac_drv_param = kzalloc(sizeof(*memac_drv_param), GFP_KERNEL); 1124 if (!memac_drv_param) { 1125 memac_free(memac); 1126 return NULL; 1127 } 1128 1129 /* Plant parameter structure pointer */ 1130 memac->memac_drv_param = memac_drv_param; 1131 1132 set_dflts(memac_drv_param); 1133 1134 memac->addr = ENET_ADDR_TO_UINT64(mac_dev->addr); 1135 1136 memac->regs = mac_dev->vaddr; 1137 memac->max_speed = params->max_speed; 1138 memac->phy_if = mac_dev->phy_if; 1139 memac->mac_id = params->mac_id; 1140 memac->exceptions = (MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER | 1141 MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI); 1142 memac->exception_cb = params->exception_cb; 1143 memac->event_cb = params->event_cb; 1144 memac->dev_id = mac_dev; 1145 memac->fm = params->fm; 1146 memac->basex_if = params->basex_if; 1147 1148 /* Save FMan revision */ 1149 fman_get_revision(memac->fm, &memac->fm_rev_info); 1150 1151 return memac; 1152 } 1153 1154 int memac_initialization(struct mac_device *mac_dev, 1155 struct device_node *mac_node, 1156 struct fman_mac_params *params) 1157 { 1158 int err; 1159 struct device_node *phy_node; 1160 struct fixed_phy_status *fixed_link; 1161 struct fman_mac *memac; 1162 1163 mac_dev->set_promisc = memac_set_promiscuous; 1164 mac_dev->change_addr = memac_modify_mac_address; 1165 mac_dev->add_hash_mac_addr = memac_add_hash_mac_address; 1166 mac_dev->remove_hash_mac_addr = memac_del_hash_mac_address; 1167 mac_dev->set_tx_pause = memac_set_tx_pause_frames; 1168 mac_dev->set_rx_pause = memac_accept_rx_pause_frames; 1169 mac_dev->set_exception = memac_set_exception; 1170 mac_dev->set_allmulti = memac_set_allmulti; 1171 mac_dev->set_tstamp = memac_set_tstamp; 1172 mac_dev->set_multi = fman_set_multi; 1173 mac_dev->adjust_link = adjust_link_memac; 1174 mac_dev->enable = memac_enable; 1175 mac_dev->disable = memac_disable; 1176 1177 if (params->max_speed == SPEED_10000) 1178 mac_dev->phy_if = PHY_INTERFACE_MODE_XGMII; 1179 1180 mac_dev->fman_mac = memac_config(mac_dev, params); 1181 if (!mac_dev->fman_mac) { 1182 err = -EINVAL; 1183 goto _return; 1184 } 1185 1186 memac = mac_dev->fman_mac; 1187 memac->memac_drv_param->max_frame_length = fman_get_max_frm(); 1188 memac->memac_drv_param->reset_on_init = true; 1189 if (memac->phy_if == PHY_INTERFACE_MODE_SGMII || 1190 memac->phy_if == PHY_INTERFACE_MODE_QSGMII) { 1191 phy_node = of_parse_phandle(mac_node, "pcsphy-handle", 0); 1192 if (!phy_node) { 1193 pr_err("PCS PHY node is not available\n"); 1194 err = -EINVAL; 1195 goto _return_fm_mac_free; 1196 } 1197 1198 memac->pcsphy = of_phy_find_device(phy_node); 1199 if (!memac->pcsphy) { 1200 pr_err("of_phy_find_device (PCS PHY) failed\n"); 1201 err = -EINVAL; 1202 goto _return_fm_mac_free; 1203 } 1204 } 1205 1206 if (!mac_dev->phy_node && of_phy_is_fixed_link(mac_node)) { 1207 struct phy_device *phy; 1208 1209 err = of_phy_register_fixed_link(mac_node); 1210 if (err) 1211 goto _return_fm_mac_free; 1212 1213 fixed_link = kzalloc(sizeof(*fixed_link), GFP_KERNEL); 1214 if (!fixed_link) { 1215 err = -ENOMEM; 1216 goto _return_fm_mac_free; 1217 } 1218 1219 mac_dev->phy_node = of_node_get(mac_node); 1220 phy = of_phy_find_device(mac_dev->phy_node); 1221 if (!phy) { 1222 err = -EINVAL; 1223 of_node_put(mac_dev->phy_node); 1224 goto _return_fixed_link_free; 1225 } 1226 1227 fixed_link->link = phy->link; 1228 fixed_link->speed = phy->speed; 1229 fixed_link->duplex = phy->duplex; 1230 fixed_link->pause = phy->pause; 1231 fixed_link->asym_pause = phy->asym_pause; 1232 1233 put_device(&phy->mdio.dev); 1234 memac->memac_drv_param->fixed_link = fixed_link; 1235 } 1236 1237 err = memac_init(mac_dev->fman_mac); 1238 if (err < 0) 1239 goto _return_fixed_link_free; 1240 1241 dev_info(mac_dev->dev, "FMan MEMAC\n"); 1242 1243 goto _return; 1244 1245 _return_fixed_link_free: 1246 kfree(fixed_link); 1247 _return_fm_mac_free: 1248 memac_free(mac_dev->fman_mac); 1249 _return: 1250 return err; 1251 } 1252