1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Fast Ethernet Controller (ENET) PTP driver for MX6x. 4 * 5 * Copyright (C) 2012 Freescale Semiconductor, Inc. 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/module.h> 11 #include <linux/kernel.h> 12 #include <linux/string.h> 13 #include <linux/ptrace.h> 14 #include <linux/errno.h> 15 #include <linux/ioport.h> 16 #include <linux/slab.h> 17 #include <linux/interrupt.h> 18 #include <linux/pci.h> 19 #include <linux/delay.h> 20 #include <linux/netdevice.h> 21 #include <linux/etherdevice.h> 22 #include <linux/skbuff.h> 23 #include <linux/spinlock.h> 24 #include <linux/workqueue.h> 25 #include <linux/bitops.h> 26 #include <linux/io.h> 27 #include <linux/irq.h> 28 #include <linux/clk.h> 29 #include <linux/platform_device.h> 30 #include <linux/phy.h> 31 #include <linux/fec.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/of_gpio.h> 35 #include <linux/of_net.h> 36 37 #include "fec.h" 38 39 /* FEC 1588 register bits */ 40 #define FEC_T_CTRL_SLAVE 0x00002000 41 #define FEC_T_CTRL_CAPTURE 0x00000800 42 #define FEC_T_CTRL_RESTART 0x00000200 43 #define FEC_T_CTRL_PERIOD_RST 0x00000030 44 #define FEC_T_CTRL_PERIOD_EN 0x00000010 45 #define FEC_T_CTRL_ENABLE 0x00000001 46 47 #define FEC_T_INC_MASK 0x0000007f 48 #define FEC_T_INC_OFFSET 0 49 #define FEC_T_INC_CORR_MASK 0x00007f00 50 #define FEC_T_INC_CORR_OFFSET 8 51 52 #define FEC_T_CTRL_PINPER 0x00000080 53 #define FEC_T_TF0_MASK 0x00000001 54 #define FEC_T_TF0_OFFSET 0 55 #define FEC_T_TF1_MASK 0x00000002 56 #define FEC_T_TF1_OFFSET 1 57 #define FEC_T_TF2_MASK 0x00000004 58 #define FEC_T_TF2_OFFSET 2 59 #define FEC_T_TF3_MASK 0x00000008 60 #define FEC_T_TF3_OFFSET 3 61 #define FEC_T_TDRE_MASK 0x00000001 62 #define FEC_T_TDRE_OFFSET 0 63 #define FEC_T_TMODE_MASK 0x0000003C 64 #define FEC_T_TMODE_OFFSET 2 65 #define FEC_T_TIE_MASK 0x00000040 66 #define FEC_T_TIE_OFFSET 6 67 #define FEC_T_TF_MASK 0x00000080 68 #define FEC_T_TF_OFFSET 7 69 70 #define FEC_ATIME_CTRL 0x400 71 #define FEC_ATIME 0x404 72 #define FEC_ATIME_EVT_OFFSET 0x408 73 #define FEC_ATIME_EVT_PERIOD 0x40c 74 #define FEC_ATIME_CORR 0x410 75 #define FEC_ATIME_INC 0x414 76 #define FEC_TS_TIMESTAMP 0x418 77 78 #define FEC_TGSR 0x604 79 #define FEC_TCSR(n) (0x608 + n * 0x08) 80 #define FEC_TCCR(n) (0x60C + n * 0x08) 81 #define MAX_TIMER_CHANNEL 3 82 #define FEC_TMODE_TOGGLE 0x05 83 #define FEC_HIGH_PULSE 0x0F 84 85 #define FEC_CC_MULT (1 << 31) 86 #define FEC_COUNTER_PERIOD (1 << 31) 87 #define PPS_OUPUT_RELOAD_PERIOD NSEC_PER_SEC 88 #define FEC_CHANNLE_0 0 89 #define DEFAULT_PPS_CHANNEL FEC_CHANNLE_0 90 91 #define FEC_PTP_MAX_NSEC_PERIOD 4000000000ULL 92 #define FEC_PTP_MAX_NSEC_COUNTER 0x80000000ULL 93 94 /** 95 * fec_ptp_enable_pps 96 * @fep: the fec_enet_private structure handle 97 * @enable: enable the channel pps output 98 * 99 * This function enble the PPS ouput on the timer channel. 100 */ 101 static int fec_ptp_enable_pps(struct fec_enet_private *fep, uint enable) 102 { 103 unsigned long flags; 104 u32 val, tempval; 105 struct timespec64 ts; 106 u64 ns; 107 108 if (fep->pps_enable == enable) 109 return 0; 110 111 fep->pps_channel = DEFAULT_PPS_CHANNEL; 112 fep->reload_period = PPS_OUPUT_RELOAD_PERIOD; 113 114 spin_lock_irqsave(&fep->tmreg_lock, flags); 115 116 if (enable) { 117 /* clear capture or output compare interrupt status if have. 118 */ 119 writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel)); 120 121 /* It is recommended to double check the TMODE field in the 122 * TCSR register to be cleared before the first compare counter 123 * is written into TCCR register. Just add a double check. 124 */ 125 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); 126 do { 127 val &= ~(FEC_T_TMODE_MASK); 128 writel(val, fep->hwp + FEC_TCSR(fep->pps_channel)); 129 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); 130 } while (val & FEC_T_TMODE_MASK); 131 132 /* Dummy read counter to update the counter */ 133 timecounter_read(&fep->tc); 134 /* We want to find the first compare event in the next 135 * second point. So we need to know what the ptp time 136 * is now and how many nanoseconds is ahead to get next second. 137 * The remaining nanosecond ahead before the next second would be 138 * NSEC_PER_SEC - ts.tv_nsec. Add the remaining nanoseconds 139 * to current timer would be next second. 140 */ 141 tempval = fep->cc.read(&fep->cc); 142 /* Convert the ptp local counter to 1588 timestamp */ 143 ns = timecounter_cyc2time(&fep->tc, tempval); 144 ts = ns_to_timespec64(ns); 145 146 /* The tempval is less than 3 seconds, and so val is less than 147 * 4 seconds. No overflow for 32bit calculation. 148 */ 149 val = NSEC_PER_SEC - (u32)ts.tv_nsec + tempval; 150 151 /* Need to consider the situation that the current time is 152 * very close to the second point, which means NSEC_PER_SEC 153 * - ts.tv_nsec is close to be zero(For example 20ns); Since the timer 154 * is still running when we calculate the first compare event, it is 155 * possible that the remaining nanoseonds run out before the compare 156 * counter is calculated and written into TCCR register. To avoid 157 * this possibility, we will set the compare event to be the next 158 * of next second. The current setting is 31-bit timer and wrap 159 * around over 2 seconds. So it is okay to set the next of next 160 * seond for the timer. 161 */ 162 val += NSEC_PER_SEC; 163 164 /* We add (2 * NSEC_PER_SEC - (u32)ts.tv_nsec) to current 165 * ptp counter, which maybe cause 32-bit wrap. Since the 166 * (NSEC_PER_SEC - (u32)ts.tv_nsec) is less than 2 second. 167 * We can ensure the wrap will not cause issue. If the offset 168 * is bigger than fep->cc.mask would be a error. 169 */ 170 val &= fep->cc.mask; 171 writel(val, fep->hwp + FEC_TCCR(fep->pps_channel)); 172 173 /* Calculate the second the compare event timestamp */ 174 fep->next_counter = (val + fep->reload_period) & fep->cc.mask; 175 176 /* * Enable compare event when overflow */ 177 val = readl(fep->hwp + FEC_ATIME_CTRL); 178 val |= FEC_T_CTRL_PINPER; 179 writel(val, fep->hwp + FEC_ATIME_CTRL); 180 181 /* Compare channel setting. */ 182 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); 183 val |= (1 << FEC_T_TF_OFFSET | 1 << FEC_T_TIE_OFFSET); 184 val &= ~(1 << FEC_T_TDRE_OFFSET); 185 val &= ~(FEC_T_TMODE_MASK); 186 val |= (FEC_HIGH_PULSE << FEC_T_TMODE_OFFSET); 187 writel(val, fep->hwp + FEC_TCSR(fep->pps_channel)); 188 189 /* Write the second compare event timestamp and calculate 190 * the third timestamp. Refer the TCCR register detail in the spec. 191 */ 192 writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel)); 193 fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask; 194 } else { 195 writel(0, fep->hwp + FEC_TCSR(fep->pps_channel)); 196 } 197 198 fep->pps_enable = enable; 199 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 200 201 return 0; 202 } 203 204 static int fec_ptp_pps_perout(struct fec_enet_private *fep) 205 { 206 u32 compare_val, ptp_hc, temp_val; 207 u64 curr_time; 208 unsigned long flags; 209 210 spin_lock_irqsave(&fep->tmreg_lock, flags); 211 212 /* Update time counter */ 213 timecounter_read(&fep->tc); 214 215 /* Get the current ptp hardware time counter */ 216 temp_val = readl(fep->hwp + FEC_ATIME_CTRL); 217 temp_val |= FEC_T_CTRL_CAPTURE; 218 writel(temp_val, fep->hwp + FEC_ATIME_CTRL); 219 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE) 220 udelay(1); 221 222 ptp_hc = readl(fep->hwp + FEC_ATIME); 223 224 /* Convert the ptp local counter to 1588 timestamp */ 225 curr_time = timecounter_cyc2time(&fep->tc, ptp_hc); 226 227 /* If the pps start time less than current time add 100ms, just return. 228 * Because the software might not able to set the comparison time into 229 * the FEC_TCCR register in time and missed the start time. 230 */ 231 if (fep->perout_stime < curr_time + 100 * NSEC_PER_MSEC) { 232 dev_err(&fep->pdev->dev, "Current time is too close to the start time!\n"); 233 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 234 return -1; 235 } 236 237 compare_val = fep->perout_stime - curr_time + ptp_hc; 238 compare_val &= fep->cc.mask; 239 240 writel(compare_val, fep->hwp + FEC_TCCR(fep->pps_channel)); 241 fep->next_counter = (compare_val + fep->reload_period) & fep->cc.mask; 242 243 /* Enable compare event when overflow */ 244 temp_val = readl(fep->hwp + FEC_ATIME_CTRL); 245 temp_val |= FEC_T_CTRL_PINPER; 246 writel(temp_val, fep->hwp + FEC_ATIME_CTRL); 247 248 /* Compare channel setting. */ 249 temp_val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); 250 temp_val |= (1 << FEC_T_TF_OFFSET | 1 << FEC_T_TIE_OFFSET); 251 temp_val &= ~(1 << FEC_T_TDRE_OFFSET); 252 temp_val &= ~(FEC_T_TMODE_MASK); 253 temp_val |= (FEC_TMODE_TOGGLE << FEC_T_TMODE_OFFSET); 254 writel(temp_val, fep->hwp + FEC_TCSR(fep->pps_channel)); 255 256 /* Write the second compare event timestamp and calculate 257 * the third timestamp. Refer the TCCR register detail in the spec. 258 */ 259 writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel)); 260 fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask; 261 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 262 263 return 0; 264 } 265 266 static enum hrtimer_restart fec_ptp_pps_perout_handler(struct hrtimer *timer) 267 { 268 struct fec_enet_private *fep = container_of(timer, 269 struct fec_enet_private, perout_timer); 270 271 fec_ptp_pps_perout(fep); 272 273 return HRTIMER_NORESTART; 274 } 275 276 /** 277 * fec_ptp_read - read raw cycle counter (to be used by time counter) 278 * @cc: the cyclecounter structure 279 * 280 * this function reads the cyclecounter registers and is called by the 281 * cyclecounter structure used to construct a ns counter from the 282 * arbitrary fixed point registers 283 */ 284 static u64 fec_ptp_read(const struct cyclecounter *cc) 285 { 286 struct fec_enet_private *fep = 287 container_of(cc, struct fec_enet_private, cc); 288 u32 tempval; 289 290 tempval = readl(fep->hwp + FEC_ATIME_CTRL); 291 tempval |= FEC_T_CTRL_CAPTURE; 292 writel(tempval, fep->hwp + FEC_ATIME_CTRL); 293 294 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE) 295 udelay(1); 296 297 return readl(fep->hwp + FEC_ATIME); 298 } 299 300 /** 301 * fec_ptp_start_cyclecounter - create the cycle counter from hw 302 * @ndev: network device 303 * 304 * this function initializes the timecounter and cyclecounter 305 * structures for use in generated a ns counter from the arbitrary 306 * fixed point cycles registers in the hardware. 307 */ 308 void fec_ptp_start_cyclecounter(struct net_device *ndev) 309 { 310 struct fec_enet_private *fep = netdev_priv(ndev); 311 unsigned long flags; 312 int inc; 313 314 inc = 1000000000 / fep->cycle_speed; 315 316 /* grab the ptp lock */ 317 spin_lock_irqsave(&fep->tmreg_lock, flags); 318 319 /* 1ns counter */ 320 writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC); 321 322 /* use 31-bit timer counter */ 323 writel(FEC_COUNTER_PERIOD, fep->hwp + FEC_ATIME_EVT_PERIOD); 324 325 writel(FEC_T_CTRL_ENABLE | FEC_T_CTRL_PERIOD_RST, 326 fep->hwp + FEC_ATIME_CTRL); 327 328 memset(&fep->cc, 0, sizeof(fep->cc)); 329 fep->cc.read = fec_ptp_read; 330 fep->cc.mask = CLOCKSOURCE_MASK(31); 331 fep->cc.shift = 31; 332 fep->cc.mult = FEC_CC_MULT; 333 334 /* reset the ns time counter */ 335 timecounter_init(&fep->tc, &fep->cc, 0); 336 337 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 338 } 339 340 /** 341 * fec_ptp_adjfreq - adjust ptp cycle frequency 342 * @ptp: the ptp clock structure 343 * @ppb: parts per billion adjustment from base 344 * 345 * Adjust the frequency of the ptp cycle counter by the 346 * indicated ppb from the base frequency. 347 * 348 * Because ENET hardware frequency adjust is complex, 349 * using software method to do that. 350 */ 351 static int fec_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 352 { 353 unsigned long flags; 354 int neg_adj = 0; 355 u32 i, tmp; 356 u32 corr_inc, corr_period; 357 u32 corr_ns; 358 u64 lhs, rhs; 359 360 struct fec_enet_private *fep = 361 container_of(ptp, struct fec_enet_private, ptp_caps); 362 363 if (ppb == 0) 364 return 0; 365 366 if (ppb < 0) { 367 ppb = -ppb; 368 neg_adj = 1; 369 } 370 371 /* In theory, corr_inc/corr_period = ppb/NSEC_PER_SEC; 372 * Try to find the corr_inc between 1 to fep->ptp_inc to 373 * meet adjustment requirement. 374 */ 375 lhs = NSEC_PER_SEC; 376 rhs = (u64)ppb * (u64)fep->ptp_inc; 377 for (i = 1; i <= fep->ptp_inc; i++) { 378 if (lhs >= rhs) { 379 corr_inc = i; 380 corr_period = div_u64(lhs, rhs); 381 break; 382 } 383 lhs += NSEC_PER_SEC; 384 } 385 /* Not found? Set it to high value - double speed 386 * correct in every clock step. 387 */ 388 if (i > fep->ptp_inc) { 389 corr_inc = fep->ptp_inc; 390 corr_period = 1; 391 } 392 393 if (neg_adj) 394 corr_ns = fep->ptp_inc - corr_inc; 395 else 396 corr_ns = fep->ptp_inc + corr_inc; 397 398 spin_lock_irqsave(&fep->tmreg_lock, flags); 399 400 tmp = readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK; 401 tmp |= corr_ns << FEC_T_INC_CORR_OFFSET; 402 writel(tmp, fep->hwp + FEC_ATIME_INC); 403 corr_period = corr_period > 1 ? corr_period - 1 : corr_period; 404 writel(corr_period, fep->hwp + FEC_ATIME_CORR); 405 /* dummy read to update the timer. */ 406 timecounter_read(&fep->tc); 407 408 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 409 410 return 0; 411 } 412 413 /** 414 * fec_ptp_adjtime 415 * @ptp: the ptp clock structure 416 * @delta: offset to adjust the cycle counter by 417 * 418 * adjust the timer by resetting the timecounter structure. 419 */ 420 static int fec_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 421 { 422 struct fec_enet_private *fep = 423 container_of(ptp, struct fec_enet_private, ptp_caps); 424 unsigned long flags; 425 426 spin_lock_irqsave(&fep->tmreg_lock, flags); 427 timecounter_adjtime(&fep->tc, delta); 428 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 429 430 return 0; 431 } 432 433 /** 434 * fec_ptp_gettime 435 * @ptp: the ptp clock structure 436 * @ts: timespec structure to hold the current time value 437 * 438 * read the timecounter and return the correct value on ns, 439 * after converting it into a struct timespec. 440 */ 441 static int fec_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 442 { 443 struct fec_enet_private *adapter = 444 container_of(ptp, struct fec_enet_private, ptp_caps); 445 u64 ns; 446 unsigned long flags; 447 448 mutex_lock(&adapter->ptp_clk_mutex); 449 /* Check the ptp clock */ 450 if (!adapter->ptp_clk_on) { 451 mutex_unlock(&adapter->ptp_clk_mutex); 452 return -EINVAL; 453 } 454 spin_lock_irqsave(&adapter->tmreg_lock, flags); 455 ns = timecounter_read(&adapter->tc); 456 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 457 mutex_unlock(&adapter->ptp_clk_mutex); 458 459 *ts = ns_to_timespec64(ns); 460 461 return 0; 462 } 463 464 /** 465 * fec_ptp_settime 466 * @ptp: the ptp clock structure 467 * @ts: the timespec containing the new time for the cycle counter 468 * 469 * reset the timecounter to use a new base value instead of the kernel 470 * wall timer value. 471 */ 472 static int fec_ptp_settime(struct ptp_clock_info *ptp, 473 const struct timespec64 *ts) 474 { 475 struct fec_enet_private *fep = 476 container_of(ptp, struct fec_enet_private, ptp_caps); 477 478 u64 ns; 479 unsigned long flags; 480 u32 counter; 481 482 mutex_lock(&fep->ptp_clk_mutex); 483 /* Check the ptp clock */ 484 if (!fep->ptp_clk_on) { 485 mutex_unlock(&fep->ptp_clk_mutex); 486 return -EINVAL; 487 } 488 489 ns = timespec64_to_ns(ts); 490 /* Get the timer value based on timestamp. 491 * Update the counter with the masked value. 492 */ 493 counter = ns & fep->cc.mask; 494 495 spin_lock_irqsave(&fep->tmreg_lock, flags); 496 writel(counter, fep->hwp + FEC_ATIME); 497 timecounter_init(&fep->tc, &fep->cc, ns); 498 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 499 mutex_unlock(&fep->ptp_clk_mutex); 500 return 0; 501 } 502 503 static int fec_ptp_pps_disable(struct fec_enet_private *fep, uint channel) 504 { 505 unsigned long flags; 506 507 spin_lock_irqsave(&fep->tmreg_lock, flags); 508 writel(0, fep->hwp + FEC_TCSR(channel)); 509 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 510 511 return 0; 512 } 513 514 /** 515 * fec_ptp_enable 516 * @ptp: the ptp clock structure 517 * @rq: the requested feature to change 518 * @on: whether to enable or disable the feature 519 * 520 */ 521 static int fec_ptp_enable(struct ptp_clock_info *ptp, 522 struct ptp_clock_request *rq, int on) 523 { 524 struct fec_enet_private *fep = 525 container_of(ptp, struct fec_enet_private, ptp_caps); 526 ktime_t timeout; 527 struct timespec64 start_time, period; 528 u64 curr_time, delta, period_ns; 529 unsigned long flags; 530 int ret = 0; 531 532 if (rq->type == PTP_CLK_REQ_PPS) { 533 ret = fec_ptp_enable_pps(fep, on); 534 535 return ret; 536 } else if (rq->type == PTP_CLK_REQ_PEROUT) { 537 /* Reject requests with unsupported flags */ 538 if (rq->perout.flags) 539 return -EOPNOTSUPP; 540 541 if (rq->perout.index != DEFAULT_PPS_CHANNEL) 542 return -EOPNOTSUPP; 543 544 fep->pps_channel = DEFAULT_PPS_CHANNEL; 545 period.tv_sec = rq->perout.period.sec; 546 period.tv_nsec = rq->perout.period.nsec; 547 period_ns = timespec64_to_ns(&period); 548 549 /* FEC PTP timer only has 31 bits, so if the period exceed 550 * 4s is not supported. 551 */ 552 if (period_ns > FEC_PTP_MAX_NSEC_PERIOD) { 553 dev_err(&fep->pdev->dev, "The period must equal to or less than 4s!\n"); 554 return -EOPNOTSUPP; 555 } 556 557 fep->reload_period = div_u64(period_ns, 2); 558 if (on && fep->reload_period) { 559 /* Convert 1588 timestamp to ns*/ 560 start_time.tv_sec = rq->perout.start.sec; 561 start_time.tv_nsec = rq->perout.start.nsec; 562 fep->perout_stime = timespec64_to_ns(&start_time); 563 564 mutex_lock(&fep->ptp_clk_mutex); 565 if (!fep->ptp_clk_on) { 566 dev_err(&fep->pdev->dev, "Error: PTP clock is closed!\n"); 567 mutex_unlock(&fep->ptp_clk_mutex); 568 return -EOPNOTSUPP; 569 } 570 spin_lock_irqsave(&fep->tmreg_lock, flags); 571 /* Read current timestamp */ 572 curr_time = timecounter_read(&fep->tc); 573 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 574 mutex_unlock(&fep->ptp_clk_mutex); 575 576 /* Calculate time difference */ 577 delta = fep->perout_stime - curr_time; 578 579 if (fep->perout_stime <= curr_time) { 580 dev_err(&fep->pdev->dev, "Start time must larger than current time!\n"); 581 return -EINVAL; 582 } 583 584 /* Because the timer counter of FEC only has 31-bits, correspondingly, 585 * the time comparison register FEC_TCCR also only low 31 bits can be 586 * set. If the start time of pps signal exceeds current time more than 587 * 0x80000000 ns, a software timer is used and the timer expires about 588 * 1 second before the start time to be able to set FEC_TCCR. 589 */ 590 if (delta > FEC_PTP_MAX_NSEC_COUNTER) { 591 timeout = ns_to_ktime(delta - NSEC_PER_SEC); 592 hrtimer_start(&fep->perout_timer, timeout, HRTIMER_MODE_REL); 593 } else { 594 return fec_ptp_pps_perout(fep); 595 } 596 } else { 597 fec_ptp_pps_disable(fep, fep->pps_channel); 598 } 599 600 return 0; 601 } else { 602 return -EOPNOTSUPP; 603 } 604 } 605 606 /** 607 * fec_ptp_disable_hwts - disable hardware time stamping 608 * @ndev: pointer to net_device 609 */ 610 void fec_ptp_disable_hwts(struct net_device *ndev) 611 { 612 struct fec_enet_private *fep = netdev_priv(ndev); 613 614 fep->hwts_tx_en = 0; 615 fep->hwts_rx_en = 0; 616 } 617 618 int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr) 619 { 620 struct fec_enet_private *fep = netdev_priv(ndev); 621 622 struct hwtstamp_config config; 623 624 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 625 return -EFAULT; 626 627 switch (config.tx_type) { 628 case HWTSTAMP_TX_OFF: 629 fep->hwts_tx_en = 0; 630 break; 631 case HWTSTAMP_TX_ON: 632 fep->hwts_tx_en = 1; 633 break; 634 default: 635 return -ERANGE; 636 } 637 638 switch (config.rx_filter) { 639 case HWTSTAMP_FILTER_NONE: 640 fep->hwts_rx_en = 0; 641 break; 642 643 default: 644 fep->hwts_rx_en = 1; 645 config.rx_filter = HWTSTAMP_FILTER_ALL; 646 break; 647 } 648 649 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 650 -EFAULT : 0; 651 } 652 653 int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr) 654 { 655 struct fec_enet_private *fep = netdev_priv(ndev); 656 struct hwtstamp_config config; 657 658 config.flags = 0; 659 config.tx_type = fep->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 660 config.rx_filter = (fep->hwts_rx_en ? 661 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE); 662 663 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 664 -EFAULT : 0; 665 } 666 667 /* 668 * fec_time_keep - call timecounter_read every second to avoid timer overrun 669 * because ENET just support 32bit counter, will timeout in 4s 670 */ 671 static void fec_time_keep(struct work_struct *work) 672 { 673 struct delayed_work *dwork = to_delayed_work(work); 674 struct fec_enet_private *fep = container_of(dwork, struct fec_enet_private, time_keep); 675 unsigned long flags; 676 677 mutex_lock(&fep->ptp_clk_mutex); 678 if (fep->ptp_clk_on) { 679 spin_lock_irqsave(&fep->tmreg_lock, flags); 680 timecounter_read(&fep->tc); 681 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 682 } 683 mutex_unlock(&fep->ptp_clk_mutex); 684 685 schedule_delayed_work(&fep->time_keep, HZ); 686 } 687 688 /* This function checks the pps event and reloads the timer compare counter. */ 689 static irqreturn_t fec_pps_interrupt(int irq, void *dev_id) 690 { 691 struct net_device *ndev = dev_id; 692 struct fec_enet_private *fep = netdev_priv(ndev); 693 u32 val; 694 u8 channel = fep->pps_channel; 695 struct ptp_clock_event event; 696 697 val = readl(fep->hwp + FEC_TCSR(channel)); 698 if (val & FEC_T_TF_MASK) { 699 /* Write the next next compare(not the next according the spec) 700 * value to the register 701 */ 702 writel(fep->next_counter, fep->hwp + FEC_TCCR(channel)); 703 do { 704 writel(val, fep->hwp + FEC_TCSR(channel)); 705 } while (readl(fep->hwp + FEC_TCSR(channel)) & FEC_T_TF_MASK); 706 707 /* Update the counter; */ 708 fep->next_counter = (fep->next_counter + fep->reload_period) & 709 fep->cc.mask; 710 711 event.type = PTP_CLOCK_PPS; 712 ptp_clock_event(fep->ptp_clock, &event); 713 return IRQ_HANDLED; 714 } 715 716 return IRQ_NONE; 717 } 718 719 /** 720 * fec_ptp_init 721 * @pdev: The FEC network adapter 722 * @irq_idx: the interrupt index 723 * 724 * This function performs the required steps for enabling ptp 725 * support. If ptp support has already been loaded it simply calls the 726 * cyclecounter init routine and exits. 727 */ 728 729 void fec_ptp_init(struct platform_device *pdev, int irq_idx) 730 { 731 struct net_device *ndev = platform_get_drvdata(pdev); 732 struct fec_enet_private *fep = netdev_priv(ndev); 733 int irq; 734 int ret; 735 736 fep->ptp_caps.owner = THIS_MODULE; 737 strscpy(fep->ptp_caps.name, "fec ptp", sizeof(fep->ptp_caps.name)); 738 739 fep->ptp_caps.max_adj = 250000000; 740 fep->ptp_caps.n_alarm = 0; 741 fep->ptp_caps.n_ext_ts = 0; 742 fep->ptp_caps.n_per_out = 1; 743 fep->ptp_caps.n_pins = 0; 744 fep->ptp_caps.pps = 1; 745 fep->ptp_caps.adjfreq = fec_ptp_adjfreq; 746 fep->ptp_caps.adjtime = fec_ptp_adjtime; 747 fep->ptp_caps.gettime64 = fec_ptp_gettime; 748 fep->ptp_caps.settime64 = fec_ptp_settime; 749 fep->ptp_caps.enable = fec_ptp_enable; 750 751 fep->cycle_speed = clk_get_rate(fep->clk_ptp); 752 if (!fep->cycle_speed) { 753 fep->cycle_speed = NSEC_PER_SEC; 754 dev_err(&fep->pdev->dev, "clk_ptp clock rate is zero\n"); 755 } 756 fep->ptp_inc = NSEC_PER_SEC / fep->cycle_speed; 757 758 spin_lock_init(&fep->tmreg_lock); 759 760 fec_ptp_start_cyclecounter(ndev); 761 762 INIT_DELAYED_WORK(&fep->time_keep, fec_time_keep); 763 764 hrtimer_init(&fep->perout_timer, CLOCK_REALTIME, HRTIMER_MODE_REL); 765 fep->perout_timer.function = fec_ptp_pps_perout_handler; 766 767 irq = platform_get_irq_byname_optional(pdev, "pps"); 768 if (irq < 0) 769 irq = platform_get_irq_optional(pdev, irq_idx); 770 /* Failure to get an irq is not fatal, 771 * only the PTP_CLOCK_PPS clock events should stop 772 */ 773 if (irq >= 0) { 774 ret = devm_request_irq(&pdev->dev, irq, fec_pps_interrupt, 775 0, pdev->name, ndev); 776 if (ret < 0) 777 dev_warn(&pdev->dev, "request for pps irq failed(%d)\n", 778 ret); 779 } 780 781 fep->ptp_clock = ptp_clock_register(&fep->ptp_caps, &pdev->dev); 782 if (IS_ERR(fep->ptp_clock)) { 783 fep->ptp_clock = NULL; 784 dev_err(&pdev->dev, "ptp_clock_register failed\n"); 785 } 786 787 schedule_delayed_work(&fep->time_keep, HZ); 788 } 789 790 void fec_ptp_stop(struct platform_device *pdev) 791 { 792 struct net_device *ndev = platform_get_drvdata(pdev); 793 struct fec_enet_private *fep = netdev_priv(ndev); 794 795 cancel_delayed_work_sync(&fep->time_keep); 796 hrtimer_cancel(&fep->perout_timer); 797 if (fep->ptp_clock) 798 ptp_clock_unregister(fep->ptp_clock); 799 } 800