1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/tso.h> 42 #include <linux/tcp.h> 43 #include <linux/udp.h> 44 #include <linux/icmp.h> 45 #include <linux/spinlock.h> 46 #include <linux/workqueue.h> 47 #include <linux/bitops.h> 48 #include <linux/io.h> 49 #include <linux/irq.h> 50 #include <linux/clk.h> 51 #include <linux/crc32.h> 52 #include <linux/platform_device.h> 53 #include <linux/mdio.h> 54 #include <linux/phy.h> 55 #include <linux/fec.h> 56 #include <linux/of.h> 57 #include <linux/of_device.h> 58 #include <linux/of_gpio.h> 59 #include <linux/of_mdio.h> 60 #include <linux/of_net.h> 61 #include <linux/regulator/consumer.h> 62 #include <linux/if_vlan.h> 63 #include <linux/pinctrl/consumer.h> 64 #include <linux/prefetch.h> 65 #include <linux/mfd/syscon.h> 66 #include <linux/regmap.h> 67 #include <soc/imx/cpuidle.h> 68 69 #include <asm/cacheflush.h> 70 71 #include "fec.h" 72 73 static void set_multicast_list(struct net_device *ndev); 74 static void fec_enet_itr_coal_init(struct net_device *ndev); 75 76 #define DRIVER_NAME "fec" 77 78 /* Pause frame feild and FIFO threshold */ 79 #define FEC_ENET_FCE (1 << 5) 80 #define FEC_ENET_RSEM_V 0x84 81 #define FEC_ENET_RSFL_V 16 82 #define FEC_ENET_RAEM_V 0x8 83 #define FEC_ENET_RAFL_V 0x8 84 #define FEC_ENET_OPD_V 0xFFF0 85 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 86 87 struct fec_devinfo { 88 u32 quirks; 89 }; 90 91 static const struct fec_devinfo fec_imx25_info = { 92 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 93 FEC_QUIRK_HAS_FRREG, 94 }; 95 96 static const struct fec_devinfo fec_imx27_info = { 97 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG, 98 }; 99 100 static const struct fec_devinfo fec_imx28_info = { 101 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 102 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 103 FEC_QUIRK_HAS_FRREG, 104 }; 105 106 static const struct fec_devinfo fec_imx6q_info = { 107 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 108 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 109 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 110 FEC_QUIRK_HAS_RACC, 111 }; 112 113 static const struct fec_devinfo fec_mvf600_info = { 114 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 115 }; 116 117 static const struct fec_devinfo fec_imx6x_info = { 118 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 119 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 120 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 121 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 122 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE, 123 }; 124 125 static const struct fec_devinfo fec_imx6ul_info = { 126 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 127 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 128 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 129 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 130 FEC_QUIRK_HAS_COALESCE, 131 }; 132 133 static struct platform_device_id fec_devtype[] = { 134 { 135 /* keep it for coldfire */ 136 .name = DRIVER_NAME, 137 .driver_data = 0, 138 }, { 139 .name = "imx25-fec", 140 .driver_data = (kernel_ulong_t)&fec_imx25_info, 141 }, { 142 .name = "imx27-fec", 143 .driver_data = (kernel_ulong_t)&fec_imx27_info, 144 }, { 145 .name = "imx28-fec", 146 .driver_data = (kernel_ulong_t)&fec_imx28_info, 147 }, { 148 .name = "imx6q-fec", 149 .driver_data = (kernel_ulong_t)&fec_imx6q_info, 150 }, { 151 .name = "mvf600-fec", 152 .driver_data = (kernel_ulong_t)&fec_mvf600_info, 153 }, { 154 .name = "imx6sx-fec", 155 .driver_data = (kernel_ulong_t)&fec_imx6x_info, 156 }, { 157 .name = "imx6ul-fec", 158 .driver_data = (kernel_ulong_t)&fec_imx6ul_info, 159 }, { 160 /* sentinel */ 161 } 162 }; 163 MODULE_DEVICE_TABLE(platform, fec_devtype); 164 165 enum imx_fec_type { 166 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 167 IMX27_FEC, /* runs on i.mx27/35/51 */ 168 IMX28_FEC, 169 IMX6Q_FEC, 170 MVF600_FEC, 171 IMX6SX_FEC, 172 IMX6UL_FEC, 173 }; 174 175 static const struct of_device_id fec_dt_ids[] = { 176 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 177 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 178 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 179 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 180 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 181 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 182 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 183 { /* sentinel */ } 184 }; 185 MODULE_DEVICE_TABLE(of, fec_dt_ids); 186 187 static unsigned char macaddr[ETH_ALEN]; 188 module_param_array(macaddr, byte, NULL, 0); 189 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 190 191 #if defined(CONFIG_M5272) 192 /* 193 * Some hardware gets it MAC address out of local flash memory. 194 * if this is non-zero then assume it is the address to get MAC from. 195 */ 196 #if defined(CONFIG_NETtel) 197 #define FEC_FLASHMAC 0xf0006006 198 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 199 #define FEC_FLASHMAC 0xf0006000 200 #elif defined(CONFIG_CANCam) 201 #define FEC_FLASHMAC 0xf0020000 202 #elif defined (CONFIG_M5272C3) 203 #define FEC_FLASHMAC (0xffe04000 + 4) 204 #elif defined(CONFIG_MOD5272) 205 #define FEC_FLASHMAC 0xffc0406b 206 #else 207 #define FEC_FLASHMAC 0 208 #endif 209 #endif /* CONFIG_M5272 */ 210 211 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 212 * 213 * 2048 byte skbufs are allocated. However, alignment requirements 214 * varies between FEC variants. Worst case is 64, so round down by 64. 215 */ 216 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 217 #define PKT_MINBUF_SIZE 64 218 219 /* FEC receive acceleration */ 220 #define FEC_RACC_IPDIS (1 << 1) 221 #define FEC_RACC_PRODIS (1 << 2) 222 #define FEC_RACC_SHIFT16 BIT(7) 223 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 224 225 /* MIB Control Register */ 226 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 227 228 /* 229 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 230 * size bits. Other FEC hardware does not, so we need to take that into 231 * account when setting it. 232 */ 233 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 234 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 235 defined(CONFIG_ARM64) 236 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 237 #else 238 #define OPT_FRAME_SIZE 0 239 #endif 240 241 /* FEC MII MMFR bits definition */ 242 #define FEC_MMFR_ST (1 << 30) 243 #define FEC_MMFR_ST_C45 (0) 244 #define FEC_MMFR_OP_READ (2 << 28) 245 #define FEC_MMFR_OP_READ_C45 (3 << 28) 246 #define FEC_MMFR_OP_WRITE (1 << 28) 247 #define FEC_MMFR_OP_ADDR_WRITE (0) 248 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 249 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 250 #define FEC_MMFR_TA (2 << 16) 251 #define FEC_MMFR_DATA(v) (v & 0xffff) 252 /* FEC ECR bits definition */ 253 #define FEC_ECR_MAGICEN (1 << 2) 254 #define FEC_ECR_SLEEP (1 << 3) 255 256 #define FEC_MII_TIMEOUT 30000 /* us */ 257 258 /* Transmitter timeout */ 259 #define TX_TIMEOUT (2 * HZ) 260 261 #define FEC_PAUSE_FLAG_AUTONEG 0x1 262 #define FEC_PAUSE_FLAG_ENABLE 0x2 263 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 264 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 265 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 266 267 #define COPYBREAK_DEFAULT 256 268 269 /* Max number of allowed TCP segments for software TSO */ 270 #define FEC_MAX_TSO_SEGS 100 271 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 272 273 #define IS_TSO_HEADER(txq, addr) \ 274 ((addr >= txq->tso_hdrs_dma) && \ 275 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 276 277 static int mii_cnt; 278 279 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 280 struct bufdesc_prop *bd) 281 { 282 return (bdp >= bd->last) ? bd->base 283 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 284 } 285 286 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 287 struct bufdesc_prop *bd) 288 { 289 return (bdp <= bd->base) ? bd->last 290 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 291 } 292 293 static int fec_enet_get_bd_index(struct bufdesc *bdp, 294 struct bufdesc_prop *bd) 295 { 296 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 297 } 298 299 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 300 { 301 int entries; 302 303 entries = (((const char *)txq->dirty_tx - 304 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 305 306 return entries >= 0 ? entries : entries + txq->bd.ring_size; 307 } 308 309 static void swap_buffer(void *bufaddr, int len) 310 { 311 int i; 312 unsigned int *buf = bufaddr; 313 314 for (i = 0; i < len; i += 4, buf++) 315 swab32s(buf); 316 } 317 318 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 319 { 320 int i; 321 unsigned int *src = src_buf; 322 unsigned int *dst = dst_buf; 323 324 for (i = 0; i < len; i += 4, src++, dst++) 325 *dst = swab32p(src); 326 } 327 328 static void fec_dump(struct net_device *ndev) 329 { 330 struct fec_enet_private *fep = netdev_priv(ndev); 331 struct bufdesc *bdp; 332 struct fec_enet_priv_tx_q *txq; 333 int index = 0; 334 335 netdev_info(ndev, "TX ring dump\n"); 336 pr_info("Nr SC addr len SKB\n"); 337 338 txq = fep->tx_queue[0]; 339 bdp = txq->bd.base; 340 341 do { 342 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 343 index, 344 bdp == txq->bd.cur ? 'S' : ' ', 345 bdp == txq->dirty_tx ? 'H' : ' ', 346 fec16_to_cpu(bdp->cbd_sc), 347 fec32_to_cpu(bdp->cbd_bufaddr), 348 fec16_to_cpu(bdp->cbd_datlen), 349 txq->tx_skbuff[index]); 350 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 351 index++; 352 } while (bdp != txq->bd.base); 353 } 354 355 static inline bool is_ipv4_pkt(struct sk_buff *skb) 356 { 357 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 358 } 359 360 static int 361 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 362 { 363 /* Only run for packets requiring a checksum. */ 364 if (skb->ip_summed != CHECKSUM_PARTIAL) 365 return 0; 366 367 if (unlikely(skb_cow_head(skb, 0))) 368 return -1; 369 370 if (is_ipv4_pkt(skb)) 371 ip_hdr(skb)->check = 0; 372 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 373 374 return 0; 375 } 376 377 static struct bufdesc * 378 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 379 struct sk_buff *skb, 380 struct net_device *ndev) 381 { 382 struct fec_enet_private *fep = netdev_priv(ndev); 383 struct bufdesc *bdp = txq->bd.cur; 384 struct bufdesc_ex *ebdp; 385 int nr_frags = skb_shinfo(skb)->nr_frags; 386 int frag, frag_len; 387 unsigned short status; 388 unsigned int estatus = 0; 389 skb_frag_t *this_frag; 390 unsigned int index; 391 void *bufaddr; 392 dma_addr_t addr; 393 int i; 394 395 for (frag = 0; frag < nr_frags; frag++) { 396 this_frag = &skb_shinfo(skb)->frags[frag]; 397 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 398 ebdp = (struct bufdesc_ex *)bdp; 399 400 status = fec16_to_cpu(bdp->cbd_sc); 401 status &= ~BD_ENET_TX_STATS; 402 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 403 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 404 405 /* Handle the last BD specially */ 406 if (frag == nr_frags - 1) { 407 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 408 if (fep->bufdesc_ex) { 409 estatus |= BD_ENET_TX_INT; 410 if (unlikely(skb_shinfo(skb)->tx_flags & 411 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 412 estatus |= BD_ENET_TX_TS; 413 } 414 } 415 416 if (fep->bufdesc_ex) { 417 if (fep->quirks & FEC_QUIRK_HAS_AVB) 418 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 419 if (skb->ip_summed == CHECKSUM_PARTIAL) 420 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 421 ebdp->cbd_bdu = 0; 422 ebdp->cbd_esc = cpu_to_fec32(estatus); 423 } 424 425 bufaddr = skb_frag_address(this_frag); 426 427 index = fec_enet_get_bd_index(bdp, &txq->bd); 428 if (((unsigned long) bufaddr) & fep->tx_align || 429 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 430 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 431 bufaddr = txq->tx_bounce[index]; 432 433 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 434 swap_buffer(bufaddr, frag_len); 435 } 436 437 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 438 DMA_TO_DEVICE); 439 if (dma_mapping_error(&fep->pdev->dev, addr)) { 440 if (net_ratelimit()) 441 netdev_err(ndev, "Tx DMA memory map failed\n"); 442 goto dma_mapping_error; 443 } 444 445 bdp->cbd_bufaddr = cpu_to_fec32(addr); 446 bdp->cbd_datlen = cpu_to_fec16(frag_len); 447 /* Make sure the updates to rest of the descriptor are 448 * performed before transferring ownership. 449 */ 450 wmb(); 451 bdp->cbd_sc = cpu_to_fec16(status); 452 } 453 454 return bdp; 455 dma_mapping_error: 456 bdp = txq->bd.cur; 457 for (i = 0; i < frag; i++) { 458 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 459 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 460 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 461 } 462 return ERR_PTR(-ENOMEM); 463 } 464 465 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 466 struct sk_buff *skb, struct net_device *ndev) 467 { 468 struct fec_enet_private *fep = netdev_priv(ndev); 469 int nr_frags = skb_shinfo(skb)->nr_frags; 470 struct bufdesc *bdp, *last_bdp; 471 void *bufaddr; 472 dma_addr_t addr; 473 unsigned short status; 474 unsigned short buflen; 475 unsigned int estatus = 0; 476 unsigned int index; 477 int entries_free; 478 479 entries_free = fec_enet_get_free_txdesc_num(txq); 480 if (entries_free < MAX_SKB_FRAGS + 1) { 481 dev_kfree_skb_any(skb); 482 if (net_ratelimit()) 483 netdev_err(ndev, "NOT enough BD for SG!\n"); 484 return NETDEV_TX_OK; 485 } 486 487 /* Protocol checksum off-load for TCP and UDP. */ 488 if (fec_enet_clear_csum(skb, ndev)) { 489 dev_kfree_skb_any(skb); 490 return NETDEV_TX_OK; 491 } 492 493 /* Fill in a Tx ring entry */ 494 bdp = txq->bd.cur; 495 last_bdp = bdp; 496 status = fec16_to_cpu(bdp->cbd_sc); 497 status &= ~BD_ENET_TX_STATS; 498 499 /* Set buffer length and buffer pointer */ 500 bufaddr = skb->data; 501 buflen = skb_headlen(skb); 502 503 index = fec_enet_get_bd_index(bdp, &txq->bd); 504 if (((unsigned long) bufaddr) & fep->tx_align || 505 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 506 memcpy(txq->tx_bounce[index], skb->data, buflen); 507 bufaddr = txq->tx_bounce[index]; 508 509 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 510 swap_buffer(bufaddr, buflen); 511 } 512 513 /* Push the data cache so the CPM does not get stale memory data. */ 514 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 515 if (dma_mapping_error(&fep->pdev->dev, addr)) { 516 dev_kfree_skb_any(skb); 517 if (net_ratelimit()) 518 netdev_err(ndev, "Tx DMA memory map failed\n"); 519 return NETDEV_TX_OK; 520 } 521 522 if (nr_frags) { 523 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 524 if (IS_ERR(last_bdp)) { 525 dma_unmap_single(&fep->pdev->dev, addr, 526 buflen, DMA_TO_DEVICE); 527 dev_kfree_skb_any(skb); 528 return NETDEV_TX_OK; 529 } 530 } else { 531 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 532 if (fep->bufdesc_ex) { 533 estatus = BD_ENET_TX_INT; 534 if (unlikely(skb_shinfo(skb)->tx_flags & 535 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 536 estatus |= BD_ENET_TX_TS; 537 } 538 } 539 bdp->cbd_bufaddr = cpu_to_fec32(addr); 540 bdp->cbd_datlen = cpu_to_fec16(buflen); 541 542 if (fep->bufdesc_ex) { 543 544 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 545 546 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 547 fep->hwts_tx_en)) 548 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 549 550 if (fep->quirks & FEC_QUIRK_HAS_AVB) 551 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 552 553 if (skb->ip_summed == CHECKSUM_PARTIAL) 554 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 555 556 ebdp->cbd_bdu = 0; 557 ebdp->cbd_esc = cpu_to_fec32(estatus); 558 } 559 560 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 561 /* Save skb pointer */ 562 txq->tx_skbuff[index] = skb; 563 564 /* Make sure the updates to rest of the descriptor are performed before 565 * transferring ownership. 566 */ 567 wmb(); 568 569 /* Send it on its way. Tell FEC it's ready, interrupt when done, 570 * it's the last BD of the frame, and to put the CRC on the end. 571 */ 572 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 573 bdp->cbd_sc = cpu_to_fec16(status); 574 575 /* If this was the last BD in the ring, start at the beginning again. */ 576 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 577 578 skb_tx_timestamp(skb); 579 580 /* Make sure the update to bdp and tx_skbuff are performed before 581 * txq->bd.cur. 582 */ 583 wmb(); 584 txq->bd.cur = bdp; 585 586 /* Trigger transmission start */ 587 writel(0, txq->bd.reg_desc_active); 588 589 return 0; 590 } 591 592 static int 593 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 594 struct net_device *ndev, 595 struct bufdesc *bdp, int index, char *data, 596 int size, bool last_tcp, bool is_last) 597 { 598 struct fec_enet_private *fep = netdev_priv(ndev); 599 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 600 unsigned short status; 601 unsigned int estatus = 0; 602 dma_addr_t addr; 603 604 status = fec16_to_cpu(bdp->cbd_sc); 605 status &= ~BD_ENET_TX_STATS; 606 607 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 608 609 if (((unsigned long) data) & fep->tx_align || 610 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 611 memcpy(txq->tx_bounce[index], data, size); 612 data = txq->tx_bounce[index]; 613 614 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 615 swap_buffer(data, size); 616 } 617 618 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 619 if (dma_mapping_error(&fep->pdev->dev, addr)) { 620 dev_kfree_skb_any(skb); 621 if (net_ratelimit()) 622 netdev_err(ndev, "Tx DMA memory map failed\n"); 623 return NETDEV_TX_BUSY; 624 } 625 626 bdp->cbd_datlen = cpu_to_fec16(size); 627 bdp->cbd_bufaddr = cpu_to_fec32(addr); 628 629 if (fep->bufdesc_ex) { 630 if (fep->quirks & FEC_QUIRK_HAS_AVB) 631 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 632 if (skb->ip_summed == CHECKSUM_PARTIAL) 633 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 634 ebdp->cbd_bdu = 0; 635 ebdp->cbd_esc = cpu_to_fec32(estatus); 636 } 637 638 /* Handle the last BD specially */ 639 if (last_tcp) 640 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 641 if (is_last) { 642 status |= BD_ENET_TX_INTR; 643 if (fep->bufdesc_ex) 644 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 645 } 646 647 bdp->cbd_sc = cpu_to_fec16(status); 648 649 return 0; 650 } 651 652 static int 653 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 654 struct sk_buff *skb, struct net_device *ndev, 655 struct bufdesc *bdp, int index) 656 { 657 struct fec_enet_private *fep = netdev_priv(ndev); 658 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 659 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 660 void *bufaddr; 661 unsigned long dmabuf; 662 unsigned short status; 663 unsigned int estatus = 0; 664 665 status = fec16_to_cpu(bdp->cbd_sc); 666 status &= ~BD_ENET_TX_STATS; 667 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 668 669 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 670 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 671 if (((unsigned long)bufaddr) & fep->tx_align || 672 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 673 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 674 bufaddr = txq->tx_bounce[index]; 675 676 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 677 swap_buffer(bufaddr, hdr_len); 678 679 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 680 hdr_len, DMA_TO_DEVICE); 681 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 682 dev_kfree_skb_any(skb); 683 if (net_ratelimit()) 684 netdev_err(ndev, "Tx DMA memory map failed\n"); 685 return NETDEV_TX_BUSY; 686 } 687 } 688 689 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 690 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 691 692 if (fep->bufdesc_ex) { 693 if (fep->quirks & FEC_QUIRK_HAS_AVB) 694 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 695 if (skb->ip_summed == CHECKSUM_PARTIAL) 696 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 697 ebdp->cbd_bdu = 0; 698 ebdp->cbd_esc = cpu_to_fec32(estatus); 699 } 700 701 bdp->cbd_sc = cpu_to_fec16(status); 702 703 return 0; 704 } 705 706 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 707 struct sk_buff *skb, 708 struct net_device *ndev) 709 { 710 struct fec_enet_private *fep = netdev_priv(ndev); 711 int hdr_len, total_len, data_left; 712 struct bufdesc *bdp = txq->bd.cur; 713 struct tso_t tso; 714 unsigned int index = 0; 715 int ret; 716 717 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 718 dev_kfree_skb_any(skb); 719 if (net_ratelimit()) 720 netdev_err(ndev, "NOT enough BD for TSO!\n"); 721 return NETDEV_TX_OK; 722 } 723 724 /* Protocol checksum off-load for TCP and UDP. */ 725 if (fec_enet_clear_csum(skb, ndev)) { 726 dev_kfree_skb_any(skb); 727 return NETDEV_TX_OK; 728 } 729 730 /* Initialize the TSO handler, and prepare the first payload */ 731 hdr_len = tso_start(skb, &tso); 732 733 total_len = skb->len - hdr_len; 734 while (total_len > 0) { 735 char *hdr; 736 737 index = fec_enet_get_bd_index(bdp, &txq->bd); 738 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 739 total_len -= data_left; 740 741 /* prepare packet headers: MAC + IP + TCP */ 742 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 743 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 744 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 745 if (ret) 746 goto err_release; 747 748 while (data_left > 0) { 749 int size; 750 751 size = min_t(int, tso.size, data_left); 752 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 753 index = fec_enet_get_bd_index(bdp, &txq->bd); 754 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 755 bdp, index, 756 tso.data, size, 757 size == data_left, 758 total_len == 0); 759 if (ret) 760 goto err_release; 761 762 data_left -= size; 763 tso_build_data(skb, &tso, size); 764 } 765 766 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 767 } 768 769 /* Save skb pointer */ 770 txq->tx_skbuff[index] = skb; 771 772 skb_tx_timestamp(skb); 773 txq->bd.cur = bdp; 774 775 /* Trigger transmission start */ 776 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 777 !readl(txq->bd.reg_desc_active) || 778 !readl(txq->bd.reg_desc_active) || 779 !readl(txq->bd.reg_desc_active) || 780 !readl(txq->bd.reg_desc_active)) 781 writel(0, txq->bd.reg_desc_active); 782 783 return 0; 784 785 err_release: 786 /* TODO: Release all used data descriptors for TSO */ 787 return ret; 788 } 789 790 static netdev_tx_t 791 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 792 { 793 struct fec_enet_private *fep = netdev_priv(ndev); 794 int entries_free; 795 unsigned short queue; 796 struct fec_enet_priv_tx_q *txq; 797 struct netdev_queue *nq; 798 int ret; 799 800 queue = skb_get_queue_mapping(skb); 801 txq = fep->tx_queue[queue]; 802 nq = netdev_get_tx_queue(ndev, queue); 803 804 if (skb_is_gso(skb)) 805 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 806 else 807 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 808 if (ret) 809 return ret; 810 811 entries_free = fec_enet_get_free_txdesc_num(txq); 812 if (entries_free <= txq->tx_stop_threshold) 813 netif_tx_stop_queue(nq); 814 815 return NETDEV_TX_OK; 816 } 817 818 /* Init RX & TX buffer descriptors 819 */ 820 static void fec_enet_bd_init(struct net_device *dev) 821 { 822 struct fec_enet_private *fep = netdev_priv(dev); 823 struct fec_enet_priv_tx_q *txq; 824 struct fec_enet_priv_rx_q *rxq; 825 struct bufdesc *bdp; 826 unsigned int i; 827 unsigned int q; 828 829 for (q = 0; q < fep->num_rx_queues; q++) { 830 /* Initialize the receive buffer descriptors. */ 831 rxq = fep->rx_queue[q]; 832 bdp = rxq->bd.base; 833 834 for (i = 0; i < rxq->bd.ring_size; i++) { 835 836 /* Initialize the BD for every fragment in the page. */ 837 if (bdp->cbd_bufaddr) 838 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 839 else 840 bdp->cbd_sc = cpu_to_fec16(0); 841 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 842 } 843 844 /* Set the last buffer to wrap */ 845 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 846 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 847 848 rxq->bd.cur = rxq->bd.base; 849 } 850 851 for (q = 0; q < fep->num_tx_queues; q++) { 852 /* ...and the same for transmit */ 853 txq = fep->tx_queue[q]; 854 bdp = txq->bd.base; 855 txq->bd.cur = bdp; 856 857 for (i = 0; i < txq->bd.ring_size; i++) { 858 /* Initialize the BD for every fragment in the page. */ 859 bdp->cbd_sc = cpu_to_fec16(0); 860 if (bdp->cbd_bufaddr && 861 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 862 dma_unmap_single(&fep->pdev->dev, 863 fec32_to_cpu(bdp->cbd_bufaddr), 864 fec16_to_cpu(bdp->cbd_datlen), 865 DMA_TO_DEVICE); 866 if (txq->tx_skbuff[i]) { 867 dev_kfree_skb_any(txq->tx_skbuff[i]); 868 txq->tx_skbuff[i] = NULL; 869 } 870 bdp->cbd_bufaddr = cpu_to_fec32(0); 871 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 872 } 873 874 /* Set the last buffer to wrap */ 875 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 876 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 877 txq->dirty_tx = bdp; 878 } 879 } 880 881 static void fec_enet_active_rxring(struct net_device *ndev) 882 { 883 struct fec_enet_private *fep = netdev_priv(ndev); 884 int i; 885 886 for (i = 0; i < fep->num_rx_queues; i++) 887 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 888 } 889 890 static void fec_enet_enable_ring(struct net_device *ndev) 891 { 892 struct fec_enet_private *fep = netdev_priv(ndev); 893 struct fec_enet_priv_tx_q *txq; 894 struct fec_enet_priv_rx_q *rxq; 895 int i; 896 897 for (i = 0; i < fep->num_rx_queues; i++) { 898 rxq = fep->rx_queue[i]; 899 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 900 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 901 902 /* enable DMA1/2 */ 903 if (i) 904 writel(RCMR_MATCHEN | RCMR_CMP(i), 905 fep->hwp + FEC_RCMR(i)); 906 } 907 908 for (i = 0; i < fep->num_tx_queues; i++) { 909 txq = fep->tx_queue[i]; 910 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 911 912 /* enable DMA1/2 */ 913 if (i) 914 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 915 fep->hwp + FEC_DMA_CFG(i)); 916 } 917 } 918 919 static void fec_enet_reset_skb(struct net_device *ndev) 920 { 921 struct fec_enet_private *fep = netdev_priv(ndev); 922 struct fec_enet_priv_tx_q *txq; 923 int i, j; 924 925 for (i = 0; i < fep->num_tx_queues; i++) { 926 txq = fep->tx_queue[i]; 927 928 for (j = 0; j < txq->bd.ring_size; j++) { 929 if (txq->tx_skbuff[j]) { 930 dev_kfree_skb_any(txq->tx_skbuff[j]); 931 txq->tx_skbuff[j] = NULL; 932 } 933 } 934 } 935 } 936 937 /* 938 * This function is called to start or restart the FEC during a link 939 * change, transmit timeout, or to reconfigure the FEC. The network 940 * packet processing for this device must be stopped before this call. 941 */ 942 static void 943 fec_restart(struct net_device *ndev) 944 { 945 struct fec_enet_private *fep = netdev_priv(ndev); 946 u32 val; 947 u32 temp_mac[2]; 948 u32 rcntl = OPT_FRAME_SIZE | 0x04; 949 u32 ecntl = 0x2; /* ETHEREN */ 950 951 /* Whack a reset. We should wait for this. 952 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 953 * instead of reset MAC itself. 954 */ 955 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 956 writel(0, fep->hwp + FEC_ECNTRL); 957 } else { 958 writel(1, fep->hwp + FEC_ECNTRL); 959 udelay(10); 960 } 961 962 /* 963 * enet-mac reset will reset mac address registers too, 964 * so need to reconfigure it. 965 */ 966 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 967 writel((__force u32)cpu_to_be32(temp_mac[0]), 968 fep->hwp + FEC_ADDR_LOW); 969 writel((__force u32)cpu_to_be32(temp_mac[1]), 970 fep->hwp + FEC_ADDR_HIGH); 971 972 /* Clear any outstanding interrupt, except MDIO. */ 973 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 974 975 fec_enet_bd_init(ndev); 976 977 fec_enet_enable_ring(ndev); 978 979 /* Reset tx SKB buffers. */ 980 fec_enet_reset_skb(ndev); 981 982 /* Enable MII mode */ 983 if (fep->full_duplex == DUPLEX_FULL) { 984 /* FD enable */ 985 writel(0x04, fep->hwp + FEC_X_CNTRL); 986 } else { 987 /* No Rcv on Xmit */ 988 rcntl |= 0x02; 989 writel(0x0, fep->hwp + FEC_X_CNTRL); 990 } 991 992 /* Set MII speed */ 993 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 994 995 #if !defined(CONFIG_M5272) 996 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 997 val = readl(fep->hwp + FEC_RACC); 998 /* align IP header */ 999 val |= FEC_RACC_SHIFT16; 1000 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1001 /* set RX checksum */ 1002 val |= FEC_RACC_OPTIONS; 1003 else 1004 val &= ~FEC_RACC_OPTIONS; 1005 writel(val, fep->hwp + FEC_RACC); 1006 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1007 } 1008 #endif 1009 1010 /* 1011 * The phy interface and speed need to get configured 1012 * differently on enet-mac. 1013 */ 1014 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1015 /* Enable flow control and length check */ 1016 rcntl |= 0x40000000 | 0x00000020; 1017 1018 /* RGMII, RMII or MII */ 1019 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1020 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1021 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1022 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1023 rcntl |= (1 << 6); 1024 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1025 rcntl |= (1 << 8); 1026 else 1027 rcntl &= ~(1 << 8); 1028 1029 /* 1G, 100M or 10M */ 1030 if (ndev->phydev) { 1031 if (ndev->phydev->speed == SPEED_1000) 1032 ecntl |= (1 << 5); 1033 else if (ndev->phydev->speed == SPEED_100) 1034 rcntl &= ~(1 << 9); 1035 else 1036 rcntl |= (1 << 9); 1037 } 1038 } else { 1039 #ifdef FEC_MIIGSK_ENR 1040 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1041 u32 cfgr; 1042 /* disable the gasket and wait */ 1043 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1044 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1045 udelay(1); 1046 1047 /* 1048 * configure the gasket: 1049 * RMII, 50 MHz, no loopback, no echo 1050 * MII, 25 MHz, no loopback, no echo 1051 */ 1052 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1053 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1054 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1055 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1056 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1057 1058 /* re-enable the gasket */ 1059 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1060 } 1061 #endif 1062 } 1063 1064 #if !defined(CONFIG_M5272) 1065 /* enable pause frame*/ 1066 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1067 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1068 ndev->phydev && ndev->phydev->pause)) { 1069 rcntl |= FEC_ENET_FCE; 1070 1071 /* set FIFO threshold parameter to reduce overrun */ 1072 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1073 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1074 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1075 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1076 1077 /* OPD */ 1078 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1079 } else { 1080 rcntl &= ~FEC_ENET_FCE; 1081 } 1082 #endif /* !defined(CONFIG_M5272) */ 1083 1084 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1085 1086 /* Setup multicast filter. */ 1087 set_multicast_list(ndev); 1088 #ifndef CONFIG_M5272 1089 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1090 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1091 #endif 1092 1093 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1094 /* enable ENET endian swap */ 1095 ecntl |= (1 << 8); 1096 /* enable ENET store and forward mode */ 1097 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1098 } 1099 1100 if (fep->bufdesc_ex) 1101 ecntl |= (1 << 4); 1102 1103 #ifndef CONFIG_M5272 1104 /* Enable the MIB statistic event counters */ 1105 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1106 #endif 1107 1108 /* And last, enable the transmit and receive processing */ 1109 writel(ecntl, fep->hwp + FEC_ECNTRL); 1110 fec_enet_active_rxring(ndev); 1111 1112 if (fep->bufdesc_ex) 1113 fec_ptp_start_cyclecounter(ndev); 1114 1115 /* Enable interrupts we wish to service */ 1116 if (fep->link) 1117 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1118 else 1119 writel(0, fep->hwp + FEC_IMASK); 1120 1121 /* Init the interrupt coalescing */ 1122 fec_enet_itr_coal_init(ndev); 1123 1124 } 1125 1126 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1127 { 1128 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1129 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1130 1131 if (stop_gpr->gpr) { 1132 if (enabled) 1133 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1134 BIT(stop_gpr->bit), 1135 BIT(stop_gpr->bit)); 1136 else 1137 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1138 BIT(stop_gpr->bit), 0); 1139 } else if (pdata && pdata->sleep_mode_enable) { 1140 pdata->sleep_mode_enable(enabled); 1141 } 1142 } 1143 1144 static void 1145 fec_stop(struct net_device *ndev) 1146 { 1147 struct fec_enet_private *fep = netdev_priv(ndev); 1148 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1149 u32 val; 1150 1151 /* We cannot expect a graceful transmit stop without link !!! */ 1152 if (fep->link) { 1153 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1154 udelay(10); 1155 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1156 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1157 } 1158 1159 /* Whack a reset. We should wait for this. 1160 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1161 * instead of reset MAC itself. 1162 */ 1163 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1164 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 1165 writel(0, fep->hwp + FEC_ECNTRL); 1166 } else { 1167 writel(1, fep->hwp + FEC_ECNTRL); 1168 udelay(10); 1169 } 1170 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1171 } else { 1172 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1173 val = readl(fep->hwp + FEC_ECNTRL); 1174 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1175 writel(val, fep->hwp + FEC_ECNTRL); 1176 fec_enet_stop_mode(fep, true); 1177 } 1178 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1179 1180 /* We have to keep ENET enabled to have MII interrupt stay working */ 1181 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1182 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1183 writel(2, fep->hwp + FEC_ECNTRL); 1184 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1185 } 1186 } 1187 1188 1189 static void 1190 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1191 { 1192 struct fec_enet_private *fep = netdev_priv(ndev); 1193 1194 fec_dump(ndev); 1195 1196 ndev->stats.tx_errors++; 1197 1198 schedule_work(&fep->tx_timeout_work); 1199 } 1200 1201 static void fec_enet_timeout_work(struct work_struct *work) 1202 { 1203 struct fec_enet_private *fep = 1204 container_of(work, struct fec_enet_private, tx_timeout_work); 1205 struct net_device *ndev = fep->netdev; 1206 1207 rtnl_lock(); 1208 if (netif_device_present(ndev) || netif_running(ndev)) { 1209 napi_disable(&fep->napi); 1210 netif_tx_lock_bh(ndev); 1211 fec_restart(ndev); 1212 netif_tx_wake_all_queues(ndev); 1213 netif_tx_unlock_bh(ndev); 1214 napi_enable(&fep->napi); 1215 } 1216 rtnl_unlock(); 1217 } 1218 1219 static void 1220 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1221 struct skb_shared_hwtstamps *hwtstamps) 1222 { 1223 unsigned long flags; 1224 u64 ns; 1225 1226 spin_lock_irqsave(&fep->tmreg_lock, flags); 1227 ns = timecounter_cyc2time(&fep->tc, ts); 1228 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1229 1230 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1231 hwtstamps->hwtstamp = ns_to_ktime(ns); 1232 } 1233 1234 static void 1235 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1236 { 1237 struct fec_enet_private *fep; 1238 struct bufdesc *bdp; 1239 unsigned short status; 1240 struct sk_buff *skb; 1241 struct fec_enet_priv_tx_q *txq; 1242 struct netdev_queue *nq; 1243 int index = 0; 1244 int entries_free; 1245 1246 fep = netdev_priv(ndev); 1247 1248 txq = fep->tx_queue[queue_id]; 1249 /* get next bdp of dirty_tx */ 1250 nq = netdev_get_tx_queue(ndev, queue_id); 1251 bdp = txq->dirty_tx; 1252 1253 /* get next bdp of dirty_tx */ 1254 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1255 1256 while (bdp != READ_ONCE(txq->bd.cur)) { 1257 /* Order the load of bd.cur and cbd_sc */ 1258 rmb(); 1259 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1260 if (status & BD_ENET_TX_READY) 1261 break; 1262 1263 index = fec_enet_get_bd_index(bdp, &txq->bd); 1264 1265 skb = txq->tx_skbuff[index]; 1266 txq->tx_skbuff[index] = NULL; 1267 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1268 dma_unmap_single(&fep->pdev->dev, 1269 fec32_to_cpu(bdp->cbd_bufaddr), 1270 fec16_to_cpu(bdp->cbd_datlen), 1271 DMA_TO_DEVICE); 1272 bdp->cbd_bufaddr = cpu_to_fec32(0); 1273 if (!skb) 1274 goto skb_done; 1275 1276 /* Check for errors. */ 1277 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1278 BD_ENET_TX_RL | BD_ENET_TX_UN | 1279 BD_ENET_TX_CSL)) { 1280 ndev->stats.tx_errors++; 1281 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1282 ndev->stats.tx_heartbeat_errors++; 1283 if (status & BD_ENET_TX_LC) /* Late collision */ 1284 ndev->stats.tx_window_errors++; 1285 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1286 ndev->stats.tx_aborted_errors++; 1287 if (status & BD_ENET_TX_UN) /* Underrun */ 1288 ndev->stats.tx_fifo_errors++; 1289 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1290 ndev->stats.tx_carrier_errors++; 1291 } else { 1292 ndev->stats.tx_packets++; 1293 ndev->stats.tx_bytes += skb->len; 1294 } 1295 1296 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1297 * are to time stamp the packet, so we still need to check time 1298 * stamping enabled flag. 1299 */ 1300 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1301 fep->hwts_tx_en) && 1302 fep->bufdesc_ex) { 1303 struct skb_shared_hwtstamps shhwtstamps; 1304 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1305 1306 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1307 skb_tstamp_tx(skb, &shhwtstamps); 1308 } 1309 1310 /* Deferred means some collisions occurred during transmit, 1311 * but we eventually sent the packet OK. 1312 */ 1313 if (status & BD_ENET_TX_DEF) 1314 ndev->stats.collisions++; 1315 1316 /* Free the sk buffer associated with this last transmit */ 1317 dev_kfree_skb_any(skb); 1318 skb_done: 1319 /* Make sure the update to bdp and tx_skbuff are performed 1320 * before dirty_tx 1321 */ 1322 wmb(); 1323 txq->dirty_tx = bdp; 1324 1325 /* Update pointer to next buffer descriptor to be transmitted */ 1326 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1327 1328 /* Since we have freed up a buffer, the ring is no longer full 1329 */ 1330 if (netif_tx_queue_stopped(nq)) { 1331 entries_free = fec_enet_get_free_txdesc_num(txq); 1332 if (entries_free >= txq->tx_wake_threshold) 1333 netif_tx_wake_queue(nq); 1334 } 1335 } 1336 1337 /* ERR006358: Keep the transmitter going */ 1338 if (bdp != txq->bd.cur && 1339 readl(txq->bd.reg_desc_active) == 0) 1340 writel(0, txq->bd.reg_desc_active); 1341 } 1342 1343 static void fec_enet_tx(struct net_device *ndev) 1344 { 1345 struct fec_enet_private *fep = netdev_priv(ndev); 1346 int i; 1347 1348 /* Make sure that AVB queues are processed first. */ 1349 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1350 fec_enet_tx_queue(ndev, i); 1351 } 1352 1353 static int 1354 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1355 { 1356 struct fec_enet_private *fep = netdev_priv(ndev); 1357 int off; 1358 1359 off = ((unsigned long)skb->data) & fep->rx_align; 1360 if (off) 1361 skb_reserve(skb, fep->rx_align + 1 - off); 1362 1363 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1364 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1365 if (net_ratelimit()) 1366 netdev_err(ndev, "Rx DMA memory map failed\n"); 1367 return -ENOMEM; 1368 } 1369 1370 return 0; 1371 } 1372 1373 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1374 struct bufdesc *bdp, u32 length, bool swap) 1375 { 1376 struct fec_enet_private *fep = netdev_priv(ndev); 1377 struct sk_buff *new_skb; 1378 1379 if (length > fep->rx_copybreak) 1380 return false; 1381 1382 new_skb = netdev_alloc_skb(ndev, length); 1383 if (!new_skb) 1384 return false; 1385 1386 dma_sync_single_for_cpu(&fep->pdev->dev, 1387 fec32_to_cpu(bdp->cbd_bufaddr), 1388 FEC_ENET_RX_FRSIZE - fep->rx_align, 1389 DMA_FROM_DEVICE); 1390 if (!swap) 1391 memcpy(new_skb->data, (*skb)->data, length); 1392 else 1393 swap_buffer2(new_skb->data, (*skb)->data, length); 1394 *skb = new_skb; 1395 1396 return true; 1397 } 1398 1399 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1400 * When we update through the ring, if the next incoming buffer has 1401 * not been given to the system, we just set the empty indicator, 1402 * effectively tossing the packet. 1403 */ 1404 static int 1405 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1406 { 1407 struct fec_enet_private *fep = netdev_priv(ndev); 1408 struct fec_enet_priv_rx_q *rxq; 1409 struct bufdesc *bdp; 1410 unsigned short status; 1411 struct sk_buff *skb_new = NULL; 1412 struct sk_buff *skb; 1413 ushort pkt_len; 1414 __u8 *data; 1415 int pkt_received = 0; 1416 struct bufdesc_ex *ebdp = NULL; 1417 bool vlan_packet_rcvd = false; 1418 u16 vlan_tag; 1419 int index = 0; 1420 bool is_copybreak; 1421 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1422 1423 #ifdef CONFIG_M532x 1424 flush_cache_all(); 1425 #endif 1426 rxq = fep->rx_queue[queue_id]; 1427 1428 /* First, grab all of the stats for the incoming packet. 1429 * These get messed up if we get called due to a busy condition. 1430 */ 1431 bdp = rxq->bd.cur; 1432 1433 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1434 1435 if (pkt_received >= budget) 1436 break; 1437 pkt_received++; 1438 1439 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); 1440 1441 /* Check for errors. */ 1442 status ^= BD_ENET_RX_LAST; 1443 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1444 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1445 BD_ENET_RX_CL)) { 1446 ndev->stats.rx_errors++; 1447 if (status & BD_ENET_RX_OV) { 1448 /* FIFO overrun */ 1449 ndev->stats.rx_fifo_errors++; 1450 goto rx_processing_done; 1451 } 1452 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1453 | BD_ENET_RX_LAST)) { 1454 /* Frame too long or too short. */ 1455 ndev->stats.rx_length_errors++; 1456 if (status & BD_ENET_RX_LAST) 1457 netdev_err(ndev, "rcv is not +last\n"); 1458 } 1459 if (status & BD_ENET_RX_CR) /* CRC Error */ 1460 ndev->stats.rx_crc_errors++; 1461 /* Report late collisions as a frame error. */ 1462 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1463 ndev->stats.rx_frame_errors++; 1464 goto rx_processing_done; 1465 } 1466 1467 /* Process the incoming frame. */ 1468 ndev->stats.rx_packets++; 1469 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1470 ndev->stats.rx_bytes += pkt_len; 1471 1472 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1473 skb = rxq->rx_skbuff[index]; 1474 1475 /* The packet length includes FCS, but we don't want to 1476 * include that when passing upstream as it messes up 1477 * bridging applications. 1478 */ 1479 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1480 need_swap); 1481 if (!is_copybreak) { 1482 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1483 if (unlikely(!skb_new)) { 1484 ndev->stats.rx_dropped++; 1485 goto rx_processing_done; 1486 } 1487 dma_unmap_single(&fep->pdev->dev, 1488 fec32_to_cpu(bdp->cbd_bufaddr), 1489 FEC_ENET_RX_FRSIZE - fep->rx_align, 1490 DMA_FROM_DEVICE); 1491 } 1492 1493 prefetch(skb->data - NET_IP_ALIGN); 1494 skb_put(skb, pkt_len - 4); 1495 data = skb->data; 1496 1497 if (!is_copybreak && need_swap) 1498 swap_buffer(data, pkt_len); 1499 1500 #if !defined(CONFIG_M5272) 1501 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1502 data = skb_pull_inline(skb, 2); 1503 #endif 1504 1505 /* Extract the enhanced buffer descriptor */ 1506 ebdp = NULL; 1507 if (fep->bufdesc_ex) 1508 ebdp = (struct bufdesc_ex *)bdp; 1509 1510 /* If this is a VLAN packet remove the VLAN Tag */ 1511 vlan_packet_rcvd = false; 1512 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1513 fep->bufdesc_ex && 1514 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1515 /* Push and remove the vlan tag */ 1516 struct vlan_hdr *vlan_header = 1517 (struct vlan_hdr *) (data + ETH_HLEN); 1518 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1519 1520 vlan_packet_rcvd = true; 1521 1522 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1523 skb_pull(skb, VLAN_HLEN); 1524 } 1525 1526 skb->protocol = eth_type_trans(skb, ndev); 1527 1528 /* Get receive timestamp from the skb */ 1529 if (fep->hwts_rx_en && fep->bufdesc_ex) 1530 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1531 skb_hwtstamps(skb)); 1532 1533 if (fep->bufdesc_ex && 1534 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1535 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1536 /* don't check it */ 1537 skb->ip_summed = CHECKSUM_UNNECESSARY; 1538 } else { 1539 skb_checksum_none_assert(skb); 1540 } 1541 } 1542 1543 /* Handle received VLAN packets */ 1544 if (vlan_packet_rcvd) 1545 __vlan_hwaccel_put_tag(skb, 1546 htons(ETH_P_8021Q), 1547 vlan_tag); 1548 1549 skb_record_rx_queue(skb, queue_id); 1550 napi_gro_receive(&fep->napi, skb); 1551 1552 if (is_copybreak) { 1553 dma_sync_single_for_device(&fep->pdev->dev, 1554 fec32_to_cpu(bdp->cbd_bufaddr), 1555 FEC_ENET_RX_FRSIZE - fep->rx_align, 1556 DMA_FROM_DEVICE); 1557 } else { 1558 rxq->rx_skbuff[index] = skb_new; 1559 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1560 } 1561 1562 rx_processing_done: 1563 /* Clear the status flags for this buffer */ 1564 status &= ~BD_ENET_RX_STATS; 1565 1566 /* Mark the buffer empty */ 1567 status |= BD_ENET_RX_EMPTY; 1568 1569 if (fep->bufdesc_ex) { 1570 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1571 1572 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1573 ebdp->cbd_prot = 0; 1574 ebdp->cbd_bdu = 0; 1575 } 1576 /* Make sure the updates to rest of the descriptor are 1577 * performed before transferring ownership. 1578 */ 1579 wmb(); 1580 bdp->cbd_sc = cpu_to_fec16(status); 1581 1582 /* Update BD pointer to next entry */ 1583 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1584 1585 /* Doing this here will keep the FEC running while we process 1586 * incoming frames. On a heavily loaded network, we should be 1587 * able to keep up at the expense of system resources. 1588 */ 1589 writel(0, rxq->bd.reg_desc_active); 1590 } 1591 rxq->bd.cur = bdp; 1592 return pkt_received; 1593 } 1594 1595 static int fec_enet_rx(struct net_device *ndev, int budget) 1596 { 1597 struct fec_enet_private *fep = netdev_priv(ndev); 1598 int i, done = 0; 1599 1600 /* Make sure that AVB queues are processed first. */ 1601 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1602 done += fec_enet_rx_queue(ndev, budget - done, i); 1603 1604 return done; 1605 } 1606 1607 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1608 { 1609 uint int_events; 1610 1611 int_events = readl(fep->hwp + FEC_IEVENT); 1612 1613 /* Don't clear MDIO events, we poll for those */ 1614 int_events &= ~FEC_ENET_MII; 1615 1616 writel(int_events, fep->hwp + FEC_IEVENT); 1617 1618 return int_events != 0; 1619 } 1620 1621 static irqreturn_t 1622 fec_enet_interrupt(int irq, void *dev_id) 1623 { 1624 struct net_device *ndev = dev_id; 1625 struct fec_enet_private *fep = netdev_priv(ndev); 1626 irqreturn_t ret = IRQ_NONE; 1627 1628 if (fec_enet_collect_events(fep) && fep->link) { 1629 ret = IRQ_HANDLED; 1630 1631 if (napi_schedule_prep(&fep->napi)) { 1632 /* Disable interrupts */ 1633 writel(0, fep->hwp + FEC_IMASK); 1634 __napi_schedule(&fep->napi); 1635 } 1636 } 1637 1638 return ret; 1639 } 1640 1641 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1642 { 1643 struct net_device *ndev = napi->dev; 1644 struct fec_enet_private *fep = netdev_priv(ndev); 1645 int done = 0; 1646 1647 do { 1648 done += fec_enet_rx(ndev, budget - done); 1649 fec_enet_tx(ndev); 1650 } while ((done < budget) && fec_enet_collect_events(fep)); 1651 1652 if (done < budget) { 1653 napi_complete_done(napi, done); 1654 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1655 } 1656 1657 return done; 1658 } 1659 1660 /* ------------------------------------------------------------------------- */ 1661 static void fec_get_mac(struct net_device *ndev) 1662 { 1663 struct fec_enet_private *fep = netdev_priv(ndev); 1664 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1665 unsigned char *iap, tmpaddr[ETH_ALEN]; 1666 1667 /* 1668 * try to get mac address in following order: 1669 * 1670 * 1) module parameter via kernel command line in form 1671 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1672 */ 1673 iap = macaddr; 1674 1675 /* 1676 * 2) from device tree data 1677 */ 1678 if (!is_valid_ether_addr(iap)) { 1679 struct device_node *np = fep->pdev->dev.of_node; 1680 if (np) { 1681 const char *mac = of_get_mac_address(np); 1682 if (!IS_ERR(mac)) 1683 iap = (unsigned char *) mac; 1684 } 1685 } 1686 1687 /* 1688 * 3) from flash or fuse (via platform data) 1689 */ 1690 if (!is_valid_ether_addr(iap)) { 1691 #ifdef CONFIG_M5272 1692 if (FEC_FLASHMAC) 1693 iap = (unsigned char *)FEC_FLASHMAC; 1694 #else 1695 if (pdata) 1696 iap = (unsigned char *)&pdata->mac; 1697 #endif 1698 } 1699 1700 /* 1701 * 4) FEC mac registers set by bootloader 1702 */ 1703 if (!is_valid_ether_addr(iap)) { 1704 *((__be32 *) &tmpaddr[0]) = 1705 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1706 *((__be16 *) &tmpaddr[4]) = 1707 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1708 iap = &tmpaddr[0]; 1709 } 1710 1711 /* 1712 * 5) random mac address 1713 */ 1714 if (!is_valid_ether_addr(iap)) { 1715 /* Report it and use a random ethernet address instead */ 1716 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1717 eth_hw_addr_random(ndev); 1718 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1719 ndev->dev_addr); 1720 return; 1721 } 1722 1723 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1724 1725 /* Adjust MAC if using macaddr */ 1726 if (iap == macaddr) 1727 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1728 } 1729 1730 /* ------------------------------------------------------------------------- */ 1731 1732 /* 1733 * Phy section 1734 */ 1735 static void fec_enet_adjust_link(struct net_device *ndev) 1736 { 1737 struct fec_enet_private *fep = netdev_priv(ndev); 1738 struct phy_device *phy_dev = ndev->phydev; 1739 int status_change = 0; 1740 1741 /* 1742 * If the netdev is down, or is going down, we're not interested 1743 * in link state events, so just mark our idea of the link as down 1744 * and ignore the event. 1745 */ 1746 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1747 fep->link = 0; 1748 } else if (phy_dev->link) { 1749 if (!fep->link) { 1750 fep->link = phy_dev->link; 1751 status_change = 1; 1752 } 1753 1754 if (fep->full_duplex != phy_dev->duplex) { 1755 fep->full_duplex = phy_dev->duplex; 1756 status_change = 1; 1757 } 1758 1759 if (phy_dev->speed != fep->speed) { 1760 fep->speed = phy_dev->speed; 1761 status_change = 1; 1762 } 1763 1764 /* if any of the above changed restart the FEC */ 1765 if (status_change) { 1766 napi_disable(&fep->napi); 1767 netif_tx_lock_bh(ndev); 1768 fec_restart(ndev); 1769 netif_tx_wake_all_queues(ndev); 1770 netif_tx_unlock_bh(ndev); 1771 napi_enable(&fep->napi); 1772 } 1773 } else { 1774 if (fep->link) { 1775 napi_disable(&fep->napi); 1776 netif_tx_lock_bh(ndev); 1777 fec_stop(ndev); 1778 netif_tx_unlock_bh(ndev); 1779 napi_enable(&fep->napi); 1780 fep->link = phy_dev->link; 1781 status_change = 1; 1782 } 1783 } 1784 1785 if (status_change) 1786 phy_print_status(phy_dev); 1787 } 1788 1789 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 1790 { 1791 uint ievent; 1792 int ret; 1793 1794 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 1795 ievent & FEC_ENET_MII, 2, 30000); 1796 1797 if (!ret) 1798 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 1799 1800 return ret; 1801 } 1802 1803 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1804 { 1805 struct fec_enet_private *fep = bus->priv; 1806 struct device *dev = &fep->pdev->dev; 1807 int ret = 0, frame_start, frame_addr, frame_op; 1808 bool is_c45 = !!(regnum & MII_ADDR_C45); 1809 1810 ret = pm_runtime_get_sync(dev); 1811 if (ret < 0) 1812 return ret; 1813 1814 if (is_c45) { 1815 frame_start = FEC_MMFR_ST_C45; 1816 1817 /* write address */ 1818 frame_addr = (regnum >> 16); 1819 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1820 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1821 FEC_MMFR_TA | (regnum & 0xFFFF), 1822 fep->hwp + FEC_MII_DATA); 1823 1824 /* wait for end of transfer */ 1825 ret = fec_enet_mdio_wait(fep); 1826 if (ret) { 1827 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1828 goto out; 1829 } 1830 1831 frame_op = FEC_MMFR_OP_READ_C45; 1832 1833 } else { 1834 /* C22 read */ 1835 frame_op = FEC_MMFR_OP_READ; 1836 frame_start = FEC_MMFR_ST; 1837 frame_addr = regnum; 1838 } 1839 1840 /* start a read op */ 1841 writel(frame_start | frame_op | 1842 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1843 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1844 1845 /* wait for end of transfer */ 1846 ret = fec_enet_mdio_wait(fep); 1847 if (ret) { 1848 netdev_err(fep->netdev, "MDIO read timeout\n"); 1849 goto out; 1850 } 1851 1852 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1853 1854 out: 1855 pm_runtime_mark_last_busy(dev); 1856 pm_runtime_put_autosuspend(dev); 1857 1858 return ret; 1859 } 1860 1861 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1862 u16 value) 1863 { 1864 struct fec_enet_private *fep = bus->priv; 1865 struct device *dev = &fep->pdev->dev; 1866 int ret, frame_start, frame_addr; 1867 bool is_c45 = !!(regnum & MII_ADDR_C45); 1868 1869 ret = pm_runtime_get_sync(dev); 1870 if (ret < 0) 1871 return ret; 1872 else 1873 ret = 0; 1874 1875 if (is_c45) { 1876 frame_start = FEC_MMFR_ST_C45; 1877 1878 /* write address */ 1879 frame_addr = (regnum >> 16); 1880 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1881 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1882 FEC_MMFR_TA | (regnum & 0xFFFF), 1883 fep->hwp + FEC_MII_DATA); 1884 1885 /* wait for end of transfer */ 1886 ret = fec_enet_mdio_wait(fep); 1887 if (ret) { 1888 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1889 goto out; 1890 } 1891 } else { 1892 /* C22 write */ 1893 frame_start = FEC_MMFR_ST; 1894 frame_addr = regnum; 1895 } 1896 1897 /* start a write op */ 1898 writel(frame_start | FEC_MMFR_OP_WRITE | 1899 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1900 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1901 fep->hwp + FEC_MII_DATA); 1902 1903 /* wait for end of transfer */ 1904 ret = fec_enet_mdio_wait(fep); 1905 if (ret) 1906 netdev_err(fep->netdev, "MDIO write timeout\n"); 1907 1908 out: 1909 pm_runtime_mark_last_busy(dev); 1910 pm_runtime_put_autosuspend(dev); 1911 1912 return ret; 1913 } 1914 1915 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1916 { 1917 struct fec_enet_private *fep = netdev_priv(ndev); 1918 int ret; 1919 1920 if (enable) { 1921 ret = clk_prepare_enable(fep->clk_enet_out); 1922 if (ret) 1923 return ret; 1924 1925 if (fep->clk_ptp) { 1926 mutex_lock(&fep->ptp_clk_mutex); 1927 ret = clk_prepare_enable(fep->clk_ptp); 1928 if (ret) { 1929 mutex_unlock(&fep->ptp_clk_mutex); 1930 goto failed_clk_ptp; 1931 } else { 1932 fep->ptp_clk_on = true; 1933 } 1934 mutex_unlock(&fep->ptp_clk_mutex); 1935 } 1936 1937 ret = clk_prepare_enable(fep->clk_ref); 1938 if (ret) 1939 goto failed_clk_ref; 1940 1941 phy_reset_after_clk_enable(ndev->phydev); 1942 } else { 1943 clk_disable_unprepare(fep->clk_enet_out); 1944 if (fep->clk_ptp) { 1945 mutex_lock(&fep->ptp_clk_mutex); 1946 clk_disable_unprepare(fep->clk_ptp); 1947 fep->ptp_clk_on = false; 1948 mutex_unlock(&fep->ptp_clk_mutex); 1949 } 1950 clk_disable_unprepare(fep->clk_ref); 1951 } 1952 1953 return 0; 1954 1955 failed_clk_ref: 1956 if (fep->clk_ptp) { 1957 mutex_lock(&fep->ptp_clk_mutex); 1958 clk_disable_unprepare(fep->clk_ptp); 1959 fep->ptp_clk_on = false; 1960 mutex_unlock(&fep->ptp_clk_mutex); 1961 } 1962 failed_clk_ptp: 1963 if (fep->clk_enet_out) 1964 clk_disable_unprepare(fep->clk_enet_out); 1965 1966 return ret; 1967 } 1968 1969 static int fec_enet_mii_probe(struct net_device *ndev) 1970 { 1971 struct fec_enet_private *fep = netdev_priv(ndev); 1972 struct phy_device *phy_dev = NULL; 1973 char mdio_bus_id[MII_BUS_ID_SIZE]; 1974 char phy_name[MII_BUS_ID_SIZE + 3]; 1975 int phy_id; 1976 int dev_id = fep->dev_id; 1977 1978 if (fep->phy_node) { 1979 phy_dev = of_phy_connect(ndev, fep->phy_node, 1980 &fec_enet_adjust_link, 0, 1981 fep->phy_interface); 1982 if (!phy_dev) { 1983 netdev_err(ndev, "Unable to connect to phy\n"); 1984 return -ENODEV; 1985 } 1986 } else { 1987 /* check for attached phy */ 1988 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1989 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 1990 continue; 1991 if (dev_id--) 1992 continue; 1993 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1994 break; 1995 } 1996 1997 if (phy_id >= PHY_MAX_ADDR) { 1998 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1999 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2000 phy_id = 0; 2001 } 2002 2003 snprintf(phy_name, sizeof(phy_name), 2004 PHY_ID_FMT, mdio_bus_id, phy_id); 2005 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2006 fep->phy_interface); 2007 } 2008 2009 if (IS_ERR(phy_dev)) { 2010 netdev_err(ndev, "could not attach to PHY\n"); 2011 return PTR_ERR(phy_dev); 2012 } 2013 2014 /* mask with MAC supported features */ 2015 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2016 phy_set_max_speed(phy_dev, 1000); 2017 phy_remove_link_mode(phy_dev, 2018 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2019 #if !defined(CONFIG_M5272) 2020 phy_support_sym_pause(phy_dev); 2021 #endif 2022 } 2023 else 2024 phy_set_max_speed(phy_dev, 100); 2025 2026 fep->link = 0; 2027 fep->full_duplex = 0; 2028 2029 phy_attached_info(phy_dev); 2030 2031 return 0; 2032 } 2033 2034 static int fec_enet_mii_init(struct platform_device *pdev) 2035 { 2036 static struct mii_bus *fec0_mii_bus; 2037 struct net_device *ndev = platform_get_drvdata(pdev); 2038 struct fec_enet_private *fep = netdev_priv(ndev); 2039 bool suppress_preamble = false; 2040 struct device_node *node; 2041 int err = -ENXIO; 2042 u32 mii_speed, holdtime; 2043 u32 bus_freq; 2044 2045 /* 2046 * The i.MX28 dual fec interfaces are not equal. 2047 * Here are the differences: 2048 * 2049 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2050 * - fec0 acts as the 1588 time master while fec1 is slave 2051 * - external phys can only be configured by fec0 2052 * 2053 * That is to say fec1 can not work independently. It only works 2054 * when fec0 is working. The reason behind this design is that the 2055 * second interface is added primarily for Switch mode. 2056 * 2057 * Because of the last point above, both phys are attached on fec0 2058 * mdio interface in board design, and need to be configured by 2059 * fec0 mii_bus. 2060 */ 2061 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2062 /* fec1 uses fec0 mii_bus */ 2063 if (mii_cnt && fec0_mii_bus) { 2064 fep->mii_bus = fec0_mii_bus; 2065 mii_cnt++; 2066 return 0; 2067 } 2068 return -ENOENT; 2069 } 2070 2071 bus_freq = 2500000; /* 2.5MHz by default */ 2072 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2073 if (node) { 2074 of_property_read_u32(node, "clock-frequency", &bus_freq); 2075 suppress_preamble = of_property_read_bool(node, 2076 "suppress-preamble"); 2077 } 2078 2079 /* 2080 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2081 * 2082 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2083 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2084 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2085 * document. 2086 */ 2087 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2088 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2089 mii_speed--; 2090 if (mii_speed > 63) { 2091 dev_err(&pdev->dev, 2092 "fec clock (%lu) too fast to get right mii speed\n", 2093 clk_get_rate(fep->clk_ipg)); 2094 err = -EINVAL; 2095 goto err_out; 2096 } 2097 2098 /* 2099 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2100 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2101 * versions are RAZ there, so just ignore the difference and write the 2102 * register always. 2103 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2104 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2105 * output. 2106 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2107 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2108 * holdtime cannot result in a value greater than 3. 2109 */ 2110 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2111 2112 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2113 2114 if (suppress_preamble) 2115 fep->phy_speed |= BIT(7); 2116 2117 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2118 * MII event generation condition: 2119 * - writing MSCR: 2120 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2121 * mscr_reg_data_in[7:0] != 0 2122 * - writing MMFR: 2123 * - mscr[7:0]_not_zero 2124 */ 2125 writel(0, fep->hwp + FEC_MII_DATA); 2126 2127 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2128 2129 /* Clear any pending transaction complete indication */ 2130 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2131 2132 fep->mii_bus = mdiobus_alloc(); 2133 if (fep->mii_bus == NULL) { 2134 err = -ENOMEM; 2135 goto err_out; 2136 } 2137 2138 fep->mii_bus->name = "fec_enet_mii_bus"; 2139 fep->mii_bus->read = fec_enet_mdio_read; 2140 fep->mii_bus->write = fec_enet_mdio_write; 2141 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2142 pdev->name, fep->dev_id + 1); 2143 fep->mii_bus->priv = fep; 2144 fep->mii_bus->parent = &pdev->dev; 2145 2146 err = of_mdiobus_register(fep->mii_bus, node); 2147 of_node_put(node); 2148 if (err) 2149 goto err_out_free_mdiobus; 2150 2151 mii_cnt++; 2152 2153 /* save fec0 mii_bus */ 2154 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2155 fec0_mii_bus = fep->mii_bus; 2156 2157 return 0; 2158 2159 err_out_free_mdiobus: 2160 mdiobus_free(fep->mii_bus); 2161 err_out: 2162 return err; 2163 } 2164 2165 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2166 { 2167 if (--mii_cnt == 0) { 2168 mdiobus_unregister(fep->mii_bus); 2169 mdiobus_free(fep->mii_bus); 2170 } 2171 } 2172 2173 static void fec_enet_get_drvinfo(struct net_device *ndev, 2174 struct ethtool_drvinfo *info) 2175 { 2176 struct fec_enet_private *fep = netdev_priv(ndev); 2177 2178 strlcpy(info->driver, fep->pdev->dev.driver->name, 2179 sizeof(info->driver)); 2180 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2181 } 2182 2183 static int fec_enet_get_regs_len(struct net_device *ndev) 2184 { 2185 struct fec_enet_private *fep = netdev_priv(ndev); 2186 struct resource *r; 2187 int s = 0; 2188 2189 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2190 if (r) 2191 s = resource_size(r); 2192 2193 return s; 2194 } 2195 2196 /* List of registers that can be safety be read to dump them with ethtool */ 2197 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2198 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2199 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2200 static __u32 fec_enet_register_version = 2; 2201 static u32 fec_enet_register_offset[] = { 2202 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2203 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2204 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2205 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2206 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2207 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2208 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2209 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2210 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2211 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2212 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2213 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2214 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2215 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2216 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2217 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2218 RMON_T_P_GTE2048, RMON_T_OCTETS, 2219 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2220 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2221 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2222 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2223 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2224 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2225 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2226 RMON_R_P_GTE2048, RMON_R_OCTETS, 2227 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2228 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2229 }; 2230 #else 2231 static __u32 fec_enet_register_version = 1; 2232 static u32 fec_enet_register_offset[] = { 2233 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2234 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2235 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2236 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2237 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2238 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2239 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2240 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2241 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2242 }; 2243 #endif 2244 2245 static void fec_enet_get_regs(struct net_device *ndev, 2246 struct ethtool_regs *regs, void *regbuf) 2247 { 2248 struct fec_enet_private *fep = netdev_priv(ndev); 2249 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2250 struct device *dev = &fep->pdev->dev; 2251 u32 *buf = (u32 *)regbuf; 2252 u32 i, off; 2253 int ret; 2254 2255 ret = pm_runtime_get_sync(dev); 2256 if (ret < 0) 2257 return; 2258 2259 regs->version = fec_enet_register_version; 2260 2261 memset(buf, 0, regs->len); 2262 2263 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2264 off = fec_enet_register_offset[i]; 2265 2266 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2267 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2268 continue; 2269 2270 off >>= 2; 2271 buf[off] = readl(&theregs[off]); 2272 } 2273 2274 pm_runtime_mark_last_busy(dev); 2275 pm_runtime_put_autosuspend(dev); 2276 } 2277 2278 static int fec_enet_get_ts_info(struct net_device *ndev, 2279 struct ethtool_ts_info *info) 2280 { 2281 struct fec_enet_private *fep = netdev_priv(ndev); 2282 2283 if (fep->bufdesc_ex) { 2284 2285 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2286 SOF_TIMESTAMPING_RX_SOFTWARE | 2287 SOF_TIMESTAMPING_SOFTWARE | 2288 SOF_TIMESTAMPING_TX_HARDWARE | 2289 SOF_TIMESTAMPING_RX_HARDWARE | 2290 SOF_TIMESTAMPING_RAW_HARDWARE; 2291 if (fep->ptp_clock) 2292 info->phc_index = ptp_clock_index(fep->ptp_clock); 2293 else 2294 info->phc_index = -1; 2295 2296 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2297 (1 << HWTSTAMP_TX_ON); 2298 2299 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2300 (1 << HWTSTAMP_FILTER_ALL); 2301 return 0; 2302 } else { 2303 return ethtool_op_get_ts_info(ndev, info); 2304 } 2305 } 2306 2307 #if !defined(CONFIG_M5272) 2308 2309 static void fec_enet_get_pauseparam(struct net_device *ndev, 2310 struct ethtool_pauseparam *pause) 2311 { 2312 struct fec_enet_private *fep = netdev_priv(ndev); 2313 2314 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2315 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2316 pause->rx_pause = pause->tx_pause; 2317 } 2318 2319 static int fec_enet_set_pauseparam(struct net_device *ndev, 2320 struct ethtool_pauseparam *pause) 2321 { 2322 struct fec_enet_private *fep = netdev_priv(ndev); 2323 2324 if (!ndev->phydev) 2325 return -ENODEV; 2326 2327 if (pause->tx_pause != pause->rx_pause) { 2328 netdev_info(ndev, 2329 "hardware only support enable/disable both tx and rx"); 2330 return -EINVAL; 2331 } 2332 2333 fep->pause_flag = 0; 2334 2335 /* tx pause must be same as rx pause */ 2336 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2337 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2338 2339 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2340 pause->autoneg); 2341 2342 if (pause->autoneg) { 2343 if (netif_running(ndev)) 2344 fec_stop(ndev); 2345 phy_start_aneg(ndev->phydev); 2346 } 2347 if (netif_running(ndev)) { 2348 napi_disable(&fep->napi); 2349 netif_tx_lock_bh(ndev); 2350 fec_restart(ndev); 2351 netif_tx_wake_all_queues(ndev); 2352 netif_tx_unlock_bh(ndev); 2353 napi_enable(&fep->napi); 2354 } 2355 2356 return 0; 2357 } 2358 2359 static const struct fec_stat { 2360 char name[ETH_GSTRING_LEN]; 2361 u16 offset; 2362 } fec_stats[] = { 2363 /* RMON TX */ 2364 { "tx_dropped", RMON_T_DROP }, 2365 { "tx_packets", RMON_T_PACKETS }, 2366 { "tx_broadcast", RMON_T_BC_PKT }, 2367 { "tx_multicast", RMON_T_MC_PKT }, 2368 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2369 { "tx_undersize", RMON_T_UNDERSIZE }, 2370 { "tx_oversize", RMON_T_OVERSIZE }, 2371 { "tx_fragment", RMON_T_FRAG }, 2372 { "tx_jabber", RMON_T_JAB }, 2373 { "tx_collision", RMON_T_COL }, 2374 { "tx_64byte", RMON_T_P64 }, 2375 { "tx_65to127byte", RMON_T_P65TO127 }, 2376 { "tx_128to255byte", RMON_T_P128TO255 }, 2377 { "tx_256to511byte", RMON_T_P256TO511 }, 2378 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2379 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2380 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2381 { "tx_octets", RMON_T_OCTETS }, 2382 2383 /* IEEE TX */ 2384 { "IEEE_tx_drop", IEEE_T_DROP }, 2385 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2386 { "IEEE_tx_1col", IEEE_T_1COL }, 2387 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2388 { "IEEE_tx_def", IEEE_T_DEF }, 2389 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2390 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2391 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2392 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2393 { "IEEE_tx_sqe", IEEE_T_SQE }, 2394 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2395 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2396 2397 /* RMON RX */ 2398 { "rx_packets", RMON_R_PACKETS }, 2399 { "rx_broadcast", RMON_R_BC_PKT }, 2400 { "rx_multicast", RMON_R_MC_PKT }, 2401 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2402 { "rx_undersize", RMON_R_UNDERSIZE }, 2403 { "rx_oversize", RMON_R_OVERSIZE }, 2404 { "rx_fragment", RMON_R_FRAG }, 2405 { "rx_jabber", RMON_R_JAB }, 2406 { "rx_64byte", RMON_R_P64 }, 2407 { "rx_65to127byte", RMON_R_P65TO127 }, 2408 { "rx_128to255byte", RMON_R_P128TO255 }, 2409 { "rx_256to511byte", RMON_R_P256TO511 }, 2410 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2411 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2412 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2413 { "rx_octets", RMON_R_OCTETS }, 2414 2415 /* IEEE RX */ 2416 { "IEEE_rx_drop", IEEE_R_DROP }, 2417 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2418 { "IEEE_rx_crc", IEEE_R_CRC }, 2419 { "IEEE_rx_align", IEEE_R_ALIGN }, 2420 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2421 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2422 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2423 }; 2424 2425 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2426 2427 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2428 { 2429 struct fec_enet_private *fep = netdev_priv(dev); 2430 int i; 2431 2432 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2433 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2434 } 2435 2436 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2437 struct ethtool_stats *stats, u64 *data) 2438 { 2439 struct fec_enet_private *fep = netdev_priv(dev); 2440 2441 if (netif_running(dev)) 2442 fec_enet_update_ethtool_stats(dev); 2443 2444 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2445 } 2446 2447 static void fec_enet_get_strings(struct net_device *netdev, 2448 u32 stringset, u8 *data) 2449 { 2450 int i; 2451 switch (stringset) { 2452 case ETH_SS_STATS: 2453 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2454 memcpy(data + i * ETH_GSTRING_LEN, 2455 fec_stats[i].name, ETH_GSTRING_LEN); 2456 break; 2457 } 2458 } 2459 2460 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2461 { 2462 switch (sset) { 2463 case ETH_SS_STATS: 2464 return ARRAY_SIZE(fec_stats); 2465 default: 2466 return -EOPNOTSUPP; 2467 } 2468 } 2469 2470 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2471 { 2472 struct fec_enet_private *fep = netdev_priv(dev); 2473 int i; 2474 2475 /* Disable MIB statistics counters */ 2476 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2477 2478 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2479 writel(0, fep->hwp + fec_stats[i].offset); 2480 2481 /* Don't disable MIB statistics counters */ 2482 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2483 } 2484 2485 #else /* !defined(CONFIG_M5272) */ 2486 #define FEC_STATS_SIZE 0 2487 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2488 { 2489 } 2490 2491 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2492 { 2493 } 2494 #endif /* !defined(CONFIG_M5272) */ 2495 2496 /* ITR clock source is enet system clock (clk_ahb). 2497 * TCTT unit is cycle_ns * 64 cycle 2498 * So, the ICTT value = X us / (cycle_ns * 64) 2499 */ 2500 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2501 { 2502 struct fec_enet_private *fep = netdev_priv(ndev); 2503 2504 return us * (fep->itr_clk_rate / 64000) / 1000; 2505 } 2506 2507 /* Set threshold for interrupt coalescing */ 2508 static void fec_enet_itr_coal_set(struct net_device *ndev) 2509 { 2510 struct fec_enet_private *fep = netdev_priv(ndev); 2511 int rx_itr, tx_itr; 2512 2513 /* Must be greater than zero to avoid unpredictable behavior */ 2514 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2515 !fep->tx_time_itr || !fep->tx_pkts_itr) 2516 return; 2517 2518 /* Select enet system clock as Interrupt Coalescing 2519 * timer Clock Source 2520 */ 2521 rx_itr = FEC_ITR_CLK_SEL; 2522 tx_itr = FEC_ITR_CLK_SEL; 2523 2524 /* set ICFT and ICTT */ 2525 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2526 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2527 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2528 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2529 2530 rx_itr |= FEC_ITR_EN; 2531 tx_itr |= FEC_ITR_EN; 2532 2533 writel(tx_itr, fep->hwp + FEC_TXIC0); 2534 writel(rx_itr, fep->hwp + FEC_RXIC0); 2535 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 2536 writel(tx_itr, fep->hwp + FEC_TXIC1); 2537 writel(rx_itr, fep->hwp + FEC_RXIC1); 2538 writel(tx_itr, fep->hwp + FEC_TXIC2); 2539 writel(rx_itr, fep->hwp + FEC_RXIC2); 2540 } 2541 } 2542 2543 static int 2544 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2545 { 2546 struct fec_enet_private *fep = netdev_priv(ndev); 2547 2548 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2549 return -EOPNOTSUPP; 2550 2551 ec->rx_coalesce_usecs = fep->rx_time_itr; 2552 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2553 2554 ec->tx_coalesce_usecs = fep->tx_time_itr; 2555 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2556 2557 return 0; 2558 } 2559 2560 static int 2561 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2562 { 2563 struct fec_enet_private *fep = netdev_priv(ndev); 2564 struct device *dev = &fep->pdev->dev; 2565 unsigned int cycle; 2566 2567 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2568 return -EOPNOTSUPP; 2569 2570 if (ec->rx_max_coalesced_frames > 255) { 2571 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 2572 return -EINVAL; 2573 } 2574 2575 if (ec->tx_max_coalesced_frames > 255) { 2576 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 2577 return -EINVAL; 2578 } 2579 2580 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 2581 if (cycle > 0xFFFF) { 2582 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 2583 return -EINVAL; 2584 } 2585 2586 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 2587 if (cycle > 0xFFFF) { 2588 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 2589 return -EINVAL; 2590 } 2591 2592 fep->rx_time_itr = ec->rx_coalesce_usecs; 2593 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2594 2595 fep->tx_time_itr = ec->tx_coalesce_usecs; 2596 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2597 2598 fec_enet_itr_coal_set(ndev); 2599 2600 return 0; 2601 } 2602 2603 static void fec_enet_itr_coal_init(struct net_device *ndev) 2604 { 2605 struct ethtool_coalesce ec; 2606 2607 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2608 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2609 2610 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2611 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2612 2613 fec_enet_set_coalesce(ndev, &ec); 2614 } 2615 2616 static int fec_enet_get_tunable(struct net_device *netdev, 2617 const struct ethtool_tunable *tuna, 2618 void *data) 2619 { 2620 struct fec_enet_private *fep = netdev_priv(netdev); 2621 int ret = 0; 2622 2623 switch (tuna->id) { 2624 case ETHTOOL_RX_COPYBREAK: 2625 *(u32 *)data = fep->rx_copybreak; 2626 break; 2627 default: 2628 ret = -EINVAL; 2629 break; 2630 } 2631 2632 return ret; 2633 } 2634 2635 static int fec_enet_set_tunable(struct net_device *netdev, 2636 const struct ethtool_tunable *tuna, 2637 const void *data) 2638 { 2639 struct fec_enet_private *fep = netdev_priv(netdev); 2640 int ret = 0; 2641 2642 switch (tuna->id) { 2643 case ETHTOOL_RX_COPYBREAK: 2644 fep->rx_copybreak = *(u32 *)data; 2645 break; 2646 default: 2647 ret = -EINVAL; 2648 break; 2649 } 2650 2651 return ret; 2652 } 2653 2654 static void 2655 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2656 { 2657 struct fec_enet_private *fep = netdev_priv(ndev); 2658 2659 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2660 wol->supported = WAKE_MAGIC; 2661 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2662 } else { 2663 wol->supported = wol->wolopts = 0; 2664 } 2665 } 2666 2667 static int 2668 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2669 { 2670 struct fec_enet_private *fep = netdev_priv(ndev); 2671 2672 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2673 return -EINVAL; 2674 2675 if (wol->wolopts & ~WAKE_MAGIC) 2676 return -EINVAL; 2677 2678 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2679 if (device_may_wakeup(&ndev->dev)) { 2680 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2681 if (fep->irq[0] > 0) 2682 enable_irq_wake(fep->irq[0]); 2683 } else { 2684 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2685 if (fep->irq[0] > 0) 2686 disable_irq_wake(fep->irq[0]); 2687 } 2688 2689 return 0; 2690 } 2691 2692 static const struct ethtool_ops fec_enet_ethtool_ops = { 2693 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2694 ETHTOOL_COALESCE_MAX_FRAMES, 2695 .get_drvinfo = fec_enet_get_drvinfo, 2696 .get_regs_len = fec_enet_get_regs_len, 2697 .get_regs = fec_enet_get_regs, 2698 .nway_reset = phy_ethtool_nway_reset, 2699 .get_link = ethtool_op_get_link, 2700 .get_coalesce = fec_enet_get_coalesce, 2701 .set_coalesce = fec_enet_set_coalesce, 2702 #ifndef CONFIG_M5272 2703 .get_pauseparam = fec_enet_get_pauseparam, 2704 .set_pauseparam = fec_enet_set_pauseparam, 2705 .get_strings = fec_enet_get_strings, 2706 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2707 .get_sset_count = fec_enet_get_sset_count, 2708 #endif 2709 .get_ts_info = fec_enet_get_ts_info, 2710 .get_tunable = fec_enet_get_tunable, 2711 .set_tunable = fec_enet_set_tunable, 2712 .get_wol = fec_enet_get_wol, 2713 .set_wol = fec_enet_set_wol, 2714 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2715 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2716 }; 2717 2718 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2719 { 2720 struct fec_enet_private *fep = netdev_priv(ndev); 2721 struct phy_device *phydev = ndev->phydev; 2722 2723 if (!netif_running(ndev)) 2724 return -EINVAL; 2725 2726 if (!phydev) 2727 return -ENODEV; 2728 2729 if (fep->bufdesc_ex) { 2730 bool use_fec_hwts = !phy_has_hwtstamp(phydev); 2731 2732 if (cmd == SIOCSHWTSTAMP) { 2733 if (use_fec_hwts) 2734 return fec_ptp_set(ndev, rq); 2735 fec_ptp_disable_hwts(ndev); 2736 } else if (cmd == SIOCGHWTSTAMP) { 2737 if (use_fec_hwts) 2738 return fec_ptp_get(ndev, rq); 2739 } 2740 } 2741 2742 return phy_mii_ioctl(phydev, rq, cmd); 2743 } 2744 2745 static void fec_enet_free_buffers(struct net_device *ndev) 2746 { 2747 struct fec_enet_private *fep = netdev_priv(ndev); 2748 unsigned int i; 2749 struct sk_buff *skb; 2750 struct bufdesc *bdp; 2751 struct fec_enet_priv_tx_q *txq; 2752 struct fec_enet_priv_rx_q *rxq; 2753 unsigned int q; 2754 2755 for (q = 0; q < fep->num_rx_queues; q++) { 2756 rxq = fep->rx_queue[q]; 2757 bdp = rxq->bd.base; 2758 for (i = 0; i < rxq->bd.ring_size; i++) { 2759 skb = rxq->rx_skbuff[i]; 2760 rxq->rx_skbuff[i] = NULL; 2761 if (skb) { 2762 dma_unmap_single(&fep->pdev->dev, 2763 fec32_to_cpu(bdp->cbd_bufaddr), 2764 FEC_ENET_RX_FRSIZE - fep->rx_align, 2765 DMA_FROM_DEVICE); 2766 dev_kfree_skb(skb); 2767 } 2768 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2769 } 2770 } 2771 2772 for (q = 0; q < fep->num_tx_queues; q++) { 2773 txq = fep->tx_queue[q]; 2774 for (i = 0; i < txq->bd.ring_size; i++) { 2775 kfree(txq->tx_bounce[i]); 2776 txq->tx_bounce[i] = NULL; 2777 skb = txq->tx_skbuff[i]; 2778 txq->tx_skbuff[i] = NULL; 2779 dev_kfree_skb(skb); 2780 } 2781 } 2782 } 2783 2784 static void fec_enet_free_queue(struct net_device *ndev) 2785 { 2786 struct fec_enet_private *fep = netdev_priv(ndev); 2787 int i; 2788 struct fec_enet_priv_tx_q *txq; 2789 2790 for (i = 0; i < fep->num_tx_queues; i++) 2791 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2792 txq = fep->tx_queue[i]; 2793 dma_free_coherent(&fep->pdev->dev, 2794 txq->bd.ring_size * TSO_HEADER_SIZE, 2795 txq->tso_hdrs, 2796 txq->tso_hdrs_dma); 2797 } 2798 2799 for (i = 0; i < fep->num_rx_queues; i++) 2800 kfree(fep->rx_queue[i]); 2801 for (i = 0; i < fep->num_tx_queues; i++) 2802 kfree(fep->tx_queue[i]); 2803 } 2804 2805 static int fec_enet_alloc_queue(struct net_device *ndev) 2806 { 2807 struct fec_enet_private *fep = netdev_priv(ndev); 2808 int i; 2809 int ret = 0; 2810 struct fec_enet_priv_tx_q *txq; 2811 2812 for (i = 0; i < fep->num_tx_queues; i++) { 2813 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 2814 if (!txq) { 2815 ret = -ENOMEM; 2816 goto alloc_failed; 2817 } 2818 2819 fep->tx_queue[i] = txq; 2820 txq->bd.ring_size = TX_RING_SIZE; 2821 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 2822 2823 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2824 txq->tx_wake_threshold = 2825 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 2826 2827 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 2828 txq->bd.ring_size * TSO_HEADER_SIZE, 2829 &txq->tso_hdrs_dma, 2830 GFP_KERNEL); 2831 if (!txq->tso_hdrs) { 2832 ret = -ENOMEM; 2833 goto alloc_failed; 2834 } 2835 } 2836 2837 for (i = 0; i < fep->num_rx_queues; i++) { 2838 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 2839 GFP_KERNEL); 2840 if (!fep->rx_queue[i]) { 2841 ret = -ENOMEM; 2842 goto alloc_failed; 2843 } 2844 2845 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 2846 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 2847 } 2848 return ret; 2849 2850 alloc_failed: 2851 fec_enet_free_queue(ndev); 2852 return ret; 2853 } 2854 2855 static int 2856 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 2857 { 2858 struct fec_enet_private *fep = netdev_priv(ndev); 2859 unsigned int i; 2860 struct sk_buff *skb; 2861 struct bufdesc *bdp; 2862 struct fec_enet_priv_rx_q *rxq; 2863 2864 rxq = fep->rx_queue[queue]; 2865 bdp = rxq->bd.base; 2866 for (i = 0; i < rxq->bd.ring_size; i++) { 2867 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2868 if (!skb) 2869 goto err_alloc; 2870 2871 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 2872 dev_kfree_skb(skb); 2873 goto err_alloc; 2874 } 2875 2876 rxq->rx_skbuff[i] = skb; 2877 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 2878 2879 if (fep->bufdesc_ex) { 2880 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2881 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 2882 } 2883 2884 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2885 } 2886 2887 /* Set the last buffer to wrap. */ 2888 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 2889 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2890 return 0; 2891 2892 err_alloc: 2893 fec_enet_free_buffers(ndev); 2894 return -ENOMEM; 2895 } 2896 2897 static int 2898 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 2899 { 2900 struct fec_enet_private *fep = netdev_priv(ndev); 2901 unsigned int i; 2902 struct bufdesc *bdp; 2903 struct fec_enet_priv_tx_q *txq; 2904 2905 txq = fep->tx_queue[queue]; 2906 bdp = txq->bd.base; 2907 for (i = 0; i < txq->bd.ring_size; i++) { 2908 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2909 if (!txq->tx_bounce[i]) 2910 goto err_alloc; 2911 2912 bdp->cbd_sc = cpu_to_fec16(0); 2913 bdp->cbd_bufaddr = cpu_to_fec32(0); 2914 2915 if (fep->bufdesc_ex) { 2916 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2917 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 2918 } 2919 2920 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 2921 } 2922 2923 /* Set the last buffer to wrap. */ 2924 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 2925 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2926 2927 return 0; 2928 2929 err_alloc: 2930 fec_enet_free_buffers(ndev); 2931 return -ENOMEM; 2932 } 2933 2934 static int fec_enet_alloc_buffers(struct net_device *ndev) 2935 { 2936 struct fec_enet_private *fep = netdev_priv(ndev); 2937 unsigned int i; 2938 2939 for (i = 0; i < fep->num_rx_queues; i++) 2940 if (fec_enet_alloc_rxq_buffers(ndev, i)) 2941 return -ENOMEM; 2942 2943 for (i = 0; i < fep->num_tx_queues; i++) 2944 if (fec_enet_alloc_txq_buffers(ndev, i)) 2945 return -ENOMEM; 2946 return 0; 2947 } 2948 2949 static int 2950 fec_enet_open(struct net_device *ndev) 2951 { 2952 struct fec_enet_private *fep = netdev_priv(ndev); 2953 int ret; 2954 bool reset_again; 2955 2956 ret = pm_runtime_get_sync(&fep->pdev->dev); 2957 if (ret < 0) 2958 return ret; 2959 2960 pinctrl_pm_select_default_state(&fep->pdev->dev); 2961 ret = fec_enet_clk_enable(ndev, true); 2962 if (ret) 2963 goto clk_enable; 2964 2965 /* During the first fec_enet_open call the PHY isn't probed at this 2966 * point. Therefore the phy_reset_after_clk_enable() call within 2967 * fec_enet_clk_enable() fails. As we need this reset in order to be 2968 * sure the PHY is working correctly we check if we need to reset again 2969 * later when the PHY is probed 2970 */ 2971 if (ndev->phydev && ndev->phydev->drv) 2972 reset_again = false; 2973 else 2974 reset_again = true; 2975 2976 /* I should reset the ring buffers here, but I don't yet know 2977 * a simple way to do that. 2978 */ 2979 2980 ret = fec_enet_alloc_buffers(ndev); 2981 if (ret) 2982 goto err_enet_alloc; 2983 2984 /* Init MAC prior to mii bus probe */ 2985 fec_restart(ndev); 2986 2987 /* Probe and connect to PHY when open the interface */ 2988 ret = fec_enet_mii_probe(ndev); 2989 if (ret) 2990 goto err_enet_mii_probe; 2991 2992 /* Call phy_reset_after_clk_enable() again if it failed during 2993 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 2994 */ 2995 if (reset_again) 2996 phy_reset_after_clk_enable(ndev->phydev); 2997 2998 if (fep->quirks & FEC_QUIRK_ERR006687) 2999 imx6q_cpuidle_fec_irqs_used(); 3000 3001 napi_enable(&fep->napi); 3002 phy_start(ndev->phydev); 3003 netif_tx_start_all_queues(ndev); 3004 3005 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3006 FEC_WOL_FLAG_ENABLE); 3007 3008 return 0; 3009 3010 err_enet_mii_probe: 3011 fec_enet_free_buffers(ndev); 3012 err_enet_alloc: 3013 fec_enet_clk_enable(ndev, false); 3014 clk_enable: 3015 pm_runtime_mark_last_busy(&fep->pdev->dev); 3016 pm_runtime_put_autosuspend(&fep->pdev->dev); 3017 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3018 return ret; 3019 } 3020 3021 static int 3022 fec_enet_close(struct net_device *ndev) 3023 { 3024 struct fec_enet_private *fep = netdev_priv(ndev); 3025 3026 phy_stop(ndev->phydev); 3027 3028 if (netif_device_present(ndev)) { 3029 napi_disable(&fep->napi); 3030 netif_tx_disable(ndev); 3031 fec_stop(ndev); 3032 } 3033 3034 phy_disconnect(ndev->phydev); 3035 3036 if (fep->quirks & FEC_QUIRK_ERR006687) 3037 imx6q_cpuidle_fec_irqs_unused(); 3038 3039 fec_enet_update_ethtool_stats(ndev); 3040 3041 fec_enet_clk_enable(ndev, false); 3042 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3043 pm_runtime_mark_last_busy(&fep->pdev->dev); 3044 pm_runtime_put_autosuspend(&fep->pdev->dev); 3045 3046 fec_enet_free_buffers(ndev); 3047 3048 return 0; 3049 } 3050 3051 /* Set or clear the multicast filter for this adaptor. 3052 * Skeleton taken from sunlance driver. 3053 * The CPM Ethernet implementation allows Multicast as well as individual 3054 * MAC address filtering. Some of the drivers check to make sure it is 3055 * a group multicast address, and discard those that are not. I guess I 3056 * will do the same for now, but just remove the test if you want 3057 * individual filtering as well (do the upper net layers want or support 3058 * this kind of feature?). 3059 */ 3060 3061 #define FEC_HASH_BITS 6 /* #bits in hash */ 3062 3063 static void set_multicast_list(struct net_device *ndev) 3064 { 3065 struct fec_enet_private *fep = netdev_priv(ndev); 3066 struct netdev_hw_addr *ha; 3067 unsigned int crc, tmp; 3068 unsigned char hash; 3069 unsigned int hash_high = 0, hash_low = 0; 3070 3071 if (ndev->flags & IFF_PROMISC) { 3072 tmp = readl(fep->hwp + FEC_R_CNTRL); 3073 tmp |= 0x8; 3074 writel(tmp, fep->hwp + FEC_R_CNTRL); 3075 return; 3076 } 3077 3078 tmp = readl(fep->hwp + FEC_R_CNTRL); 3079 tmp &= ~0x8; 3080 writel(tmp, fep->hwp + FEC_R_CNTRL); 3081 3082 if (ndev->flags & IFF_ALLMULTI) { 3083 /* Catch all multicast addresses, so set the 3084 * filter to all 1's 3085 */ 3086 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3087 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3088 3089 return; 3090 } 3091 3092 /* Add the addresses in hash register */ 3093 netdev_for_each_mc_addr(ha, ndev) { 3094 /* calculate crc32 value of mac address */ 3095 crc = ether_crc_le(ndev->addr_len, ha->addr); 3096 3097 /* only upper 6 bits (FEC_HASH_BITS) are used 3098 * which point to specific bit in the hash registers 3099 */ 3100 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3101 3102 if (hash > 31) 3103 hash_high |= 1 << (hash - 32); 3104 else 3105 hash_low |= 1 << hash; 3106 } 3107 3108 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3109 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3110 } 3111 3112 /* Set a MAC change in hardware. */ 3113 static int 3114 fec_set_mac_address(struct net_device *ndev, void *p) 3115 { 3116 struct fec_enet_private *fep = netdev_priv(ndev); 3117 struct sockaddr *addr = p; 3118 3119 if (addr) { 3120 if (!is_valid_ether_addr(addr->sa_data)) 3121 return -EADDRNOTAVAIL; 3122 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 3123 } 3124 3125 /* Add netif status check here to avoid system hang in below case: 3126 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3127 * After ethx down, fec all clocks are gated off and then register 3128 * access causes system hang. 3129 */ 3130 if (!netif_running(ndev)) 3131 return 0; 3132 3133 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3134 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3135 fep->hwp + FEC_ADDR_LOW); 3136 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3137 fep->hwp + FEC_ADDR_HIGH); 3138 return 0; 3139 } 3140 3141 #ifdef CONFIG_NET_POLL_CONTROLLER 3142 /** 3143 * fec_poll_controller - FEC Poll controller function 3144 * @dev: The FEC network adapter 3145 * 3146 * Polled functionality used by netconsole and others in non interrupt mode 3147 * 3148 */ 3149 static void fec_poll_controller(struct net_device *dev) 3150 { 3151 int i; 3152 struct fec_enet_private *fep = netdev_priv(dev); 3153 3154 for (i = 0; i < FEC_IRQ_NUM; i++) { 3155 if (fep->irq[i] > 0) { 3156 disable_irq(fep->irq[i]); 3157 fec_enet_interrupt(fep->irq[i], dev); 3158 enable_irq(fep->irq[i]); 3159 } 3160 } 3161 } 3162 #endif 3163 3164 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3165 netdev_features_t features) 3166 { 3167 struct fec_enet_private *fep = netdev_priv(netdev); 3168 netdev_features_t changed = features ^ netdev->features; 3169 3170 netdev->features = features; 3171 3172 /* Receive checksum has been changed */ 3173 if (changed & NETIF_F_RXCSUM) { 3174 if (features & NETIF_F_RXCSUM) 3175 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3176 else 3177 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3178 } 3179 } 3180 3181 static int fec_set_features(struct net_device *netdev, 3182 netdev_features_t features) 3183 { 3184 struct fec_enet_private *fep = netdev_priv(netdev); 3185 netdev_features_t changed = features ^ netdev->features; 3186 3187 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3188 napi_disable(&fep->napi); 3189 netif_tx_lock_bh(netdev); 3190 fec_stop(netdev); 3191 fec_enet_set_netdev_features(netdev, features); 3192 fec_restart(netdev); 3193 netif_tx_wake_all_queues(netdev); 3194 netif_tx_unlock_bh(netdev); 3195 napi_enable(&fep->napi); 3196 } else { 3197 fec_enet_set_netdev_features(netdev, features); 3198 } 3199 3200 return 0; 3201 } 3202 3203 static const struct net_device_ops fec_netdev_ops = { 3204 .ndo_open = fec_enet_open, 3205 .ndo_stop = fec_enet_close, 3206 .ndo_start_xmit = fec_enet_start_xmit, 3207 .ndo_set_rx_mode = set_multicast_list, 3208 .ndo_validate_addr = eth_validate_addr, 3209 .ndo_tx_timeout = fec_timeout, 3210 .ndo_set_mac_address = fec_set_mac_address, 3211 .ndo_do_ioctl = fec_enet_ioctl, 3212 #ifdef CONFIG_NET_POLL_CONTROLLER 3213 .ndo_poll_controller = fec_poll_controller, 3214 #endif 3215 .ndo_set_features = fec_set_features, 3216 }; 3217 3218 static const unsigned short offset_des_active_rxq[] = { 3219 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3220 }; 3221 3222 static const unsigned short offset_des_active_txq[] = { 3223 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3224 }; 3225 3226 /* 3227 * XXX: We need to clean up on failure exits here. 3228 * 3229 */ 3230 static int fec_enet_init(struct net_device *ndev) 3231 { 3232 struct fec_enet_private *fep = netdev_priv(ndev); 3233 struct bufdesc *cbd_base; 3234 dma_addr_t bd_dma; 3235 int bd_size; 3236 unsigned int i; 3237 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3238 sizeof(struct bufdesc); 3239 unsigned dsize_log2 = __fls(dsize); 3240 int ret; 3241 3242 WARN_ON(dsize != (1 << dsize_log2)); 3243 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 3244 fep->rx_align = 0xf; 3245 fep->tx_align = 0xf; 3246 #else 3247 fep->rx_align = 0x3; 3248 fep->tx_align = 0x3; 3249 #endif 3250 3251 /* Check mask of the streaming and coherent API */ 3252 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 3253 if (ret < 0) { 3254 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 3255 return ret; 3256 } 3257 3258 fec_enet_alloc_queue(ndev); 3259 3260 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3261 3262 /* Allocate memory for buffer descriptors. */ 3263 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3264 GFP_KERNEL); 3265 if (!cbd_base) { 3266 return -ENOMEM; 3267 } 3268 3269 /* Get the Ethernet address */ 3270 fec_get_mac(ndev); 3271 /* make sure MAC we just acquired is programmed into the hw */ 3272 fec_set_mac_address(ndev, NULL); 3273 3274 /* Set receive and transmit descriptor base. */ 3275 for (i = 0; i < fep->num_rx_queues; i++) { 3276 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3277 unsigned size = dsize * rxq->bd.ring_size; 3278 3279 rxq->bd.qid = i; 3280 rxq->bd.base = cbd_base; 3281 rxq->bd.cur = cbd_base; 3282 rxq->bd.dma = bd_dma; 3283 rxq->bd.dsize = dsize; 3284 rxq->bd.dsize_log2 = dsize_log2; 3285 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3286 bd_dma += size; 3287 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3288 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3289 } 3290 3291 for (i = 0; i < fep->num_tx_queues; i++) { 3292 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3293 unsigned size = dsize * txq->bd.ring_size; 3294 3295 txq->bd.qid = i; 3296 txq->bd.base = cbd_base; 3297 txq->bd.cur = cbd_base; 3298 txq->bd.dma = bd_dma; 3299 txq->bd.dsize = dsize; 3300 txq->bd.dsize_log2 = dsize_log2; 3301 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3302 bd_dma += size; 3303 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3304 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3305 } 3306 3307 3308 /* The FEC Ethernet specific entries in the device structure */ 3309 ndev->watchdog_timeo = TX_TIMEOUT; 3310 ndev->netdev_ops = &fec_netdev_ops; 3311 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3312 3313 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3314 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3315 3316 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3317 /* enable hw VLAN support */ 3318 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3319 3320 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3321 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3322 3323 /* enable hw accelerator */ 3324 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3325 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3326 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3327 } 3328 3329 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 3330 fep->tx_align = 0; 3331 fep->rx_align = 0x3f; 3332 } 3333 3334 ndev->hw_features = ndev->features; 3335 3336 fec_restart(ndev); 3337 3338 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 3339 fec_enet_clear_ethtool_stats(ndev); 3340 else 3341 fec_enet_update_ethtool_stats(ndev); 3342 3343 return 0; 3344 } 3345 3346 #ifdef CONFIG_OF 3347 static int fec_reset_phy(struct platform_device *pdev) 3348 { 3349 int err, phy_reset; 3350 bool active_high = false; 3351 int msec = 1, phy_post_delay = 0; 3352 struct device_node *np = pdev->dev.of_node; 3353 3354 if (!np) 3355 return 0; 3356 3357 err = of_property_read_u32(np, "phy-reset-duration", &msec); 3358 /* A sane reset duration should not be longer than 1s */ 3359 if (!err && msec > 1000) 3360 msec = 1; 3361 3362 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3363 if (phy_reset == -EPROBE_DEFER) 3364 return phy_reset; 3365 else if (!gpio_is_valid(phy_reset)) 3366 return 0; 3367 3368 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 3369 /* valid reset duration should be less than 1s */ 3370 if (!err && phy_post_delay > 1000) 3371 return -EINVAL; 3372 3373 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3374 3375 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3376 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3377 "phy-reset"); 3378 if (err) { 3379 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3380 return err; 3381 } 3382 3383 if (msec > 20) 3384 msleep(msec); 3385 else 3386 usleep_range(msec * 1000, msec * 1000 + 1000); 3387 3388 gpio_set_value_cansleep(phy_reset, !active_high); 3389 3390 if (!phy_post_delay) 3391 return 0; 3392 3393 if (phy_post_delay > 20) 3394 msleep(phy_post_delay); 3395 else 3396 usleep_range(phy_post_delay * 1000, 3397 phy_post_delay * 1000 + 1000); 3398 3399 return 0; 3400 } 3401 #else /* CONFIG_OF */ 3402 static int fec_reset_phy(struct platform_device *pdev) 3403 { 3404 /* 3405 * In case of platform probe, the reset has been done 3406 * by machine code. 3407 */ 3408 return 0; 3409 } 3410 #endif /* CONFIG_OF */ 3411 3412 static void 3413 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3414 { 3415 struct device_node *np = pdev->dev.of_node; 3416 3417 *num_tx = *num_rx = 1; 3418 3419 if (!np || !of_device_is_available(np)) 3420 return; 3421 3422 /* parse the num of tx and rx queues */ 3423 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3424 3425 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3426 3427 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3428 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3429 *num_tx); 3430 *num_tx = 1; 3431 return; 3432 } 3433 3434 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3435 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3436 *num_rx); 3437 *num_rx = 1; 3438 return; 3439 } 3440 3441 } 3442 3443 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 3444 { 3445 int irq_cnt = platform_irq_count(pdev); 3446 3447 if (irq_cnt > FEC_IRQ_NUM) 3448 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 3449 else if (irq_cnt == 2) 3450 irq_cnt = 1; /* last for pps */ 3451 else if (irq_cnt <= 0) 3452 irq_cnt = 1; /* At least 1 irq is needed */ 3453 return irq_cnt; 3454 } 3455 3456 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 3457 struct device_node *np) 3458 { 3459 struct device_node *gpr_np; 3460 u32 out_val[3]; 3461 int ret = 0; 3462 3463 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 3464 if (!gpr_np) 3465 return 0; 3466 3467 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 3468 ARRAY_SIZE(out_val)); 3469 if (ret) { 3470 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 3471 return ret; 3472 } 3473 3474 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 3475 if (IS_ERR(fep->stop_gpr.gpr)) { 3476 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 3477 ret = PTR_ERR(fep->stop_gpr.gpr); 3478 fep->stop_gpr.gpr = NULL; 3479 goto out; 3480 } 3481 3482 fep->stop_gpr.reg = out_val[1]; 3483 fep->stop_gpr.bit = out_val[2]; 3484 3485 out: 3486 of_node_put(gpr_np); 3487 3488 return ret; 3489 } 3490 3491 static int 3492 fec_probe(struct platform_device *pdev) 3493 { 3494 struct fec_enet_private *fep; 3495 struct fec_platform_data *pdata; 3496 phy_interface_t interface; 3497 struct net_device *ndev; 3498 int i, irq, ret = 0; 3499 const struct of_device_id *of_id; 3500 static int dev_id; 3501 struct device_node *np = pdev->dev.of_node, *phy_node; 3502 int num_tx_qs; 3503 int num_rx_qs; 3504 char irq_name[8]; 3505 int irq_cnt; 3506 struct fec_devinfo *dev_info; 3507 3508 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3509 3510 /* Init network device */ 3511 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 3512 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 3513 if (!ndev) 3514 return -ENOMEM; 3515 3516 SET_NETDEV_DEV(ndev, &pdev->dev); 3517 3518 /* setup board info structure */ 3519 fep = netdev_priv(ndev); 3520 3521 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3522 if (of_id) 3523 pdev->id_entry = of_id->data; 3524 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; 3525 if (dev_info) 3526 fep->quirks = dev_info->quirks; 3527 3528 fep->netdev = ndev; 3529 fep->num_rx_queues = num_rx_qs; 3530 fep->num_tx_queues = num_tx_qs; 3531 3532 #if !defined(CONFIG_M5272) 3533 /* default enable pause frame auto negotiation */ 3534 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3535 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3536 #endif 3537 3538 /* Select default pin state */ 3539 pinctrl_pm_select_default_state(&pdev->dev); 3540 3541 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 3542 if (IS_ERR(fep->hwp)) { 3543 ret = PTR_ERR(fep->hwp); 3544 goto failed_ioremap; 3545 } 3546 3547 fep->pdev = pdev; 3548 fep->dev_id = dev_id++; 3549 3550 platform_set_drvdata(pdev, ndev); 3551 3552 if ((of_machine_is_compatible("fsl,imx6q") || 3553 of_machine_is_compatible("fsl,imx6dl")) && 3554 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3555 fep->quirks |= FEC_QUIRK_ERR006687; 3556 3557 if (of_get_property(np, "fsl,magic-packet", NULL)) 3558 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3559 3560 ret = fec_enet_init_stop_mode(fep, np); 3561 if (ret) 3562 goto failed_stop_mode; 3563 3564 phy_node = of_parse_phandle(np, "phy-handle", 0); 3565 if (!phy_node && of_phy_is_fixed_link(np)) { 3566 ret = of_phy_register_fixed_link(np); 3567 if (ret < 0) { 3568 dev_err(&pdev->dev, 3569 "broken fixed-link specification\n"); 3570 goto failed_phy; 3571 } 3572 phy_node = of_node_get(np); 3573 } 3574 fep->phy_node = phy_node; 3575 3576 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 3577 if (ret) { 3578 pdata = dev_get_platdata(&pdev->dev); 3579 if (pdata) 3580 fep->phy_interface = pdata->phy; 3581 else 3582 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3583 } else { 3584 fep->phy_interface = interface; 3585 } 3586 3587 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3588 if (IS_ERR(fep->clk_ipg)) { 3589 ret = PTR_ERR(fep->clk_ipg); 3590 goto failed_clk; 3591 } 3592 3593 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3594 if (IS_ERR(fep->clk_ahb)) { 3595 ret = PTR_ERR(fep->clk_ahb); 3596 goto failed_clk; 3597 } 3598 3599 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3600 3601 /* enet_out is optional, depends on board */ 3602 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3603 if (IS_ERR(fep->clk_enet_out)) 3604 fep->clk_enet_out = NULL; 3605 3606 fep->ptp_clk_on = false; 3607 mutex_init(&fep->ptp_clk_mutex); 3608 3609 /* clk_ref is optional, depends on board */ 3610 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3611 if (IS_ERR(fep->clk_ref)) 3612 fep->clk_ref = NULL; 3613 3614 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3615 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3616 if (IS_ERR(fep->clk_ptp)) { 3617 fep->clk_ptp = NULL; 3618 fep->bufdesc_ex = false; 3619 } 3620 3621 ret = fec_enet_clk_enable(ndev, true); 3622 if (ret) 3623 goto failed_clk; 3624 3625 ret = clk_prepare_enable(fep->clk_ipg); 3626 if (ret) 3627 goto failed_clk_ipg; 3628 ret = clk_prepare_enable(fep->clk_ahb); 3629 if (ret) 3630 goto failed_clk_ahb; 3631 3632 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 3633 if (!IS_ERR(fep->reg_phy)) { 3634 ret = regulator_enable(fep->reg_phy); 3635 if (ret) { 3636 dev_err(&pdev->dev, 3637 "Failed to enable phy regulator: %d\n", ret); 3638 goto failed_regulator; 3639 } 3640 } else { 3641 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 3642 ret = -EPROBE_DEFER; 3643 goto failed_regulator; 3644 } 3645 fep->reg_phy = NULL; 3646 } 3647 3648 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3649 pm_runtime_use_autosuspend(&pdev->dev); 3650 pm_runtime_get_noresume(&pdev->dev); 3651 pm_runtime_set_active(&pdev->dev); 3652 pm_runtime_enable(&pdev->dev); 3653 3654 ret = fec_reset_phy(pdev); 3655 if (ret) 3656 goto failed_reset; 3657 3658 irq_cnt = fec_enet_get_irq_cnt(pdev); 3659 if (fep->bufdesc_ex) 3660 fec_ptp_init(pdev, irq_cnt); 3661 3662 ret = fec_enet_init(ndev); 3663 if (ret) 3664 goto failed_init; 3665 3666 for (i = 0; i < irq_cnt; i++) { 3667 snprintf(irq_name, sizeof(irq_name), "int%d", i); 3668 irq = platform_get_irq_byname_optional(pdev, irq_name); 3669 if (irq < 0) 3670 irq = platform_get_irq(pdev, i); 3671 if (irq < 0) { 3672 ret = irq; 3673 goto failed_irq; 3674 } 3675 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3676 0, pdev->name, ndev); 3677 if (ret) 3678 goto failed_irq; 3679 3680 fep->irq[i] = irq; 3681 } 3682 3683 ret = fec_enet_mii_init(pdev); 3684 if (ret) 3685 goto failed_mii_init; 3686 3687 /* Carrier starts down, phylib will bring it up */ 3688 netif_carrier_off(ndev); 3689 fec_enet_clk_enable(ndev, false); 3690 pinctrl_pm_select_sleep_state(&pdev->dev); 3691 3692 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN; 3693 3694 ret = register_netdev(ndev); 3695 if (ret) 3696 goto failed_register; 3697 3698 device_init_wakeup(&ndev->dev, fep->wol_flag & 3699 FEC_WOL_HAS_MAGIC_PACKET); 3700 3701 if (fep->bufdesc_ex && fep->ptp_clock) 3702 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3703 3704 fep->rx_copybreak = COPYBREAK_DEFAULT; 3705 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3706 3707 pm_runtime_mark_last_busy(&pdev->dev); 3708 pm_runtime_put_autosuspend(&pdev->dev); 3709 3710 return 0; 3711 3712 failed_register: 3713 fec_enet_mii_remove(fep); 3714 failed_mii_init: 3715 failed_irq: 3716 failed_init: 3717 fec_ptp_stop(pdev); 3718 failed_reset: 3719 pm_runtime_put_noidle(&pdev->dev); 3720 pm_runtime_disable(&pdev->dev); 3721 if (fep->reg_phy) 3722 regulator_disable(fep->reg_phy); 3723 failed_regulator: 3724 clk_disable_unprepare(fep->clk_ahb); 3725 failed_clk_ahb: 3726 clk_disable_unprepare(fep->clk_ipg); 3727 failed_clk_ipg: 3728 fec_enet_clk_enable(ndev, false); 3729 failed_clk: 3730 if (of_phy_is_fixed_link(np)) 3731 of_phy_deregister_fixed_link(np); 3732 of_node_put(phy_node); 3733 failed_stop_mode: 3734 failed_phy: 3735 dev_id--; 3736 failed_ioremap: 3737 free_netdev(ndev); 3738 3739 return ret; 3740 } 3741 3742 static int 3743 fec_drv_remove(struct platform_device *pdev) 3744 { 3745 struct net_device *ndev = platform_get_drvdata(pdev); 3746 struct fec_enet_private *fep = netdev_priv(ndev); 3747 struct device_node *np = pdev->dev.of_node; 3748 int ret; 3749 3750 ret = pm_runtime_get_sync(&pdev->dev); 3751 if (ret < 0) 3752 return ret; 3753 3754 cancel_work_sync(&fep->tx_timeout_work); 3755 fec_ptp_stop(pdev); 3756 unregister_netdev(ndev); 3757 fec_enet_mii_remove(fep); 3758 if (fep->reg_phy) 3759 regulator_disable(fep->reg_phy); 3760 3761 if (of_phy_is_fixed_link(np)) 3762 of_phy_deregister_fixed_link(np); 3763 of_node_put(fep->phy_node); 3764 free_netdev(ndev); 3765 3766 clk_disable_unprepare(fep->clk_ahb); 3767 clk_disable_unprepare(fep->clk_ipg); 3768 pm_runtime_put_noidle(&pdev->dev); 3769 pm_runtime_disable(&pdev->dev); 3770 3771 return 0; 3772 } 3773 3774 static int __maybe_unused fec_suspend(struct device *dev) 3775 { 3776 struct net_device *ndev = dev_get_drvdata(dev); 3777 struct fec_enet_private *fep = netdev_priv(ndev); 3778 3779 rtnl_lock(); 3780 if (netif_running(ndev)) { 3781 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 3782 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 3783 phy_stop(ndev->phydev); 3784 napi_disable(&fep->napi); 3785 netif_tx_lock_bh(ndev); 3786 netif_device_detach(ndev); 3787 netif_tx_unlock_bh(ndev); 3788 fec_stop(ndev); 3789 fec_enet_clk_enable(ndev, false); 3790 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3791 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3792 } 3793 rtnl_unlock(); 3794 3795 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3796 regulator_disable(fep->reg_phy); 3797 3798 /* SOC supply clock to phy, when clock is disabled, phy link down 3799 * SOC control phy regulator, when regulator is disabled, phy link down 3800 */ 3801 if (fep->clk_enet_out || fep->reg_phy) 3802 fep->link = 0; 3803 3804 return 0; 3805 } 3806 3807 static int __maybe_unused fec_resume(struct device *dev) 3808 { 3809 struct net_device *ndev = dev_get_drvdata(dev); 3810 struct fec_enet_private *fep = netdev_priv(ndev); 3811 int ret; 3812 int val; 3813 3814 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 3815 ret = regulator_enable(fep->reg_phy); 3816 if (ret) 3817 return ret; 3818 } 3819 3820 rtnl_lock(); 3821 if (netif_running(ndev)) { 3822 ret = fec_enet_clk_enable(ndev, true); 3823 if (ret) { 3824 rtnl_unlock(); 3825 goto failed_clk; 3826 } 3827 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 3828 fec_enet_stop_mode(fep, false); 3829 3830 val = readl(fep->hwp + FEC_ECNTRL); 3831 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 3832 writel(val, fep->hwp + FEC_ECNTRL); 3833 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 3834 } else { 3835 pinctrl_pm_select_default_state(&fep->pdev->dev); 3836 } 3837 fec_restart(ndev); 3838 netif_tx_lock_bh(ndev); 3839 netif_device_attach(ndev); 3840 netif_tx_unlock_bh(ndev); 3841 napi_enable(&fep->napi); 3842 phy_start(ndev->phydev); 3843 } 3844 rtnl_unlock(); 3845 3846 return 0; 3847 3848 failed_clk: 3849 if (fep->reg_phy) 3850 regulator_disable(fep->reg_phy); 3851 return ret; 3852 } 3853 3854 static int __maybe_unused fec_runtime_suspend(struct device *dev) 3855 { 3856 struct net_device *ndev = dev_get_drvdata(dev); 3857 struct fec_enet_private *fep = netdev_priv(ndev); 3858 3859 clk_disable_unprepare(fep->clk_ahb); 3860 clk_disable_unprepare(fep->clk_ipg); 3861 3862 return 0; 3863 } 3864 3865 static int __maybe_unused fec_runtime_resume(struct device *dev) 3866 { 3867 struct net_device *ndev = dev_get_drvdata(dev); 3868 struct fec_enet_private *fep = netdev_priv(ndev); 3869 int ret; 3870 3871 ret = clk_prepare_enable(fep->clk_ahb); 3872 if (ret) 3873 return ret; 3874 ret = clk_prepare_enable(fep->clk_ipg); 3875 if (ret) 3876 goto failed_clk_ipg; 3877 3878 return 0; 3879 3880 failed_clk_ipg: 3881 clk_disable_unprepare(fep->clk_ahb); 3882 return ret; 3883 } 3884 3885 static const struct dev_pm_ops fec_pm_ops = { 3886 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 3887 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 3888 }; 3889 3890 static struct platform_driver fec_driver = { 3891 .driver = { 3892 .name = DRIVER_NAME, 3893 .pm = &fec_pm_ops, 3894 .of_match_table = fec_dt_ids, 3895 .suppress_bind_attrs = true, 3896 }, 3897 .id_table = fec_devtype, 3898 .probe = fec_probe, 3899 .remove = fec_drv_remove, 3900 }; 3901 3902 module_platform_driver(fec_driver); 3903 3904 MODULE_ALIAS("platform:"DRIVER_NAME); 3905 MODULE_LICENSE("GPL"); 3906