1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
4  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5  *
6  * Right now, I am very wasteful with the buffers.  I allocate memory
7  * pages and then divide them into 2K frame buffers.  This way I know I
8  * have buffers large enough to hold one frame within one buffer descriptor.
9  * Once I get this working, I will use 64 or 128 byte CPM buffers, which
10  * will be much more memory efficient and will easily handle lots of
11  * small packets.
12  *
13  * Much better multiple PHY support by Magnus Damm.
14  * Copyright (c) 2000 Ericsson Radio Systems AB.
15  *
16  * Support for FEC controller of ColdFire processors.
17  * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18  *
19  * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
20  * Copyright (c) 2004-2006 Macq Electronique SA.
21  *
22  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
23  */
24 
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/string.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/ptrace.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/slab.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/in.h>
39 #include <linux/ip.h>
40 #include <net/ip.h>
41 #include <net/page_pool/helpers.h>
42 #include <net/selftests.h>
43 #include <net/tso.h>
44 #include <linux/tcp.h>
45 #include <linux/udp.h>
46 #include <linux/icmp.h>
47 #include <linux/spinlock.h>
48 #include <linux/workqueue.h>
49 #include <linux/bitops.h>
50 #include <linux/io.h>
51 #include <linux/irq.h>
52 #include <linux/clk.h>
53 #include <linux/crc32.h>
54 #include <linux/platform_device.h>
55 #include <linux/mdio.h>
56 #include <linux/phy.h>
57 #include <linux/fec.h>
58 #include <linux/of.h>
59 #include <linux/of_device.h>
60 #include <linux/of_mdio.h>
61 #include <linux/of_net.h>
62 #include <linux/regulator/consumer.h>
63 #include <linux/if_vlan.h>
64 #include <linux/pinctrl/consumer.h>
65 #include <linux/gpio/consumer.h>
66 #include <linux/prefetch.h>
67 #include <linux/mfd/syscon.h>
68 #include <linux/regmap.h>
69 #include <soc/imx/cpuidle.h>
70 #include <linux/filter.h>
71 #include <linux/bpf.h>
72 #include <linux/bpf_trace.h>
73 
74 #include <asm/cacheflush.h>
75 
76 #include "fec.h"
77 
78 static void set_multicast_list(struct net_device *ndev);
79 static void fec_enet_itr_coal_set(struct net_device *ndev);
80 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep,
81 				int cpu, struct xdp_buff *xdp,
82 				u32 dma_sync_len);
83 
84 #define DRIVER_NAME	"fec"
85 
86 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2};
87 
88 /* Pause frame feild and FIFO threshold */
89 #define FEC_ENET_FCE	(1 << 5)
90 #define FEC_ENET_RSEM_V	0x84
91 #define FEC_ENET_RSFL_V	16
92 #define FEC_ENET_RAEM_V	0x8
93 #define FEC_ENET_RAFL_V	0x8
94 #define FEC_ENET_OPD_V	0xFFF0
95 #define FEC_MDIO_PM_TIMEOUT  100 /* ms */
96 
97 #define FEC_ENET_XDP_PASS          0
98 #define FEC_ENET_XDP_CONSUMED      BIT(0)
99 #define FEC_ENET_XDP_TX            BIT(1)
100 #define FEC_ENET_XDP_REDIR         BIT(2)
101 
102 struct fec_devinfo {
103 	u32 quirks;
104 };
105 
106 static const struct fec_devinfo fec_imx25_info = {
107 	.quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR |
108 		  FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45,
109 };
110 
111 static const struct fec_devinfo fec_imx27_info = {
112 	.quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG |
113 		  FEC_QUIRK_HAS_MDIO_C45,
114 };
115 
116 static const struct fec_devinfo fec_imx28_info = {
117 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
118 		  FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
119 		  FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII |
120 		  FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45,
121 };
122 
123 static const struct fec_devinfo fec_imx6q_info = {
124 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
125 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
126 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
127 		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII |
128 		  FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45,
129 };
130 
131 static const struct fec_devinfo fec_mvf600_info = {
132 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC |
133 		  FEC_QUIRK_HAS_MDIO_C45,
134 };
135 
136 static const struct fec_devinfo fec_imx6x_info = {
137 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
138 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
139 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
140 		  FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
141 		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
142 		  FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
143 		  FEC_QUIRK_HAS_MDIO_C45,
144 };
145 
146 static const struct fec_devinfo fec_imx6ul_info = {
147 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
148 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
149 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
150 		  FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
151 		  FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII |
152 		  FEC_QUIRK_HAS_MDIO_C45,
153 };
154 
155 static const struct fec_devinfo fec_imx8mq_info = {
156 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
157 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
158 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
159 		  FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
160 		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
161 		  FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
162 		  FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 |
163 		  FEC_QUIRK_HAS_MDIO_C45,
164 };
165 
166 static const struct fec_devinfo fec_imx8qm_info = {
167 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
168 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
169 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
170 		  FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
171 		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
172 		  FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
173 		  FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45,
174 };
175 
176 static const struct fec_devinfo fec_s32v234_info = {
177 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
178 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
179 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
180 		  FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
181 		  FEC_QUIRK_HAS_MDIO_C45,
182 };
183 
184 static struct platform_device_id fec_devtype[] = {
185 	{
186 		/* keep it for coldfire */
187 		.name = DRIVER_NAME,
188 		.driver_data = 0,
189 	}, {
190 		.name = "imx25-fec",
191 		.driver_data = (kernel_ulong_t)&fec_imx25_info,
192 	}, {
193 		.name = "imx27-fec",
194 		.driver_data = (kernel_ulong_t)&fec_imx27_info,
195 	}, {
196 		.name = "imx28-fec",
197 		.driver_data = (kernel_ulong_t)&fec_imx28_info,
198 	}, {
199 		.name = "imx6q-fec",
200 		.driver_data = (kernel_ulong_t)&fec_imx6q_info,
201 	}, {
202 		.name = "mvf600-fec",
203 		.driver_data = (kernel_ulong_t)&fec_mvf600_info,
204 	}, {
205 		.name = "imx6sx-fec",
206 		.driver_data = (kernel_ulong_t)&fec_imx6x_info,
207 	}, {
208 		.name = "imx6ul-fec",
209 		.driver_data = (kernel_ulong_t)&fec_imx6ul_info,
210 	}, {
211 		.name = "imx8mq-fec",
212 		.driver_data = (kernel_ulong_t)&fec_imx8mq_info,
213 	}, {
214 		.name = "imx8qm-fec",
215 		.driver_data = (kernel_ulong_t)&fec_imx8qm_info,
216 	}, {
217 		.name = "s32v234-fec",
218 		.driver_data = (kernel_ulong_t)&fec_s32v234_info,
219 	}, {
220 		/* sentinel */
221 	}
222 };
223 MODULE_DEVICE_TABLE(platform, fec_devtype);
224 
225 enum imx_fec_type {
226 	IMX25_FEC = 1,	/* runs on i.mx25/50/53 */
227 	IMX27_FEC,	/* runs on i.mx27/35/51 */
228 	IMX28_FEC,
229 	IMX6Q_FEC,
230 	MVF600_FEC,
231 	IMX6SX_FEC,
232 	IMX6UL_FEC,
233 	IMX8MQ_FEC,
234 	IMX8QM_FEC,
235 	S32V234_FEC,
236 };
237 
238 static const struct of_device_id fec_dt_ids[] = {
239 	{ .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
240 	{ .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
241 	{ .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
242 	{ .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
243 	{ .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
244 	{ .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
245 	{ .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
246 	{ .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], },
247 	{ .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], },
248 	{ .compatible = "fsl,s32v234-fec", .data = &fec_devtype[S32V234_FEC], },
249 	{ /* sentinel */ }
250 };
251 MODULE_DEVICE_TABLE(of, fec_dt_ids);
252 
253 static unsigned char macaddr[ETH_ALEN];
254 module_param_array(macaddr, byte, NULL, 0);
255 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
256 
257 #if defined(CONFIG_M5272)
258 /*
259  * Some hardware gets it MAC address out of local flash memory.
260  * if this is non-zero then assume it is the address to get MAC from.
261  */
262 #if defined(CONFIG_NETtel)
263 #define	FEC_FLASHMAC	0xf0006006
264 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
265 #define	FEC_FLASHMAC	0xf0006000
266 #elif defined(CONFIG_CANCam)
267 #define	FEC_FLASHMAC	0xf0020000
268 #elif defined (CONFIG_M5272C3)
269 #define	FEC_FLASHMAC	(0xffe04000 + 4)
270 #elif defined(CONFIG_MOD5272)
271 #define FEC_FLASHMAC	0xffc0406b
272 #else
273 #define	FEC_FLASHMAC	0
274 #endif
275 #endif /* CONFIG_M5272 */
276 
277 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
278  *
279  * 2048 byte skbufs are allocated. However, alignment requirements
280  * varies between FEC variants. Worst case is 64, so round down by 64.
281  */
282 #define PKT_MAXBUF_SIZE		(round_down(2048 - 64, 64))
283 #define PKT_MINBUF_SIZE		64
284 
285 /* FEC receive acceleration */
286 #define FEC_RACC_IPDIS		(1 << 1)
287 #define FEC_RACC_PRODIS		(1 << 2)
288 #define FEC_RACC_SHIFT16	BIT(7)
289 #define FEC_RACC_OPTIONS	(FEC_RACC_IPDIS | FEC_RACC_PRODIS)
290 
291 /* MIB Control Register */
292 #define FEC_MIB_CTRLSTAT_DISABLE	BIT(31)
293 
294 /*
295  * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
296  * size bits. Other FEC hardware does not, so we need to take that into
297  * account when setting it.
298  */
299 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
300     defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
301     defined(CONFIG_ARM64)
302 #define	OPT_FRAME_SIZE	(PKT_MAXBUF_SIZE << 16)
303 #else
304 #define	OPT_FRAME_SIZE	0
305 #endif
306 
307 /* FEC MII MMFR bits definition */
308 #define FEC_MMFR_ST		(1 << 30)
309 #define FEC_MMFR_ST_C45		(0)
310 #define FEC_MMFR_OP_READ	(2 << 28)
311 #define FEC_MMFR_OP_READ_C45	(3 << 28)
312 #define FEC_MMFR_OP_WRITE	(1 << 28)
313 #define FEC_MMFR_OP_ADDR_WRITE	(0)
314 #define FEC_MMFR_PA(v)		((v & 0x1f) << 23)
315 #define FEC_MMFR_RA(v)		((v & 0x1f) << 18)
316 #define FEC_MMFR_TA		(2 << 16)
317 #define FEC_MMFR_DATA(v)	(v & 0xffff)
318 /* FEC ECR bits definition */
319 #define FEC_ECR_MAGICEN		(1 << 2)
320 #define FEC_ECR_SLEEP		(1 << 3)
321 
322 #define FEC_MII_TIMEOUT		30000 /* us */
323 
324 /* Transmitter timeout */
325 #define TX_TIMEOUT (2 * HZ)
326 
327 #define FEC_PAUSE_FLAG_AUTONEG	0x1
328 #define FEC_PAUSE_FLAG_ENABLE	0x2
329 #define FEC_WOL_HAS_MAGIC_PACKET	(0x1 << 0)
330 #define FEC_WOL_FLAG_ENABLE		(0x1 << 1)
331 #define FEC_WOL_FLAG_SLEEP_ON		(0x1 << 2)
332 
333 /* Max number of allowed TCP segments for software TSO */
334 #define FEC_MAX_TSO_SEGS	100
335 #define FEC_MAX_SKB_DESCS	(FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
336 
337 #define IS_TSO_HEADER(txq, addr) \
338 	((addr >= txq->tso_hdrs_dma) && \
339 	(addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
340 
341 static int mii_cnt;
342 
343 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
344 					     struct bufdesc_prop *bd)
345 {
346 	return (bdp >= bd->last) ? bd->base
347 			: (struct bufdesc *)(((void *)bdp) + bd->dsize);
348 }
349 
350 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
351 					     struct bufdesc_prop *bd)
352 {
353 	return (bdp <= bd->base) ? bd->last
354 			: (struct bufdesc *)(((void *)bdp) - bd->dsize);
355 }
356 
357 static int fec_enet_get_bd_index(struct bufdesc *bdp,
358 				 struct bufdesc_prop *bd)
359 {
360 	return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
361 }
362 
363 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
364 {
365 	int entries;
366 
367 	entries = (((const char *)txq->dirty_tx -
368 			(const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
369 
370 	return entries >= 0 ? entries : entries + txq->bd.ring_size;
371 }
372 
373 static void swap_buffer(void *bufaddr, int len)
374 {
375 	int i;
376 	unsigned int *buf = bufaddr;
377 
378 	for (i = 0; i < len; i += 4, buf++)
379 		swab32s(buf);
380 }
381 
382 static void fec_dump(struct net_device *ndev)
383 {
384 	struct fec_enet_private *fep = netdev_priv(ndev);
385 	struct bufdesc *bdp;
386 	struct fec_enet_priv_tx_q *txq;
387 	int index = 0;
388 
389 	netdev_info(ndev, "TX ring dump\n");
390 	pr_info("Nr     SC     addr       len  SKB\n");
391 
392 	txq = fep->tx_queue[0];
393 	bdp = txq->bd.base;
394 
395 	do {
396 		pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
397 			index,
398 			bdp == txq->bd.cur ? 'S' : ' ',
399 			bdp == txq->dirty_tx ? 'H' : ' ',
400 			fec16_to_cpu(bdp->cbd_sc),
401 			fec32_to_cpu(bdp->cbd_bufaddr),
402 			fec16_to_cpu(bdp->cbd_datlen),
403 			txq->tx_buf[index].buf_p);
404 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
405 		index++;
406 	} while (bdp != txq->bd.base);
407 }
408 
409 static inline bool is_ipv4_pkt(struct sk_buff *skb)
410 {
411 	return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
412 }
413 
414 static int
415 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
416 {
417 	/* Only run for packets requiring a checksum. */
418 	if (skb->ip_summed != CHECKSUM_PARTIAL)
419 		return 0;
420 
421 	if (unlikely(skb_cow_head(skb, 0)))
422 		return -1;
423 
424 	if (is_ipv4_pkt(skb))
425 		ip_hdr(skb)->check = 0;
426 	*(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
427 
428 	return 0;
429 }
430 
431 static int
432 fec_enet_create_page_pool(struct fec_enet_private *fep,
433 			  struct fec_enet_priv_rx_q *rxq, int size)
434 {
435 	struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog);
436 	struct page_pool_params pp_params = {
437 		.order = 0,
438 		.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
439 		.pool_size = size,
440 		.nid = dev_to_node(&fep->pdev->dev),
441 		.dev = &fep->pdev->dev,
442 		.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE,
443 		.offset = FEC_ENET_XDP_HEADROOM,
444 		.max_len = FEC_ENET_RX_FRSIZE,
445 	};
446 	int err;
447 
448 	rxq->page_pool = page_pool_create(&pp_params);
449 	if (IS_ERR(rxq->page_pool)) {
450 		err = PTR_ERR(rxq->page_pool);
451 		rxq->page_pool = NULL;
452 		return err;
453 	}
454 
455 	err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0);
456 	if (err < 0)
457 		goto err_free_pp;
458 
459 	err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL,
460 					 rxq->page_pool);
461 	if (err)
462 		goto err_unregister_rxq;
463 
464 	return 0;
465 
466 err_unregister_rxq:
467 	xdp_rxq_info_unreg(&rxq->xdp_rxq);
468 err_free_pp:
469 	page_pool_destroy(rxq->page_pool);
470 	rxq->page_pool = NULL;
471 	return err;
472 }
473 
474 static struct bufdesc *
475 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
476 			     struct sk_buff *skb,
477 			     struct net_device *ndev)
478 {
479 	struct fec_enet_private *fep = netdev_priv(ndev);
480 	struct bufdesc *bdp = txq->bd.cur;
481 	struct bufdesc_ex *ebdp;
482 	int nr_frags = skb_shinfo(skb)->nr_frags;
483 	int frag, frag_len;
484 	unsigned short status;
485 	unsigned int estatus = 0;
486 	skb_frag_t *this_frag;
487 	unsigned int index;
488 	void *bufaddr;
489 	dma_addr_t addr;
490 	int i;
491 
492 	for (frag = 0; frag < nr_frags; frag++) {
493 		this_frag = &skb_shinfo(skb)->frags[frag];
494 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
495 		ebdp = (struct bufdesc_ex *)bdp;
496 
497 		status = fec16_to_cpu(bdp->cbd_sc);
498 		status &= ~BD_ENET_TX_STATS;
499 		status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
500 		frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]);
501 
502 		/* Handle the last BD specially */
503 		if (frag == nr_frags - 1) {
504 			status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
505 			if (fep->bufdesc_ex) {
506 				estatus |= BD_ENET_TX_INT;
507 				if (unlikely(skb_shinfo(skb)->tx_flags &
508 					SKBTX_HW_TSTAMP && fep->hwts_tx_en))
509 					estatus |= BD_ENET_TX_TS;
510 			}
511 		}
512 
513 		if (fep->bufdesc_ex) {
514 			if (fep->quirks & FEC_QUIRK_HAS_AVB)
515 				estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
516 			if (skb->ip_summed == CHECKSUM_PARTIAL)
517 				estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
518 
519 			ebdp->cbd_bdu = 0;
520 			ebdp->cbd_esc = cpu_to_fec32(estatus);
521 		}
522 
523 		bufaddr = skb_frag_address(this_frag);
524 
525 		index = fec_enet_get_bd_index(bdp, &txq->bd);
526 		if (((unsigned long) bufaddr) & fep->tx_align ||
527 			fep->quirks & FEC_QUIRK_SWAP_FRAME) {
528 			memcpy(txq->tx_bounce[index], bufaddr, frag_len);
529 			bufaddr = txq->tx_bounce[index];
530 
531 			if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
532 				swap_buffer(bufaddr, frag_len);
533 		}
534 
535 		addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
536 				      DMA_TO_DEVICE);
537 		if (dma_mapping_error(&fep->pdev->dev, addr)) {
538 			if (net_ratelimit())
539 				netdev_err(ndev, "Tx DMA memory map failed\n");
540 			goto dma_mapping_error;
541 		}
542 
543 		bdp->cbd_bufaddr = cpu_to_fec32(addr);
544 		bdp->cbd_datlen = cpu_to_fec16(frag_len);
545 		/* Make sure the updates to rest of the descriptor are
546 		 * performed before transferring ownership.
547 		 */
548 		wmb();
549 		bdp->cbd_sc = cpu_to_fec16(status);
550 	}
551 
552 	return bdp;
553 dma_mapping_error:
554 	bdp = txq->bd.cur;
555 	for (i = 0; i < frag; i++) {
556 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
557 		dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
558 				 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
559 	}
560 	return ERR_PTR(-ENOMEM);
561 }
562 
563 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
564 				   struct sk_buff *skb, struct net_device *ndev)
565 {
566 	struct fec_enet_private *fep = netdev_priv(ndev);
567 	int nr_frags = skb_shinfo(skb)->nr_frags;
568 	struct bufdesc *bdp, *last_bdp;
569 	void *bufaddr;
570 	dma_addr_t addr;
571 	unsigned short status;
572 	unsigned short buflen;
573 	unsigned int estatus = 0;
574 	unsigned int index;
575 	int entries_free;
576 
577 	entries_free = fec_enet_get_free_txdesc_num(txq);
578 	if (entries_free < MAX_SKB_FRAGS + 1) {
579 		dev_kfree_skb_any(skb);
580 		if (net_ratelimit())
581 			netdev_err(ndev, "NOT enough BD for SG!\n");
582 		return NETDEV_TX_OK;
583 	}
584 
585 	/* Protocol checksum off-load for TCP and UDP. */
586 	if (fec_enet_clear_csum(skb, ndev)) {
587 		dev_kfree_skb_any(skb);
588 		return NETDEV_TX_OK;
589 	}
590 
591 	/* Fill in a Tx ring entry */
592 	bdp = txq->bd.cur;
593 	last_bdp = bdp;
594 	status = fec16_to_cpu(bdp->cbd_sc);
595 	status &= ~BD_ENET_TX_STATS;
596 
597 	/* Set buffer length and buffer pointer */
598 	bufaddr = skb->data;
599 	buflen = skb_headlen(skb);
600 
601 	index = fec_enet_get_bd_index(bdp, &txq->bd);
602 	if (((unsigned long) bufaddr) & fep->tx_align ||
603 		fep->quirks & FEC_QUIRK_SWAP_FRAME) {
604 		memcpy(txq->tx_bounce[index], skb->data, buflen);
605 		bufaddr = txq->tx_bounce[index];
606 
607 		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
608 			swap_buffer(bufaddr, buflen);
609 	}
610 
611 	/* Push the data cache so the CPM does not get stale memory data. */
612 	addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
613 	if (dma_mapping_error(&fep->pdev->dev, addr)) {
614 		dev_kfree_skb_any(skb);
615 		if (net_ratelimit())
616 			netdev_err(ndev, "Tx DMA memory map failed\n");
617 		return NETDEV_TX_OK;
618 	}
619 
620 	if (nr_frags) {
621 		last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
622 		if (IS_ERR(last_bdp)) {
623 			dma_unmap_single(&fep->pdev->dev, addr,
624 					 buflen, DMA_TO_DEVICE);
625 			dev_kfree_skb_any(skb);
626 			return NETDEV_TX_OK;
627 		}
628 	} else {
629 		status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
630 		if (fep->bufdesc_ex) {
631 			estatus = BD_ENET_TX_INT;
632 			if (unlikely(skb_shinfo(skb)->tx_flags &
633 				SKBTX_HW_TSTAMP && fep->hwts_tx_en))
634 				estatus |= BD_ENET_TX_TS;
635 		}
636 	}
637 	bdp->cbd_bufaddr = cpu_to_fec32(addr);
638 	bdp->cbd_datlen = cpu_to_fec16(buflen);
639 
640 	if (fep->bufdesc_ex) {
641 
642 		struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
643 
644 		if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
645 			fep->hwts_tx_en))
646 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
647 
648 		if (fep->quirks & FEC_QUIRK_HAS_AVB)
649 			estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
650 
651 		if (skb->ip_summed == CHECKSUM_PARTIAL)
652 			estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
653 
654 		ebdp->cbd_bdu = 0;
655 		ebdp->cbd_esc = cpu_to_fec32(estatus);
656 	}
657 
658 	index = fec_enet_get_bd_index(last_bdp, &txq->bd);
659 	/* Save skb pointer */
660 	txq->tx_buf[index].buf_p = skb;
661 
662 	/* Make sure the updates to rest of the descriptor are performed before
663 	 * transferring ownership.
664 	 */
665 	wmb();
666 
667 	/* Send it on its way.  Tell FEC it's ready, interrupt when done,
668 	 * it's the last BD of the frame, and to put the CRC on the end.
669 	 */
670 	status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
671 	bdp->cbd_sc = cpu_to_fec16(status);
672 
673 	/* If this was the last BD in the ring, start at the beginning again. */
674 	bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
675 
676 	skb_tx_timestamp(skb);
677 
678 	/* Make sure the update to bdp is performed before txq->bd.cur. */
679 	wmb();
680 	txq->bd.cur = bdp;
681 
682 	/* Trigger transmission start */
683 	writel(0, txq->bd.reg_desc_active);
684 
685 	return 0;
686 }
687 
688 static int
689 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
690 			  struct net_device *ndev,
691 			  struct bufdesc *bdp, int index, char *data,
692 			  int size, bool last_tcp, bool is_last)
693 {
694 	struct fec_enet_private *fep = netdev_priv(ndev);
695 	struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
696 	unsigned short status;
697 	unsigned int estatus = 0;
698 	dma_addr_t addr;
699 
700 	status = fec16_to_cpu(bdp->cbd_sc);
701 	status &= ~BD_ENET_TX_STATS;
702 
703 	status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
704 
705 	if (((unsigned long) data) & fep->tx_align ||
706 		fep->quirks & FEC_QUIRK_SWAP_FRAME) {
707 		memcpy(txq->tx_bounce[index], data, size);
708 		data = txq->tx_bounce[index];
709 
710 		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
711 			swap_buffer(data, size);
712 	}
713 
714 	addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
715 	if (dma_mapping_error(&fep->pdev->dev, addr)) {
716 		dev_kfree_skb_any(skb);
717 		if (net_ratelimit())
718 			netdev_err(ndev, "Tx DMA memory map failed\n");
719 		return NETDEV_TX_OK;
720 	}
721 
722 	bdp->cbd_datlen = cpu_to_fec16(size);
723 	bdp->cbd_bufaddr = cpu_to_fec32(addr);
724 
725 	if (fep->bufdesc_ex) {
726 		if (fep->quirks & FEC_QUIRK_HAS_AVB)
727 			estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
728 		if (skb->ip_summed == CHECKSUM_PARTIAL)
729 			estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
730 		ebdp->cbd_bdu = 0;
731 		ebdp->cbd_esc = cpu_to_fec32(estatus);
732 	}
733 
734 	/* Handle the last BD specially */
735 	if (last_tcp)
736 		status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
737 	if (is_last) {
738 		status |= BD_ENET_TX_INTR;
739 		if (fep->bufdesc_ex)
740 			ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
741 	}
742 
743 	bdp->cbd_sc = cpu_to_fec16(status);
744 
745 	return 0;
746 }
747 
748 static int
749 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
750 			 struct sk_buff *skb, struct net_device *ndev,
751 			 struct bufdesc *bdp, int index)
752 {
753 	struct fec_enet_private *fep = netdev_priv(ndev);
754 	int hdr_len = skb_tcp_all_headers(skb);
755 	struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
756 	void *bufaddr;
757 	unsigned long dmabuf;
758 	unsigned short status;
759 	unsigned int estatus = 0;
760 
761 	status = fec16_to_cpu(bdp->cbd_sc);
762 	status &= ~BD_ENET_TX_STATS;
763 	status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
764 
765 	bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
766 	dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
767 	if (((unsigned long)bufaddr) & fep->tx_align ||
768 		fep->quirks & FEC_QUIRK_SWAP_FRAME) {
769 		memcpy(txq->tx_bounce[index], skb->data, hdr_len);
770 		bufaddr = txq->tx_bounce[index];
771 
772 		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
773 			swap_buffer(bufaddr, hdr_len);
774 
775 		dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
776 					hdr_len, DMA_TO_DEVICE);
777 		if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
778 			dev_kfree_skb_any(skb);
779 			if (net_ratelimit())
780 				netdev_err(ndev, "Tx DMA memory map failed\n");
781 			return NETDEV_TX_OK;
782 		}
783 	}
784 
785 	bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
786 	bdp->cbd_datlen = cpu_to_fec16(hdr_len);
787 
788 	if (fep->bufdesc_ex) {
789 		if (fep->quirks & FEC_QUIRK_HAS_AVB)
790 			estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
791 		if (skb->ip_summed == CHECKSUM_PARTIAL)
792 			estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
793 		ebdp->cbd_bdu = 0;
794 		ebdp->cbd_esc = cpu_to_fec32(estatus);
795 	}
796 
797 	bdp->cbd_sc = cpu_to_fec16(status);
798 
799 	return 0;
800 }
801 
802 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
803 				   struct sk_buff *skb,
804 				   struct net_device *ndev)
805 {
806 	struct fec_enet_private *fep = netdev_priv(ndev);
807 	int hdr_len, total_len, data_left;
808 	struct bufdesc *bdp = txq->bd.cur;
809 	struct tso_t tso;
810 	unsigned int index = 0;
811 	int ret;
812 
813 	if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
814 		dev_kfree_skb_any(skb);
815 		if (net_ratelimit())
816 			netdev_err(ndev, "NOT enough BD for TSO!\n");
817 		return NETDEV_TX_OK;
818 	}
819 
820 	/* Protocol checksum off-load for TCP and UDP. */
821 	if (fec_enet_clear_csum(skb, ndev)) {
822 		dev_kfree_skb_any(skb);
823 		return NETDEV_TX_OK;
824 	}
825 
826 	/* Initialize the TSO handler, and prepare the first payload */
827 	hdr_len = tso_start(skb, &tso);
828 
829 	total_len = skb->len - hdr_len;
830 	while (total_len > 0) {
831 		char *hdr;
832 
833 		index = fec_enet_get_bd_index(bdp, &txq->bd);
834 		data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
835 		total_len -= data_left;
836 
837 		/* prepare packet headers: MAC + IP + TCP */
838 		hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
839 		tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
840 		ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
841 		if (ret)
842 			goto err_release;
843 
844 		while (data_left > 0) {
845 			int size;
846 
847 			size = min_t(int, tso.size, data_left);
848 			bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
849 			index = fec_enet_get_bd_index(bdp, &txq->bd);
850 			ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
851 							bdp, index,
852 							tso.data, size,
853 							size == data_left,
854 							total_len == 0);
855 			if (ret)
856 				goto err_release;
857 
858 			data_left -= size;
859 			tso_build_data(skb, &tso, size);
860 		}
861 
862 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
863 	}
864 
865 	/* Save skb pointer */
866 	txq->tx_buf[index].buf_p = skb;
867 
868 	skb_tx_timestamp(skb);
869 	txq->bd.cur = bdp;
870 
871 	/* Trigger transmission start */
872 	if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
873 	    !readl(txq->bd.reg_desc_active) ||
874 	    !readl(txq->bd.reg_desc_active) ||
875 	    !readl(txq->bd.reg_desc_active) ||
876 	    !readl(txq->bd.reg_desc_active))
877 		writel(0, txq->bd.reg_desc_active);
878 
879 	return 0;
880 
881 err_release:
882 	/* TODO: Release all used data descriptors for TSO */
883 	return ret;
884 }
885 
886 static netdev_tx_t
887 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
888 {
889 	struct fec_enet_private *fep = netdev_priv(ndev);
890 	int entries_free;
891 	unsigned short queue;
892 	struct fec_enet_priv_tx_q *txq;
893 	struct netdev_queue *nq;
894 	int ret;
895 
896 	queue = skb_get_queue_mapping(skb);
897 	txq = fep->tx_queue[queue];
898 	nq = netdev_get_tx_queue(ndev, queue);
899 
900 	if (skb_is_gso(skb))
901 		ret = fec_enet_txq_submit_tso(txq, skb, ndev);
902 	else
903 		ret = fec_enet_txq_submit_skb(txq, skb, ndev);
904 	if (ret)
905 		return ret;
906 
907 	entries_free = fec_enet_get_free_txdesc_num(txq);
908 	if (entries_free <= txq->tx_stop_threshold)
909 		netif_tx_stop_queue(nq);
910 
911 	return NETDEV_TX_OK;
912 }
913 
914 /* Init RX & TX buffer descriptors
915  */
916 static void fec_enet_bd_init(struct net_device *dev)
917 {
918 	struct fec_enet_private *fep = netdev_priv(dev);
919 	struct fec_enet_priv_tx_q *txq;
920 	struct fec_enet_priv_rx_q *rxq;
921 	struct bufdesc *bdp;
922 	unsigned int i;
923 	unsigned int q;
924 
925 	for (q = 0; q < fep->num_rx_queues; q++) {
926 		/* Initialize the receive buffer descriptors. */
927 		rxq = fep->rx_queue[q];
928 		bdp = rxq->bd.base;
929 
930 		for (i = 0; i < rxq->bd.ring_size; i++) {
931 
932 			/* Initialize the BD for every fragment in the page. */
933 			if (bdp->cbd_bufaddr)
934 				bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
935 			else
936 				bdp->cbd_sc = cpu_to_fec16(0);
937 			bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
938 		}
939 
940 		/* Set the last buffer to wrap */
941 		bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
942 		bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
943 
944 		rxq->bd.cur = rxq->bd.base;
945 	}
946 
947 	for (q = 0; q < fep->num_tx_queues; q++) {
948 		/* ...and the same for transmit */
949 		txq = fep->tx_queue[q];
950 		bdp = txq->bd.base;
951 		txq->bd.cur = bdp;
952 
953 		for (i = 0; i < txq->bd.ring_size; i++) {
954 			/* Initialize the BD for every fragment in the page. */
955 			bdp->cbd_sc = cpu_to_fec16(0);
956 			if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) {
957 				if (bdp->cbd_bufaddr &&
958 				    !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
959 					dma_unmap_single(&fep->pdev->dev,
960 							 fec32_to_cpu(bdp->cbd_bufaddr),
961 							 fec16_to_cpu(bdp->cbd_datlen),
962 							 DMA_TO_DEVICE);
963 				if (txq->tx_buf[i].buf_p)
964 					dev_kfree_skb_any(txq->tx_buf[i].buf_p);
965 			} else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) {
966 				if (bdp->cbd_bufaddr)
967 					dma_unmap_single(&fep->pdev->dev,
968 							 fec32_to_cpu(bdp->cbd_bufaddr),
969 							 fec16_to_cpu(bdp->cbd_datlen),
970 							 DMA_TO_DEVICE);
971 
972 				if (txq->tx_buf[i].buf_p)
973 					xdp_return_frame(txq->tx_buf[i].buf_p);
974 			} else {
975 				struct page *page = txq->tx_buf[i].buf_p;
976 
977 				if (page)
978 					page_pool_put_page(page->pp, page, 0, false);
979 			}
980 
981 			txq->tx_buf[i].buf_p = NULL;
982 			/* restore default tx buffer type: FEC_TXBUF_T_SKB */
983 			txq->tx_buf[i].type = FEC_TXBUF_T_SKB;
984 			bdp->cbd_bufaddr = cpu_to_fec32(0);
985 			bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
986 		}
987 
988 		/* Set the last buffer to wrap */
989 		bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
990 		bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
991 		txq->dirty_tx = bdp;
992 	}
993 }
994 
995 static void fec_enet_active_rxring(struct net_device *ndev)
996 {
997 	struct fec_enet_private *fep = netdev_priv(ndev);
998 	int i;
999 
1000 	for (i = 0; i < fep->num_rx_queues; i++)
1001 		writel(0, fep->rx_queue[i]->bd.reg_desc_active);
1002 }
1003 
1004 static void fec_enet_enable_ring(struct net_device *ndev)
1005 {
1006 	struct fec_enet_private *fep = netdev_priv(ndev);
1007 	struct fec_enet_priv_tx_q *txq;
1008 	struct fec_enet_priv_rx_q *rxq;
1009 	int i;
1010 
1011 	for (i = 0; i < fep->num_rx_queues; i++) {
1012 		rxq = fep->rx_queue[i];
1013 		writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
1014 		writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
1015 
1016 		/* enable DMA1/2 */
1017 		if (i)
1018 			writel(RCMR_MATCHEN | RCMR_CMP(i),
1019 			       fep->hwp + FEC_RCMR(i));
1020 	}
1021 
1022 	for (i = 0; i < fep->num_tx_queues; i++) {
1023 		txq = fep->tx_queue[i];
1024 		writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
1025 
1026 		/* enable DMA1/2 */
1027 		if (i)
1028 			writel(DMA_CLASS_EN | IDLE_SLOPE(i),
1029 			       fep->hwp + FEC_DMA_CFG(i));
1030 	}
1031 }
1032 
1033 /*
1034  * This function is called to start or restart the FEC during a link
1035  * change, transmit timeout, or to reconfigure the FEC.  The network
1036  * packet processing for this device must be stopped before this call.
1037  */
1038 static void
1039 fec_restart(struct net_device *ndev)
1040 {
1041 	struct fec_enet_private *fep = netdev_priv(ndev);
1042 	u32 temp_mac[2];
1043 	u32 rcntl = OPT_FRAME_SIZE | 0x04;
1044 	u32 ecntl = 0x2; /* ETHEREN */
1045 
1046 	/* Whack a reset.  We should wait for this.
1047 	 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1048 	 * instead of reset MAC itself.
1049 	 */
1050 	if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES ||
1051 	    ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) {
1052 		writel(0, fep->hwp + FEC_ECNTRL);
1053 	} else {
1054 		writel(1, fep->hwp + FEC_ECNTRL);
1055 		udelay(10);
1056 	}
1057 
1058 	/*
1059 	 * enet-mac reset will reset mac address registers too,
1060 	 * so need to reconfigure it.
1061 	 */
1062 	memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
1063 	writel((__force u32)cpu_to_be32(temp_mac[0]),
1064 	       fep->hwp + FEC_ADDR_LOW);
1065 	writel((__force u32)cpu_to_be32(temp_mac[1]),
1066 	       fep->hwp + FEC_ADDR_HIGH);
1067 
1068 	/* Clear any outstanding interrupt, except MDIO. */
1069 	writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT);
1070 
1071 	fec_enet_bd_init(ndev);
1072 
1073 	fec_enet_enable_ring(ndev);
1074 
1075 	/* Enable MII mode */
1076 	if (fep->full_duplex == DUPLEX_FULL) {
1077 		/* FD enable */
1078 		writel(0x04, fep->hwp + FEC_X_CNTRL);
1079 	} else {
1080 		/* No Rcv on Xmit */
1081 		rcntl |= 0x02;
1082 		writel(0x0, fep->hwp + FEC_X_CNTRL);
1083 	}
1084 
1085 	/* Set MII speed */
1086 	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1087 
1088 #if !defined(CONFIG_M5272)
1089 	if (fep->quirks & FEC_QUIRK_HAS_RACC) {
1090 		u32 val = readl(fep->hwp + FEC_RACC);
1091 
1092 		/* align IP header */
1093 		val |= FEC_RACC_SHIFT16;
1094 		if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
1095 			/* set RX checksum */
1096 			val |= FEC_RACC_OPTIONS;
1097 		else
1098 			val &= ~FEC_RACC_OPTIONS;
1099 		writel(val, fep->hwp + FEC_RACC);
1100 		writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
1101 	}
1102 #endif
1103 
1104 	/*
1105 	 * The phy interface and speed need to get configured
1106 	 * differently on enet-mac.
1107 	 */
1108 	if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1109 		/* Enable flow control and length check */
1110 		rcntl |= 0x40000000 | 0x00000020;
1111 
1112 		/* RGMII, RMII or MII */
1113 		if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
1114 		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1115 		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1116 		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1117 			rcntl |= (1 << 6);
1118 		else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1119 			rcntl |= (1 << 8);
1120 		else
1121 			rcntl &= ~(1 << 8);
1122 
1123 		/* 1G, 100M or 10M */
1124 		if (ndev->phydev) {
1125 			if (ndev->phydev->speed == SPEED_1000)
1126 				ecntl |= (1 << 5);
1127 			else if (ndev->phydev->speed == SPEED_100)
1128 				rcntl &= ~(1 << 9);
1129 			else
1130 				rcntl |= (1 << 9);
1131 		}
1132 	} else {
1133 #ifdef FEC_MIIGSK_ENR
1134 		if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1135 			u32 cfgr;
1136 			/* disable the gasket and wait */
1137 			writel(0, fep->hwp + FEC_MIIGSK_ENR);
1138 			while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1139 				udelay(1);
1140 
1141 			/*
1142 			 * configure the gasket:
1143 			 *   RMII, 50 MHz, no loopback, no echo
1144 			 *   MII, 25 MHz, no loopback, no echo
1145 			 */
1146 			cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1147 				? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1148 			if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1149 				cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1150 			writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1151 
1152 			/* re-enable the gasket */
1153 			writel(2, fep->hwp + FEC_MIIGSK_ENR);
1154 		}
1155 #endif
1156 	}
1157 
1158 #if !defined(CONFIG_M5272)
1159 	/* enable pause frame*/
1160 	if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1161 	    ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1162 	     ndev->phydev && ndev->phydev->pause)) {
1163 		rcntl |= FEC_ENET_FCE;
1164 
1165 		/* set FIFO threshold parameter to reduce overrun */
1166 		writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1167 		writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1168 		writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1169 		writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1170 
1171 		/* OPD */
1172 		writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1173 	} else {
1174 		rcntl &= ~FEC_ENET_FCE;
1175 	}
1176 #endif /* !defined(CONFIG_M5272) */
1177 
1178 	writel(rcntl, fep->hwp + FEC_R_CNTRL);
1179 
1180 	/* Setup multicast filter. */
1181 	set_multicast_list(ndev);
1182 #ifndef CONFIG_M5272
1183 	writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1184 	writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1185 #endif
1186 
1187 	if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1188 		/* enable ENET endian swap */
1189 		ecntl |= (1 << 8);
1190 		/* enable ENET store and forward mode */
1191 		writel(1 << 8, fep->hwp + FEC_X_WMRK);
1192 	}
1193 
1194 	if (fep->bufdesc_ex)
1195 		ecntl |= (1 << 4);
1196 
1197 	if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT &&
1198 	    fep->rgmii_txc_dly)
1199 		ecntl |= FEC_ENET_TXC_DLY;
1200 	if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT &&
1201 	    fep->rgmii_rxc_dly)
1202 		ecntl |= FEC_ENET_RXC_DLY;
1203 
1204 #ifndef CONFIG_M5272
1205 	/* Enable the MIB statistic event counters */
1206 	writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1207 #endif
1208 
1209 	/* And last, enable the transmit and receive processing */
1210 	writel(ecntl, fep->hwp + FEC_ECNTRL);
1211 	fec_enet_active_rxring(ndev);
1212 
1213 	if (fep->bufdesc_ex)
1214 		fec_ptp_start_cyclecounter(ndev);
1215 
1216 	/* Enable interrupts we wish to service */
1217 	if (fep->link)
1218 		writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1219 	else
1220 		writel(0, fep->hwp + FEC_IMASK);
1221 
1222 	/* Init the interrupt coalescing */
1223 	if (fep->quirks & FEC_QUIRK_HAS_COALESCE)
1224 		fec_enet_itr_coal_set(ndev);
1225 }
1226 
1227 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep)
1228 {
1229 	if (!(of_machine_is_compatible("fsl,imx8qm") ||
1230 	      of_machine_is_compatible("fsl,imx8qxp") ||
1231 	      of_machine_is_compatible("fsl,imx8dxl")))
1232 		return 0;
1233 
1234 	return imx_scu_get_handle(&fep->ipc_handle);
1235 }
1236 
1237 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled)
1238 {
1239 	struct device_node *np = fep->pdev->dev.of_node;
1240 	u32 rsrc_id, val;
1241 	int idx;
1242 
1243 	if (!np || !fep->ipc_handle)
1244 		return;
1245 
1246 	idx = of_alias_get_id(np, "ethernet");
1247 	if (idx < 0)
1248 		idx = 0;
1249 	rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0;
1250 
1251 	val = enabled ? 1 : 0;
1252 	imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val);
1253 }
1254 
1255 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled)
1256 {
1257 	struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1258 	struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr;
1259 
1260 	if (stop_gpr->gpr) {
1261 		if (enabled)
1262 			regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1263 					   BIT(stop_gpr->bit),
1264 					   BIT(stop_gpr->bit));
1265 		else
1266 			regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1267 					   BIT(stop_gpr->bit), 0);
1268 	} else if (pdata && pdata->sleep_mode_enable) {
1269 		pdata->sleep_mode_enable(enabled);
1270 	} else {
1271 		fec_enet_ipg_stop_set(fep, enabled);
1272 	}
1273 }
1274 
1275 static void fec_irqs_disable(struct net_device *ndev)
1276 {
1277 	struct fec_enet_private *fep = netdev_priv(ndev);
1278 
1279 	writel(0, fep->hwp + FEC_IMASK);
1280 }
1281 
1282 static void fec_irqs_disable_except_wakeup(struct net_device *ndev)
1283 {
1284 	struct fec_enet_private *fep = netdev_priv(ndev);
1285 
1286 	writel(0, fep->hwp + FEC_IMASK);
1287 	writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1288 }
1289 
1290 static void
1291 fec_stop(struct net_device *ndev)
1292 {
1293 	struct fec_enet_private *fep = netdev_priv(ndev);
1294 	u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1295 	u32 val;
1296 
1297 	/* We cannot expect a graceful transmit stop without link !!! */
1298 	if (fep->link) {
1299 		writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1300 		udelay(10);
1301 		if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1302 			netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1303 	}
1304 
1305 	/* Whack a reset.  We should wait for this.
1306 	 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1307 	 * instead of reset MAC itself.
1308 	 */
1309 	if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1310 		if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
1311 			writel(0, fep->hwp + FEC_ECNTRL);
1312 		} else {
1313 			writel(1, fep->hwp + FEC_ECNTRL);
1314 			udelay(10);
1315 		}
1316 	} else {
1317 		val = readl(fep->hwp + FEC_ECNTRL);
1318 		val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1319 		writel(val, fep->hwp + FEC_ECNTRL);
1320 	}
1321 	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1322 	writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1323 
1324 	/* We have to keep ENET enabled to have MII interrupt stay working */
1325 	if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1326 		!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1327 		writel(2, fep->hwp + FEC_ECNTRL);
1328 		writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1329 	}
1330 }
1331 
1332 
1333 static void
1334 fec_timeout(struct net_device *ndev, unsigned int txqueue)
1335 {
1336 	struct fec_enet_private *fep = netdev_priv(ndev);
1337 
1338 	fec_dump(ndev);
1339 
1340 	ndev->stats.tx_errors++;
1341 
1342 	schedule_work(&fep->tx_timeout_work);
1343 }
1344 
1345 static void fec_enet_timeout_work(struct work_struct *work)
1346 {
1347 	struct fec_enet_private *fep =
1348 		container_of(work, struct fec_enet_private, tx_timeout_work);
1349 	struct net_device *ndev = fep->netdev;
1350 
1351 	rtnl_lock();
1352 	if (netif_device_present(ndev) || netif_running(ndev)) {
1353 		napi_disable(&fep->napi);
1354 		netif_tx_lock_bh(ndev);
1355 		fec_restart(ndev);
1356 		netif_tx_wake_all_queues(ndev);
1357 		netif_tx_unlock_bh(ndev);
1358 		napi_enable(&fep->napi);
1359 	}
1360 	rtnl_unlock();
1361 }
1362 
1363 static void
1364 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1365 	struct skb_shared_hwtstamps *hwtstamps)
1366 {
1367 	unsigned long flags;
1368 	u64 ns;
1369 
1370 	spin_lock_irqsave(&fep->tmreg_lock, flags);
1371 	ns = timecounter_cyc2time(&fep->tc, ts);
1372 	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1373 
1374 	memset(hwtstamps, 0, sizeof(*hwtstamps));
1375 	hwtstamps->hwtstamp = ns_to_ktime(ns);
1376 }
1377 
1378 static void
1379 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget)
1380 {
1381 	struct	fec_enet_private *fep;
1382 	struct xdp_frame *xdpf;
1383 	struct bufdesc *bdp;
1384 	unsigned short status;
1385 	struct	sk_buff	*skb;
1386 	struct fec_enet_priv_tx_q *txq;
1387 	struct netdev_queue *nq;
1388 	int	index = 0;
1389 	int	entries_free;
1390 	struct page *page;
1391 	int frame_len;
1392 
1393 	fep = netdev_priv(ndev);
1394 
1395 	txq = fep->tx_queue[queue_id];
1396 	/* get next bdp of dirty_tx */
1397 	nq = netdev_get_tx_queue(ndev, queue_id);
1398 	bdp = txq->dirty_tx;
1399 
1400 	/* get next bdp of dirty_tx */
1401 	bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1402 
1403 	while (bdp != READ_ONCE(txq->bd.cur)) {
1404 		/* Order the load of bd.cur and cbd_sc */
1405 		rmb();
1406 		status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1407 		if (status & BD_ENET_TX_READY)
1408 			break;
1409 
1410 		index = fec_enet_get_bd_index(bdp, &txq->bd);
1411 
1412 		if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) {
1413 			skb = txq->tx_buf[index].buf_p;
1414 			if (bdp->cbd_bufaddr &&
1415 			    !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1416 				dma_unmap_single(&fep->pdev->dev,
1417 						 fec32_to_cpu(bdp->cbd_bufaddr),
1418 						 fec16_to_cpu(bdp->cbd_datlen),
1419 						 DMA_TO_DEVICE);
1420 			bdp->cbd_bufaddr = cpu_to_fec32(0);
1421 			if (!skb)
1422 				goto tx_buf_done;
1423 		} else {
1424 			/* Tx processing cannot call any XDP (or page pool) APIs if
1425 			 * the "budget" is 0. Because NAPI is called with budget of
1426 			 * 0 (such as netpoll) indicates we may be in an IRQ context,
1427 			 * however, we can't use the page pool from IRQ context.
1428 			 */
1429 			if (unlikely(!budget))
1430 				break;
1431 
1432 			if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) {
1433 				xdpf = txq->tx_buf[index].buf_p;
1434 				if (bdp->cbd_bufaddr)
1435 					dma_unmap_single(&fep->pdev->dev,
1436 							 fec32_to_cpu(bdp->cbd_bufaddr),
1437 							 fec16_to_cpu(bdp->cbd_datlen),
1438 							 DMA_TO_DEVICE);
1439 			} else {
1440 				page = txq->tx_buf[index].buf_p;
1441 			}
1442 
1443 			bdp->cbd_bufaddr = cpu_to_fec32(0);
1444 			if (unlikely(!txq->tx_buf[index].buf_p)) {
1445 				txq->tx_buf[index].type = FEC_TXBUF_T_SKB;
1446 				goto tx_buf_done;
1447 			}
1448 
1449 			frame_len = fec16_to_cpu(bdp->cbd_datlen);
1450 		}
1451 
1452 		/* Check for errors. */
1453 		if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1454 				   BD_ENET_TX_RL | BD_ENET_TX_UN |
1455 				   BD_ENET_TX_CSL)) {
1456 			ndev->stats.tx_errors++;
1457 			if (status & BD_ENET_TX_HB)  /* No heartbeat */
1458 				ndev->stats.tx_heartbeat_errors++;
1459 			if (status & BD_ENET_TX_LC)  /* Late collision */
1460 				ndev->stats.tx_window_errors++;
1461 			if (status & BD_ENET_TX_RL)  /* Retrans limit */
1462 				ndev->stats.tx_aborted_errors++;
1463 			if (status & BD_ENET_TX_UN)  /* Underrun */
1464 				ndev->stats.tx_fifo_errors++;
1465 			if (status & BD_ENET_TX_CSL) /* Carrier lost */
1466 				ndev->stats.tx_carrier_errors++;
1467 		} else {
1468 			ndev->stats.tx_packets++;
1469 
1470 			if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB)
1471 				ndev->stats.tx_bytes += skb->len;
1472 			else
1473 				ndev->stats.tx_bytes += frame_len;
1474 		}
1475 
1476 		/* Deferred means some collisions occurred during transmit,
1477 		 * but we eventually sent the packet OK.
1478 		 */
1479 		if (status & BD_ENET_TX_DEF)
1480 			ndev->stats.collisions++;
1481 
1482 		if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) {
1483 			/* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who
1484 			 * are to time stamp the packet, so we still need to check time
1485 			 * stamping enabled flag.
1486 			 */
1487 			if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS &&
1488 				     fep->hwts_tx_en) && fep->bufdesc_ex) {
1489 				struct skb_shared_hwtstamps shhwtstamps;
1490 				struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1491 
1492 				fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1493 				skb_tstamp_tx(skb, &shhwtstamps);
1494 			}
1495 
1496 			/* Free the sk buffer associated with this last transmit */
1497 			napi_consume_skb(skb, budget);
1498 		} else if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) {
1499 			xdp_return_frame_rx_napi(xdpf);
1500 		} else { /* recycle pages of XDP_TX frames */
1501 			/* The dma_sync_size = 0 as XDP_TX has already synced DMA for_device */
1502 			page_pool_put_page(page->pp, page, 0, true);
1503 		}
1504 
1505 		txq->tx_buf[index].buf_p = NULL;
1506 		/* restore default tx buffer type: FEC_TXBUF_T_SKB */
1507 		txq->tx_buf[index].type = FEC_TXBUF_T_SKB;
1508 
1509 tx_buf_done:
1510 		/* Make sure the update to bdp and tx_buf are performed
1511 		 * before dirty_tx
1512 		 */
1513 		wmb();
1514 		txq->dirty_tx = bdp;
1515 
1516 		/* Update pointer to next buffer descriptor to be transmitted */
1517 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1518 
1519 		/* Since we have freed up a buffer, the ring is no longer full
1520 		 */
1521 		if (netif_tx_queue_stopped(nq)) {
1522 			entries_free = fec_enet_get_free_txdesc_num(txq);
1523 			if (entries_free >= txq->tx_wake_threshold)
1524 				netif_tx_wake_queue(nq);
1525 		}
1526 	}
1527 
1528 	/* ERR006358: Keep the transmitter going */
1529 	if (bdp != txq->bd.cur &&
1530 	    readl(txq->bd.reg_desc_active) == 0)
1531 		writel(0, txq->bd.reg_desc_active);
1532 }
1533 
1534 static void fec_enet_tx(struct net_device *ndev, int budget)
1535 {
1536 	struct fec_enet_private *fep = netdev_priv(ndev);
1537 	int i;
1538 
1539 	/* Make sure that AVB queues are processed first. */
1540 	for (i = fep->num_tx_queues - 1; i >= 0; i--)
1541 		fec_enet_tx_queue(ndev, i, budget);
1542 }
1543 
1544 static void fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq,
1545 				struct bufdesc *bdp, int index)
1546 {
1547 	struct page *new_page;
1548 	dma_addr_t phys_addr;
1549 
1550 	new_page = page_pool_dev_alloc_pages(rxq->page_pool);
1551 	WARN_ON(!new_page);
1552 	rxq->rx_skb_info[index].page = new_page;
1553 
1554 	rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM;
1555 	phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM;
1556 	bdp->cbd_bufaddr = cpu_to_fec32(phys_addr);
1557 }
1558 
1559 static u32
1560 fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog,
1561 		 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int cpu)
1562 {
1563 	unsigned int sync, len = xdp->data_end - xdp->data;
1564 	u32 ret = FEC_ENET_XDP_PASS;
1565 	struct page *page;
1566 	int err;
1567 	u32 act;
1568 
1569 	act = bpf_prog_run_xdp(prog, xdp);
1570 
1571 	/* Due xdp_adjust_tail and xdp_adjust_head: DMA sync for_device cover
1572 	 * max len CPU touch
1573 	 */
1574 	sync = xdp->data_end - xdp->data;
1575 	sync = max(sync, len);
1576 
1577 	switch (act) {
1578 	case XDP_PASS:
1579 		rxq->stats[RX_XDP_PASS]++;
1580 		ret = FEC_ENET_XDP_PASS;
1581 		break;
1582 
1583 	case XDP_REDIRECT:
1584 		rxq->stats[RX_XDP_REDIRECT]++;
1585 		err = xdp_do_redirect(fep->netdev, xdp, prog);
1586 		if (unlikely(err))
1587 			goto xdp_err;
1588 
1589 		ret = FEC_ENET_XDP_REDIR;
1590 		break;
1591 
1592 	case XDP_TX:
1593 		rxq->stats[RX_XDP_TX]++;
1594 		err = fec_enet_xdp_tx_xmit(fep, cpu, xdp, sync);
1595 		if (unlikely(err)) {
1596 			rxq->stats[RX_XDP_TX_ERRORS]++;
1597 			goto xdp_err;
1598 		}
1599 
1600 		ret = FEC_ENET_XDP_TX;
1601 		break;
1602 
1603 	default:
1604 		bpf_warn_invalid_xdp_action(fep->netdev, prog, act);
1605 		fallthrough;
1606 
1607 	case XDP_ABORTED:
1608 		fallthrough;    /* handle aborts by dropping packet */
1609 
1610 	case XDP_DROP:
1611 		rxq->stats[RX_XDP_DROP]++;
1612 xdp_err:
1613 		ret = FEC_ENET_XDP_CONSUMED;
1614 		page = virt_to_head_page(xdp->data);
1615 		page_pool_put_page(rxq->page_pool, page, sync, true);
1616 		if (act != XDP_DROP)
1617 			trace_xdp_exception(fep->netdev, prog, act);
1618 		break;
1619 	}
1620 
1621 	return ret;
1622 }
1623 
1624 /* During a receive, the bd_rx.cur points to the current incoming buffer.
1625  * When we update through the ring, if the next incoming buffer has
1626  * not been given to the system, we just set the empty indicator,
1627  * effectively tossing the packet.
1628  */
1629 static int
1630 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1631 {
1632 	struct fec_enet_private *fep = netdev_priv(ndev);
1633 	struct fec_enet_priv_rx_q *rxq;
1634 	struct bufdesc *bdp;
1635 	unsigned short status;
1636 	struct  sk_buff *skb;
1637 	ushort	pkt_len;
1638 	__u8 *data;
1639 	int	pkt_received = 0;
1640 	struct	bufdesc_ex *ebdp = NULL;
1641 	bool	vlan_packet_rcvd = false;
1642 	u16	vlan_tag;
1643 	int	index = 0;
1644 	bool	need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1645 	struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog);
1646 	u32 ret, xdp_result = FEC_ENET_XDP_PASS;
1647 	u32 data_start = FEC_ENET_XDP_HEADROOM;
1648 	int cpu = smp_processor_id();
1649 	struct xdp_buff xdp;
1650 	struct page *page;
1651 	u32 sub_len = 4;
1652 
1653 #if !defined(CONFIG_M5272)
1654 	/*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of
1655 	 * FEC_RACC_SHIFT16 is set by default in the probe function.
1656 	 */
1657 	if (fep->quirks & FEC_QUIRK_HAS_RACC) {
1658 		data_start += 2;
1659 		sub_len += 2;
1660 	}
1661 #endif
1662 
1663 #ifdef CONFIG_M532x
1664 	flush_cache_all();
1665 #endif
1666 	rxq = fep->rx_queue[queue_id];
1667 
1668 	/* First, grab all of the stats for the incoming packet.
1669 	 * These get messed up if we get called due to a busy condition.
1670 	 */
1671 	bdp = rxq->bd.cur;
1672 	xdp_init_buff(&xdp, PAGE_SIZE, &rxq->xdp_rxq);
1673 
1674 	while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1675 
1676 		if (pkt_received >= budget)
1677 			break;
1678 		pkt_received++;
1679 
1680 		writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT);
1681 
1682 		/* Check for errors. */
1683 		status ^= BD_ENET_RX_LAST;
1684 		if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1685 			   BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1686 			   BD_ENET_RX_CL)) {
1687 			ndev->stats.rx_errors++;
1688 			if (status & BD_ENET_RX_OV) {
1689 				/* FIFO overrun */
1690 				ndev->stats.rx_fifo_errors++;
1691 				goto rx_processing_done;
1692 			}
1693 			if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1694 						| BD_ENET_RX_LAST)) {
1695 				/* Frame too long or too short. */
1696 				ndev->stats.rx_length_errors++;
1697 				if (status & BD_ENET_RX_LAST)
1698 					netdev_err(ndev, "rcv is not +last\n");
1699 			}
1700 			if (status & BD_ENET_RX_CR)	/* CRC Error */
1701 				ndev->stats.rx_crc_errors++;
1702 			/* Report late collisions as a frame error. */
1703 			if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1704 				ndev->stats.rx_frame_errors++;
1705 			goto rx_processing_done;
1706 		}
1707 
1708 		/* Process the incoming frame. */
1709 		ndev->stats.rx_packets++;
1710 		pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1711 		ndev->stats.rx_bytes += pkt_len;
1712 
1713 		index = fec_enet_get_bd_index(bdp, &rxq->bd);
1714 		page = rxq->rx_skb_info[index].page;
1715 		dma_sync_single_for_cpu(&fep->pdev->dev,
1716 					fec32_to_cpu(bdp->cbd_bufaddr),
1717 					pkt_len,
1718 					DMA_FROM_DEVICE);
1719 		prefetch(page_address(page));
1720 		fec_enet_update_cbd(rxq, bdp, index);
1721 
1722 		if (xdp_prog) {
1723 			xdp_buff_clear_frags_flag(&xdp);
1724 			/* subtract 16bit shift and FCS */
1725 			xdp_prepare_buff(&xdp, page_address(page),
1726 					 data_start, pkt_len - sub_len, false);
1727 			ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, cpu);
1728 			xdp_result |= ret;
1729 			if (ret != FEC_ENET_XDP_PASS)
1730 				goto rx_processing_done;
1731 		}
1732 
1733 		/* The packet length includes FCS, but we don't want to
1734 		 * include that when passing upstream as it messes up
1735 		 * bridging applications.
1736 		 */
1737 		skb = build_skb(page_address(page), PAGE_SIZE);
1738 		if (unlikely(!skb)) {
1739 			page_pool_recycle_direct(rxq->page_pool, page);
1740 			ndev->stats.rx_dropped++;
1741 
1742 			netdev_err_once(ndev, "build_skb failed!\n");
1743 			goto rx_processing_done;
1744 		}
1745 
1746 		skb_reserve(skb, data_start);
1747 		skb_put(skb, pkt_len - sub_len);
1748 		skb_mark_for_recycle(skb);
1749 
1750 		if (unlikely(need_swap)) {
1751 			data = page_address(page) + FEC_ENET_XDP_HEADROOM;
1752 			swap_buffer(data, pkt_len);
1753 		}
1754 		data = skb->data;
1755 
1756 		/* Extract the enhanced buffer descriptor */
1757 		ebdp = NULL;
1758 		if (fep->bufdesc_ex)
1759 			ebdp = (struct bufdesc_ex *)bdp;
1760 
1761 		/* If this is a VLAN packet remove the VLAN Tag */
1762 		vlan_packet_rcvd = false;
1763 		if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1764 		    fep->bufdesc_ex &&
1765 		    (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1766 			/* Push and remove the vlan tag */
1767 			struct vlan_hdr *vlan_header =
1768 					(struct vlan_hdr *) (data + ETH_HLEN);
1769 			vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1770 
1771 			vlan_packet_rcvd = true;
1772 
1773 			memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1774 			skb_pull(skb, VLAN_HLEN);
1775 		}
1776 
1777 		skb->protocol = eth_type_trans(skb, ndev);
1778 
1779 		/* Get receive timestamp from the skb */
1780 		if (fep->hwts_rx_en && fep->bufdesc_ex)
1781 			fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1782 					  skb_hwtstamps(skb));
1783 
1784 		if (fep->bufdesc_ex &&
1785 		    (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1786 			if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1787 				/* don't check it */
1788 				skb->ip_summed = CHECKSUM_UNNECESSARY;
1789 			} else {
1790 				skb_checksum_none_assert(skb);
1791 			}
1792 		}
1793 
1794 		/* Handle received VLAN packets */
1795 		if (vlan_packet_rcvd)
1796 			__vlan_hwaccel_put_tag(skb,
1797 					       htons(ETH_P_8021Q),
1798 					       vlan_tag);
1799 
1800 		skb_record_rx_queue(skb, queue_id);
1801 		napi_gro_receive(&fep->napi, skb);
1802 
1803 rx_processing_done:
1804 		/* Clear the status flags for this buffer */
1805 		status &= ~BD_ENET_RX_STATS;
1806 
1807 		/* Mark the buffer empty */
1808 		status |= BD_ENET_RX_EMPTY;
1809 
1810 		if (fep->bufdesc_ex) {
1811 			struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1812 
1813 			ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1814 			ebdp->cbd_prot = 0;
1815 			ebdp->cbd_bdu = 0;
1816 		}
1817 		/* Make sure the updates to rest of the descriptor are
1818 		 * performed before transferring ownership.
1819 		 */
1820 		wmb();
1821 		bdp->cbd_sc = cpu_to_fec16(status);
1822 
1823 		/* Update BD pointer to next entry */
1824 		bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1825 
1826 		/* Doing this here will keep the FEC running while we process
1827 		 * incoming frames.  On a heavily loaded network, we should be
1828 		 * able to keep up at the expense of system resources.
1829 		 */
1830 		writel(0, rxq->bd.reg_desc_active);
1831 	}
1832 	rxq->bd.cur = bdp;
1833 
1834 	if (xdp_result & FEC_ENET_XDP_REDIR)
1835 		xdp_do_flush_map();
1836 
1837 	return pkt_received;
1838 }
1839 
1840 static int fec_enet_rx(struct net_device *ndev, int budget)
1841 {
1842 	struct fec_enet_private *fep = netdev_priv(ndev);
1843 	int i, done = 0;
1844 
1845 	/* Make sure that AVB queues are processed first. */
1846 	for (i = fep->num_rx_queues - 1; i >= 0; i--)
1847 		done += fec_enet_rx_queue(ndev, budget - done, i);
1848 
1849 	return done;
1850 }
1851 
1852 static bool fec_enet_collect_events(struct fec_enet_private *fep)
1853 {
1854 	uint int_events;
1855 
1856 	int_events = readl(fep->hwp + FEC_IEVENT);
1857 
1858 	/* Don't clear MDIO events, we poll for those */
1859 	int_events &= ~FEC_ENET_MII;
1860 
1861 	writel(int_events, fep->hwp + FEC_IEVENT);
1862 
1863 	return int_events != 0;
1864 }
1865 
1866 static irqreturn_t
1867 fec_enet_interrupt(int irq, void *dev_id)
1868 {
1869 	struct net_device *ndev = dev_id;
1870 	struct fec_enet_private *fep = netdev_priv(ndev);
1871 	irqreturn_t ret = IRQ_NONE;
1872 
1873 	if (fec_enet_collect_events(fep) && fep->link) {
1874 		ret = IRQ_HANDLED;
1875 
1876 		if (napi_schedule_prep(&fep->napi)) {
1877 			/* Disable interrupts */
1878 			writel(0, fep->hwp + FEC_IMASK);
1879 			__napi_schedule(&fep->napi);
1880 		}
1881 	}
1882 
1883 	return ret;
1884 }
1885 
1886 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1887 {
1888 	struct net_device *ndev = napi->dev;
1889 	struct fec_enet_private *fep = netdev_priv(ndev);
1890 	int done = 0;
1891 
1892 	do {
1893 		done += fec_enet_rx(ndev, budget - done);
1894 		fec_enet_tx(ndev, budget);
1895 	} while ((done < budget) && fec_enet_collect_events(fep));
1896 
1897 	if (done < budget) {
1898 		napi_complete_done(napi, done);
1899 		writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1900 	}
1901 
1902 	return done;
1903 }
1904 
1905 /* ------------------------------------------------------------------------- */
1906 static int fec_get_mac(struct net_device *ndev)
1907 {
1908 	struct fec_enet_private *fep = netdev_priv(ndev);
1909 	unsigned char *iap, tmpaddr[ETH_ALEN];
1910 	int ret;
1911 
1912 	/*
1913 	 * try to get mac address in following order:
1914 	 *
1915 	 * 1) module parameter via kernel command line in form
1916 	 *    fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1917 	 */
1918 	iap = macaddr;
1919 
1920 	/*
1921 	 * 2) from device tree data
1922 	 */
1923 	if (!is_valid_ether_addr(iap)) {
1924 		struct device_node *np = fep->pdev->dev.of_node;
1925 		if (np) {
1926 			ret = of_get_mac_address(np, tmpaddr);
1927 			if (!ret)
1928 				iap = tmpaddr;
1929 			else if (ret == -EPROBE_DEFER)
1930 				return ret;
1931 		}
1932 	}
1933 
1934 	/*
1935 	 * 3) from flash or fuse (via platform data)
1936 	 */
1937 	if (!is_valid_ether_addr(iap)) {
1938 #ifdef CONFIG_M5272
1939 		if (FEC_FLASHMAC)
1940 			iap = (unsigned char *)FEC_FLASHMAC;
1941 #else
1942 		struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1943 
1944 		if (pdata)
1945 			iap = (unsigned char *)&pdata->mac;
1946 #endif
1947 	}
1948 
1949 	/*
1950 	 * 4) FEC mac registers set by bootloader
1951 	 */
1952 	if (!is_valid_ether_addr(iap)) {
1953 		*((__be32 *) &tmpaddr[0]) =
1954 			cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1955 		*((__be16 *) &tmpaddr[4]) =
1956 			cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1957 		iap = &tmpaddr[0];
1958 	}
1959 
1960 	/*
1961 	 * 5) random mac address
1962 	 */
1963 	if (!is_valid_ether_addr(iap)) {
1964 		/* Report it and use a random ethernet address instead */
1965 		dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap);
1966 		eth_hw_addr_random(ndev);
1967 		dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n",
1968 			 ndev->dev_addr);
1969 		return 0;
1970 	}
1971 
1972 	/* Adjust MAC if using macaddr */
1973 	eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0);
1974 
1975 	return 0;
1976 }
1977 
1978 /* ------------------------------------------------------------------------- */
1979 
1980 /*
1981  * Phy section
1982  */
1983 static void fec_enet_adjust_link(struct net_device *ndev)
1984 {
1985 	struct fec_enet_private *fep = netdev_priv(ndev);
1986 	struct phy_device *phy_dev = ndev->phydev;
1987 	int status_change = 0;
1988 
1989 	/*
1990 	 * If the netdev is down, or is going down, we're not interested
1991 	 * in link state events, so just mark our idea of the link as down
1992 	 * and ignore the event.
1993 	 */
1994 	if (!netif_running(ndev) || !netif_device_present(ndev)) {
1995 		fep->link = 0;
1996 	} else if (phy_dev->link) {
1997 		if (!fep->link) {
1998 			fep->link = phy_dev->link;
1999 			status_change = 1;
2000 		}
2001 
2002 		if (fep->full_duplex != phy_dev->duplex) {
2003 			fep->full_duplex = phy_dev->duplex;
2004 			status_change = 1;
2005 		}
2006 
2007 		if (phy_dev->speed != fep->speed) {
2008 			fep->speed = phy_dev->speed;
2009 			status_change = 1;
2010 		}
2011 
2012 		/* if any of the above changed restart the FEC */
2013 		if (status_change) {
2014 			netif_stop_queue(ndev);
2015 			napi_disable(&fep->napi);
2016 			netif_tx_lock_bh(ndev);
2017 			fec_restart(ndev);
2018 			netif_tx_wake_all_queues(ndev);
2019 			netif_tx_unlock_bh(ndev);
2020 			napi_enable(&fep->napi);
2021 		}
2022 	} else {
2023 		if (fep->link) {
2024 			netif_stop_queue(ndev);
2025 			napi_disable(&fep->napi);
2026 			netif_tx_lock_bh(ndev);
2027 			fec_stop(ndev);
2028 			netif_tx_unlock_bh(ndev);
2029 			napi_enable(&fep->napi);
2030 			fep->link = phy_dev->link;
2031 			status_change = 1;
2032 		}
2033 	}
2034 
2035 	if (status_change)
2036 		phy_print_status(phy_dev);
2037 }
2038 
2039 static int fec_enet_mdio_wait(struct fec_enet_private *fep)
2040 {
2041 	uint ievent;
2042 	int ret;
2043 
2044 	ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent,
2045 					ievent & FEC_ENET_MII, 2, 30000);
2046 
2047 	if (!ret)
2048 		writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
2049 
2050 	return ret;
2051 }
2052 
2053 static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum)
2054 {
2055 	struct fec_enet_private *fep = bus->priv;
2056 	struct device *dev = &fep->pdev->dev;
2057 	int ret = 0, frame_start, frame_addr, frame_op;
2058 
2059 	ret = pm_runtime_resume_and_get(dev);
2060 	if (ret < 0)
2061 		return ret;
2062 
2063 	/* C22 read */
2064 	frame_op = FEC_MMFR_OP_READ;
2065 	frame_start = FEC_MMFR_ST;
2066 	frame_addr = regnum;
2067 
2068 	/* start a read op */
2069 	writel(frame_start | frame_op |
2070 	       FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
2071 	       FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
2072 
2073 	/* wait for end of transfer */
2074 	ret = fec_enet_mdio_wait(fep);
2075 	if (ret) {
2076 		netdev_err(fep->netdev, "MDIO read timeout\n");
2077 		goto out;
2078 	}
2079 
2080 	ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
2081 
2082 out:
2083 	pm_runtime_mark_last_busy(dev);
2084 	pm_runtime_put_autosuspend(dev);
2085 
2086 	return ret;
2087 }
2088 
2089 static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id,
2090 				  int devad, int regnum)
2091 {
2092 	struct fec_enet_private *fep = bus->priv;
2093 	struct device *dev = &fep->pdev->dev;
2094 	int ret = 0, frame_start, frame_op;
2095 
2096 	ret = pm_runtime_resume_and_get(dev);
2097 	if (ret < 0)
2098 		return ret;
2099 
2100 	frame_start = FEC_MMFR_ST_C45;
2101 
2102 	/* write address */
2103 	writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
2104 	       FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2105 	       FEC_MMFR_TA | (regnum & 0xFFFF),
2106 	       fep->hwp + FEC_MII_DATA);
2107 
2108 	/* wait for end of transfer */
2109 	ret = fec_enet_mdio_wait(fep);
2110 	if (ret) {
2111 		netdev_err(fep->netdev, "MDIO address write timeout\n");
2112 		goto out;
2113 	}
2114 
2115 	frame_op = FEC_MMFR_OP_READ_C45;
2116 
2117 	/* start a read op */
2118 	writel(frame_start | frame_op |
2119 	       FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2120 	       FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
2121 
2122 	/* wait for end of transfer */
2123 	ret = fec_enet_mdio_wait(fep);
2124 	if (ret) {
2125 		netdev_err(fep->netdev, "MDIO read timeout\n");
2126 		goto out;
2127 	}
2128 
2129 	ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
2130 
2131 out:
2132 	pm_runtime_mark_last_busy(dev);
2133 	pm_runtime_put_autosuspend(dev);
2134 
2135 	return ret;
2136 }
2137 
2138 static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,
2139 				   u16 value)
2140 {
2141 	struct fec_enet_private *fep = bus->priv;
2142 	struct device *dev = &fep->pdev->dev;
2143 	int ret, frame_start, frame_addr;
2144 
2145 	ret = pm_runtime_resume_and_get(dev);
2146 	if (ret < 0)
2147 		return ret;
2148 
2149 	/* C22 write */
2150 	frame_start = FEC_MMFR_ST;
2151 	frame_addr = regnum;
2152 
2153 	/* start a write op */
2154 	writel(frame_start | FEC_MMFR_OP_WRITE |
2155 	       FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
2156 	       FEC_MMFR_TA | FEC_MMFR_DATA(value),
2157 	       fep->hwp + FEC_MII_DATA);
2158 
2159 	/* wait for end of transfer */
2160 	ret = fec_enet_mdio_wait(fep);
2161 	if (ret)
2162 		netdev_err(fep->netdev, "MDIO write timeout\n");
2163 
2164 	pm_runtime_mark_last_busy(dev);
2165 	pm_runtime_put_autosuspend(dev);
2166 
2167 	return ret;
2168 }
2169 
2170 static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id,
2171 				   int devad, int regnum, u16 value)
2172 {
2173 	struct fec_enet_private *fep = bus->priv;
2174 	struct device *dev = &fep->pdev->dev;
2175 	int ret, frame_start;
2176 
2177 	ret = pm_runtime_resume_and_get(dev);
2178 	if (ret < 0)
2179 		return ret;
2180 
2181 	frame_start = FEC_MMFR_ST_C45;
2182 
2183 	/* write address */
2184 	writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
2185 	       FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2186 	       FEC_MMFR_TA | (regnum & 0xFFFF),
2187 	       fep->hwp + FEC_MII_DATA);
2188 
2189 	/* wait for end of transfer */
2190 	ret = fec_enet_mdio_wait(fep);
2191 	if (ret) {
2192 		netdev_err(fep->netdev, "MDIO address write timeout\n");
2193 		goto out;
2194 	}
2195 
2196 	/* start a write op */
2197 	writel(frame_start | FEC_MMFR_OP_WRITE |
2198 	       FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2199 	       FEC_MMFR_TA | FEC_MMFR_DATA(value),
2200 	       fep->hwp + FEC_MII_DATA);
2201 
2202 	/* wait for end of transfer */
2203 	ret = fec_enet_mdio_wait(fep);
2204 	if (ret)
2205 		netdev_err(fep->netdev, "MDIO write timeout\n");
2206 
2207 out:
2208 	pm_runtime_mark_last_busy(dev);
2209 	pm_runtime_put_autosuspend(dev);
2210 
2211 	return ret;
2212 }
2213 
2214 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev)
2215 {
2216 	struct fec_enet_private *fep = netdev_priv(ndev);
2217 	struct phy_device *phy_dev = ndev->phydev;
2218 
2219 	if (phy_dev) {
2220 		phy_reset_after_clk_enable(phy_dev);
2221 	} else if (fep->phy_node) {
2222 		/*
2223 		 * If the PHY still is not bound to the MAC, but there is
2224 		 * OF PHY node and a matching PHY device instance already,
2225 		 * use the OF PHY node to obtain the PHY device instance,
2226 		 * and then use that PHY device instance when triggering
2227 		 * the PHY reset.
2228 		 */
2229 		phy_dev = of_phy_find_device(fep->phy_node);
2230 		phy_reset_after_clk_enable(phy_dev);
2231 		put_device(&phy_dev->mdio.dev);
2232 	}
2233 }
2234 
2235 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
2236 {
2237 	struct fec_enet_private *fep = netdev_priv(ndev);
2238 	int ret;
2239 
2240 	if (enable) {
2241 		ret = clk_prepare_enable(fep->clk_enet_out);
2242 		if (ret)
2243 			return ret;
2244 
2245 		if (fep->clk_ptp) {
2246 			mutex_lock(&fep->ptp_clk_mutex);
2247 			ret = clk_prepare_enable(fep->clk_ptp);
2248 			if (ret) {
2249 				mutex_unlock(&fep->ptp_clk_mutex);
2250 				goto failed_clk_ptp;
2251 			} else {
2252 				fep->ptp_clk_on = true;
2253 			}
2254 			mutex_unlock(&fep->ptp_clk_mutex);
2255 		}
2256 
2257 		ret = clk_prepare_enable(fep->clk_ref);
2258 		if (ret)
2259 			goto failed_clk_ref;
2260 
2261 		ret = clk_prepare_enable(fep->clk_2x_txclk);
2262 		if (ret)
2263 			goto failed_clk_2x_txclk;
2264 
2265 		fec_enet_phy_reset_after_clk_enable(ndev);
2266 	} else {
2267 		clk_disable_unprepare(fep->clk_enet_out);
2268 		if (fep->clk_ptp) {
2269 			mutex_lock(&fep->ptp_clk_mutex);
2270 			clk_disable_unprepare(fep->clk_ptp);
2271 			fep->ptp_clk_on = false;
2272 			mutex_unlock(&fep->ptp_clk_mutex);
2273 		}
2274 		clk_disable_unprepare(fep->clk_ref);
2275 		clk_disable_unprepare(fep->clk_2x_txclk);
2276 	}
2277 
2278 	return 0;
2279 
2280 failed_clk_2x_txclk:
2281 	if (fep->clk_ref)
2282 		clk_disable_unprepare(fep->clk_ref);
2283 failed_clk_ref:
2284 	if (fep->clk_ptp) {
2285 		mutex_lock(&fep->ptp_clk_mutex);
2286 		clk_disable_unprepare(fep->clk_ptp);
2287 		fep->ptp_clk_on = false;
2288 		mutex_unlock(&fep->ptp_clk_mutex);
2289 	}
2290 failed_clk_ptp:
2291 	clk_disable_unprepare(fep->clk_enet_out);
2292 
2293 	return ret;
2294 }
2295 
2296 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep,
2297 				      struct device_node *np)
2298 {
2299 	u32 rgmii_tx_delay, rgmii_rx_delay;
2300 
2301 	/* For rgmii tx internal delay, valid values are 0ps and 2000ps */
2302 	if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) {
2303 		if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) {
2304 			dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps");
2305 			return -EINVAL;
2306 		} else if (rgmii_tx_delay == 2000) {
2307 			fep->rgmii_txc_dly = true;
2308 		}
2309 	}
2310 
2311 	/* For rgmii rx internal delay, valid values are 0ps and 2000ps */
2312 	if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) {
2313 		if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) {
2314 			dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps");
2315 			return -EINVAL;
2316 		} else if (rgmii_rx_delay == 2000) {
2317 			fep->rgmii_rxc_dly = true;
2318 		}
2319 	}
2320 
2321 	return 0;
2322 }
2323 
2324 static int fec_enet_mii_probe(struct net_device *ndev)
2325 {
2326 	struct fec_enet_private *fep = netdev_priv(ndev);
2327 	struct phy_device *phy_dev = NULL;
2328 	char mdio_bus_id[MII_BUS_ID_SIZE];
2329 	char phy_name[MII_BUS_ID_SIZE + 3];
2330 	int phy_id;
2331 	int dev_id = fep->dev_id;
2332 
2333 	if (fep->phy_node) {
2334 		phy_dev = of_phy_connect(ndev, fep->phy_node,
2335 					 &fec_enet_adjust_link, 0,
2336 					 fep->phy_interface);
2337 		if (!phy_dev) {
2338 			netdev_err(ndev, "Unable to connect to phy\n");
2339 			return -ENODEV;
2340 		}
2341 	} else {
2342 		/* check for attached phy */
2343 		for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
2344 			if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
2345 				continue;
2346 			if (dev_id--)
2347 				continue;
2348 			strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
2349 			break;
2350 		}
2351 
2352 		if (phy_id >= PHY_MAX_ADDR) {
2353 			netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
2354 			strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
2355 			phy_id = 0;
2356 		}
2357 
2358 		snprintf(phy_name, sizeof(phy_name),
2359 			 PHY_ID_FMT, mdio_bus_id, phy_id);
2360 		phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
2361 				      fep->phy_interface);
2362 	}
2363 
2364 	if (IS_ERR(phy_dev)) {
2365 		netdev_err(ndev, "could not attach to PHY\n");
2366 		return PTR_ERR(phy_dev);
2367 	}
2368 
2369 	/* mask with MAC supported features */
2370 	if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
2371 		phy_set_max_speed(phy_dev, 1000);
2372 		phy_remove_link_mode(phy_dev,
2373 				     ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
2374 #if !defined(CONFIG_M5272)
2375 		phy_support_sym_pause(phy_dev);
2376 #endif
2377 	}
2378 	else
2379 		phy_set_max_speed(phy_dev, 100);
2380 
2381 	fep->link = 0;
2382 	fep->full_duplex = 0;
2383 
2384 	phy_attached_info(phy_dev);
2385 
2386 	return 0;
2387 }
2388 
2389 static int fec_enet_mii_init(struct platform_device *pdev)
2390 {
2391 	static struct mii_bus *fec0_mii_bus;
2392 	struct net_device *ndev = platform_get_drvdata(pdev);
2393 	struct fec_enet_private *fep = netdev_priv(ndev);
2394 	bool suppress_preamble = false;
2395 	struct phy_device *phydev;
2396 	struct device_node *node;
2397 	int err = -ENXIO;
2398 	u32 mii_speed, holdtime;
2399 	u32 bus_freq;
2400 	int addr;
2401 
2402 	/*
2403 	 * The i.MX28 dual fec interfaces are not equal.
2404 	 * Here are the differences:
2405 	 *
2406 	 *  - fec0 supports MII & RMII modes while fec1 only supports RMII
2407 	 *  - fec0 acts as the 1588 time master while fec1 is slave
2408 	 *  - external phys can only be configured by fec0
2409 	 *
2410 	 * That is to say fec1 can not work independently. It only works
2411 	 * when fec0 is working. The reason behind this design is that the
2412 	 * second interface is added primarily for Switch mode.
2413 	 *
2414 	 * Because of the last point above, both phys are attached on fec0
2415 	 * mdio interface in board design, and need to be configured by
2416 	 * fec0 mii_bus.
2417 	 */
2418 	if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
2419 		/* fec1 uses fec0 mii_bus */
2420 		if (mii_cnt && fec0_mii_bus) {
2421 			fep->mii_bus = fec0_mii_bus;
2422 			mii_cnt++;
2423 			return 0;
2424 		}
2425 		return -ENOENT;
2426 	}
2427 
2428 	bus_freq = 2500000; /* 2.5MHz by default */
2429 	node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2430 	if (node) {
2431 		of_property_read_u32(node, "clock-frequency", &bus_freq);
2432 		suppress_preamble = of_property_read_bool(node,
2433 							  "suppress-preamble");
2434 	}
2435 
2436 	/*
2437 	 * Set MII speed (= clk_get_rate() / 2 * phy_speed)
2438 	 *
2439 	 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2440 	 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'.  The i.MX28
2441 	 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2442 	 * document.
2443 	 */
2444 	mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2);
2445 	if (fep->quirks & FEC_QUIRK_ENET_MAC)
2446 		mii_speed--;
2447 	if (mii_speed > 63) {
2448 		dev_err(&pdev->dev,
2449 			"fec clock (%lu) too fast to get right mii speed\n",
2450 			clk_get_rate(fep->clk_ipg));
2451 		err = -EINVAL;
2452 		goto err_out;
2453 	}
2454 
2455 	/*
2456 	 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2457 	 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2458 	 * versions are RAZ there, so just ignore the difference and write the
2459 	 * register always.
2460 	 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2461 	 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2462 	 * output.
2463 	 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2464 	 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2465 	 * holdtime cannot result in a value greater than 3.
2466 	 */
2467 	holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2468 
2469 	fep->phy_speed = mii_speed << 1 | holdtime << 8;
2470 
2471 	if (suppress_preamble)
2472 		fep->phy_speed |= BIT(7);
2473 
2474 	if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) {
2475 		/* Clear MMFR to avoid to generate MII event by writing MSCR.
2476 		 * MII event generation condition:
2477 		 * - writing MSCR:
2478 		 *	- mmfr[31:0]_not_zero & mscr[7:0]_is_zero &
2479 		 *	  mscr_reg_data_in[7:0] != 0
2480 		 * - writing MMFR:
2481 		 *	- mscr[7:0]_not_zero
2482 		 */
2483 		writel(0, fep->hwp + FEC_MII_DATA);
2484 	}
2485 
2486 	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2487 
2488 	/* Clear any pending transaction complete indication */
2489 	writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
2490 
2491 	fep->mii_bus = mdiobus_alloc();
2492 	if (fep->mii_bus == NULL) {
2493 		err = -ENOMEM;
2494 		goto err_out;
2495 	}
2496 
2497 	fep->mii_bus->name = "fec_enet_mii_bus";
2498 	fep->mii_bus->read = fec_enet_mdio_read_c22;
2499 	fep->mii_bus->write = fec_enet_mdio_write_c22;
2500 	if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) {
2501 		fep->mii_bus->read_c45 = fec_enet_mdio_read_c45;
2502 		fep->mii_bus->write_c45 = fec_enet_mdio_write_c45;
2503 	}
2504 	snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2505 		pdev->name, fep->dev_id + 1);
2506 	fep->mii_bus->priv = fep;
2507 	fep->mii_bus->parent = &pdev->dev;
2508 
2509 	err = of_mdiobus_register(fep->mii_bus, node);
2510 	if (err)
2511 		goto err_out_free_mdiobus;
2512 	of_node_put(node);
2513 
2514 	/* find all the PHY devices on the bus and set mac_managed_pm to true */
2515 	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
2516 		phydev = mdiobus_get_phy(fep->mii_bus, addr);
2517 		if (phydev)
2518 			phydev->mac_managed_pm = true;
2519 	}
2520 
2521 	mii_cnt++;
2522 
2523 	/* save fec0 mii_bus */
2524 	if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2525 		fec0_mii_bus = fep->mii_bus;
2526 
2527 	return 0;
2528 
2529 err_out_free_mdiobus:
2530 	mdiobus_free(fep->mii_bus);
2531 err_out:
2532 	of_node_put(node);
2533 	return err;
2534 }
2535 
2536 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2537 {
2538 	if (--mii_cnt == 0) {
2539 		mdiobus_unregister(fep->mii_bus);
2540 		mdiobus_free(fep->mii_bus);
2541 	}
2542 }
2543 
2544 static void fec_enet_get_drvinfo(struct net_device *ndev,
2545 				 struct ethtool_drvinfo *info)
2546 {
2547 	struct fec_enet_private *fep = netdev_priv(ndev);
2548 
2549 	strscpy(info->driver, fep->pdev->dev.driver->name,
2550 		sizeof(info->driver));
2551 	strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2552 }
2553 
2554 static int fec_enet_get_regs_len(struct net_device *ndev)
2555 {
2556 	struct fec_enet_private *fep = netdev_priv(ndev);
2557 	struct resource *r;
2558 	int s = 0;
2559 
2560 	r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2561 	if (r)
2562 		s = resource_size(r);
2563 
2564 	return s;
2565 }
2566 
2567 /* List of registers that can be safety be read to dump them with ethtool */
2568 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2569 	defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2570 	defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2571 static __u32 fec_enet_register_version = 2;
2572 static u32 fec_enet_register_offset[] = {
2573 	FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2574 	FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2575 	FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2576 	FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2577 	FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2578 	FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2579 	FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2580 	FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2581 	FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2582 	FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2583 	FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2584 	FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2585 	RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2586 	RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2587 	RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2588 	RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2589 	RMON_T_P_GTE2048, RMON_T_OCTETS,
2590 	IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2591 	IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2592 	IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2593 	RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2594 	RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2595 	RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2596 	RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2597 	RMON_R_P_GTE2048, RMON_R_OCTETS,
2598 	IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2599 	IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2600 };
2601 /* for i.MX6ul */
2602 static u32 fec_enet_register_offset_6ul[] = {
2603 	FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2604 	FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2605 	FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0,
2606 	FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH,
2607 	FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0,
2608 	FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2609 	FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC,
2610 	RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2611 	RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2612 	RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2613 	RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2614 	RMON_T_P_GTE2048, RMON_T_OCTETS,
2615 	IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2616 	IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2617 	IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2618 	RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2619 	RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2620 	RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2621 	RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2622 	RMON_R_P_GTE2048, RMON_R_OCTETS,
2623 	IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2624 	IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2625 };
2626 #else
2627 static __u32 fec_enet_register_version = 1;
2628 static u32 fec_enet_register_offset[] = {
2629 	FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2630 	FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2631 	FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2632 	FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2633 	FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2634 	FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2635 	FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2636 	FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2637 	FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2638 };
2639 #endif
2640 
2641 static void fec_enet_get_regs(struct net_device *ndev,
2642 			      struct ethtool_regs *regs, void *regbuf)
2643 {
2644 	struct fec_enet_private *fep = netdev_priv(ndev);
2645 	u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2646 	struct device *dev = &fep->pdev->dev;
2647 	u32 *buf = (u32 *)regbuf;
2648 	u32 i, off;
2649 	int ret;
2650 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2651 	defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2652 	defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2653 	u32 *reg_list;
2654 	u32 reg_cnt;
2655 
2656 	if (!of_machine_is_compatible("fsl,imx6ul")) {
2657 		reg_list = fec_enet_register_offset;
2658 		reg_cnt = ARRAY_SIZE(fec_enet_register_offset);
2659 	} else {
2660 		reg_list = fec_enet_register_offset_6ul;
2661 		reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul);
2662 	}
2663 #else
2664 	/* coldfire */
2665 	static u32 *reg_list = fec_enet_register_offset;
2666 	static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset);
2667 #endif
2668 	ret = pm_runtime_resume_and_get(dev);
2669 	if (ret < 0)
2670 		return;
2671 
2672 	regs->version = fec_enet_register_version;
2673 
2674 	memset(buf, 0, regs->len);
2675 
2676 	for (i = 0; i < reg_cnt; i++) {
2677 		off = reg_list[i];
2678 
2679 		if ((off == FEC_R_BOUND || off == FEC_R_FSTART) &&
2680 		    !(fep->quirks & FEC_QUIRK_HAS_FRREG))
2681 			continue;
2682 
2683 		off >>= 2;
2684 		buf[off] = readl(&theregs[off]);
2685 	}
2686 
2687 	pm_runtime_mark_last_busy(dev);
2688 	pm_runtime_put_autosuspend(dev);
2689 }
2690 
2691 static int fec_enet_get_ts_info(struct net_device *ndev,
2692 				struct ethtool_ts_info *info)
2693 {
2694 	struct fec_enet_private *fep = netdev_priv(ndev);
2695 
2696 	if (fep->bufdesc_ex) {
2697 
2698 		info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2699 					SOF_TIMESTAMPING_RX_SOFTWARE |
2700 					SOF_TIMESTAMPING_SOFTWARE |
2701 					SOF_TIMESTAMPING_TX_HARDWARE |
2702 					SOF_TIMESTAMPING_RX_HARDWARE |
2703 					SOF_TIMESTAMPING_RAW_HARDWARE;
2704 		if (fep->ptp_clock)
2705 			info->phc_index = ptp_clock_index(fep->ptp_clock);
2706 		else
2707 			info->phc_index = -1;
2708 
2709 		info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2710 				 (1 << HWTSTAMP_TX_ON);
2711 
2712 		info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2713 				   (1 << HWTSTAMP_FILTER_ALL);
2714 		return 0;
2715 	} else {
2716 		return ethtool_op_get_ts_info(ndev, info);
2717 	}
2718 }
2719 
2720 #if !defined(CONFIG_M5272)
2721 
2722 static void fec_enet_get_pauseparam(struct net_device *ndev,
2723 				    struct ethtool_pauseparam *pause)
2724 {
2725 	struct fec_enet_private *fep = netdev_priv(ndev);
2726 
2727 	pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2728 	pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2729 	pause->rx_pause = pause->tx_pause;
2730 }
2731 
2732 static int fec_enet_set_pauseparam(struct net_device *ndev,
2733 				   struct ethtool_pauseparam *pause)
2734 {
2735 	struct fec_enet_private *fep = netdev_priv(ndev);
2736 
2737 	if (!ndev->phydev)
2738 		return -ENODEV;
2739 
2740 	if (pause->tx_pause != pause->rx_pause) {
2741 		netdev_info(ndev,
2742 			"hardware only support enable/disable both tx and rx");
2743 		return -EINVAL;
2744 	}
2745 
2746 	fep->pause_flag = 0;
2747 
2748 	/* tx pause must be same as rx pause */
2749 	fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2750 	fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2751 
2752 	phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause,
2753 			  pause->autoneg);
2754 
2755 	if (pause->autoneg) {
2756 		if (netif_running(ndev))
2757 			fec_stop(ndev);
2758 		phy_start_aneg(ndev->phydev);
2759 	}
2760 	if (netif_running(ndev)) {
2761 		napi_disable(&fep->napi);
2762 		netif_tx_lock_bh(ndev);
2763 		fec_restart(ndev);
2764 		netif_tx_wake_all_queues(ndev);
2765 		netif_tx_unlock_bh(ndev);
2766 		napi_enable(&fep->napi);
2767 	}
2768 
2769 	return 0;
2770 }
2771 
2772 static const struct fec_stat {
2773 	char name[ETH_GSTRING_LEN];
2774 	u16 offset;
2775 } fec_stats[] = {
2776 	/* RMON TX */
2777 	{ "tx_dropped", RMON_T_DROP },
2778 	{ "tx_packets", RMON_T_PACKETS },
2779 	{ "tx_broadcast", RMON_T_BC_PKT },
2780 	{ "tx_multicast", RMON_T_MC_PKT },
2781 	{ "tx_crc_errors", RMON_T_CRC_ALIGN },
2782 	{ "tx_undersize", RMON_T_UNDERSIZE },
2783 	{ "tx_oversize", RMON_T_OVERSIZE },
2784 	{ "tx_fragment", RMON_T_FRAG },
2785 	{ "tx_jabber", RMON_T_JAB },
2786 	{ "tx_collision", RMON_T_COL },
2787 	{ "tx_64byte", RMON_T_P64 },
2788 	{ "tx_65to127byte", RMON_T_P65TO127 },
2789 	{ "tx_128to255byte", RMON_T_P128TO255 },
2790 	{ "tx_256to511byte", RMON_T_P256TO511 },
2791 	{ "tx_512to1023byte", RMON_T_P512TO1023 },
2792 	{ "tx_1024to2047byte", RMON_T_P1024TO2047 },
2793 	{ "tx_GTE2048byte", RMON_T_P_GTE2048 },
2794 	{ "tx_octets", RMON_T_OCTETS },
2795 
2796 	/* IEEE TX */
2797 	{ "IEEE_tx_drop", IEEE_T_DROP },
2798 	{ "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2799 	{ "IEEE_tx_1col", IEEE_T_1COL },
2800 	{ "IEEE_tx_mcol", IEEE_T_MCOL },
2801 	{ "IEEE_tx_def", IEEE_T_DEF },
2802 	{ "IEEE_tx_lcol", IEEE_T_LCOL },
2803 	{ "IEEE_tx_excol", IEEE_T_EXCOL },
2804 	{ "IEEE_tx_macerr", IEEE_T_MACERR },
2805 	{ "IEEE_tx_cserr", IEEE_T_CSERR },
2806 	{ "IEEE_tx_sqe", IEEE_T_SQE },
2807 	{ "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2808 	{ "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2809 
2810 	/* RMON RX */
2811 	{ "rx_packets", RMON_R_PACKETS },
2812 	{ "rx_broadcast", RMON_R_BC_PKT },
2813 	{ "rx_multicast", RMON_R_MC_PKT },
2814 	{ "rx_crc_errors", RMON_R_CRC_ALIGN },
2815 	{ "rx_undersize", RMON_R_UNDERSIZE },
2816 	{ "rx_oversize", RMON_R_OVERSIZE },
2817 	{ "rx_fragment", RMON_R_FRAG },
2818 	{ "rx_jabber", RMON_R_JAB },
2819 	{ "rx_64byte", RMON_R_P64 },
2820 	{ "rx_65to127byte", RMON_R_P65TO127 },
2821 	{ "rx_128to255byte", RMON_R_P128TO255 },
2822 	{ "rx_256to511byte", RMON_R_P256TO511 },
2823 	{ "rx_512to1023byte", RMON_R_P512TO1023 },
2824 	{ "rx_1024to2047byte", RMON_R_P1024TO2047 },
2825 	{ "rx_GTE2048byte", RMON_R_P_GTE2048 },
2826 	{ "rx_octets", RMON_R_OCTETS },
2827 
2828 	/* IEEE RX */
2829 	{ "IEEE_rx_drop", IEEE_R_DROP },
2830 	{ "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2831 	{ "IEEE_rx_crc", IEEE_R_CRC },
2832 	{ "IEEE_rx_align", IEEE_R_ALIGN },
2833 	{ "IEEE_rx_macerr", IEEE_R_MACERR },
2834 	{ "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2835 	{ "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2836 };
2837 
2838 #define FEC_STATS_SIZE		(ARRAY_SIZE(fec_stats) * sizeof(u64))
2839 
2840 static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = {
2841 	"rx_xdp_redirect",           /* RX_XDP_REDIRECT = 0, */
2842 	"rx_xdp_pass",               /* RX_XDP_PASS, */
2843 	"rx_xdp_drop",               /* RX_XDP_DROP, */
2844 	"rx_xdp_tx",                 /* RX_XDP_TX, */
2845 	"rx_xdp_tx_errors",          /* RX_XDP_TX_ERRORS, */
2846 	"tx_xdp_xmit",               /* TX_XDP_XMIT, */
2847 	"tx_xdp_xmit_errors",        /* TX_XDP_XMIT_ERRORS, */
2848 };
2849 
2850 static void fec_enet_update_ethtool_stats(struct net_device *dev)
2851 {
2852 	struct fec_enet_private *fep = netdev_priv(dev);
2853 	int i;
2854 
2855 	for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2856 		fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2857 }
2858 
2859 static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data)
2860 {
2861 	u64 xdp_stats[XDP_STATS_TOTAL] = { 0 };
2862 	struct fec_enet_priv_rx_q *rxq;
2863 	int i, j;
2864 
2865 	for (i = fep->num_rx_queues - 1; i >= 0; i--) {
2866 		rxq = fep->rx_queue[i];
2867 
2868 		for (j = 0; j < XDP_STATS_TOTAL; j++)
2869 			xdp_stats[j] += rxq->stats[j];
2870 	}
2871 
2872 	memcpy(data, xdp_stats, sizeof(xdp_stats));
2873 }
2874 
2875 static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data)
2876 {
2877 #ifdef CONFIG_PAGE_POOL_STATS
2878 	struct page_pool_stats stats = {};
2879 	struct fec_enet_priv_rx_q *rxq;
2880 	int i;
2881 
2882 	for (i = fep->num_rx_queues - 1; i >= 0; i--) {
2883 		rxq = fep->rx_queue[i];
2884 
2885 		if (!rxq->page_pool)
2886 			continue;
2887 
2888 		page_pool_get_stats(rxq->page_pool, &stats);
2889 	}
2890 
2891 	page_pool_ethtool_stats_get(data, &stats);
2892 #endif
2893 }
2894 
2895 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2896 				       struct ethtool_stats *stats, u64 *data)
2897 {
2898 	struct fec_enet_private *fep = netdev_priv(dev);
2899 
2900 	if (netif_running(dev))
2901 		fec_enet_update_ethtool_stats(dev);
2902 
2903 	memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2904 	data += FEC_STATS_SIZE / sizeof(u64);
2905 
2906 	fec_enet_get_xdp_stats(fep, data);
2907 	data += XDP_STATS_TOTAL;
2908 
2909 	fec_enet_page_pool_stats(fep, data);
2910 }
2911 
2912 static void fec_enet_get_strings(struct net_device *netdev,
2913 	u32 stringset, u8 *data)
2914 {
2915 	int i;
2916 	switch (stringset) {
2917 	case ETH_SS_STATS:
2918 		for (i = 0; i < ARRAY_SIZE(fec_stats); i++) {
2919 			memcpy(data, fec_stats[i].name, ETH_GSTRING_LEN);
2920 			data += ETH_GSTRING_LEN;
2921 		}
2922 		for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) {
2923 			strncpy(data, fec_xdp_stat_strs[i], ETH_GSTRING_LEN);
2924 			data += ETH_GSTRING_LEN;
2925 		}
2926 		page_pool_ethtool_stats_get_strings(data);
2927 
2928 		break;
2929 	case ETH_SS_TEST:
2930 		net_selftest_get_strings(data);
2931 		break;
2932 	}
2933 }
2934 
2935 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2936 {
2937 	int count;
2938 
2939 	switch (sset) {
2940 	case ETH_SS_STATS:
2941 		count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL;
2942 		count += page_pool_ethtool_stats_get_count();
2943 		return count;
2944 
2945 	case ETH_SS_TEST:
2946 		return net_selftest_get_count();
2947 	default:
2948 		return -EOPNOTSUPP;
2949 	}
2950 }
2951 
2952 static void fec_enet_clear_ethtool_stats(struct net_device *dev)
2953 {
2954 	struct fec_enet_private *fep = netdev_priv(dev);
2955 	struct fec_enet_priv_rx_q *rxq;
2956 	int i, j;
2957 
2958 	/* Disable MIB statistics counters */
2959 	writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
2960 
2961 	for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2962 		writel(0, fep->hwp + fec_stats[i].offset);
2963 
2964 	for (i = fep->num_rx_queues - 1; i >= 0; i--) {
2965 		rxq = fep->rx_queue[i];
2966 		for (j = 0; j < XDP_STATS_TOTAL; j++)
2967 			rxq->stats[j] = 0;
2968 	}
2969 
2970 	/* Don't disable MIB statistics counters */
2971 	writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
2972 }
2973 
2974 #else	/* !defined(CONFIG_M5272) */
2975 #define FEC_STATS_SIZE	0
2976 static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2977 {
2978 }
2979 
2980 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
2981 {
2982 }
2983 #endif /* !defined(CONFIG_M5272) */
2984 
2985 /* ITR clock source is enet system clock (clk_ahb).
2986  * TCTT unit is cycle_ns * 64 cycle
2987  * So, the ICTT value = X us / (cycle_ns * 64)
2988  */
2989 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2990 {
2991 	struct fec_enet_private *fep = netdev_priv(ndev);
2992 
2993 	return us * (fep->itr_clk_rate / 64000) / 1000;
2994 }
2995 
2996 /* Set threshold for interrupt coalescing */
2997 static void fec_enet_itr_coal_set(struct net_device *ndev)
2998 {
2999 	struct fec_enet_private *fep = netdev_priv(ndev);
3000 	int rx_itr, tx_itr;
3001 
3002 	/* Must be greater than zero to avoid unpredictable behavior */
3003 	if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
3004 	    !fep->tx_time_itr || !fep->tx_pkts_itr)
3005 		return;
3006 
3007 	/* Select enet system clock as Interrupt Coalescing
3008 	 * timer Clock Source
3009 	 */
3010 	rx_itr = FEC_ITR_CLK_SEL;
3011 	tx_itr = FEC_ITR_CLK_SEL;
3012 
3013 	/* set ICFT and ICTT */
3014 	rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
3015 	rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
3016 	tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
3017 	tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
3018 
3019 	rx_itr |= FEC_ITR_EN;
3020 	tx_itr |= FEC_ITR_EN;
3021 
3022 	writel(tx_itr, fep->hwp + FEC_TXIC0);
3023 	writel(rx_itr, fep->hwp + FEC_RXIC0);
3024 	if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
3025 		writel(tx_itr, fep->hwp + FEC_TXIC1);
3026 		writel(rx_itr, fep->hwp + FEC_RXIC1);
3027 		writel(tx_itr, fep->hwp + FEC_TXIC2);
3028 		writel(rx_itr, fep->hwp + FEC_RXIC2);
3029 	}
3030 }
3031 
3032 static int fec_enet_get_coalesce(struct net_device *ndev,
3033 				 struct ethtool_coalesce *ec,
3034 				 struct kernel_ethtool_coalesce *kernel_coal,
3035 				 struct netlink_ext_ack *extack)
3036 {
3037 	struct fec_enet_private *fep = netdev_priv(ndev);
3038 
3039 	if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
3040 		return -EOPNOTSUPP;
3041 
3042 	ec->rx_coalesce_usecs = fep->rx_time_itr;
3043 	ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
3044 
3045 	ec->tx_coalesce_usecs = fep->tx_time_itr;
3046 	ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
3047 
3048 	return 0;
3049 }
3050 
3051 static int fec_enet_set_coalesce(struct net_device *ndev,
3052 				 struct ethtool_coalesce *ec,
3053 				 struct kernel_ethtool_coalesce *kernel_coal,
3054 				 struct netlink_ext_ack *extack)
3055 {
3056 	struct fec_enet_private *fep = netdev_priv(ndev);
3057 	struct device *dev = &fep->pdev->dev;
3058 	unsigned int cycle;
3059 
3060 	if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
3061 		return -EOPNOTSUPP;
3062 
3063 	if (ec->rx_max_coalesced_frames > 255) {
3064 		dev_err(dev, "Rx coalesced frames exceed hardware limitation\n");
3065 		return -EINVAL;
3066 	}
3067 
3068 	if (ec->tx_max_coalesced_frames > 255) {
3069 		dev_err(dev, "Tx coalesced frame exceed hardware limitation\n");
3070 		return -EINVAL;
3071 	}
3072 
3073 	cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs);
3074 	if (cycle > 0xFFFF) {
3075 		dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");
3076 		return -EINVAL;
3077 	}
3078 
3079 	cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs);
3080 	if (cycle > 0xFFFF) {
3081 		dev_err(dev, "Tx coalesced usec exceed hardware limitation\n");
3082 		return -EINVAL;
3083 	}
3084 
3085 	fep->rx_time_itr = ec->rx_coalesce_usecs;
3086 	fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
3087 
3088 	fep->tx_time_itr = ec->tx_coalesce_usecs;
3089 	fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
3090 
3091 	fec_enet_itr_coal_set(ndev);
3092 
3093 	return 0;
3094 }
3095 
3096 /* LPI Sleep Ts count base on tx clk (clk_ref).
3097  * The lpi sleep cnt value = X us / (cycle_ns).
3098  */
3099 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us)
3100 {
3101 	struct fec_enet_private *fep = netdev_priv(ndev);
3102 
3103 	return us * (fep->clk_ref_rate / 1000) / 1000;
3104 }
3105 
3106 static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable)
3107 {
3108 	struct fec_enet_private *fep = netdev_priv(ndev);
3109 	struct ethtool_eee *p = &fep->eee;
3110 	unsigned int sleep_cycle, wake_cycle;
3111 	int ret = 0;
3112 
3113 	if (enable) {
3114 		ret = phy_init_eee(ndev->phydev, false);
3115 		if (ret)
3116 			return ret;
3117 
3118 		sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer);
3119 		wake_cycle = sleep_cycle;
3120 	} else {
3121 		sleep_cycle = 0;
3122 		wake_cycle = 0;
3123 	}
3124 
3125 	p->tx_lpi_enabled = enable;
3126 	p->eee_enabled = enable;
3127 	p->eee_active = enable;
3128 
3129 	writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP);
3130 	writel(wake_cycle, fep->hwp + FEC_LPI_WAKE);
3131 
3132 	return 0;
3133 }
3134 
3135 static int
3136 fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
3137 {
3138 	struct fec_enet_private *fep = netdev_priv(ndev);
3139 	struct ethtool_eee *p = &fep->eee;
3140 
3141 	if (!(fep->quirks & FEC_QUIRK_HAS_EEE))
3142 		return -EOPNOTSUPP;
3143 
3144 	if (!netif_running(ndev))
3145 		return -ENETDOWN;
3146 
3147 	edata->eee_enabled = p->eee_enabled;
3148 	edata->eee_active = p->eee_active;
3149 	edata->tx_lpi_timer = p->tx_lpi_timer;
3150 	edata->tx_lpi_enabled = p->tx_lpi_enabled;
3151 
3152 	return phy_ethtool_get_eee(ndev->phydev, edata);
3153 }
3154 
3155 static int
3156 fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
3157 {
3158 	struct fec_enet_private *fep = netdev_priv(ndev);
3159 	struct ethtool_eee *p = &fep->eee;
3160 	int ret = 0;
3161 
3162 	if (!(fep->quirks & FEC_QUIRK_HAS_EEE))
3163 		return -EOPNOTSUPP;
3164 
3165 	if (!netif_running(ndev))
3166 		return -ENETDOWN;
3167 
3168 	p->tx_lpi_timer = edata->tx_lpi_timer;
3169 
3170 	if (!edata->eee_enabled || !edata->tx_lpi_enabled ||
3171 	    !edata->tx_lpi_timer)
3172 		ret = fec_enet_eee_mode_set(ndev, false);
3173 	else
3174 		ret = fec_enet_eee_mode_set(ndev, true);
3175 
3176 	if (ret)
3177 		return ret;
3178 
3179 	return phy_ethtool_set_eee(ndev->phydev, edata);
3180 }
3181 
3182 static void
3183 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
3184 {
3185 	struct fec_enet_private *fep = netdev_priv(ndev);
3186 
3187 	if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
3188 		wol->supported = WAKE_MAGIC;
3189 		wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
3190 	} else {
3191 		wol->supported = wol->wolopts = 0;
3192 	}
3193 }
3194 
3195 static int
3196 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
3197 {
3198 	struct fec_enet_private *fep = netdev_priv(ndev);
3199 
3200 	if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
3201 		return -EINVAL;
3202 
3203 	if (wol->wolopts & ~WAKE_MAGIC)
3204 		return -EINVAL;
3205 
3206 	device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
3207 	if (device_may_wakeup(&ndev->dev))
3208 		fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
3209 	else
3210 		fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
3211 
3212 	return 0;
3213 }
3214 
3215 static const struct ethtool_ops fec_enet_ethtool_ops = {
3216 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |
3217 				     ETHTOOL_COALESCE_MAX_FRAMES,
3218 	.get_drvinfo		= fec_enet_get_drvinfo,
3219 	.get_regs_len		= fec_enet_get_regs_len,
3220 	.get_regs		= fec_enet_get_regs,
3221 	.nway_reset		= phy_ethtool_nway_reset,
3222 	.get_link		= ethtool_op_get_link,
3223 	.get_coalesce		= fec_enet_get_coalesce,
3224 	.set_coalesce		= fec_enet_set_coalesce,
3225 #ifndef CONFIG_M5272
3226 	.get_pauseparam		= fec_enet_get_pauseparam,
3227 	.set_pauseparam		= fec_enet_set_pauseparam,
3228 	.get_strings		= fec_enet_get_strings,
3229 	.get_ethtool_stats	= fec_enet_get_ethtool_stats,
3230 	.get_sset_count		= fec_enet_get_sset_count,
3231 #endif
3232 	.get_ts_info		= fec_enet_get_ts_info,
3233 	.get_wol		= fec_enet_get_wol,
3234 	.set_wol		= fec_enet_set_wol,
3235 	.get_eee		= fec_enet_get_eee,
3236 	.set_eee		= fec_enet_set_eee,
3237 	.get_link_ksettings	= phy_ethtool_get_link_ksettings,
3238 	.set_link_ksettings	= phy_ethtool_set_link_ksettings,
3239 	.self_test		= net_selftest,
3240 };
3241 
3242 static void fec_enet_free_buffers(struct net_device *ndev)
3243 {
3244 	struct fec_enet_private *fep = netdev_priv(ndev);
3245 	unsigned int i;
3246 	struct fec_enet_priv_tx_q *txq;
3247 	struct fec_enet_priv_rx_q *rxq;
3248 	unsigned int q;
3249 
3250 	for (q = 0; q < fep->num_rx_queues; q++) {
3251 		rxq = fep->rx_queue[q];
3252 		for (i = 0; i < rxq->bd.ring_size; i++)
3253 			page_pool_put_full_page(rxq->page_pool, rxq->rx_skb_info[i].page, false);
3254 
3255 		for (i = 0; i < XDP_STATS_TOTAL; i++)
3256 			rxq->stats[i] = 0;
3257 
3258 		if (xdp_rxq_info_is_reg(&rxq->xdp_rxq))
3259 			xdp_rxq_info_unreg(&rxq->xdp_rxq);
3260 		page_pool_destroy(rxq->page_pool);
3261 		rxq->page_pool = NULL;
3262 	}
3263 
3264 	for (q = 0; q < fep->num_tx_queues; q++) {
3265 		txq = fep->tx_queue[q];
3266 		for (i = 0; i < txq->bd.ring_size; i++) {
3267 			kfree(txq->tx_bounce[i]);
3268 			txq->tx_bounce[i] = NULL;
3269 
3270 			if (!txq->tx_buf[i].buf_p) {
3271 				txq->tx_buf[i].type = FEC_TXBUF_T_SKB;
3272 				continue;
3273 			}
3274 
3275 			if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) {
3276 				dev_kfree_skb(txq->tx_buf[i].buf_p);
3277 			} else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) {
3278 				xdp_return_frame(txq->tx_buf[i].buf_p);
3279 			} else {
3280 				struct page *page = txq->tx_buf[i].buf_p;
3281 
3282 				page_pool_put_page(page->pp, page, 0, false);
3283 			}
3284 
3285 			txq->tx_buf[i].buf_p = NULL;
3286 			txq->tx_buf[i].type = FEC_TXBUF_T_SKB;
3287 		}
3288 	}
3289 }
3290 
3291 static void fec_enet_free_queue(struct net_device *ndev)
3292 {
3293 	struct fec_enet_private *fep = netdev_priv(ndev);
3294 	int i;
3295 	struct fec_enet_priv_tx_q *txq;
3296 
3297 	for (i = 0; i < fep->num_tx_queues; i++)
3298 		if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
3299 			txq = fep->tx_queue[i];
3300 			dma_free_coherent(&fep->pdev->dev,
3301 					  txq->bd.ring_size * TSO_HEADER_SIZE,
3302 					  txq->tso_hdrs,
3303 					  txq->tso_hdrs_dma);
3304 		}
3305 
3306 	for (i = 0; i < fep->num_rx_queues; i++)
3307 		kfree(fep->rx_queue[i]);
3308 	for (i = 0; i < fep->num_tx_queues; i++)
3309 		kfree(fep->tx_queue[i]);
3310 }
3311 
3312 static int fec_enet_alloc_queue(struct net_device *ndev)
3313 {
3314 	struct fec_enet_private *fep = netdev_priv(ndev);
3315 	int i;
3316 	int ret = 0;
3317 	struct fec_enet_priv_tx_q *txq;
3318 
3319 	for (i = 0; i < fep->num_tx_queues; i++) {
3320 		txq = kzalloc(sizeof(*txq), GFP_KERNEL);
3321 		if (!txq) {
3322 			ret = -ENOMEM;
3323 			goto alloc_failed;
3324 		}
3325 
3326 		fep->tx_queue[i] = txq;
3327 		txq->bd.ring_size = TX_RING_SIZE;
3328 		fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
3329 
3330 		txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
3331 		txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS;
3332 
3333 		txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev,
3334 					txq->bd.ring_size * TSO_HEADER_SIZE,
3335 					&txq->tso_hdrs_dma,
3336 					GFP_KERNEL);
3337 		if (!txq->tso_hdrs) {
3338 			ret = -ENOMEM;
3339 			goto alloc_failed;
3340 		}
3341 	}
3342 
3343 	for (i = 0; i < fep->num_rx_queues; i++) {
3344 		fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
3345 					   GFP_KERNEL);
3346 		if (!fep->rx_queue[i]) {
3347 			ret = -ENOMEM;
3348 			goto alloc_failed;
3349 		}
3350 
3351 		fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
3352 		fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
3353 	}
3354 	return ret;
3355 
3356 alloc_failed:
3357 	fec_enet_free_queue(ndev);
3358 	return ret;
3359 }
3360 
3361 static int
3362 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
3363 {
3364 	struct fec_enet_private *fep = netdev_priv(ndev);
3365 	struct fec_enet_priv_rx_q *rxq;
3366 	dma_addr_t phys_addr;
3367 	struct bufdesc	*bdp;
3368 	struct page *page;
3369 	int i, err;
3370 
3371 	rxq = fep->rx_queue[queue];
3372 	bdp = rxq->bd.base;
3373 
3374 	err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size);
3375 	if (err < 0) {
3376 		netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err);
3377 		return err;
3378 	}
3379 
3380 	for (i = 0; i < rxq->bd.ring_size; i++) {
3381 		page = page_pool_dev_alloc_pages(rxq->page_pool);
3382 		if (!page)
3383 			goto err_alloc;
3384 
3385 		phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM;
3386 		bdp->cbd_bufaddr = cpu_to_fec32(phys_addr);
3387 
3388 		rxq->rx_skb_info[i].page = page;
3389 		rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM;
3390 		bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
3391 
3392 		if (fep->bufdesc_ex) {
3393 			struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3394 			ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
3395 		}
3396 
3397 		bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
3398 	}
3399 
3400 	/* Set the last buffer to wrap. */
3401 	bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
3402 	bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
3403 	return 0;
3404 
3405  err_alloc:
3406 	fec_enet_free_buffers(ndev);
3407 	return -ENOMEM;
3408 }
3409 
3410 static int
3411 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
3412 {
3413 	struct fec_enet_private *fep = netdev_priv(ndev);
3414 	unsigned int i;
3415 	struct bufdesc  *bdp;
3416 	struct fec_enet_priv_tx_q *txq;
3417 
3418 	txq = fep->tx_queue[queue];
3419 	bdp = txq->bd.base;
3420 	for (i = 0; i < txq->bd.ring_size; i++) {
3421 		txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
3422 		if (!txq->tx_bounce[i])
3423 			goto err_alloc;
3424 
3425 		bdp->cbd_sc = cpu_to_fec16(0);
3426 		bdp->cbd_bufaddr = cpu_to_fec32(0);
3427 
3428 		if (fep->bufdesc_ex) {
3429 			struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3430 			ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
3431 		}
3432 
3433 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
3434 	}
3435 
3436 	/* Set the last buffer to wrap. */
3437 	bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
3438 	bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
3439 
3440 	return 0;
3441 
3442  err_alloc:
3443 	fec_enet_free_buffers(ndev);
3444 	return -ENOMEM;
3445 }
3446 
3447 static int fec_enet_alloc_buffers(struct net_device *ndev)
3448 {
3449 	struct fec_enet_private *fep = netdev_priv(ndev);
3450 	unsigned int i;
3451 
3452 	for (i = 0; i < fep->num_rx_queues; i++)
3453 		if (fec_enet_alloc_rxq_buffers(ndev, i))
3454 			return -ENOMEM;
3455 
3456 	for (i = 0; i < fep->num_tx_queues; i++)
3457 		if (fec_enet_alloc_txq_buffers(ndev, i))
3458 			return -ENOMEM;
3459 	return 0;
3460 }
3461 
3462 static int
3463 fec_enet_open(struct net_device *ndev)
3464 {
3465 	struct fec_enet_private *fep = netdev_priv(ndev);
3466 	int ret;
3467 	bool reset_again;
3468 
3469 	ret = pm_runtime_resume_and_get(&fep->pdev->dev);
3470 	if (ret < 0)
3471 		return ret;
3472 
3473 	pinctrl_pm_select_default_state(&fep->pdev->dev);
3474 	ret = fec_enet_clk_enable(ndev, true);
3475 	if (ret)
3476 		goto clk_enable;
3477 
3478 	/* During the first fec_enet_open call the PHY isn't probed at this
3479 	 * point. Therefore the phy_reset_after_clk_enable() call within
3480 	 * fec_enet_clk_enable() fails. As we need this reset in order to be
3481 	 * sure the PHY is working correctly we check if we need to reset again
3482 	 * later when the PHY is probed
3483 	 */
3484 	if (ndev->phydev && ndev->phydev->drv)
3485 		reset_again = false;
3486 	else
3487 		reset_again = true;
3488 
3489 	/* I should reset the ring buffers here, but I don't yet know
3490 	 * a simple way to do that.
3491 	 */
3492 
3493 	ret = fec_enet_alloc_buffers(ndev);
3494 	if (ret)
3495 		goto err_enet_alloc;
3496 
3497 	/* Init MAC prior to mii bus probe */
3498 	fec_restart(ndev);
3499 
3500 	/* Call phy_reset_after_clk_enable() again if it failed during
3501 	 * phy_reset_after_clk_enable() before because the PHY wasn't probed.
3502 	 */
3503 	if (reset_again)
3504 		fec_enet_phy_reset_after_clk_enable(ndev);
3505 
3506 	/* Probe and connect to PHY when open the interface */
3507 	ret = fec_enet_mii_probe(ndev);
3508 	if (ret)
3509 		goto err_enet_mii_probe;
3510 
3511 	if (fep->quirks & FEC_QUIRK_ERR006687)
3512 		imx6q_cpuidle_fec_irqs_used();
3513 
3514 	if (fep->quirks & FEC_QUIRK_HAS_PMQOS)
3515 		cpu_latency_qos_add_request(&fep->pm_qos_req, 0);
3516 
3517 	napi_enable(&fep->napi);
3518 	phy_start(ndev->phydev);
3519 	netif_tx_start_all_queues(ndev);
3520 
3521 	device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
3522 				 FEC_WOL_FLAG_ENABLE);
3523 
3524 	return 0;
3525 
3526 err_enet_mii_probe:
3527 	fec_enet_free_buffers(ndev);
3528 err_enet_alloc:
3529 	fec_enet_clk_enable(ndev, false);
3530 clk_enable:
3531 	pm_runtime_mark_last_busy(&fep->pdev->dev);
3532 	pm_runtime_put_autosuspend(&fep->pdev->dev);
3533 	pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3534 	return ret;
3535 }
3536 
3537 static int
3538 fec_enet_close(struct net_device *ndev)
3539 {
3540 	struct fec_enet_private *fep = netdev_priv(ndev);
3541 
3542 	phy_stop(ndev->phydev);
3543 
3544 	if (netif_device_present(ndev)) {
3545 		napi_disable(&fep->napi);
3546 		netif_tx_disable(ndev);
3547 		fec_stop(ndev);
3548 	}
3549 
3550 	phy_disconnect(ndev->phydev);
3551 
3552 	if (fep->quirks & FEC_QUIRK_ERR006687)
3553 		imx6q_cpuidle_fec_irqs_unused();
3554 
3555 	fec_enet_update_ethtool_stats(ndev);
3556 
3557 	fec_enet_clk_enable(ndev, false);
3558 	if (fep->quirks & FEC_QUIRK_HAS_PMQOS)
3559 		cpu_latency_qos_remove_request(&fep->pm_qos_req);
3560 
3561 	pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3562 	pm_runtime_mark_last_busy(&fep->pdev->dev);
3563 	pm_runtime_put_autosuspend(&fep->pdev->dev);
3564 
3565 	fec_enet_free_buffers(ndev);
3566 
3567 	return 0;
3568 }
3569 
3570 /* Set or clear the multicast filter for this adaptor.
3571  * Skeleton taken from sunlance driver.
3572  * The CPM Ethernet implementation allows Multicast as well as individual
3573  * MAC address filtering.  Some of the drivers check to make sure it is
3574  * a group multicast address, and discard those that are not.  I guess I
3575  * will do the same for now, but just remove the test if you want
3576  * individual filtering as well (do the upper net layers want or support
3577  * this kind of feature?).
3578  */
3579 
3580 #define FEC_HASH_BITS	6		/* #bits in hash */
3581 
3582 static void set_multicast_list(struct net_device *ndev)
3583 {
3584 	struct fec_enet_private *fep = netdev_priv(ndev);
3585 	struct netdev_hw_addr *ha;
3586 	unsigned int crc, tmp;
3587 	unsigned char hash;
3588 	unsigned int hash_high = 0, hash_low = 0;
3589 
3590 	if (ndev->flags & IFF_PROMISC) {
3591 		tmp = readl(fep->hwp + FEC_R_CNTRL);
3592 		tmp |= 0x8;
3593 		writel(tmp, fep->hwp + FEC_R_CNTRL);
3594 		return;
3595 	}
3596 
3597 	tmp = readl(fep->hwp + FEC_R_CNTRL);
3598 	tmp &= ~0x8;
3599 	writel(tmp, fep->hwp + FEC_R_CNTRL);
3600 
3601 	if (ndev->flags & IFF_ALLMULTI) {
3602 		/* Catch all multicast addresses, so set the
3603 		 * filter to all 1's
3604 		 */
3605 		writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3606 		writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3607 
3608 		return;
3609 	}
3610 
3611 	/* Add the addresses in hash register */
3612 	netdev_for_each_mc_addr(ha, ndev) {
3613 		/* calculate crc32 value of mac address */
3614 		crc = ether_crc_le(ndev->addr_len, ha->addr);
3615 
3616 		/* only upper 6 bits (FEC_HASH_BITS) are used
3617 		 * which point to specific bit in the hash registers
3618 		 */
3619 		hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
3620 
3621 		if (hash > 31)
3622 			hash_high |= 1 << (hash - 32);
3623 		else
3624 			hash_low |= 1 << hash;
3625 	}
3626 
3627 	writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3628 	writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3629 }
3630 
3631 /* Set a MAC change in hardware. */
3632 static int
3633 fec_set_mac_address(struct net_device *ndev, void *p)
3634 {
3635 	struct fec_enet_private *fep = netdev_priv(ndev);
3636 	struct sockaddr *addr = p;
3637 
3638 	if (addr) {
3639 		if (!is_valid_ether_addr(addr->sa_data))
3640 			return -EADDRNOTAVAIL;
3641 		eth_hw_addr_set(ndev, addr->sa_data);
3642 	}
3643 
3644 	/* Add netif status check here to avoid system hang in below case:
3645 	 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3646 	 * After ethx down, fec all clocks are gated off and then register
3647 	 * access causes system hang.
3648 	 */
3649 	if (!netif_running(ndev))
3650 		return 0;
3651 
3652 	writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3653 		(ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3654 		fep->hwp + FEC_ADDR_LOW);
3655 	writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3656 		fep->hwp + FEC_ADDR_HIGH);
3657 	return 0;
3658 }
3659 
3660 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3661 	netdev_features_t features)
3662 {
3663 	struct fec_enet_private *fep = netdev_priv(netdev);
3664 	netdev_features_t changed = features ^ netdev->features;
3665 
3666 	netdev->features = features;
3667 
3668 	/* Receive checksum has been changed */
3669 	if (changed & NETIF_F_RXCSUM) {
3670 		if (features & NETIF_F_RXCSUM)
3671 			fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3672 		else
3673 			fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3674 	}
3675 }
3676 
3677 static int fec_set_features(struct net_device *netdev,
3678 	netdev_features_t features)
3679 {
3680 	struct fec_enet_private *fep = netdev_priv(netdev);
3681 	netdev_features_t changed = features ^ netdev->features;
3682 
3683 	if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3684 		napi_disable(&fep->napi);
3685 		netif_tx_lock_bh(netdev);
3686 		fec_stop(netdev);
3687 		fec_enet_set_netdev_features(netdev, features);
3688 		fec_restart(netdev);
3689 		netif_tx_wake_all_queues(netdev);
3690 		netif_tx_unlock_bh(netdev);
3691 		napi_enable(&fep->napi);
3692 	} else {
3693 		fec_enet_set_netdev_features(netdev, features);
3694 	}
3695 
3696 	return 0;
3697 }
3698 
3699 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb,
3700 				 struct net_device *sb_dev)
3701 {
3702 	struct fec_enet_private *fep = netdev_priv(ndev);
3703 	u16 vlan_tag = 0;
3704 
3705 	if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
3706 		return netdev_pick_tx(ndev, skb, NULL);
3707 
3708 	/* VLAN is present in the payload.*/
3709 	if (eth_type_vlan(skb->protocol)) {
3710 		struct vlan_ethhdr *vhdr = skb_vlan_eth_hdr(skb);
3711 
3712 		vlan_tag = ntohs(vhdr->h_vlan_TCI);
3713 	/*  VLAN is present in the skb but not yet pushed in the payload.*/
3714 	} else if (skb_vlan_tag_present(skb)) {
3715 		vlan_tag = skb->vlan_tci;
3716 	} else {
3717 		return vlan_tag;
3718 	}
3719 
3720 	return fec_enet_vlan_pri_to_queue[vlan_tag >> 13];
3721 }
3722 
3723 static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf)
3724 {
3725 	struct fec_enet_private *fep = netdev_priv(dev);
3726 	bool is_run = netif_running(dev);
3727 	struct bpf_prog *old_prog;
3728 
3729 	switch (bpf->command) {
3730 	case XDP_SETUP_PROG:
3731 		/* No need to support the SoCs that require to
3732 		 * do the frame swap because the performance wouldn't be
3733 		 * better than the skb mode.
3734 		 */
3735 		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
3736 			return -EOPNOTSUPP;
3737 
3738 		if (!bpf->prog)
3739 			xdp_features_clear_redirect_target(dev);
3740 
3741 		if (is_run) {
3742 			napi_disable(&fep->napi);
3743 			netif_tx_disable(dev);
3744 		}
3745 
3746 		old_prog = xchg(&fep->xdp_prog, bpf->prog);
3747 		if (old_prog)
3748 			bpf_prog_put(old_prog);
3749 
3750 		fec_restart(dev);
3751 
3752 		if (is_run) {
3753 			napi_enable(&fep->napi);
3754 			netif_tx_start_all_queues(dev);
3755 		}
3756 
3757 		if (bpf->prog)
3758 			xdp_features_set_redirect_target(dev, false);
3759 
3760 		return 0;
3761 
3762 	case XDP_SETUP_XSK_POOL:
3763 		return -EOPNOTSUPP;
3764 
3765 	default:
3766 		return -EOPNOTSUPP;
3767 	}
3768 }
3769 
3770 static int
3771 fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index)
3772 {
3773 	if (unlikely(index < 0))
3774 		return 0;
3775 
3776 	return (index % fep->num_tx_queues);
3777 }
3778 
3779 static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep,
3780 				   struct fec_enet_priv_tx_q *txq,
3781 				   void *frame, u32 dma_sync_len,
3782 				   bool ndo_xmit)
3783 {
3784 	unsigned int index, status, estatus;
3785 	struct bufdesc *bdp;
3786 	dma_addr_t dma_addr;
3787 	int entries_free;
3788 	u16 frame_len;
3789 
3790 	entries_free = fec_enet_get_free_txdesc_num(txq);
3791 	if (entries_free < MAX_SKB_FRAGS + 1) {
3792 		netdev_err_once(fep->netdev, "NOT enough BD for SG!\n");
3793 		return -EBUSY;
3794 	}
3795 
3796 	/* Fill in a Tx ring entry */
3797 	bdp = txq->bd.cur;
3798 	status = fec16_to_cpu(bdp->cbd_sc);
3799 	status &= ~BD_ENET_TX_STATS;
3800 
3801 	index = fec_enet_get_bd_index(bdp, &txq->bd);
3802 
3803 	if (ndo_xmit) {
3804 		struct xdp_frame *xdpf = frame;
3805 
3806 		dma_addr = dma_map_single(&fep->pdev->dev, xdpf->data,
3807 					  xdpf->len, DMA_TO_DEVICE);
3808 		if (dma_mapping_error(&fep->pdev->dev, dma_addr))
3809 			return -ENOMEM;
3810 
3811 		frame_len = xdpf->len;
3812 		txq->tx_buf[index].buf_p = xdpf;
3813 		txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO;
3814 	} else {
3815 		struct xdp_buff *xdpb = frame;
3816 		struct page *page;
3817 
3818 		page = virt_to_page(xdpb->data);
3819 		dma_addr = page_pool_get_dma_addr(page) +
3820 			   (xdpb->data - xdpb->data_hard_start);
3821 		dma_sync_single_for_device(&fep->pdev->dev, dma_addr,
3822 					   dma_sync_len, DMA_BIDIRECTIONAL);
3823 		frame_len = xdpb->data_end - xdpb->data;
3824 		txq->tx_buf[index].buf_p = page;
3825 		txq->tx_buf[index].type = FEC_TXBUF_T_XDP_TX;
3826 	}
3827 
3828 	status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
3829 	if (fep->bufdesc_ex)
3830 		estatus = BD_ENET_TX_INT;
3831 
3832 	bdp->cbd_bufaddr = cpu_to_fec32(dma_addr);
3833 	bdp->cbd_datlen = cpu_to_fec16(frame_len);
3834 
3835 	if (fep->bufdesc_ex) {
3836 		struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3837 
3838 		if (fep->quirks & FEC_QUIRK_HAS_AVB)
3839 			estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
3840 
3841 		ebdp->cbd_bdu = 0;
3842 		ebdp->cbd_esc = cpu_to_fec32(estatus);
3843 	}
3844 
3845 	/* Make sure the updates to rest of the descriptor are performed before
3846 	 * transferring ownership.
3847 	 */
3848 	dma_wmb();
3849 
3850 	/* Send it on its way.  Tell FEC it's ready, interrupt when done,
3851 	 * it's the last BD of the frame, and to put the CRC on the end.
3852 	 */
3853 	status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
3854 	bdp->cbd_sc = cpu_to_fec16(status);
3855 
3856 	/* If this was the last BD in the ring, start at the beginning again. */
3857 	bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
3858 
3859 	/* Make sure the update to bdp are performed before txq->bd.cur. */
3860 	dma_wmb();
3861 
3862 	txq->bd.cur = bdp;
3863 
3864 	/* Trigger transmission start */
3865 	writel(0, txq->bd.reg_desc_active);
3866 
3867 	return 0;
3868 }
3869 
3870 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep,
3871 				int cpu, struct xdp_buff *xdp,
3872 				u32 dma_sync_len)
3873 {
3874 	struct fec_enet_priv_tx_q *txq;
3875 	struct netdev_queue *nq;
3876 	int queue, ret;
3877 
3878 	queue = fec_enet_xdp_get_tx_queue(fep, cpu);
3879 	txq = fep->tx_queue[queue];
3880 	nq = netdev_get_tx_queue(fep->netdev, queue);
3881 
3882 	__netif_tx_lock(nq, cpu);
3883 
3884 	/* Avoid tx timeout as XDP shares the queue with kernel stack */
3885 	txq_trans_cond_update(nq);
3886 	ret = fec_enet_txq_xmit_frame(fep, txq, xdp, dma_sync_len, false);
3887 
3888 	__netif_tx_unlock(nq);
3889 
3890 	return ret;
3891 }
3892 
3893 static int fec_enet_xdp_xmit(struct net_device *dev,
3894 			     int num_frames,
3895 			     struct xdp_frame **frames,
3896 			     u32 flags)
3897 {
3898 	struct fec_enet_private *fep = netdev_priv(dev);
3899 	struct fec_enet_priv_tx_q *txq;
3900 	int cpu = smp_processor_id();
3901 	unsigned int sent_frames = 0;
3902 	struct netdev_queue *nq;
3903 	unsigned int queue;
3904 	int i;
3905 
3906 	queue = fec_enet_xdp_get_tx_queue(fep, cpu);
3907 	txq = fep->tx_queue[queue];
3908 	nq = netdev_get_tx_queue(fep->netdev, queue);
3909 
3910 	__netif_tx_lock(nq, cpu);
3911 
3912 	/* Avoid tx timeout as XDP shares the queue with kernel stack */
3913 	txq_trans_cond_update(nq);
3914 	for (i = 0; i < num_frames; i++) {
3915 		if (fec_enet_txq_xmit_frame(fep, txq, frames[i], 0, true) < 0)
3916 			break;
3917 		sent_frames++;
3918 	}
3919 
3920 	__netif_tx_unlock(nq);
3921 
3922 	return sent_frames;
3923 }
3924 
3925 static int fec_hwtstamp_get(struct net_device *ndev,
3926 			    struct kernel_hwtstamp_config *config)
3927 {
3928 	struct fec_enet_private *fep = netdev_priv(ndev);
3929 
3930 	if (!netif_running(ndev))
3931 		return -EINVAL;
3932 
3933 	if (!fep->bufdesc_ex)
3934 		return -EOPNOTSUPP;
3935 
3936 	fec_ptp_get(ndev, config);
3937 
3938 	return 0;
3939 }
3940 
3941 static int fec_hwtstamp_set(struct net_device *ndev,
3942 			    struct kernel_hwtstamp_config *config,
3943 			    struct netlink_ext_ack *extack)
3944 {
3945 	struct fec_enet_private *fep = netdev_priv(ndev);
3946 
3947 	if (!netif_running(ndev))
3948 		return -EINVAL;
3949 
3950 	if (!fep->bufdesc_ex)
3951 		return -EOPNOTSUPP;
3952 
3953 	return fec_ptp_set(ndev, config, extack);
3954 }
3955 
3956 static const struct net_device_ops fec_netdev_ops = {
3957 	.ndo_open		= fec_enet_open,
3958 	.ndo_stop		= fec_enet_close,
3959 	.ndo_start_xmit		= fec_enet_start_xmit,
3960 	.ndo_select_queue       = fec_enet_select_queue,
3961 	.ndo_set_rx_mode	= set_multicast_list,
3962 	.ndo_validate_addr	= eth_validate_addr,
3963 	.ndo_tx_timeout		= fec_timeout,
3964 	.ndo_set_mac_address	= fec_set_mac_address,
3965 	.ndo_eth_ioctl		= phy_do_ioctl_running,
3966 	.ndo_set_features	= fec_set_features,
3967 	.ndo_bpf		= fec_enet_bpf,
3968 	.ndo_xdp_xmit		= fec_enet_xdp_xmit,
3969 	.ndo_hwtstamp_get	= fec_hwtstamp_get,
3970 	.ndo_hwtstamp_set	= fec_hwtstamp_set,
3971 };
3972 
3973 static const unsigned short offset_des_active_rxq[] = {
3974 	FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3975 };
3976 
3977 static const unsigned short offset_des_active_txq[] = {
3978 	FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3979 };
3980 
3981  /*
3982   * XXX:  We need to clean up on failure exits here.
3983   *
3984   */
3985 static int fec_enet_init(struct net_device *ndev)
3986 {
3987 	struct fec_enet_private *fep = netdev_priv(ndev);
3988 	struct bufdesc *cbd_base;
3989 	dma_addr_t bd_dma;
3990 	int bd_size;
3991 	unsigned int i;
3992 	unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3993 			sizeof(struct bufdesc);
3994 	unsigned dsize_log2 = __fls(dsize);
3995 	int ret;
3996 
3997 	WARN_ON(dsize != (1 << dsize_log2));
3998 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
3999 	fep->rx_align = 0xf;
4000 	fep->tx_align = 0xf;
4001 #else
4002 	fep->rx_align = 0x3;
4003 	fep->tx_align = 0x3;
4004 #endif
4005 	fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT;
4006 	fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT;
4007 	fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT;
4008 	fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT;
4009 
4010 	/* Check mask of the streaming and coherent API */
4011 	ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32));
4012 	if (ret < 0) {
4013 		dev_warn(&fep->pdev->dev, "No suitable DMA available\n");
4014 		return ret;
4015 	}
4016 
4017 	ret = fec_enet_alloc_queue(ndev);
4018 	if (ret)
4019 		return ret;
4020 
4021 	bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
4022 
4023 	/* Allocate memory for buffer descriptors. */
4024 	cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
4025 				       GFP_KERNEL);
4026 	if (!cbd_base) {
4027 		ret = -ENOMEM;
4028 		goto free_queue_mem;
4029 	}
4030 
4031 	/* Get the Ethernet address */
4032 	ret = fec_get_mac(ndev);
4033 	if (ret)
4034 		goto free_queue_mem;
4035 
4036 	/* Set receive and transmit descriptor base. */
4037 	for (i = 0; i < fep->num_rx_queues; i++) {
4038 		struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
4039 		unsigned size = dsize * rxq->bd.ring_size;
4040 
4041 		rxq->bd.qid = i;
4042 		rxq->bd.base = cbd_base;
4043 		rxq->bd.cur = cbd_base;
4044 		rxq->bd.dma = bd_dma;
4045 		rxq->bd.dsize = dsize;
4046 		rxq->bd.dsize_log2 = dsize_log2;
4047 		rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
4048 		bd_dma += size;
4049 		cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
4050 		rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
4051 	}
4052 
4053 	for (i = 0; i < fep->num_tx_queues; i++) {
4054 		struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
4055 		unsigned size = dsize * txq->bd.ring_size;
4056 
4057 		txq->bd.qid = i;
4058 		txq->bd.base = cbd_base;
4059 		txq->bd.cur = cbd_base;
4060 		txq->bd.dma = bd_dma;
4061 		txq->bd.dsize = dsize;
4062 		txq->bd.dsize_log2 = dsize_log2;
4063 		txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
4064 		bd_dma += size;
4065 		cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
4066 		txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
4067 	}
4068 
4069 
4070 	/* The FEC Ethernet specific entries in the device structure */
4071 	ndev->watchdog_timeo = TX_TIMEOUT;
4072 	ndev->netdev_ops = &fec_netdev_ops;
4073 	ndev->ethtool_ops = &fec_enet_ethtool_ops;
4074 
4075 	writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
4076 	netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi);
4077 
4078 	if (fep->quirks & FEC_QUIRK_HAS_VLAN)
4079 		/* enable hw VLAN support */
4080 		ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
4081 
4082 	if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
4083 		netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS);
4084 
4085 		/* enable hw accelerator */
4086 		ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
4087 				| NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
4088 		fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
4089 	}
4090 
4091 	if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
4092 		fep->tx_align = 0;
4093 		fep->rx_align = 0x3f;
4094 	}
4095 
4096 	ndev->hw_features = ndev->features;
4097 
4098 	if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME))
4099 		ndev->xdp_features = NETDEV_XDP_ACT_BASIC |
4100 				     NETDEV_XDP_ACT_REDIRECT;
4101 
4102 	fec_restart(ndev);
4103 
4104 	if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
4105 		fec_enet_clear_ethtool_stats(ndev);
4106 	else
4107 		fec_enet_update_ethtool_stats(ndev);
4108 
4109 	return 0;
4110 
4111 free_queue_mem:
4112 	fec_enet_free_queue(ndev);
4113 	return ret;
4114 }
4115 
4116 static void fec_enet_deinit(struct net_device *ndev)
4117 {
4118 	struct fec_enet_private *fep = netdev_priv(ndev);
4119 
4120 	netif_napi_del(&fep->napi);
4121 	fec_enet_free_queue(ndev);
4122 }
4123 
4124 #ifdef CONFIG_OF
4125 static int fec_reset_phy(struct platform_device *pdev)
4126 {
4127 	struct gpio_desc *phy_reset;
4128 	int msec = 1, phy_post_delay = 0;
4129 	struct device_node *np = pdev->dev.of_node;
4130 	int err;
4131 
4132 	if (!np)
4133 		return 0;
4134 
4135 	err = of_property_read_u32(np, "phy-reset-duration", &msec);
4136 	/* A sane reset duration should not be longer than 1s */
4137 	if (!err && msec > 1000)
4138 		msec = 1;
4139 
4140 	err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
4141 	/* valid reset duration should be less than 1s */
4142 	if (!err && phy_post_delay > 1000)
4143 		return -EINVAL;
4144 
4145 	phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset",
4146 					    GPIOD_OUT_HIGH);
4147 	if (IS_ERR(phy_reset))
4148 		return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset),
4149 				     "failed to get phy-reset-gpios\n");
4150 
4151 	if (!phy_reset)
4152 		return 0;
4153 
4154 	if (msec > 20)
4155 		msleep(msec);
4156 	else
4157 		usleep_range(msec * 1000, msec * 1000 + 1000);
4158 
4159 	gpiod_set_value_cansleep(phy_reset, 0);
4160 
4161 	if (!phy_post_delay)
4162 		return 0;
4163 
4164 	if (phy_post_delay > 20)
4165 		msleep(phy_post_delay);
4166 	else
4167 		usleep_range(phy_post_delay * 1000,
4168 			     phy_post_delay * 1000 + 1000);
4169 
4170 	return 0;
4171 }
4172 #else /* CONFIG_OF */
4173 static int fec_reset_phy(struct platform_device *pdev)
4174 {
4175 	/*
4176 	 * In case of platform probe, the reset has been done
4177 	 * by machine code.
4178 	 */
4179 	return 0;
4180 }
4181 #endif /* CONFIG_OF */
4182 
4183 static void
4184 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
4185 {
4186 	struct device_node *np = pdev->dev.of_node;
4187 
4188 	*num_tx = *num_rx = 1;
4189 
4190 	if (!np || !of_device_is_available(np))
4191 		return;
4192 
4193 	/* parse the num of tx and rx queues */
4194 	of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
4195 
4196 	of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
4197 
4198 	if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
4199 		dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
4200 			 *num_tx);
4201 		*num_tx = 1;
4202 		return;
4203 	}
4204 
4205 	if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
4206 		dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
4207 			 *num_rx);
4208 		*num_rx = 1;
4209 		return;
4210 	}
4211 
4212 }
4213 
4214 static int fec_enet_get_irq_cnt(struct platform_device *pdev)
4215 {
4216 	int irq_cnt = platform_irq_count(pdev);
4217 
4218 	if (irq_cnt > FEC_IRQ_NUM)
4219 		irq_cnt = FEC_IRQ_NUM;	/* last for pps */
4220 	else if (irq_cnt == 2)
4221 		irq_cnt = 1;	/* last for pps */
4222 	else if (irq_cnt <= 0)
4223 		irq_cnt = 1;	/* At least 1 irq is needed */
4224 	return irq_cnt;
4225 }
4226 
4227 static void fec_enet_get_wakeup_irq(struct platform_device *pdev)
4228 {
4229 	struct net_device *ndev = platform_get_drvdata(pdev);
4230 	struct fec_enet_private *fep = netdev_priv(ndev);
4231 
4232 	if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2)
4233 		fep->wake_irq = fep->irq[2];
4234 	else
4235 		fep->wake_irq = fep->irq[0];
4236 }
4237 
4238 static int fec_enet_init_stop_mode(struct fec_enet_private *fep,
4239 				   struct device_node *np)
4240 {
4241 	struct device_node *gpr_np;
4242 	u32 out_val[3];
4243 	int ret = 0;
4244 
4245 	gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0);
4246 	if (!gpr_np)
4247 		return 0;
4248 
4249 	ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
4250 					 ARRAY_SIZE(out_val));
4251 	if (ret) {
4252 		dev_dbg(&fep->pdev->dev, "no stop mode property\n");
4253 		goto out;
4254 	}
4255 
4256 	fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np);
4257 	if (IS_ERR(fep->stop_gpr.gpr)) {
4258 		dev_err(&fep->pdev->dev, "could not find gpr regmap\n");
4259 		ret = PTR_ERR(fep->stop_gpr.gpr);
4260 		fep->stop_gpr.gpr = NULL;
4261 		goto out;
4262 	}
4263 
4264 	fep->stop_gpr.reg = out_val[1];
4265 	fep->stop_gpr.bit = out_val[2];
4266 
4267 out:
4268 	of_node_put(gpr_np);
4269 
4270 	return ret;
4271 }
4272 
4273 static int
4274 fec_probe(struct platform_device *pdev)
4275 {
4276 	struct fec_enet_private *fep;
4277 	struct fec_platform_data *pdata;
4278 	phy_interface_t interface;
4279 	struct net_device *ndev;
4280 	int i, irq, ret = 0;
4281 	const struct of_device_id *of_id;
4282 	static int dev_id;
4283 	struct device_node *np = pdev->dev.of_node, *phy_node;
4284 	int num_tx_qs;
4285 	int num_rx_qs;
4286 	char irq_name[8];
4287 	int irq_cnt;
4288 	struct fec_devinfo *dev_info;
4289 
4290 	fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
4291 
4292 	/* Init network device */
4293 	ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
4294 				  FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
4295 	if (!ndev)
4296 		return -ENOMEM;
4297 
4298 	SET_NETDEV_DEV(ndev, &pdev->dev);
4299 
4300 	/* setup board info structure */
4301 	fep = netdev_priv(ndev);
4302 
4303 	of_id = of_match_device(fec_dt_ids, &pdev->dev);
4304 	if (of_id)
4305 		pdev->id_entry = of_id->data;
4306 	dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data;
4307 	if (dev_info)
4308 		fep->quirks = dev_info->quirks;
4309 
4310 	fep->netdev = ndev;
4311 	fep->num_rx_queues = num_rx_qs;
4312 	fep->num_tx_queues = num_tx_qs;
4313 
4314 #if !defined(CONFIG_M5272)
4315 	/* default enable pause frame auto negotiation */
4316 	if (fep->quirks & FEC_QUIRK_HAS_GBIT)
4317 		fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
4318 #endif
4319 
4320 	/* Select default pin state */
4321 	pinctrl_pm_select_default_state(&pdev->dev);
4322 
4323 	fep->hwp = devm_platform_ioremap_resource(pdev, 0);
4324 	if (IS_ERR(fep->hwp)) {
4325 		ret = PTR_ERR(fep->hwp);
4326 		goto failed_ioremap;
4327 	}
4328 
4329 	fep->pdev = pdev;
4330 	fep->dev_id = dev_id++;
4331 
4332 	platform_set_drvdata(pdev, ndev);
4333 
4334 	if ((of_machine_is_compatible("fsl,imx6q") ||
4335 	     of_machine_is_compatible("fsl,imx6dl")) &&
4336 	    !of_property_read_bool(np, "fsl,err006687-workaround-present"))
4337 		fep->quirks |= FEC_QUIRK_ERR006687;
4338 
4339 	ret = fec_enet_ipc_handle_init(fep);
4340 	if (ret)
4341 		goto failed_ipc_init;
4342 
4343 	if (of_property_read_bool(np, "fsl,magic-packet"))
4344 		fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
4345 
4346 	ret = fec_enet_init_stop_mode(fep, np);
4347 	if (ret)
4348 		goto failed_stop_mode;
4349 
4350 	phy_node = of_parse_phandle(np, "phy-handle", 0);
4351 	if (!phy_node && of_phy_is_fixed_link(np)) {
4352 		ret = of_phy_register_fixed_link(np);
4353 		if (ret < 0) {
4354 			dev_err(&pdev->dev,
4355 				"broken fixed-link specification\n");
4356 			goto failed_phy;
4357 		}
4358 		phy_node = of_node_get(np);
4359 	}
4360 	fep->phy_node = phy_node;
4361 
4362 	ret = of_get_phy_mode(pdev->dev.of_node, &interface);
4363 	if (ret) {
4364 		pdata = dev_get_platdata(&pdev->dev);
4365 		if (pdata)
4366 			fep->phy_interface = pdata->phy;
4367 		else
4368 			fep->phy_interface = PHY_INTERFACE_MODE_MII;
4369 	} else {
4370 		fep->phy_interface = interface;
4371 	}
4372 
4373 	ret = fec_enet_parse_rgmii_delay(fep, np);
4374 	if (ret)
4375 		goto failed_rgmii_delay;
4376 
4377 	fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
4378 	if (IS_ERR(fep->clk_ipg)) {
4379 		ret = PTR_ERR(fep->clk_ipg);
4380 		goto failed_clk;
4381 	}
4382 
4383 	fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
4384 	if (IS_ERR(fep->clk_ahb)) {
4385 		ret = PTR_ERR(fep->clk_ahb);
4386 		goto failed_clk;
4387 	}
4388 
4389 	fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
4390 
4391 	/* enet_out is optional, depends on board */
4392 	fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out");
4393 	if (IS_ERR(fep->clk_enet_out)) {
4394 		ret = PTR_ERR(fep->clk_enet_out);
4395 		goto failed_clk;
4396 	}
4397 
4398 	fep->ptp_clk_on = false;
4399 	mutex_init(&fep->ptp_clk_mutex);
4400 
4401 	/* clk_ref is optional, depends on board */
4402 	fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref");
4403 	if (IS_ERR(fep->clk_ref)) {
4404 		ret = PTR_ERR(fep->clk_ref);
4405 		goto failed_clk;
4406 	}
4407 	fep->clk_ref_rate = clk_get_rate(fep->clk_ref);
4408 
4409 	/* clk_2x_txclk is optional, depends on board */
4410 	if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) {
4411 		fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk");
4412 		if (IS_ERR(fep->clk_2x_txclk))
4413 			fep->clk_2x_txclk = NULL;
4414 	}
4415 
4416 	fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
4417 	fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
4418 	if (IS_ERR(fep->clk_ptp)) {
4419 		fep->clk_ptp = NULL;
4420 		fep->bufdesc_ex = false;
4421 	}
4422 
4423 	ret = fec_enet_clk_enable(ndev, true);
4424 	if (ret)
4425 		goto failed_clk;
4426 
4427 	ret = clk_prepare_enable(fep->clk_ipg);
4428 	if (ret)
4429 		goto failed_clk_ipg;
4430 	ret = clk_prepare_enable(fep->clk_ahb);
4431 	if (ret)
4432 		goto failed_clk_ahb;
4433 
4434 	fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy");
4435 	if (!IS_ERR(fep->reg_phy)) {
4436 		ret = regulator_enable(fep->reg_phy);
4437 		if (ret) {
4438 			dev_err(&pdev->dev,
4439 				"Failed to enable phy regulator: %d\n", ret);
4440 			goto failed_regulator;
4441 		}
4442 	} else {
4443 		if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
4444 			ret = -EPROBE_DEFER;
4445 			goto failed_regulator;
4446 		}
4447 		fep->reg_phy = NULL;
4448 	}
4449 
4450 	pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
4451 	pm_runtime_use_autosuspend(&pdev->dev);
4452 	pm_runtime_get_noresume(&pdev->dev);
4453 	pm_runtime_set_active(&pdev->dev);
4454 	pm_runtime_enable(&pdev->dev);
4455 
4456 	ret = fec_reset_phy(pdev);
4457 	if (ret)
4458 		goto failed_reset;
4459 
4460 	irq_cnt = fec_enet_get_irq_cnt(pdev);
4461 	if (fep->bufdesc_ex)
4462 		fec_ptp_init(pdev, irq_cnt);
4463 
4464 	ret = fec_enet_init(ndev);
4465 	if (ret)
4466 		goto failed_init;
4467 
4468 	for (i = 0; i < irq_cnt; i++) {
4469 		snprintf(irq_name, sizeof(irq_name), "int%d", i);
4470 		irq = platform_get_irq_byname_optional(pdev, irq_name);
4471 		if (irq < 0)
4472 			irq = platform_get_irq(pdev, i);
4473 		if (irq < 0) {
4474 			ret = irq;
4475 			goto failed_irq;
4476 		}
4477 		ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
4478 				       0, pdev->name, ndev);
4479 		if (ret)
4480 			goto failed_irq;
4481 
4482 		fep->irq[i] = irq;
4483 	}
4484 
4485 	/* Decide which interrupt line is wakeup capable */
4486 	fec_enet_get_wakeup_irq(pdev);
4487 
4488 	ret = fec_enet_mii_init(pdev);
4489 	if (ret)
4490 		goto failed_mii_init;
4491 
4492 	/* Carrier starts down, phylib will bring it up */
4493 	netif_carrier_off(ndev);
4494 	fec_enet_clk_enable(ndev, false);
4495 	pinctrl_pm_select_sleep_state(&pdev->dev);
4496 
4497 	ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN;
4498 
4499 	ret = register_netdev(ndev);
4500 	if (ret)
4501 		goto failed_register;
4502 
4503 	device_init_wakeup(&ndev->dev, fep->wol_flag &
4504 			   FEC_WOL_HAS_MAGIC_PACKET);
4505 
4506 	if (fep->bufdesc_ex && fep->ptp_clock)
4507 		netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
4508 
4509 	INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
4510 
4511 	pm_runtime_mark_last_busy(&pdev->dev);
4512 	pm_runtime_put_autosuspend(&pdev->dev);
4513 
4514 	return 0;
4515 
4516 failed_register:
4517 	fec_enet_mii_remove(fep);
4518 failed_mii_init:
4519 failed_irq:
4520 	fec_enet_deinit(ndev);
4521 failed_init:
4522 	fec_ptp_stop(pdev);
4523 failed_reset:
4524 	pm_runtime_put_noidle(&pdev->dev);
4525 	pm_runtime_disable(&pdev->dev);
4526 	if (fep->reg_phy)
4527 		regulator_disable(fep->reg_phy);
4528 failed_regulator:
4529 	clk_disable_unprepare(fep->clk_ahb);
4530 failed_clk_ahb:
4531 	clk_disable_unprepare(fep->clk_ipg);
4532 failed_clk_ipg:
4533 	fec_enet_clk_enable(ndev, false);
4534 failed_clk:
4535 failed_rgmii_delay:
4536 	if (of_phy_is_fixed_link(np))
4537 		of_phy_deregister_fixed_link(np);
4538 	of_node_put(phy_node);
4539 failed_stop_mode:
4540 failed_ipc_init:
4541 failed_phy:
4542 	dev_id--;
4543 failed_ioremap:
4544 	free_netdev(ndev);
4545 
4546 	return ret;
4547 }
4548 
4549 static void
4550 fec_drv_remove(struct platform_device *pdev)
4551 {
4552 	struct net_device *ndev = platform_get_drvdata(pdev);
4553 	struct fec_enet_private *fep = netdev_priv(ndev);
4554 	struct device_node *np = pdev->dev.of_node;
4555 	int ret;
4556 
4557 	ret = pm_runtime_get_sync(&pdev->dev);
4558 	if (ret < 0)
4559 		dev_err(&pdev->dev,
4560 			"Failed to resume device in remove callback (%pe)\n",
4561 			ERR_PTR(ret));
4562 
4563 	cancel_work_sync(&fep->tx_timeout_work);
4564 	fec_ptp_stop(pdev);
4565 	unregister_netdev(ndev);
4566 	fec_enet_mii_remove(fep);
4567 	if (fep->reg_phy)
4568 		regulator_disable(fep->reg_phy);
4569 
4570 	if (of_phy_is_fixed_link(np))
4571 		of_phy_deregister_fixed_link(np);
4572 	of_node_put(fep->phy_node);
4573 
4574 	/* After pm_runtime_get_sync() failed, the clks are still off, so skip
4575 	 * disabling them again.
4576 	 */
4577 	if (ret >= 0) {
4578 		clk_disable_unprepare(fep->clk_ahb);
4579 		clk_disable_unprepare(fep->clk_ipg);
4580 	}
4581 	pm_runtime_put_noidle(&pdev->dev);
4582 	pm_runtime_disable(&pdev->dev);
4583 
4584 	fec_enet_deinit(ndev);
4585 	free_netdev(ndev);
4586 }
4587 
4588 static int __maybe_unused fec_suspend(struct device *dev)
4589 {
4590 	struct net_device *ndev = dev_get_drvdata(dev);
4591 	struct fec_enet_private *fep = netdev_priv(ndev);
4592 	int ret;
4593 
4594 	rtnl_lock();
4595 	if (netif_running(ndev)) {
4596 		if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
4597 			fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
4598 		phy_stop(ndev->phydev);
4599 		napi_disable(&fep->napi);
4600 		netif_tx_lock_bh(ndev);
4601 		netif_device_detach(ndev);
4602 		netif_tx_unlock_bh(ndev);
4603 		fec_stop(ndev);
4604 		if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
4605 			fec_irqs_disable(ndev);
4606 			pinctrl_pm_select_sleep_state(&fep->pdev->dev);
4607 		} else {
4608 			fec_irqs_disable_except_wakeup(ndev);
4609 			if (fep->wake_irq > 0) {
4610 				disable_irq(fep->wake_irq);
4611 				enable_irq_wake(fep->wake_irq);
4612 			}
4613 			fec_enet_stop_mode(fep, true);
4614 		}
4615 		/* It's safe to disable clocks since interrupts are masked */
4616 		fec_enet_clk_enable(ndev, false);
4617 
4618 		fep->rpm_active = !pm_runtime_status_suspended(dev);
4619 		if (fep->rpm_active) {
4620 			ret = pm_runtime_force_suspend(dev);
4621 			if (ret < 0) {
4622 				rtnl_unlock();
4623 				return ret;
4624 			}
4625 		}
4626 	}
4627 	rtnl_unlock();
4628 
4629 	if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
4630 		regulator_disable(fep->reg_phy);
4631 
4632 	/* SOC supply clock to phy, when clock is disabled, phy link down
4633 	 * SOC control phy regulator, when regulator is disabled, phy link down
4634 	 */
4635 	if (fep->clk_enet_out || fep->reg_phy)
4636 		fep->link = 0;
4637 
4638 	return 0;
4639 }
4640 
4641 static int __maybe_unused fec_resume(struct device *dev)
4642 {
4643 	struct net_device *ndev = dev_get_drvdata(dev);
4644 	struct fec_enet_private *fep = netdev_priv(ndev);
4645 	int ret;
4646 	int val;
4647 
4648 	if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
4649 		ret = regulator_enable(fep->reg_phy);
4650 		if (ret)
4651 			return ret;
4652 	}
4653 
4654 	rtnl_lock();
4655 	if (netif_running(ndev)) {
4656 		if (fep->rpm_active)
4657 			pm_runtime_force_resume(dev);
4658 
4659 		ret = fec_enet_clk_enable(ndev, true);
4660 		if (ret) {
4661 			rtnl_unlock();
4662 			goto failed_clk;
4663 		}
4664 		if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
4665 			fec_enet_stop_mode(fep, false);
4666 			if (fep->wake_irq) {
4667 				disable_irq_wake(fep->wake_irq);
4668 				enable_irq(fep->wake_irq);
4669 			}
4670 
4671 			val = readl(fep->hwp + FEC_ECNTRL);
4672 			val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
4673 			writel(val, fep->hwp + FEC_ECNTRL);
4674 			fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
4675 		} else {
4676 			pinctrl_pm_select_default_state(&fep->pdev->dev);
4677 		}
4678 		fec_restart(ndev);
4679 		netif_tx_lock_bh(ndev);
4680 		netif_device_attach(ndev);
4681 		netif_tx_unlock_bh(ndev);
4682 		napi_enable(&fep->napi);
4683 		phy_init_hw(ndev->phydev);
4684 		phy_start(ndev->phydev);
4685 	}
4686 	rtnl_unlock();
4687 
4688 	return 0;
4689 
4690 failed_clk:
4691 	if (fep->reg_phy)
4692 		regulator_disable(fep->reg_phy);
4693 	return ret;
4694 }
4695 
4696 static int __maybe_unused fec_runtime_suspend(struct device *dev)
4697 {
4698 	struct net_device *ndev = dev_get_drvdata(dev);
4699 	struct fec_enet_private *fep = netdev_priv(ndev);
4700 
4701 	clk_disable_unprepare(fep->clk_ahb);
4702 	clk_disable_unprepare(fep->clk_ipg);
4703 
4704 	return 0;
4705 }
4706 
4707 static int __maybe_unused fec_runtime_resume(struct device *dev)
4708 {
4709 	struct net_device *ndev = dev_get_drvdata(dev);
4710 	struct fec_enet_private *fep = netdev_priv(ndev);
4711 	int ret;
4712 
4713 	ret = clk_prepare_enable(fep->clk_ahb);
4714 	if (ret)
4715 		return ret;
4716 	ret = clk_prepare_enable(fep->clk_ipg);
4717 	if (ret)
4718 		goto failed_clk_ipg;
4719 
4720 	return 0;
4721 
4722 failed_clk_ipg:
4723 	clk_disable_unprepare(fep->clk_ahb);
4724 	return ret;
4725 }
4726 
4727 static const struct dev_pm_ops fec_pm_ops = {
4728 	SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
4729 	SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
4730 };
4731 
4732 static struct platform_driver fec_driver = {
4733 	.driver	= {
4734 		.name	= DRIVER_NAME,
4735 		.pm	= &fec_pm_ops,
4736 		.of_match_table = fec_dt_ids,
4737 		.suppress_bind_attrs = true,
4738 	},
4739 	.id_table = fec_devtype,
4740 	.probe	= fec_probe,
4741 	.remove_new = fec_drv_remove,
4742 };
4743 
4744 module_platform_driver(fec_driver);
4745 
4746 MODULE_LICENSE("GPL");
4747