1 /* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 * 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/string.h> 27 #include <linux/ptrace.h> 28 #include <linux/errno.h> 29 #include <linux/ioport.h> 30 #include <linux/slab.h> 31 #include <linux/interrupt.h> 32 #include <linux/init.h> 33 #include <linux/delay.h> 34 #include <linux/netdevice.h> 35 #include <linux/etherdevice.h> 36 #include <linux/skbuff.h> 37 #include <linux/in.h> 38 #include <linux/ip.h> 39 #include <net/ip.h> 40 #include <linux/tcp.h> 41 #include <linux/udp.h> 42 #include <linux/icmp.h> 43 #include <linux/spinlock.h> 44 #include <linux/workqueue.h> 45 #include <linux/bitops.h> 46 #include <linux/io.h> 47 #include <linux/irq.h> 48 #include <linux/clk.h> 49 #include <linux/platform_device.h> 50 #include <linux/phy.h> 51 #include <linux/fec.h> 52 #include <linux/of.h> 53 #include <linux/of_device.h> 54 #include <linux/of_gpio.h> 55 #include <linux/of_net.h> 56 #include <linux/regulator/consumer.h> 57 #include <linux/if_vlan.h> 58 59 #include <asm/cacheflush.h> 60 61 #include "fec.h" 62 63 static void set_multicast_list(struct net_device *ndev); 64 65 #if defined(CONFIG_ARM) 66 #define FEC_ALIGNMENT 0xf 67 #else 68 #define FEC_ALIGNMENT 0x3 69 #endif 70 71 #define DRIVER_NAME "fec" 72 73 /* Pause frame feild and FIFO threshold */ 74 #define FEC_ENET_FCE (1 << 5) 75 #define FEC_ENET_RSEM_V 0x84 76 #define FEC_ENET_RSFL_V 16 77 #define FEC_ENET_RAEM_V 0x8 78 #define FEC_ENET_RAFL_V 0x8 79 #define FEC_ENET_OPD_V 0xFFF0 80 81 /* Controller is ENET-MAC */ 82 #define FEC_QUIRK_ENET_MAC (1 << 0) 83 /* Controller needs driver to swap frame */ 84 #define FEC_QUIRK_SWAP_FRAME (1 << 1) 85 /* Controller uses gasket */ 86 #define FEC_QUIRK_USE_GASKET (1 << 2) 87 /* Controller has GBIT support */ 88 #define FEC_QUIRK_HAS_GBIT (1 << 3) 89 /* Controller has extend desc buffer */ 90 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) 91 /* Controller has hardware checksum support */ 92 #define FEC_QUIRK_HAS_CSUM (1 << 5) 93 /* Controller has hardware vlan support */ 94 #define FEC_QUIRK_HAS_VLAN (1 << 6) 95 /* ENET IP errata ERR006358 96 * 97 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously 98 * detected as not set during a prior frame transmission, then the 99 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs 100 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in 101 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously 102 * detected as not set during a prior frame transmission, then the 103 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs 104 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in 105 * frames not being transmitted until there is a 0-to-1 transition on 106 * ENET_TDAR[TDAR]. 107 */ 108 #define FEC_QUIRK_ERR006358 (1 << 7) 109 110 static struct platform_device_id fec_devtype[] = { 111 { 112 /* keep it for coldfire */ 113 .name = DRIVER_NAME, 114 .driver_data = 0, 115 }, { 116 .name = "imx25-fec", 117 .driver_data = FEC_QUIRK_USE_GASKET, 118 }, { 119 .name = "imx27-fec", 120 .driver_data = 0, 121 }, { 122 .name = "imx28-fec", 123 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, 124 }, { 125 .name = "imx6q-fec", 126 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 127 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 128 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358, 129 }, { 130 .name = "mvf600-fec", 131 .driver_data = FEC_QUIRK_ENET_MAC, 132 }, { 133 /* sentinel */ 134 } 135 }; 136 MODULE_DEVICE_TABLE(platform, fec_devtype); 137 138 enum imx_fec_type { 139 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 140 IMX27_FEC, /* runs on i.mx27/35/51 */ 141 IMX28_FEC, 142 IMX6Q_FEC, 143 MVF600_FEC, 144 }; 145 146 static const struct of_device_id fec_dt_ids[] = { 147 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 148 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 149 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 150 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 151 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 152 { /* sentinel */ } 153 }; 154 MODULE_DEVICE_TABLE(of, fec_dt_ids); 155 156 static unsigned char macaddr[ETH_ALEN]; 157 module_param_array(macaddr, byte, NULL, 0); 158 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 159 160 #if defined(CONFIG_M5272) 161 /* 162 * Some hardware gets it MAC address out of local flash memory. 163 * if this is non-zero then assume it is the address to get MAC from. 164 */ 165 #if defined(CONFIG_NETtel) 166 #define FEC_FLASHMAC 0xf0006006 167 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 168 #define FEC_FLASHMAC 0xf0006000 169 #elif defined(CONFIG_CANCam) 170 #define FEC_FLASHMAC 0xf0020000 171 #elif defined (CONFIG_M5272C3) 172 #define FEC_FLASHMAC (0xffe04000 + 4) 173 #elif defined(CONFIG_MOD5272) 174 #define FEC_FLASHMAC 0xffc0406b 175 #else 176 #define FEC_FLASHMAC 0 177 #endif 178 #endif /* CONFIG_M5272 */ 179 180 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE) 181 #error "FEC: descriptor ring size constants too large" 182 #endif 183 184 /* Interrupt events/masks. */ 185 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ 186 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ 187 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ 188 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ 189 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ 190 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ 191 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ 192 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ 193 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ 194 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ 195 196 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) 197 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) 198 199 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 200 */ 201 #define PKT_MAXBUF_SIZE 1522 202 #define PKT_MINBUF_SIZE 64 203 #define PKT_MAXBLR_SIZE 1536 204 205 /* FEC receive acceleration */ 206 #define FEC_RACC_IPDIS (1 << 1) 207 #define FEC_RACC_PRODIS (1 << 2) 208 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 209 210 /* 211 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 212 * size bits. Other FEC hardware does not, so we need to take that into 213 * account when setting it. 214 */ 215 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 216 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 217 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 218 #else 219 #define OPT_FRAME_SIZE 0 220 #endif 221 222 /* FEC MII MMFR bits definition */ 223 #define FEC_MMFR_ST (1 << 30) 224 #define FEC_MMFR_OP_READ (2 << 28) 225 #define FEC_MMFR_OP_WRITE (1 << 28) 226 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 227 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 228 #define FEC_MMFR_TA (2 << 16) 229 #define FEC_MMFR_DATA(v) (v & 0xffff) 230 231 #define FEC_MII_TIMEOUT 30000 /* us */ 232 233 /* Transmitter timeout */ 234 #define TX_TIMEOUT (2 * HZ) 235 236 #define FEC_PAUSE_FLAG_AUTONEG 0x1 237 #define FEC_PAUSE_FLAG_ENABLE 0x2 238 239 static int mii_cnt; 240 241 static inline 242 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep) 243 { 244 struct bufdesc *new_bd = bdp + 1; 245 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1; 246 struct bufdesc_ex *ex_base; 247 struct bufdesc *base; 248 int ring_size; 249 250 if (bdp >= fep->tx_bd_base) { 251 base = fep->tx_bd_base; 252 ring_size = fep->tx_ring_size; 253 ex_base = (struct bufdesc_ex *)fep->tx_bd_base; 254 } else { 255 base = fep->rx_bd_base; 256 ring_size = fep->rx_ring_size; 257 ex_base = (struct bufdesc_ex *)fep->rx_bd_base; 258 } 259 260 if (fep->bufdesc_ex) 261 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ? 262 ex_base : ex_new_bd); 263 else 264 return (new_bd >= (base + ring_size)) ? 265 base : new_bd; 266 } 267 268 static inline 269 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep) 270 { 271 struct bufdesc *new_bd = bdp - 1; 272 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1; 273 struct bufdesc_ex *ex_base; 274 struct bufdesc *base; 275 int ring_size; 276 277 if (bdp >= fep->tx_bd_base) { 278 base = fep->tx_bd_base; 279 ring_size = fep->tx_ring_size; 280 ex_base = (struct bufdesc_ex *)fep->tx_bd_base; 281 } else { 282 base = fep->rx_bd_base; 283 ring_size = fep->rx_ring_size; 284 ex_base = (struct bufdesc_ex *)fep->rx_bd_base; 285 } 286 287 if (fep->bufdesc_ex) 288 return (struct bufdesc *)((ex_new_bd < ex_base) ? 289 (ex_new_bd + ring_size) : ex_new_bd); 290 else 291 return (new_bd < base) ? (new_bd + ring_size) : new_bd; 292 } 293 294 static void *swap_buffer(void *bufaddr, int len) 295 { 296 int i; 297 unsigned int *buf = bufaddr; 298 299 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++) 300 *buf = cpu_to_be32(*buf); 301 302 return bufaddr; 303 } 304 305 static int 306 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 307 { 308 /* Only run for packets requiring a checksum. */ 309 if (skb->ip_summed != CHECKSUM_PARTIAL) 310 return 0; 311 312 if (unlikely(skb_cow_head(skb, 0))) 313 return -1; 314 315 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 316 317 return 0; 318 } 319 320 static netdev_tx_t 321 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 322 { 323 struct fec_enet_private *fep = netdev_priv(ndev); 324 const struct platform_device_id *id_entry = 325 platform_get_device_id(fep->pdev); 326 struct bufdesc *bdp, *bdp_pre; 327 void *bufaddr; 328 unsigned short status; 329 unsigned int index; 330 331 /* Fill in a Tx ring entry */ 332 bdp = fep->cur_tx; 333 334 status = bdp->cbd_sc; 335 336 if (status & BD_ENET_TX_READY) { 337 /* Ooops. All transmit buffers are full. Bail out. 338 * This should not happen, since ndev->tbusy should be set. 339 */ 340 netdev_err(ndev, "tx queue full!\n"); 341 return NETDEV_TX_BUSY; 342 } 343 344 /* Protocol checksum off-load for TCP and UDP. */ 345 if (fec_enet_clear_csum(skb, ndev)) { 346 kfree_skb(skb); 347 return NETDEV_TX_OK; 348 } 349 350 /* Clear all of the status flags */ 351 status &= ~BD_ENET_TX_STATS; 352 353 /* Set buffer length and buffer pointer */ 354 bufaddr = skb->data; 355 bdp->cbd_datlen = skb->len; 356 357 /* 358 * On some FEC implementations data must be aligned on 359 * 4-byte boundaries. Use bounce buffers to copy data 360 * and get it aligned. Ugh. 361 */ 362 if (fep->bufdesc_ex) 363 index = (struct bufdesc_ex *)bdp - 364 (struct bufdesc_ex *)fep->tx_bd_base; 365 else 366 index = bdp - fep->tx_bd_base; 367 368 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { 369 memcpy(fep->tx_bounce[index], skb->data, skb->len); 370 bufaddr = fep->tx_bounce[index]; 371 } 372 373 /* 374 * Some design made an incorrect assumption on endian mode of 375 * the system that it's running on. As the result, driver has to 376 * swap every frame going to and coming from the controller. 377 */ 378 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 379 swap_buffer(bufaddr, skb->len); 380 381 /* Save skb pointer */ 382 fep->tx_skbuff[index] = skb; 383 384 /* Push the data cache so the CPM does not get stale memory 385 * data. 386 */ 387 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, 388 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); 389 390 /* Send it on its way. Tell FEC it's ready, interrupt when done, 391 * it's the last BD of the frame, and to put the CRC on the end. 392 */ 393 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR 394 | BD_ENET_TX_LAST | BD_ENET_TX_TC); 395 bdp->cbd_sc = status; 396 397 if (fep->bufdesc_ex) { 398 399 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 400 ebdp->cbd_bdu = 0; 401 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 402 fep->hwts_tx_en)) { 403 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT); 404 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 405 } else { 406 ebdp->cbd_esc = BD_ENET_TX_INT; 407 408 /* Enable protocol checksum flags 409 * We do not bother with the IP Checksum bits as they 410 * are done by the kernel 411 */ 412 if (skb->ip_summed == CHECKSUM_PARTIAL) 413 ebdp->cbd_esc |= BD_ENET_TX_PINS; 414 } 415 } 416 417 bdp_pre = fec_enet_get_prevdesc(bdp, fep); 418 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) && 419 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) { 420 fep->delay_work.trig_tx = true; 421 schedule_delayed_work(&(fep->delay_work.delay_work), 422 msecs_to_jiffies(1)); 423 } 424 425 /* If this was the last BD in the ring, start at the beginning again. */ 426 bdp = fec_enet_get_nextdesc(bdp, fep); 427 428 fep->cur_tx = bdp; 429 430 if (fep->cur_tx == fep->dirty_tx) 431 netif_stop_queue(ndev); 432 433 /* Trigger transmission start */ 434 writel(0, fep->hwp + FEC_X_DES_ACTIVE); 435 436 skb_tx_timestamp(skb); 437 438 return NETDEV_TX_OK; 439 } 440 441 /* Init RX & TX buffer descriptors 442 */ 443 static void fec_enet_bd_init(struct net_device *dev) 444 { 445 struct fec_enet_private *fep = netdev_priv(dev); 446 struct bufdesc *bdp; 447 unsigned int i; 448 449 /* Initialize the receive buffer descriptors. */ 450 bdp = fep->rx_bd_base; 451 for (i = 0; i < fep->rx_ring_size; i++) { 452 453 /* Initialize the BD for every fragment in the page. */ 454 if (bdp->cbd_bufaddr) 455 bdp->cbd_sc = BD_ENET_RX_EMPTY; 456 else 457 bdp->cbd_sc = 0; 458 bdp = fec_enet_get_nextdesc(bdp, fep); 459 } 460 461 /* Set the last buffer to wrap */ 462 bdp = fec_enet_get_prevdesc(bdp, fep); 463 bdp->cbd_sc |= BD_SC_WRAP; 464 465 fep->cur_rx = fep->rx_bd_base; 466 467 /* ...and the same for transmit */ 468 bdp = fep->tx_bd_base; 469 fep->cur_tx = bdp; 470 for (i = 0; i < fep->tx_ring_size; i++) { 471 472 /* Initialize the BD for every fragment in the page. */ 473 bdp->cbd_sc = 0; 474 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) { 475 dev_kfree_skb_any(fep->tx_skbuff[i]); 476 fep->tx_skbuff[i] = NULL; 477 } 478 bdp->cbd_bufaddr = 0; 479 bdp = fec_enet_get_nextdesc(bdp, fep); 480 } 481 482 /* Set the last buffer to wrap */ 483 bdp = fec_enet_get_prevdesc(bdp, fep); 484 bdp->cbd_sc |= BD_SC_WRAP; 485 fep->dirty_tx = bdp; 486 } 487 488 /* This function is called to start or restart the FEC during a link 489 * change. This only happens when switching between half and full 490 * duplex. 491 */ 492 static void 493 fec_restart(struct net_device *ndev, int duplex) 494 { 495 struct fec_enet_private *fep = netdev_priv(ndev); 496 const struct platform_device_id *id_entry = 497 platform_get_device_id(fep->pdev); 498 int i; 499 u32 val; 500 u32 temp_mac[2]; 501 u32 rcntl = OPT_FRAME_SIZE | 0x04; 502 u32 ecntl = 0x2; /* ETHEREN */ 503 504 if (netif_running(ndev)) { 505 netif_device_detach(ndev); 506 napi_disable(&fep->napi); 507 netif_stop_queue(ndev); 508 netif_tx_lock_bh(ndev); 509 } 510 511 /* Whack a reset. We should wait for this. */ 512 writel(1, fep->hwp + FEC_ECNTRL); 513 udelay(10); 514 515 /* 516 * enet-mac reset will reset mac address registers too, 517 * so need to reconfigure it. 518 */ 519 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 520 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 521 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); 522 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); 523 } 524 525 /* Clear any outstanding interrupt. */ 526 writel(0xffc00000, fep->hwp + FEC_IEVENT); 527 528 /* Setup multicast filter. */ 529 set_multicast_list(ndev); 530 #ifndef CONFIG_M5272 531 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 532 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 533 #endif 534 535 /* Set maximum receive buffer size. */ 536 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); 537 538 fec_enet_bd_init(ndev); 539 540 /* Set receive and transmit descriptor base. */ 541 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); 542 if (fep->bufdesc_ex) 543 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex) 544 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START); 545 else 546 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) 547 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START); 548 549 550 for (i = 0; i <= TX_RING_MOD_MASK; i++) { 551 if (fep->tx_skbuff[i]) { 552 dev_kfree_skb_any(fep->tx_skbuff[i]); 553 fep->tx_skbuff[i] = NULL; 554 } 555 } 556 557 /* Enable MII mode */ 558 if (duplex) { 559 /* FD enable */ 560 writel(0x04, fep->hwp + FEC_X_CNTRL); 561 } else { 562 /* No Rcv on Xmit */ 563 rcntl |= 0x02; 564 writel(0x0, fep->hwp + FEC_X_CNTRL); 565 } 566 567 fep->full_duplex = duplex; 568 569 /* Set MII speed */ 570 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 571 572 #if !defined(CONFIG_M5272) 573 /* set RX checksum */ 574 val = readl(fep->hwp + FEC_RACC); 575 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 576 val |= FEC_RACC_OPTIONS; 577 else 578 val &= ~FEC_RACC_OPTIONS; 579 writel(val, fep->hwp + FEC_RACC); 580 #endif 581 582 /* 583 * The phy interface and speed need to get configured 584 * differently on enet-mac. 585 */ 586 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 587 /* Enable flow control and length check */ 588 rcntl |= 0x40000000 | 0x00000020; 589 590 /* RGMII, RMII or MII */ 591 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) 592 rcntl |= (1 << 6); 593 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 594 rcntl |= (1 << 8); 595 else 596 rcntl &= ~(1 << 8); 597 598 /* 1G, 100M or 10M */ 599 if (fep->phy_dev) { 600 if (fep->phy_dev->speed == SPEED_1000) 601 ecntl |= (1 << 5); 602 else if (fep->phy_dev->speed == SPEED_100) 603 rcntl &= ~(1 << 9); 604 else 605 rcntl |= (1 << 9); 606 } 607 } else { 608 #ifdef FEC_MIIGSK_ENR 609 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { 610 u32 cfgr; 611 /* disable the gasket and wait */ 612 writel(0, fep->hwp + FEC_MIIGSK_ENR); 613 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 614 udelay(1); 615 616 /* 617 * configure the gasket: 618 * RMII, 50 MHz, no loopback, no echo 619 * MII, 25 MHz, no loopback, no echo 620 */ 621 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 622 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 623 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) 624 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 625 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 626 627 /* re-enable the gasket */ 628 writel(2, fep->hwp + FEC_MIIGSK_ENR); 629 } 630 #endif 631 } 632 633 #if !defined(CONFIG_M5272) 634 /* enable pause frame*/ 635 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 636 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 637 fep->phy_dev && fep->phy_dev->pause)) { 638 rcntl |= FEC_ENET_FCE; 639 640 /* set FIFO threshold parameter to reduce overrun */ 641 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 642 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 643 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 644 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 645 646 /* OPD */ 647 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 648 } else { 649 rcntl &= ~FEC_ENET_FCE; 650 } 651 #endif /* !defined(CONFIG_M5272) */ 652 653 writel(rcntl, fep->hwp + FEC_R_CNTRL); 654 655 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 656 /* enable ENET endian swap */ 657 ecntl |= (1 << 8); 658 /* enable ENET store and forward mode */ 659 writel(1 << 8, fep->hwp + FEC_X_WMRK); 660 } 661 662 if (fep->bufdesc_ex) 663 ecntl |= (1 << 4); 664 665 #ifndef CONFIG_M5272 666 /* Enable the MIB statistic event counters */ 667 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 668 #endif 669 670 /* And last, enable the transmit and receive processing */ 671 writel(ecntl, fep->hwp + FEC_ECNTRL); 672 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 673 674 if (fep->bufdesc_ex) 675 fec_ptp_start_cyclecounter(ndev); 676 677 /* Enable interrupts we wish to service */ 678 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 679 680 if (netif_running(ndev)) { 681 netif_tx_unlock_bh(ndev); 682 netif_wake_queue(ndev); 683 napi_enable(&fep->napi); 684 netif_device_attach(ndev); 685 } 686 } 687 688 static void 689 fec_stop(struct net_device *ndev) 690 { 691 struct fec_enet_private *fep = netdev_priv(ndev); 692 const struct platform_device_id *id_entry = 693 platform_get_device_id(fep->pdev); 694 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 695 696 /* We cannot expect a graceful transmit stop without link !!! */ 697 if (fep->link) { 698 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 699 udelay(10); 700 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 701 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 702 } 703 704 /* Whack a reset. We should wait for this. */ 705 writel(1, fep->hwp + FEC_ECNTRL); 706 udelay(10); 707 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 708 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 709 710 /* We have to keep ENET enabled to have MII interrupt stay working */ 711 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 712 writel(2, fep->hwp + FEC_ECNTRL); 713 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 714 } 715 } 716 717 718 static void 719 fec_timeout(struct net_device *ndev) 720 { 721 struct fec_enet_private *fep = netdev_priv(ndev); 722 723 ndev->stats.tx_errors++; 724 725 fep->delay_work.timeout = true; 726 schedule_delayed_work(&(fep->delay_work.delay_work), 0); 727 } 728 729 static void fec_enet_work(struct work_struct *work) 730 { 731 struct fec_enet_private *fep = 732 container_of(work, 733 struct fec_enet_private, 734 delay_work.delay_work.work); 735 736 if (fep->delay_work.timeout) { 737 fep->delay_work.timeout = false; 738 fec_restart(fep->netdev, fep->full_duplex); 739 netif_wake_queue(fep->netdev); 740 } 741 742 if (fep->delay_work.trig_tx) { 743 fep->delay_work.trig_tx = false; 744 writel(0, fep->hwp + FEC_X_DES_ACTIVE); 745 } 746 } 747 748 static void 749 fec_enet_tx(struct net_device *ndev) 750 { 751 struct fec_enet_private *fep; 752 struct bufdesc *bdp; 753 unsigned short status; 754 struct sk_buff *skb; 755 int index = 0; 756 757 fep = netdev_priv(ndev); 758 bdp = fep->dirty_tx; 759 760 /* get next bdp of dirty_tx */ 761 bdp = fec_enet_get_nextdesc(bdp, fep); 762 763 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { 764 765 /* current queue is empty */ 766 if (bdp == fep->cur_tx) 767 break; 768 769 if (fep->bufdesc_ex) 770 index = (struct bufdesc_ex *)bdp - 771 (struct bufdesc_ex *)fep->tx_bd_base; 772 else 773 index = bdp - fep->tx_bd_base; 774 775 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 776 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); 777 bdp->cbd_bufaddr = 0; 778 779 skb = fep->tx_skbuff[index]; 780 781 /* Check for errors. */ 782 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 783 BD_ENET_TX_RL | BD_ENET_TX_UN | 784 BD_ENET_TX_CSL)) { 785 ndev->stats.tx_errors++; 786 if (status & BD_ENET_TX_HB) /* No heartbeat */ 787 ndev->stats.tx_heartbeat_errors++; 788 if (status & BD_ENET_TX_LC) /* Late collision */ 789 ndev->stats.tx_window_errors++; 790 if (status & BD_ENET_TX_RL) /* Retrans limit */ 791 ndev->stats.tx_aborted_errors++; 792 if (status & BD_ENET_TX_UN) /* Underrun */ 793 ndev->stats.tx_fifo_errors++; 794 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 795 ndev->stats.tx_carrier_errors++; 796 } else { 797 ndev->stats.tx_packets++; 798 ndev->stats.tx_bytes += bdp->cbd_datlen; 799 } 800 801 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 802 fep->bufdesc_ex) { 803 struct skb_shared_hwtstamps shhwtstamps; 804 unsigned long flags; 805 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 806 807 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 808 spin_lock_irqsave(&fep->tmreg_lock, flags); 809 shhwtstamps.hwtstamp = ns_to_ktime( 810 timecounter_cyc2time(&fep->tc, ebdp->ts)); 811 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 812 skb_tstamp_tx(skb, &shhwtstamps); 813 } 814 815 if (status & BD_ENET_TX_READY) 816 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n"); 817 818 /* Deferred means some collisions occurred during transmit, 819 * but we eventually sent the packet OK. 820 */ 821 if (status & BD_ENET_TX_DEF) 822 ndev->stats.collisions++; 823 824 /* Free the sk buffer associated with this last transmit */ 825 dev_kfree_skb_any(skb); 826 fep->tx_skbuff[index] = NULL; 827 828 fep->dirty_tx = bdp; 829 830 /* Update pointer to next buffer descriptor to be transmitted */ 831 bdp = fec_enet_get_nextdesc(bdp, fep); 832 833 /* Since we have freed up a buffer, the ring is no longer full 834 */ 835 if (fep->dirty_tx != fep->cur_tx) { 836 if (netif_queue_stopped(ndev)) 837 netif_wake_queue(ndev); 838 } 839 } 840 return; 841 } 842 843 844 /* During a receive, the cur_rx points to the current incoming buffer. 845 * When we update through the ring, if the next incoming buffer has 846 * not been given to the system, we just set the empty indicator, 847 * effectively tossing the packet. 848 */ 849 static int 850 fec_enet_rx(struct net_device *ndev, int budget) 851 { 852 struct fec_enet_private *fep = netdev_priv(ndev); 853 const struct platform_device_id *id_entry = 854 platform_get_device_id(fep->pdev); 855 struct bufdesc *bdp; 856 unsigned short status; 857 struct sk_buff *skb; 858 ushort pkt_len; 859 __u8 *data; 860 int pkt_received = 0; 861 struct bufdesc_ex *ebdp = NULL; 862 bool vlan_packet_rcvd = false; 863 u16 vlan_tag; 864 865 #ifdef CONFIG_M532x 866 flush_cache_all(); 867 #endif 868 869 /* First, grab all of the stats for the incoming packet. 870 * These get messed up if we get called due to a busy condition. 871 */ 872 bdp = fep->cur_rx; 873 874 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { 875 876 if (pkt_received >= budget) 877 break; 878 pkt_received++; 879 880 /* Since we have allocated space to hold a complete frame, 881 * the last indicator should be set. 882 */ 883 if ((status & BD_ENET_RX_LAST) == 0) 884 netdev_err(ndev, "rcv is not +last\n"); 885 886 if (!fep->opened) 887 goto rx_processing_done; 888 889 /* Check for errors. */ 890 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 891 BD_ENET_RX_CR | BD_ENET_RX_OV)) { 892 ndev->stats.rx_errors++; 893 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { 894 /* Frame too long or too short. */ 895 ndev->stats.rx_length_errors++; 896 } 897 if (status & BD_ENET_RX_NO) /* Frame alignment */ 898 ndev->stats.rx_frame_errors++; 899 if (status & BD_ENET_RX_CR) /* CRC Error */ 900 ndev->stats.rx_crc_errors++; 901 if (status & BD_ENET_RX_OV) /* FIFO overrun */ 902 ndev->stats.rx_fifo_errors++; 903 } 904 905 /* Report late collisions as a frame error. 906 * On this error, the BD is closed, but we don't know what we 907 * have in the buffer. So, just drop this frame on the floor. 908 */ 909 if (status & BD_ENET_RX_CL) { 910 ndev->stats.rx_errors++; 911 ndev->stats.rx_frame_errors++; 912 goto rx_processing_done; 913 } 914 915 /* Process the incoming frame. */ 916 ndev->stats.rx_packets++; 917 pkt_len = bdp->cbd_datlen; 918 ndev->stats.rx_bytes += pkt_len; 919 data = (__u8*)__va(bdp->cbd_bufaddr); 920 921 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 922 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); 923 924 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 925 swap_buffer(data, pkt_len); 926 927 /* Extract the enhanced buffer descriptor */ 928 ebdp = NULL; 929 if (fep->bufdesc_ex) 930 ebdp = (struct bufdesc_ex *)bdp; 931 932 /* If this is a VLAN packet remove the VLAN Tag */ 933 vlan_packet_rcvd = false; 934 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 935 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) { 936 /* Push and remove the vlan tag */ 937 struct vlan_hdr *vlan_header = 938 (struct vlan_hdr *) (data + ETH_HLEN); 939 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 940 pkt_len -= VLAN_HLEN; 941 942 vlan_packet_rcvd = true; 943 } 944 945 /* This does 16 byte alignment, exactly what we need. 946 * The packet length includes FCS, but we don't want to 947 * include that when passing upstream as it messes up 948 * bridging applications. 949 */ 950 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); 951 952 if (unlikely(!skb)) { 953 ndev->stats.rx_dropped++; 954 } else { 955 int payload_offset = (2 * ETH_ALEN); 956 skb_reserve(skb, NET_IP_ALIGN); 957 skb_put(skb, pkt_len - 4); /* Make room */ 958 959 /* Extract the frame data without the VLAN header. */ 960 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN)); 961 if (vlan_packet_rcvd) 962 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN; 963 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN), 964 data + payload_offset, 965 pkt_len - 4 - (2 * ETH_ALEN)); 966 967 skb->protocol = eth_type_trans(skb, ndev); 968 969 /* Get receive timestamp from the skb */ 970 if (fep->hwts_rx_en && fep->bufdesc_ex) { 971 struct skb_shared_hwtstamps *shhwtstamps = 972 skb_hwtstamps(skb); 973 unsigned long flags; 974 975 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 976 977 spin_lock_irqsave(&fep->tmreg_lock, flags); 978 shhwtstamps->hwtstamp = ns_to_ktime( 979 timecounter_cyc2time(&fep->tc, ebdp->ts)); 980 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 981 } 982 983 if (fep->bufdesc_ex && 984 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 985 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) { 986 /* don't check it */ 987 skb->ip_summed = CHECKSUM_UNNECESSARY; 988 } else { 989 skb_checksum_none_assert(skb); 990 } 991 } 992 993 /* Handle received VLAN packets */ 994 if (vlan_packet_rcvd) 995 __vlan_hwaccel_put_tag(skb, 996 htons(ETH_P_8021Q), 997 vlan_tag); 998 999 napi_gro_receive(&fep->napi, skb); 1000 } 1001 1002 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data, 1003 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); 1004 rx_processing_done: 1005 /* Clear the status flags for this buffer */ 1006 status &= ~BD_ENET_RX_STATS; 1007 1008 /* Mark the buffer empty */ 1009 status |= BD_ENET_RX_EMPTY; 1010 bdp->cbd_sc = status; 1011 1012 if (fep->bufdesc_ex) { 1013 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1014 1015 ebdp->cbd_esc = BD_ENET_RX_INT; 1016 ebdp->cbd_prot = 0; 1017 ebdp->cbd_bdu = 0; 1018 } 1019 1020 /* Update BD pointer to next entry */ 1021 bdp = fec_enet_get_nextdesc(bdp, fep); 1022 1023 /* Doing this here will keep the FEC running while we process 1024 * incoming frames. On a heavily loaded network, we should be 1025 * able to keep up at the expense of system resources. 1026 */ 1027 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 1028 } 1029 fep->cur_rx = bdp; 1030 1031 return pkt_received; 1032 } 1033 1034 static irqreturn_t 1035 fec_enet_interrupt(int irq, void *dev_id) 1036 { 1037 struct net_device *ndev = dev_id; 1038 struct fec_enet_private *fep = netdev_priv(ndev); 1039 uint int_events; 1040 irqreturn_t ret = IRQ_NONE; 1041 1042 do { 1043 int_events = readl(fep->hwp + FEC_IEVENT); 1044 writel(int_events, fep->hwp + FEC_IEVENT); 1045 1046 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) { 1047 ret = IRQ_HANDLED; 1048 1049 /* Disable the RX interrupt */ 1050 if (napi_schedule_prep(&fep->napi)) { 1051 writel(FEC_RX_DISABLED_IMASK, 1052 fep->hwp + FEC_IMASK); 1053 __napi_schedule(&fep->napi); 1054 } 1055 } 1056 1057 if (int_events & FEC_ENET_MII) { 1058 ret = IRQ_HANDLED; 1059 complete(&fep->mdio_done); 1060 } 1061 } while (int_events); 1062 1063 return ret; 1064 } 1065 1066 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1067 { 1068 struct net_device *ndev = napi->dev; 1069 int pkts = fec_enet_rx(ndev, budget); 1070 struct fec_enet_private *fep = netdev_priv(ndev); 1071 1072 fec_enet_tx(ndev); 1073 1074 if (pkts < budget) { 1075 napi_complete(napi); 1076 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1077 } 1078 return pkts; 1079 } 1080 1081 /* ------------------------------------------------------------------------- */ 1082 static void fec_get_mac(struct net_device *ndev) 1083 { 1084 struct fec_enet_private *fep = netdev_priv(ndev); 1085 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1086 unsigned char *iap, tmpaddr[ETH_ALEN]; 1087 1088 /* 1089 * try to get mac address in following order: 1090 * 1091 * 1) module parameter via kernel command line in form 1092 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1093 */ 1094 iap = macaddr; 1095 1096 /* 1097 * 2) from device tree data 1098 */ 1099 if (!is_valid_ether_addr(iap)) { 1100 struct device_node *np = fep->pdev->dev.of_node; 1101 if (np) { 1102 const char *mac = of_get_mac_address(np); 1103 if (mac) 1104 iap = (unsigned char *) mac; 1105 } 1106 } 1107 1108 /* 1109 * 3) from flash or fuse (via platform data) 1110 */ 1111 if (!is_valid_ether_addr(iap)) { 1112 #ifdef CONFIG_M5272 1113 if (FEC_FLASHMAC) 1114 iap = (unsigned char *)FEC_FLASHMAC; 1115 #else 1116 if (pdata) 1117 iap = (unsigned char *)&pdata->mac; 1118 #endif 1119 } 1120 1121 /* 1122 * 4) FEC mac registers set by bootloader 1123 */ 1124 if (!is_valid_ether_addr(iap)) { 1125 *((__be32 *) &tmpaddr[0]) = 1126 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1127 *((__be16 *) &tmpaddr[4]) = 1128 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1129 iap = &tmpaddr[0]; 1130 } 1131 1132 /* 1133 * 5) random mac address 1134 */ 1135 if (!is_valid_ether_addr(iap)) { 1136 /* Report it and use a random ethernet address instead */ 1137 netdev_err(ndev, "Invalid MAC address: %pM\n", iap); 1138 eth_hw_addr_random(ndev); 1139 netdev_info(ndev, "Using random MAC address: %pM\n", 1140 ndev->dev_addr); 1141 return; 1142 } 1143 1144 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1145 1146 /* Adjust MAC if using macaddr */ 1147 if (iap == macaddr) 1148 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1149 } 1150 1151 /* ------------------------------------------------------------------------- */ 1152 1153 /* 1154 * Phy section 1155 */ 1156 static void fec_enet_adjust_link(struct net_device *ndev) 1157 { 1158 struct fec_enet_private *fep = netdev_priv(ndev); 1159 struct phy_device *phy_dev = fep->phy_dev; 1160 int status_change = 0; 1161 1162 /* Prevent a state halted on mii error */ 1163 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 1164 phy_dev->state = PHY_RESUMING; 1165 return; 1166 } 1167 1168 if (phy_dev->link) { 1169 if (!fep->link) { 1170 fep->link = phy_dev->link; 1171 status_change = 1; 1172 } 1173 1174 if (fep->full_duplex != phy_dev->duplex) 1175 status_change = 1; 1176 1177 if (phy_dev->speed != fep->speed) { 1178 fep->speed = phy_dev->speed; 1179 status_change = 1; 1180 } 1181 1182 /* if any of the above changed restart the FEC */ 1183 if (status_change) 1184 fec_restart(ndev, phy_dev->duplex); 1185 } else { 1186 if (fep->link) { 1187 fec_stop(ndev); 1188 fep->link = phy_dev->link; 1189 status_change = 1; 1190 } 1191 } 1192 1193 if (status_change) 1194 phy_print_status(phy_dev); 1195 } 1196 1197 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1198 { 1199 struct fec_enet_private *fep = bus->priv; 1200 unsigned long time_left; 1201 1202 fep->mii_timeout = 0; 1203 init_completion(&fep->mdio_done); 1204 1205 /* start a read op */ 1206 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 1207 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1208 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1209 1210 /* wait for end of transfer */ 1211 time_left = wait_for_completion_timeout(&fep->mdio_done, 1212 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1213 if (time_left == 0) { 1214 fep->mii_timeout = 1; 1215 netdev_err(fep->netdev, "MDIO read timeout\n"); 1216 return -ETIMEDOUT; 1217 } 1218 1219 /* return value */ 1220 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1221 } 1222 1223 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1224 u16 value) 1225 { 1226 struct fec_enet_private *fep = bus->priv; 1227 unsigned long time_left; 1228 1229 fep->mii_timeout = 0; 1230 init_completion(&fep->mdio_done); 1231 1232 /* start a write op */ 1233 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 1234 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1235 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1236 fep->hwp + FEC_MII_DATA); 1237 1238 /* wait for end of transfer */ 1239 time_left = wait_for_completion_timeout(&fep->mdio_done, 1240 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1241 if (time_left == 0) { 1242 fep->mii_timeout = 1; 1243 netdev_err(fep->netdev, "MDIO write timeout\n"); 1244 return -ETIMEDOUT; 1245 } 1246 1247 return 0; 1248 } 1249 1250 static int fec_enet_mdio_reset(struct mii_bus *bus) 1251 { 1252 return 0; 1253 } 1254 1255 static int fec_enet_mii_probe(struct net_device *ndev) 1256 { 1257 struct fec_enet_private *fep = netdev_priv(ndev); 1258 const struct platform_device_id *id_entry = 1259 platform_get_device_id(fep->pdev); 1260 struct phy_device *phy_dev = NULL; 1261 char mdio_bus_id[MII_BUS_ID_SIZE]; 1262 char phy_name[MII_BUS_ID_SIZE + 3]; 1263 int phy_id; 1264 int dev_id = fep->dev_id; 1265 1266 fep->phy_dev = NULL; 1267 1268 /* check for attached phy */ 1269 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1270 if ((fep->mii_bus->phy_mask & (1 << phy_id))) 1271 continue; 1272 if (fep->mii_bus->phy_map[phy_id] == NULL) 1273 continue; 1274 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) 1275 continue; 1276 if (dev_id--) 1277 continue; 1278 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1279 break; 1280 } 1281 1282 if (phy_id >= PHY_MAX_ADDR) { 1283 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1284 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 1285 phy_id = 0; 1286 } 1287 1288 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); 1289 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 1290 fep->phy_interface); 1291 if (IS_ERR(phy_dev)) { 1292 netdev_err(ndev, "could not attach to PHY\n"); 1293 return PTR_ERR(phy_dev); 1294 } 1295 1296 /* mask with MAC supported features */ 1297 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) { 1298 phy_dev->supported &= PHY_GBIT_FEATURES; 1299 #if !defined(CONFIG_M5272) 1300 phy_dev->supported |= SUPPORTED_Pause; 1301 #endif 1302 } 1303 else 1304 phy_dev->supported &= PHY_BASIC_FEATURES; 1305 1306 phy_dev->advertising = phy_dev->supported; 1307 1308 fep->phy_dev = phy_dev; 1309 fep->link = 0; 1310 fep->full_duplex = 0; 1311 1312 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 1313 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), 1314 fep->phy_dev->irq); 1315 1316 return 0; 1317 } 1318 1319 static int fec_enet_mii_init(struct platform_device *pdev) 1320 { 1321 static struct mii_bus *fec0_mii_bus; 1322 struct net_device *ndev = platform_get_drvdata(pdev); 1323 struct fec_enet_private *fep = netdev_priv(ndev); 1324 const struct platform_device_id *id_entry = 1325 platform_get_device_id(fep->pdev); 1326 int err = -ENXIO, i; 1327 1328 /* 1329 * The dual fec interfaces are not equivalent with enet-mac. 1330 * Here are the differences: 1331 * 1332 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1333 * - fec0 acts as the 1588 time master while fec1 is slave 1334 * - external phys can only be configured by fec0 1335 * 1336 * That is to say fec1 can not work independently. It only works 1337 * when fec0 is working. The reason behind this design is that the 1338 * second interface is added primarily for Switch mode. 1339 * 1340 * Because of the last point above, both phys are attached on fec0 1341 * mdio interface in board design, and need to be configured by 1342 * fec0 mii_bus. 1343 */ 1344 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { 1345 /* fec1 uses fec0 mii_bus */ 1346 if (mii_cnt && fec0_mii_bus) { 1347 fep->mii_bus = fec0_mii_bus; 1348 mii_cnt++; 1349 return 0; 1350 } 1351 return -ENOENT; 1352 } 1353 1354 fep->mii_timeout = 0; 1355 1356 /* 1357 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 1358 * 1359 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 1360 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 1361 * Reference Manual has an error on this, and gets fixed on i.MX6Q 1362 * document. 1363 */ 1364 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000); 1365 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1366 fep->phy_speed--; 1367 fep->phy_speed <<= 1; 1368 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1369 1370 fep->mii_bus = mdiobus_alloc(); 1371 if (fep->mii_bus == NULL) { 1372 err = -ENOMEM; 1373 goto err_out; 1374 } 1375 1376 fep->mii_bus->name = "fec_enet_mii_bus"; 1377 fep->mii_bus->read = fec_enet_mdio_read; 1378 fep->mii_bus->write = fec_enet_mdio_write; 1379 fep->mii_bus->reset = fec_enet_mdio_reset; 1380 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1381 pdev->name, fep->dev_id + 1); 1382 fep->mii_bus->priv = fep; 1383 fep->mii_bus->parent = &pdev->dev; 1384 1385 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 1386 if (!fep->mii_bus->irq) { 1387 err = -ENOMEM; 1388 goto err_out_free_mdiobus; 1389 } 1390 1391 for (i = 0; i < PHY_MAX_ADDR; i++) 1392 fep->mii_bus->irq[i] = PHY_POLL; 1393 1394 if (mdiobus_register(fep->mii_bus)) 1395 goto err_out_free_mdio_irq; 1396 1397 mii_cnt++; 1398 1399 /* save fec0 mii_bus */ 1400 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1401 fec0_mii_bus = fep->mii_bus; 1402 1403 return 0; 1404 1405 err_out_free_mdio_irq: 1406 kfree(fep->mii_bus->irq); 1407 err_out_free_mdiobus: 1408 mdiobus_free(fep->mii_bus); 1409 err_out: 1410 return err; 1411 } 1412 1413 static void fec_enet_mii_remove(struct fec_enet_private *fep) 1414 { 1415 if (--mii_cnt == 0) { 1416 mdiobus_unregister(fep->mii_bus); 1417 kfree(fep->mii_bus->irq); 1418 mdiobus_free(fep->mii_bus); 1419 } 1420 } 1421 1422 static int fec_enet_get_settings(struct net_device *ndev, 1423 struct ethtool_cmd *cmd) 1424 { 1425 struct fec_enet_private *fep = netdev_priv(ndev); 1426 struct phy_device *phydev = fep->phy_dev; 1427 1428 if (!phydev) 1429 return -ENODEV; 1430 1431 return phy_ethtool_gset(phydev, cmd); 1432 } 1433 1434 static int fec_enet_set_settings(struct net_device *ndev, 1435 struct ethtool_cmd *cmd) 1436 { 1437 struct fec_enet_private *fep = netdev_priv(ndev); 1438 struct phy_device *phydev = fep->phy_dev; 1439 1440 if (!phydev) 1441 return -ENODEV; 1442 1443 return phy_ethtool_sset(phydev, cmd); 1444 } 1445 1446 static void fec_enet_get_drvinfo(struct net_device *ndev, 1447 struct ethtool_drvinfo *info) 1448 { 1449 struct fec_enet_private *fep = netdev_priv(ndev); 1450 1451 strlcpy(info->driver, fep->pdev->dev.driver->name, 1452 sizeof(info->driver)); 1453 strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); 1454 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 1455 } 1456 1457 static int fec_enet_get_ts_info(struct net_device *ndev, 1458 struct ethtool_ts_info *info) 1459 { 1460 struct fec_enet_private *fep = netdev_priv(ndev); 1461 1462 if (fep->bufdesc_ex) { 1463 1464 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1465 SOF_TIMESTAMPING_RX_SOFTWARE | 1466 SOF_TIMESTAMPING_SOFTWARE | 1467 SOF_TIMESTAMPING_TX_HARDWARE | 1468 SOF_TIMESTAMPING_RX_HARDWARE | 1469 SOF_TIMESTAMPING_RAW_HARDWARE; 1470 if (fep->ptp_clock) 1471 info->phc_index = ptp_clock_index(fep->ptp_clock); 1472 else 1473 info->phc_index = -1; 1474 1475 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 1476 (1 << HWTSTAMP_TX_ON); 1477 1478 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 1479 (1 << HWTSTAMP_FILTER_ALL); 1480 return 0; 1481 } else { 1482 return ethtool_op_get_ts_info(ndev, info); 1483 } 1484 } 1485 1486 #if !defined(CONFIG_M5272) 1487 1488 static void fec_enet_get_pauseparam(struct net_device *ndev, 1489 struct ethtool_pauseparam *pause) 1490 { 1491 struct fec_enet_private *fep = netdev_priv(ndev); 1492 1493 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 1494 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 1495 pause->rx_pause = pause->tx_pause; 1496 } 1497 1498 static int fec_enet_set_pauseparam(struct net_device *ndev, 1499 struct ethtool_pauseparam *pause) 1500 { 1501 struct fec_enet_private *fep = netdev_priv(ndev); 1502 1503 if (pause->tx_pause != pause->rx_pause) { 1504 netdev_info(ndev, 1505 "hardware only support enable/disable both tx and rx"); 1506 return -EINVAL; 1507 } 1508 1509 fep->pause_flag = 0; 1510 1511 /* tx pause must be same as rx pause */ 1512 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 1513 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 1514 1515 if (pause->rx_pause || pause->autoneg) { 1516 fep->phy_dev->supported |= ADVERTISED_Pause; 1517 fep->phy_dev->advertising |= ADVERTISED_Pause; 1518 } else { 1519 fep->phy_dev->supported &= ~ADVERTISED_Pause; 1520 fep->phy_dev->advertising &= ~ADVERTISED_Pause; 1521 } 1522 1523 if (pause->autoneg) { 1524 if (netif_running(ndev)) 1525 fec_stop(ndev); 1526 phy_start_aneg(fep->phy_dev); 1527 } 1528 if (netif_running(ndev)) 1529 fec_restart(ndev, 0); 1530 1531 return 0; 1532 } 1533 1534 static const struct fec_stat { 1535 char name[ETH_GSTRING_LEN]; 1536 u16 offset; 1537 } fec_stats[] = { 1538 /* RMON TX */ 1539 { "tx_dropped", RMON_T_DROP }, 1540 { "tx_packets", RMON_T_PACKETS }, 1541 { "tx_broadcast", RMON_T_BC_PKT }, 1542 { "tx_multicast", RMON_T_MC_PKT }, 1543 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 1544 { "tx_undersize", RMON_T_UNDERSIZE }, 1545 { "tx_oversize", RMON_T_OVERSIZE }, 1546 { "tx_fragment", RMON_T_FRAG }, 1547 { "tx_jabber", RMON_T_JAB }, 1548 { "tx_collision", RMON_T_COL }, 1549 { "tx_64byte", RMON_T_P64 }, 1550 { "tx_65to127byte", RMON_T_P65TO127 }, 1551 { "tx_128to255byte", RMON_T_P128TO255 }, 1552 { "tx_256to511byte", RMON_T_P256TO511 }, 1553 { "tx_512to1023byte", RMON_T_P512TO1023 }, 1554 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 1555 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 1556 { "tx_octets", RMON_T_OCTETS }, 1557 1558 /* IEEE TX */ 1559 { "IEEE_tx_drop", IEEE_T_DROP }, 1560 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 1561 { "IEEE_tx_1col", IEEE_T_1COL }, 1562 { "IEEE_tx_mcol", IEEE_T_MCOL }, 1563 { "IEEE_tx_def", IEEE_T_DEF }, 1564 { "IEEE_tx_lcol", IEEE_T_LCOL }, 1565 { "IEEE_tx_excol", IEEE_T_EXCOL }, 1566 { "IEEE_tx_macerr", IEEE_T_MACERR }, 1567 { "IEEE_tx_cserr", IEEE_T_CSERR }, 1568 { "IEEE_tx_sqe", IEEE_T_SQE }, 1569 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 1570 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 1571 1572 /* RMON RX */ 1573 { "rx_packets", RMON_R_PACKETS }, 1574 { "rx_broadcast", RMON_R_BC_PKT }, 1575 { "rx_multicast", RMON_R_MC_PKT }, 1576 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 1577 { "rx_undersize", RMON_R_UNDERSIZE }, 1578 { "rx_oversize", RMON_R_OVERSIZE }, 1579 { "rx_fragment", RMON_R_FRAG }, 1580 { "rx_jabber", RMON_R_JAB }, 1581 { "rx_64byte", RMON_R_P64 }, 1582 { "rx_65to127byte", RMON_R_P65TO127 }, 1583 { "rx_128to255byte", RMON_R_P128TO255 }, 1584 { "rx_256to511byte", RMON_R_P256TO511 }, 1585 { "rx_512to1023byte", RMON_R_P512TO1023 }, 1586 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 1587 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 1588 { "rx_octets", RMON_R_OCTETS }, 1589 1590 /* IEEE RX */ 1591 { "IEEE_rx_drop", IEEE_R_DROP }, 1592 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 1593 { "IEEE_rx_crc", IEEE_R_CRC }, 1594 { "IEEE_rx_align", IEEE_R_ALIGN }, 1595 { "IEEE_rx_macerr", IEEE_R_MACERR }, 1596 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 1597 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 1598 }; 1599 1600 static void fec_enet_get_ethtool_stats(struct net_device *dev, 1601 struct ethtool_stats *stats, u64 *data) 1602 { 1603 struct fec_enet_private *fep = netdev_priv(dev); 1604 int i; 1605 1606 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 1607 data[i] = readl(fep->hwp + fec_stats[i].offset); 1608 } 1609 1610 static void fec_enet_get_strings(struct net_device *netdev, 1611 u32 stringset, u8 *data) 1612 { 1613 int i; 1614 switch (stringset) { 1615 case ETH_SS_STATS: 1616 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 1617 memcpy(data + i * ETH_GSTRING_LEN, 1618 fec_stats[i].name, ETH_GSTRING_LEN); 1619 break; 1620 } 1621 } 1622 1623 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 1624 { 1625 switch (sset) { 1626 case ETH_SS_STATS: 1627 return ARRAY_SIZE(fec_stats); 1628 default: 1629 return -EOPNOTSUPP; 1630 } 1631 } 1632 #endif /* !defined(CONFIG_M5272) */ 1633 1634 static int fec_enet_nway_reset(struct net_device *dev) 1635 { 1636 struct fec_enet_private *fep = netdev_priv(dev); 1637 struct phy_device *phydev = fep->phy_dev; 1638 1639 if (!phydev) 1640 return -ENODEV; 1641 1642 return genphy_restart_aneg(phydev); 1643 } 1644 1645 static const struct ethtool_ops fec_enet_ethtool_ops = { 1646 #if !defined(CONFIG_M5272) 1647 .get_pauseparam = fec_enet_get_pauseparam, 1648 .set_pauseparam = fec_enet_set_pauseparam, 1649 #endif 1650 .get_settings = fec_enet_get_settings, 1651 .set_settings = fec_enet_set_settings, 1652 .get_drvinfo = fec_enet_get_drvinfo, 1653 .get_link = ethtool_op_get_link, 1654 .get_ts_info = fec_enet_get_ts_info, 1655 .nway_reset = fec_enet_nway_reset, 1656 #ifndef CONFIG_M5272 1657 .get_ethtool_stats = fec_enet_get_ethtool_stats, 1658 .get_strings = fec_enet_get_strings, 1659 .get_sset_count = fec_enet_get_sset_count, 1660 #endif 1661 }; 1662 1663 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 1664 { 1665 struct fec_enet_private *fep = netdev_priv(ndev); 1666 struct phy_device *phydev = fep->phy_dev; 1667 1668 if (!netif_running(ndev)) 1669 return -EINVAL; 1670 1671 if (!phydev) 1672 return -ENODEV; 1673 1674 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex) 1675 return fec_ptp_ioctl(ndev, rq, cmd); 1676 1677 return phy_mii_ioctl(phydev, rq, cmd); 1678 } 1679 1680 static void fec_enet_free_buffers(struct net_device *ndev) 1681 { 1682 struct fec_enet_private *fep = netdev_priv(ndev); 1683 unsigned int i; 1684 struct sk_buff *skb; 1685 struct bufdesc *bdp; 1686 1687 bdp = fep->rx_bd_base; 1688 for (i = 0; i < fep->rx_ring_size; i++) { 1689 skb = fep->rx_skbuff[i]; 1690 1691 if (bdp->cbd_bufaddr) 1692 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 1693 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1694 if (skb) 1695 dev_kfree_skb(skb); 1696 bdp = fec_enet_get_nextdesc(bdp, fep); 1697 } 1698 1699 bdp = fep->tx_bd_base; 1700 for (i = 0; i < fep->tx_ring_size; i++) 1701 kfree(fep->tx_bounce[i]); 1702 } 1703 1704 static int fec_enet_alloc_buffers(struct net_device *ndev) 1705 { 1706 struct fec_enet_private *fep = netdev_priv(ndev); 1707 unsigned int i; 1708 struct sk_buff *skb; 1709 struct bufdesc *bdp; 1710 1711 bdp = fep->rx_bd_base; 1712 for (i = 0; i < fep->rx_ring_size; i++) { 1713 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1714 if (!skb) { 1715 fec_enet_free_buffers(ndev); 1716 return -ENOMEM; 1717 } 1718 fep->rx_skbuff[i] = skb; 1719 1720 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, 1721 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1722 bdp->cbd_sc = BD_ENET_RX_EMPTY; 1723 1724 if (fep->bufdesc_ex) { 1725 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1726 ebdp->cbd_esc = BD_ENET_RX_INT; 1727 } 1728 1729 bdp = fec_enet_get_nextdesc(bdp, fep); 1730 } 1731 1732 /* Set the last buffer to wrap. */ 1733 bdp = fec_enet_get_prevdesc(bdp, fep); 1734 bdp->cbd_sc |= BD_SC_WRAP; 1735 1736 bdp = fep->tx_bd_base; 1737 for (i = 0; i < fep->tx_ring_size; i++) { 1738 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 1739 1740 bdp->cbd_sc = 0; 1741 bdp->cbd_bufaddr = 0; 1742 1743 if (fep->bufdesc_ex) { 1744 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1745 ebdp->cbd_esc = BD_ENET_TX_INT; 1746 } 1747 1748 bdp = fec_enet_get_nextdesc(bdp, fep); 1749 } 1750 1751 /* Set the last buffer to wrap. */ 1752 bdp = fec_enet_get_prevdesc(bdp, fep); 1753 bdp->cbd_sc |= BD_SC_WRAP; 1754 1755 return 0; 1756 } 1757 1758 static int 1759 fec_enet_open(struct net_device *ndev) 1760 { 1761 struct fec_enet_private *fep = netdev_priv(ndev); 1762 int ret; 1763 1764 napi_enable(&fep->napi); 1765 1766 /* I should reset the ring buffers here, but I don't yet know 1767 * a simple way to do that. 1768 */ 1769 1770 ret = fec_enet_alloc_buffers(ndev); 1771 if (ret) 1772 return ret; 1773 1774 /* Probe and connect to PHY when open the interface */ 1775 ret = fec_enet_mii_probe(ndev); 1776 if (ret) { 1777 fec_enet_free_buffers(ndev); 1778 return ret; 1779 } 1780 phy_start(fep->phy_dev); 1781 netif_start_queue(ndev); 1782 fep->opened = 1; 1783 return 0; 1784 } 1785 1786 static int 1787 fec_enet_close(struct net_device *ndev) 1788 { 1789 struct fec_enet_private *fep = netdev_priv(ndev); 1790 1791 /* Don't know what to do yet. */ 1792 napi_disable(&fep->napi); 1793 fep->opened = 0; 1794 netif_stop_queue(ndev); 1795 fec_stop(ndev); 1796 1797 if (fep->phy_dev) { 1798 phy_stop(fep->phy_dev); 1799 phy_disconnect(fep->phy_dev); 1800 } 1801 1802 fec_enet_free_buffers(ndev); 1803 1804 return 0; 1805 } 1806 1807 /* Set or clear the multicast filter for this adaptor. 1808 * Skeleton taken from sunlance driver. 1809 * The CPM Ethernet implementation allows Multicast as well as individual 1810 * MAC address filtering. Some of the drivers check to make sure it is 1811 * a group multicast address, and discard those that are not. I guess I 1812 * will do the same for now, but just remove the test if you want 1813 * individual filtering as well (do the upper net layers want or support 1814 * this kind of feature?). 1815 */ 1816 1817 #define HASH_BITS 6 /* #bits in hash */ 1818 #define CRC32_POLY 0xEDB88320 1819 1820 static void set_multicast_list(struct net_device *ndev) 1821 { 1822 struct fec_enet_private *fep = netdev_priv(ndev); 1823 struct netdev_hw_addr *ha; 1824 unsigned int i, bit, data, crc, tmp; 1825 unsigned char hash; 1826 1827 if (ndev->flags & IFF_PROMISC) { 1828 tmp = readl(fep->hwp + FEC_R_CNTRL); 1829 tmp |= 0x8; 1830 writel(tmp, fep->hwp + FEC_R_CNTRL); 1831 return; 1832 } 1833 1834 tmp = readl(fep->hwp + FEC_R_CNTRL); 1835 tmp &= ~0x8; 1836 writel(tmp, fep->hwp + FEC_R_CNTRL); 1837 1838 if (ndev->flags & IFF_ALLMULTI) { 1839 /* Catch all multicast addresses, so set the 1840 * filter to all 1's 1841 */ 1842 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1843 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1844 1845 return; 1846 } 1847 1848 /* Clear filter and add the addresses in hash register 1849 */ 1850 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1851 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1852 1853 netdev_for_each_mc_addr(ha, ndev) { 1854 /* calculate crc32 value of mac address */ 1855 crc = 0xffffffff; 1856 1857 for (i = 0; i < ndev->addr_len; i++) { 1858 data = ha->addr[i]; 1859 for (bit = 0; bit < 8; bit++, data >>= 1) { 1860 crc = (crc >> 1) ^ 1861 (((crc ^ data) & 1) ? CRC32_POLY : 0); 1862 } 1863 } 1864 1865 /* only upper 6 bits (HASH_BITS) are used 1866 * which point to specific bit in he hash registers 1867 */ 1868 hash = (crc >> (32 - HASH_BITS)) & 0x3f; 1869 1870 if (hash > 31) { 1871 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1872 tmp |= 1 << (hash - 32); 1873 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1874 } else { 1875 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1876 tmp |= 1 << hash; 1877 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1878 } 1879 } 1880 } 1881 1882 /* Set a MAC change in hardware. */ 1883 static int 1884 fec_set_mac_address(struct net_device *ndev, void *p) 1885 { 1886 struct fec_enet_private *fep = netdev_priv(ndev); 1887 struct sockaddr *addr = p; 1888 1889 if (!is_valid_ether_addr(addr->sa_data)) 1890 return -EADDRNOTAVAIL; 1891 1892 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 1893 1894 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 1895 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 1896 fep->hwp + FEC_ADDR_LOW); 1897 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 1898 fep->hwp + FEC_ADDR_HIGH); 1899 return 0; 1900 } 1901 1902 #ifdef CONFIG_NET_POLL_CONTROLLER 1903 /** 1904 * fec_poll_controller - FEC Poll controller function 1905 * @dev: The FEC network adapter 1906 * 1907 * Polled functionality used by netconsole and others in non interrupt mode 1908 * 1909 */ 1910 static void fec_poll_controller(struct net_device *dev) 1911 { 1912 int i; 1913 struct fec_enet_private *fep = netdev_priv(dev); 1914 1915 for (i = 0; i < FEC_IRQ_NUM; i++) { 1916 if (fep->irq[i] > 0) { 1917 disable_irq(fep->irq[i]); 1918 fec_enet_interrupt(fep->irq[i], dev); 1919 enable_irq(fep->irq[i]); 1920 } 1921 } 1922 } 1923 #endif 1924 1925 static int fec_set_features(struct net_device *netdev, 1926 netdev_features_t features) 1927 { 1928 struct fec_enet_private *fep = netdev_priv(netdev); 1929 netdev_features_t changed = features ^ netdev->features; 1930 1931 netdev->features = features; 1932 1933 /* Receive checksum has been changed */ 1934 if (changed & NETIF_F_RXCSUM) { 1935 if (features & NETIF_F_RXCSUM) 1936 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 1937 else 1938 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 1939 1940 if (netif_running(netdev)) { 1941 fec_stop(netdev); 1942 fec_restart(netdev, fep->phy_dev->duplex); 1943 netif_wake_queue(netdev); 1944 } else { 1945 fec_restart(netdev, fep->phy_dev->duplex); 1946 } 1947 } 1948 1949 return 0; 1950 } 1951 1952 static const struct net_device_ops fec_netdev_ops = { 1953 .ndo_open = fec_enet_open, 1954 .ndo_stop = fec_enet_close, 1955 .ndo_start_xmit = fec_enet_start_xmit, 1956 .ndo_set_rx_mode = set_multicast_list, 1957 .ndo_change_mtu = eth_change_mtu, 1958 .ndo_validate_addr = eth_validate_addr, 1959 .ndo_tx_timeout = fec_timeout, 1960 .ndo_set_mac_address = fec_set_mac_address, 1961 .ndo_do_ioctl = fec_enet_ioctl, 1962 #ifdef CONFIG_NET_POLL_CONTROLLER 1963 .ndo_poll_controller = fec_poll_controller, 1964 #endif 1965 .ndo_set_features = fec_set_features, 1966 }; 1967 1968 /* 1969 * XXX: We need to clean up on failure exits here. 1970 * 1971 */ 1972 static int fec_enet_init(struct net_device *ndev) 1973 { 1974 struct fec_enet_private *fep = netdev_priv(ndev); 1975 const struct platform_device_id *id_entry = 1976 platform_get_device_id(fep->pdev); 1977 struct bufdesc *cbd_base; 1978 1979 /* Allocate memory for buffer descriptors. */ 1980 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, 1981 GFP_KERNEL); 1982 if (!cbd_base) 1983 return -ENOMEM; 1984 1985 memset(cbd_base, 0, PAGE_SIZE); 1986 1987 fep->netdev = ndev; 1988 1989 /* Get the Ethernet address */ 1990 fec_get_mac(ndev); 1991 1992 /* init the tx & rx ring size */ 1993 fep->tx_ring_size = TX_RING_SIZE; 1994 fep->rx_ring_size = RX_RING_SIZE; 1995 1996 /* Set receive and transmit descriptor base. */ 1997 fep->rx_bd_base = cbd_base; 1998 if (fep->bufdesc_ex) 1999 fep->tx_bd_base = (struct bufdesc *) 2000 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size); 2001 else 2002 fep->tx_bd_base = cbd_base + fep->rx_ring_size; 2003 2004 /* The FEC Ethernet specific entries in the device structure */ 2005 ndev->watchdog_timeo = TX_TIMEOUT; 2006 ndev->netdev_ops = &fec_netdev_ops; 2007 ndev->ethtool_ops = &fec_enet_ethtool_ops; 2008 2009 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 2010 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 2011 2012 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) { 2013 /* enable hw VLAN support */ 2014 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 2015 ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 2016 } 2017 2018 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) { 2019 /* enable hw accelerator */ 2020 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 2021 | NETIF_F_RXCSUM); 2022 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 2023 | NETIF_F_RXCSUM); 2024 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 2025 } 2026 2027 fec_restart(ndev, 0); 2028 2029 return 0; 2030 } 2031 2032 #ifdef CONFIG_OF 2033 static void fec_reset_phy(struct platform_device *pdev) 2034 { 2035 int err, phy_reset; 2036 int msec = 1; 2037 struct device_node *np = pdev->dev.of_node; 2038 2039 if (!np) 2040 return; 2041 2042 of_property_read_u32(np, "phy-reset-duration", &msec); 2043 /* A sane reset duration should not be longer than 1s */ 2044 if (msec > 1000) 2045 msec = 1; 2046 2047 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 2048 if (!gpio_is_valid(phy_reset)) 2049 return; 2050 2051 err = devm_gpio_request_one(&pdev->dev, phy_reset, 2052 GPIOF_OUT_INIT_LOW, "phy-reset"); 2053 if (err) { 2054 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 2055 return; 2056 } 2057 msleep(msec); 2058 gpio_set_value(phy_reset, 1); 2059 } 2060 #else /* CONFIG_OF */ 2061 static void fec_reset_phy(struct platform_device *pdev) 2062 { 2063 /* 2064 * In case of platform probe, the reset has been done 2065 * by machine code. 2066 */ 2067 } 2068 #endif /* CONFIG_OF */ 2069 2070 static int 2071 fec_probe(struct platform_device *pdev) 2072 { 2073 struct fec_enet_private *fep; 2074 struct fec_platform_data *pdata; 2075 struct net_device *ndev; 2076 int i, irq, ret = 0; 2077 struct resource *r; 2078 const struct of_device_id *of_id; 2079 static int dev_id; 2080 2081 of_id = of_match_device(fec_dt_ids, &pdev->dev); 2082 if (of_id) 2083 pdev->id_entry = of_id->data; 2084 2085 /* Init network device */ 2086 ndev = alloc_etherdev(sizeof(struct fec_enet_private)); 2087 if (!ndev) 2088 return -ENOMEM; 2089 2090 SET_NETDEV_DEV(ndev, &pdev->dev); 2091 2092 /* setup board info structure */ 2093 fep = netdev_priv(ndev); 2094 2095 #if !defined(CONFIG_M5272) 2096 /* default enable pause frame auto negotiation */ 2097 if (pdev->id_entry && 2098 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT)) 2099 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 2100 #endif 2101 2102 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2103 fep->hwp = devm_ioremap_resource(&pdev->dev, r); 2104 if (IS_ERR(fep->hwp)) { 2105 ret = PTR_ERR(fep->hwp); 2106 goto failed_ioremap; 2107 } 2108 2109 fep->pdev = pdev; 2110 fep->dev_id = dev_id++; 2111 2112 fep->bufdesc_ex = 0; 2113 2114 platform_set_drvdata(pdev, ndev); 2115 2116 ret = of_get_phy_mode(pdev->dev.of_node); 2117 if (ret < 0) { 2118 pdata = dev_get_platdata(&pdev->dev); 2119 if (pdata) 2120 fep->phy_interface = pdata->phy; 2121 else 2122 fep->phy_interface = PHY_INTERFACE_MODE_MII; 2123 } else { 2124 fep->phy_interface = ret; 2125 } 2126 2127 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2128 if (IS_ERR(fep->clk_ipg)) { 2129 ret = PTR_ERR(fep->clk_ipg); 2130 goto failed_clk; 2131 } 2132 2133 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 2134 if (IS_ERR(fep->clk_ahb)) { 2135 ret = PTR_ERR(fep->clk_ahb); 2136 goto failed_clk; 2137 } 2138 2139 /* enet_out is optional, depends on board */ 2140 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 2141 if (IS_ERR(fep->clk_enet_out)) 2142 fep->clk_enet_out = NULL; 2143 2144 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 2145 fep->bufdesc_ex = 2146 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX; 2147 if (IS_ERR(fep->clk_ptp)) { 2148 fep->clk_ptp = NULL; 2149 fep->bufdesc_ex = 0; 2150 } 2151 2152 ret = clk_prepare_enable(fep->clk_ahb); 2153 if (ret) 2154 goto failed_clk; 2155 2156 ret = clk_prepare_enable(fep->clk_ipg); 2157 if (ret) 2158 goto failed_clk_ipg; 2159 2160 if (fep->clk_enet_out) { 2161 ret = clk_prepare_enable(fep->clk_enet_out); 2162 if (ret) 2163 goto failed_clk_enet_out; 2164 } 2165 2166 if (fep->clk_ptp) { 2167 ret = clk_prepare_enable(fep->clk_ptp); 2168 if (ret) 2169 goto failed_clk_ptp; 2170 } 2171 2172 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); 2173 if (!IS_ERR(fep->reg_phy)) { 2174 ret = regulator_enable(fep->reg_phy); 2175 if (ret) { 2176 dev_err(&pdev->dev, 2177 "Failed to enable phy regulator: %d\n", ret); 2178 goto failed_regulator; 2179 } 2180 } else { 2181 fep->reg_phy = NULL; 2182 } 2183 2184 fec_reset_phy(pdev); 2185 2186 if (fep->bufdesc_ex) 2187 fec_ptp_init(pdev); 2188 2189 ret = fec_enet_init(ndev); 2190 if (ret) 2191 goto failed_init; 2192 2193 for (i = 0; i < FEC_IRQ_NUM; i++) { 2194 irq = platform_get_irq(pdev, i); 2195 if (irq < 0) { 2196 if (i) 2197 break; 2198 ret = irq; 2199 goto failed_irq; 2200 } 2201 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 2202 0, pdev->name, ndev); 2203 if (ret) 2204 goto failed_irq; 2205 } 2206 2207 ret = fec_enet_mii_init(pdev); 2208 if (ret) 2209 goto failed_mii_init; 2210 2211 /* Carrier starts down, phylib will bring it up */ 2212 netif_carrier_off(ndev); 2213 2214 ret = register_netdev(ndev); 2215 if (ret) 2216 goto failed_register; 2217 2218 if (fep->bufdesc_ex && fep->ptp_clock) 2219 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 2220 2221 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work); 2222 return 0; 2223 2224 failed_register: 2225 fec_enet_mii_remove(fep); 2226 failed_mii_init: 2227 failed_irq: 2228 failed_init: 2229 if (fep->reg_phy) 2230 regulator_disable(fep->reg_phy); 2231 failed_regulator: 2232 if (fep->clk_ptp) 2233 clk_disable_unprepare(fep->clk_ptp); 2234 failed_clk_ptp: 2235 if (fep->clk_enet_out) 2236 clk_disable_unprepare(fep->clk_enet_out); 2237 failed_clk_enet_out: 2238 clk_disable_unprepare(fep->clk_ipg); 2239 failed_clk_ipg: 2240 clk_disable_unprepare(fep->clk_ahb); 2241 failed_clk: 2242 failed_ioremap: 2243 free_netdev(ndev); 2244 2245 return ret; 2246 } 2247 2248 static int 2249 fec_drv_remove(struct platform_device *pdev) 2250 { 2251 struct net_device *ndev = platform_get_drvdata(pdev); 2252 struct fec_enet_private *fep = netdev_priv(ndev); 2253 2254 cancel_delayed_work_sync(&(fep->delay_work.delay_work)); 2255 unregister_netdev(ndev); 2256 fec_enet_mii_remove(fep); 2257 del_timer_sync(&fep->time_keep); 2258 if (fep->reg_phy) 2259 regulator_disable(fep->reg_phy); 2260 if (fep->clk_ptp) 2261 clk_disable_unprepare(fep->clk_ptp); 2262 if (fep->ptp_clock) 2263 ptp_clock_unregister(fep->ptp_clock); 2264 if (fep->clk_enet_out) 2265 clk_disable_unprepare(fep->clk_enet_out); 2266 clk_disable_unprepare(fep->clk_ipg); 2267 clk_disable_unprepare(fep->clk_ahb); 2268 free_netdev(ndev); 2269 2270 return 0; 2271 } 2272 2273 #ifdef CONFIG_PM_SLEEP 2274 static int 2275 fec_suspend(struct device *dev) 2276 { 2277 struct net_device *ndev = dev_get_drvdata(dev); 2278 struct fec_enet_private *fep = netdev_priv(ndev); 2279 2280 if (netif_running(ndev)) { 2281 fec_stop(ndev); 2282 netif_device_detach(ndev); 2283 } 2284 if (fep->clk_ptp) 2285 clk_disable_unprepare(fep->clk_ptp); 2286 if (fep->clk_enet_out) 2287 clk_disable_unprepare(fep->clk_enet_out); 2288 clk_disable_unprepare(fep->clk_ipg); 2289 clk_disable_unprepare(fep->clk_ahb); 2290 2291 if (fep->reg_phy) 2292 regulator_disable(fep->reg_phy); 2293 2294 return 0; 2295 } 2296 2297 static int 2298 fec_resume(struct device *dev) 2299 { 2300 struct net_device *ndev = dev_get_drvdata(dev); 2301 struct fec_enet_private *fep = netdev_priv(ndev); 2302 int ret; 2303 2304 if (fep->reg_phy) { 2305 ret = regulator_enable(fep->reg_phy); 2306 if (ret) 2307 return ret; 2308 } 2309 2310 ret = clk_prepare_enable(fep->clk_ahb); 2311 if (ret) 2312 goto failed_clk_ahb; 2313 2314 ret = clk_prepare_enable(fep->clk_ipg); 2315 if (ret) 2316 goto failed_clk_ipg; 2317 2318 if (fep->clk_enet_out) { 2319 ret = clk_prepare_enable(fep->clk_enet_out); 2320 if (ret) 2321 goto failed_clk_enet_out; 2322 } 2323 2324 if (fep->clk_ptp) { 2325 ret = clk_prepare_enable(fep->clk_ptp); 2326 if (ret) 2327 goto failed_clk_ptp; 2328 } 2329 2330 if (netif_running(ndev)) { 2331 fec_restart(ndev, fep->full_duplex); 2332 netif_device_attach(ndev); 2333 } 2334 2335 return 0; 2336 2337 failed_clk_ptp: 2338 if (fep->clk_enet_out) 2339 clk_disable_unprepare(fep->clk_enet_out); 2340 failed_clk_enet_out: 2341 clk_disable_unprepare(fep->clk_ipg); 2342 failed_clk_ipg: 2343 clk_disable_unprepare(fep->clk_ahb); 2344 failed_clk_ahb: 2345 if (fep->reg_phy) 2346 regulator_disable(fep->reg_phy); 2347 return ret; 2348 } 2349 #endif /* CONFIG_PM_SLEEP */ 2350 2351 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume); 2352 2353 static struct platform_driver fec_driver = { 2354 .driver = { 2355 .name = DRIVER_NAME, 2356 .owner = THIS_MODULE, 2357 .pm = &fec_pm_ops, 2358 .of_match_table = fec_dt_ids, 2359 }, 2360 .id_table = fec_devtype, 2361 .probe = fec_probe, 2362 .remove = fec_drv_remove, 2363 }; 2364 2365 module_platform_driver(fec_driver); 2366 2367 MODULE_ALIAS("platform:"DRIVER_NAME); 2368 MODULE_LICENSE("GPL"); 2369