1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/selftests.h> 42 #include <net/tso.h> 43 #include <linux/tcp.h> 44 #include <linux/udp.h> 45 #include <linux/icmp.h> 46 #include <linux/spinlock.h> 47 #include <linux/workqueue.h> 48 #include <linux/bitops.h> 49 #include <linux/io.h> 50 #include <linux/irq.h> 51 #include <linux/clk.h> 52 #include <linux/crc32.h> 53 #include <linux/platform_device.h> 54 #include <linux/mdio.h> 55 #include <linux/phy.h> 56 #include <linux/fec.h> 57 #include <linux/of.h> 58 #include <linux/of_device.h> 59 #include <linux/of_gpio.h> 60 #include <linux/of_mdio.h> 61 #include <linux/of_net.h> 62 #include <linux/regulator/consumer.h> 63 #include <linux/if_vlan.h> 64 #include <linux/pinctrl/consumer.h> 65 #include <linux/prefetch.h> 66 #include <linux/mfd/syscon.h> 67 #include <linux/regmap.h> 68 #include <soc/imx/cpuidle.h> 69 #include <linux/filter.h> 70 #include <linux/bpf.h> 71 72 #include <asm/cacheflush.h> 73 74 #include "fec.h" 75 76 static void set_multicast_list(struct net_device *ndev); 77 static void fec_enet_itr_coal_init(struct net_device *ndev); 78 79 #define DRIVER_NAME "fec" 80 81 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 82 83 /* Pause frame feild and FIFO threshold */ 84 #define FEC_ENET_FCE (1 << 5) 85 #define FEC_ENET_RSEM_V 0x84 86 #define FEC_ENET_RSFL_V 16 87 #define FEC_ENET_RAEM_V 0x8 88 #define FEC_ENET_RAFL_V 0x8 89 #define FEC_ENET_OPD_V 0xFFF0 90 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 91 92 #define FEC_ENET_XDP_PASS 0 93 #define FEC_ENET_XDP_CONSUMED BIT(0) 94 #define FEC_ENET_XDP_TX BIT(1) 95 #define FEC_ENET_XDP_REDIR BIT(2) 96 97 struct fec_devinfo { 98 u32 quirks; 99 }; 100 101 static const struct fec_devinfo fec_imx25_info = { 102 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 103 FEC_QUIRK_HAS_FRREG, 104 }; 105 106 static const struct fec_devinfo fec_imx27_info = { 107 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG, 108 }; 109 110 static const struct fec_devinfo fec_imx28_info = { 111 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 112 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 113 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 114 FEC_QUIRK_NO_HARD_RESET, 115 }; 116 117 static const struct fec_devinfo fec_imx6q_info = { 118 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 119 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 120 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 121 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII | 122 FEC_QUIRK_HAS_PMQOS, 123 }; 124 125 static const struct fec_devinfo fec_mvf600_info = { 126 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 127 }; 128 129 static const struct fec_devinfo fec_imx6x_info = { 130 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 131 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 132 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 133 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 134 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 135 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES, 136 }; 137 138 static const struct fec_devinfo fec_imx6ul_info = { 139 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 140 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 141 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 142 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 143 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII, 144 }; 145 146 static const struct fec_devinfo fec_imx8mq_info = { 147 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 148 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 149 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 150 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 151 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 152 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 153 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2, 154 }; 155 156 static const struct fec_devinfo fec_imx8qm_info = { 157 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 158 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 159 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 160 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 161 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 162 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 163 FEC_QUIRK_DELAYED_CLKS_SUPPORT, 164 }; 165 166 static const struct fec_devinfo fec_s32v234_info = { 167 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 168 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 169 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 170 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE, 171 }; 172 173 static struct platform_device_id fec_devtype[] = { 174 { 175 /* keep it for coldfire */ 176 .name = DRIVER_NAME, 177 .driver_data = 0, 178 }, { 179 .name = "imx25-fec", 180 .driver_data = (kernel_ulong_t)&fec_imx25_info, 181 }, { 182 .name = "imx27-fec", 183 .driver_data = (kernel_ulong_t)&fec_imx27_info, 184 }, { 185 .name = "imx28-fec", 186 .driver_data = (kernel_ulong_t)&fec_imx28_info, 187 }, { 188 .name = "imx6q-fec", 189 .driver_data = (kernel_ulong_t)&fec_imx6q_info, 190 }, { 191 .name = "mvf600-fec", 192 .driver_data = (kernel_ulong_t)&fec_mvf600_info, 193 }, { 194 .name = "imx6sx-fec", 195 .driver_data = (kernel_ulong_t)&fec_imx6x_info, 196 }, { 197 .name = "imx6ul-fec", 198 .driver_data = (kernel_ulong_t)&fec_imx6ul_info, 199 }, { 200 .name = "imx8mq-fec", 201 .driver_data = (kernel_ulong_t)&fec_imx8mq_info, 202 }, { 203 .name = "imx8qm-fec", 204 .driver_data = (kernel_ulong_t)&fec_imx8qm_info, 205 }, { 206 .name = "s32v234-fec", 207 .driver_data = (kernel_ulong_t)&fec_s32v234_info, 208 }, { 209 /* sentinel */ 210 } 211 }; 212 MODULE_DEVICE_TABLE(platform, fec_devtype); 213 214 enum imx_fec_type { 215 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 216 IMX27_FEC, /* runs on i.mx27/35/51 */ 217 IMX28_FEC, 218 IMX6Q_FEC, 219 MVF600_FEC, 220 IMX6SX_FEC, 221 IMX6UL_FEC, 222 IMX8MQ_FEC, 223 IMX8QM_FEC, 224 S32V234_FEC, 225 }; 226 227 static const struct of_device_id fec_dt_ids[] = { 228 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 229 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 230 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 231 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 232 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 233 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 234 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 235 { .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], }, 236 { .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], }, 237 { .compatible = "fsl,s32v234-fec", .data = &fec_devtype[S32V234_FEC], }, 238 { /* sentinel */ } 239 }; 240 MODULE_DEVICE_TABLE(of, fec_dt_ids); 241 242 static unsigned char macaddr[ETH_ALEN]; 243 module_param_array(macaddr, byte, NULL, 0); 244 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 245 246 #if defined(CONFIG_M5272) 247 /* 248 * Some hardware gets it MAC address out of local flash memory. 249 * if this is non-zero then assume it is the address to get MAC from. 250 */ 251 #if defined(CONFIG_NETtel) 252 #define FEC_FLASHMAC 0xf0006006 253 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 254 #define FEC_FLASHMAC 0xf0006000 255 #elif defined(CONFIG_CANCam) 256 #define FEC_FLASHMAC 0xf0020000 257 #elif defined (CONFIG_M5272C3) 258 #define FEC_FLASHMAC (0xffe04000 + 4) 259 #elif defined(CONFIG_MOD5272) 260 #define FEC_FLASHMAC 0xffc0406b 261 #else 262 #define FEC_FLASHMAC 0 263 #endif 264 #endif /* CONFIG_M5272 */ 265 266 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 267 * 268 * 2048 byte skbufs are allocated. However, alignment requirements 269 * varies between FEC variants. Worst case is 64, so round down by 64. 270 */ 271 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 272 #define PKT_MINBUF_SIZE 64 273 274 /* FEC receive acceleration */ 275 #define FEC_RACC_IPDIS (1 << 1) 276 #define FEC_RACC_PRODIS (1 << 2) 277 #define FEC_RACC_SHIFT16 BIT(7) 278 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 279 280 /* MIB Control Register */ 281 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 282 283 /* 284 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 285 * size bits. Other FEC hardware does not, so we need to take that into 286 * account when setting it. 287 */ 288 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 289 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 290 defined(CONFIG_ARM64) 291 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 292 #else 293 #define OPT_FRAME_SIZE 0 294 #endif 295 296 /* FEC MII MMFR bits definition */ 297 #define FEC_MMFR_ST (1 << 30) 298 #define FEC_MMFR_ST_C45 (0) 299 #define FEC_MMFR_OP_READ (2 << 28) 300 #define FEC_MMFR_OP_READ_C45 (3 << 28) 301 #define FEC_MMFR_OP_WRITE (1 << 28) 302 #define FEC_MMFR_OP_ADDR_WRITE (0) 303 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 304 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 305 #define FEC_MMFR_TA (2 << 16) 306 #define FEC_MMFR_DATA(v) (v & 0xffff) 307 /* FEC ECR bits definition */ 308 #define FEC_ECR_MAGICEN (1 << 2) 309 #define FEC_ECR_SLEEP (1 << 3) 310 311 #define FEC_MII_TIMEOUT 30000 /* us */ 312 313 /* Transmitter timeout */ 314 #define TX_TIMEOUT (2 * HZ) 315 316 #define FEC_PAUSE_FLAG_AUTONEG 0x1 317 #define FEC_PAUSE_FLAG_ENABLE 0x2 318 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 319 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 320 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 321 322 #define COPYBREAK_DEFAULT 256 323 324 /* Max number of allowed TCP segments for software TSO */ 325 #define FEC_MAX_TSO_SEGS 100 326 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 327 328 #define IS_TSO_HEADER(txq, addr) \ 329 ((addr >= txq->tso_hdrs_dma) && \ 330 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 331 332 static int mii_cnt; 333 334 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 335 struct bufdesc_prop *bd) 336 { 337 return (bdp >= bd->last) ? bd->base 338 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 339 } 340 341 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 342 struct bufdesc_prop *bd) 343 { 344 return (bdp <= bd->base) ? bd->last 345 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 346 } 347 348 static int fec_enet_get_bd_index(struct bufdesc *bdp, 349 struct bufdesc_prop *bd) 350 { 351 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 352 } 353 354 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 355 { 356 int entries; 357 358 entries = (((const char *)txq->dirty_tx - 359 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 360 361 return entries >= 0 ? entries : entries + txq->bd.ring_size; 362 } 363 364 static void swap_buffer(void *bufaddr, int len) 365 { 366 int i; 367 unsigned int *buf = bufaddr; 368 369 for (i = 0; i < len; i += 4, buf++) 370 swab32s(buf); 371 } 372 373 static void fec_dump(struct net_device *ndev) 374 { 375 struct fec_enet_private *fep = netdev_priv(ndev); 376 struct bufdesc *bdp; 377 struct fec_enet_priv_tx_q *txq; 378 int index = 0; 379 380 netdev_info(ndev, "TX ring dump\n"); 381 pr_info("Nr SC addr len SKB\n"); 382 383 txq = fep->tx_queue[0]; 384 bdp = txq->bd.base; 385 386 do { 387 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 388 index, 389 bdp == txq->bd.cur ? 'S' : ' ', 390 bdp == txq->dirty_tx ? 'H' : ' ', 391 fec16_to_cpu(bdp->cbd_sc), 392 fec32_to_cpu(bdp->cbd_bufaddr), 393 fec16_to_cpu(bdp->cbd_datlen), 394 txq->tx_skbuff[index]); 395 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 396 index++; 397 } while (bdp != txq->bd.base); 398 } 399 400 static inline bool is_ipv4_pkt(struct sk_buff *skb) 401 { 402 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 403 } 404 405 static int 406 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 407 { 408 /* Only run for packets requiring a checksum. */ 409 if (skb->ip_summed != CHECKSUM_PARTIAL) 410 return 0; 411 412 if (unlikely(skb_cow_head(skb, 0))) 413 return -1; 414 415 if (is_ipv4_pkt(skb)) 416 ip_hdr(skb)->check = 0; 417 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 418 419 return 0; 420 } 421 422 static int 423 fec_enet_create_page_pool(struct fec_enet_private *fep, 424 struct fec_enet_priv_rx_q *rxq, int size) 425 { 426 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 427 struct page_pool_params pp_params = { 428 .order = 0, 429 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 430 .pool_size = size, 431 .nid = dev_to_node(&fep->pdev->dev), 432 .dev = &fep->pdev->dev, 433 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 434 .offset = FEC_ENET_XDP_HEADROOM, 435 .max_len = FEC_ENET_RX_FRSIZE, 436 }; 437 int err; 438 439 rxq->page_pool = page_pool_create(&pp_params); 440 if (IS_ERR(rxq->page_pool)) { 441 err = PTR_ERR(rxq->page_pool); 442 rxq->page_pool = NULL; 443 return err; 444 } 445 446 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0); 447 if (err < 0) 448 goto err_free_pp; 449 450 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 451 rxq->page_pool); 452 if (err) 453 goto err_unregister_rxq; 454 455 return 0; 456 457 err_unregister_rxq: 458 xdp_rxq_info_unreg(&rxq->xdp_rxq); 459 err_free_pp: 460 page_pool_destroy(rxq->page_pool); 461 rxq->page_pool = NULL; 462 return err; 463 } 464 465 static struct bufdesc * 466 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 467 struct sk_buff *skb, 468 struct net_device *ndev) 469 { 470 struct fec_enet_private *fep = netdev_priv(ndev); 471 struct bufdesc *bdp = txq->bd.cur; 472 struct bufdesc_ex *ebdp; 473 int nr_frags = skb_shinfo(skb)->nr_frags; 474 int frag, frag_len; 475 unsigned short status; 476 unsigned int estatus = 0; 477 skb_frag_t *this_frag; 478 unsigned int index; 479 void *bufaddr; 480 dma_addr_t addr; 481 int i; 482 483 for (frag = 0; frag < nr_frags; frag++) { 484 this_frag = &skb_shinfo(skb)->frags[frag]; 485 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 486 ebdp = (struct bufdesc_ex *)bdp; 487 488 status = fec16_to_cpu(bdp->cbd_sc); 489 status &= ~BD_ENET_TX_STATS; 490 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 491 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 492 493 /* Handle the last BD specially */ 494 if (frag == nr_frags - 1) { 495 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 496 if (fep->bufdesc_ex) { 497 estatus |= BD_ENET_TX_INT; 498 if (unlikely(skb_shinfo(skb)->tx_flags & 499 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 500 estatus |= BD_ENET_TX_TS; 501 } 502 } 503 504 if (fep->bufdesc_ex) { 505 if (fep->quirks & FEC_QUIRK_HAS_AVB) 506 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 507 if (skb->ip_summed == CHECKSUM_PARTIAL) 508 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 509 510 ebdp->cbd_bdu = 0; 511 ebdp->cbd_esc = cpu_to_fec32(estatus); 512 } 513 514 bufaddr = skb_frag_address(this_frag); 515 516 index = fec_enet_get_bd_index(bdp, &txq->bd); 517 if (((unsigned long) bufaddr) & fep->tx_align || 518 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 519 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 520 bufaddr = txq->tx_bounce[index]; 521 522 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 523 swap_buffer(bufaddr, frag_len); 524 } 525 526 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 527 DMA_TO_DEVICE); 528 if (dma_mapping_error(&fep->pdev->dev, addr)) { 529 if (net_ratelimit()) 530 netdev_err(ndev, "Tx DMA memory map failed\n"); 531 goto dma_mapping_error; 532 } 533 534 bdp->cbd_bufaddr = cpu_to_fec32(addr); 535 bdp->cbd_datlen = cpu_to_fec16(frag_len); 536 /* Make sure the updates to rest of the descriptor are 537 * performed before transferring ownership. 538 */ 539 wmb(); 540 bdp->cbd_sc = cpu_to_fec16(status); 541 } 542 543 return bdp; 544 dma_mapping_error: 545 bdp = txq->bd.cur; 546 for (i = 0; i < frag; i++) { 547 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 548 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 549 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 550 } 551 return ERR_PTR(-ENOMEM); 552 } 553 554 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 555 struct sk_buff *skb, struct net_device *ndev) 556 { 557 struct fec_enet_private *fep = netdev_priv(ndev); 558 int nr_frags = skb_shinfo(skb)->nr_frags; 559 struct bufdesc *bdp, *last_bdp; 560 void *bufaddr; 561 dma_addr_t addr; 562 unsigned short status; 563 unsigned short buflen; 564 unsigned int estatus = 0; 565 unsigned int index; 566 int entries_free; 567 568 entries_free = fec_enet_get_free_txdesc_num(txq); 569 if (entries_free < MAX_SKB_FRAGS + 1) { 570 dev_kfree_skb_any(skb); 571 if (net_ratelimit()) 572 netdev_err(ndev, "NOT enough BD for SG!\n"); 573 return NETDEV_TX_OK; 574 } 575 576 /* Protocol checksum off-load for TCP and UDP. */ 577 if (fec_enet_clear_csum(skb, ndev)) { 578 dev_kfree_skb_any(skb); 579 return NETDEV_TX_OK; 580 } 581 582 /* Fill in a Tx ring entry */ 583 bdp = txq->bd.cur; 584 last_bdp = bdp; 585 status = fec16_to_cpu(bdp->cbd_sc); 586 status &= ~BD_ENET_TX_STATS; 587 588 /* Set buffer length and buffer pointer */ 589 bufaddr = skb->data; 590 buflen = skb_headlen(skb); 591 592 index = fec_enet_get_bd_index(bdp, &txq->bd); 593 if (((unsigned long) bufaddr) & fep->tx_align || 594 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 595 memcpy(txq->tx_bounce[index], skb->data, buflen); 596 bufaddr = txq->tx_bounce[index]; 597 598 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 599 swap_buffer(bufaddr, buflen); 600 } 601 602 /* Push the data cache so the CPM does not get stale memory data. */ 603 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 604 if (dma_mapping_error(&fep->pdev->dev, addr)) { 605 dev_kfree_skb_any(skb); 606 if (net_ratelimit()) 607 netdev_err(ndev, "Tx DMA memory map failed\n"); 608 return NETDEV_TX_OK; 609 } 610 611 if (nr_frags) { 612 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 613 if (IS_ERR(last_bdp)) { 614 dma_unmap_single(&fep->pdev->dev, addr, 615 buflen, DMA_TO_DEVICE); 616 dev_kfree_skb_any(skb); 617 return NETDEV_TX_OK; 618 } 619 } else { 620 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 621 if (fep->bufdesc_ex) { 622 estatus = BD_ENET_TX_INT; 623 if (unlikely(skb_shinfo(skb)->tx_flags & 624 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 625 estatus |= BD_ENET_TX_TS; 626 } 627 } 628 bdp->cbd_bufaddr = cpu_to_fec32(addr); 629 bdp->cbd_datlen = cpu_to_fec16(buflen); 630 631 if (fep->bufdesc_ex) { 632 633 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 634 635 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 636 fep->hwts_tx_en)) 637 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 638 639 if (fep->quirks & FEC_QUIRK_HAS_AVB) 640 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 641 642 if (skb->ip_summed == CHECKSUM_PARTIAL) 643 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 644 645 ebdp->cbd_bdu = 0; 646 ebdp->cbd_esc = cpu_to_fec32(estatus); 647 } 648 649 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 650 /* Save skb pointer */ 651 txq->tx_skbuff[index] = skb; 652 653 /* Make sure the updates to rest of the descriptor are performed before 654 * transferring ownership. 655 */ 656 wmb(); 657 658 /* Send it on its way. Tell FEC it's ready, interrupt when done, 659 * it's the last BD of the frame, and to put the CRC on the end. 660 */ 661 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 662 bdp->cbd_sc = cpu_to_fec16(status); 663 664 /* If this was the last BD in the ring, start at the beginning again. */ 665 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 666 667 skb_tx_timestamp(skb); 668 669 /* Make sure the update to bdp and tx_skbuff are performed before 670 * txq->bd.cur. 671 */ 672 wmb(); 673 txq->bd.cur = bdp; 674 675 /* Trigger transmission start */ 676 writel(0, txq->bd.reg_desc_active); 677 678 return 0; 679 } 680 681 static int 682 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 683 struct net_device *ndev, 684 struct bufdesc *bdp, int index, char *data, 685 int size, bool last_tcp, bool is_last) 686 { 687 struct fec_enet_private *fep = netdev_priv(ndev); 688 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 689 unsigned short status; 690 unsigned int estatus = 0; 691 dma_addr_t addr; 692 693 status = fec16_to_cpu(bdp->cbd_sc); 694 status &= ~BD_ENET_TX_STATS; 695 696 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 697 698 if (((unsigned long) data) & fep->tx_align || 699 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 700 memcpy(txq->tx_bounce[index], data, size); 701 data = txq->tx_bounce[index]; 702 703 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 704 swap_buffer(data, size); 705 } 706 707 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 708 if (dma_mapping_error(&fep->pdev->dev, addr)) { 709 dev_kfree_skb_any(skb); 710 if (net_ratelimit()) 711 netdev_err(ndev, "Tx DMA memory map failed\n"); 712 return NETDEV_TX_OK; 713 } 714 715 bdp->cbd_datlen = cpu_to_fec16(size); 716 bdp->cbd_bufaddr = cpu_to_fec32(addr); 717 718 if (fep->bufdesc_ex) { 719 if (fep->quirks & FEC_QUIRK_HAS_AVB) 720 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 721 if (skb->ip_summed == CHECKSUM_PARTIAL) 722 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 723 ebdp->cbd_bdu = 0; 724 ebdp->cbd_esc = cpu_to_fec32(estatus); 725 } 726 727 /* Handle the last BD specially */ 728 if (last_tcp) 729 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 730 if (is_last) { 731 status |= BD_ENET_TX_INTR; 732 if (fep->bufdesc_ex) 733 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 734 } 735 736 bdp->cbd_sc = cpu_to_fec16(status); 737 738 return 0; 739 } 740 741 static int 742 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 743 struct sk_buff *skb, struct net_device *ndev, 744 struct bufdesc *bdp, int index) 745 { 746 struct fec_enet_private *fep = netdev_priv(ndev); 747 int hdr_len = skb_tcp_all_headers(skb); 748 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 749 void *bufaddr; 750 unsigned long dmabuf; 751 unsigned short status; 752 unsigned int estatus = 0; 753 754 status = fec16_to_cpu(bdp->cbd_sc); 755 status &= ~BD_ENET_TX_STATS; 756 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 757 758 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 759 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 760 if (((unsigned long)bufaddr) & fep->tx_align || 761 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 762 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 763 bufaddr = txq->tx_bounce[index]; 764 765 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 766 swap_buffer(bufaddr, hdr_len); 767 768 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 769 hdr_len, DMA_TO_DEVICE); 770 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 771 dev_kfree_skb_any(skb); 772 if (net_ratelimit()) 773 netdev_err(ndev, "Tx DMA memory map failed\n"); 774 return NETDEV_TX_OK; 775 } 776 } 777 778 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 779 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 780 781 if (fep->bufdesc_ex) { 782 if (fep->quirks & FEC_QUIRK_HAS_AVB) 783 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 784 if (skb->ip_summed == CHECKSUM_PARTIAL) 785 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 786 ebdp->cbd_bdu = 0; 787 ebdp->cbd_esc = cpu_to_fec32(estatus); 788 } 789 790 bdp->cbd_sc = cpu_to_fec16(status); 791 792 return 0; 793 } 794 795 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 796 struct sk_buff *skb, 797 struct net_device *ndev) 798 { 799 struct fec_enet_private *fep = netdev_priv(ndev); 800 int hdr_len, total_len, data_left; 801 struct bufdesc *bdp = txq->bd.cur; 802 struct tso_t tso; 803 unsigned int index = 0; 804 int ret; 805 806 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 807 dev_kfree_skb_any(skb); 808 if (net_ratelimit()) 809 netdev_err(ndev, "NOT enough BD for TSO!\n"); 810 return NETDEV_TX_OK; 811 } 812 813 /* Protocol checksum off-load for TCP and UDP. */ 814 if (fec_enet_clear_csum(skb, ndev)) { 815 dev_kfree_skb_any(skb); 816 return NETDEV_TX_OK; 817 } 818 819 /* Initialize the TSO handler, and prepare the first payload */ 820 hdr_len = tso_start(skb, &tso); 821 822 total_len = skb->len - hdr_len; 823 while (total_len > 0) { 824 char *hdr; 825 826 index = fec_enet_get_bd_index(bdp, &txq->bd); 827 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 828 total_len -= data_left; 829 830 /* prepare packet headers: MAC + IP + TCP */ 831 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 832 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 833 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 834 if (ret) 835 goto err_release; 836 837 while (data_left > 0) { 838 int size; 839 840 size = min_t(int, tso.size, data_left); 841 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 842 index = fec_enet_get_bd_index(bdp, &txq->bd); 843 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 844 bdp, index, 845 tso.data, size, 846 size == data_left, 847 total_len == 0); 848 if (ret) 849 goto err_release; 850 851 data_left -= size; 852 tso_build_data(skb, &tso, size); 853 } 854 855 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 856 } 857 858 /* Save skb pointer */ 859 txq->tx_skbuff[index] = skb; 860 861 skb_tx_timestamp(skb); 862 txq->bd.cur = bdp; 863 864 /* Trigger transmission start */ 865 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 866 !readl(txq->bd.reg_desc_active) || 867 !readl(txq->bd.reg_desc_active) || 868 !readl(txq->bd.reg_desc_active) || 869 !readl(txq->bd.reg_desc_active)) 870 writel(0, txq->bd.reg_desc_active); 871 872 return 0; 873 874 err_release: 875 /* TODO: Release all used data descriptors for TSO */ 876 return ret; 877 } 878 879 static netdev_tx_t 880 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 881 { 882 struct fec_enet_private *fep = netdev_priv(ndev); 883 int entries_free; 884 unsigned short queue; 885 struct fec_enet_priv_tx_q *txq; 886 struct netdev_queue *nq; 887 int ret; 888 889 queue = skb_get_queue_mapping(skb); 890 txq = fep->tx_queue[queue]; 891 nq = netdev_get_tx_queue(ndev, queue); 892 893 if (skb_is_gso(skb)) 894 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 895 else 896 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 897 if (ret) 898 return ret; 899 900 entries_free = fec_enet_get_free_txdesc_num(txq); 901 if (entries_free <= txq->tx_stop_threshold) 902 netif_tx_stop_queue(nq); 903 904 return NETDEV_TX_OK; 905 } 906 907 /* Init RX & TX buffer descriptors 908 */ 909 static void fec_enet_bd_init(struct net_device *dev) 910 { 911 struct fec_enet_private *fep = netdev_priv(dev); 912 struct fec_enet_priv_tx_q *txq; 913 struct fec_enet_priv_rx_q *rxq; 914 struct bufdesc *bdp; 915 unsigned int i; 916 unsigned int q; 917 918 for (q = 0; q < fep->num_rx_queues; q++) { 919 /* Initialize the receive buffer descriptors. */ 920 rxq = fep->rx_queue[q]; 921 bdp = rxq->bd.base; 922 923 for (i = 0; i < rxq->bd.ring_size; i++) { 924 925 /* Initialize the BD for every fragment in the page. */ 926 if (bdp->cbd_bufaddr) 927 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 928 else 929 bdp->cbd_sc = cpu_to_fec16(0); 930 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 931 } 932 933 /* Set the last buffer to wrap */ 934 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 935 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 936 937 rxq->bd.cur = rxq->bd.base; 938 } 939 940 for (q = 0; q < fep->num_tx_queues; q++) { 941 /* ...and the same for transmit */ 942 txq = fep->tx_queue[q]; 943 bdp = txq->bd.base; 944 txq->bd.cur = bdp; 945 946 for (i = 0; i < txq->bd.ring_size; i++) { 947 /* Initialize the BD for every fragment in the page. */ 948 bdp->cbd_sc = cpu_to_fec16(0); 949 if (bdp->cbd_bufaddr && 950 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 951 dma_unmap_single(&fep->pdev->dev, 952 fec32_to_cpu(bdp->cbd_bufaddr), 953 fec16_to_cpu(bdp->cbd_datlen), 954 DMA_TO_DEVICE); 955 if (txq->tx_skbuff[i]) { 956 dev_kfree_skb_any(txq->tx_skbuff[i]); 957 txq->tx_skbuff[i] = NULL; 958 } 959 bdp->cbd_bufaddr = cpu_to_fec32(0); 960 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 961 } 962 963 /* Set the last buffer to wrap */ 964 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 965 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 966 txq->dirty_tx = bdp; 967 } 968 } 969 970 static void fec_enet_active_rxring(struct net_device *ndev) 971 { 972 struct fec_enet_private *fep = netdev_priv(ndev); 973 int i; 974 975 for (i = 0; i < fep->num_rx_queues; i++) 976 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 977 } 978 979 static void fec_enet_enable_ring(struct net_device *ndev) 980 { 981 struct fec_enet_private *fep = netdev_priv(ndev); 982 struct fec_enet_priv_tx_q *txq; 983 struct fec_enet_priv_rx_q *rxq; 984 int i; 985 986 for (i = 0; i < fep->num_rx_queues; i++) { 987 rxq = fep->rx_queue[i]; 988 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 989 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 990 991 /* enable DMA1/2 */ 992 if (i) 993 writel(RCMR_MATCHEN | RCMR_CMP(i), 994 fep->hwp + FEC_RCMR(i)); 995 } 996 997 for (i = 0; i < fep->num_tx_queues; i++) { 998 txq = fep->tx_queue[i]; 999 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 1000 1001 /* enable DMA1/2 */ 1002 if (i) 1003 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 1004 fep->hwp + FEC_DMA_CFG(i)); 1005 } 1006 } 1007 1008 static void fec_enet_reset_skb(struct net_device *ndev) 1009 { 1010 struct fec_enet_private *fep = netdev_priv(ndev); 1011 struct fec_enet_priv_tx_q *txq; 1012 int i, j; 1013 1014 for (i = 0; i < fep->num_tx_queues; i++) { 1015 txq = fep->tx_queue[i]; 1016 1017 for (j = 0; j < txq->bd.ring_size; j++) { 1018 if (txq->tx_skbuff[j]) { 1019 dev_kfree_skb_any(txq->tx_skbuff[j]); 1020 txq->tx_skbuff[j] = NULL; 1021 } 1022 } 1023 } 1024 } 1025 1026 /* 1027 * This function is called to start or restart the FEC during a link 1028 * change, transmit timeout, or to reconfigure the FEC. The network 1029 * packet processing for this device must be stopped before this call. 1030 */ 1031 static void 1032 fec_restart(struct net_device *ndev) 1033 { 1034 struct fec_enet_private *fep = netdev_priv(ndev); 1035 u32 temp_mac[2]; 1036 u32 rcntl = OPT_FRAME_SIZE | 0x04; 1037 u32 ecntl = 0x2; /* ETHEREN */ 1038 1039 /* Whack a reset. We should wait for this. 1040 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1041 * instead of reset MAC itself. 1042 */ 1043 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 1044 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 1045 writel(0, fep->hwp + FEC_ECNTRL); 1046 } else { 1047 writel(1, fep->hwp + FEC_ECNTRL); 1048 udelay(10); 1049 } 1050 1051 /* 1052 * enet-mac reset will reset mac address registers too, 1053 * so need to reconfigure it. 1054 */ 1055 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 1056 writel((__force u32)cpu_to_be32(temp_mac[0]), 1057 fep->hwp + FEC_ADDR_LOW); 1058 writel((__force u32)cpu_to_be32(temp_mac[1]), 1059 fep->hwp + FEC_ADDR_HIGH); 1060 1061 /* Clear any outstanding interrupt, except MDIO. */ 1062 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1063 1064 fec_enet_bd_init(ndev); 1065 1066 fec_enet_enable_ring(ndev); 1067 1068 /* Reset tx SKB buffers. */ 1069 fec_enet_reset_skb(ndev); 1070 1071 /* Enable MII mode */ 1072 if (fep->full_duplex == DUPLEX_FULL) { 1073 /* FD enable */ 1074 writel(0x04, fep->hwp + FEC_X_CNTRL); 1075 } else { 1076 /* No Rcv on Xmit */ 1077 rcntl |= 0x02; 1078 writel(0x0, fep->hwp + FEC_X_CNTRL); 1079 } 1080 1081 /* Set MII speed */ 1082 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1083 1084 #if !defined(CONFIG_M5272) 1085 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1086 u32 val = readl(fep->hwp + FEC_RACC); 1087 1088 /* align IP header */ 1089 val |= FEC_RACC_SHIFT16; 1090 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1091 /* set RX checksum */ 1092 val |= FEC_RACC_OPTIONS; 1093 else 1094 val &= ~FEC_RACC_OPTIONS; 1095 writel(val, fep->hwp + FEC_RACC); 1096 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1097 } 1098 #endif 1099 1100 /* 1101 * The phy interface and speed need to get configured 1102 * differently on enet-mac. 1103 */ 1104 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1105 /* Enable flow control and length check */ 1106 rcntl |= 0x40000000 | 0x00000020; 1107 1108 /* RGMII, RMII or MII */ 1109 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1110 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1111 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1112 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1113 rcntl |= (1 << 6); 1114 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1115 rcntl |= (1 << 8); 1116 else 1117 rcntl &= ~(1 << 8); 1118 1119 /* 1G, 100M or 10M */ 1120 if (ndev->phydev) { 1121 if (ndev->phydev->speed == SPEED_1000) 1122 ecntl |= (1 << 5); 1123 else if (ndev->phydev->speed == SPEED_100) 1124 rcntl &= ~(1 << 9); 1125 else 1126 rcntl |= (1 << 9); 1127 } 1128 } else { 1129 #ifdef FEC_MIIGSK_ENR 1130 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1131 u32 cfgr; 1132 /* disable the gasket and wait */ 1133 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1134 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1135 udelay(1); 1136 1137 /* 1138 * configure the gasket: 1139 * RMII, 50 MHz, no loopback, no echo 1140 * MII, 25 MHz, no loopback, no echo 1141 */ 1142 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1143 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1144 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1145 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1146 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1147 1148 /* re-enable the gasket */ 1149 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1150 } 1151 #endif 1152 } 1153 1154 #if !defined(CONFIG_M5272) 1155 /* enable pause frame*/ 1156 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1157 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1158 ndev->phydev && ndev->phydev->pause)) { 1159 rcntl |= FEC_ENET_FCE; 1160 1161 /* set FIFO threshold parameter to reduce overrun */ 1162 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1163 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1164 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1165 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1166 1167 /* OPD */ 1168 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1169 } else { 1170 rcntl &= ~FEC_ENET_FCE; 1171 } 1172 #endif /* !defined(CONFIG_M5272) */ 1173 1174 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1175 1176 /* Setup multicast filter. */ 1177 set_multicast_list(ndev); 1178 #ifndef CONFIG_M5272 1179 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1180 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1181 #endif 1182 1183 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1184 /* enable ENET endian swap */ 1185 ecntl |= (1 << 8); 1186 /* enable ENET store and forward mode */ 1187 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1188 } 1189 1190 if (fep->bufdesc_ex) 1191 ecntl |= (1 << 4); 1192 1193 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1194 fep->rgmii_txc_dly) 1195 ecntl |= FEC_ENET_TXC_DLY; 1196 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1197 fep->rgmii_rxc_dly) 1198 ecntl |= FEC_ENET_RXC_DLY; 1199 1200 #ifndef CONFIG_M5272 1201 /* Enable the MIB statistic event counters */ 1202 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1203 #endif 1204 1205 /* And last, enable the transmit and receive processing */ 1206 writel(ecntl, fep->hwp + FEC_ECNTRL); 1207 fec_enet_active_rxring(ndev); 1208 1209 if (fep->bufdesc_ex) 1210 fec_ptp_start_cyclecounter(ndev); 1211 1212 /* Enable interrupts we wish to service */ 1213 if (fep->link) 1214 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1215 else 1216 writel(0, fep->hwp + FEC_IMASK); 1217 1218 /* Init the interrupt coalescing */ 1219 fec_enet_itr_coal_init(ndev); 1220 1221 } 1222 1223 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep) 1224 { 1225 if (!(of_machine_is_compatible("fsl,imx8qm") || 1226 of_machine_is_compatible("fsl,imx8qxp") || 1227 of_machine_is_compatible("fsl,imx8dxl"))) 1228 return 0; 1229 1230 return imx_scu_get_handle(&fep->ipc_handle); 1231 } 1232 1233 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled) 1234 { 1235 struct device_node *np = fep->pdev->dev.of_node; 1236 u32 rsrc_id, val; 1237 int idx; 1238 1239 if (!np || !fep->ipc_handle) 1240 return; 1241 1242 idx = of_alias_get_id(np, "ethernet"); 1243 if (idx < 0) 1244 idx = 0; 1245 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0; 1246 1247 val = enabled ? 1 : 0; 1248 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val); 1249 } 1250 1251 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1252 { 1253 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1254 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1255 1256 if (stop_gpr->gpr) { 1257 if (enabled) 1258 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1259 BIT(stop_gpr->bit), 1260 BIT(stop_gpr->bit)); 1261 else 1262 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1263 BIT(stop_gpr->bit), 0); 1264 } else if (pdata && pdata->sleep_mode_enable) { 1265 pdata->sleep_mode_enable(enabled); 1266 } else { 1267 fec_enet_ipg_stop_set(fep, enabled); 1268 } 1269 } 1270 1271 static void fec_irqs_disable(struct net_device *ndev) 1272 { 1273 struct fec_enet_private *fep = netdev_priv(ndev); 1274 1275 writel(0, fep->hwp + FEC_IMASK); 1276 } 1277 1278 static void fec_irqs_disable_except_wakeup(struct net_device *ndev) 1279 { 1280 struct fec_enet_private *fep = netdev_priv(ndev); 1281 1282 writel(0, fep->hwp + FEC_IMASK); 1283 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1284 } 1285 1286 static void 1287 fec_stop(struct net_device *ndev) 1288 { 1289 struct fec_enet_private *fep = netdev_priv(ndev); 1290 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1291 u32 val; 1292 1293 /* We cannot expect a graceful transmit stop without link !!! */ 1294 if (fep->link) { 1295 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1296 udelay(10); 1297 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1298 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1299 } 1300 1301 /* Whack a reset. We should wait for this. 1302 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1303 * instead of reset MAC itself. 1304 */ 1305 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1306 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 1307 writel(0, fep->hwp + FEC_ECNTRL); 1308 } else { 1309 writel(1, fep->hwp + FEC_ECNTRL); 1310 udelay(10); 1311 } 1312 } else { 1313 val = readl(fep->hwp + FEC_ECNTRL); 1314 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1315 writel(val, fep->hwp + FEC_ECNTRL); 1316 } 1317 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1318 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1319 1320 /* We have to keep ENET enabled to have MII interrupt stay working */ 1321 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1322 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1323 writel(2, fep->hwp + FEC_ECNTRL); 1324 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1325 } 1326 } 1327 1328 1329 static void 1330 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1331 { 1332 struct fec_enet_private *fep = netdev_priv(ndev); 1333 1334 fec_dump(ndev); 1335 1336 ndev->stats.tx_errors++; 1337 1338 schedule_work(&fep->tx_timeout_work); 1339 } 1340 1341 static void fec_enet_timeout_work(struct work_struct *work) 1342 { 1343 struct fec_enet_private *fep = 1344 container_of(work, struct fec_enet_private, tx_timeout_work); 1345 struct net_device *ndev = fep->netdev; 1346 1347 rtnl_lock(); 1348 if (netif_device_present(ndev) || netif_running(ndev)) { 1349 napi_disable(&fep->napi); 1350 netif_tx_lock_bh(ndev); 1351 fec_restart(ndev); 1352 netif_tx_wake_all_queues(ndev); 1353 netif_tx_unlock_bh(ndev); 1354 napi_enable(&fep->napi); 1355 } 1356 rtnl_unlock(); 1357 } 1358 1359 static void 1360 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1361 struct skb_shared_hwtstamps *hwtstamps) 1362 { 1363 unsigned long flags; 1364 u64 ns; 1365 1366 spin_lock_irqsave(&fep->tmreg_lock, flags); 1367 ns = timecounter_cyc2time(&fep->tc, ts); 1368 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1369 1370 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1371 hwtstamps->hwtstamp = ns_to_ktime(ns); 1372 } 1373 1374 static void 1375 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1376 { 1377 struct fec_enet_private *fep; 1378 struct bufdesc *bdp; 1379 unsigned short status; 1380 struct sk_buff *skb; 1381 struct fec_enet_priv_tx_q *txq; 1382 struct netdev_queue *nq; 1383 int index = 0; 1384 int entries_free; 1385 1386 fep = netdev_priv(ndev); 1387 1388 txq = fep->tx_queue[queue_id]; 1389 /* get next bdp of dirty_tx */ 1390 nq = netdev_get_tx_queue(ndev, queue_id); 1391 bdp = txq->dirty_tx; 1392 1393 /* get next bdp of dirty_tx */ 1394 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1395 1396 while (bdp != READ_ONCE(txq->bd.cur)) { 1397 /* Order the load of bd.cur and cbd_sc */ 1398 rmb(); 1399 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1400 if (status & BD_ENET_TX_READY) 1401 break; 1402 1403 index = fec_enet_get_bd_index(bdp, &txq->bd); 1404 1405 skb = txq->tx_skbuff[index]; 1406 txq->tx_skbuff[index] = NULL; 1407 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1408 dma_unmap_single(&fep->pdev->dev, 1409 fec32_to_cpu(bdp->cbd_bufaddr), 1410 fec16_to_cpu(bdp->cbd_datlen), 1411 DMA_TO_DEVICE); 1412 bdp->cbd_bufaddr = cpu_to_fec32(0); 1413 if (!skb) 1414 goto skb_done; 1415 1416 /* Check for errors. */ 1417 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1418 BD_ENET_TX_RL | BD_ENET_TX_UN | 1419 BD_ENET_TX_CSL)) { 1420 ndev->stats.tx_errors++; 1421 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1422 ndev->stats.tx_heartbeat_errors++; 1423 if (status & BD_ENET_TX_LC) /* Late collision */ 1424 ndev->stats.tx_window_errors++; 1425 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1426 ndev->stats.tx_aborted_errors++; 1427 if (status & BD_ENET_TX_UN) /* Underrun */ 1428 ndev->stats.tx_fifo_errors++; 1429 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1430 ndev->stats.tx_carrier_errors++; 1431 } else { 1432 ndev->stats.tx_packets++; 1433 ndev->stats.tx_bytes += skb->len; 1434 } 1435 1436 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1437 * are to time stamp the packet, so we still need to check time 1438 * stamping enabled flag. 1439 */ 1440 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1441 fep->hwts_tx_en) && 1442 fep->bufdesc_ex) { 1443 struct skb_shared_hwtstamps shhwtstamps; 1444 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1445 1446 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1447 skb_tstamp_tx(skb, &shhwtstamps); 1448 } 1449 1450 /* Deferred means some collisions occurred during transmit, 1451 * but we eventually sent the packet OK. 1452 */ 1453 if (status & BD_ENET_TX_DEF) 1454 ndev->stats.collisions++; 1455 1456 /* Free the sk buffer associated with this last transmit */ 1457 dev_kfree_skb_any(skb); 1458 skb_done: 1459 /* Make sure the update to bdp and tx_skbuff are performed 1460 * before dirty_tx 1461 */ 1462 wmb(); 1463 txq->dirty_tx = bdp; 1464 1465 /* Update pointer to next buffer descriptor to be transmitted */ 1466 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1467 1468 /* Since we have freed up a buffer, the ring is no longer full 1469 */ 1470 if (netif_tx_queue_stopped(nq)) { 1471 entries_free = fec_enet_get_free_txdesc_num(txq); 1472 if (entries_free >= txq->tx_wake_threshold) 1473 netif_tx_wake_queue(nq); 1474 } 1475 } 1476 1477 /* ERR006358: Keep the transmitter going */ 1478 if (bdp != txq->bd.cur && 1479 readl(txq->bd.reg_desc_active) == 0) 1480 writel(0, txq->bd.reg_desc_active); 1481 } 1482 1483 static void fec_enet_tx(struct net_device *ndev) 1484 { 1485 struct fec_enet_private *fep = netdev_priv(ndev); 1486 int i; 1487 1488 /* Make sure that AVB queues are processed first. */ 1489 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1490 fec_enet_tx_queue(ndev, i); 1491 } 1492 1493 static void fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq, 1494 struct bufdesc *bdp, int index) 1495 { 1496 struct page *new_page; 1497 dma_addr_t phys_addr; 1498 1499 new_page = page_pool_dev_alloc_pages(rxq->page_pool); 1500 WARN_ON(!new_page); 1501 rxq->rx_skb_info[index].page = new_page; 1502 1503 rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM; 1504 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM; 1505 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 1506 } 1507 1508 static u32 1509 fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog, 1510 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int index) 1511 { 1512 unsigned int sync, len = xdp->data_end - xdp->data; 1513 u32 ret = FEC_ENET_XDP_PASS; 1514 struct page *page; 1515 int err; 1516 u32 act; 1517 1518 act = bpf_prog_run_xdp(prog, xdp); 1519 1520 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */ 1521 sync = xdp->data_end - xdp->data_hard_start - FEC_ENET_XDP_HEADROOM; 1522 sync = max(sync, len); 1523 1524 switch (act) { 1525 case XDP_PASS: 1526 ret = FEC_ENET_XDP_PASS; 1527 break; 1528 1529 case XDP_REDIRECT: 1530 err = xdp_do_redirect(fep->netdev, xdp, prog); 1531 if (!err) { 1532 ret = FEC_ENET_XDP_REDIR; 1533 } else { 1534 ret = FEC_ENET_XDP_CONSUMED; 1535 page = virt_to_head_page(xdp->data); 1536 page_pool_put_page(rxq->page_pool, page, sync, true); 1537 } 1538 break; 1539 1540 default: 1541 bpf_warn_invalid_xdp_action(fep->netdev, prog, act); 1542 fallthrough; 1543 1544 case XDP_TX: 1545 bpf_warn_invalid_xdp_action(fep->netdev, prog, act); 1546 fallthrough; 1547 1548 case XDP_ABORTED: 1549 fallthrough; /* handle aborts by dropping packet */ 1550 1551 case XDP_DROP: 1552 ret = FEC_ENET_XDP_CONSUMED; 1553 page = virt_to_head_page(xdp->data); 1554 page_pool_put_page(rxq->page_pool, page, sync, true); 1555 break; 1556 } 1557 1558 return ret; 1559 } 1560 1561 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1562 * When we update through the ring, if the next incoming buffer has 1563 * not been given to the system, we just set the empty indicator, 1564 * effectively tossing the packet. 1565 */ 1566 static int 1567 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1568 { 1569 struct fec_enet_private *fep = netdev_priv(ndev); 1570 struct fec_enet_priv_rx_q *rxq; 1571 struct bufdesc *bdp; 1572 unsigned short status; 1573 struct sk_buff *skb; 1574 ushort pkt_len; 1575 __u8 *data; 1576 int pkt_received = 0; 1577 struct bufdesc_ex *ebdp = NULL; 1578 bool vlan_packet_rcvd = false; 1579 u16 vlan_tag; 1580 int index = 0; 1581 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1582 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 1583 u32 ret, xdp_result = FEC_ENET_XDP_PASS; 1584 u32 data_start = FEC_ENET_XDP_HEADROOM; 1585 struct xdp_buff xdp; 1586 struct page *page; 1587 u32 sub_len = 4; 1588 1589 #if !defined(CONFIG_M5272) 1590 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of 1591 * FEC_RACC_SHIFT16 is set by default in the probe function. 1592 */ 1593 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1594 data_start += 2; 1595 sub_len += 2; 1596 } 1597 #endif 1598 1599 #ifdef CONFIG_M532x 1600 flush_cache_all(); 1601 #endif 1602 rxq = fep->rx_queue[queue_id]; 1603 1604 /* First, grab all of the stats for the incoming packet. 1605 * These get messed up if we get called due to a busy condition. 1606 */ 1607 bdp = rxq->bd.cur; 1608 xdp_init_buff(&xdp, PAGE_SIZE, &rxq->xdp_rxq); 1609 1610 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1611 1612 if (pkt_received >= budget) 1613 break; 1614 pkt_received++; 1615 1616 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); 1617 1618 /* Check for errors. */ 1619 status ^= BD_ENET_RX_LAST; 1620 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1621 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1622 BD_ENET_RX_CL)) { 1623 ndev->stats.rx_errors++; 1624 if (status & BD_ENET_RX_OV) { 1625 /* FIFO overrun */ 1626 ndev->stats.rx_fifo_errors++; 1627 goto rx_processing_done; 1628 } 1629 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1630 | BD_ENET_RX_LAST)) { 1631 /* Frame too long or too short. */ 1632 ndev->stats.rx_length_errors++; 1633 if (status & BD_ENET_RX_LAST) 1634 netdev_err(ndev, "rcv is not +last\n"); 1635 } 1636 if (status & BD_ENET_RX_CR) /* CRC Error */ 1637 ndev->stats.rx_crc_errors++; 1638 /* Report late collisions as a frame error. */ 1639 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1640 ndev->stats.rx_frame_errors++; 1641 goto rx_processing_done; 1642 } 1643 1644 /* Process the incoming frame. */ 1645 ndev->stats.rx_packets++; 1646 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1647 ndev->stats.rx_bytes += pkt_len; 1648 1649 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1650 page = rxq->rx_skb_info[index].page; 1651 dma_sync_single_for_cpu(&fep->pdev->dev, 1652 fec32_to_cpu(bdp->cbd_bufaddr), 1653 pkt_len, 1654 DMA_FROM_DEVICE); 1655 prefetch(page_address(page)); 1656 fec_enet_update_cbd(rxq, bdp, index); 1657 1658 if (xdp_prog) { 1659 xdp_buff_clear_frags_flag(&xdp); 1660 /* subtract 16bit shift and FCS */ 1661 xdp_prepare_buff(&xdp, page_address(page), 1662 data_start, pkt_len - sub_len, false); 1663 ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, index); 1664 xdp_result |= ret; 1665 if (ret != FEC_ENET_XDP_PASS) 1666 goto rx_processing_done; 1667 } 1668 1669 /* The packet length includes FCS, but we don't want to 1670 * include that when passing upstream as it messes up 1671 * bridging applications. 1672 */ 1673 skb = build_skb(page_address(page), PAGE_SIZE); 1674 skb_reserve(skb, data_start); 1675 skb_put(skb, pkt_len - sub_len); 1676 skb_mark_for_recycle(skb); 1677 1678 if (unlikely(need_swap)) { 1679 data = page_address(page) + FEC_ENET_XDP_HEADROOM; 1680 swap_buffer(data, pkt_len); 1681 } 1682 data = skb->data; 1683 1684 /* Extract the enhanced buffer descriptor */ 1685 ebdp = NULL; 1686 if (fep->bufdesc_ex) 1687 ebdp = (struct bufdesc_ex *)bdp; 1688 1689 /* If this is a VLAN packet remove the VLAN Tag */ 1690 vlan_packet_rcvd = false; 1691 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1692 fep->bufdesc_ex && 1693 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1694 /* Push and remove the vlan tag */ 1695 struct vlan_hdr *vlan_header = 1696 (struct vlan_hdr *) (data + ETH_HLEN); 1697 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1698 1699 vlan_packet_rcvd = true; 1700 1701 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1702 skb_pull(skb, VLAN_HLEN); 1703 } 1704 1705 skb->protocol = eth_type_trans(skb, ndev); 1706 1707 /* Get receive timestamp from the skb */ 1708 if (fep->hwts_rx_en && fep->bufdesc_ex) 1709 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1710 skb_hwtstamps(skb)); 1711 1712 if (fep->bufdesc_ex && 1713 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1714 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1715 /* don't check it */ 1716 skb->ip_summed = CHECKSUM_UNNECESSARY; 1717 } else { 1718 skb_checksum_none_assert(skb); 1719 } 1720 } 1721 1722 /* Handle received VLAN packets */ 1723 if (vlan_packet_rcvd) 1724 __vlan_hwaccel_put_tag(skb, 1725 htons(ETH_P_8021Q), 1726 vlan_tag); 1727 1728 skb_record_rx_queue(skb, queue_id); 1729 napi_gro_receive(&fep->napi, skb); 1730 1731 rx_processing_done: 1732 /* Clear the status flags for this buffer */ 1733 status &= ~BD_ENET_RX_STATS; 1734 1735 /* Mark the buffer empty */ 1736 status |= BD_ENET_RX_EMPTY; 1737 1738 if (fep->bufdesc_ex) { 1739 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1740 1741 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1742 ebdp->cbd_prot = 0; 1743 ebdp->cbd_bdu = 0; 1744 } 1745 /* Make sure the updates to rest of the descriptor are 1746 * performed before transferring ownership. 1747 */ 1748 wmb(); 1749 bdp->cbd_sc = cpu_to_fec16(status); 1750 1751 /* Update BD pointer to next entry */ 1752 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1753 1754 /* Doing this here will keep the FEC running while we process 1755 * incoming frames. On a heavily loaded network, we should be 1756 * able to keep up at the expense of system resources. 1757 */ 1758 writel(0, rxq->bd.reg_desc_active); 1759 } 1760 rxq->bd.cur = bdp; 1761 1762 if (xdp_result & FEC_ENET_XDP_REDIR) 1763 xdp_do_flush_map(); 1764 1765 return pkt_received; 1766 } 1767 1768 static int fec_enet_rx(struct net_device *ndev, int budget) 1769 { 1770 struct fec_enet_private *fep = netdev_priv(ndev); 1771 int i, done = 0; 1772 1773 /* Make sure that AVB queues are processed first. */ 1774 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1775 done += fec_enet_rx_queue(ndev, budget - done, i); 1776 1777 return done; 1778 } 1779 1780 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1781 { 1782 uint int_events; 1783 1784 int_events = readl(fep->hwp + FEC_IEVENT); 1785 1786 /* Don't clear MDIO events, we poll for those */ 1787 int_events &= ~FEC_ENET_MII; 1788 1789 writel(int_events, fep->hwp + FEC_IEVENT); 1790 1791 return int_events != 0; 1792 } 1793 1794 static irqreturn_t 1795 fec_enet_interrupt(int irq, void *dev_id) 1796 { 1797 struct net_device *ndev = dev_id; 1798 struct fec_enet_private *fep = netdev_priv(ndev); 1799 irqreturn_t ret = IRQ_NONE; 1800 1801 if (fec_enet_collect_events(fep) && fep->link) { 1802 ret = IRQ_HANDLED; 1803 1804 if (napi_schedule_prep(&fep->napi)) { 1805 /* Disable interrupts */ 1806 writel(0, fep->hwp + FEC_IMASK); 1807 __napi_schedule(&fep->napi); 1808 } 1809 } 1810 1811 return ret; 1812 } 1813 1814 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1815 { 1816 struct net_device *ndev = napi->dev; 1817 struct fec_enet_private *fep = netdev_priv(ndev); 1818 int done = 0; 1819 1820 do { 1821 done += fec_enet_rx(ndev, budget - done); 1822 fec_enet_tx(ndev); 1823 } while ((done < budget) && fec_enet_collect_events(fep)); 1824 1825 if (done < budget) { 1826 napi_complete_done(napi, done); 1827 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1828 } 1829 1830 return done; 1831 } 1832 1833 /* ------------------------------------------------------------------------- */ 1834 static int fec_get_mac(struct net_device *ndev) 1835 { 1836 struct fec_enet_private *fep = netdev_priv(ndev); 1837 unsigned char *iap, tmpaddr[ETH_ALEN]; 1838 int ret; 1839 1840 /* 1841 * try to get mac address in following order: 1842 * 1843 * 1) module parameter via kernel command line in form 1844 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1845 */ 1846 iap = macaddr; 1847 1848 /* 1849 * 2) from device tree data 1850 */ 1851 if (!is_valid_ether_addr(iap)) { 1852 struct device_node *np = fep->pdev->dev.of_node; 1853 if (np) { 1854 ret = of_get_mac_address(np, tmpaddr); 1855 if (!ret) 1856 iap = tmpaddr; 1857 else if (ret == -EPROBE_DEFER) 1858 return ret; 1859 } 1860 } 1861 1862 /* 1863 * 3) from flash or fuse (via platform data) 1864 */ 1865 if (!is_valid_ether_addr(iap)) { 1866 #ifdef CONFIG_M5272 1867 if (FEC_FLASHMAC) 1868 iap = (unsigned char *)FEC_FLASHMAC; 1869 #else 1870 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1871 1872 if (pdata) 1873 iap = (unsigned char *)&pdata->mac; 1874 #endif 1875 } 1876 1877 /* 1878 * 4) FEC mac registers set by bootloader 1879 */ 1880 if (!is_valid_ether_addr(iap)) { 1881 *((__be32 *) &tmpaddr[0]) = 1882 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1883 *((__be16 *) &tmpaddr[4]) = 1884 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1885 iap = &tmpaddr[0]; 1886 } 1887 1888 /* 1889 * 5) random mac address 1890 */ 1891 if (!is_valid_ether_addr(iap)) { 1892 /* Report it and use a random ethernet address instead */ 1893 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1894 eth_hw_addr_random(ndev); 1895 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1896 ndev->dev_addr); 1897 return 0; 1898 } 1899 1900 /* Adjust MAC if using macaddr */ 1901 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); 1902 1903 return 0; 1904 } 1905 1906 /* ------------------------------------------------------------------------- */ 1907 1908 /* 1909 * Phy section 1910 */ 1911 static void fec_enet_adjust_link(struct net_device *ndev) 1912 { 1913 struct fec_enet_private *fep = netdev_priv(ndev); 1914 struct phy_device *phy_dev = ndev->phydev; 1915 int status_change = 0; 1916 1917 /* 1918 * If the netdev is down, or is going down, we're not interested 1919 * in link state events, so just mark our idea of the link as down 1920 * and ignore the event. 1921 */ 1922 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1923 fep->link = 0; 1924 } else if (phy_dev->link) { 1925 if (!fep->link) { 1926 fep->link = phy_dev->link; 1927 status_change = 1; 1928 } 1929 1930 if (fep->full_duplex != phy_dev->duplex) { 1931 fep->full_duplex = phy_dev->duplex; 1932 status_change = 1; 1933 } 1934 1935 if (phy_dev->speed != fep->speed) { 1936 fep->speed = phy_dev->speed; 1937 status_change = 1; 1938 } 1939 1940 /* if any of the above changed restart the FEC */ 1941 if (status_change) { 1942 napi_disable(&fep->napi); 1943 netif_tx_lock_bh(ndev); 1944 fec_restart(ndev); 1945 netif_tx_wake_all_queues(ndev); 1946 netif_tx_unlock_bh(ndev); 1947 napi_enable(&fep->napi); 1948 } 1949 } else { 1950 if (fep->link) { 1951 napi_disable(&fep->napi); 1952 netif_tx_lock_bh(ndev); 1953 fec_stop(ndev); 1954 netif_tx_unlock_bh(ndev); 1955 napi_enable(&fep->napi); 1956 fep->link = phy_dev->link; 1957 status_change = 1; 1958 } 1959 } 1960 1961 if (status_change) 1962 phy_print_status(phy_dev); 1963 } 1964 1965 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 1966 { 1967 uint ievent; 1968 int ret; 1969 1970 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 1971 ievent & FEC_ENET_MII, 2, 30000); 1972 1973 if (!ret) 1974 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 1975 1976 return ret; 1977 } 1978 1979 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1980 { 1981 struct fec_enet_private *fep = bus->priv; 1982 struct device *dev = &fep->pdev->dev; 1983 int ret = 0, frame_start, frame_addr, frame_op; 1984 bool is_c45 = !!(regnum & MII_ADDR_C45); 1985 1986 ret = pm_runtime_resume_and_get(dev); 1987 if (ret < 0) 1988 return ret; 1989 1990 if (is_c45) { 1991 frame_start = FEC_MMFR_ST_C45; 1992 1993 /* write address */ 1994 frame_addr = (regnum >> 16); 1995 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1996 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1997 FEC_MMFR_TA | (regnum & 0xFFFF), 1998 fep->hwp + FEC_MII_DATA); 1999 2000 /* wait for end of transfer */ 2001 ret = fec_enet_mdio_wait(fep); 2002 if (ret) { 2003 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2004 goto out; 2005 } 2006 2007 frame_op = FEC_MMFR_OP_READ_C45; 2008 2009 } else { 2010 /* C22 read */ 2011 frame_op = FEC_MMFR_OP_READ; 2012 frame_start = FEC_MMFR_ST; 2013 frame_addr = regnum; 2014 } 2015 2016 /* start a read op */ 2017 writel(frame_start | frame_op | 2018 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2019 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2020 2021 /* wait for end of transfer */ 2022 ret = fec_enet_mdio_wait(fep); 2023 if (ret) { 2024 netdev_err(fep->netdev, "MDIO read timeout\n"); 2025 goto out; 2026 } 2027 2028 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2029 2030 out: 2031 pm_runtime_mark_last_busy(dev); 2032 pm_runtime_put_autosuspend(dev); 2033 2034 return ret; 2035 } 2036 2037 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 2038 u16 value) 2039 { 2040 struct fec_enet_private *fep = bus->priv; 2041 struct device *dev = &fep->pdev->dev; 2042 int ret, frame_start, frame_addr; 2043 bool is_c45 = !!(regnum & MII_ADDR_C45); 2044 2045 ret = pm_runtime_resume_and_get(dev); 2046 if (ret < 0) 2047 return ret; 2048 2049 if (is_c45) { 2050 frame_start = FEC_MMFR_ST_C45; 2051 2052 /* write address */ 2053 frame_addr = (regnum >> 16); 2054 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2055 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2056 FEC_MMFR_TA | (regnum & 0xFFFF), 2057 fep->hwp + FEC_MII_DATA); 2058 2059 /* wait for end of transfer */ 2060 ret = fec_enet_mdio_wait(fep); 2061 if (ret) { 2062 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2063 goto out; 2064 } 2065 } else { 2066 /* C22 write */ 2067 frame_start = FEC_MMFR_ST; 2068 frame_addr = regnum; 2069 } 2070 2071 /* start a write op */ 2072 writel(frame_start | FEC_MMFR_OP_WRITE | 2073 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2074 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2075 fep->hwp + FEC_MII_DATA); 2076 2077 /* wait for end of transfer */ 2078 ret = fec_enet_mdio_wait(fep); 2079 if (ret) 2080 netdev_err(fep->netdev, "MDIO write timeout\n"); 2081 2082 out: 2083 pm_runtime_mark_last_busy(dev); 2084 pm_runtime_put_autosuspend(dev); 2085 2086 return ret; 2087 } 2088 2089 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 2090 { 2091 struct fec_enet_private *fep = netdev_priv(ndev); 2092 struct phy_device *phy_dev = ndev->phydev; 2093 2094 if (phy_dev) { 2095 phy_reset_after_clk_enable(phy_dev); 2096 } else if (fep->phy_node) { 2097 /* 2098 * If the PHY still is not bound to the MAC, but there is 2099 * OF PHY node and a matching PHY device instance already, 2100 * use the OF PHY node to obtain the PHY device instance, 2101 * and then use that PHY device instance when triggering 2102 * the PHY reset. 2103 */ 2104 phy_dev = of_phy_find_device(fep->phy_node); 2105 phy_reset_after_clk_enable(phy_dev); 2106 put_device(&phy_dev->mdio.dev); 2107 } 2108 } 2109 2110 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 2111 { 2112 struct fec_enet_private *fep = netdev_priv(ndev); 2113 int ret; 2114 2115 if (enable) { 2116 ret = clk_prepare_enable(fep->clk_enet_out); 2117 if (ret) 2118 return ret; 2119 2120 if (fep->clk_ptp) { 2121 mutex_lock(&fep->ptp_clk_mutex); 2122 ret = clk_prepare_enable(fep->clk_ptp); 2123 if (ret) { 2124 mutex_unlock(&fep->ptp_clk_mutex); 2125 goto failed_clk_ptp; 2126 } else { 2127 fep->ptp_clk_on = true; 2128 } 2129 mutex_unlock(&fep->ptp_clk_mutex); 2130 } 2131 2132 ret = clk_prepare_enable(fep->clk_ref); 2133 if (ret) 2134 goto failed_clk_ref; 2135 2136 ret = clk_prepare_enable(fep->clk_2x_txclk); 2137 if (ret) 2138 goto failed_clk_2x_txclk; 2139 2140 fec_enet_phy_reset_after_clk_enable(ndev); 2141 } else { 2142 clk_disable_unprepare(fep->clk_enet_out); 2143 if (fep->clk_ptp) { 2144 mutex_lock(&fep->ptp_clk_mutex); 2145 clk_disable_unprepare(fep->clk_ptp); 2146 fep->ptp_clk_on = false; 2147 mutex_unlock(&fep->ptp_clk_mutex); 2148 } 2149 clk_disable_unprepare(fep->clk_ref); 2150 clk_disable_unprepare(fep->clk_2x_txclk); 2151 } 2152 2153 return 0; 2154 2155 failed_clk_2x_txclk: 2156 if (fep->clk_ref) 2157 clk_disable_unprepare(fep->clk_ref); 2158 failed_clk_ref: 2159 if (fep->clk_ptp) { 2160 mutex_lock(&fep->ptp_clk_mutex); 2161 clk_disable_unprepare(fep->clk_ptp); 2162 fep->ptp_clk_on = false; 2163 mutex_unlock(&fep->ptp_clk_mutex); 2164 } 2165 failed_clk_ptp: 2166 clk_disable_unprepare(fep->clk_enet_out); 2167 2168 return ret; 2169 } 2170 2171 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2172 struct device_node *np) 2173 { 2174 u32 rgmii_tx_delay, rgmii_rx_delay; 2175 2176 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2177 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2178 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2179 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2180 return -EINVAL; 2181 } else if (rgmii_tx_delay == 2000) { 2182 fep->rgmii_txc_dly = true; 2183 } 2184 } 2185 2186 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2187 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2188 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2189 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2190 return -EINVAL; 2191 } else if (rgmii_rx_delay == 2000) { 2192 fep->rgmii_rxc_dly = true; 2193 } 2194 } 2195 2196 return 0; 2197 } 2198 2199 static int fec_enet_mii_probe(struct net_device *ndev) 2200 { 2201 struct fec_enet_private *fep = netdev_priv(ndev); 2202 struct phy_device *phy_dev = NULL; 2203 char mdio_bus_id[MII_BUS_ID_SIZE]; 2204 char phy_name[MII_BUS_ID_SIZE + 3]; 2205 int phy_id; 2206 int dev_id = fep->dev_id; 2207 2208 if (fep->phy_node) { 2209 phy_dev = of_phy_connect(ndev, fep->phy_node, 2210 &fec_enet_adjust_link, 0, 2211 fep->phy_interface); 2212 if (!phy_dev) { 2213 netdev_err(ndev, "Unable to connect to phy\n"); 2214 return -ENODEV; 2215 } 2216 } else { 2217 /* check for attached phy */ 2218 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2219 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2220 continue; 2221 if (dev_id--) 2222 continue; 2223 strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2224 break; 2225 } 2226 2227 if (phy_id >= PHY_MAX_ADDR) { 2228 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2229 strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2230 phy_id = 0; 2231 } 2232 2233 snprintf(phy_name, sizeof(phy_name), 2234 PHY_ID_FMT, mdio_bus_id, phy_id); 2235 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2236 fep->phy_interface); 2237 } 2238 2239 if (IS_ERR(phy_dev)) { 2240 netdev_err(ndev, "could not attach to PHY\n"); 2241 return PTR_ERR(phy_dev); 2242 } 2243 2244 /* mask with MAC supported features */ 2245 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2246 phy_set_max_speed(phy_dev, 1000); 2247 phy_remove_link_mode(phy_dev, 2248 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2249 #if !defined(CONFIG_M5272) 2250 phy_support_sym_pause(phy_dev); 2251 #endif 2252 } 2253 else 2254 phy_set_max_speed(phy_dev, 100); 2255 2256 fep->link = 0; 2257 fep->full_duplex = 0; 2258 2259 phy_dev->mac_managed_pm = true; 2260 2261 phy_attached_info(phy_dev); 2262 2263 return 0; 2264 } 2265 2266 static int fec_enet_mii_init(struct platform_device *pdev) 2267 { 2268 static struct mii_bus *fec0_mii_bus; 2269 struct net_device *ndev = platform_get_drvdata(pdev); 2270 struct fec_enet_private *fep = netdev_priv(ndev); 2271 bool suppress_preamble = false; 2272 struct device_node *node; 2273 int err = -ENXIO; 2274 u32 mii_speed, holdtime; 2275 u32 bus_freq; 2276 2277 /* 2278 * The i.MX28 dual fec interfaces are not equal. 2279 * Here are the differences: 2280 * 2281 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2282 * - fec0 acts as the 1588 time master while fec1 is slave 2283 * - external phys can only be configured by fec0 2284 * 2285 * That is to say fec1 can not work independently. It only works 2286 * when fec0 is working. The reason behind this design is that the 2287 * second interface is added primarily for Switch mode. 2288 * 2289 * Because of the last point above, both phys are attached on fec0 2290 * mdio interface in board design, and need to be configured by 2291 * fec0 mii_bus. 2292 */ 2293 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2294 /* fec1 uses fec0 mii_bus */ 2295 if (mii_cnt && fec0_mii_bus) { 2296 fep->mii_bus = fec0_mii_bus; 2297 mii_cnt++; 2298 return 0; 2299 } 2300 return -ENOENT; 2301 } 2302 2303 bus_freq = 2500000; /* 2.5MHz by default */ 2304 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2305 if (node) { 2306 of_property_read_u32(node, "clock-frequency", &bus_freq); 2307 suppress_preamble = of_property_read_bool(node, 2308 "suppress-preamble"); 2309 } 2310 2311 /* 2312 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2313 * 2314 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2315 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2316 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2317 * document. 2318 */ 2319 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2320 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2321 mii_speed--; 2322 if (mii_speed > 63) { 2323 dev_err(&pdev->dev, 2324 "fec clock (%lu) too fast to get right mii speed\n", 2325 clk_get_rate(fep->clk_ipg)); 2326 err = -EINVAL; 2327 goto err_out; 2328 } 2329 2330 /* 2331 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2332 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2333 * versions are RAZ there, so just ignore the difference and write the 2334 * register always. 2335 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2336 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2337 * output. 2338 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2339 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2340 * holdtime cannot result in a value greater than 3. 2341 */ 2342 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2343 2344 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2345 2346 if (suppress_preamble) 2347 fep->phy_speed |= BIT(7); 2348 2349 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2350 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2351 * MII event generation condition: 2352 * - writing MSCR: 2353 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2354 * mscr_reg_data_in[7:0] != 0 2355 * - writing MMFR: 2356 * - mscr[7:0]_not_zero 2357 */ 2358 writel(0, fep->hwp + FEC_MII_DATA); 2359 } 2360 2361 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2362 2363 /* Clear any pending transaction complete indication */ 2364 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2365 2366 fep->mii_bus = mdiobus_alloc(); 2367 if (fep->mii_bus == NULL) { 2368 err = -ENOMEM; 2369 goto err_out; 2370 } 2371 2372 fep->mii_bus->name = "fec_enet_mii_bus"; 2373 fep->mii_bus->read = fec_enet_mdio_read; 2374 fep->mii_bus->write = fec_enet_mdio_write; 2375 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2376 pdev->name, fep->dev_id + 1); 2377 fep->mii_bus->priv = fep; 2378 fep->mii_bus->parent = &pdev->dev; 2379 2380 err = of_mdiobus_register(fep->mii_bus, node); 2381 if (err) 2382 goto err_out_free_mdiobus; 2383 of_node_put(node); 2384 2385 mii_cnt++; 2386 2387 /* save fec0 mii_bus */ 2388 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2389 fec0_mii_bus = fep->mii_bus; 2390 2391 return 0; 2392 2393 err_out_free_mdiobus: 2394 mdiobus_free(fep->mii_bus); 2395 err_out: 2396 of_node_put(node); 2397 return err; 2398 } 2399 2400 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2401 { 2402 if (--mii_cnt == 0) { 2403 mdiobus_unregister(fep->mii_bus); 2404 mdiobus_free(fep->mii_bus); 2405 } 2406 } 2407 2408 static void fec_enet_get_drvinfo(struct net_device *ndev, 2409 struct ethtool_drvinfo *info) 2410 { 2411 struct fec_enet_private *fep = netdev_priv(ndev); 2412 2413 strscpy(info->driver, fep->pdev->dev.driver->name, 2414 sizeof(info->driver)); 2415 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2416 } 2417 2418 static int fec_enet_get_regs_len(struct net_device *ndev) 2419 { 2420 struct fec_enet_private *fep = netdev_priv(ndev); 2421 struct resource *r; 2422 int s = 0; 2423 2424 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2425 if (r) 2426 s = resource_size(r); 2427 2428 return s; 2429 } 2430 2431 /* List of registers that can be safety be read to dump them with ethtool */ 2432 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2433 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2434 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2435 static __u32 fec_enet_register_version = 2; 2436 static u32 fec_enet_register_offset[] = { 2437 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2438 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2439 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2440 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2441 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2442 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2443 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2444 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2445 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2446 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2447 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2448 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2449 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2450 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2451 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2452 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2453 RMON_T_P_GTE2048, RMON_T_OCTETS, 2454 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2455 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2456 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2457 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2458 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2459 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2460 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2461 RMON_R_P_GTE2048, RMON_R_OCTETS, 2462 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2463 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2464 }; 2465 /* for i.MX6ul */ 2466 static u32 fec_enet_register_offset_6ul[] = { 2467 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2468 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2469 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0, 2470 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, 2471 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0, 2472 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2473 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, 2474 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2475 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2476 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2477 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2478 RMON_T_P_GTE2048, RMON_T_OCTETS, 2479 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2480 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2481 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2482 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2483 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2484 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2485 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2486 RMON_R_P_GTE2048, RMON_R_OCTETS, 2487 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2488 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2489 }; 2490 #else 2491 static __u32 fec_enet_register_version = 1; 2492 static u32 fec_enet_register_offset[] = { 2493 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2494 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2495 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2496 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2497 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2498 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2499 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2500 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2501 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2502 }; 2503 #endif 2504 2505 static void fec_enet_get_regs(struct net_device *ndev, 2506 struct ethtool_regs *regs, void *regbuf) 2507 { 2508 struct fec_enet_private *fep = netdev_priv(ndev); 2509 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2510 struct device *dev = &fep->pdev->dev; 2511 u32 *buf = (u32 *)regbuf; 2512 u32 i, off; 2513 int ret; 2514 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2515 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2516 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2517 u32 *reg_list; 2518 u32 reg_cnt; 2519 2520 if (!of_machine_is_compatible("fsl,imx6ul")) { 2521 reg_list = fec_enet_register_offset; 2522 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2523 } else { 2524 reg_list = fec_enet_register_offset_6ul; 2525 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul); 2526 } 2527 #else 2528 /* coldfire */ 2529 static u32 *reg_list = fec_enet_register_offset; 2530 static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2531 #endif 2532 ret = pm_runtime_resume_and_get(dev); 2533 if (ret < 0) 2534 return; 2535 2536 regs->version = fec_enet_register_version; 2537 2538 memset(buf, 0, regs->len); 2539 2540 for (i = 0; i < reg_cnt; i++) { 2541 off = reg_list[i]; 2542 2543 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2544 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2545 continue; 2546 2547 off >>= 2; 2548 buf[off] = readl(&theregs[off]); 2549 } 2550 2551 pm_runtime_mark_last_busy(dev); 2552 pm_runtime_put_autosuspend(dev); 2553 } 2554 2555 static int fec_enet_get_ts_info(struct net_device *ndev, 2556 struct ethtool_ts_info *info) 2557 { 2558 struct fec_enet_private *fep = netdev_priv(ndev); 2559 2560 if (fep->bufdesc_ex) { 2561 2562 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2563 SOF_TIMESTAMPING_RX_SOFTWARE | 2564 SOF_TIMESTAMPING_SOFTWARE | 2565 SOF_TIMESTAMPING_TX_HARDWARE | 2566 SOF_TIMESTAMPING_RX_HARDWARE | 2567 SOF_TIMESTAMPING_RAW_HARDWARE; 2568 if (fep->ptp_clock) 2569 info->phc_index = ptp_clock_index(fep->ptp_clock); 2570 else 2571 info->phc_index = -1; 2572 2573 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2574 (1 << HWTSTAMP_TX_ON); 2575 2576 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2577 (1 << HWTSTAMP_FILTER_ALL); 2578 return 0; 2579 } else { 2580 return ethtool_op_get_ts_info(ndev, info); 2581 } 2582 } 2583 2584 #if !defined(CONFIG_M5272) 2585 2586 static void fec_enet_get_pauseparam(struct net_device *ndev, 2587 struct ethtool_pauseparam *pause) 2588 { 2589 struct fec_enet_private *fep = netdev_priv(ndev); 2590 2591 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2592 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2593 pause->rx_pause = pause->tx_pause; 2594 } 2595 2596 static int fec_enet_set_pauseparam(struct net_device *ndev, 2597 struct ethtool_pauseparam *pause) 2598 { 2599 struct fec_enet_private *fep = netdev_priv(ndev); 2600 2601 if (!ndev->phydev) 2602 return -ENODEV; 2603 2604 if (pause->tx_pause != pause->rx_pause) { 2605 netdev_info(ndev, 2606 "hardware only support enable/disable both tx and rx"); 2607 return -EINVAL; 2608 } 2609 2610 fep->pause_flag = 0; 2611 2612 /* tx pause must be same as rx pause */ 2613 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2614 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2615 2616 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2617 pause->autoneg); 2618 2619 if (pause->autoneg) { 2620 if (netif_running(ndev)) 2621 fec_stop(ndev); 2622 phy_start_aneg(ndev->phydev); 2623 } 2624 if (netif_running(ndev)) { 2625 napi_disable(&fep->napi); 2626 netif_tx_lock_bh(ndev); 2627 fec_restart(ndev); 2628 netif_tx_wake_all_queues(ndev); 2629 netif_tx_unlock_bh(ndev); 2630 napi_enable(&fep->napi); 2631 } 2632 2633 return 0; 2634 } 2635 2636 static const struct fec_stat { 2637 char name[ETH_GSTRING_LEN]; 2638 u16 offset; 2639 } fec_stats[] = { 2640 /* RMON TX */ 2641 { "tx_dropped", RMON_T_DROP }, 2642 { "tx_packets", RMON_T_PACKETS }, 2643 { "tx_broadcast", RMON_T_BC_PKT }, 2644 { "tx_multicast", RMON_T_MC_PKT }, 2645 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2646 { "tx_undersize", RMON_T_UNDERSIZE }, 2647 { "tx_oversize", RMON_T_OVERSIZE }, 2648 { "tx_fragment", RMON_T_FRAG }, 2649 { "tx_jabber", RMON_T_JAB }, 2650 { "tx_collision", RMON_T_COL }, 2651 { "tx_64byte", RMON_T_P64 }, 2652 { "tx_65to127byte", RMON_T_P65TO127 }, 2653 { "tx_128to255byte", RMON_T_P128TO255 }, 2654 { "tx_256to511byte", RMON_T_P256TO511 }, 2655 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2656 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2657 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2658 { "tx_octets", RMON_T_OCTETS }, 2659 2660 /* IEEE TX */ 2661 { "IEEE_tx_drop", IEEE_T_DROP }, 2662 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2663 { "IEEE_tx_1col", IEEE_T_1COL }, 2664 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2665 { "IEEE_tx_def", IEEE_T_DEF }, 2666 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2667 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2668 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2669 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2670 { "IEEE_tx_sqe", IEEE_T_SQE }, 2671 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2672 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2673 2674 /* RMON RX */ 2675 { "rx_packets", RMON_R_PACKETS }, 2676 { "rx_broadcast", RMON_R_BC_PKT }, 2677 { "rx_multicast", RMON_R_MC_PKT }, 2678 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2679 { "rx_undersize", RMON_R_UNDERSIZE }, 2680 { "rx_oversize", RMON_R_OVERSIZE }, 2681 { "rx_fragment", RMON_R_FRAG }, 2682 { "rx_jabber", RMON_R_JAB }, 2683 { "rx_64byte", RMON_R_P64 }, 2684 { "rx_65to127byte", RMON_R_P65TO127 }, 2685 { "rx_128to255byte", RMON_R_P128TO255 }, 2686 { "rx_256to511byte", RMON_R_P256TO511 }, 2687 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2688 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2689 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2690 { "rx_octets", RMON_R_OCTETS }, 2691 2692 /* IEEE RX */ 2693 { "IEEE_rx_drop", IEEE_R_DROP }, 2694 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2695 { "IEEE_rx_crc", IEEE_R_CRC }, 2696 { "IEEE_rx_align", IEEE_R_ALIGN }, 2697 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2698 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2699 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2700 }; 2701 2702 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2703 2704 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2705 { 2706 struct fec_enet_private *fep = netdev_priv(dev); 2707 int i; 2708 2709 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2710 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2711 } 2712 2713 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2714 struct ethtool_stats *stats, u64 *data) 2715 { 2716 struct fec_enet_private *fep = netdev_priv(dev); 2717 2718 if (netif_running(dev)) 2719 fec_enet_update_ethtool_stats(dev); 2720 2721 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2722 } 2723 2724 static void fec_enet_get_strings(struct net_device *netdev, 2725 u32 stringset, u8 *data) 2726 { 2727 int i; 2728 switch (stringset) { 2729 case ETH_SS_STATS: 2730 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2731 memcpy(data + i * ETH_GSTRING_LEN, 2732 fec_stats[i].name, ETH_GSTRING_LEN); 2733 break; 2734 case ETH_SS_TEST: 2735 net_selftest_get_strings(data); 2736 break; 2737 } 2738 } 2739 2740 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2741 { 2742 switch (sset) { 2743 case ETH_SS_STATS: 2744 return ARRAY_SIZE(fec_stats); 2745 case ETH_SS_TEST: 2746 return net_selftest_get_count(); 2747 default: 2748 return -EOPNOTSUPP; 2749 } 2750 } 2751 2752 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2753 { 2754 struct fec_enet_private *fep = netdev_priv(dev); 2755 int i; 2756 2757 /* Disable MIB statistics counters */ 2758 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2759 2760 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2761 writel(0, fep->hwp + fec_stats[i].offset); 2762 2763 /* Don't disable MIB statistics counters */ 2764 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2765 } 2766 2767 #else /* !defined(CONFIG_M5272) */ 2768 #define FEC_STATS_SIZE 0 2769 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2770 { 2771 } 2772 2773 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2774 { 2775 } 2776 #endif /* !defined(CONFIG_M5272) */ 2777 2778 /* ITR clock source is enet system clock (clk_ahb). 2779 * TCTT unit is cycle_ns * 64 cycle 2780 * So, the ICTT value = X us / (cycle_ns * 64) 2781 */ 2782 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2783 { 2784 struct fec_enet_private *fep = netdev_priv(ndev); 2785 2786 return us * (fep->itr_clk_rate / 64000) / 1000; 2787 } 2788 2789 /* Set threshold for interrupt coalescing */ 2790 static void fec_enet_itr_coal_set(struct net_device *ndev) 2791 { 2792 struct fec_enet_private *fep = netdev_priv(ndev); 2793 int rx_itr, tx_itr; 2794 2795 /* Must be greater than zero to avoid unpredictable behavior */ 2796 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2797 !fep->tx_time_itr || !fep->tx_pkts_itr) 2798 return; 2799 2800 /* Select enet system clock as Interrupt Coalescing 2801 * timer Clock Source 2802 */ 2803 rx_itr = FEC_ITR_CLK_SEL; 2804 tx_itr = FEC_ITR_CLK_SEL; 2805 2806 /* set ICFT and ICTT */ 2807 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2808 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2809 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2810 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2811 2812 rx_itr |= FEC_ITR_EN; 2813 tx_itr |= FEC_ITR_EN; 2814 2815 writel(tx_itr, fep->hwp + FEC_TXIC0); 2816 writel(rx_itr, fep->hwp + FEC_RXIC0); 2817 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 2818 writel(tx_itr, fep->hwp + FEC_TXIC1); 2819 writel(rx_itr, fep->hwp + FEC_RXIC1); 2820 writel(tx_itr, fep->hwp + FEC_TXIC2); 2821 writel(rx_itr, fep->hwp + FEC_RXIC2); 2822 } 2823 } 2824 2825 static int fec_enet_get_coalesce(struct net_device *ndev, 2826 struct ethtool_coalesce *ec, 2827 struct kernel_ethtool_coalesce *kernel_coal, 2828 struct netlink_ext_ack *extack) 2829 { 2830 struct fec_enet_private *fep = netdev_priv(ndev); 2831 2832 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2833 return -EOPNOTSUPP; 2834 2835 ec->rx_coalesce_usecs = fep->rx_time_itr; 2836 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2837 2838 ec->tx_coalesce_usecs = fep->tx_time_itr; 2839 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2840 2841 return 0; 2842 } 2843 2844 static int fec_enet_set_coalesce(struct net_device *ndev, 2845 struct ethtool_coalesce *ec, 2846 struct kernel_ethtool_coalesce *kernel_coal, 2847 struct netlink_ext_ack *extack) 2848 { 2849 struct fec_enet_private *fep = netdev_priv(ndev); 2850 struct device *dev = &fep->pdev->dev; 2851 unsigned int cycle; 2852 2853 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2854 return -EOPNOTSUPP; 2855 2856 if (ec->rx_max_coalesced_frames > 255) { 2857 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 2858 return -EINVAL; 2859 } 2860 2861 if (ec->tx_max_coalesced_frames > 255) { 2862 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 2863 return -EINVAL; 2864 } 2865 2866 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 2867 if (cycle > 0xFFFF) { 2868 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 2869 return -EINVAL; 2870 } 2871 2872 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 2873 if (cycle > 0xFFFF) { 2874 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 2875 return -EINVAL; 2876 } 2877 2878 fep->rx_time_itr = ec->rx_coalesce_usecs; 2879 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2880 2881 fep->tx_time_itr = ec->tx_coalesce_usecs; 2882 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2883 2884 fec_enet_itr_coal_set(ndev); 2885 2886 return 0; 2887 } 2888 2889 static void fec_enet_itr_coal_init(struct net_device *ndev) 2890 { 2891 struct ethtool_coalesce ec; 2892 2893 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2894 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2895 2896 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2897 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2898 2899 fec_enet_set_coalesce(ndev, &ec, NULL, NULL); 2900 } 2901 2902 static int fec_enet_get_tunable(struct net_device *netdev, 2903 const struct ethtool_tunable *tuna, 2904 void *data) 2905 { 2906 struct fec_enet_private *fep = netdev_priv(netdev); 2907 int ret = 0; 2908 2909 switch (tuna->id) { 2910 case ETHTOOL_RX_COPYBREAK: 2911 *(u32 *)data = fep->rx_copybreak; 2912 break; 2913 default: 2914 ret = -EINVAL; 2915 break; 2916 } 2917 2918 return ret; 2919 } 2920 2921 static int fec_enet_set_tunable(struct net_device *netdev, 2922 const struct ethtool_tunable *tuna, 2923 const void *data) 2924 { 2925 struct fec_enet_private *fep = netdev_priv(netdev); 2926 int ret = 0; 2927 2928 switch (tuna->id) { 2929 case ETHTOOL_RX_COPYBREAK: 2930 fep->rx_copybreak = *(u32 *)data; 2931 break; 2932 default: 2933 ret = -EINVAL; 2934 break; 2935 } 2936 2937 return ret; 2938 } 2939 2940 /* LPI Sleep Ts count base on tx clk (clk_ref). 2941 * The lpi sleep cnt value = X us / (cycle_ns). 2942 */ 2943 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 2944 { 2945 struct fec_enet_private *fep = netdev_priv(ndev); 2946 2947 return us * (fep->clk_ref_rate / 1000) / 1000; 2948 } 2949 2950 static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable) 2951 { 2952 struct fec_enet_private *fep = netdev_priv(ndev); 2953 struct ethtool_eee *p = &fep->eee; 2954 unsigned int sleep_cycle, wake_cycle; 2955 int ret = 0; 2956 2957 if (enable) { 2958 ret = phy_init_eee(ndev->phydev, false); 2959 if (ret) 2960 return ret; 2961 2962 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer); 2963 wake_cycle = sleep_cycle; 2964 } else { 2965 sleep_cycle = 0; 2966 wake_cycle = 0; 2967 } 2968 2969 p->tx_lpi_enabled = enable; 2970 p->eee_enabled = enable; 2971 p->eee_active = enable; 2972 2973 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 2974 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 2975 2976 return 0; 2977 } 2978 2979 static int 2980 fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata) 2981 { 2982 struct fec_enet_private *fep = netdev_priv(ndev); 2983 struct ethtool_eee *p = &fep->eee; 2984 2985 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 2986 return -EOPNOTSUPP; 2987 2988 if (!netif_running(ndev)) 2989 return -ENETDOWN; 2990 2991 edata->eee_enabled = p->eee_enabled; 2992 edata->eee_active = p->eee_active; 2993 edata->tx_lpi_timer = p->tx_lpi_timer; 2994 edata->tx_lpi_enabled = p->tx_lpi_enabled; 2995 2996 return phy_ethtool_get_eee(ndev->phydev, edata); 2997 } 2998 2999 static int 3000 fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata) 3001 { 3002 struct fec_enet_private *fep = netdev_priv(ndev); 3003 struct ethtool_eee *p = &fep->eee; 3004 int ret = 0; 3005 3006 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3007 return -EOPNOTSUPP; 3008 3009 if (!netif_running(ndev)) 3010 return -ENETDOWN; 3011 3012 p->tx_lpi_timer = edata->tx_lpi_timer; 3013 3014 if (!edata->eee_enabled || !edata->tx_lpi_enabled || 3015 !edata->tx_lpi_timer) 3016 ret = fec_enet_eee_mode_set(ndev, false); 3017 else 3018 ret = fec_enet_eee_mode_set(ndev, true); 3019 3020 if (ret) 3021 return ret; 3022 3023 return phy_ethtool_set_eee(ndev->phydev, edata); 3024 } 3025 3026 static void 3027 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3028 { 3029 struct fec_enet_private *fep = netdev_priv(ndev); 3030 3031 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 3032 wol->supported = WAKE_MAGIC; 3033 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 3034 } else { 3035 wol->supported = wol->wolopts = 0; 3036 } 3037 } 3038 3039 static int 3040 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3041 { 3042 struct fec_enet_private *fep = netdev_priv(ndev); 3043 3044 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 3045 return -EINVAL; 3046 3047 if (wol->wolopts & ~WAKE_MAGIC) 3048 return -EINVAL; 3049 3050 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 3051 if (device_may_wakeup(&ndev->dev)) 3052 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 3053 else 3054 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 3055 3056 return 0; 3057 } 3058 3059 static const struct ethtool_ops fec_enet_ethtool_ops = { 3060 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3061 ETHTOOL_COALESCE_MAX_FRAMES, 3062 .get_drvinfo = fec_enet_get_drvinfo, 3063 .get_regs_len = fec_enet_get_regs_len, 3064 .get_regs = fec_enet_get_regs, 3065 .nway_reset = phy_ethtool_nway_reset, 3066 .get_link = ethtool_op_get_link, 3067 .get_coalesce = fec_enet_get_coalesce, 3068 .set_coalesce = fec_enet_set_coalesce, 3069 #ifndef CONFIG_M5272 3070 .get_pauseparam = fec_enet_get_pauseparam, 3071 .set_pauseparam = fec_enet_set_pauseparam, 3072 .get_strings = fec_enet_get_strings, 3073 .get_ethtool_stats = fec_enet_get_ethtool_stats, 3074 .get_sset_count = fec_enet_get_sset_count, 3075 #endif 3076 .get_ts_info = fec_enet_get_ts_info, 3077 .get_tunable = fec_enet_get_tunable, 3078 .set_tunable = fec_enet_set_tunable, 3079 .get_wol = fec_enet_get_wol, 3080 .set_wol = fec_enet_set_wol, 3081 .get_eee = fec_enet_get_eee, 3082 .set_eee = fec_enet_set_eee, 3083 .get_link_ksettings = phy_ethtool_get_link_ksettings, 3084 .set_link_ksettings = phy_ethtool_set_link_ksettings, 3085 .self_test = net_selftest, 3086 }; 3087 3088 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 3089 { 3090 struct fec_enet_private *fep = netdev_priv(ndev); 3091 struct phy_device *phydev = ndev->phydev; 3092 3093 if (!netif_running(ndev)) 3094 return -EINVAL; 3095 3096 if (!phydev) 3097 return -ENODEV; 3098 3099 if (fep->bufdesc_ex) { 3100 bool use_fec_hwts = !phy_has_hwtstamp(phydev); 3101 3102 if (cmd == SIOCSHWTSTAMP) { 3103 if (use_fec_hwts) 3104 return fec_ptp_set(ndev, rq); 3105 fec_ptp_disable_hwts(ndev); 3106 } else if (cmd == SIOCGHWTSTAMP) { 3107 if (use_fec_hwts) 3108 return fec_ptp_get(ndev, rq); 3109 } 3110 } 3111 3112 return phy_mii_ioctl(phydev, rq, cmd); 3113 } 3114 3115 static void fec_enet_free_buffers(struct net_device *ndev) 3116 { 3117 struct fec_enet_private *fep = netdev_priv(ndev); 3118 unsigned int i; 3119 struct sk_buff *skb; 3120 struct fec_enet_priv_tx_q *txq; 3121 struct fec_enet_priv_rx_q *rxq; 3122 unsigned int q; 3123 3124 for (q = 0; q < fep->num_rx_queues; q++) { 3125 rxq = fep->rx_queue[q]; 3126 for (i = 0; i < rxq->bd.ring_size; i++) 3127 page_pool_release_page(rxq->page_pool, rxq->rx_skb_info[i].page); 3128 3129 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 3130 xdp_rxq_info_unreg(&rxq->xdp_rxq); 3131 page_pool_destroy(rxq->page_pool); 3132 rxq->page_pool = NULL; 3133 } 3134 3135 for (q = 0; q < fep->num_tx_queues; q++) { 3136 txq = fep->tx_queue[q]; 3137 for (i = 0; i < txq->bd.ring_size; i++) { 3138 kfree(txq->tx_bounce[i]); 3139 txq->tx_bounce[i] = NULL; 3140 skb = txq->tx_skbuff[i]; 3141 txq->tx_skbuff[i] = NULL; 3142 dev_kfree_skb(skb); 3143 } 3144 } 3145 } 3146 3147 static void fec_enet_free_queue(struct net_device *ndev) 3148 { 3149 struct fec_enet_private *fep = netdev_priv(ndev); 3150 int i; 3151 struct fec_enet_priv_tx_q *txq; 3152 3153 for (i = 0; i < fep->num_tx_queues; i++) 3154 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 3155 txq = fep->tx_queue[i]; 3156 dma_free_coherent(&fep->pdev->dev, 3157 txq->bd.ring_size * TSO_HEADER_SIZE, 3158 txq->tso_hdrs, 3159 txq->tso_hdrs_dma); 3160 } 3161 3162 for (i = 0; i < fep->num_rx_queues; i++) 3163 kfree(fep->rx_queue[i]); 3164 for (i = 0; i < fep->num_tx_queues; i++) 3165 kfree(fep->tx_queue[i]); 3166 } 3167 3168 static int fec_enet_alloc_queue(struct net_device *ndev) 3169 { 3170 struct fec_enet_private *fep = netdev_priv(ndev); 3171 int i; 3172 int ret = 0; 3173 struct fec_enet_priv_tx_q *txq; 3174 3175 for (i = 0; i < fep->num_tx_queues; i++) { 3176 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3177 if (!txq) { 3178 ret = -ENOMEM; 3179 goto alloc_failed; 3180 } 3181 3182 fep->tx_queue[i] = txq; 3183 txq->bd.ring_size = TX_RING_SIZE; 3184 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3185 3186 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3187 txq->tx_wake_threshold = 3188 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 3189 3190 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 3191 txq->bd.ring_size * TSO_HEADER_SIZE, 3192 &txq->tso_hdrs_dma, 3193 GFP_KERNEL); 3194 if (!txq->tso_hdrs) { 3195 ret = -ENOMEM; 3196 goto alloc_failed; 3197 } 3198 } 3199 3200 for (i = 0; i < fep->num_rx_queues; i++) { 3201 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3202 GFP_KERNEL); 3203 if (!fep->rx_queue[i]) { 3204 ret = -ENOMEM; 3205 goto alloc_failed; 3206 } 3207 3208 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3209 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3210 } 3211 return ret; 3212 3213 alloc_failed: 3214 fec_enet_free_queue(ndev); 3215 return ret; 3216 } 3217 3218 static int 3219 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3220 { 3221 struct fec_enet_private *fep = netdev_priv(ndev); 3222 struct fec_enet_priv_rx_q *rxq; 3223 dma_addr_t phys_addr; 3224 struct bufdesc *bdp; 3225 struct page *page; 3226 int i, err; 3227 3228 rxq = fep->rx_queue[queue]; 3229 bdp = rxq->bd.base; 3230 3231 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size); 3232 if (err < 0) { 3233 netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err); 3234 return err; 3235 } 3236 3237 for (i = 0; i < rxq->bd.ring_size; i++) { 3238 page = page_pool_dev_alloc_pages(rxq->page_pool); 3239 if (!page) 3240 goto err_alloc; 3241 3242 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM; 3243 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 3244 3245 rxq->rx_skb_info[i].page = page; 3246 rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM; 3247 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3248 3249 if (fep->bufdesc_ex) { 3250 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3251 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3252 } 3253 3254 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3255 } 3256 3257 /* Set the last buffer to wrap. */ 3258 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3259 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3260 return 0; 3261 3262 err_alloc: 3263 fec_enet_free_buffers(ndev); 3264 return -ENOMEM; 3265 } 3266 3267 static int 3268 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3269 { 3270 struct fec_enet_private *fep = netdev_priv(ndev); 3271 unsigned int i; 3272 struct bufdesc *bdp; 3273 struct fec_enet_priv_tx_q *txq; 3274 3275 txq = fep->tx_queue[queue]; 3276 bdp = txq->bd.base; 3277 for (i = 0; i < txq->bd.ring_size; i++) { 3278 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3279 if (!txq->tx_bounce[i]) 3280 goto err_alloc; 3281 3282 bdp->cbd_sc = cpu_to_fec16(0); 3283 bdp->cbd_bufaddr = cpu_to_fec32(0); 3284 3285 if (fep->bufdesc_ex) { 3286 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3287 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3288 } 3289 3290 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3291 } 3292 3293 /* Set the last buffer to wrap. */ 3294 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3295 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3296 3297 return 0; 3298 3299 err_alloc: 3300 fec_enet_free_buffers(ndev); 3301 return -ENOMEM; 3302 } 3303 3304 static int fec_enet_alloc_buffers(struct net_device *ndev) 3305 { 3306 struct fec_enet_private *fep = netdev_priv(ndev); 3307 unsigned int i; 3308 3309 for (i = 0; i < fep->num_rx_queues; i++) 3310 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3311 return -ENOMEM; 3312 3313 for (i = 0; i < fep->num_tx_queues; i++) 3314 if (fec_enet_alloc_txq_buffers(ndev, i)) 3315 return -ENOMEM; 3316 return 0; 3317 } 3318 3319 static int 3320 fec_enet_open(struct net_device *ndev) 3321 { 3322 struct fec_enet_private *fep = netdev_priv(ndev); 3323 int ret; 3324 bool reset_again; 3325 3326 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3327 if (ret < 0) 3328 return ret; 3329 3330 pinctrl_pm_select_default_state(&fep->pdev->dev); 3331 ret = fec_enet_clk_enable(ndev, true); 3332 if (ret) 3333 goto clk_enable; 3334 3335 /* During the first fec_enet_open call the PHY isn't probed at this 3336 * point. Therefore the phy_reset_after_clk_enable() call within 3337 * fec_enet_clk_enable() fails. As we need this reset in order to be 3338 * sure the PHY is working correctly we check if we need to reset again 3339 * later when the PHY is probed 3340 */ 3341 if (ndev->phydev && ndev->phydev->drv) 3342 reset_again = false; 3343 else 3344 reset_again = true; 3345 3346 /* I should reset the ring buffers here, but I don't yet know 3347 * a simple way to do that. 3348 */ 3349 3350 ret = fec_enet_alloc_buffers(ndev); 3351 if (ret) 3352 goto err_enet_alloc; 3353 3354 /* Init MAC prior to mii bus probe */ 3355 fec_restart(ndev); 3356 3357 /* Call phy_reset_after_clk_enable() again if it failed during 3358 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3359 */ 3360 if (reset_again) 3361 fec_enet_phy_reset_after_clk_enable(ndev); 3362 3363 /* Probe and connect to PHY when open the interface */ 3364 ret = fec_enet_mii_probe(ndev); 3365 if (ret) 3366 goto err_enet_mii_probe; 3367 3368 if (fep->quirks & FEC_QUIRK_ERR006687) 3369 imx6q_cpuidle_fec_irqs_used(); 3370 3371 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3372 cpu_latency_qos_add_request(&fep->pm_qos_req, 0); 3373 3374 napi_enable(&fep->napi); 3375 phy_start(ndev->phydev); 3376 netif_tx_start_all_queues(ndev); 3377 3378 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3379 FEC_WOL_FLAG_ENABLE); 3380 3381 return 0; 3382 3383 err_enet_mii_probe: 3384 fec_enet_free_buffers(ndev); 3385 err_enet_alloc: 3386 fec_enet_clk_enable(ndev, false); 3387 clk_enable: 3388 pm_runtime_mark_last_busy(&fep->pdev->dev); 3389 pm_runtime_put_autosuspend(&fep->pdev->dev); 3390 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3391 return ret; 3392 } 3393 3394 static int 3395 fec_enet_close(struct net_device *ndev) 3396 { 3397 struct fec_enet_private *fep = netdev_priv(ndev); 3398 3399 phy_stop(ndev->phydev); 3400 3401 if (netif_device_present(ndev)) { 3402 napi_disable(&fep->napi); 3403 netif_tx_disable(ndev); 3404 fec_stop(ndev); 3405 } 3406 3407 phy_disconnect(ndev->phydev); 3408 3409 if (fep->quirks & FEC_QUIRK_ERR006687) 3410 imx6q_cpuidle_fec_irqs_unused(); 3411 3412 fec_enet_update_ethtool_stats(ndev); 3413 3414 fec_enet_clk_enable(ndev, false); 3415 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3416 cpu_latency_qos_remove_request(&fep->pm_qos_req); 3417 3418 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3419 pm_runtime_mark_last_busy(&fep->pdev->dev); 3420 pm_runtime_put_autosuspend(&fep->pdev->dev); 3421 3422 fec_enet_free_buffers(ndev); 3423 3424 return 0; 3425 } 3426 3427 /* Set or clear the multicast filter for this adaptor. 3428 * Skeleton taken from sunlance driver. 3429 * The CPM Ethernet implementation allows Multicast as well as individual 3430 * MAC address filtering. Some of the drivers check to make sure it is 3431 * a group multicast address, and discard those that are not. I guess I 3432 * will do the same for now, but just remove the test if you want 3433 * individual filtering as well (do the upper net layers want or support 3434 * this kind of feature?). 3435 */ 3436 3437 #define FEC_HASH_BITS 6 /* #bits in hash */ 3438 3439 static void set_multicast_list(struct net_device *ndev) 3440 { 3441 struct fec_enet_private *fep = netdev_priv(ndev); 3442 struct netdev_hw_addr *ha; 3443 unsigned int crc, tmp; 3444 unsigned char hash; 3445 unsigned int hash_high = 0, hash_low = 0; 3446 3447 if (ndev->flags & IFF_PROMISC) { 3448 tmp = readl(fep->hwp + FEC_R_CNTRL); 3449 tmp |= 0x8; 3450 writel(tmp, fep->hwp + FEC_R_CNTRL); 3451 return; 3452 } 3453 3454 tmp = readl(fep->hwp + FEC_R_CNTRL); 3455 tmp &= ~0x8; 3456 writel(tmp, fep->hwp + FEC_R_CNTRL); 3457 3458 if (ndev->flags & IFF_ALLMULTI) { 3459 /* Catch all multicast addresses, so set the 3460 * filter to all 1's 3461 */ 3462 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3463 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3464 3465 return; 3466 } 3467 3468 /* Add the addresses in hash register */ 3469 netdev_for_each_mc_addr(ha, ndev) { 3470 /* calculate crc32 value of mac address */ 3471 crc = ether_crc_le(ndev->addr_len, ha->addr); 3472 3473 /* only upper 6 bits (FEC_HASH_BITS) are used 3474 * which point to specific bit in the hash registers 3475 */ 3476 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3477 3478 if (hash > 31) 3479 hash_high |= 1 << (hash - 32); 3480 else 3481 hash_low |= 1 << hash; 3482 } 3483 3484 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3485 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3486 } 3487 3488 /* Set a MAC change in hardware. */ 3489 static int 3490 fec_set_mac_address(struct net_device *ndev, void *p) 3491 { 3492 struct fec_enet_private *fep = netdev_priv(ndev); 3493 struct sockaddr *addr = p; 3494 3495 if (addr) { 3496 if (!is_valid_ether_addr(addr->sa_data)) 3497 return -EADDRNOTAVAIL; 3498 eth_hw_addr_set(ndev, addr->sa_data); 3499 } 3500 3501 /* Add netif status check here to avoid system hang in below case: 3502 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3503 * After ethx down, fec all clocks are gated off and then register 3504 * access causes system hang. 3505 */ 3506 if (!netif_running(ndev)) 3507 return 0; 3508 3509 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3510 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3511 fep->hwp + FEC_ADDR_LOW); 3512 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3513 fep->hwp + FEC_ADDR_HIGH); 3514 return 0; 3515 } 3516 3517 #ifdef CONFIG_NET_POLL_CONTROLLER 3518 /** 3519 * fec_poll_controller - FEC Poll controller function 3520 * @dev: The FEC network adapter 3521 * 3522 * Polled functionality used by netconsole and others in non interrupt mode 3523 * 3524 */ 3525 static void fec_poll_controller(struct net_device *dev) 3526 { 3527 int i; 3528 struct fec_enet_private *fep = netdev_priv(dev); 3529 3530 for (i = 0; i < FEC_IRQ_NUM; i++) { 3531 if (fep->irq[i] > 0) { 3532 disable_irq(fep->irq[i]); 3533 fec_enet_interrupt(fep->irq[i], dev); 3534 enable_irq(fep->irq[i]); 3535 } 3536 } 3537 } 3538 #endif 3539 3540 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3541 netdev_features_t features) 3542 { 3543 struct fec_enet_private *fep = netdev_priv(netdev); 3544 netdev_features_t changed = features ^ netdev->features; 3545 3546 netdev->features = features; 3547 3548 /* Receive checksum has been changed */ 3549 if (changed & NETIF_F_RXCSUM) { 3550 if (features & NETIF_F_RXCSUM) 3551 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3552 else 3553 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3554 } 3555 } 3556 3557 static int fec_set_features(struct net_device *netdev, 3558 netdev_features_t features) 3559 { 3560 struct fec_enet_private *fep = netdev_priv(netdev); 3561 netdev_features_t changed = features ^ netdev->features; 3562 3563 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3564 napi_disable(&fep->napi); 3565 netif_tx_lock_bh(netdev); 3566 fec_stop(netdev); 3567 fec_enet_set_netdev_features(netdev, features); 3568 fec_restart(netdev); 3569 netif_tx_wake_all_queues(netdev); 3570 netif_tx_unlock_bh(netdev); 3571 napi_enable(&fep->napi); 3572 } else { 3573 fec_enet_set_netdev_features(netdev, features); 3574 } 3575 3576 return 0; 3577 } 3578 3579 static u16 fec_enet_get_raw_vlan_tci(struct sk_buff *skb) 3580 { 3581 struct vlan_ethhdr *vhdr; 3582 unsigned short vlan_TCI = 0; 3583 3584 if (skb->protocol == htons(ETH_P_ALL)) { 3585 vhdr = (struct vlan_ethhdr *)(skb->data); 3586 vlan_TCI = ntohs(vhdr->h_vlan_TCI); 3587 } 3588 3589 return vlan_TCI; 3590 } 3591 3592 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3593 struct net_device *sb_dev) 3594 { 3595 struct fec_enet_private *fep = netdev_priv(ndev); 3596 u16 vlan_tag; 3597 3598 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3599 return netdev_pick_tx(ndev, skb, NULL); 3600 3601 vlan_tag = fec_enet_get_raw_vlan_tci(skb); 3602 if (!vlan_tag) 3603 return vlan_tag; 3604 3605 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3606 } 3607 3608 static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf) 3609 { 3610 struct fec_enet_private *fep = netdev_priv(dev); 3611 bool is_run = netif_running(dev); 3612 struct bpf_prog *old_prog; 3613 3614 switch (bpf->command) { 3615 case XDP_SETUP_PROG: 3616 /* No need to support the SoCs that require to 3617 * do the frame swap because the performance wouldn't be 3618 * better than the skb mode. 3619 */ 3620 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 3621 return -EOPNOTSUPP; 3622 3623 if (is_run) { 3624 napi_disable(&fep->napi); 3625 netif_tx_disable(dev); 3626 } 3627 3628 old_prog = xchg(&fep->xdp_prog, bpf->prog); 3629 fec_restart(dev); 3630 3631 if (is_run) { 3632 napi_enable(&fep->napi); 3633 netif_tx_start_all_queues(dev); 3634 } 3635 3636 if (old_prog) 3637 bpf_prog_put(old_prog); 3638 3639 return 0; 3640 3641 case XDP_SETUP_XSK_POOL: 3642 return -EOPNOTSUPP; 3643 3644 default: 3645 return -EOPNOTSUPP; 3646 } 3647 } 3648 3649 static int 3650 fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index) 3651 { 3652 if (unlikely(index < 0)) 3653 return 0; 3654 3655 return (index % fep->num_tx_queues); 3656 } 3657 3658 static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep, 3659 struct fec_enet_priv_tx_q *txq, 3660 struct xdp_frame *frame) 3661 { 3662 unsigned int index, status, estatus; 3663 struct bufdesc *bdp, *last_bdp; 3664 dma_addr_t dma_addr; 3665 int entries_free; 3666 3667 entries_free = fec_enet_get_free_txdesc_num(txq); 3668 if (entries_free < MAX_SKB_FRAGS + 1) { 3669 netdev_err(fep->netdev, "NOT enough BD for SG!\n"); 3670 return NETDEV_TX_OK; 3671 } 3672 3673 /* Fill in a Tx ring entry */ 3674 bdp = txq->bd.cur; 3675 last_bdp = bdp; 3676 status = fec16_to_cpu(bdp->cbd_sc); 3677 status &= ~BD_ENET_TX_STATS; 3678 3679 index = fec_enet_get_bd_index(bdp, &txq->bd); 3680 3681 dma_addr = dma_map_single(&fep->pdev->dev, frame->data, 3682 frame->len, DMA_TO_DEVICE); 3683 if (dma_mapping_error(&fep->pdev->dev, dma_addr)) 3684 return FEC_ENET_XDP_CONSUMED; 3685 3686 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 3687 if (fep->bufdesc_ex) 3688 estatus = BD_ENET_TX_INT; 3689 3690 bdp->cbd_bufaddr = cpu_to_fec32(dma_addr); 3691 bdp->cbd_datlen = cpu_to_fec16(frame->len); 3692 3693 if (fep->bufdesc_ex) { 3694 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3695 3696 if (fep->quirks & FEC_QUIRK_HAS_AVB) 3697 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 3698 3699 ebdp->cbd_bdu = 0; 3700 ebdp->cbd_esc = cpu_to_fec32(estatus); 3701 } 3702 3703 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 3704 txq->tx_skbuff[index] = NULL; 3705 3706 /* Send it on its way. Tell FEC it's ready, interrupt when done, 3707 * it's the last BD of the frame, and to put the CRC on the end. 3708 */ 3709 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 3710 bdp->cbd_sc = cpu_to_fec16(status); 3711 3712 /* If this was the last BD in the ring, start at the beginning again. */ 3713 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 3714 3715 txq->bd.cur = bdp; 3716 3717 return 0; 3718 } 3719 3720 static int fec_enet_xdp_xmit(struct net_device *dev, 3721 int num_frames, 3722 struct xdp_frame **frames, 3723 u32 flags) 3724 { 3725 struct fec_enet_private *fep = netdev_priv(dev); 3726 struct fec_enet_priv_tx_q *txq; 3727 int cpu = smp_processor_id(); 3728 struct netdev_queue *nq; 3729 unsigned int queue; 3730 int i; 3731 3732 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3733 txq = fep->tx_queue[queue]; 3734 nq = netdev_get_tx_queue(fep->netdev, queue); 3735 3736 __netif_tx_lock(nq, cpu); 3737 3738 for (i = 0; i < num_frames; i++) 3739 fec_enet_txq_xmit_frame(fep, txq, frames[i]); 3740 3741 /* Make sure the update to bdp and tx_skbuff are performed. */ 3742 wmb(); 3743 3744 /* Trigger transmission start */ 3745 writel(0, txq->bd.reg_desc_active); 3746 3747 __netif_tx_unlock(nq); 3748 3749 return num_frames; 3750 } 3751 3752 static const struct net_device_ops fec_netdev_ops = { 3753 .ndo_open = fec_enet_open, 3754 .ndo_stop = fec_enet_close, 3755 .ndo_start_xmit = fec_enet_start_xmit, 3756 .ndo_select_queue = fec_enet_select_queue, 3757 .ndo_set_rx_mode = set_multicast_list, 3758 .ndo_validate_addr = eth_validate_addr, 3759 .ndo_tx_timeout = fec_timeout, 3760 .ndo_set_mac_address = fec_set_mac_address, 3761 .ndo_eth_ioctl = fec_enet_ioctl, 3762 #ifdef CONFIG_NET_POLL_CONTROLLER 3763 .ndo_poll_controller = fec_poll_controller, 3764 #endif 3765 .ndo_set_features = fec_set_features, 3766 .ndo_bpf = fec_enet_bpf, 3767 .ndo_xdp_xmit = fec_enet_xdp_xmit, 3768 }; 3769 3770 static const unsigned short offset_des_active_rxq[] = { 3771 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3772 }; 3773 3774 static const unsigned short offset_des_active_txq[] = { 3775 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3776 }; 3777 3778 /* 3779 * XXX: We need to clean up on failure exits here. 3780 * 3781 */ 3782 static int fec_enet_init(struct net_device *ndev) 3783 { 3784 struct fec_enet_private *fep = netdev_priv(ndev); 3785 struct bufdesc *cbd_base; 3786 dma_addr_t bd_dma; 3787 int bd_size; 3788 unsigned int i; 3789 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3790 sizeof(struct bufdesc); 3791 unsigned dsize_log2 = __fls(dsize); 3792 int ret; 3793 3794 WARN_ON(dsize != (1 << dsize_log2)); 3795 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 3796 fep->rx_align = 0xf; 3797 fep->tx_align = 0xf; 3798 #else 3799 fep->rx_align = 0x3; 3800 fep->tx_align = 0x3; 3801 #endif 3802 3803 /* Check mask of the streaming and coherent API */ 3804 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 3805 if (ret < 0) { 3806 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 3807 return ret; 3808 } 3809 3810 ret = fec_enet_alloc_queue(ndev); 3811 if (ret) 3812 return ret; 3813 3814 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3815 3816 /* Allocate memory for buffer descriptors. */ 3817 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3818 GFP_KERNEL); 3819 if (!cbd_base) { 3820 ret = -ENOMEM; 3821 goto free_queue_mem; 3822 } 3823 3824 /* Get the Ethernet address */ 3825 ret = fec_get_mac(ndev); 3826 if (ret) 3827 goto free_queue_mem; 3828 3829 /* make sure MAC we just acquired is programmed into the hw */ 3830 fec_set_mac_address(ndev, NULL); 3831 3832 /* Set receive and transmit descriptor base. */ 3833 for (i = 0; i < fep->num_rx_queues; i++) { 3834 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3835 unsigned size = dsize * rxq->bd.ring_size; 3836 3837 rxq->bd.qid = i; 3838 rxq->bd.base = cbd_base; 3839 rxq->bd.cur = cbd_base; 3840 rxq->bd.dma = bd_dma; 3841 rxq->bd.dsize = dsize; 3842 rxq->bd.dsize_log2 = dsize_log2; 3843 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3844 bd_dma += size; 3845 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3846 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3847 } 3848 3849 for (i = 0; i < fep->num_tx_queues; i++) { 3850 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3851 unsigned size = dsize * txq->bd.ring_size; 3852 3853 txq->bd.qid = i; 3854 txq->bd.base = cbd_base; 3855 txq->bd.cur = cbd_base; 3856 txq->bd.dma = bd_dma; 3857 txq->bd.dsize = dsize; 3858 txq->bd.dsize_log2 = dsize_log2; 3859 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3860 bd_dma += size; 3861 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3862 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3863 } 3864 3865 3866 /* The FEC Ethernet specific entries in the device structure */ 3867 ndev->watchdog_timeo = TX_TIMEOUT; 3868 ndev->netdev_ops = &fec_netdev_ops; 3869 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3870 3871 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3872 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi); 3873 3874 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3875 /* enable hw VLAN support */ 3876 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3877 3878 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3879 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS); 3880 3881 /* enable hw accelerator */ 3882 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3883 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3884 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3885 } 3886 3887 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 3888 fep->tx_align = 0; 3889 fep->rx_align = 0x3f; 3890 } 3891 3892 ndev->hw_features = ndev->features; 3893 3894 fec_restart(ndev); 3895 3896 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 3897 fec_enet_clear_ethtool_stats(ndev); 3898 else 3899 fec_enet_update_ethtool_stats(ndev); 3900 3901 return 0; 3902 3903 free_queue_mem: 3904 fec_enet_free_queue(ndev); 3905 return ret; 3906 } 3907 3908 #ifdef CONFIG_OF 3909 static int fec_reset_phy(struct platform_device *pdev) 3910 { 3911 int err, phy_reset; 3912 bool active_high = false; 3913 int msec = 1, phy_post_delay = 0; 3914 struct device_node *np = pdev->dev.of_node; 3915 3916 if (!np) 3917 return 0; 3918 3919 err = of_property_read_u32(np, "phy-reset-duration", &msec); 3920 /* A sane reset duration should not be longer than 1s */ 3921 if (!err && msec > 1000) 3922 msec = 1; 3923 3924 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3925 if (phy_reset == -EPROBE_DEFER) 3926 return phy_reset; 3927 else if (!gpio_is_valid(phy_reset)) 3928 return 0; 3929 3930 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 3931 /* valid reset duration should be less than 1s */ 3932 if (!err && phy_post_delay > 1000) 3933 return -EINVAL; 3934 3935 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3936 3937 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3938 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3939 "phy-reset"); 3940 if (err) { 3941 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3942 return err; 3943 } 3944 3945 if (msec > 20) 3946 msleep(msec); 3947 else 3948 usleep_range(msec * 1000, msec * 1000 + 1000); 3949 3950 gpio_set_value_cansleep(phy_reset, !active_high); 3951 3952 if (!phy_post_delay) 3953 return 0; 3954 3955 if (phy_post_delay > 20) 3956 msleep(phy_post_delay); 3957 else 3958 usleep_range(phy_post_delay * 1000, 3959 phy_post_delay * 1000 + 1000); 3960 3961 return 0; 3962 } 3963 #else /* CONFIG_OF */ 3964 static int fec_reset_phy(struct platform_device *pdev) 3965 { 3966 /* 3967 * In case of platform probe, the reset has been done 3968 * by machine code. 3969 */ 3970 return 0; 3971 } 3972 #endif /* CONFIG_OF */ 3973 3974 static void 3975 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3976 { 3977 struct device_node *np = pdev->dev.of_node; 3978 3979 *num_tx = *num_rx = 1; 3980 3981 if (!np || !of_device_is_available(np)) 3982 return; 3983 3984 /* parse the num of tx and rx queues */ 3985 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3986 3987 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3988 3989 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3990 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3991 *num_tx); 3992 *num_tx = 1; 3993 return; 3994 } 3995 3996 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3997 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3998 *num_rx); 3999 *num_rx = 1; 4000 return; 4001 } 4002 4003 } 4004 4005 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 4006 { 4007 int irq_cnt = platform_irq_count(pdev); 4008 4009 if (irq_cnt > FEC_IRQ_NUM) 4010 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 4011 else if (irq_cnt == 2) 4012 irq_cnt = 1; /* last for pps */ 4013 else if (irq_cnt <= 0) 4014 irq_cnt = 1; /* At least 1 irq is needed */ 4015 return irq_cnt; 4016 } 4017 4018 static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 4019 { 4020 struct net_device *ndev = platform_get_drvdata(pdev); 4021 struct fec_enet_private *fep = netdev_priv(ndev); 4022 4023 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 4024 fep->wake_irq = fep->irq[2]; 4025 else 4026 fep->wake_irq = fep->irq[0]; 4027 } 4028 4029 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 4030 struct device_node *np) 4031 { 4032 struct device_node *gpr_np; 4033 u32 out_val[3]; 4034 int ret = 0; 4035 4036 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 4037 if (!gpr_np) 4038 return 0; 4039 4040 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 4041 ARRAY_SIZE(out_val)); 4042 if (ret) { 4043 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 4044 goto out; 4045 } 4046 4047 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 4048 if (IS_ERR(fep->stop_gpr.gpr)) { 4049 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 4050 ret = PTR_ERR(fep->stop_gpr.gpr); 4051 fep->stop_gpr.gpr = NULL; 4052 goto out; 4053 } 4054 4055 fep->stop_gpr.reg = out_val[1]; 4056 fep->stop_gpr.bit = out_val[2]; 4057 4058 out: 4059 of_node_put(gpr_np); 4060 4061 return ret; 4062 } 4063 4064 static int 4065 fec_probe(struct platform_device *pdev) 4066 { 4067 struct fec_enet_private *fep; 4068 struct fec_platform_data *pdata; 4069 phy_interface_t interface; 4070 struct net_device *ndev; 4071 int i, irq, ret = 0; 4072 const struct of_device_id *of_id; 4073 static int dev_id; 4074 struct device_node *np = pdev->dev.of_node, *phy_node; 4075 int num_tx_qs; 4076 int num_rx_qs; 4077 char irq_name[8]; 4078 int irq_cnt; 4079 struct fec_devinfo *dev_info; 4080 4081 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 4082 4083 /* Init network device */ 4084 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 4085 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 4086 if (!ndev) 4087 return -ENOMEM; 4088 4089 SET_NETDEV_DEV(ndev, &pdev->dev); 4090 4091 /* setup board info structure */ 4092 fep = netdev_priv(ndev); 4093 4094 of_id = of_match_device(fec_dt_ids, &pdev->dev); 4095 if (of_id) 4096 pdev->id_entry = of_id->data; 4097 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; 4098 if (dev_info) 4099 fep->quirks = dev_info->quirks; 4100 4101 fep->netdev = ndev; 4102 fep->num_rx_queues = num_rx_qs; 4103 fep->num_tx_queues = num_tx_qs; 4104 4105 #if !defined(CONFIG_M5272) 4106 /* default enable pause frame auto negotiation */ 4107 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 4108 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 4109 #endif 4110 4111 /* Select default pin state */ 4112 pinctrl_pm_select_default_state(&pdev->dev); 4113 4114 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 4115 if (IS_ERR(fep->hwp)) { 4116 ret = PTR_ERR(fep->hwp); 4117 goto failed_ioremap; 4118 } 4119 4120 fep->pdev = pdev; 4121 fep->dev_id = dev_id++; 4122 4123 platform_set_drvdata(pdev, ndev); 4124 4125 if ((of_machine_is_compatible("fsl,imx6q") || 4126 of_machine_is_compatible("fsl,imx6dl")) && 4127 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 4128 fep->quirks |= FEC_QUIRK_ERR006687; 4129 4130 ret = fec_enet_ipc_handle_init(fep); 4131 if (ret) 4132 goto failed_ipc_init; 4133 4134 if (of_get_property(np, "fsl,magic-packet", NULL)) 4135 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 4136 4137 ret = fec_enet_init_stop_mode(fep, np); 4138 if (ret) 4139 goto failed_stop_mode; 4140 4141 phy_node = of_parse_phandle(np, "phy-handle", 0); 4142 if (!phy_node && of_phy_is_fixed_link(np)) { 4143 ret = of_phy_register_fixed_link(np); 4144 if (ret < 0) { 4145 dev_err(&pdev->dev, 4146 "broken fixed-link specification\n"); 4147 goto failed_phy; 4148 } 4149 phy_node = of_node_get(np); 4150 } 4151 fep->phy_node = phy_node; 4152 4153 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 4154 if (ret) { 4155 pdata = dev_get_platdata(&pdev->dev); 4156 if (pdata) 4157 fep->phy_interface = pdata->phy; 4158 else 4159 fep->phy_interface = PHY_INTERFACE_MODE_MII; 4160 } else { 4161 fep->phy_interface = interface; 4162 } 4163 4164 ret = fec_enet_parse_rgmii_delay(fep, np); 4165 if (ret) 4166 goto failed_rgmii_delay; 4167 4168 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 4169 if (IS_ERR(fep->clk_ipg)) { 4170 ret = PTR_ERR(fep->clk_ipg); 4171 goto failed_clk; 4172 } 4173 4174 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 4175 if (IS_ERR(fep->clk_ahb)) { 4176 ret = PTR_ERR(fep->clk_ahb); 4177 goto failed_clk; 4178 } 4179 4180 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 4181 4182 /* enet_out is optional, depends on board */ 4183 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out"); 4184 if (IS_ERR(fep->clk_enet_out)) { 4185 ret = PTR_ERR(fep->clk_enet_out); 4186 goto failed_clk; 4187 } 4188 4189 fep->ptp_clk_on = false; 4190 mutex_init(&fep->ptp_clk_mutex); 4191 4192 /* clk_ref is optional, depends on board */ 4193 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref"); 4194 if (IS_ERR(fep->clk_ref)) { 4195 ret = PTR_ERR(fep->clk_ref); 4196 goto failed_clk; 4197 } 4198 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 4199 4200 /* clk_2x_txclk is optional, depends on board */ 4201 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 4202 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 4203 if (IS_ERR(fep->clk_2x_txclk)) 4204 fep->clk_2x_txclk = NULL; 4205 } 4206 4207 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 4208 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 4209 if (IS_ERR(fep->clk_ptp)) { 4210 fep->clk_ptp = NULL; 4211 fep->bufdesc_ex = false; 4212 } 4213 4214 ret = fec_enet_clk_enable(ndev, true); 4215 if (ret) 4216 goto failed_clk; 4217 4218 ret = clk_prepare_enable(fep->clk_ipg); 4219 if (ret) 4220 goto failed_clk_ipg; 4221 ret = clk_prepare_enable(fep->clk_ahb); 4222 if (ret) 4223 goto failed_clk_ahb; 4224 4225 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 4226 if (!IS_ERR(fep->reg_phy)) { 4227 ret = regulator_enable(fep->reg_phy); 4228 if (ret) { 4229 dev_err(&pdev->dev, 4230 "Failed to enable phy regulator: %d\n", ret); 4231 goto failed_regulator; 4232 } 4233 } else { 4234 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 4235 ret = -EPROBE_DEFER; 4236 goto failed_regulator; 4237 } 4238 fep->reg_phy = NULL; 4239 } 4240 4241 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 4242 pm_runtime_use_autosuspend(&pdev->dev); 4243 pm_runtime_get_noresume(&pdev->dev); 4244 pm_runtime_set_active(&pdev->dev); 4245 pm_runtime_enable(&pdev->dev); 4246 4247 ret = fec_reset_phy(pdev); 4248 if (ret) 4249 goto failed_reset; 4250 4251 irq_cnt = fec_enet_get_irq_cnt(pdev); 4252 if (fep->bufdesc_ex) 4253 fec_ptp_init(pdev, irq_cnt); 4254 4255 ret = fec_enet_init(ndev); 4256 if (ret) 4257 goto failed_init; 4258 4259 for (i = 0; i < irq_cnt; i++) { 4260 snprintf(irq_name, sizeof(irq_name), "int%d", i); 4261 irq = platform_get_irq_byname_optional(pdev, irq_name); 4262 if (irq < 0) 4263 irq = platform_get_irq(pdev, i); 4264 if (irq < 0) { 4265 ret = irq; 4266 goto failed_irq; 4267 } 4268 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 4269 0, pdev->name, ndev); 4270 if (ret) 4271 goto failed_irq; 4272 4273 fep->irq[i] = irq; 4274 } 4275 4276 /* Decide which interrupt line is wakeup capable */ 4277 fec_enet_get_wakeup_irq(pdev); 4278 4279 ret = fec_enet_mii_init(pdev); 4280 if (ret) 4281 goto failed_mii_init; 4282 4283 /* Carrier starts down, phylib will bring it up */ 4284 netif_carrier_off(ndev); 4285 fec_enet_clk_enable(ndev, false); 4286 pinctrl_pm_select_sleep_state(&pdev->dev); 4287 4288 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN; 4289 4290 ret = register_netdev(ndev); 4291 if (ret) 4292 goto failed_register; 4293 4294 device_init_wakeup(&ndev->dev, fep->wol_flag & 4295 FEC_WOL_HAS_MAGIC_PACKET); 4296 4297 if (fep->bufdesc_ex && fep->ptp_clock) 4298 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 4299 4300 fep->rx_copybreak = COPYBREAK_DEFAULT; 4301 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 4302 4303 pm_runtime_mark_last_busy(&pdev->dev); 4304 pm_runtime_put_autosuspend(&pdev->dev); 4305 4306 return 0; 4307 4308 failed_register: 4309 fec_enet_mii_remove(fep); 4310 failed_mii_init: 4311 failed_irq: 4312 failed_init: 4313 fec_ptp_stop(pdev); 4314 failed_reset: 4315 pm_runtime_put_noidle(&pdev->dev); 4316 pm_runtime_disable(&pdev->dev); 4317 if (fep->reg_phy) 4318 regulator_disable(fep->reg_phy); 4319 failed_regulator: 4320 clk_disable_unprepare(fep->clk_ahb); 4321 failed_clk_ahb: 4322 clk_disable_unprepare(fep->clk_ipg); 4323 failed_clk_ipg: 4324 fec_enet_clk_enable(ndev, false); 4325 failed_clk: 4326 failed_rgmii_delay: 4327 if (of_phy_is_fixed_link(np)) 4328 of_phy_deregister_fixed_link(np); 4329 of_node_put(phy_node); 4330 failed_stop_mode: 4331 failed_ipc_init: 4332 failed_phy: 4333 dev_id--; 4334 failed_ioremap: 4335 free_netdev(ndev); 4336 4337 return ret; 4338 } 4339 4340 static int 4341 fec_drv_remove(struct platform_device *pdev) 4342 { 4343 struct net_device *ndev = platform_get_drvdata(pdev); 4344 struct fec_enet_private *fep = netdev_priv(ndev); 4345 struct device_node *np = pdev->dev.of_node; 4346 int ret; 4347 4348 ret = pm_runtime_resume_and_get(&pdev->dev); 4349 if (ret < 0) 4350 return ret; 4351 4352 cancel_work_sync(&fep->tx_timeout_work); 4353 fec_ptp_stop(pdev); 4354 unregister_netdev(ndev); 4355 fec_enet_mii_remove(fep); 4356 if (fep->reg_phy) 4357 regulator_disable(fep->reg_phy); 4358 4359 if (of_phy_is_fixed_link(np)) 4360 of_phy_deregister_fixed_link(np); 4361 of_node_put(fep->phy_node); 4362 4363 clk_disable_unprepare(fep->clk_ahb); 4364 clk_disable_unprepare(fep->clk_ipg); 4365 pm_runtime_put_noidle(&pdev->dev); 4366 pm_runtime_disable(&pdev->dev); 4367 4368 free_netdev(ndev); 4369 return 0; 4370 } 4371 4372 static int __maybe_unused fec_suspend(struct device *dev) 4373 { 4374 struct net_device *ndev = dev_get_drvdata(dev); 4375 struct fec_enet_private *fep = netdev_priv(ndev); 4376 int ret; 4377 4378 rtnl_lock(); 4379 if (netif_running(ndev)) { 4380 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4381 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4382 phy_stop(ndev->phydev); 4383 napi_disable(&fep->napi); 4384 netif_tx_lock_bh(ndev); 4385 netif_device_detach(ndev); 4386 netif_tx_unlock_bh(ndev); 4387 fec_stop(ndev); 4388 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4389 fec_irqs_disable(ndev); 4390 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4391 } else { 4392 fec_irqs_disable_except_wakeup(ndev); 4393 if (fep->wake_irq > 0) { 4394 disable_irq(fep->wake_irq); 4395 enable_irq_wake(fep->wake_irq); 4396 } 4397 fec_enet_stop_mode(fep, true); 4398 } 4399 /* It's safe to disable clocks since interrupts are masked */ 4400 fec_enet_clk_enable(ndev, false); 4401 4402 fep->rpm_active = !pm_runtime_status_suspended(dev); 4403 if (fep->rpm_active) { 4404 ret = pm_runtime_force_suspend(dev); 4405 if (ret < 0) { 4406 rtnl_unlock(); 4407 return ret; 4408 } 4409 } 4410 } 4411 rtnl_unlock(); 4412 4413 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4414 regulator_disable(fep->reg_phy); 4415 4416 /* SOC supply clock to phy, when clock is disabled, phy link down 4417 * SOC control phy regulator, when regulator is disabled, phy link down 4418 */ 4419 if (fep->clk_enet_out || fep->reg_phy) 4420 fep->link = 0; 4421 4422 return 0; 4423 } 4424 4425 static int __maybe_unused fec_resume(struct device *dev) 4426 { 4427 struct net_device *ndev = dev_get_drvdata(dev); 4428 struct fec_enet_private *fep = netdev_priv(ndev); 4429 int ret; 4430 int val; 4431 4432 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4433 ret = regulator_enable(fep->reg_phy); 4434 if (ret) 4435 return ret; 4436 } 4437 4438 rtnl_lock(); 4439 if (netif_running(ndev)) { 4440 if (fep->rpm_active) 4441 pm_runtime_force_resume(dev); 4442 4443 ret = fec_enet_clk_enable(ndev, true); 4444 if (ret) { 4445 rtnl_unlock(); 4446 goto failed_clk; 4447 } 4448 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4449 fec_enet_stop_mode(fep, false); 4450 if (fep->wake_irq) { 4451 disable_irq_wake(fep->wake_irq); 4452 enable_irq(fep->wake_irq); 4453 } 4454 4455 val = readl(fep->hwp + FEC_ECNTRL); 4456 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4457 writel(val, fep->hwp + FEC_ECNTRL); 4458 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4459 } else { 4460 pinctrl_pm_select_default_state(&fep->pdev->dev); 4461 } 4462 fec_restart(ndev); 4463 netif_tx_lock_bh(ndev); 4464 netif_device_attach(ndev); 4465 netif_tx_unlock_bh(ndev); 4466 napi_enable(&fep->napi); 4467 phy_init_hw(ndev->phydev); 4468 phy_start(ndev->phydev); 4469 } 4470 rtnl_unlock(); 4471 4472 return 0; 4473 4474 failed_clk: 4475 if (fep->reg_phy) 4476 regulator_disable(fep->reg_phy); 4477 return ret; 4478 } 4479 4480 static int __maybe_unused fec_runtime_suspend(struct device *dev) 4481 { 4482 struct net_device *ndev = dev_get_drvdata(dev); 4483 struct fec_enet_private *fep = netdev_priv(ndev); 4484 4485 clk_disable_unprepare(fep->clk_ahb); 4486 clk_disable_unprepare(fep->clk_ipg); 4487 4488 return 0; 4489 } 4490 4491 static int __maybe_unused fec_runtime_resume(struct device *dev) 4492 { 4493 struct net_device *ndev = dev_get_drvdata(dev); 4494 struct fec_enet_private *fep = netdev_priv(ndev); 4495 int ret; 4496 4497 ret = clk_prepare_enable(fep->clk_ahb); 4498 if (ret) 4499 return ret; 4500 ret = clk_prepare_enable(fep->clk_ipg); 4501 if (ret) 4502 goto failed_clk_ipg; 4503 4504 return 0; 4505 4506 failed_clk_ipg: 4507 clk_disable_unprepare(fep->clk_ahb); 4508 return ret; 4509 } 4510 4511 static const struct dev_pm_ops fec_pm_ops = { 4512 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4513 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4514 }; 4515 4516 static struct platform_driver fec_driver = { 4517 .driver = { 4518 .name = DRIVER_NAME, 4519 .pm = &fec_pm_ops, 4520 .of_match_table = fec_dt_ids, 4521 .suppress_bind_attrs = true, 4522 }, 4523 .id_table = fec_devtype, 4524 .probe = fec_probe, 4525 .remove = fec_drv_remove, 4526 }; 4527 4528 module_platform_driver(fec_driver); 4529 4530 MODULE_LICENSE("GPL"); 4531