1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/tso.h> 42 #include <linux/tcp.h> 43 #include <linux/udp.h> 44 #include <linux/icmp.h> 45 #include <linux/spinlock.h> 46 #include <linux/workqueue.h> 47 #include <linux/bitops.h> 48 #include <linux/io.h> 49 #include <linux/irq.h> 50 #include <linux/clk.h> 51 #include <linux/crc32.h> 52 #include <linux/platform_device.h> 53 #include <linux/mdio.h> 54 #include <linux/phy.h> 55 #include <linux/fec.h> 56 #include <linux/of.h> 57 #include <linux/of_device.h> 58 #include <linux/of_gpio.h> 59 #include <linux/of_mdio.h> 60 #include <linux/of_net.h> 61 #include <linux/regulator/consumer.h> 62 #include <linux/if_vlan.h> 63 #include <linux/pinctrl/consumer.h> 64 #include <linux/prefetch.h> 65 #include <soc/imx/cpuidle.h> 66 67 #include <asm/cacheflush.h> 68 69 #include "fec.h" 70 71 static void set_multicast_list(struct net_device *ndev); 72 static void fec_enet_itr_coal_init(struct net_device *ndev); 73 74 #define DRIVER_NAME "fec" 75 76 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0)) 77 78 /* Pause frame feild and FIFO threshold */ 79 #define FEC_ENET_FCE (1 << 5) 80 #define FEC_ENET_RSEM_V 0x84 81 #define FEC_ENET_RSFL_V 16 82 #define FEC_ENET_RAEM_V 0x8 83 #define FEC_ENET_RAFL_V 0x8 84 #define FEC_ENET_OPD_V 0xFFF0 85 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 86 87 static struct platform_device_id fec_devtype[] = { 88 { 89 /* keep it for coldfire */ 90 .name = DRIVER_NAME, 91 .driver_data = 0, 92 }, { 93 .name = "imx25-fec", 94 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR, 95 }, { 96 .name = "imx27-fec", 97 .driver_data = FEC_QUIRK_MIB_CLEAR, 98 }, { 99 .name = "imx28-fec", 100 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 101 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC, 102 }, { 103 .name = "imx6q-fec", 104 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 105 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 106 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 107 FEC_QUIRK_HAS_RACC, 108 }, { 109 .name = "mvf600-fec", 110 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 111 }, { 112 .name = "imx6sx-fec", 113 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 114 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 115 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 116 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 117 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE, 118 }, { 119 .name = "imx6ul-fec", 120 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 121 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 122 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 123 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 124 FEC_QUIRK_HAS_COALESCE, 125 }, { 126 /* sentinel */ 127 } 128 }; 129 MODULE_DEVICE_TABLE(platform, fec_devtype); 130 131 enum imx_fec_type { 132 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 133 IMX27_FEC, /* runs on i.mx27/35/51 */ 134 IMX28_FEC, 135 IMX6Q_FEC, 136 MVF600_FEC, 137 IMX6SX_FEC, 138 IMX6UL_FEC, 139 }; 140 141 static const struct of_device_id fec_dt_ids[] = { 142 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 143 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 144 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 145 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 146 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 147 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 148 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 149 { /* sentinel */ } 150 }; 151 MODULE_DEVICE_TABLE(of, fec_dt_ids); 152 153 static unsigned char macaddr[ETH_ALEN]; 154 module_param_array(macaddr, byte, NULL, 0); 155 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 156 157 #if defined(CONFIG_M5272) 158 /* 159 * Some hardware gets it MAC address out of local flash memory. 160 * if this is non-zero then assume it is the address to get MAC from. 161 */ 162 #if defined(CONFIG_NETtel) 163 #define FEC_FLASHMAC 0xf0006006 164 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 165 #define FEC_FLASHMAC 0xf0006000 166 #elif defined(CONFIG_CANCam) 167 #define FEC_FLASHMAC 0xf0020000 168 #elif defined (CONFIG_M5272C3) 169 #define FEC_FLASHMAC (0xffe04000 + 4) 170 #elif defined(CONFIG_MOD5272) 171 #define FEC_FLASHMAC 0xffc0406b 172 #else 173 #define FEC_FLASHMAC 0 174 #endif 175 #endif /* CONFIG_M5272 */ 176 177 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 178 * 179 * 2048 byte skbufs are allocated. However, alignment requirements 180 * varies between FEC variants. Worst case is 64, so round down by 64. 181 */ 182 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 183 #define PKT_MINBUF_SIZE 64 184 185 /* FEC receive acceleration */ 186 #define FEC_RACC_IPDIS (1 << 1) 187 #define FEC_RACC_PRODIS (1 << 2) 188 #define FEC_RACC_SHIFT16 BIT(7) 189 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 190 191 /* MIB Control Register */ 192 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 193 194 /* 195 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 196 * size bits. Other FEC hardware does not, so we need to take that into 197 * account when setting it. 198 */ 199 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 200 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 201 defined(CONFIG_ARM64) 202 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 203 #else 204 #define OPT_FRAME_SIZE 0 205 #endif 206 207 /* FEC MII MMFR bits definition */ 208 #define FEC_MMFR_ST (1 << 30) 209 #define FEC_MMFR_OP_READ (2 << 28) 210 #define FEC_MMFR_OP_WRITE (1 << 28) 211 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 212 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 213 #define FEC_MMFR_TA (2 << 16) 214 #define FEC_MMFR_DATA(v) (v & 0xffff) 215 /* FEC ECR bits definition */ 216 #define FEC_ECR_MAGICEN (1 << 2) 217 #define FEC_ECR_SLEEP (1 << 3) 218 219 #define FEC_MII_TIMEOUT 30000 /* us */ 220 221 /* Transmitter timeout */ 222 #define TX_TIMEOUT (2 * HZ) 223 224 #define FEC_PAUSE_FLAG_AUTONEG 0x1 225 #define FEC_PAUSE_FLAG_ENABLE 0x2 226 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 227 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 228 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 229 230 #define COPYBREAK_DEFAULT 256 231 232 /* Max number of allowed TCP segments for software TSO */ 233 #define FEC_MAX_TSO_SEGS 100 234 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 235 236 #define IS_TSO_HEADER(txq, addr) \ 237 ((addr >= txq->tso_hdrs_dma) && \ 238 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 239 240 static int mii_cnt; 241 242 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 243 struct bufdesc_prop *bd) 244 { 245 return (bdp >= bd->last) ? bd->base 246 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 247 } 248 249 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 250 struct bufdesc_prop *bd) 251 { 252 return (bdp <= bd->base) ? bd->last 253 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 254 } 255 256 static int fec_enet_get_bd_index(struct bufdesc *bdp, 257 struct bufdesc_prop *bd) 258 { 259 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 260 } 261 262 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 263 { 264 int entries; 265 266 entries = (((const char *)txq->dirty_tx - 267 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 268 269 return entries >= 0 ? entries : entries + txq->bd.ring_size; 270 } 271 272 static void swap_buffer(void *bufaddr, int len) 273 { 274 int i; 275 unsigned int *buf = bufaddr; 276 277 for (i = 0; i < len; i += 4, buf++) 278 swab32s(buf); 279 } 280 281 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 282 { 283 int i; 284 unsigned int *src = src_buf; 285 unsigned int *dst = dst_buf; 286 287 for (i = 0; i < len; i += 4, src++, dst++) 288 *dst = swab32p(src); 289 } 290 291 static void fec_dump(struct net_device *ndev) 292 { 293 struct fec_enet_private *fep = netdev_priv(ndev); 294 struct bufdesc *bdp; 295 struct fec_enet_priv_tx_q *txq; 296 int index = 0; 297 298 netdev_info(ndev, "TX ring dump\n"); 299 pr_info("Nr SC addr len SKB\n"); 300 301 txq = fep->tx_queue[0]; 302 bdp = txq->bd.base; 303 304 do { 305 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 306 index, 307 bdp == txq->bd.cur ? 'S' : ' ', 308 bdp == txq->dirty_tx ? 'H' : ' ', 309 fec16_to_cpu(bdp->cbd_sc), 310 fec32_to_cpu(bdp->cbd_bufaddr), 311 fec16_to_cpu(bdp->cbd_datlen), 312 txq->tx_skbuff[index]); 313 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 314 index++; 315 } while (bdp != txq->bd.base); 316 } 317 318 static inline bool is_ipv4_pkt(struct sk_buff *skb) 319 { 320 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 321 } 322 323 static int 324 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 325 { 326 /* Only run for packets requiring a checksum. */ 327 if (skb->ip_summed != CHECKSUM_PARTIAL) 328 return 0; 329 330 if (unlikely(skb_cow_head(skb, 0))) 331 return -1; 332 333 if (is_ipv4_pkt(skb)) 334 ip_hdr(skb)->check = 0; 335 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 336 337 return 0; 338 } 339 340 static struct bufdesc * 341 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 342 struct sk_buff *skb, 343 struct net_device *ndev) 344 { 345 struct fec_enet_private *fep = netdev_priv(ndev); 346 struct bufdesc *bdp = txq->bd.cur; 347 struct bufdesc_ex *ebdp; 348 int nr_frags = skb_shinfo(skb)->nr_frags; 349 int frag, frag_len; 350 unsigned short status; 351 unsigned int estatus = 0; 352 skb_frag_t *this_frag; 353 unsigned int index; 354 void *bufaddr; 355 dma_addr_t addr; 356 int i; 357 358 for (frag = 0; frag < nr_frags; frag++) { 359 this_frag = &skb_shinfo(skb)->frags[frag]; 360 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 361 ebdp = (struct bufdesc_ex *)bdp; 362 363 status = fec16_to_cpu(bdp->cbd_sc); 364 status &= ~BD_ENET_TX_STATS; 365 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 366 frag_len = skb_shinfo(skb)->frags[frag].size; 367 368 /* Handle the last BD specially */ 369 if (frag == nr_frags - 1) { 370 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 371 if (fep->bufdesc_ex) { 372 estatus |= BD_ENET_TX_INT; 373 if (unlikely(skb_shinfo(skb)->tx_flags & 374 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 375 estatus |= BD_ENET_TX_TS; 376 } 377 } 378 379 if (fep->bufdesc_ex) { 380 if (fep->quirks & FEC_QUIRK_HAS_AVB) 381 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 382 if (skb->ip_summed == CHECKSUM_PARTIAL) 383 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 384 ebdp->cbd_bdu = 0; 385 ebdp->cbd_esc = cpu_to_fec32(estatus); 386 } 387 388 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset; 389 390 index = fec_enet_get_bd_index(bdp, &txq->bd); 391 if (((unsigned long) bufaddr) & fep->tx_align || 392 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 393 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 394 bufaddr = txq->tx_bounce[index]; 395 396 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 397 swap_buffer(bufaddr, frag_len); 398 } 399 400 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 401 DMA_TO_DEVICE); 402 if (dma_mapping_error(&fep->pdev->dev, addr)) { 403 if (net_ratelimit()) 404 netdev_err(ndev, "Tx DMA memory map failed\n"); 405 goto dma_mapping_error; 406 } 407 408 bdp->cbd_bufaddr = cpu_to_fec32(addr); 409 bdp->cbd_datlen = cpu_to_fec16(frag_len); 410 /* Make sure the updates to rest of the descriptor are 411 * performed before transferring ownership. 412 */ 413 wmb(); 414 bdp->cbd_sc = cpu_to_fec16(status); 415 } 416 417 return bdp; 418 dma_mapping_error: 419 bdp = txq->bd.cur; 420 for (i = 0; i < frag; i++) { 421 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 422 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 423 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 424 } 425 return ERR_PTR(-ENOMEM); 426 } 427 428 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 429 struct sk_buff *skb, struct net_device *ndev) 430 { 431 struct fec_enet_private *fep = netdev_priv(ndev); 432 int nr_frags = skb_shinfo(skb)->nr_frags; 433 struct bufdesc *bdp, *last_bdp; 434 void *bufaddr; 435 dma_addr_t addr; 436 unsigned short status; 437 unsigned short buflen; 438 unsigned int estatus = 0; 439 unsigned int index; 440 int entries_free; 441 442 entries_free = fec_enet_get_free_txdesc_num(txq); 443 if (entries_free < MAX_SKB_FRAGS + 1) { 444 dev_kfree_skb_any(skb); 445 if (net_ratelimit()) 446 netdev_err(ndev, "NOT enough BD for SG!\n"); 447 return NETDEV_TX_OK; 448 } 449 450 /* Protocol checksum off-load for TCP and UDP. */ 451 if (fec_enet_clear_csum(skb, ndev)) { 452 dev_kfree_skb_any(skb); 453 return NETDEV_TX_OK; 454 } 455 456 /* Fill in a Tx ring entry */ 457 bdp = txq->bd.cur; 458 last_bdp = bdp; 459 status = fec16_to_cpu(bdp->cbd_sc); 460 status &= ~BD_ENET_TX_STATS; 461 462 /* Set buffer length and buffer pointer */ 463 bufaddr = skb->data; 464 buflen = skb_headlen(skb); 465 466 index = fec_enet_get_bd_index(bdp, &txq->bd); 467 if (((unsigned long) bufaddr) & fep->tx_align || 468 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 469 memcpy(txq->tx_bounce[index], skb->data, buflen); 470 bufaddr = txq->tx_bounce[index]; 471 472 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 473 swap_buffer(bufaddr, buflen); 474 } 475 476 /* Push the data cache so the CPM does not get stale memory data. */ 477 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 478 if (dma_mapping_error(&fep->pdev->dev, addr)) { 479 dev_kfree_skb_any(skb); 480 if (net_ratelimit()) 481 netdev_err(ndev, "Tx DMA memory map failed\n"); 482 return NETDEV_TX_OK; 483 } 484 485 if (nr_frags) { 486 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 487 if (IS_ERR(last_bdp)) { 488 dma_unmap_single(&fep->pdev->dev, addr, 489 buflen, DMA_TO_DEVICE); 490 dev_kfree_skb_any(skb); 491 return NETDEV_TX_OK; 492 } 493 } else { 494 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 495 if (fep->bufdesc_ex) { 496 estatus = BD_ENET_TX_INT; 497 if (unlikely(skb_shinfo(skb)->tx_flags & 498 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 499 estatus |= BD_ENET_TX_TS; 500 } 501 } 502 bdp->cbd_bufaddr = cpu_to_fec32(addr); 503 bdp->cbd_datlen = cpu_to_fec16(buflen); 504 505 if (fep->bufdesc_ex) { 506 507 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 508 509 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 510 fep->hwts_tx_en)) 511 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 512 513 if (fep->quirks & FEC_QUIRK_HAS_AVB) 514 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 515 516 if (skb->ip_summed == CHECKSUM_PARTIAL) 517 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 518 519 ebdp->cbd_bdu = 0; 520 ebdp->cbd_esc = cpu_to_fec32(estatus); 521 } 522 523 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 524 /* Save skb pointer */ 525 txq->tx_skbuff[index] = skb; 526 527 /* Make sure the updates to rest of the descriptor are performed before 528 * transferring ownership. 529 */ 530 wmb(); 531 532 /* Send it on its way. Tell FEC it's ready, interrupt when done, 533 * it's the last BD of the frame, and to put the CRC on the end. 534 */ 535 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 536 bdp->cbd_sc = cpu_to_fec16(status); 537 538 /* If this was the last BD in the ring, start at the beginning again. */ 539 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 540 541 skb_tx_timestamp(skb); 542 543 /* Make sure the update to bdp and tx_skbuff are performed before 544 * txq->bd.cur. 545 */ 546 wmb(); 547 txq->bd.cur = bdp; 548 549 /* Trigger transmission start */ 550 writel(0, txq->bd.reg_desc_active); 551 552 return 0; 553 } 554 555 static int 556 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 557 struct net_device *ndev, 558 struct bufdesc *bdp, int index, char *data, 559 int size, bool last_tcp, bool is_last) 560 { 561 struct fec_enet_private *fep = netdev_priv(ndev); 562 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 563 unsigned short status; 564 unsigned int estatus = 0; 565 dma_addr_t addr; 566 567 status = fec16_to_cpu(bdp->cbd_sc); 568 status &= ~BD_ENET_TX_STATS; 569 570 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 571 572 if (((unsigned long) data) & fep->tx_align || 573 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 574 memcpy(txq->tx_bounce[index], data, size); 575 data = txq->tx_bounce[index]; 576 577 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 578 swap_buffer(data, size); 579 } 580 581 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 582 if (dma_mapping_error(&fep->pdev->dev, addr)) { 583 dev_kfree_skb_any(skb); 584 if (net_ratelimit()) 585 netdev_err(ndev, "Tx DMA memory map failed\n"); 586 return NETDEV_TX_BUSY; 587 } 588 589 bdp->cbd_datlen = cpu_to_fec16(size); 590 bdp->cbd_bufaddr = cpu_to_fec32(addr); 591 592 if (fep->bufdesc_ex) { 593 if (fep->quirks & FEC_QUIRK_HAS_AVB) 594 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 595 if (skb->ip_summed == CHECKSUM_PARTIAL) 596 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 597 ebdp->cbd_bdu = 0; 598 ebdp->cbd_esc = cpu_to_fec32(estatus); 599 } 600 601 /* Handle the last BD specially */ 602 if (last_tcp) 603 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 604 if (is_last) { 605 status |= BD_ENET_TX_INTR; 606 if (fep->bufdesc_ex) 607 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 608 } 609 610 bdp->cbd_sc = cpu_to_fec16(status); 611 612 return 0; 613 } 614 615 static int 616 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 617 struct sk_buff *skb, struct net_device *ndev, 618 struct bufdesc *bdp, int index) 619 { 620 struct fec_enet_private *fep = netdev_priv(ndev); 621 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 622 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 623 void *bufaddr; 624 unsigned long dmabuf; 625 unsigned short status; 626 unsigned int estatus = 0; 627 628 status = fec16_to_cpu(bdp->cbd_sc); 629 status &= ~BD_ENET_TX_STATS; 630 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 631 632 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 633 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 634 if (((unsigned long)bufaddr) & fep->tx_align || 635 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 636 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 637 bufaddr = txq->tx_bounce[index]; 638 639 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 640 swap_buffer(bufaddr, hdr_len); 641 642 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 643 hdr_len, DMA_TO_DEVICE); 644 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 645 dev_kfree_skb_any(skb); 646 if (net_ratelimit()) 647 netdev_err(ndev, "Tx DMA memory map failed\n"); 648 return NETDEV_TX_BUSY; 649 } 650 } 651 652 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 653 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 654 655 if (fep->bufdesc_ex) { 656 if (fep->quirks & FEC_QUIRK_HAS_AVB) 657 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 658 if (skb->ip_summed == CHECKSUM_PARTIAL) 659 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 660 ebdp->cbd_bdu = 0; 661 ebdp->cbd_esc = cpu_to_fec32(estatus); 662 } 663 664 bdp->cbd_sc = cpu_to_fec16(status); 665 666 return 0; 667 } 668 669 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 670 struct sk_buff *skb, 671 struct net_device *ndev) 672 { 673 struct fec_enet_private *fep = netdev_priv(ndev); 674 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 675 int total_len, data_left; 676 struct bufdesc *bdp = txq->bd.cur; 677 struct tso_t tso; 678 unsigned int index = 0; 679 int ret; 680 681 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 682 dev_kfree_skb_any(skb); 683 if (net_ratelimit()) 684 netdev_err(ndev, "NOT enough BD for TSO!\n"); 685 return NETDEV_TX_OK; 686 } 687 688 /* Protocol checksum off-load for TCP and UDP. */ 689 if (fec_enet_clear_csum(skb, ndev)) { 690 dev_kfree_skb_any(skb); 691 return NETDEV_TX_OK; 692 } 693 694 /* Initialize the TSO handler, and prepare the first payload */ 695 tso_start(skb, &tso); 696 697 total_len = skb->len - hdr_len; 698 while (total_len > 0) { 699 char *hdr; 700 701 index = fec_enet_get_bd_index(bdp, &txq->bd); 702 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 703 total_len -= data_left; 704 705 /* prepare packet headers: MAC + IP + TCP */ 706 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 707 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 708 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 709 if (ret) 710 goto err_release; 711 712 while (data_left > 0) { 713 int size; 714 715 size = min_t(int, tso.size, data_left); 716 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 717 index = fec_enet_get_bd_index(bdp, &txq->bd); 718 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 719 bdp, index, 720 tso.data, size, 721 size == data_left, 722 total_len == 0); 723 if (ret) 724 goto err_release; 725 726 data_left -= size; 727 tso_build_data(skb, &tso, size); 728 } 729 730 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 731 } 732 733 /* Save skb pointer */ 734 txq->tx_skbuff[index] = skb; 735 736 skb_tx_timestamp(skb); 737 txq->bd.cur = bdp; 738 739 /* Trigger transmission start */ 740 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 741 !readl(txq->bd.reg_desc_active) || 742 !readl(txq->bd.reg_desc_active) || 743 !readl(txq->bd.reg_desc_active) || 744 !readl(txq->bd.reg_desc_active)) 745 writel(0, txq->bd.reg_desc_active); 746 747 return 0; 748 749 err_release: 750 /* TODO: Release all used data descriptors for TSO */ 751 return ret; 752 } 753 754 static netdev_tx_t 755 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 756 { 757 struct fec_enet_private *fep = netdev_priv(ndev); 758 int entries_free; 759 unsigned short queue; 760 struct fec_enet_priv_tx_q *txq; 761 struct netdev_queue *nq; 762 int ret; 763 764 queue = skb_get_queue_mapping(skb); 765 txq = fep->tx_queue[queue]; 766 nq = netdev_get_tx_queue(ndev, queue); 767 768 if (skb_is_gso(skb)) 769 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 770 else 771 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 772 if (ret) 773 return ret; 774 775 entries_free = fec_enet_get_free_txdesc_num(txq); 776 if (entries_free <= txq->tx_stop_threshold) 777 netif_tx_stop_queue(nq); 778 779 return NETDEV_TX_OK; 780 } 781 782 /* Init RX & TX buffer descriptors 783 */ 784 static void fec_enet_bd_init(struct net_device *dev) 785 { 786 struct fec_enet_private *fep = netdev_priv(dev); 787 struct fec_enet_priv_tx_q *txq; 788 struct fec_enet_priv_rx_q *rxq; 789 struct bufdesc *bdp; 790 unsigned int i; 791 unsigned int q; 792 793 for (q = 0; q < fep->num_rx_queues; q++) { 794 /* Initialize the receive buffer descriptors. */ 795 rxq = fep->rx_queue[q]; 796 bdp = rxq->bd.base; 797 798 for (i = 0; i < rxq->bd.ring_size; i++) { 799 800 /* Initialize the BD for every fragment in the page. */ 801 if (bdp->cbd_bufaddr) 802 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 803 else 804 bdp->cbd_sc = cpu_to_fec16(0); 805 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 806 } 807 808 /* Set the last buffer to wrap */ 809 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 810 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 811 812 rxq->bd.cur = rxq->bd.base; 813 } 814 815 for (q = 0; q < fep->num_tx_queues; q++) { 816 /* ...and the same for transmit */ 817 txq = fep->tx_queue[q]; 818 bdp = txq->bd.base; 819 txq->bd.cur = bdp; 820 821 for (i = 0; i < txq->bd.ring_size; i++) { 822 /* Initialize the BD for every fragment in the page. */ 823 bdp->cbd_sc = cpu_to_fec16(0); 824 if (bdp->cbd_bufaddr && 825 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 826 dma_unmap_single(&fep->pdev->dev, 827 fec32_to_cpu(bdp->cbd_bufaddr), 828 fec16_to_cpu(bdp->cbd_datlen), 829 DMA_TO_DEVICE); 830 if (txq->tx_skbuff[i]) { 831 dev_kfree_skb_any(txq->tx_skbuff[i]); 832 txq->tx_skbuff[i] = NULL; 833 } 834 bdp->cbd_bufaddr = cpu_to_fec32(0); 835 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 836 } 837 838 /* Set the last buffer to wrap */ 839 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 840 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 841 txq->dirty_tx = bdp; 842 } 843 } 844 845 static void fec_enet_active_rxring(struct net_device *ndev) 846 { 847 struct fec_enet_private *fep = netdev_priv(ndev); 848 int i; 849 850 for (i = 0; i < fep->num_rx_queues; i++) 851 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 852 } 853 854 static void fec_enet_enable_ring(struct net_device *ndev) 855 { 856 struct fec_enet_private *fep = netdev_priv(ndev); 857 struct fec_enet_priv_tx_q *txq; 858 struct fec_enet_priv_rx_q *rxq; 859 int i; 860 861 for (i = 0; i < fep->num_rx_queues; i++) { 862 rxq = fep->rx_queue[i]; 863 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 864 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 865 866 /* enable DMA1/2 */ 867 if (i) 868 writel(RCMR_MATCHEN | RCMR_CMP(i), 869 fep->hwp + FEC_RCMR(i)); 870 } 871 872 for (i = 0; i < fep->num_tx_queues; i++) { 873 txq = fep->tx_queue[i]; 874 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 875 876 /* enable DMA1/2 */ 877 if (i) 878 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 879 fep->hwp + FEC_DMA_CFG(i)); 880 } 881 } 882 883 static void fec_enet_reset_skb(struct net_device *ndev) 884 { 885 struct fec_enet_private *fep = netdev_priv(ndev); 886 struct fec_enet_priv_tx_q *txq; 887 int i, j; 888 889 for (i = 0; i < fep->num_tx_queues; i++) { 890 txq = fep->tx_queue[i]; 891 892 for (j = 0; j < txq->bd.ring_size; j++) { 893 if (txq->tx_skbuff[j]) { 894 dev_kfree_skb_any(txq->tx_skbuff[j]); 895 txq->tx_skbuff[j] = NULL; 896 } 897 } 898 } 899 } 900 901 /* 902 * This function is called to start or restart the FEC during a link 903 * change, transmit timeout, or to reconfigure the FEC. The network 904 * packet processing for this device must be stopped before this call. 905 */ 906 static void 907 fec_restart(struct net_device *ndev) 908 { 909 struct fec_enet_private *fep = netdev_priv(ndev); 910 u32 val; 911 u32 temp_mac[2]; 912 u32 rcntl = OPT_FRAME_SIZE | 0x04; 913 u32 ecntl = 0x2; /* ETHEREN */ 914 915 /* Whack a reset. We should wait for this. 916 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 917 * instead of reset MAC itself. 918 */ 919 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 920 writel(0, fep->hwp + FEC_ECNTRL); 921 } else { 922 writel(1, fep->hwp + FEC_ECNTRL); 923 udelay(10); 924 } 925 926 /* 927 * enet-mac reset will reset mac address registers too, 928 * so need to reconfigure it. 929 */ 930 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 931 writel((__force u32)cpu_to_be32(temp_mac[0]), 932 fep->hwp + FEC_ADDR_LOW); 933 writel((__force u32)cpu_to_be32(temp_mac[1]), 934 fep->hwp + FEC_ADDR_HIGH); 935 936 /* Clear any outstanding interrupt. */ 937 writel(0xffffffff, fep->hwp + FEC_IEVENT); 938 939 fec_enet_bd_init(ndev); 940 941 fec_enet_enable_ring(ndev); 942 943 /* Reset tx SKB buffers. */ 944 fec_enet_reset_skb(ndev); 945 946 /* Enable MII mode */ 947 if (fep->full_duplex == DUPLEX_FULL) { 948 /* FD enable */ 949 writel(0x04, fep->hwp + FEC_X_CNTRL); 950 } else { 951 /* No Rcv on Xmit */ 952 rcntl |= 0x02; 953 writel(0x0, fep->hwp + FEC_X_CNTRL); 954 } 955 956 /* Set MII speed */ 957 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 958 959 #if !defined(CONFIG_M5272) 960 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 961 val = readl(fep->hwp + FEC_RACC); 962 /* align IP header */ 963 val |= FEC_RACC_SHIFT16; 964 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 965 /* set RX checksum */ 966 val |= FEC_RACC_OPTIONS; 967 else 968 val &= ~FEC_RACC_OPTIONS; 969 writel(val, fep->hwp + FEC_RACC); 970 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 971 } 972 #endif 973 974 /* 975 * The phy interface and speed need to get configured 976 * differently on enet-mac. 977 */ 978 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 979 /* Enable flow control and length check */ 980 rcntl |= 0x40000000 | 0x00000020; 981 982 /* RGMII, RMII or MII */ 983 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 984 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 985 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 986 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 987 rcntl |= (1 << 6); 988 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 989 rcntl |= (1 << 8); 990 else 991 rcntl &= ~(1 << 8); 992 993 /* 1G, 100M or 10M */ 994 if (ndev->phydev) { 995 if (ndev->phydev->speed == SPEED_1000) 996 ecntl |= (1 << 5); 997 else if (ndev->phydev->speed == SPEED_100) 998 rcntl &= ~(1 << 9); 999 else 1000 rcntl |= (1 << 9); 1001 } 1002 } else { 1003 #ifdef FEC_MIIGSK_ENR 1004 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1005 u32 cfgr; 1006 /* disable the gasket and wait */ 1007 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1008 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1009 udelay(1); 1010 1011 /* 1012 * configure the gasket: 1013 * RMII, 50 MHz, no loopback, no echo 1014 * MII, 25 MHz, no loopback, no echo 1015 */ 1016 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1017 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1018 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1019 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1020 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1021 1022 /* re-enable the gasket */ 1023 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1024 } 1025 #endif 1026 } 1027 1028 #if !defined(CONFIG_M5272) 1029 /* enable pause frame*/ 1030 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1031 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1032 ndev->phydev && ndev->phydev->pause)) { 1033 rcntl |= FEC_ENET_FCE; 1034 1035 /* set FIFO threshold parameter to reduce overrun */ 1036 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1037 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1038 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1039 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1040 1041 /* OPD */ 1042 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1043 } else { 1044 rcntl &= ~FEC_ENET_FCE; 1045 } 1046 #endif /* !defined(CONFIG_M5272) */ 1047 1048 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1049 1050 /* Setup multicast filter. */ 1051 set_multicast_list(ndev); 1052 #ifndef CONFIG_M5272 1053 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1054 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1055 #endif 1056 1057 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1058 /* enable ENET endian swap */ 1059 ecntl |= (1 << 8); 1060 /* enable ENET store and forward mode */ 1061 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1062 } 1063 1064 if (fep->bufdesc_ex) 1065 ecntl |= (1 << 4); 1066 1067 #ifndef CONFIG_M5272 1068 /* Enable the MIB statistic event counters */ 1069 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1070 #endif 1071 1072 /* And last, enable the transmit and receive processing */ 1073 writel(ecntl, fep->hwp + FEC_ECNTRL); 1074 fec_enet_active_rxring(ndev); 1075 1076 if (fep->bufdesc_ex) 1077 fec_ptp_start_cyclecounter(ndev); 1078 1079 /* Enable interrupts we wish to service */ 1080 if (fep->link) 1081 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1082 else 1083 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); 1084 1085 /* Init the interrupt coalescing */ 1086 fec_enet_itr_coal_init(ndev); 1087 1088 } 1089 1090 static void 1091 fec_stop(struct net_device *ndev) 1092 { 1093 struct fec_enet_private *fep = netdev_priv(ndev); 1094 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1095 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1096 u32 val; 1097 1098 /* We cannot expect a graceful transmit stop without link !!! */ 1099 if (fep->link) { 1100 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1101 udelay(10); 1102 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1103 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1104 } 1105 1106 /* Whack a reset. We should wait for this. 1107 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1108 * instead of reset MAC itself. 1109 */ 1110 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1111 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 1112 writel(0, fep->hwp + FEC_ECNTRL); 1113 } else { 1114 writel(1, fep->hwp + FEC_ECNTRL); 1115 udelay(10); 1116 } 1117 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1118 } else { 1119 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1120 val = readl(fep->hwp + FEC_ECNTRL); 1121 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1122 writel(val, fep->hwp + FEC_ECNTRL); 1123 1124 if (pdata && pdata->sleep_mode_enable) 1125 pdata->sleep_mode_enable(true); 1126 } 1127 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1128 1129 /* We have to keep ENET enabled to have MII interrupt stay working */ 1130 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1131 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1132 writel(2, fep->hwp + FEC_ECNTRL); 1133 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1134 } 1135 } 1136 1137 1138 static void 1139 fec_timeout(struct net_device *ndev) 1140 { 1141 struct fec_enet_private *fep = netdev_priv(ndev); 1142 1143 fec_dump(ndev); 1144 1145 ndev->stats.tx_errors++; 1146 1147 schedule_work(&fep->tx_timeout_work); 1148 } 1149 1150 static void fec_enet_timeout_work(struct work_struct *work) 1151 { 1152 struct fec_enet_private *fep = 1153 container_of(work, struct fec_enet_private, tx_timeout_work); 1154 struct net_device *ndev = fep->netdev; 1155 1156 rtnl_lock(); 1157 if (netif_device_present(ndev) || netif_running(ndev)) { 1158 napi_disable(&fep->napi); 1159 netif_tx_lock_bh(ndev); 1160 fec_restart(ndev); 1161 netif_wake_queue(ndev); 1162 netif_tx_unlock_bh(ndev); 1163 napi_enable(&fep->napi); 1164 } 1165 rtnl_unlock(); 1166 } 1167 1168 static void 1169 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1170 struct skb_shared_hwtstamps *hwtstamps) 1171 { 1172 unsigned long flags; 1173 u64 ns; 1174 1175 spin_lock_irqsave(&fep->tmreg_lock, flags); 1176 ns = timecounter_cyc2time(&fep->tc, ts); 1177 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1178 1179 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1180 hwtstamps->hwtstamp = ns_to_ktime(ns); 1181 } 1182 1183 static void 1184 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1185 { 1186 struct fec_enet_private *fep; 1187 struct bufdesc *bdp; 1188 unsigned short status; 1189 struct sk_buff *skb; 1190 struct fec_enet_priv_tx_q *txq; 1191 struct netdev_queue *nq; 1192 int index = 0; 1193 int entries_free; 1194 1195 fep = netdev_priv(ndev); 1196 1197 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1198 1199 txq = fep->tx_queue[queue_id]; 1200 /* get next bdp of dirty_tx */ 1201 nq = netdev_get_tx_queue(ndev, queue_id); 1202 bdp = txq->dirty_tx; 1203 1204 /* get next bdp of dirty_tx */ 1205 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1206 1207 while (bdp != READ_ONCE(txq->bd.cur)) { 1208 /* Order the load of bd.cur and cbd_sc */ 1209 rmb(); 1210 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1211 if (status & BD_ENET_TX_READY) 1212 break; 1213 1214 index = fec_enet_get_bd_index(bdp, &txq->bd); 1215 1216 skb = txq->tx_skbuff[index]; 1217 txq->tx_skbuff[index] = NULL; 1218 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1219 dma_unmap_single(&fep->pdev->dev, 1220 fec32_to_cpu(bdp->cbd_bufaddr), 1221 fec16_to_cpu(bdp->cbd_datlen), 1222 DMA_TO_DEVICE); 1223 bdp->cbd_bufaddr = cpu_to_fec32(0); 1224 if (!skb) 1225 goto skb_done; 1226 1227 /* Check for errors. */ 1228 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1229 BD_ENET_TX_RL | BD_ENET_TX_UN | 1230 BD_ENET_TX_CSL)) { 1231 ndev->stats.tx_errors++; 1232 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1233 ndev->stats.tx_heartbeat_errors++; 1234 if (status & BD_ENET_TX_LC) /* Late collision */ 1235 ndev->stats.tx_window_errors++; 1236 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1237 ndev->stats.tx_aborted_errors++; 1238 if (status & BD_ENET_TX_UN) /* Underrun */ 1239 ndev->stats.tx_fifo_errors++; 1240 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1241 ndev->stats.tx_carrier_errors++; 1242 } else { 1243 ndev->stats.tx_packets++; 1244 ndev->stats.tx_bytes += skb->len; 1245 } 1246 1247 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 1248 fep->bufdesc_ex) { 1249 struct skb_shared_hwtstamps shhwtstamps; 1250 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1251 1252 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1253 skb_tstamp_tx(skb, &shhwtstamps); 1254 } 1255 1256 /* Deferred means some collisions occurred during transmit, 1257 * but we eventually sent the packet OK. 1258 */ 1259 if (status & BD_ENET_TX_DEF) 1260 ndev->stats.collisions++; 1261 1262 /* Free the sk buffer associated with this last transmit */ 1263 dev_kfree_skb_any(skb); 1264 skb_done: 1265 /* Make sure the update to bdp and tx_skbuff are performed 1266 * before dirty_tx 1267 */ 1268 wmb(); 1269 txq->dirty_tx = bdp; 1270 1271 /* Update pointer to next buffer descriptor to be transmitted */ 1272 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1273 1274 /* Since we have freed up a buffer, the ring is no longer full 1275 */ 1276 if (netif_queue_stopped(ndev)) { 1277 entries_free = fec_enet_get_free_txdesc_num(txq); 1278 if (entries_free >= txq->tx_wake_threshold) 1279 netif_tx_wake_queue(nq); 1280 } 1281 } 1282 1283 /* ERR006358: Keep the transmitter going */ 1284 if (bdp != txq->bd.cur && 1285 readl(txq->bd.reg_desc_active) == 0) 1286 writel(0, txq->bd.reg_desc_active); 1287 } 1288 1289 static void 1290 fec_enet_tx(struct net_device *ndev) 1291 { 1292 struct fec_enet_private *fep = netdev_priv(ndev); 1293 u16 queue_id; 1294 /* First process class A queue, then Class B and Best Effort queue */ 1295 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) { 1296 clear_bit(queue_id, &fep->work_tx); 1297 fec_enet_tx_queue(ndev, queue_id); 1298 } 1299 return; 1300 } 1301 1302 static int 1303 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1304 { 1305 struct fec_enet_private *fep = netdev_priv(ndev); 1306 int off; 1307 1308 off = ((unsigned long)skb->data) & fep->rx_align; 1309 if (off) 1310 skb_reserve(skb, fep->rx_align + 1 - off); 1311 1312 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1313 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1314 if (net_ratelimit()) 1315 netdev_err(ndev, "Rx DMA memory map failed\n"); 1316 return -ENOMEM; 1317 } 1318 1319 return 0; 1320 } 1321 1322 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1323 struct bufdesc *bdp, u32 length, bool swap) 1324 { 1325 struct fec_enet_private *fep = netdev_priv(ndev); 1326 struct sk_buff *new_skb; 1327 1328 if (length > fep->rx_copybreak) 1329 return false; 1330 1331 new_skb = netdev_alloc_skb(ndev, length); 1332 if (!new_skb) 1333 return false; 1334 1335 dma_sync_single_for_cpu(&fep->pdev->dev, 1336 fec32_to_cpu(bdp->cbd_bufaddr), 1337 FEC_ENET_RX_FRSIZE - fep->rx_align, 1338 DMA_FROM_DEVICE); 1339 if (!swap) 1340 memcpy(new_skb->data, (*skb)->data, length); 1341 else 1342 swap_buffer2(new_skb->data, (*skb)->data, length); 1343 *skb = new_skb; 1344 1345 return true; 1346 } 1347 1348 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1349 * When we update through the ring, if the next incoming buffer has 1350 * not been given to the system, we just set the empty indicator, 1351 * effectively tossing the packet. 1352 */ 1353 static int 1354 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1355 { 1356 struct fec_enet_private *fep = netdev_priv(ndev); 1357 struct fec_enet_priv_rx_q *rxq; 1358 struct bufdesc *bdp; 1359 unsigned short status; 1360 struct sk_buff *skb_new = NULL; 1361 struct sk_buff *skb; 1362 ushort pkt_len; 1363 __u8 *data; 1364 int pkt_received = 0; 1365 struct bufdesc_ex *ebdp = NULL; 1366 bool vlan_packet_rcvd = false; 1367 u16 vlan_tag; 1368 int index = 0; 1369 bool is_copybreak; 1370 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1371 1372 #ifdef CONFIG_M532x 1373 flush_cache_all(); 1374 #endif 1375 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1376 rxq = fep->rx_queue[queue_id]; 1377 1378 /* First, grab all of the stats for the incoming packet. 1379 * These get messed up if we get called due to a busy condition. 1380 */ 1381 bdp = rxq->bd.cur; 1382 1383 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1384 1385 if (pkt_received >= budget) 1386 break; 1387 pkt_received++; 1388 1389 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); 1390 1391 /* Check for errors. */ 1392 status ^= BD_ENET_RX_LAST; 1393 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1394 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1395 BD_ENET_RX_CL)) { 1396 ndev->stats.rx_errors++; 1397 if (status & BD_ENET_RX_OV) { 1398 /* FIFO overrun */ 1399 ndev->stats.rx_fifo_errors++; 1400 goto rx_processing_done; 1401 } 1402 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1403 | BD_ENET_RX_LAST)) { 1404 /* Frame too long or too short. */ 1405 ndev->stats.rx_length_errors++; 1406 if (status & BD_ENET_RX_LAST) 1407 netdev_err(ndev, "rcv is not +last\n"); 1408 } 1409 if (status & BD_ENET_RX_CR) /* CRC Error */ 1410 ndev->stats.rx_crc_errors++; 1411 /* Report late collisions as a frame error. */ 1412 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1413 ndev->stats.rx_frame_errors++; 1414 goto rx_processing_done; 1415 } 1416 1417 /* Process the incoming frame. */ 1418 ndev->stats.rx_packets++; 1419 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1420 ndev->stats.rx_bytes += pkt_len; 1421 1422 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1423 skb = rxq->rx_skbuff[index]; 1424 1425 /* The packet length includes FCS, but we don't want to 1426 * include that when passing upstream as it messes up 1427 * bridging applications. 1428 */ 1429 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1430 need_swap); 1431 if (!is_copybreak) { 1432 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1433 if (unlikely(!skb_new)) { 1434 ndev->stats.rx_dropped++; 1435 goto rx_processing_done; 1436 } 1437 dma_unmap_single(&fep->pdev->dev, 1438 fec32_to_cpu(bdp->cbd_bufaddr), 1439 FEC_ENET_RX_FRSIZE - fep->rx_align, 1440 DMA_FROM_DEVICE); 1441 } 1442 1443 prefetch(skb->data - NET_IP_ALIGN); 1444 skb_put(skb, pkt_len - 4); 1445 data = skb->data; 1446 1447 if (!is_copybreak && need_swap) 1448 swap_buffer(data, pkt_len); 1449 1450 #if !defined(CONFIG_M5272) 1451 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1452 data = skb_pull_inline(skb, 2); 1453 #endif 1454 1455 /* Extract the enhanced buffer descriptor */ 1456 ebdp = NULL; 1457 if (fep->bufdesc_ex) 1458 ebdp = (struct bufdesc_ex *)bdp; 1459 1460 /* If this is a VLAN packet remove the VLAN Tag */ 1461 vlan_packet_rcvd = false; 1462 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1463 fep->bufdesc_ex && 1464 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1465 /* Push and remove the vlan tag */ 1466 struct vlan_hdr *vlan_header = 1467 (struct vlan_hdr *) (data + ETH_HLEN); 1468 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1469 1470 vlan_packet_rcvd = true; 1471 1472 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1473 skb_pull(skb, VLAN_HLEN); 1474 } 1475 1476 skb->protocol = eth_type_trans(skb, ndev); 1477 1478 /* Get receive timestamp from the skb */ 1479 if (fep->hwts_rx_en && fep->bufdesc_ex) 1480 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1481 skb_hwtstamps(skb)); 1482 1483 if (fep->bufdesc_ex && 1484 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1485 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1486 /* don't check it */ 1487 skb->ip_summed = CHECKSUM_UNNECESSARY; 1488 } else { 1489 skb_checksum_none_assert(skb); 1490 } 1491 } 1492 1493 /* Handle received VLAN packets */ 1494 if (vlan_packet_rcvd) 1495 __vlan_hwaccel_put_tag(skb, 1496 htons(ETH_P_8021Q), 1497 vlan_tag); 1498 1499 napi_gro_receive(&fep->napi, skb); 1500 1501 if (is_copybreak) { 1502 dma_sync_single_for_device(&fep->pdev->dev, 1503 fec32_to_cpu(bdp->cbd_bufaddr), 1504 FEC_ENET_RX_FRSIZE - fep->rx_align, 1505 DMA_FROM_DEVICE); 1506 } else { 1507 rxq->rx_skbuff[index] = skb_new; 1508 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1509 } 1510 1511 rx_processing_done: 1512 /* Clear the status flags for this buffer */ 1513 status &= ~BD_ENET_RX_STATS; 1514 1515 /* Mark the buffer empty */ 1516 status |= BD_ENET_RX_EMPTY; 1517 1518 if (fep->bufdesc_ex) { 1519 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1520 1521 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1522 ebdp->cbd_prot = 0; 1523 ebdp->cbd_bdu = 0; 1524 } 1525 /* Make sure the updates to rest of the descriptor are 1526 * performed before transferring ownership. 1527 */ 1528 wmb(); 1529 bdp->cbd_sc = cpu_to_fec16(status); 1530 1531 /* Update BD pointer to next entry */ 1532 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1533 1534 /* Doing this here will keep the FEC running while we process 1535 * incoming frames. On a heavily loaded network, we should be 1536 * able to keep up at the expense of system resources. 1537 */ 1538 writel(0, rxq->bd.reg_desc_active); 1539 } 1540 rxq->bd.cur = bdp; 1541 return pkt_received; 1542 } 1543 1544 static int 1545 fec_enet_rx(struct net_device *ndev, int budget) 1546 { 1547 int pkt_received = 0; 1548 u16 queue_id; 1549 struct fec_enet_private *fep = netdev_priv(ndev); 1550 1551 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) { 1552 int ret; 1553 1554 ret = fec_enet_rx_queue(ndev, 1555 budget - pkt_received, queue_id); 1556 1557 if (ret < budget - pkt_received) 1558 clear_bit(queue_id, &fep->work_rx); 1559 1560 pkt_received += ret; 1561 } 1562 return pkt_received; 1563 } 1564 1565 static bool 1566 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events) 1567 { 1568 if (int_events == 0) 1569 return false; 1570 1571 if (int_events & FEC_ENET_RXF_0) 1572 fep->work_rx |= (1 << 2); 1573 if (int_events & FEC_ENET_RXF_1) 1574 fep->work_rx |= (1 << 0); 1575 if (int_events & FEC_ENET_RXF_2) 1576 fep->work_rx |= (1 << 1); 1577 1578 if (int_events & FEC_ENET_TXF_0) 1579 fep->work_tx |= (1 << 2); 1580 if (int_events & FEC_ENET_TXF_1) 1581 fep->work_tx |= (1 << 0); 1582 if (int_events & FEC_ENET_TXF_2) 1583 fep->work_tx |= (1 << 1); 1584 1585 return true; 1586 } 1587 1588 static irqreturn_t 1589 fec_enet_interrupt(int irq, void *dev_id) 1590 { 1591 struct net_device *ndev = dev_id; 1592 struct fec_enet_private *fep = netdev_priv(ndev); 1593 uint int_events; 1594 irqreturn_t ret = IRQ_NONE; 1595 1596 int_events = readl(fep->hwp + FEC_IEVENT); 1597 writel(int_events, fep->hwp + FEC_IEVENT); 1598 fec_enet_collect_events(fep, int_events); 1599 1600 if ((fep->work_tx || fep->work_rx) && fep->link) { 1601 ret = IRQ_HANDLED; 1602 1603 if (napi_schedule_prep(&fep->napi)) { 1604 /* Disable the NAPI interrupts */ 1605 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK); 1606 __napi_schedule(&fep->napi); 1607 } 1608 } 1609 1610 if (int_events & FEC_ENET_MII) { 1611 ret = IRQ_HANDLED; 1612 complete(&fep->mdio_done); 1613 } 1614 return ret; 1615 } 1616 1617 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1618 { 1619 struct net_device *ndev = napi->dev; 1620 struct fec_enet_private *fep = netdev_priv(ndev); 1621 int pkts; 1622 1623 pkts = fec_enet_rx(ndev, budget); 1624 1625 fec_enet_tx(ndev); 1626 1627 if (pkts < budget) { 1628 napi_complete_done(napi, pkts); 1629 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1630 } 1631 return pkts; 1632 } 1633 1634 /* ------------------------------------------------------------------------- */ 1635 static void fec_get_mac(struct net_device *ndev) 1636 { 1637 struct fec_enet_private *fep = netdev_priv(ndev); 1638 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1639 unsigned char *iap, tmpaddr[ETH_ALEN]; 1640 1641 /* 1642 * try to get mac address in following order: 1643 * 1644 * 1) module parameter via kernel command line in form 1645 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1646 */ 1647 iap = macaddr; 1648 1649 /* 1650 * 2) from device tree data 1651 */ 1652 if (!is_valid_ether_addr(iap)) { 1653 struct device_node *np = fep->pdev->dev.of_node; 1654 if (np) { 1655 const char *mac = of_get_mac_address(np); 1656 if (mac) 1657 iap = (unsigned char *) mac; 1658 } 1659 } 1660 1661 /* 1662 * 3) from flash or fuse (via platform data) 1663 */ 1664 if (!is_valid_ether_addr(iap)) { 1665 #ifdef CONFIG_M5272 1666 if (FEC_FLASHMAC) 1667 iap = (unsigned char *)FEC_FLASHMAC; 1668 #else 1669 if (pdata) 1670 iap = (unsigned char *)&pdata->mac; 1671 #endif 1672 } 1673 1674 /* 1675 * 4) FEC mac registers set by bootloader 1676 */ 1677 if (!is_valid_ether_addr(iap)) { 1678 *((__be32 *) &tmpaddr[0]) = 1679 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1680 *((__be16 *) &tmpaddr[4]) = 1681 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1682 iap = &tmpaddr[0]; 1683 } 1684 1685 /* 1686 * 5) random mac address 1687 */ 1688 if (!is_valid_ether_addr(iap)) { 1689 /* Report it and use a random ethernet address instead */ 1690 netdev_err(ndev, "Invalid MAC address: %pM\n", iap); 1691 eth_hw_addr_random(ndev); 1692 netdev_info(ndev, "Using random MAC address: %pM\n", 1693 ndev->dev_addr); 1694 return; 1695 } 1696 1697 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1698 1699 /* Adjust MAC if using macaddr */ 1700 if (iap == macaddr) 1701 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1702 } 1703 1704 /* ------------------------------------------------------------------------- */ 1705 1706 /* 1707 * Phy section 1708 */ 1709 static void fec_enet_adjust_link(struct net_device *ndev) 1710 { 1711 struct fec_enet_private *fep = netdev_priv(ndev); 1712 struct phy_device *phy_dev = ndev->phydev; 1713 int status_change = 0; 1714 1715 /* Prevent a state halted on mii error */ 1716 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 1717 phy_dev->state = PHY_RESUMING; 1718 return; 1719 } 1720 1721 /* 1722 * If the netdev is down, or is going down, we're not interested 1723 * in link state events, so just mark our idea of the link as down 1724 * and ignore the event. 1725 */ 1726 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1727 fep->link = 0; 1728 } else if (phy_dev->link) { 1729 if (!fep->link) { 1730 fep->link = phy_dev->link; 1731 status_change = 1; 1732 } 1733 1734 if (fep->full_duplex != phy_dev->duplex) { 1735 fep->full_duplex = phy_dev->duplex; 1736 status_change = 1; 1737 } 1738 1739 if (phy_dev->speed != fep->speed) { 1740 fep->speed = phy_dev->speed; 1741 status_change = 1; 1742 } 1743 1744 /* if any of the above changed restart the FEC */ 1745 if (status_change) { 1746 napi_disable(&fep->napi); 1747 netif_tx_lock_bh(ndev); 1748 fec_restart(ndev); 1749 netif_wake_queue(ndev); 1750 netif_tx_unlock_bh(ndev); 1751 napi_enable(&fep->napi); 1752 } 1753 } else { 1754 if (fep->link) { 1755 napi_disable(&fep->napi); 1756 netif_tx_lock_bh(ndev); 1757 fec_stop(ndev); 1758 netif_tx_unlock_bh(ndev); 1759 napi_enable(&fep->napi); 1760 fep->link = phy_dev->link; 1761 status_change = 1; 1762 } 1763 } 1764 1765 if (status_change) 1766 phy_print_status(phy_dev); 1767 } 1768 1769 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1770 { 1771 struct fec_enet_private *fep = bus->priv; 1772 struct device *dev = &fep->pdev->dev; 1773 unsigned long time_left; 1774 int ret = 0; 1775 1776 ret = pm_runtime_get_sync(dev); 1777 if (ret < 0) 1778 return ret; 1779 1780 fep->mii_timeout = 0; 1781 reinit_completion(&fep->mdio_done); 1782 1783 /* start a read op */ 1784 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 1785 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1786 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1787 1788 /* wait for end of transfer */ 1789 time_left = wait_for_completion_timeout(&fep->mdio_done, 1790 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1791 if (time_left == 0) { 1792 fep->mii_timeout = 1; 1793 netdev_err(fep->netdev, "MDIO read timeout\n"); 1794 ret = -ETIMEDOUT; 1795 goto out; 1796 } 1797 1798 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1799 1800 out: 1801 pm_runtime_mark_last_busy(dev); 1802 pm_runtime_put_autosuspend(dev); 1803 1804 return ret; 1805 } 1806 1807 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1808 u16 value) 1809 { 1810 struct fec_enet_private *fep = bus->priv; 1811 struct device *dev = &fep->pdev->dev; 1812 unsigned long time_left; 1813 int ret; 1814 1815 ret = pm_runtime_get_sync(dev); 1816 if (ret < 0) 1817 return ret; 1818 else 1819 ret = 0; 1820 1821 fep->mii_timeout = 0; 1822 reinit_completion(&fep->mdio_done); 1823 1824 /* start a write op */ 1825 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 1826 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1827 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1828 fep->hwp + FEC_MII_DATA); 1829 1830 /* wait for end of transfer */ 1831 time_left = wait_for_completion_timeout(&fep->mdio_done, 1832 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1833 if (time_left == 0) { 1834 fep->mii_timeout = 1; 1835 netdev_err(fep->netdev, "MDIO write timeout\n"); 1836 ret = -ETIMEDOUT; 1837 } 1838 1839 pm_runtime_mark_last_busy(dev); 1840 pm_runtime_put_autosuspend(dev); 1841 1842 return ret; 1843 } 1844 1845 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1846 { 1847 struct fec_enet_private *fep = netdev_priv(ndev); 1848 int ret; 1849 1850 if (enable) { 1851 ret = clk_prepare_enable(fep->clk_ahb); 1852 if (ret) 1853 return ret; 1854 1855 ret = clk_prepare_enable(fep->clk_enet_out); 1856 if (ret) 1857 goto failed_clk_enet_out; 1858 1859 if (fep->clk_ptp) { 1860 mutex_lock(&fep->ptp_clk_mutex); 1861 ret = clk_prepare_enable(fep->clk_ptp); 1862 if (ret) { 1863 mutex_unlock(&fep->ptp_clk_mutex); 1864 goto failed_clk_ptp; 1865 } else { 1866 fep->ptp_clk_on = true; 1867 } 1868 mutex_unlock(&fep->ptp_clk_mutex); 1869 } 1870 1871 ret = clk_prepare_enable(fep->clk_ref); 1872 if (ret) 1873 goto failed_clk_ref; 1874 1875 phy_reset_after_clk_enable(ndev->phydev); 1876 } else { 1877 clk_disable_unprepare(fep->clk_ahb); 1878 clk_disable_unprepare(fep->clk_enet_out); 1879 if (fep->clk_ptp) { 1880 mutex_lock(&fep->ptp_clk_mutex); 1881 clk_disable_unprepare(fep->clk_ptp); 1882 fep->ptp_clk_on = false; 1883 mutex_unlock(&fep->ptp_clk_mutex); 1884 } 1885 clk_disable_unprepare(fep->clk_ref); 1886 } 1887 1888 return 0; 1889 1890 failed_clk_ref: 1891 if (fep->clk_ref) 1892 clk_disable_unprepare(fep->clk_ref); 1893 failed_clk_ptp: 1894 if (fep->clk_enet_out) 1895 clk_disable_unprepare(fep->clk_enet_out); 1896 failed_clk_enet_out: 1897 clk_disable_unprepare(fep->clk_ahb); 1898 1899 return ret; 1900 } 1901 1902 static int fec_enet_mii_probe(struct net_device *ndev) 1903 { 1904 struct fec_enet_private *fep = netdev_priv(ndev); 1905 struct phy_device *phy_dev = NULL; 1906 char mdio_bus_id[MII_BUS_ID_SIZE]; 1907 char phy_name[MII_BUS_ID_SIZE + 3]; 1908 int phy_id; 1909 int dev_id = fep->dev_id; 1910 1911 if (fep->phy_node) { 1912 phy_dev = of_phy_connect(ndev, fep->phy_node, 1913 &fec_enet_adjust_link, 0, 1914 fep->phy_interface); 1915 if (!phy_dev) { 1916 netdev_err(ndev, "Unable to connect to phy\n"); 1917 return -ENODEV; 1918 } 1919 } else { 1920 /* check for attached phy */ 1921 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1922 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 1923 continue; 1924 if (dev_id--) 1925 continue; 1926 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1927 break; 1928 } 1929 1930 if (phy_id >= PHY_MAX_ADDR) { 1931 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1932 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 1933 phy_id = 0; 1934 } 1935 1936 snprintf(phy_name, sizeof(phy_name), 1937 PHY_ID_FMT, mdio_bus_id, phy_id); 1938 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 1939 fep->phy_interface); 1940 } 1941 1942 if (IS_ERR(phy_dev)) { 1943 netdev_err(ndev, "could not attach to PHY\n"); 1944 return PTR_ERR(phy_dev); 1945 } 1946 1947 /* mask with MAC supported features */ 1948 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 1949 phy_set_max_speed(phy_dev, 1000); 1950 phy_remove_link_mode(phy_dev, 1951 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1952 #if !defined(CONFIG_M5272) 1953 phy_support_sym_pause(phy_dev); 1954 #endif 1955 } 1956 else 1957 phy_set_max_speed(phy_dev, 100); 1958 1959 fep->link = 0; 1960 fep->full_duplex = 0; 1961 1962 phy_attached_info(phy_dev); 1963 1964 return 0; 1965 } 1966 1967 static int fec_enet_mii_init(struct platform_device *pdev) 1968 { 1969 static struct mii_bus *fec0_mii_bus; 1970 struct net_device *ndev = platform_get_drvdata(pdev); 1971 struct fec_enet_private *fep = netdev_priv(ndev); 1972 struct device_node *node; 1973 int err = -ENXIO; 1974 u32 mii_speed, holdtime; 1975 1976 /* 1977 * The i.MX28 dual fec interfaces are not equal. 1978 * Here are the differences: 1979 * 1980 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1981 * - fec0 acts as the 1588 time master while fec1 is slave 1982 * - external phys can only be configured by fec0 1983 * 1984 * That is to say fec1 can not work independently. It only works 1985 * when fec0 is working. The reason behind this design is that the 1986 * second interface is added primarily for Switch mode. 1987 * 1988 * Because of the last point above, both phys are attached on fec0 1989 * mdio interface in board design, and need to be configured by 1990 * fec0 mii_bus. 1991 */ 1992 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 1993 /* fec1 uses fec0 mii_bus */ 1994 if (mii_cnt && fec0_mii_bus) { 1995 fep->mii_bus = fec0_mii_bus; 1996 mii_cnt++; 1997 return 0; 1998 } 1999 return -ENOENT; 2000 } 2001 2002 fep->mii_timeout = 0; 2003 2004 /* 2005 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 2006 * 2007 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2008 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2009 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2010 * document. 2011 */ 2012 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000); 2013 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2014 mii_speed--; 2015 if (mii_speed > 63) { 2016 dev_err(&pdev->dev, 2017 "fec clock (%lu) too fast to get right mii speed\n", 2018 clk_get_rate(fep->clk_ipg)); 2019 err = -EINVAL; 2020 goto err_out; 2021 } 2022 2023 /* 2024 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2025 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2026 * versions are RAZ there, so just ignore the difference and write the 2027 * register always. 2028 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2029 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2030 * output. 2031 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2032 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2033 * holdtime cannot result in a value greater than 3. 2034 */ 2035 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2036 2037 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2038 2039 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2040 2041 fep->mii_bus = mdiobus_alloc(); 2042 if (fep->mii_bus == NULL) { 2043 err = -ENOMEM; 2044 goto err_out; 2045 } 2046 2047 fep->mii_bus->name = "fec_enet_mii_bus"; 2048 fep->mii_bus->read = fec_enet_mdio_read; 2049 fep->mii_bus->write = fec_enet_mdio_write; 2050 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2051 pdev->name, fep->dev_id + 1); 2052 fep->mii_bus->priv = fep; 2053 fep->mii_bus->parent = &pdev->dev; 2054 2055 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2056 err = of_mdiobus_register(fep->mii_bus, node); 2057 if (node) 2058 of_node_put(node); 2059 if (err) 2060 goto err_out_free_mdiobus; 2061 2062 mii_cnt++; 2063 2064 /* save fec0 mii_bus */ 2065 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2066 fec0_mii_bus = fep->mii_bus; 2067 2068 return 0; 2069 2070 err_out_free_mdiobus: 2071 mdiobus_free(fep->mii_bus); 2072 err_out: 2073 return err; 2074 } 2075 2076 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2077 { 2078 if (--mii_cnt == 0) { 2079 mdiobus_unregister(fep->mii_bus); 2080 mdiobus_free(fep->mii_bus); 2081 } 2082 } 2083 2084 static void fec_enet_get_drvinfo(struct net_device *ndev, 2085 struct ethtool_drvinfo *info) 2086 { 2087 struct fec_enet_private *fep = netdev_priv(ndev); 2088 2089 strlcpy(info->driver, fep->pdev->dev.driver->name, 2090 sizeof(info->driver)); 2091 strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); 2092 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2093 } 2094 2095 static int fec_enet_get_regs_len(struct net_device *ndev) 2096 { 2097 struct fec_enet_private *fep = netdev_priv(ndev); 2098 struct resource *r; 2099 int s = 0; 2100 2101 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2102 if (r) 2103 s = resource_size(r); 2104 2105 return s; 2106 } 2107 2108 /* List of registers that can be safety be read to dump them with ethtool */ 2109 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2110 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2111 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2112 static u32 fec_enet_register_offset[] = { 2113 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2114 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2115 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2116 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2117 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2118 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2119 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2120 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2121 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2122 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2123 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2124 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2125 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2126 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2127 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2128 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2129 RMON_T_P_GTE2048, RMON_T_OCTETS, 2130 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2131 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2132 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2133 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2134 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2135 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2136 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2137 RMON_R_P_GTE2048, RMON_R_OCTETS, 2138 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2139 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2140 }; 2141 #else 2142 static u32 fec_enet_register_offset[] = { 2143 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2144 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2145 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2146 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2147 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2148 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2149 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2150 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2151 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2152 }; 2153 #endif 2154 2155 static void fec_enet_get_regs(struct net_device *ndev, 2156 struct ethtool_regs *regs, void *regbuf) 2157 { 2158 struct fec_enet_private *fep = netdev_priv(ndev); 2159 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2160 u32 *buf = (u32 *)regbuf; 2161 u32 i, off; 2162 2163 memset(buf, 0, regs->len); 2164 2165 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2166 off = fec_enet_register_offset[i] / 4; 2167 buf[off] = readl(&theregs[off]); 2168 } 2169 } 2170 2171 static int fec_enet_get_ts_info(struct net_device *ndev, 2172 struct ethtool_ts_info *info) 2173 { 2174 struct fec_enet_private *fep = netdev_priv(ndev); 2175 2176 if (fep->bufdesc_ex) { 2177 2178 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2179 SOF_TIMESTAMPING_RX_SOFTWARE | 2180 SOF_TIMESTAMPING_SOFTWARE | 2181 SOF_TIMESTAMPING_TX_HARDWARE | 2182 SOF_TIMESTAMPING_RX_HARDWARE | 2183 SOF_TIMESTAMPING_RAW_HARDWARE; 2184 if (fep->ptp_clock) 2185 info->phc_index = ptp_clock_index(fep->ptp_clock); 2186 else 2187 info->phc_index = -1; 2188 2189 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2190 (1 << HWTSTAMP_TX_ON); 2191 2192 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2193 (1 << HWTSTAMP_FILTER_ALL); 2194 return 0; 2195 } else { 2196 return ethtool_op_get_ts_info(ndev, info); 2197 } 2198 } 2199 2200 #if !defined(CONFIG_M5272) 2201 2202 static void fec_enet_get_pauseparam(struct net_device *ndev, 2203 struct ethtool_pauseparam *pause) 2204 { 2205 struct fec_enet_private *fep = netdev_priv(ndev); 2206 2207 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2208 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2209 pause->rx_pause = pause->tx_pause; 2210 } 2211 2212 static int fec_enet_set_pauseparam(struct net_device *ndev, 2213 struct ethtool_pauseparam *pause) 2214 { 2215 struct fec_enet_private *fep = netdev_priv(ndev); 2216 2217 if (!ndev->phydev) 2218 return -ENODEV; 2219 2220 if (pause->tx_pause != pause->rx_pause) { 2221 netdev_info(ndev, 2222 "hardware only support enable/disable both tx and rx"); 2223 return -EINVAL; 2224 } 2225 2226 fep->pause_flag = 0; 2227 2228 /* tx pause must be same as rx pause */ 2229 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2230 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2231 2232 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2233 pause->autoneg); 2234 2235 if (pause->autoneg) { 2236 if (netif_running(ndev)) 2237 fec_stop(ndev); 2238 phy_start_aneg(ndev->phydev); 2239 } 2240 if (netif_running(ndev)) { 2241 napi_disable(&fep->napi); 2242 netif_tx_lock_bh(ndev); 2243 fec_restart(ndev); 2244 netif_wake_queue(ndev); 2245 netif_tx_unlock_bh(ndev); 2246 napi_enable(&fep->napi); 2247 } 2248 2249 return 0; 2250 } 2251 2252 static const struct fec_stat { 2253 char name[ETH_GSTRING_LEN]; 2254 u16 offset; 2255 } fec_stats[] = { 2256 /* RMON TX */ 2257 { "tx_dropped", RMON_T_DROP }, 2258 { "tx_packets", RMON_T_PACKETS }, 2259 { "tx_broadcast", RMON_T_BC_PKT }, 2260 { "tx_multicast", RMON_T_MC_PKT }, 2261 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2262 { "tx_undersize", RMON_T_UNDERSIZE }, 2263 { "tx_oversize", RMON_T_OVERSIZE }, 2264 { "tx_fragment", RMON_T_FRAG }, 2265 { "tx_jabber", RMON_T_JAB }, 2266 { "tx_collision", RMON_T_COL }, 2267 { "tx_64byte", RMON_T_P64 }, 2268 { "tx_65to127byte", RMON_T_P65TO127 }, 2269 { "tx_128to255byte", RMON_T_P128TO255 }, 2270 { "tx_256to511byte", RMON_T_P256TO511 }, 2271 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2272 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2273 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2274 { "tx_octets", RMON_T_OCTETS }, 2275 2276 /* IEEE TX */ 2277 { "IEEE_tx_drop", IEEE_T_DROP }, 2278 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2279 { "IEEE_tx_1col", IEEE_T_1COL }, 2280 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2281 { "IEEE_tx_def", IEEE_T_DEF }, 2282 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2283 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2284 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2285 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2286 { "IEEE_tx_sqe", IEEE_T_SQE }, 2287 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2288 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2289 2290 /* RMON RX */ 2291 { "rx_packets", RMON_R_PACKETS }, 2292 { "rx_broadcast", RMON_R_BC_PKT }, 2293 { "rx_multicast", RMON_R_MC_PKT }, 2294 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2295 { "rx_undersize", RMON_R_UNDERSIZE }, 2296 { "rx_oversize", RMON_R_OVERSIZE }, 2297 { "rx_fragment", RMON_R_FRAG }, 2298 { "rx_jabber", RMON_R_JAB }, 2299 { "rx_64byte", RMON_R_P64 }, 2300 { "rx_65to127byte", RMON_R_P65TO127 }, 2301 { "rx_128to255byte", RMON_R_P128TO255 }, 2302 { "rx_256to511byte", RMON_R_P256TO511 }, 2303 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2304 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2305 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2306 { "rx_octets", RMON_R_OCTETS }, 2307 2308 /* IEEE RX */ 2309 { "IEEE_rx_drop", IEEE_R_DROP }, 2310 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2311 { "IEEE_rx_crc", IEEE_R_CRC }, 2312 { "IEEE_rx_align", IEEE_R_ALIGN }, 2313 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2314 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2315 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2316 }; 2317 2318 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2319 2320 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2321 { 2322 struct fec_enet_private *fep = netdev_priv(dev); 2323 int i; 2324 2325 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2326 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2327 } 2328 2329 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2330 struct ethtool_stats *stats, u64 *data) 2331 { 2332 struct fec_enet_private *fep = netdev_priv(dev); 2333 2334 if (netif_running(dev)) 2335 fec_enet_update_ethtool_stats(dev); 2336 2337 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2338 } 2339 2340 static void fec_enet_get_strings(struct net_device *netdev, 2341 u32 stringset, u8 *data) 2342 { 2343 int i; 2344 switch (stringset) { 2345 case ETH_SS_STATS: 2346 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2347 memcpy(data + i * ETH_GSTRING_LEN, 2348 fec_stats[i].name, ETH_GSTRING_LEN); 2349 break; 2350 } 2351 } 2352 2353 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2354 { 2355 switch (sset) { 2356 case ETH_SS_STATS: 2357 return ARRAY_SIZE(fec_stats); 2358 default: 2359 return -EOPNOTSUPP; 2360 } 2361 } 2362 2363 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2364 { 2365 struct fec_enet_private *fep = netdev_priv(dev); 2366 int i; 2367 2368 /* Disable MIB statistics counters */ 2369 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2370 2371 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2372 writel(0, fep->hwp + fec_stats[i].offset); 2373 2374 /* Don't disable MIB statistics counters */ 2375 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2376 } 2377 2378 #else /* !defined(CONFIG_M5272) */ 2379 #define FEC_STATS_SIZE 0 2380 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2381 { 2382 } 2383 2384 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2385 { 2386 } 2387 #endif /* !defined(CONFIG_M5272) */ 2388 2389 /* ITR clock source is enet system clock (clk_ahb). 2390 * TCTT unit is cycle_ns * 64 cycle 2391 * So, the ICTT value = X us / (cycle_ns * 64) 2392 */ 2393 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2394 { 2395 struct fec_enet_private *fep = netdev_priv(ndev); 2396 2397 return us * (fep->itr_clk_rate / 64000) / 1000; 2398 } 2399 2400 /* Set threshold for interrupt coalescing */ 2401 static void fec_enet_itr_coal_set(struct net_device *ndev) 2402 { 2403 struct fec_enet_private *fep = netdev_priv(ndev); 2404 int rx_itr, tx_itr; 2405 2406 /* Must be greater than zero to avoid unpredictable behavior */ 2407 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2408 !fep->tx_time_itr || !fep->tx_pkts_itr) 2409 return; 2410 2411 /* Select enet system clock as Interrupt Coalescing 2412 * timer Clock Source 2413 */ 2414 rx_itr = FEC_ITR_CLK_SEL; 2415 tx_itr = FEC_ITR_CLK_SEL; 2416 2417 /* set ICFT and ICTT */ 2418 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2419 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2420 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2421 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2422 2423 rx_itr |= FEC_ITR_EN; 2424 tx_itr |= FEC_ITR_EN; 2425 2426 writel(tx_itr, fep->hwp + FEC_TXIC0); 2427 writel(rx_itr, fep->hwp + FEC_RXIC0); 2428 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 2429 writel(tx_itr, fep->hwp + FEC_TXIC1); 2430 writel(rx_itr, fep->hwp + FEC_RXIC1); 2431 writel(tx_itr, fep->hwp + FEC_TXIC2); 2432 writel(rx_itr, fep->hwp + FEC_RXIC2); 2433 } 2434 } 2435 2436 static int 2437 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2438 { 2439 struct fec_enet_private *fep = netdev_priv(ndev); 2440 2441 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2442 return -EOPNOTSUPP; 2443 2444 ec->rx_coalesce_usecs = fep->rx_time_itr; 2445 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2446 2447 ec->tx_coalesce_usecs = fep->tx_time_itr; 2448 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2449 2450 return 0; 2451 } 2452 2453 static int 2454 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2455 { 2456 struct fec_enet_private *fep = netdev_priv(ndev); 2457 unsigned int cycle; 2458 2459 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2460 return -EOPNOTSUPP; 2461 2462 if (ec->rx_max_coalesced_frames > 255) { 2463 pr_err("Rx coalesced frames exceed hardware limitation\n"); 2464 return -EINVAL; 2465 } 2466 2467 if (ec->tx_max_coalesced_frames > 255) { 2468 pr_err("Tx coalesced frame exceed hardware limitation\n"); 2469 return -EINVAL; 2470 } 2471 2472 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); 2473 if (cycle > 0xFFFF) { 2474 pr_err("Rx coalesced usec exceed hardware limitation\n"); 2475 return -EINVAL; 2476 } 2477 2478 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); 2479 if (cycle > 0xFFFF) { 2480 pr_err("Rx coalesced usec exceed hardware limitation\n"); 2481 return -EINVAL; 2482 } 2483 2484 fep->rx_time_itr = ec->rx_coalesce_usecs; 2485 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2486 2487 fep->tx_time_itr = ec->tx_coalesce_usecs; 2488 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2489 2490 fec_enet_itr_coal_set(ndev); 2491 2492 return 0; 2493 } 2494 2495 static void fec_enet_itr_coal_init(struct net_device *ndev) 2496 { 2497 struct ethtool_coalesce ec; 2498 2499 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2500 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2501 2502 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2503 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2504 2505 fec_enet_set_coalesce(ndev, &ec); 2506 } 2507 2508 static int fec_enet_get_tunable(struct net_device *netdev, 2509 const struct ethtool_tunable *tuna, 2510 void *data) 2511 { 2512 struct fec_enet_private *fep = netdev_priv(netdev); 2513 int ret = 0; 2514 2515 switch (tuna->id) { 2516 case ETHTOOL_RX_COPYBREAK: 2517 *(u32 *)data = fep->rx_copybreak; 2518 break; 2519 default: 2520 ret = -EINVAL; 2521 break; 2522 } 2523 2524 return ret; 2525 } 2526 2527 static int fec_enet_set_tunable(struct net_device *netdev, 2528 const struct ethtool_tunable *tuna, 2529 const void *data) 2530 { 2531 struct fec_enet_private *fep = netdev_priv(netdev); 2532 int ret = 0; 2533 2534 switch (tuna->id) { 2535 case ETHTOOL_RX_COPYBREAK: 2536 fep->rx_copybreak = *(u32 *)data; 2537 break; 2538 default: 2539 ret = -EINVAL; 2540 break; 2541 } 2542 2543 return ret; 2544 } 2545 2546 static void 2547 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2548 { 2549 struct fec_enet_private *fep = netdev_priv(ndev); 2550 2551 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2552 wol->supported = WAKE_MAGIC; 2553 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2554 } else { 2555 wol->supported = wol->wolopts = 0; 2556 } 2557 } 2558 2559 static int 2560 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2561 { 2562 struct fec_enet_private *fep = netdev_priv(ndev); 2563 2564 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2565 return -EINVAL; 2566 2567 if (wol->wolopts & ~WAKE_MAGIC) 2568 return -EINVAL; 2569 2570 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2571 if (device_may_wakeup(&ndev->dev)) { 2572 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2573 if (fep->irq[0] > 0) 2574 enable_irq_wake(fep->irq[0]); 2575 } else { 2576 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2577 if (fep->irq[0] > 0) 2578 disable_irq_wake(fep->irq[0]); 2579 } 2580 2581 return 0; 2582 } 2583 2584 static const struct ethtool_ops fec_enet_ethtool_ops = { 2585 .get_drvinfo = fec_enet_get_drvinfo, 2586 .get_regs_len = fec_enet_get_regs_len, 2587 .get_regs = fec_enet_get_regs, 2588 .nway_reset = phy_ethtool_nway_reset, 2589 .get_link = ethtool_op_get_link, 2590 .get_coalesce = fec_enet_get_coalesce, 2591 .set_coalesce = fec_enet_set_coalesce, 2592 #ifndef CONFIG_M5272 2593 .get_pauseparam = fec_enet_get_pauseparam, 2594 .set_pauseparam = fec_enet_set_pauseparam, 2595 .get_strings = fec_enet_get_strings, 2596 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2597 .get_sset_count = fec_enet_get_sset_count, 2598 #endif 2599 .get_ts_info = fec_enet_get_ts_info, 2600 .get_tunable = fec_enet_get_tunable, 2601 .set_tunable = fec_enet_set_tunable, 2602 .get_wol = fec_enet_get_wol, 2603 .set_wol = fec_enet_set_wol, 2604 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2605 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2606 }; 2607 2608 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2609 { 2610 struct fec_enet_private *fep = netdev_priv(ndev); 2611 struct phy_device *phydev = ndev->phydev; 2612 2613 if (!netif_running(ndev)) 2614 return -EINVAL; 2615 2616 if (!phydev) 2617 return -ENODEV; 2618 2619 if (fep->bufdesc_ex) { 2620 if (cmd == SIOCSHWTSTAMP) 2621 return fec_ptp_set(ndev, rq); 2622 if (cmd == SIOCGHWTSTAMP) 2623 return fec_ptp_get(ndev, rq); 2624 } 2625 2626 return phy_mii_ioctl(phydev, rq, cmd); 2627 } 2628 2629 static void fec_enet_free_buffers(struct net_device *ndev) 2630 { 2631 struct fec_enet_private *fep = netdev_priv(ndev); 2632 unsigned int i; 2633 struct sk_buff *skb; 2634 struct bufdesc *bdp; 2635 struct fec_enet_priv_tx_q *txq; 2636 struct fec_enet_priv_rx_q *rxq; 2637 unsigned int q; 2638 2639 for (q = 0; q < fep->num_rx_queues; q++) { 2640 rxq = fep->rx_queue[q]; 2641 bdp = rxq->bd.base; 2642 for (i = 0; i < rxq->bd.ring_size; i++) { 2643 skb = rxq->rx_skbuff[i]; 2644 rxq->rx_skbuff[i] = NULL; 2645 if (skb) { 2646 dma_unmap_single(&fep->pdev->dev, 2647 fec32_to_cpu(bdp->cbd_bufaddr), 2648 FEC_ENET_RX_FRSIZE - fep->rx_align, 2649 DMA_FROM_DEVICE); 2650 dev_kfree_skb(skb); 2651 } 2652 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2653 } 2654 } 2655 2656 for (q = 0; q < fep->num_tx_queues; q++) { 2657 txq = fep->tx_queue[q]; 2658 bdp = txq->bd.base; 2659 for (i = 0; i < txq->bd.ring_size; i++) { 2660 kfree(txq->tx_bounce[i]); 2661 txq->tx_bounce[i] = NULL; 2662 skb = txq->tx_skbuff[i]; 2663 txq->tx_skbuff[i] = NULL; 2664 dev_kfree_skb(skb); 2665 } 2666 } 2667 } 2668 2669 static void fec_enet_free_queue(struct net_device *ndev) 2670 { 2671 struct fec_enet_private *fep = netdev_priv(ndev); 2672 int i; 2673 struct fec_enet_priv_tx_q *txq; 2674 2675 for (i = 0; i < fep->num_tx_queues; i++) 2676 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2677 txq = fep->tx_queue[i]; 2678 dma_free_coherent(&fep->pdev->dev, 2679 txq->bd.ring_size * TSO_HEADER_SIZE, 2680 txq->tso_hdrs, 2681 txq->tso_hdrs_dma); 2682 } 2683 2684 for (i = 0; i < fep->num_rx_queues; i++) 2685 kfree(fep->rx_queue[i]); 2686 for (i = 0; i < fep->num_tx_queues; i++) 2687 kfree(fep->tx_queue[i]); 2688 } 2689 2690 static int fec_enet_alloc_queue(struct net_device *ndev) 2691 { 2692 struct fec_enet_private *fep = netdev_priv(ndev); 2693 int i; 2694 int ret = 0; 2695 struct fec_enet_priv_tx_q *txq; 2696 2697 for (i = 0; i < fep->num_tx_queues; i++) { 2698 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 2699 if (!txq) { 2700 ret = -ENOMEM; 2701 goto alloc_failed; 2702 } 2703 2704 fep->tx_queue[i] = txq; 2705 txq->bd.ring_size = TX_RING_SIZE; 2706 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 2707 2708 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2709 txq->tx_wake_threshold = 2710 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 2711 2712 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 2713 txq->bd.ring_size * TSO_HEADER_SIZE, 2714 &txq->tso_hdrs_dma, 2715 GFP_KERNEL); 2716 if (!txq->tso_hdrs) { 2717 ret = -ENOMEM; 2718 goto alloc_failed; 2719 } 2720 } 2721 2722 for (i = 0; i < fep->num_rx_queues; i++) { 2723 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 2724 GFP_KERNEL); 2725 if (!fep->rx_queue[i]) { 2726 ret = -ENOMEM; 2727 goto alloc_failed; 2728 } 2729 2730 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 2731 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 2732 } 2733 return ret; 2734 2735 alloc_failed: 2736 fec_enet_free_queue(ndev); 2737 return ret; 2738 } 2739 2740 static int 2741 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 2742 { 2743 struct fec_enet_private *fep = netdev_priv(ndev); 2744 unsigned int i; 2745 struct sk_buff *skb; 2746 struct bufdesc *bdp; 2747 struct fec_enet_priv_rx_q *rxq; 2748 2749 rxq = fep->rx_queue[queue]; 2750 bdp = rxq->bd.base; 2751 for (i = 0; i < rxq->bd.ring_size; i++) { 2752 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2753 if (!skb) 2754 goto err_alloc; 2755 2756 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 2757 dev_kfree_skb(skb); 2758 goto err_alloc; 2759 } 2760 2761 rxq->rx_skbuff[i] = skb; 2762 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 2763 2764 if (fep->bufdesc_ex) { 2765 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2766 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 2767 } 2768 2769 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2770 } 2771 2772 /* Set the last buffer to wrap. */ 2773 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 2774 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2775 return 0; 2776 2777 err_alloc: 2778 fec_enet_free_buffers(ndev); 2779 return -ENOMEM; 2780 } 2781 2782 static int 2783 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 2784 { 2785 struct fec_enet_private *fep = netdev_priv(ndev); 2786 unsigned int i; 2787 struct bufdesc *bdp; 2788 struct fec_enet_priv_tx_q *txq; 2789 2790 txq = fep->tx_queue[queue]; 2791 bdp = txq->bd.base; 2792 for (i = 0; i < txq->bd.ring_size; i++) { 2793 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2794 if (!txq->tx_bounce[i]) 2795 goto err_alloc; 2796 2797 bdp->cbd_sc = cpu_to_fec16(0); 2798 bdp->cbd_bufaddr = cpu_to_fec32(0); 2799 2800 if (fep->bufdesc_ex) { 2801 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2802 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 2803 } 2804 2805 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 2806 } 2807 2808 /* Set the last buffer to wrap. */ 2809 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 2810 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2811 2812 return 0; 2813 2814 err_alloc: 2815 fec_enet_free_buffers(ndev); 2816 return -ENOMEM; 2817 } 2818 2819 static int fec_enet_alloc_buffers(struct net_device *ndev) 2820 { 2821 struct fec_enet_private *fep = netdev_priv(ndev); 2822 unsigned int i; 2823 2824 for (i = 0; i < fep->num_rx_queues; i++) 2825 if (fec_enet_alloc_rxq_buffers(ndev, i)) 2826 return -ENOMEM; 2827 2828 for (i = 0; i < fep->num_tx_queues; i++) 2829 if (fec_enet_alloc_txq_buffers(ndev, i)) 2830 return -ENOMEM; 2831 return 0; 2832 } 2833 2834 static int 2835 fec_enet_open(struct net_device *ndev) 2836 { 2837 struct fec_enet_private *fep = netdev_priv(ndev); 2838 int ret; 2839 bool reset_again; 2840 2841 ret = pm_runtime_get_sync(&fep->pdev->dev); 2842 if (ret < 0) 2843 return ret; 2844 2845 pinctrl_pm_select_default_state(&fep->pdev->dev); 2846 ret = fec_enet_clk_enable(ndev, true); 2847 if (ret) 2848 goto clk_enable; 2849 2850 /* During the first fec_enet_open call the PHY isn't probed at this 2851 * point. Therefore the phy_reset_after_clk_enable() call within 2852 * fec_enet_clk_enable() fails. As we need this reset in order to be 2853 * sure the PHY is working correctly we check if we need to reset again 2854 * later when the PHY is probed 2855 */ 2856 if (ndev->phydev && ndev->phydev->drv) 2857 reset_again = false; 2858 else 2859 reset_again = true; 2860 2861 /* I should reset the ring buffers here, but I don't yet know 2862 * a simple way to do that. 2863 */ 2864 2865 ret = fec_enet_alloc_buffers(ndev); 2866 if (ret) 2867 goto err_enet_alloc; 2868 2869 /* Init MAC prior to mii bus probe */ 2870 fec_restart(ndev); 2871 2872 /* Probe and connect to PHY when open the interface */ 2873 ret = fec_enet_mii_probe(ndev); 2874 if (ret) 2875 goto err_enet_mii_probe; 2876 2877 /* Call phy_reset_after_clk_enable() again if it failed during 2878 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 2879 */ 2880 if (reset_again) 2881 phy_reset_after_clk_enable(ndev->phydev); 2882 2883 if (fep->quirks & FEC_QUIRK_ERR006687) 2884 imx6q_cpuidle_fec_irqs_used(); 2885 2886 napi_enable(&fep->napi); 2887 phy_start(ndev->phydev); 2888 netif_tx_start_all_queues(ndev); 2889 2890 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 2891 FEC_WOL_FLAG_ENABLE); 2892 2893 return 0; 2894 2895 err_enet_mii_probe: 2896 fec_enet_free_buffers(ndev); 2897 err_enet_alloc: 2898 fec_enet_clk_enable(ndev, false); 2899 clk_enable: 2900 pm_runtime_mark_last_busy(&fep->pdev->dev); 2901 pm_runtime_put_autosuspend(&fep->pdev->dev); 2902 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2903 return ret; 2904 } 2905 2906 static int 2907 fec_enet_close(struct net_device *ndev) 2908 { 2909 struct fec_enet_private *fep = netdev_priv(ndev); 2910 2911 phy_stop(ndev->phydev); 2912 2913 if (netif_device_present(ndev)) { 2914 napi_disable(&fep->napi); 2915 netif_tx_disable(ndev); 2916 fec_stop(ndev); 2917 } 2918 2919 phy_disconnect(ndev->phydev); 2920 2921 if (fep->quirks & FEC_QUIRK_ERR006687) 2922 imx6q_cpuidle_fec_irqs_unused(); 2923 2924 fec_enet_update_ethtool_stats(ndev); 2925 2926 fec_enet_clk_enable(ndev, false); 2927 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2928 pm_runtime_mark_last_busy(&fep->pdev->dev); 2929 pm_runtime_put_autosuspend(&fep->pdev->dev); 2930 2931 fec_enet_free_buffers(ndev); 2932 2933 return 0; 2934 } 2935 2936 /* Set or clear the multicast filter for this adaptor. 2937 * Skeleton taken from sunlance driver. 2938 * The CPM Ethernet implementation allows Multicast as well as individual 2939 * MAC address filtering. Some of the drivers check to make sure it is 2940 * a group multicast address, and discard those that are not. I guess I 2941 * will do the same for now, but just remove the test if you want 2942 * individual filtering as well (do the upper net layers want or support 2943 * this kind of feature?). 2944 */ 2945 2946 #define FEC_HASH_BITS 6 /* #bits in hash */ 2947 2948 static void set_multicast_list(struct net_device *ndev) 2949 { 2950 struct fec_enet_private *fep = netdev_priv(ndev); 2951 struct netdev_hw_addr *ha; 2952 unsigned int crc, tmp; 2953 unsigned char hash; 2954 unsigned int hash_high = 0, hash_low = 0; 2955 2956 if (ndev->flags & IFF_PROMISC) { 2957 tmp = readl(fep->hwp + FEC_R_CNTRL); 2958 tmp |= 0x8; 2959 writel(tmp, fep->hwp + FEC_R_CNTRL); 2960 return; 2961 } 2962 2963 tmp = readl(fep->hwp + FEC_R_CNTRL); 2964 tmp &= ~0x8; 2965 writel(tmp, fep->hwp + FEC_R_CNTRL); 2966 2967 if (ndev->flags & IFF_ALLMULTI) { 2968 /* Catch all multicast addresses, so set the 2969 * filter to all 1's 2970 */ 2971 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2972 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2973 2974 return; 2975 } 2976 2977 /* Add the addresses in hash register */ 2978 netdev_for_each_mc_addr(ha, ndev) { 2979 /* calculate crc32 value of mac address */ 2980 crc = ether_crc_le(ndev->addr_len, ha->addr); 2981 2982 /* only upper 6 bits (FEC_HASH_BITS) are used 2983 * which point to specific bit in the hash registers 2984 */ 2985 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 2986 2987 if (hash > 31) 2988 hash_high |= 1 << (hash - 32); 2989 else 2990 hash_low |= 1 << hash; 2991 } 2992 2993 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2994 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2995 } 2996 2997 /* Set a MAC change in hardware. */ 2998 static int 2999 fec_set_mac_address(struct net_device *ndev, void *p) 3000 { 3001 struct fec_enet_private *fep = netdev_priv(ndev); 3002 struct sockaddr *addr = p; 3003 3004 if (addr) { 3005 if (!is_valid_ether_addr(addr->sa_data)) 3006 return -EADDRNOTAVAIL; 3007 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 3008 } 3009 3010 /* Add netif status check here to avoid system hang in below case: 3011 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3012 * After ethx down, fec all clocks are gated off and then register 3013 * access causes system hang. 3014 */ 3015 if (!netif_running(ndev)) 3016 return 0; 3017 3018 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3019 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3020 fep->hwp + FEC_ADDR_LOW); 3021 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3022 fep->hwp + FEC_ADDR_HIGH); 3023 return 0; 3024 } 3025 3026 #ifdef CONFIG_NET_POLL_CONTROLLER 3027 /** 3028 * fec_poll_controller - FEC Poll controller function 3029 * @dev: The FEC network adapter 3030 * 3031 * Polled functionality used by netconsole and others in non interrupt mode 3032 * 3033 */ 3034 static void fec_poll_controller(struct net_device *dev) 3035 { 3036 int i; 3037 struct fec_enet_private *fep = netdev_priv(dev); 3038 3039 for (i = 0; i < FEC_IRQ_NUM; i++) { 3040 if (fep->irq[i] > 0) { 3041 disable_irq(fep->irq[i]); 3042 fec_enet_interrupt(fep->irq[i], dev); 3043 enable_irq(fep->irq[i]); 3044 } 3045 } 3046 } 3047 #endif 3048 3049 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3050 netdev_features_t features) 3051 { 3052 struct fec_enet_private *fep = netdev_priv(netdev); 3053 netdev_features_t changed = features ^ netdev->features; 3054 3055 netdev->features = features; 3056 3057 /* Receive checksum has been changed */ 3058 if (changed & NETIF_F_RXCSUM) { 3059 if (features & NETIF_F_RXCSUM) 3060 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3061 else 3062 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3063 } 3064 } 3065 3066 static int fec_set_features(struct net_device *netdev, 3067 netdev_features_t features) 3068 { 3069 struct fec_enet_private *fep = netdev_priv(netdev); 3070 netdev_features_t changed = features ^ netdev->features; 3071 3072 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3073 napi_disable(&fep->napi); 3074 netif_tx_lock_bh(netdev); 3075 fec_stop(netdev); 3076 fec_enet_set_netdev_features(netdev, features); 3077 fec_restart(netdev); 3078 netif_tx_wake_all_queues(netdev); 3079 netif_tx_unlock_bh(netdev); 3080 napi_enable(&fep->napi); 3081 } else { 3082 fec_enet_set_netdev_features(netdev, features); 3083 } 3084 3085 return 0; 3086 } 3087 3088 static const struct net_device_ops fec_netdev_ops = { 3089 .ndo_open = fec_enet_open, 3090 .ndo_stop = fec_enet_close, 3091 .ndo_start_xmit = fec_enet_start_xmit, 3092 .ndo_set_rx_mode = set_multicast_list, 3093 .ndo_validate_addr = eth_validate_addr, 3094 .ndo_tx_timeout = fec_timeout, 3095 .ndo_set_mac_address = fec_set_mac_address, 3096 .ndo_do_ioctl = fec_enet_ioctl, 3097 #ifdef CONFIG_NET_POLL_CONTROLLER 3098 .ndo_poll_controller = fec_poll_controller, 3099 #endif 3100 .ndo_set_features = fec_set_features, 3101 }; 3102 3103 static const unsigned short offset_des_active_rxq[] = { 3104 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3105 }; 3106 3107 static const unsigned short offset_des_active_txq[] = { 3108 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3109 }; 3110 3111 /* 3112 * XXX: We need to clean up on failure exits here. 3113 * 3114 */ 3115 static int fec_enet_init(struct net_device *ndev) 3116 { 3117 struct fec_enet_private *fep = netdev_priv(ndev); 3118 struct bufdesc *cbd_base; 3119 dma_addr_t bd_dma; 3120 int bd_size; 3121 unsigned int i; 3122 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3123 sizeof(struct bufdesc); 3124 unsigned dsize_log2 = __fls(dsize); 3125 int ret; 3126 3127 WARN_ON(dsize != (1 << dsize_log2)); 3128 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 3129 fep->rx_align = 0xf; 3130 fep->tx_align = 0xf; 3131 #else 3132 fep->rx_align = 0x3; 3133 fep->tx_align = 0x3; 3134 #endif 3135 3136 /* Check mask of the streaming and coherent API */ 3137 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 3138 if (ret < 0) { 3139 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 3140 return ret; 3141 } 3142 3143 fec_enet_alloc_queue(ndev); 3144 3145 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3146 3147 /* Allocate memory for buffer descriptors. */ 3148 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3149 GFP_KERNEL); 3150 if (!cbd_base) { 3151 return -ENOMEM; 3152 } 3153 3154 memset(cbd_base, 0, bd_size); 3155 3156 /* Get the Ethernet address */ 3157 fec_get_mac(ndev); 3158 /* make sure MAC we just acquired is programmed into the hw */ 3159 fec_set_mac_address(ndev, NULL); 3160 3161 /* Set receive and transmit descriptor base. */ 3162 for (i = 0; i < fep->num_rx_queues; i++) { 3163 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3164 unsigned size = dsize * rxq->bd.ring_size; 3165 3166 rxq->bd.qid = i; 3167 rxq->bd.base = cbd_base; 3168 rxq->bd.cur = cbd_base; 3169 rxq->bd.dma = bd_dma; 3170 rxq->bd.dsize = dsize; 3171 rxq->bd.dsize_log2 = dsize_log2; 3172 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3173 bd_dma += size; 3174 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3175 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3176 } 3177 3178 for (i = 0; i < fep->num_tx_queues; i++) { 3179 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3180 unsigned size = dsize * txq->bd.ring_size; 3181 3182 txq->bd.qid = i; 3183 txq->bd.base = cbd_base; 3184 txq->bd.cur = cbd_base; 3185 txq->bd.dma = bd_dma; 3186 txq->bd.dsize = dsize; 3187 txq->bd.dsize_log2 = dsize_log2; 3188 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3189 bd_dma += size; 3190 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3191 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3192 } 3193 3194 3195 /* The FEC Ethernet specific entries in the device structure */ 3196 ndev->watchdog_timeo = TX_TIMEOUT; 3197 ndev->netdev_ops = &fec_netdev_ops; 3198 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3199 3200 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3201 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3202 3203 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3204 /* enable hw VLAN support */ 3205 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3206 3207 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3208 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3209 3210 /* enable hw accelerator */ 3211 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3212 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3213 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3214 } 3215 3216 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 3217 fep->tx_align = 0; 3218 fep->rx_align = 0x3f; 3219 } 3220 3221 ndev->hw_features = ndev->features; 3222 3223 fec_restart(ndev); 3224 3225 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 3226 fec_enet_clear_ethtool_stats(ndev); 3227 else 3228 fec_enet_update_ethtool_stats(ndev); 3229 3230 return 0; 3231 } 3232 3233 #ifdef CONFIG_OF 3234 static int fec_reset_phy(struct platform_device *pdev) 3235 { 3236 int err, phy_reset; 3237 bool active_high = false; 3238 int msec = 1, phy_post_delay = 0; 3239 struct device_node *np = pdev->dev.of_node; 3240 3241 if (!np) 3242 return 0; 3243 3244 err = of_property_read_u32(np, "phy-reset-duration", &msec); 3245 /* A sane reset duration should not be longer than 1s */ 3246 if (!err && msec > 1000) 3247 msec = 1; 3248 3249 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3250 if (phy_reset == -EPROBE_DEFER) 3251 return phy_reset; 3252 else if (!gpio_is_valid(phy_reset)) 3253 return 0; 3254 3255 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 3256 /* valid reset duration should be less than 1s */ 3257 if (!err && phy_post_delay > 1000) 3258 return -EINVAL; 3259 3260 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3261 3262 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3263 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3264 "phy-reset"); 3265 if (err) { 3266 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3267 return err; 3268 } 3269 3270 if (msec > 20) 3271 msleep(msec); 3272 else 3273 usleep_range(msec * 1000, msec * 1000 + 1000); 3274 3275 gpio_set_value_cansleep(phy_reset, !active_high); 3276 3277 if (!phy_post_delay) 3278 return 0; 3279 3280 if (phy_post_delay > 20) 3281 msleep(phy_post_delay); 3282 else 3283 usleep_range(phy_post_delay * 1000, 3284 phy_post_delay * 1000 + 1000); 3285 3286 return 0; 3287 } 3288 #else /* CONFIG_OF */ 3289 static int fec_reset_phy(struct platform_device *pdev) 3290 { 3291 /* 3292 * In case of platform probe, the reset has been done 3293 * by machine code. 3294 */ 3295 return 0; 3296 } 3297 #endif /* CONFIG_OF */ 3298 3299 static void 3300 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3301 { 3302 struct device_node *np = pdev->dev.of_node; 3303 3304 *num_tx = *num_rx = 1; 3305 3306 if (!np || !of_device_is_available(np)) 3307 return; 3308 3309 /* parse the num of tx and rx queues */ 3310 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3311 3312 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3313 3314 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3315 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3316 *num_tx); 3317 *num_tx = 1; 3318 return; 3319 } 3320 3321 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3322 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3323 *num_rx); 3324 *num_rx = 1; 3325 return; 3326 } 3327 3328 } 3329 3330 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 3331 { 3332 int irq_cnt = platform_irq_count(pdev); 3333 3334 if (irq_cnt > FEC_IRQ_NUM) 3335 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 3336 else if (irq_cnt == 2) 3337 irq_cnt = 1; /* last for pps */ 3338 else if (irq_cnt <= 0) 3339 irq_cnt = 1; /* At least 1 irq is needed */ 3340 return irq_cnt; 3341 } 3342 3343 static int 3344 fec_probe(struct platform_device *pdev) 3345 { 3346 struct fec_enet_private *fep; 3347 struct fec_platform_data *pdata; 3348 struct net_device *ndev; 3349 int i, irq, ret = 0; 3350 struct resource *r; 3351 const struct of_device_id *of_id; 3352 static int dev_id; 3353 struct device_node *np = pdev->dev.of_node, *phy_node; 3354 int num_tx_qs; 3355 int num_rx_qs; 3356 char irq_name[8]; 3357 int irq_cnt; 3358 3359 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3360 3361 /* Init network device */ 3362 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 3363 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 3364 if (!ndev) 3365 return -ENOMEM; 3366 3367 SET_NETDEV_DEV(ndev, &pdev->dev); 3368 3369 /* setup board info structure */ 3370 fep = netdev_priv(ndev); 3371 3372 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3373 if (of_id) 3374 pdev->id_entry = of_id->data; 3375 fep->quirks = pdev->id_entry->driver_data; 3376 3377 fep->netdev = ndev; 3378 fep->num_rx_queues = num_rx_qs; 3379 fep->num_tx_queues = num_tx_qs; 3380 3381 #if !defined(CONFIG_M5272) 3382 /* default enable pause frame auto negotiation */ 3383 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3384 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3385 #endif 3386 3387 /* Select default pin state */ 3388 pinctrl_pm_select_default_state(&pdev->dev); 3389 3390 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3391 fep->hwp = devm_ioremap_resource(&pdev->dev, r); 3392 if (IS_ERR(fep->hwp)) { 3393 ret = PTR_ERR(fep->hwp); 3394 goto failed_ioremap; 3395 } 3396 3397 fep->pdev = pdev; 3398 fep->dev_id = dev_id++; 3399 3400 platform_set_drvdata(pdev, ndev); 3401 3402 if ((of_machine_is_compatible("fsl,imx6q") || 3403 of_machine_is_compatible("fsl,imx6dl")) && 3404 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3405 fep->quirks |= FEC_QUIRK_ERR006687; 3406 3407 if (of_get_property(np, "fsl,magic-packet", NULL)) 3408 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3409 3410 phy_node = of_parse_phandle(np, "phy-handle", 0); 3411 if (!phy_node && of_phy_is_fixed_link(np)) { 3412 ret = of_phy_register_fixed_link(np); 3413 if (ret < 0) { 3414 dev_err(&pdev->dev, 3415 "broken fixed-link specification\n"); 3416 goto failed_phy; 3417 } 3418 phy_node = of_node_get(np); 3419 } 3420 fep->phy_node = phy_node; 3421 3422 ret = of_get_phy_mode(pdev->dev.of_node); 3423 if (ret < 0) { 3424 pdata = dev_get_platdata(&pdev->dev); 3425 if (pdata) 3426 fep->phy_interface = pdata->phy; 3427 else 3428 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3429 } else { 3430 fep->phy_interface = ret; 3431 } 3432 3433 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3434 if (IS_ERR(fep->clk_ipg)) { 3435 ret = PTR_ERR(fep->clk_ipg); 3436 goto failed_clk; 3437 } 3438 3439 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3440 if (IS_ERR(fep->clk_ahb)) { 3441 ret = PTR_ERR(fep->clk_ahb); 3442 goto failed_clk; 3443 } 3444 3445 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3446 3447 /* enet_out is optional, depends on board */ 3448 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3449 if (IS_ERR(fep->clk_enet_out)) 3450 fep->clk_enet_out = NULL; 3451 3452 fep->ptp_clk_on = false; 3453 mutex_init(&fep->ptp_clk_mutex); 3454 3455 /* clk_ref is optional, depends on board */ 3456 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3457 if (IS_ERR(fep->clk_ref)) 3458 fep->clk_ref = NULL; 3459 3460 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3461 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3462 if (IS_ERR(fep->clk_ptp)) { 3463 fep->clk_ptp = NULL; 3464 fep->bufdesc_ex = false; 3465 } 3466 3467 ret = fec_enet_clk_enable(ndev, true); 3468 if (ret) 3469 goto failed_clk; 3470 3471 ret = clk_prepare_enable(fep->clk_ipg); 3472 if (ret) 3473 goto failed_clk_ipg; 3474 3475 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); 3476 if (!IS_ERR(fep->reg_phy)) { 3477 ret = regulator_enable(fep->reg_phy); 3478 if (ret) { 3479 dev_err(&pdev->dev, 3480 "Failed to enable phy regulator: %d\n", ret); 3481 clk_disable_unprepare(fep->clk_ipg); 3482 goto failed_regulator; 3483 } 3484 } else { 3485 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 3486 ret = -EPROBE_DEFER; 3487 goto failed_regulator; 3488 } 3489 fep->reg_phy = NULL; 3490 } 3491 3492 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3493 pm_runtime_use_autosuspend(&pdev->dev); 3494 pm_runtime_get_noresume(&pdev->dev); 3495 pm_runtime_set_active(&pdev->dev); 3496 pm_runtime_enable(&pdev->dev); 3497 3498 ret = fec_reset_phy(pdev); 3499 if (ret) 3500 goto failed_reset; 3501 3502 irq_cnt = fec_enet_get_irq_cnt(pdev); 3503 if (fep->bufdesc_ex) 3504 fec_ptp_init(pdev, irq_cnt); 3505 3506 ret = fec_enet_init(ndev); 3507 if (ret) 3508 goto failed_init; 3509 3510 for (i = 0; i < irq_cnt; i++) { 3511 snprintf(irq_name, sizeof(irq_name), "int%d", i); 3512 irq = platform_get_irq_byname(pdev, irq_name); 3513 if (irq < 0) 3514 irq = platform_get_irq(pdev, i); 3515 if (irq < 0) { 3516 ret = irq; 3517 goto failed_irq; 3518 } 3519 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3520 0, pdev->name, ndev); 3521 if (ret) 3522 goto failed_irq; 3523 3524 fep->irq[i] = irq; 3525 } 3526 3527 init_completion(&fep->mdio_done); 3528 ret = fec_enet_mii_init(pdev); 3529 if (ret) 3530 goto failed_mii_init; 3531 3532 /* Carrier starts down, phylib will bring it up */ 3533 netif_carrier_off(ndev); 3534 fec_enet_clk_enable(ndev, false); 3535 pinctrl_pm_select_sleep_state(&pdev->dev); 3536 3537 ret = register_netdev(ndev); 3538 if (ret) 3539 goto failed_register; 3540 3541 device_init_wakeup(&ndev->dev, fep->wol_flag & 3542 FEC_WOL_HAS_MAGIC_PACKET); 3543 3544 if (fep->bufdesc_ex && fep->ptp_clock) 3545 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3546 3547 fep->rx_copybreak = COPYBREAK_DEFAULT; 3548 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3549 3550 pm_runtime_mark_last_busy(&pdev->dev); 3551 pm_runtime_put_autosuspend(&pdev->dev); 3552 3553 return 0; 3554 3555 failed_register: 3556 fec_enet_mii_remove(fep); 3557 failed_mii_init: 3558 failed_irq: 3559 failed_init: 3560 fec_ptp_stop(pdev); 3561 if (fep->reg_phy) 3562 regulator_disable(fep->reg_phy); 3563 failed_reset: 3564 pm_runtime_put(&pdev->dev); 3565 pm_runtime_disable(&pdev->dev); 3566 failed_regulator: 3567 failed_clk_ipg: 3568 fec_enet_clk_enable(ndev, false); 3569 failed_clk: 3570 if (of_phy_is_fixed_link(np)) 3571 of_phy_deregister_fixed_link(np); 3572 of_node_put(phy_node); 3573 failed_phy: 3574 dev_id--; 3575 failed_ioremap: 3576 free_netdev(ndev); 3577 3578 return ret; 3579 } 3580 3581 static int 3582 fec_drv_remove(struct platform_device *pdev) 3583 { 3584 struct net_device *ndev = platform_get_drvdata(pdev); 3585 struct fec_enet_private *fep = netdev_priv(ndev); 3586 struct device_node *np = pdev->dev.of_node; 3587 3588 cancel_work_sync(&fep->tx_timeout_work); 3589 fec_ptp_stop(pdev); 3590 unregister_netdev(ndev); 3591 fec_enet_mii_remove(fep); 3592 if (fep->reg_phy) 3593 regulator_disable(fep->reg_phy); 3594 pm_runtime_put(&pdev->dev); 3595 pm_runtime_disable(&pdev->dev); 3596 if (of_phy_is_fixed_link(np)) 3597 of_phy_deregister_fixed_link(np); 3598 of_node_put(fep->phy_node); 3599 free_netdev(ndev); 3600 3601 return 0; 3602 } 3603 3604 static int __maybe_unused fec_suspend(struct device *dev) 3605 { 3606 struct net_device *ndev = dev_get_drvdata(dev); 3607 struct fec_enet_private *fep = netdev_priv(ndev); 3608 3609 rtnl_lock(); 3610 if (netif_running(ndev)) { 3611 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 3612 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 3613 phy_stop(ndev->phydev); 3614 napi_disable(&fep->napi); 3615 netif_tx_lock_bh(ndev); 3616 netif_device_detach(ndev); 3617 netif_tx_unlock_bh(ndev); 3618 fec_stop(ndev); 3619 fec_enet_clk_enable(ndev, false); 3620 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3621 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3622 } 3623 rtnl_unlock(); 3624 3625 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3626 regulator_disable(fep->reg_phy); 3627 3628 /* SOC supply clock to phy, when clock is disabled, phy link down 3629 * SOC control phy regulator, when regulator is disabled, phy link down 3630 */ 3631 if (fep->clk_enet_out || fep->reg_phy) 3632 fep->link = 0; 3633 3634 return 0; 3635 } 3636 3637 static int __maybe_unused fec_resume(struct device *dev) 3638 { 3639 struct net_device *ndev = dev_get_drvdata(dev); 3640 struct fec_enet_private *fep = netdev_priv(ndev); 3641 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 3642 int ret; 3643 int val; 3644 3645 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 3646 ret = regulator_enable(fep->reg_phy); 3647 if (ret) 3648 return ret; 3649 } 3650 3651 rtnl_lock(); 3652 if (netif_running(ndev)) { 3653 ret = fec_enet_clk_enable(ndev, true); 3654 if (ret) { 3655 rtnl_unlock(); 3656 goto failed_clk; 3657 } 3658 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 3659 if (pdata && pdata->sleep_mode_enable) 3660 pdata->sleep_mode_enable(false); 3661 val = readl(fep->hwp + FEC_ECNTRL); 3662 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 3663 writel(val, fep->hwp + FEC_ECNTRL); 3664 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 3665 } else { 3666 pinctrl_pm_select_default_state(&fep->pdev->dev); 3667 } 3668 fec_restart(ndev); 3669 netif_tx_lock_bh(ndev); 3670 netif_device_attach(ndev); 3671 netif_tx_unlock_bh(ndev); 3672 napi_enable(&fep->napi); 3673 phy_start(ndev->phydev); 3674 } 3675 rtnl_unlock(); 3676 3677 return 0; 3678 3679 failed_clk: 3680 if (fep->reg_phy) 3681 regulator_disable(fep->reg_phy); 3682 return ret; 3683 } 3684 3685 static int __maybe_unused fec_runtime_suspend(struct device *dev) 3686 { 3687 struct net_device *ndev = dev_get_drvdata(dev); 3688 struct fec_enet_private *fep = netdev_priv(ndev); 3689 3690 clk_disable_unprepare(fep->clk_ipg); 3691 3692 return 0; 3693 } 3694 3695 static int __maybe_unused fec_runtime_resume(struct device *dev) 3696 { 3697 struct net_device *ndev = dev_get_drvdata(dev); 3698 struct fec_enet_private *fep = netdev_priv(ndev); 3699 3700 return clk_prepare_enable(fep->clk_ipg); 3701 } 3702 3703 static const struct dev_pm_ops fec_pm_ops = { 3704 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 3705 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 3706 }; 3707 3708 static struct platform_driver fec_driver = { 3709 .driver = { 3710 .name = DRIVER_NAME, 3711 .pm = &fec_pm_ops, 3712 .of_match_table = fec_dt_ids, 3713 }, 3714 .id_table = fec_devtype, 3715 .probe = fec_probe, 3716 .remove = fec_drv_remove, 3717 }; 3718 3719 module_platform_driver(fec_driver); 3720 3721 MODULE_ALIAS("platform:"DRIVER_NAME); 3722 MODULE_LICENSE("GPL"); 3723