1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/selftests.h> 42 #include <net/tso.h> 43 #include <linux/tcp.h> 44 #include <linux/udp.h> 45 #include <linux/icmp.h> 46 #include <linux/spinlock.h> 47 #include <linux/workqueue.h> 48 #include <linux/bitops.h> 49 #include <linux/io.h> 50 #include <linux/irq.h> 51 #include <linux/clk.h> 52 #include <linux/crc32.h> 53 #include <linux/platform_device.h> 54 #include <linux/mdio.h> 55 #include <linux/phy.h> 56 #include <linux/fec.h> 57 #include <linux/of.h> 58 #include <linux/of_device.h> 59 #include <linux/of_gpio.h> 60 #include <linux/of_mdio.h> 61 #include <linux/of_net.h> 62 #include <linux/regulator/consumer.h> 63 #include <linux/if_vlan.h> 64 #include <linux/pinctrl/consumer.h> 65 #include <linux/prefetch.h> 66 #include <linux/mfd/syscon.h> 67 #include <linux/regmap.h> 68 #include <soc/imx/cpuidle.h> 69 70 #include <asm/cacheflush.h> 71 72 #include "fec.h" 73 74 static void set_multicast_list(struct net_device *ndev); 75 static void fec_enet_itr_coal_init(struct net_device *ndev); 76 77 #define DRIVER_NAME "fec" 78 79 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 80 81 /* Pause frame feild and FIFO threshold */ 82 #define FEC_ENET_FCE (1 << 5) 83 #define FEC_ENET_RSEM_V 0x84 84 #define FEC_ENET_RSFL_V 16 85 #define FEC_ENET_RAEM_V 0x8 86 #define FEC_ENET_RAFL_V 0x8 87 #define FEC_ENET_OPD_V 0xFFF0 88 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 89 90 struct fec_devinfo { 91 u32 quirks; 92 }; 93 94 static const struct fec_devinfo fec_imx25_info = { 95 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 96 FEC_QUIRK_HAS_FRREG, 97 }; 98 99 static const struct fec_devinfo fec_imx27_info = { 100 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG, 101 }; 102 103 static const struct fec_devinfo fec_imx28_info = { 104 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 105 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 106 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 107 FEC_QUIRK_NO_HARD_RESET, 108 }; 109 110 static const struct fec_devinfo fec_imx6q_info = { 111 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 112 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 113 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 114 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII, 115 }; 116 117 static const struct fec_devinfo fec_mvf600_info = { 118 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 119 }; 120 121 static const struct fec_devinfo fec_imx6x_info = { 122 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 125 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 126 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 127 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES, 128 }; 129 130 static const struct fec_devinfo fec_imx6ul_info = { 131 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 132 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 133 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 134 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 135 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII, 136 }; 137 138 static const struct fec_devinfo fec_imx8mq_info = { 139 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 140 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 141 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 142 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 143 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 144 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 145 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2, 146 }; 147 148 static const struct fec_devinfo fec_imx8qm_info = { 149 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 150 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 151 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 152 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 153 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 154 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 155 FEC_QUIRK_DELAYED_CLKS_SUPPORT, 156 }; 157 158 static struct platform_device_id fec_devtype[] = { 159 { 160 /* keep it for coldfire */ 161 .name = DRIVER_NAME, 162 .driver_data = 0, 163 }, { 164 .name = "imx25-fec", 165 .driver_data = (kernel_ulong_t)&fec_imx25_info, 166 }, { 167 .name = "imx27-fec", 168 .driver_data = (kernel_ulong_t)&fec_imx27_info, 169 }, { 170 .name = "imx28-fec", 171 .driver_data = (kernel_ulong_t)&fec_imx28_info, 172 }, { 173 .name = "imx6q-fec", 174 .driver_data = (kernel_ulong_t)&fec_imx6q_info, 175 }, { 176 .name = "mvf600-fec", 177 .driver_data = (kernel_ulong_t)&fec_mvf600_info, 178 }, { 179 .name = "imx6sx-fec", 180 .driver_data = (kernel_ulong_t)&fec_imx6x_info, 181 }, { 182 .name = "imx6ul-fec", 183 .driver_data = (kernel_ulong_t)&fec_imx6ul_info, 184 }, { 185 .name = "imx8mq-fec", 186 .driver_data = (kernel_ulong_t)&fec_imx8mq_info, 187 }, { 188 .name = "imx8qm-fec", 189 .driver_data = (kernel_ulong_t)&fec_imx8qm_info, 190 }, { 191 /* sentinel */ 192 } 193 }; 194 MODULE_DEVICE_TABLE(platform, fec_devtype); 195 196 enum imx_fec_type { 197 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 198 IMX27_FEC, /* runs on i.mx27/35/51 */ 199 IMX28_FEC, 200 IMX6Q_FEC, 201 MVF600_FEC, 202 IMX6SX_FEC, 203 IMX6UL_FEC, 204 IMX8MQ_FEC, 205 IMX8QM_FEC, 206 }; 207 208 static const struct of_device_id fec_dt_ids[] = { 209 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 210 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 211 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 212 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 213 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 214 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 215 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 216 { .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], }, 217 { .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], }, 218 { /* sentinel */ } 219 }; 220 MODULE_DEVICE_TABLE(of, fec_dt_ids); 221 222 static unsigned char macaddr[ETH_ALEN]; 223 module_param_array(macaddr, byte, NULL, 0); 224 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 225 226 #if defined(CONFIG_M5272) 227 /* 228 * Some hardware gets it MAC address out of local flash memory. 229 * if this is non-zero then assume it is the address to get MAC from. 230 */ 231 #if defined(CONFIG_NETtel) 232 #define FEC_FLASHMAC 0xf0006006 233 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 234 #define FEC_FLASHMAC 0xf0006000 235 #elif defined(CONFIG_CANCam) 236 #define FEC_FLASHMAC 0xf0020000 237 #elif defined (CONFIG_M5272C3) 238 #define FEC_FLASHMAC (0xffe04000 + 4) 239 #elif defined(CONFIG_MOD5272) 240 #define FEC_FLASHMAC 0xffc0406b 241 #else 242 #define FEC_FLASHMAC 0 243 #endif 244 #endif /* CONFIG_M5272 */ 245 246 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 247 * 248 * 2048 byte skbufs are allocated. However, alignment requirements 249 * varies between FEC variants. Worst case is 64, so round down by 64. 250 */ 251 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 252 #define PKT_MINBUF_SIZE 64 253 254 /* FEC receive acceleration */ 255 #define FEC_RACC_IPDIS (1 << 1) 256 #define FEC_RACC_PRODIS (1 << 2) 257 #define FEC_RACC_SHIFT16 BIT(7) 258 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 259 260 /* MIB Control Register */ 261 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 262 263 /* 264 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 265 * size bits. Other FEC hardware does not, so we need to take that into 266 * account when setting it. 267 */ 268 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 269 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 270 defined(CONFIG_ARM64) 271 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 272 #else 273 #define OPT_FRAME_SIZE 0 274 #endif 275 276 /* FEC MII MMFR bits definition */ 277 #define FEC_MMFR_ST (1 << 30) 278 #define FEC_MMFR_ST_C45 (0) 279 #define FEC_MMFR_OP_READ (2 << 28) 280 #define FEC_MMFR_OP_READ_C45 (3 << 28) 281 #define FEC_MMFR_OP_WRITE (1 << 28) 282 #define FEC_MMFR_OP_ADDR_WRITE (0) 283 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 284 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 285 #define FEC_MMFR_TA (2 << 16) 286 #define FEC_MMFR_DATA(v) (v & 0xffff) 287 /* FEC ECR bits definition */ 288 #define FEC_ECR_MAGICEN (1 << 2) 289 #define FEC_ECR_SLEEP (1 << 3) 290 291 #define FEC_MII_TIMEOUT 30000 /* us */ 292 293 /* Transmitter timeout */ 294 #define TX_TIMEOUT (2 * HZ) 295 296 #define FEC_PAUSE_FLAG_AUTONEG 0x1 297 #define FEC_PAUSE_FLAG_ENABLE 0x2 298 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 299 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 300 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 301 302 #define COPYBREAK_DEFAULT 256 303 304 /* Max number of allowed TCP segments for software TSO */ 305 #define FEC_MAX_TSO_SEGS 100 306 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 307 308 #define IS_TSO_HEADER(txq, addr) \ 309 ((addr >= txq->tso_hdrs_dma) && \ 310 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 311 312 static int mii_cnt; 313 314 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 315 struct bufdesc_prop *bd) 316 { 317 return (bdp >= bd->last) ? bd->base 318 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 319 } 320 321 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 322 struct bufdesc_prop *bd) 323 { 324 return (bdp <= bd->base) ? bd->last 325 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 326 } 327 328 static int fec_enet_get_bd_index(struct bufdesc *bdp, 329 struct bufdesc_prop *bd) 330 { 331 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 332 } 333 334 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 335 { 336 int entries; 337 338 entries = (((const char *)txq->dirty_tx - 339 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 340 341 return entries >= 0 ? entries : entries + txq->bd.ring_size; 342 } 343 344 static void swap_buffer(void *bufaddr, int len) 345 { 346 int i; 347 unsigned int *buf = bufaddr; 348 349 for (i = 0; i < len; i += 4, buf++) 350 swab32s(buf); 351 } 352 353 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 354 { 355 int i; 356 unsigned int *src = src_buf; 357 unsigned int *dst = dst_buf; 358 359 for (i = 0; i < len; i += 4, src++, dst++) 360 *dst = swab32p(src); 361 } 362 363 static void fec_dump(struct net_device *ndev) 364 { 365 struct fec_enet_private *fep = netdev_priv(ndev); 366 struct bufdesc *bdp; 367 struct fec_enet_priv_tx_q *txq; 368 int index = 0; 369 370 netdev_info(ndev, "TX ring dump\n"); 371 pr_info("Nr SC addr len SKB\n"); 372 373 txq = fep->tx_queue[0]; 374 bdp = txq->bd.base; 375 376 do { 377 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 378 index, 379 bdp == txq->bd.cur ? 'S' : ' ', 380 bdp == txq->dirty_tx ? 'H' : ' ', 381 fec16_to_cpu(bdp->cbd_sc), 382 fec32_to_cpu(bdp->cbd_bufaddr), 383 fec16_to_cpu(bdp->cbd_datlen), 384 txq->tx_skbuff[index]); 385 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 386 index++; 387 } while (bdp != txq->bd.base); 388 } 389 390 static inline bool is_ipv4_pkt(struct sk_buff *skb) 391 { 392 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 393 } 394 395 static int 396 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 397 { 398 /* Only run for packets requiring a checksum. */ 399 if (skb->ip_summed != CHECKSUM_PARTIAL) 400 return 0; 401 402 if (unlikely(skb_cow_head(skb, 0))) 403 return -1; 404 405 if (is_ipv4_pkt(skb)) 406 ip_hdr(skb)->check = 0; 407 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 408 409 return 0; 410 } 411 412 static struct bufdesc * 413 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 414 struct sk_buff *skb, 415 struct net_device *ndev) 416 { 417 struct fec_enet_private *fep = netdev_priv(ndev); 418 struct bufdesc *bdp = txq->bd.cur; 419 struct bufdesc_ex *ebdp; 420 int nr_frags = skb_shinfo(skb)->nr_frags; 421 int frag, frag_len; 422 unsigned short status; 423 unsigned int estatus = 0; 424 skb_frag_t *this_frag; 425 unsigned int index; 426 void *bufaddr; 427 dma_addr_t addr; 428 int i; 429 430 for (frag = 0; frag < nr_frags; frag++) { 431 this_frag = &skb_shinfo(skb)->frags[frag]; 432 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 433 ebdp = (struct bufdesc_ex *)bdp; 434 435 status = fec16_to_cpu(bdp->cbd_sc); 436 status &= ~BD_ENET_TX_STATS; 437 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 438 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 439 440 /* Handle the last BD specially */ 441 if (frag == nr_frags - 1) { 442 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 443 if (fep->bufdesc_ex) { 444 estatus |= BD_ENET_TX_INT; 445 if (unlikely(skb_shinfo(skb)->tx_flags & 446 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 447 estatus |= BD_ENET_TX_TS; 448 } 449 } 450 451 if (fep->bufdesc_ex) { 452 if (fep->quirks & FEC_QUIRK_HAS_AVB) 453 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 454 if (skb->ip_summed == CHECKSUM_PARTIAL) 455 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 456 457 ebdp->cbd_bdu = 0; 458 ebdp->cbd_esc = cpu_to_fec32(estatus); 459 } 460 461 bufaddr = skb_frag_address(this_frag); 462 463 index = fec_enet_get_bd_index(bdp, &txq->bd); 464 if (((unsigned long) bufaddr) & fep->tx_align || 465 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 466 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 467 bufaddr = txq->tx_bounce[index]; 468 469 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 470 swap_buffer(bufaddr, frag_len); 471 } 472 473 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 474 DMA_TO_DEVICE); 475 if (dma_mapping_error(&fep->pdev->dev, addr)) { 476 if (net_ratelimit()) 477 netdev_err(ndev, "Tx DMA memory map failed\n"); 478 goto dma_mapping_error; 479 } 480 481 bdp->cbd_bufaddr = cpu_to_fec32(addr); 482 bdp->cbd_datlen = cpu_to_fec16(frag_len); 483 /* Make sure the updates to rest of the descriptor are 484 * performed before transferring ownership. 485 */ 486 wmb(); 487 bdp->cbd_sc = cpu_to_fec16(status); 488 } 489 490 return bdp; 491 dma_mapping_error: 492 bdp = txq->bd.cur; 493 for (i = 0; i < frag; i++) { 494 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 495 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 496 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 497 } 498 return ERR_PTR(-ENOMEM); 499 } 500 501 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 502 struct sk_buff *skb, struct net_device *ndev) 503 { 504 struct fec_enet_private *fep = netdev_priv(ndev); 505 int nr_frags = skb_shinfo(skb)->nr_frags; 506 struct bufdesc *bdp, *last_bdp; 507 void *bufaddr; 508 dma_addr_t addr; 509 unsigned short status; 510 unsigned short buflen; 511 unsigned int estatus = 0; 512 unsigned int index; 513 int entries_free; 514 515 entries_free = fec_enet_get_free_txdesc_num(txq); 516 if (entries_free < MAX_SKB_FRAGS + 1) { 517 dev_kfree_skb_any(skb); 518 if (net_ratelimit()) 519 netdev_err(ndev, "NOT enough BD for SG!\n"); 520 return NETDEV_TX_OK; 521 } 522 523 /* Protocol checksum off-load for TCP and UDP. */ 524 if (fec_enet_clear_csum(skb, ndev)) { 525 dev_kfree_skb_any(skb); 526 return NETDEV_TX_OK; 527 } 528 529 /* Fill in a Tx ring entry */ 530 bdp = txq->bd.cur; 531 last_bdp = bdp; 532 status = fec16_to_cpu(bdp->cbd_sc); 533 status &= ~BD_ENET_TX_STATS; 534 535 /* Set buffer length and buffer pointer */ 536 bufaddr = skb->data; 537 buflen = skb_headlen(skb); 538 539 index = fec_enet_get_bd_index(bdp, &txq->bd); 540 if (((unsigned long) bufaddr) & fep->tx_align || 541 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 542 memcpy(txq->tx_bounce[index], skb->data, buflen); 543 bufaddr = txq->tx_bounce[index]; 544 545 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 546 swap_buffer(bufaddr, buflen); 547 } 548 549 /* Push the data cache so the CPM does not get stale memory data. */ 550 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 551 if (dma_mapping_error(&fep->pdev->dev, addr)) { 552 dev_kfree_skb_any(skb); 553 if (net_ratelimit()) 554 netdev_err(ndev, "Tx DMA memory map failed\n"); 555 return NETDEV_TX_OK; 556 } 557 558 if (nr_frags) { 559 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 560 if (IS_ERR(last_bdp)) { 561 dma_unmap_single(&fep->pdev->dev, addr, 562 buflen, DMA_TO_DEVICE); 563 dev_kfree_skb_any(skb); 564 return NETDEV_TX_OK; 565 } 566 } else { 567 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 568 if (fep->bufdesc_ex) { 569 estatus = BD_ENET_TX_INT; 570 if (unlikely(skb_shinfo(skb)->tx_flags & 571 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 572 estatus |= BD_ENET_TX_TS; 573 } 574 } 575 bdp->cbd_bufaddr = cpu_to_fec32(addr); 576 bdp->cbd_datlen = cpu_to_fec16(buflen); 577 578 if (fep->bufdesc_ex) { 579 580 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 581 582 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 583 fep->hwts_tx_en)) 584 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 585 586 if (fep->quirks & FEC_QUIRK_HAS_AVB) 587 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 588 589 if (skb->ip_summed == CHECKSUM_PARTIAL) 590 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 591 592 ebdp->cbd_bdu = 0; 593 ebdp->cbd_esc = cpu_to_fec32(estatus); 594 } 595 596 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 597 /* Save skb pointer */ 598 txq->tx_skbuff[index] = skb; 599 600 /* Make sure the updates to rest of the descriptor are performed before 601 * transferring ownership. 602 */ 603 wmb(); 604 605 /* Send it on its way. Tell FEC it's ready, interrupt when done, 606 * it's the last BD of the frame, and to put the CRC on the end. 607 */ 608 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 609 bdp->cbd_sc = cpu_to_fec16(status); 610 611 /* If this was the last BD in the ring, start at the beginning again. */ 612 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 613 614 skb_tx_timestamp(skb); 615 616 /* Make sure the update to bdp and tx_skbuff are performed before 617 * txq->bd.cur. 618 */ 619 wmb(); 620 txq->bd.cur = bdp; 621 622 /* Trigger transmission start */ 623 writel(0, txq->bd.reg_desc_active); 624 625 return 0; 626 } 627 628 static int 629 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 630 struct net_device *ndev, 631 struct bufdesc *bdp, int index, char *data, 632 int size, bool last_tcp, bool is_last) 633 { 634 struct fec_enet_private *fep = netdev_priv(ndev); 635 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 636 unsigned short status; 637 unsigned int estatus = 0; 638 dma_addr_t addr; 639 640 status = fec16_to_cpu(bdp->cbd_sc); 641 status &= ~BD_ENET_TX_STATS; 642 643 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 644 645 if (((unsigned long) data) & fep->tx_align || 646 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 647 memcpy(txq->tx_bounce[index], data, size); 648 data = txq->tx_bounce[index]; 649 650 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 651 swap_buffer(data, size); 652 } 653 654 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 655 if (dma_mapping_error(&fep->pdev->dev, addr)) { 656 dev_kfree_skb_any(skb); 657 if (net_ratelimit()) 658 netdev_err(ndev, "Tx DMA memory map failed\n"); 659 return NETDEV_TX_BUSY; 660 } 661 662 bdp->cbd_datlen = cpu_to_fec16(size); 663 bdp->cbd_bufaddr = cpu_to_fec32(addr); 664 665 if (fep->bufdesc_ex) { 666 if (fep->quirks & FEC_QUIRK_HAS_AVB) 667 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 668 if (skb->ip_summed == CHECKSUM_PARTIAL) 669 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 670 ebdp->cbd_bdu = 0; 671 ebdp->cbd_esc = cpu_to_fec32(estatus); 672 } 673 674 /* Handle the last BD specially */ 675 if (last_tcp) 676 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 677 if (is_last) { 678 status |= BD_ENET_TX_INTR; 679 if (fep->bufdesc_ex) 680 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 681 } 682 683 bdp->cbd_sc = cpu_to_fec16(status); 684 685 return 0; 686 } 687 688 static int 689 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 690 struct sk_buff *skb, struct net_device *ndev, 691 struct bufdesc *bdp, int index) 692 { 693 struct fec_enet_private *fep = netdev_priv(ndev); 694 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 695 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 696 void *bufaddr; 697 unsigned long dmabuf; 698 unsigned short status; 699 unsigned int estatus = 0; 700 701 status = fec16_to_cpu(bdp->cbd_sc); 702 status &= ~BD_ENET_TX_STATS; 703 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 704 705 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 706 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 707 if (((unsigned long)bufaddr) & fep->tx_align || 708 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 709 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 710 bufaddr = txq->tx_bounce[index]; 711 712 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 713 swap_buffer(bufaddr, hdr_len); 714 715 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 716 hdr_len, DMA_TO_DEVICE); 717 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 718 dev_kfree_skb_any(skb); 719 if (net_ratelimit()) 720 netdev_err(ndev, "Tx DMA memory map failed\n"); 721 return NETDEV_TX_BUSY; 722 } 723 } 724 725 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 726 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 727 728 if (fep->bufdesc_ex) { 729 if (fep->quirks & FEC_QUIRK_HAS_AVB) 730 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 731 if (skb->ip_summed == CHECKSUM_PARTIAL) 732 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 733 ebdp->cbd_bdu = 0; 734 ebdp->cbd_esc = cpu_to_fec32(estatus); 735 } 736 737 bdp->cbd_sc = cpu_to_fec16(status); 738 739 return 0; 740 } 741 742 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 743 struct sk_buff *skb, 744 struct net_device *ndev) 745 { 746 struct fec_enet_private *fep = netdev_priv(ndev); 747 int hdr_len, total_len, data_left; 748 struct bufdesc *bdp = txq->bd.cur; 749 struct tso_t tso; 750 unsigned int index = 0; 751 int ret; 752 753 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 754 dev_kfree_skb_any(skb); 755 if (net_ratelimit()) 756 netdev_err(ndev, "NOT enough BD for TSO!\n"); 757 return NETDEV_TX_OK; 758 } 759 760 /* Protocol checksum off-load for TCP and UDP. */ 761 if (fec_enet_clear_csum(skb, ndev)) { 762 dev_kfree_skb_any(skb); 763 return NETDEV_TX_OK; 764 } 765 766 /* Initialize the TSO handler, and prepare the first payload */ 767 hdr_len = tso_start(skb, &tso); 768 769 total_len = skb->len - hdr_len; 770 while (total_len > 0) { 771 char *hdr; 772 773 index = fec_enet_get_bd_index(bdp, &txq->bd); 774 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 775 total_len -= data_left; 776 777 /* prepare packet headers: MAC + IP + TCP */ 778 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 779 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 780 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 781 if (ret) 782 goto err_release; 783 784 while (data_left > 0) { 785 int size; 786 787 size = min_t(int, tso.size, data_left); 788 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 789 index = fec_enet_get_bd_index(bdp, &txq->bd); 790 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 791 bdp, index, 792 tso.data, size, 793 size == data_left, 794 total_len == 0); 795 if (ret) 796 goto err_release; 797 798 data_left -= size; 799 tso_build_data(skb, &tso, size); 800 } 801 802 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 803 } 804 805 /* Save skb pointer */ 806 txq->tx_skbuff[index] = skb; 807 808 skb_tx_timestamp(skb); 809 txq->bd.cur = bdp; 810 811 /* Trigger transmission start */ 812 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 813 !readl(txq->bd.reg_desc_active) || 814 !readl(txq->bd.reg_desc_active) || 815 !readl(txq->bd.reg_desc_active) || 816 !readl(txq->bd.reg_desc_active)) 817 writel(0, txq->bd.reg_desc_active); 818 819 return 0; 820 821 err_release: 822 /* TODO: Release all used data descriptors for TSO */ 823 return ret; 824 } 825 826 static netdev_tx_t 827 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 828 { 829 struct fec_enet_private *fep = netdev_priv(ndev); 830 int entries_free; 831 unsigned short queue; 832 struct fec_enet_priv_tx_q *txq; 833 struct netdev_queue *nq; 834 int ret; 835 836 queue = skb_get_queue_mapping(skb); 837 txq = fep->tx_queue[queue]; 838 nq = netdev_get_tx_queue(ndev, queue); 839 840 if (skb_is_gso(skb)) 841 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 842 else 843 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 844 if (ret) 845 return ret; 846 847 entries_free = fec_enet_get_free_txdesc_num(txq); 848 if (entries_free <= txq->tx_stop_threshold) 849 netif_tx_stop_queue(nq); 850 851 return NETDEV_TX_OK; 852 } 853 854 /* Init RX & TX buffer descriptors 855 */ 856 static void fec_enet_bd_init(struct net_device *dev) 857 { 858 struct fec_enet_private *fep = netdev_priv(dev); 859 struct fec_enet_priv_tx_q *txq; 860 struct fec_enet_priv_rx_q *rxq; 861 struct bufdesc *bdp; 862 unsigned int i; 863 unsigned int q; 864 865 for (q = 0; q < fep->num_rx_queues; q++) { 866 /* Initialize the receive buffer descriptors. */ 867 rxq = fep->rx_queue[q]; 868 bdp = rxq->bd.base; 869 870 for (i = 0; i < rxq->bd.ring_size; i++) { 871 872 /* Initialize the BD for every fragment in the page. */ 873 if (bdp->cbd_bufaddr) 874 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 875 else 876 bdp->cbd_sc = cpu_to_fec16(0); 877 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 878 } 879 880 /* Set the last buffer to wrap */ 881 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 882 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 883 884 rxq->bd.cur = rxq->bd.base; 885 } 886 887 for (q = 0; q < fep->num_tx_queues; q++) { 888 /* ...and the same for transmit */ 889 txq = fep->tx_queue[q]; 890 bdp = txq->bd.base; 891 txq->bd.cur = bdp; 892 893 for (i = 0; i < txq->bd.ring_size; i++) { 894 /* Initialize the BD for every fragment in the page. */ 895 bdp->cbd_sc = cpu_to_fec16(0); 896 if (bdp->cbd_bufaddr && 897 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 898 dma_unmap_single(&fep->pdev->dev, 899 fec32_to_cpu(bdp->cbd_bufaddr), 900 fec16_to_cpu(bdp->cbd_datlen), 901 DMA_TO_DEVICE); 902 if (txq->tx_skbuff[i]) { 903 dev_kfree_skb_any(txq->tx_skbuff[i]); 904 txq->tx_skbuff[i] = NULL; 905 } 906 bdp->cbd_bufaddr = cpu_to_fec32(0); 907 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 908 } 909 910 /* Set the last buffer to wrap */ 911 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 912 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 913 txq->dirty_tx = bdp; 914 } 915 } 916 917 static void fec_enet_active_rxring(struct net_device *ndev) 918 { 919 struct fec_enet_private *fep = netdev_priv(ndev); 920 int i; 921 922 for (i = 0; i < fep->num_rx_queues; i++) 923 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 924 } 925 926 static void fec_enet_enable_ring(struct net_device *ndev) 927 { 928 struct fec_enet_private *fep = netdev_priv(ndev); 929 struct fec_enet_priv_tx_q *txq; 930 struct fec_enet_priv_rx_q *rxq; 931 int i; 932 933 for (i = 0; i < fep->num_rx_queues; i++) { 934 rxq = fep->rx_queue[i]; 935 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 936 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 937 938 /* enable DMA1/2 */ 939 if (i) 940 writel(RCMR_MATCHEN | RCMR_CMP(i), 941 fep->hwp + FEC_RCMR(i)); 942 } 943 944 for (i = 0; i < fep->num_tx_queues; i++) { 945 txq = fep->tx_queue[i]; 946 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 947 948 /* enable DMA1/2 */ 949 if (i) 950 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 951 fep->hwp + FEC_DMA_CFG(i)); 952 } 953 } 954 955 static void fec_enet_reset_skb(struct net_device *ndev) 956 { 957 struct fec_enet_private *fep = netdev_priv(ndev); 958 struct fec_enet_priv_tx_q *txq; 959 int i, j; 960 961 for (i = 0; i < fep->num_tx_queues; i++) { 962 txq = fep->tx_queue[i]; 963 964 for (j = 0; j < txq->bd.ring_size; j++) { 965 if (txq->tx_skbuff[j]) { 966 dev_kfree_skb_any(txq->tx_skbuff[j]); 967 txq->tx_skbuff[j] = NULL; 968 } 969 } 970 } 971 } 972 973 /* 974 * This function is called to start or restart the FEC during a link 975 * change, transmit timeout, or to reconfigure the FEC. The network 976 * packet processing for this device must be stopped before this call. 977 */ 978 static void 979 fec_restart(struct net_device *ndev) 980 { 981 struct fec_enet_private *fep = netdev_priv(ndev); 982 u32 temp_mac[2]; 983 u32 rcntl = OPT_FRAME_SIZE | 0x04; 984 u32 ecntl = 0x2; /* ETHEREN */ 985 986 /* Whack a reset. We should wait for this. 987 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 988 * instead of reset MAC itself. 989 */ 990 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 991 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 992 writel(0, fep->hwp + FEC_ECNTRL); 993 } else { 994 writel(1, fep->hwp + FEC_ECNTRL); 995 udelay(10); 996 } 997 998 /* 999 * enet-mac reset will reset mac address registers too, 1000 * so need to reconfigure it. 1001 */ 1002 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 1003 writel((__force u32)cpu_to_be32(temp_mac[0]), 1004 fep->hwp + FEC_ADDR_LOW); 1005 writel((__force u32)cpu_to_be32(temp_mac[1]), 1006 fep->hwp + FEC_ADDR_HIGH); 1007 1008 /* Clear any outstanding interrupt, except MDIO. */ 1009 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1010 1011 fec_enet_bd_init(ndev); 1012 1013 fec_enet_enable_ring(ndev); 1014 1015 /* Reset tx SKB buffers. */ 1016 fec_enet_reset_skb(ndev); 1017 1018 /* Enable MII mode */ 1019 if (fep->full_duplex == DUPLEX_FULL) { 1020 /* FD enable */ 1021 writel(0x04, fep->hwp + FEC_X_CNTRL); 1022 } else { 1023 /* No Rcv on Xmit */ 1024 rcntl |= 0x02; 1025 writel(0x0, fep->hwp + FEC_X_CNTRL); 1026 } 1027 1028 /* Set MII speed */ 1029 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1030 1031 #if !defined(CONFIG_M5272) 1032 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1033 u32 val = readl(fep->hwp + FEC_RACC); 1034 1035 /* align IP header */ 1036 val |= FEC_RACC_SHIFT16; 1037 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1038 /* set RX checksum */ 1039 val |= FEC_RACC_OPTIONS; 1040 else 1041 val &= ~FEC_RACC_OPTIONS; 1042 writel(val, fep->hwp + FEC_RACC); 1043 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1044 } 1045 #endif 1046 1047 /* 1048 * The phy interface and speed need to get configured 1049 * differently on enet-mac. 1050 */ 1051 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1052 /* Enable flow control and length check */ 1053 rcntl |= 0x40000000 | 0x00000020; 1054 1055 /* RGMII, RMII or MII */ 1056 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1057 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1058 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1059 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1060 rcntl |= (1 << 6); 1061 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1062 rcntl |= (1 << 8); 1063 else 1064 rcntl &= ~(1 << 8); 1065 1066 /* 1G, 100M or 10M */ 1067 if (ndev->phydev) { 1068 if (ndev->phydev->speed == SPEED_1000) 1069 ecntl |= (1 << 5); 1070 else if (ndev->phydev->speed == SPEED_100) 1071 rcntl &= ~(1 << 9); 1072 else 1073 rcntl |= (1 << 9); 1074 } 1075 } else { 1076 #ifdef FEC_MIIGSK_ENR 1077 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1078 u32 cfgr; 1079 /* disable the gasket and wait */ 1080 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1081 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1082 udelay(1); 1083 1084 /* 1085 * configure the gasket: 1086 * RMII, 50 MHz, no loopback, no echo 1087 * MII, 25 MHz, no loopback, no echo 1088 */ 1089 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1090 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1091 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1092 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1093 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1094 1095 /* re-enable the gasket */ 1096 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1097 } 1098 #endif 1099 } 1100 1101 #if !defined(CONFIG_M5272) 1102 /* enable pause frame*/ 1103 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1104 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1105 ndev->phydev && ndev->phydev->pause)) { 1106 rcntl |= FEC_ENET_FCE; 1107 1108 /* set FIFO threshold parameter to reduce overrun */ 1109 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1110 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1111 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1112 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1113 1114 /* OPD */ 1115 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1116 } else { 1117 rcntl &= ~FEC_ENET_FCE; 1118 } 1119 #endif /* !defined(CONFIG_M5272) */ 1120 1121 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1122 1123 /* Setup multicast filter. */ 1124 set_multicast_list(ndev); 1125 #ifndef CONFIG_M5272 1126 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1127 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1128 #endif 1129 1130 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1131 /* enable ENET endian swap */ 1132 ecntl |= (1 << 8); 1133 /* enable ENET store and forward mode */ 1134 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1135 } 1136 1137 if (fep->bufdesc_ex) 1138 ecntl |= (1 << 4); 1139 1140 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1141 fep->rgmii_txc_dly) 1142 ecntl |= FEC_ENET_TXC_DLY; 1143 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1144 fep->rgmii_rxc_dly) 1145 ecntl |= FEC_ENET_RXC_DLY; 1146 1147 #ifndef CONFIG_M5272 1148 /* Enable the MIB statistic event counters */ 1149 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1150 #endif 1151 1152 /* And last, enable the transmit and receive processing */ 1153 writel(ecntl, fep->hwp + FEC_ECNTRL); 1154 fec_enet_active_rxring(ndev); 1155 1156 if (fep->bufdesc_ex) 1157 fec_ptp_start_cyclecounter(ndev); 1158 1159 /* Enable interrupts we wish to service */ 1160 if (fep->link) 1161 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1162 else 1163 writel(0, fep->hwp + FEC_IMASK); 1164 1165 /* Init the interrupt coalescing */ 1166 fec_enet_itr_coal_init(ndev); 1167 1168 } 1169 1170 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1171 { 1172 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1173 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1174 1175 if (stop_gpr->gpr) { 1176 if (enabled) 1177 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1178 BIT(stop_gpr->bit), 1179 BIT(stop_gpr->bit)); 1180 else 1181 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1182 BIT(stop_gpr->bit), 0); 1183 } else if (pdata && pdata->sleep_mode_enable) { 1184 pdata->sleep_mode_enable(enabled); 1185 } 1186 } 1187 1188 static void 1189 fec_stop(struct net_device *ndev) 1190 { 1191 struct fec_enet_private *fep = netdev_priv(ndev); 1192 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1193 u32 val; 1194 1195 /* We cannot expect a graceful transmit stop without link !!! */ 1196 if (fep->link) { 1197 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1198 udelay(10); 1199 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1200 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1201 } 1202 1203 /* Whack a reset. We should wait for this. 1204 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1205 * instead of reset MAC itself. 1206 */ 1207 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1208 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 1209 writel(0, fep->hwp + FEC_ECNTRL); 1210 } else { 1211 writel(1, fep->hwp + FEC_ECNTRL); 1212 udelay(10); 1213 } 1214 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1215 } else { 1216 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1217 val = readl(fep->hwp + FEC_ECNTRL); 1218 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1219 writel(val, fep->hwp + FEC_ECNTRL); 1220 fec_enet_stop_mode(fep, true); 1221 } 1222 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1223 1224 /* We have to keep ENET enabled to have MII interrupt stay working */ 1225 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1226 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1227 writel(2, fep->hwp + FEC_ECNTRL); 1228 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1229 } 1230 } 1231 1232 1233 static void 1234 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1235 { 1236 struct fec_enet_private *fep = netdev_priv(ndev); 1237 1238 fec_dump(ndev); 1239 1240 ndev->stats.tx_errors++; 1241 1242 schedule_work(&fep->tx_timeout_work); 1243 } 1244 1245 static void fec_enet_timeout_work(struct work_struct *work) 1246 { 1247 struct fec_enet_private *fep = 1248 container_of(work, struct fec_enet_private, tx_timeout_work); 1249 struct net_device *ndev = fep->netdev; 1250 1251 rtnl_lock(); 1252 if (netif_device_present(ndev) || netif_running(ndev)) { 1253 napi_disable(&fep->napi); 1254 netif_tx_lock_bh(ndev); 1255 fec_restart(ndev); 1256 netif_tx_wake_all_queues(ndev); 1257 netif_tx_unlock_bh(ndev); 1258 napi_enable(&fep->napi); 1259 } 1260 rtnl_unlock(); 1261 } 1262 1263 static void 1264 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1265 struct skb_shared_hwtstamps *hwtstamps) 1266 { 1267 unsigned long flags; 1268 u64 ns; 1269 1270 spin_lock_irqsave(&fep->tmreg_lock, flags); 1271 ns = timecounter_cyc2time(&fep->tc, ts); 1272 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1273 1274 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1275 hwtstamps->hwtstamp = ns_to_ktime(ns); 1276 } 1277 1278 static void 1279 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1280 { 1281 struct fec_enet_private *fep; 1282 struct bufdesc *bdp; 1283 unsigned short status; 1284 struct sk_buff *skb; 1285 struct fec_enet_priv_tx_q *txq; 1286 struct netdev_queue *nq; 1287 int index = 0; 1288 int entries_free; 1289 1290 fep = netdev_priv(ndev); 1291 1292 txq = fep->tx_queue[queue_id]; 1293 /* get next bdp of dirty_tx */ 1294 nq = netdev_get_tx_queue(ndev, queue_id); 1295 bdp = txq->dirty_tx; 1296 1297 /* get next bdp of dirty_tx */ 1298 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1299 1300 while (bdp != READ_ONCE(txq->bd.cur)) { 1301 /* Order the load of bd.cur and cbd_sc */ 1302 rmb(); 1303 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1304 if (status & BD_ENET_TX_READY) 1305 break; 1306 1307 index = fec_enet_get_bd_index(bdp, &txq->bd); 1308 1309 skb = txq->tx_skbuff[index]; 1310 txq->tx_skbuff[index] = NULL; 1311 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1312 dma_unmap_single(&fep->pdev->dev, 1313 fec32_to_cpu(bdp->cbd_bufaddr), 1314 fec16_to_cpu(bdp->cbd_datlen), 1315 DMA_TO_DEVICE); 1316 bdp->cbd_bufaddr = cpu_to_fec32(0); 1317 if (!skb) 1318 goto skb_done; 1319 1320 /* Check for errors. */ 1321 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1322 BD_ENET_TX_RL | BD_ENET_TX_UN | 1323 BD_ENET_TX_CSL)) { 1324 ndev->stats.tx_errors++; 1325 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1326 ndev->stats.tx_heartbeat_errors++; 1327 if (status & BD_ENET_TX_LC) /* Late collision */ 1328 ndev->stats.tx_window_errors++; 1329 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1330 ndev->stats.tx_aborted_errors++; 1331 if (status & BD_ENET_TX_UN) /* Underrun */ 1332 ndev->stats.tx_fifo_errors++; 1333 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1334 ndev->stats.tx_carrier_errors++; 1335 } else { 1336 ndev->stats.tx_packets++; 1337 ndev->stats.tx_bytes += skb->len; 1338 } 1339 1340 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1341 * are to time stamp the packet, so we still need to check time 1342 * stamping enabled flag. 1343 */ 1344 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1345 fep->hwts_tx_en) && 1346 fep->bufdesc_ex) { 1347 struct skb_shared_hwtstamps shhwtstamps; 1348 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1349 1350 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1351 skb_tstamp_tx(skb, &shhwtstamps); 1352 } 1353 1354 /* Deferred means some collisions occurred during transmit, 1355 * but we eventually sent the packet OK. 1356 */ 1357 if (status & BD_ENET_TX_DEF) 1358 ndev->stats.collisions++; 1359 1360 /* Free the sk buffer associated with this last transmit */ 1361 dev_kfree_skb_any(skb); 1362 skb_done: 1363 /* Make sure the update to bdp and tx_skbuff are performed 1364 * before dirty_tx 1365 */ 1366 wmb(); 1367 txq->dirty_tx = bdp; 1368 1369 /* Update pointer to next buffer descriptor to be transmitted */ 1370 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1371 1372 /* Since we have freed up a buffer, the ring is no longer full 1373 */ 1374 if (netif_tx_queue_stopped(nq)) { 1375 entries_free = fec_enet_get_free_txdesc_num(txq); 1376 if (entries_free >= txq->tx_wake_threshold) 1377 netif_tx_wake_queue(nq); 1378 } 1379 } 1380 1381 /* ERR006358: Keep the transmitter going */ 1382 if (bdp != txq->bd.cur && 1383 readl(txq->bd.reg_desc_active) == 0) 1384 writel(0, txq->bd.reg_desc_active); 1385 } 1386 1387 static void fec_enet_tx(struct net_device *ndev) 1388 { 1389 struct fec_enet_private *fep = netdev_priv(ndev); 1390 int i; 1391 1392 /* Make sure that AVB queues are processed first. */ 1393 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1394 fec_enet_tx_queue(ndev, i); 1395 } 1396 1397 static int 1398 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1399 { 1400 struct fec_enet_private *fep = netdev_priv(ndev); 1401 int off; 1402 1403 off = ((unsigned long)skb->data) & fep->rx_align; 1404 if (off) 1405 skb_reserve(skb, fep->rx_align + 1 - off); 1406 1407 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1408 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1409 if (net_ratelimit()) 1410 netdev_err(ndev, "Rx DMA memory map failed\n"); 1411 return -ENOMEM; 1412 } 1413 1414 return 0; 1415 } 1416 1417 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1418 struct bufdesc *bdp, u32 length, bool swap) 1419 { 1420 struct fec_enet_private *fep = netdev_priv(ndev); 1421 struct sk_buff *new_skb; 1422 1423 if (length > fep->rx_copybreak) 1424 return false; 1425 1426 new_skb = netdev_alloc_skb(ndev, length); 1427 if (!new_skb) 1428 return false; 1429 1430 dma_sync_single_for_cpu(&fep->pdev->dev, 1431 fec32_to_cpu(bdp->cbd_bufaddr), 1432 FEC_ENET_RX_FRSIZE - fep->rx_align, 1433 DMA_FROM_DEVICE); 1434 if (!swap) 1435 memcpy(new_skb->data, (*skb)->data, length); 1436 else 1437 swap_buffer2(new_skb->data, (*skb)->data, length); 1438 *skb = new_skb; 1439 1440 return true; 1441 } 1442 1443 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1444 * When we update through the ring, if the next incoming buffer has 1445 * not been given to the system, we just set the empty indicator, 1446 * effectively tossing the packet. 1447 */ 1448 static int 1449 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1450 { 1451 struct fec_enet_private *fep = netdev_priv(ndev); 1452 struct fec_enet_priv_rx_q *rxq; 1453 struct bufdesc *bdp; 1454 unsigned short status; 1455 struct sk_buff *skb_new = NULL; 1456 struct sk_buff *skb; 1457 ushort pkt_len; 1458 __u8 *data; 1459 int pkt_received = 0; 1460 struct bufdesc_ex *ebdp = NULL; 1461 bool vlan_packet_rcvd = false; 1462 u16 vlan_tag; 1463 int index = 0; 1464 bool is_copybreak; 1465 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1466 1467 #ifdef CONFIG_M532x 1468 flush_cache_all(); 1469 #endif 1470 rxq = fep->rx_queue[queue_id]; 1471 1472 /* First, grab all of the stats for the incoming packet. 1473 * These get messed up if we get called due to a busy condition. 1474 */ 1475 bdp = rxq->bd.cur; 1476 1477 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1478 1479 if (pkt_received >= budget) 1480 break; 1481 pkt_received++; 1482 1483 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); 1484 1485 /* Check for errors. */ 1486 status ^= BD_ENET_RX_LAST; 1487 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1488 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1489 BD_ENET_RX_CL)) { 1490 ndev->stats.rx_errors++; 1491 if (status & BD_ENET_RX_OV) { 1492 /* FIFO overrun */ 1493 ndev->stats.rx_fifo_errors++; 1494 goto rx_processing_done; 1495 } 1496 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1497 | BD_ENET_RX_LAST)) { 1498 /* Frame too long or too short. */ 1499 ndev->stats.rx_length_errors++; 1500 if (status & BD_ENET_RX_LAST) 1501 netdev_err(ndev, "rcv is not +last\n"); 1502 } 1503 if (status & BD_ENET_RX_CR) /* CRC Error */ 1504 ndev->stats.rx_crc_errors++; 1505 /* Report late collisions as a frame error. */ 1506 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1507 ndev->stats.rx_frame_errors++; 1508 goto rx_processing_done; 1509 } 1510 1511 /* Process the incoming frame. */ 1512 ndev->stats.rx_packets++; 1513 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1514 ndev->stats.rx_bytes += pkt_len; 1515 1516 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1517 skb = rxq->rx_skbuff[index]; 1518 1519 /* The packet length includes FCS, but we don't want to 1520 * include that when passing upstream as it messes up 1521 * bridging applications. 1522 */ 1523 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1524 need_swap); 1525 if (!is_copybreak) { 1526 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1527 if (unlikely(!skb_new)) { 1528 ndev->stats.rx_dropped++; 1529 goto rx_processing_done; 1530 } 1531 dma_unmap_single(&fep->pdev->dev, 1532 fec32_to_cpu(bdp->cbd_bufaddr), 1533 FEC_ENET_RX_FRSIZE - fep->rx_align, 1534 DMA_FROM_DEVICE); 1535 } 1536 1537 prefetch(skb->data - NET_IP_ALIGN); 1538 skb_put(skb, pkt_len - 4); 1539 data = skb->data; 1540 1541 if (!is_copybreak && need_swap) 1542 swap_buffer(data, pkt_len); 1543 1544 #if !defined(CONFIG_M5272) 1545 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1546 data = skb_pull_inline(skb, 2); 1547 #endif 1548 1549 /* Extract the enhanced buffer descriptor */ 1550 ebdp = NULL; 1551 if (fep->bufdesc_ex) 1552 ebdp = (struct bufdesc_ex *)bdp; 1553 1554 /* If this is a VLAN packet remove the VLAN Tag */ 1555 vlan_packet_rcvd = false; 1556 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1557 fep->bufdesc_ex && 1558 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1559 /* Push and remove the vlan tag */ 1560 struct vlan_hdr *vlan_header = 1561 (struct vlan_hdr *) (data + ETH_HLEN); 1562 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1563 1564 vlan_packet_rcvd = true; 1565 1566 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1567 skb_pull(skb, VLAN_HLEN); 1568 } 1569 1570 skb->protocol = eth_type_trans(skb, ndev); 1571 1572 /* Get receive timestamp from the skb */ 1573 if (fep->hwts_rx_en && fep->bufdesc_ex) 1574 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1575 skb_hwtstamps(skb)); 1576 1577 if (fep->bufdesc_ex && 1578 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1579 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1580 /* don't check it */ 1581 skb->ip_summed = CHECKSUM_UNNECESSARY; 1582 } else { 1583 skb_checksum_none_assert(skb); 1584 } 1585 } 1586 1587 /* Handle received VLAN packets */ 1588 if (vlan_packet_rcvd) 1589 __vlan_hwaccel_put_tag(skb, 1590 htons(ETH_P_8021Q), 1591 vlan_tag); 1592 1593 skb_record_rx_queue(skb, queue_id); 1594 napi_gro_receive(&fep->napi, skb); 1595 1596 if (is_copybreak) { 1597 dma_sync_single_for_device(&fep->pdev->dev, 1598 fec32_to_cpu(bdp->cbd_bufaddr), 1599 FEC_ENET_RX_FRSIZE - fep->rx_align, 1600 DMA_FROM_DEVICE); 1601 } else { 1602 rxq->rx_skbuff[index] = skb_new; 1603 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1604 } 1605 1606 rx_processing_done: 1607 /* Clear the status flags for this buffer */ 1608 status &= ~BD_ENET_RX_STATS; 1609 1610 /* Mark the buffer empty */ 1611 status |= BD_ENET_RX_EMPTY; 1612 1613 if (fep->bufdesc_ex) { 1614 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1615 1616 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1617 ebdp->cbd_prot = 0; 1618 ebdp->cbd_bdu = 0; 1619 } 1620 /* Make sure the updates to rest of the descriptor are 1621 * performed before transferring ownership. 1622 */ 1623 wmb(); 1624 bdp->cbd_sc = cpu_to_fec16(status); 1625 1626 /* Update BD pointer to next entry */ 1627 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1628 1629 /* Doing this here will keep the FEC running while we process 1630 * incoming frames. On a heavily loaded network, we should be 1631 * able to keep up at the expense of system resources. 1632 */ 1633 writel(0, rxq->bd.reg_desc_active); 1634 } 1635 rxq->bd.cur = bdp; 1636 return pkt_received; 1637 } 1638 1639 static int fec_enet_rx(struct net_device *ndev, int budget) 1640 { 1641 struct fec_enet_private *fep = netdev_priv(ndev); 1642 int i, done = 0; 1643 1644 /* Make sure that AVB queues are processed first. */ 1645 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1646 done += fec_enet_rx_queue(ndev, budget - done, i); 1647 1648 return done; 1649 } 1650 1651 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1652 { 1653 uint int_events; 1654 1655 int_events = readl(fep->hwp + FEC_IEVENT); 1656 1657 /* Don't clear MDIO events, we poll for those */ 1658 int_events &= ~FEC_ENET_MII; 1659 1660 writel(int_events, fep->hwp + FEC_IEVENT); 1661 1662 return int_events != 0; 1663 } 1664 1665 static irqreturn_t 1666 fec_enet_interrupt(int irq, void *dev_id) 1667 { 1668 struct net_device *ndev = dev_id; 1669 struct fec_enet_private *fep = netdev_priv(ndev); 1670 irqreturn_t ret = IRQ_NONE; 1671 1672 if (fec_enet_collect_events(fep) && fep->link) { 1673 ret = IRQ_HANDLED; 1674 1675 if (napi_schedule_prep(&fep->napi)) { 1676 /* Disable interrupts */ 1677 writel(0, fep->hwp + FEC_IMASK); 1678 __napi_schedule(&fep->napi); 1679 } 1680 } 1681 1682 return ret; 1683 } 1684 1685 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1686 { 1687 struct net_device *ndev = napi->dev; 1688 struct fec_enet_private *fep = netdev_priv(ndev); 1689 int done = 0; 1690 1691 do { 1692 done += fec_enet_rx(ndev, budget - done); 1693 fec_enet_tx(ndev); 1694 } while ((done < budget) && fec_enet_collect_events(fep)); 1695 1696 if (done < budget) { 1697 napi_complete_done(napi, done); 1698 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1699 } 1700 1701 return done; 1702 } 1703 1704 /* ------------------------------------------------------------------------- */ 1705 static int fec_get_mac(struct net_device *ndev) 1706 { 1707 struct fec_enet_private *fep = netdev_priv(ndev); 1708 unsigned char *iap, tmpaddr[ETH_ALEN]; 1709 int ret; 1710 1711 /* 1712 * try to get mac address in following order: 1713 * 1714 * 1) module parameter via kernel command line in form 1715 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1716 */ 1717 iap = macaddr; 1718 1719 /* 1720 * 2) from device tree data 1721 */ 1722 if (!is_valid_ether_addr(iap)) { 1723 struct device_node *np = fep->pdev->dev.of_node; 1724 if (np) { 1725 ret = of_get_mac_address(np, tmpaddr); 1726 if (!ret) 1727 iap = tmpaddr; 1728 else if (ret == -EPROBE_DEFER) 1729 return ret; 1730 } 1731 } 1732 1733 /* 1734 * 3) from flash or fuse (via platform data) 1735 */ 1736 if (!is_valid_ether_addr(iap)) { 1737 #ifdef CONFIG_M5272 1738 if (FEC_FLASHMAC) 1739 iap = (unsigned char *)FEC_FLASHMAC; 1740 #else 1741 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1742 1743 if (pdata) 1744 iap = (unsigned char *)&pdata->mac; 1745 #endif 1746 } 1747 1748 /* 1749 * 4) FEC mac registers set by bootloader 1750 */ 1751 if (!is_valid_ether_addr(iap)) { 1752 *((__be32 *) &tmpaddr[0]) = 1753 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1754 *((__be16 *) &tmpaddr[4]) = 1755 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1756 iap = &tmpaddr[0]; 1757 } 1758 1759 /* 1760 * 5) random mac address 1761 */ 1762 if (!is_valid_ether_addr(iap)) { 1763 /* Report it and use a random ethernet address instead */ 1764 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1765 eth_hw_addr_random(ndev); 1766 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1767 ndev->dev_addr); 1768 return 0; 1769 } 1770 1771 /* Adjust MAC if using macaddr */ 1772 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); 1773 1774 return 0; 1775 } 1776 1777 /* ------------------------------------------------------------------------- */ 1778 1779 /* 1780 * Phy section 1781 */ 1782 static void fec_enet_adjust_link(struct net_device *ndev) 1783 { 1784 struct fec_enet_private *fep = netdev_priv(ndev); 1785 struct phy_device *phy_dev = ndev->phydev; 1786 int status_change = 0; 1787 1788 /* 1789 * If the netdev is down, or is going down, we're not interested 1790 * in link state events, so just mark our idea of the link as down 1791 * and ignore the event. 1792 */ 1793 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1794 fep->link = 0; 1795 } else if (phy_dev->link) { 1796 if (!fep->link) { 1797 fep->link = phy_dev->link; 1798 status_change = 1; 1799 } 1800 1801 if (fep->full_duplex != phy_dev->duplex) { 1802 fep->full_duplex = phy_dev->duplex; 1803 status_change = 1; 1804 } 1805 1806 if (phy_dev->speed != fep->speed) { 1807 fep->speed = phy_dev->speed; 1808 status_change = 1; 1809 } 1810 1811 /* if any of the above changed restart the FEC */ 1812 if (status_change) { 1813 napi_disable(&fep->napi); 1814 netif_tx_lock_bh(ndev); 1815 fec_restart(ndev); 1816 netif_tx_wake_all_queues(ndev); 1817 netif_tx_unlock_bh(ndev); 1818 napi_enable(&fep->napi); 1819 } 1820 } else { 1821 if (fep->link) { 1822 napi_disable(&fep->napi); 1823 netif_tx_lock_bh(ndev); 1824 fec_stop(ndev); 1825 netif_tx_unlock_bh(ndev); 1826 napi_enable(&fep->napi); 1827 fep->link = phy_dev->link; 1828 status_change = 1; 1829 } 1830 } 1831 1832 if (status_change) 1833 phy_print_status(phy_dev); 1834 } 1835 1836 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 1837 { 1838 uint ievent; 1839 int ret; 1840 1841 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 1842 ievent & FEC_ENET_MII, 2, 30000); 1843 1844 if (!ret) 1845 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 1846 1847 return ret; 1848 } 1849 1850 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1851 { 1852 struct fec_enet_private *fep = bus->priv; 1853 struct device *dev = &fep->pdev->dev; 1854 int ret = 0, frame_start, frame_addr, frame_op; 1855 bool is_c45 = !!(regnum & MII_ADDR_C45); 1856 1857 ret = pm_runtime_resume_and_get(dev); 1858 if (ret < 0) 1859 return ret; 1860 1861 if (is_c45) { 1862 frame_start = FEC_MMFR_ST_C45; 1863 1864 /* write address */ 1865 frame_addr = (regnum >> 16); 1866 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1867 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1868 FEC_MMFR_TA | (regnum & 0xFFFF), 1869 fep->hwp + FEC_MII_DATA); 1870 1871 /* wait for end of transfer */ 1872 ret = fec_enet_mdio_wait(fep); 1873 if (ret) { 1874 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1875 goto out; 1876 } 1877 1878 frame_op = FEC_MMFR_OP_READ_C45; 1879 1880 } else { 1881 /* C22 read */ 1882 frame_op = FEC_MMFR_OP_READ; 1883 frame_start = FEC_MMFR_ST; 1884 frame_addr = regnum; 1885 } 1886 1887 /* start a read op */ 1888 writel(frame_start | frame_op | 1889 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1890 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1891 1892 /* wait for end of transfer */ 1893 ret = fec_enet_mdio_wait(fep); 1894 if (ret) { 1895 netdev_err(fep->netdev, "MDIO read timeout\n"); 1896 goto out; 1897 } 1898 1899 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1900 1901 out: 1902 pm_runtime_mark_last_busy(dev); 1903 pm_runtime_put_autosuspend(dev); 1904 1905 return ret; 1906 } 1907 1908 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1909 u16 value) 1910 { 1911 struct fec_enet_private *fep = bus->priv; 1912 struct device *dev = &fep->pdev->dev; 1913 int ret, frame_start, frame_addr; 1914 bool is_c45 = !!(regnum & MII_ADDR_C45); 1915 1916 ret = pm_runtime_resume_and_get(dev); 1917 if (ret < 0) 1918 return ret; 1919 1920 if (is_c45) { 1921 frame_start = FEC_MMFR_ST_C45; 1922 1923 /* write address */ 1924 frame_addr = (regnum >> 16); 1925 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1926 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1927 FEC_MMFR_TA | (regnum & 0xFFFF), 1928 fep->hwp + FEC_MII_DATA); 1929 1930 /* wait for end of transfer */ 1931 ret = fec_enet_mdio_wait(fep); 1932 if (ret) { 1933 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1934 goto out; 1935 } 1936 } else { 1937 /* C22 write */ 1938 frame_start = FEC_MMFR_ST; 1939 frame_addr = regnum; 1940 } 1941 1942 /* start a write op */ 1943 writel(frame_start | FEC_MMFR_OP_WRITE | 1944 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1945 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1946 fep->hwp + FEC_MII_DATA); 1947 1948 /* wait for end of transfer */ 1949 ret = fec_enet_mdio_wait(fep); 1950 if (ret) 1951 netdev_err(fep->netdev, "MDIO write timeout\n"); 1952 1953 out: 1954 pm_runtime_mark_last_busy(dev); 1955 pm_runtime_put_autosuspend(dev); 1956 1957 return ret; 1958 } 1959 1960 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 1961 { 1962 struct fec_enet_private *fep = netdev_priv(ndev); 1963 struct phy_device *phy_dev = ndev->phydev; 1964 1965 if (phy_dev) { 1966 phy_reset_after_clk_enable(phy_dev); 1967 } else if (fep->phy_node) { 1968 /* 1969 * If the PHY still is not bound to the MAC, but there is 1970 * OF PHY node and a matching PHY device instance already, 1971 * use the OF PHY node to obtain the PHY device instance, 1972 * and then use that PHY device instance when triggering 1973 * the PHY reset. 1974 */ 1975 phy_dev = of_phy_find_device(fep->phy_node); 1976 phy_reset_after_clk_enable(phy_dev); 1977 put_device(&phy_dev->mdio.dev); 1978 } 1979 } 1980 1981 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1982 { 1983 struct fec_enet_private *fep = netdev_priv(ndev); 1984 int ret; 1985 1986 if (enable) { 1987 ret = clk_prepare_enable(fep->clk_enet_out); 1988 if (ret) 1989 return ret; 1990 1991 if (fep->clk_ptp) { 1992 mutex_lock(&fep->ptp_clk_mutex); 1993 ret = clk_prepare_enable(fep->clk_ptp); 1994 if (ret) { 1995 mutex_unlock(&fep->ptp_clk_mutex); 1996 goto failed_clk_ptp; 1997 } else { 1998 fep->ptp_clk_on = true; 1999 } 2000 mutex_unlock(&fep->ptp_clk_mutex); 2001 } 2002 2003 ret = clk_prepare_enable(fep->clk_ref); 2004 if (ret) 2005 goto failed_clk_ref; 2006 2007 ret = clk_prepare_enable(fep->clk_2x_txclk); 2008 if (ret) 2009 goto failed_clk_2x_txclk; 2010 2011 fec_enet_phy_reset_after_clk_enable(ndev); 2012 } else { 2013 clk_disable_unprepare(fep->clk_enet_out); 2014 if (fep->clk_ptp) { 2015 mutex_lock(&fep->ptp_clk_mutex); 2016 clk_disable_unprepare(fep->clk_ptp); 2017 fep->ptp_clk_on = false; 2018 mutex_unlock(&fep->ptp_clk_mutex); 2019 } 2020 clk_disable_unprepare(fep->clk_ref); 2021 clk_disable_unprepare(fep->clk_2x_txclk); 2022 } 2023 2024 return 0; 2025 2026 failed_clk_2x_txclk: 2027 if (fep->clk_ref) 2028 clk_disable_unprepare(fep->clk_ref); 2029 failed_clk_ref: 2030 if (fep->clk_ptp) { 2031 mutex_lock(&fep->ptp_clk_mutex); 2032 clk_disable_unprepare(fep->clk_ptp); 2033 fep->ptp_clk_on = false; 2034 mutex_unlock(&fep->ptp_clk_mutex); 2035 } 2036 failed_clk_ptp: 2037 clk_disable_unprepare(fep->clk_enet_out); 2038 2039 return ret; 2040 } 2041 2042 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2043 struct device_node *np) 2044 { 2045 u32 rgmii_tx_delay, rgmii_rx_delay; 2046 2047 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2048 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2049 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2050 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2051 return -EINVAL; 2052 } else if (rgmii_tx_delay == 2000) { 2053 fep->rgmii_txc_dly = true; 2054 } 2055 } 2056 2057 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2058 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2059 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2060 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2061 return -EINVAL; 2062 } else if (rgmii_rx_delay == 2000) { 2063 fep->rgmii_rxc_dly = true; 2064 } 2065 } 2066 2067 return 0; 2068 } 2069 2070 static int fec_enet_mii_probe(struct net_device *ndev) 2071 { 2072 struct fec_enet_private *fep = netdev_priv(ndev); 2073 struct phy_device *phy_dev = NULL; 2074 char mdio_bus_id[MII_BUS_ID_SIZE]; 2075 char phy_name[MII_BUS_ID_SIZE + 3]; 2076 int phy_id; 2077 int dev_id = fep->dev_id; 2078 2079 if (fep->phy_node) { 2080 phy_dev = of_phy_connect(ndev, fep->phy_node, 2081 &fec_enet_adjust_link, 0, 2082 fep->phy_interface); 2083 if (!phy_dev) { 2084 netdev_err(ndev, "Unable to connect to phy\n"); 2085 return -ENODEV; 2086 } 2087 } else { 2088 /* check for attached phy */ 2089 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2090 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2091 continue; 2092 if (dev_id--) 2093 continue; 2094 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2095 break; 2096 } 2097 2098 if (phy_id >= PHY_MAX_ADDR) { 2099 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2100 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2101 phy_id = 0; 2102 } 2103 2104 snprintf(phy_name, sizeof(phy_name), 2105 PHY_ID_FMT, mdio_bus_id, phy_id); 2106 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2107 fep->phy_interface); 2108 } 2109 2110 if (IS_ERR(phy_dev)) { 2111 netdev_err(ndev, "could not attach to PHY\n"); 2112 return PTR_ERR(phy_dev); 2113 } 2114 2115 /* mask with MAC supported features */ 2116 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2117 phy_set_max_speed(phy_dev, 1000); 2118 phy_remove_link_mode(phy_dev, 2119 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2120 #if !defined(CONFIG_M5272) 2121 phy_support_sym_pause(phy_dev); 2122 #endif 2123 } 2124 else 2125 phy_set_max_speed(phy_dev, 100); 2126 2127 fep->link = 0; 2128 fep->full_duplex = 0; 2129 2130 phy_dev->mac_managed_pm = 1; 2131 2132 phy_attached_info(phy_dev); 2133 2134 return 0; 2135 } 2136 2137 static int fec_enet_mii_init(struct platform_device *pdev) 2138 { 2139 static struct mii_bus *fec0_mii_bus; 2140 struct net_device *ndev = platform_get_drvdata(pdev); 2141 struct fec_enet_private *fep = netdev_priv(ndev); 2142 bool suppress_preamble = false; 2143 struct device_node *node; 2144 int err = -ENXIO; 2145 u32 mii_speed, holdtime; 2146 u32 bus_freq; 2147 2148 /* 2149 * The i.MX28 dual fec interfaces are not equal. 2150 * Here are the differences: 2151 * 2152 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2153 * - fec0 acts as the 1588 time master while fec1 is slave 2154 * - external phys can only be configured by fec0 2155 * 2156 * That is to say fec1 can not work independently. It only works 2157 * when fec0 is working. The reason behind this design is that the 2158 * second interface is added primarily for Switch mode. 2159 * 2160 * Because of the last point above, both phys are attached on fec0 2161 * mdio interface in board design, and need to be configured by 2162 * fec0 mii_bus. 2163 */ 2164 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2165 /* fec1 uses fec0 mii_bus */ 2166 if (mii_cnt && fec0_mii_bus) { 2167 fep->mii_bus = fec0_mii_bus; 2168 mii_cnt++; 2169 return 0; 2170 } 2171 return -ENOENT; 2172 } 2173 2174 bus_freq = 2500000; /* 2.5MHz by default */ 2175 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2176 if (node) { 2177 of_property_read_u32(node, "clock-frequency", &bus_freq); 2178 suppress_preamble = of_property_read_bool(node, 2179 "suppress-preamble"); 2180 } 2181 2182 /* 2183 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2184 * 2185 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2186 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2187 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2188 * document. 2189 */ 2190 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2191 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2192 mii_speed--; 2193 if (mii_speed > 63) { 2194 dev_err(&pdev->dev, 2195 "fec clock (%lu) too fast to get right mii speed\n", 2196 clk_get_rate(fep->clk_ipg)); 2197 err = -EINVAL; 2198 goto err_out; 2199 } 2200 2201 /* 2202 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2203 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2204 * versions are RAZ there, so just ignore the difference and write the 2205 * register always. 2206 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2207 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2208 * output. 2209 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2210 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2211 * holdtime cannot result in a value greater than 3. 2212 */ 2213 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2214 2215 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2216 2217 if (suppress_preamble) 2218 fep->phy_speed |= BIT(7); 2219 2220 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2221 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2222 * MII event generation condition: 2223 * - writing MSCR: 2224 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2225 * mscr_reg_data_in[7:0] != 0 2226 * - writing MMFR: 2227 * - mscr[7:0]_not_zero 2228 */ 2229 writel(0, fep->hwp + FEC_MII_DATA); 2230 } 2231 2232 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2233 2234 /* Clear any pending transaction complete indication */ 2235 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2236 2237 fep->mii_bus = mdiobus_alloc(); 2238 if (fep->mii_bus == NULL) { 2239 err = -ENOMEM; 2240 goto err_out; 2241 } 2242 2243 fep->mii_bus->name = "fec_enet_mii_bus"; 2244 fep->mii_bus->read = fec_enet_mdio_read; 2245 fep->mii_bus->write = fec_enet_mdio_write; 2246 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2247 pdev->name, fep->dev_id + 1); 2248 fep->mii_bus->priv = fep; 2249 fep->mii_bus->parent = &pdev->dev; 2250 2251 err = of_mdiobus_register(fep->mii_bus, node); 2252 if (err) 2253 goto err_out_free_mdiobus; 2254 of_node_put(node); 2255 2256 mii_cnt++; 2257 2258 /* save fec0 mii_bus */ 2259 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2260 fec0_mii_bus = fep->mii_bus; 2261 2262 return 0; 2263 2264 err_out_free_mdiobus: 2265 mdiobus_free(fep->mii_bus); 2266 err_out: 2267 of_node_put(node); 2268 return err; 2269 } 2270 2271 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2272 { 2273 if (--mii_cnt == 0) { 2274 mdiobus_unregister(fep->mii_bus); 2275 mdiobus_free(fep->mii_bus); 2276 } 2277 } 2278 2279 static void fec_enet_get_drvinfo(struct net_device *ndev, 2280 struct ethtool_drvinfo *info) 2281 { 2282 struct fec_enet_private *fep = netdev_priv(ndev); 2283 2284 strlcpy(info->driver, fep->pdev->dev.driver->name, 2285 sizeof(info->driver)); 2286 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2287 } 2288 2289 static int fec_enet_get_regs_len(struct net_device *ndev) 2290 { 2291 struct fec_enet_private *fep = netdev_priv(ndev); 2292 struct resource *r; 2293 int s = 0; 2294 2295 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2296 if (r) 2297 s = resource_size(r); 2298 2299 return s; 2300 } 2301 2302 /* List of registers that can be safety be read to dump them with ethtool */ 2303 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2304 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2305 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2306 static __u32 fec_enet_register_version = 2; 2307 static u32 fec_enet_register_offset[] = { 2308 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2309 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2310 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2311 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2312 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2313 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2314 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2315 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2316 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2317 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2318 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2319 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2320 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2321 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2322 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2323 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2324 RMON_T_P_GTE2048, RMON_T_OCTETS, 2325 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2326 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2327 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2328 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2329 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2330 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2331 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2332 RMON_R_P_GTE2048, RMON_R_OCTETS, 2333 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2334 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2335 }; 2336 #else 2337 static __u32 fec_enet_register_version = 1; 2338 static u32 fec_enet_register_offset[] = { 2339 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2340 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2341 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2342 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2343 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2344 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2345 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2346 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2347 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2348 }; 2349 #endif 2350 2351 static void fec_enet_get_regs(struct net_device *ndev, 2352 struct ethtool_regs *regs, void *regbuf) 2353 { 2354 struct fec_enet_private *fep = netdev_priv(ndev); 2355 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2356 struct device *dev = &fep->pdev->dev; 2357 u32 *buf = (u32 *)regbuf; 2358 u32 i, off; 2359 int ret; 2360 2361 ret = pm_runtime_resume_and_get(dev); 2362 if (ret < 0) 2363 return; 2364 2365 regs->version = fec_enet_register_version; 2366 2367 memset(buf, 0, regs->len); 2368 2369 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2370 off = fec_enet_register_offset[i]; 2371 2372 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2373 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2374 continue; 2375 2376 off >>= 2; 2377 buf[off] = readl(&theregs[off]); 2378 } 2379 2380 pm_runtime_mark_last_busy(dev); 2381 pm_runtime_put_autosuspend(dev); 2382 } 2383 2384 static int fec_enet_get_ts_info(struct net_device *ndev, 2385 struct ethtool_ts_info *info) 2386 { 2387 struct fec_enet_private *fep = netdev_priv(ndev); 2388 2389 if (fep->bufdesc_ex) { 2390 2391 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2392 SOF_TIMESTAMPING_RX_SOFTWARE | 2393 SOF_TIMESTAMPING_SOFTWARE | 2394 SOF_TIMESTAMPING_TX_HARDWARE | 2395 SOF_TIMESTAMPING_RX_HARDWARE | 2396 SOF_TIMESTAMPING_RAW_HARDWARE; 2397 if (fep->ptp_clock) 2398 info->phc_index = ptp_clock_index(fep->ptp_clock); 2399 else 2400 info->phc_index = -1; 2401 2402 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2403 (1 << HWTSTAMP_TX_ON); 2404 2405 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2406 (1 << HWTSTAMP_FILTER_ALL); 2407 return 0; 2408 } else { 2409 return ethtool_op_get_ts_info(ndev, info); 2410 } 2411 } 2412 2413 #if !defined(CONFIG_M5272) 2414 2415 static void fec_enet_get_pauseparam(struct net_device *ndev, 2416 struct ethtool_pauseparam *pause) 2417 { 2418 struct fec_enet_private *fep = netdev_priv(ndev); 2419 2420 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2421 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2422 pause->rx_pause = pause->tx_pause; 2423 } 2424 2425 static int fec_enet_set_pauseparam(struct net_device *ndev, 2426 struct ethtool_pauseparam *pause) 2427 { 2428 struct fec_enet_private *fep = netdev_priv(ndev); 2429 2430 if (!ndev->phydev) 2431 return -ENODEV; 2432 2433 if (pause->tx_pause != pause->rx_pause) { 2434 netdev_info(ndev, 2435 "hardware only support enable/disable both tx and rx"); 2436 return -EINVAL; 2437 } 2438 2439 fep->pause_flag = 0; 2440 2441 /* tx pause must be same as rx pause */ 2442 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2443 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2444 2445 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2446 pause->autoneg); 2447 2448 if (pause->autoneg) { 2449 if (netif_running(ndev)) 2450 fec_stop(ndev); 2451 phy_start_aneg(ndev->phydev); 2452 } 2453 if (netif_running(ndev)) { 2454 napi_disable(&fep->napi); 2455 netif_tx_lock_bh(ndev); 2456 fec_restart(ndev); 2457 netif_tx_wake_all_queues(ndev); 2458 netif_tx_unlock_bh(ndev); 2459 napi_enable(&fep->napi); 2460 } 2461 2462 return 0; 2463 } 2464 2465 static const struct fec_stat { 2466 char name[ETH_GSTRING_LEN]; 2467 u16 offset; 2468 } fec_stats[] = { 2469 /* RMON TX */ 2470 { "tx_dropped", RMON_T_DROP }, 2471 { "tx_packets", RMON_T_PACKETS }, 2472 { "tx_broadcast", RMON_T_BC_PKT }, 2473 { "tx_multicast", RMON_T_MC_PKT }, 2474 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2475 { "tx_undersize", RMON_T_UNDERSIZE }, 2476 { "tx_oversize", RMON_T_OVERSIZE }, 2477 { "tx_fragment", RMON_T_FRAG }, 2478 { "tx_jabber", RMON_T_JAB }, 2479 { "tx_collision", RMON_T_COL }, 2480 { "tx_64byte", RMON_T_P64 }, 2481 { "tx_65to127byte", RMON_T_P65TO127 }, 2482 { "tx_128to255byte", RMON_T_P128TO255 }, 2483 { "tx_256to511byte", RMON_T_P256TO511 }, 2484 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2485 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2486 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2487 { "tx_octets", RMON_T_OCTETS }, 2488 2489 /* IEEE TX */ 2490 { "IEEE_tx_drop", IEEE_T_DROP }, 2491 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2492 { "IEEE_tx_1col", IEEE_T_1COL }, 2493 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2494 { "IEEE_tx_def", IEEE_T_DEF }, 2495 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2496 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2497 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2498 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2499 { "IEEE_tx_sqe", IEEE_T_SQE }, 2500 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2501 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2502 2503 /* RMON RX */ 2504 { "rx_packets", RMON_R_PACKETS }, 2505 { "rx_broadcast", RMON_R_BC_PKT }, 2506 { "rx_multicast", RMON_R_MC_PKT }, 2507 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2508 { "rx_undersize", RMON_R_UNDERSIZE }, 2509 { "rx_oversize", RMON_R_OVERSIZE }, 2510 { "rx_fragment", RMON_R_FRAG }, 2511 { "rx_jabber", RMON_R_JAB }, 2512 { "rx_64byte", RMON_R_P64 }, 2513 { "rx_65to127byte", RMON_R_P65TO127 }, 2514 { "rx_128to255byte", RMON_R_P128TO255 }, 2515 { "rx_256to511byte", RMON_R_P256TO511 }, 2516 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2517 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2518 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2519 { "rx_octets", RMON_R_OCTETS }, 2520 2521 /* IEEE RX */ 2522 { "IEEE_rx_drop", IEEE_R_DROP }, 2523 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2524 { "IEEE_rx_crc", IEEE_R_CRC }, 2525 { "IEEE_rx_align", IEEE_R_ALIGN }, 2526 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2527 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2528 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2529 }; 2530 2531 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2532 2533 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2534 { 2535 struct fec_enet_private *fep = netdev_priv(dev); 2536 int i; 2537 2538 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2539 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2540 } 2541 2542 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2543 struct ethtool_stats *stats, u64 *data) 2544 { 2545 struct fec_enet_private *fep = netdev_priv(dev); 2546 2547 if (netif_running(dev)) 2548 fec_enet_update_ethtool_stats(dev); 2549 2550 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2551 } 2552 2553 static void fec_enet_get_strings(struct net_device *netdev, 2554 u32 stringset, u8 *data) 2555 { 2556 int i; 2557 switch (stringset) { 2558 case ETH_SS_STATS: 2559 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2560 memcpy(data + i * ETH_GSTRING_LEN, 2561 fec_stats[i].name, ETH_GSTRING_LEN); 2562 break; 2563 case ETH_SS_TEST: 2564 net_selftest_get_strings(data); 2565 break; 2566 } 2567 } 2568 2569 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2570 { 2571 switch (sset) { 2572 case ETH_SS_STATS: 2573 return ARRAY_SIZE(fec_stats); 2574 case ETH_SS_TEST: 2575 return net_selftest_get_count(); 2576 default: 2577 return -EOPNOTSUPP; 2578 } 2579 } 2580 2581 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2582 { 2583 struct fec_enet_private *fep = netdev_priv(dev); 2584 int i; 2585 2586 /* Disable MIB statistics counters */ 2587 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2588 2589 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2590 writel(0, fep->hwp + fec_stats[i].offset); 2591 2592 /* Don't disable MIB statistics counters */ 2593 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2594 } 2595 2596 #else /* !defined(CONFIG_M5272) */ 2597 #define FEC_STATS_SIZE 0 2598 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2599 { 2600 } 2601 2602 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2603 { 2604 } 2605 #endif /* !defined(CONFIG_M5272) */ 2606 2607 /* ITR clock source is enet system clock (clk_ahb). 2608 * TCTT unit is cycle_ns * 64 cycle 2609 * So, the ICTT value = X us / (cycle_ns * 64) 2610 */ 2611 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2612 { 2613 struct fec_enet_private *fep = netdev_priv(ndev); 2614 2615 return us * (fep->itr_clk_rate / 64000) / 1000; 2616 } 2617 2618 /* Set threshold for interrupt coalescing */ 2619 static void fec_enet_itr_coal_set(struct net_device *ndev) 2620 { 2621 struct fec_enet_private *fep = netdev_priv(ndev); 2622 int rx_itr, tx_itr; 2623 2624 /* Must be greater than zero to avoid unpredictable behavior */ 2625 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2626 !fep->tx_time_itr || !fep->tx_pkts_itr) 2627 return; 2628 2629 /* Select enet system clock as Interrupt Coalescing 2630 * timer Clock Source 2631 */ 2632 rx_itr = FEC_ITR_CLK_SEL; 2633 tx_itr = FEC_ITR_CLK_SEL; 2634 2635 /* set ICFT and ICTT */ 2636 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2637 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2638 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2639 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2640 2641 rx_itr |= FEC_ITR_EN; 2642 tx_itr |= FEC_ITR_EN; 2643 2644 writel(tx_itr, fep->hwp + FEC_TXIC0); 2645 writel(rx_itr, fep->hwp + FEC_RXIC0); 2646 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 2647 writel(tx_itr, fep->hwp + FEC_TXIC1); 2648 writel(rx_itr, fep->hwp + FEC_RXIC1); 2649 writel(tx_itr, fep->hwp + FEC_TXIC2); 2650 writel(rx_itr, fep->hwp + FEC_RXIC2); 2651 } 2652 } 2653 2654 static int fec_enet_get_coalesce(struct net_device *ndev, 2655 struct ethtool_coalesce *ec, 2656 struct kernel_ethtool_coalesce *kernel_coal, 2657 struct netlink_ext_ack *extack) 2658 { 2659 struct fec_enet_private *fep = netdev_priv(ndev); 2660 2661 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2662 return -EOPNOTSUPP; 2663 2664 ec->rx_coalesce_usecs = fep->rx_time_itr; 2665 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2666 2667 ec->tx_coalesce_usecs = fep->tx_time_itr; 2668 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2669 2670 return 0; 2671 } 2672 2673 static int fec_enet_set_coalesce(struct net_device *ndev, 2674 struct ethtool_coalesce *ec, 2675 struct kernel_ethtool_coalesce *kernel_coal, 2676 struct netlink_ext_ack *extack) 2677 { 2678 struct fec_enet_private *fep = netdev_priv(ndev); 2679 struct device *dev = &fep->pdev->dev; 2680 unsigned int cycle; 2681 2682 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2683 return -EOPNOTSUPP; 2684 2685 if (ec->rx_max_coalesced_frames > 255) { 2686 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 2687 return -EINVAL; 2688 } 2689 2690 if (ec->tx_max_coalesced_frames > 255) { 2691 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 2692 return -EINVAL; 2693 } 2694 2695 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 2696 if (cycle > 0xFFFF) { 2697 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 2698 return -EINVAL; 2699 } 2700 2701 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 2702 if (cycle > 0xFFFF) { 2703 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 2704 return -EINVAL; 2705 } 2706 2707 fep->rx_time_itr = ec->rx_coalesce_usecs; 2708 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2709 2710 fep->tx_time_itr = ec->tx_coalesce_usecs; 2711 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2712 2713 fec_enet_itr_coal_set(ndev); 2714 2715 return 0; 2716 } 2717 2718 static void fec_enet_itr_coal_init(struct net_device *ndev) 2719 { 2720 struct ethtool_coalesce ec; 2721 2722 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2723 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2724 2725 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2726 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2727 2728 fec_enet_set_coalesce(ndev, &ec, NULL, NULL); 2729 } 2730 2731 static int fec_enet_get_tunable(struct net_device *netdev, 2732 const struct ethtool_tunable *tuna, 2733 void *data) 2734 { 2735 struct fec_enet_private *fep = netdev_priv(netdev); 2736 int ret = 0; 2737 2738 switch (tuna->id) { 2739 case ETHTOOL_RX_COPYBREAK: 2740 *(u32 *)data = fep->rx_copybreak; 2741 break; 2742 default: 2743 ret = -EINVAL; 2744 break; 2745 } 2746 2747 return ret; 2748 } 2749 2750 static int fec_enet_set_tunable(struct net_device *netdev, 2751 const struct ethtool_tunable *tuna, 2752 const void *data) 2753 { 2754 struct fec_enet_private *fep = netdev_priv(netdev); 2755 int ret = 0; 2756 2757 switch (tuna->id) { 2758 case ETHTOOL_RX_COPYBREAK: 2759 fep->rx_copybreak = *(u32 *)data; 2760 break; 2761 default: 2762 ret = -EINVAL; 2763 break; 2764 } 2765 2766 return ret; 2767 } 2768 2769 /* LPI Sleep Ts count base on tx clk (clk_ref). 2770 * The lpi sleep cnt value = X us / (cycle_ns). 2771 */ 2772 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 2773 { 2774 struct fec_enet_private *fep = netdev_priv(ndev); 2775 2776 return us * (fep->clk_ref_rate / 1000) / 1000; 2777 } 2778 2779 static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable) 2780 { 2781 struct fec_enet_private *fep = netdev_priv(ndev); 2782 struct ethtool_eee *p = &fep->eee; 2783 unsigned int sleep_cycle, wake_cycle; 2784 int ret = 0; 2785 2786 if (enable) { 2787 ret = phy_init_eee(ndev->phydev, 0); 2788 if (ret) 2789 return ret; 2790 2791 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer); 2792 wake_cycle = sleep_cycle; 2793 } else { 2794 sleep_cycle = 0; 2795 wake_cycle = 0; 2796 } 2797 2798 p->tx_lpi_enabled = enable; 2799 p->eee_enabled = enable; 2800 p->eee_active = enable; 2801 2802 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 2803 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 2804 2805 return 0; 2806 } 2807 2808 static int 2809 fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata) 2810 { 2811 struct fec_enet_private *fep = netdev_priv(ndev); 2812 struct ethtool_eee *p = &fep->eee; 2813 2814 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 2815 return -EOPNOTSUPP; 2816 2817 if (!netif_running(ndev)) 2818 return -ENETDOWN; 2819 2820 edata->eee_enabled = p->eee_enabled; 2821 edata->eee_active = p->eee_active; 2822 edata->tx_lpi_timer = p->tx_lpi_timer; 2823 edata->tx_lpi_enabled = p->tx_lpi_enabled; 2824 2825 return phy_ethtool_get_eee(ndev->phydev, edata); 2826 } 2827 2828 static int 2829 fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata) 2830 { 2831 struct fec_enet_private *fep = netdev_priv(ndev); 2832 struct ethtool_eee *p = &fep->eee; 2833 int ret = 0; 2834 2835 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 2836 return -EOPNOTSUPP; 2837 2838 if (!netif_running(ndev)) 2839 return -ENETDOWN; 2840 2841 p->tx_lpi_timer = edata->tx_lpi_timer; 2842 2843 if (!edata->eee_enabled || !edata->tx_lpi_enabled || 2844 !edata->tx_lpi_timer) 2845 ret = fec_enet_eee_mode_set(ndev, false); 2846 else 2847 ret = fec_enet_eee_mode_set(ndev, true); 2848 2849 if (ret) 2850 return ret; 2851 2852 return phy_ethtool_set_eee(ndev->phydev, edata); 2853 } 2854 2855 static void 2856 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2857 { 2858 struct fec_enet_private *fep = netdev_priv(ndev); 2859 2860 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2861 wol->supported = WAKE_MAGIC; 2862 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2863 } else { 2864 wol->supported = wol->wolopts = 0; 2865 } 2866 } 2867 2868 static int 2869 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2870 { 2871 struct fec_enet_private *fep = netdev_priv(ndev); 2872 2873 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2874 return -EINVAL; 2875 2876 if (wol->wolopts & ~WAKE_MAGIC) 2877 return -EINVAL; 2878 2879 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2880 if (device_may_wakeup(&ndev->dev)) { 2881 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2882 if (fep->wake_irq > 0) 2883 enable_irq_wake(fep->wake_irq); 2884 } else { 2885 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2886 if (fep->wake_irq > 0) 2887 disable_irq_wake(fep->wake_irq); 2888 } 2889 2890 return 0; 2891 } 2892 2893 static const struct ethtool_ops fec_enet_ethtool_ops = { 2894 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2895 ETHTOOL_COALESCE_MAX_FRAMES, 2896 .get_drvinfo = fec_enet_get_drvinfo, 2897 .get_regs_len = fec_enet_get_regs_len, 2898 .get_regs = fec_enet_get_regs, 2899 .nway_reset = phy_ethtool_nway_reset, 2900 .get_link = ethtool_op_get_link, 2901 .get_coalesce = fec_enet_get_coalesce, 2902 .set_coalesce = fec_enet_set_coalesce, 2903 #ifndef CONFIG_M5272 2904 .get_pauseparam = fec_enet_get_pauseparam, 2905 .set_pauseparam = fec_enet_set_pauseparam, 2906 .get_strings = fec_enet_get_strings, 2907 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2908 .get_sset_count = fec_enet_get_sset_count, 2909 #endif 2910 .get_ts_info = fec_enet_get_ts_info, 2911 .get_tunable = fec_enet_get_tunable, 2912 .set_tunable = fec_enet_set_tunable, 2913 .get_wol = fec_enet_get_wol, 2914 .set_wol = fec_enet_set_wol, 2915 .get_eee = fec_enet_get_eee, 2916 .set_eee = fec_enet_set_eee, 2917 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2918 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2919 .self_test = net_selftest, 2920 }; 2921 2922 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2923 { 2924 struct fec_enet_private *fep = netdev_priv(ndev); 2925 struct phy_device *phydev = ndev->phydev; 2926 2927 if (!netif_running(ndev)) 2928 return -EINVAL; 2929 2930 if (!phydev) 2931 return -ENODEV; 2932 2933 if (fep->bufdesc_ex) { 2934 bool use_fec_hwts = !phy_has_hwtstamp(phydev); 2935 2936 if (cmd == SIOCSHWTSTAMP) { 2937 if (use_fec_hwts) 2938 return fec_ptp_set(ndev, rq); 2939 fec_ptp_disable_hwts(ndev); 2940 } else if (cmd == SIOCGHWTSTAMP) { 2941 if (use_fec_hwts) 2942 return fec_ptp_get(ndev, rq); 2943 } 2944 } 2945 2946 return phy_mii_ioctl(phydev, rq, cmd); 2947 } 2948 2949 static void fec_enet_free_buffers(struct net_device *ndev) 2950 { 2951 struct fec_enet_private *fep = netdev_priv(ndev); 2952 unsigned int i; 2953 struct sk_buff *skb; 2954 struct bufdesc *bdp; 2955 struct fec_enet_priv_tx_q *txq; 2956 struct fec_enet_priv_rx_q *rxq; 2957 unsigned int q; 2958 2959 for (q = 0; q < fep->num_rx_queues; q++) { 2960 rxq = fep->rx_queue[q]; 2961 bdp = rxq->bd.base; 2962 for (i = 0; i < rxq->bd.ring_size; i++) { 2963 skb = rxq->rx_skbuff[i]; 2964 rxq->rx_skbuff[i] = NULL; 2965 if (skb) { 2966 dma_unmap_single(&fep->pdev->dev, 2967 fec32_to_cpu(bdp->cbd_bufaddr), 2968 FEC_ENET_RX_FRSIZE - fep->rx_align, 2969 DMA_FROM_DEVICE); 2970 dev_kfree_skb(skb); 2971 } 2972 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2973 } 2974 } 2975 2976 for (q = 0; q < fep->num_tx_queues; q++) { 2977 txq = fep->tx_queue[q]; 2978 for (i = 0; i < txq->bd.ring_size; i++) { 2979 kfree(txq->tx_bounce[i]); 2980 txq->tx_bounce[i] = NULL; 2981 skb = txq->tx_skbuff[i]; 2982 txq->tx_skbuff[i] = NULL; 2983 dev_kfree_skb(skb); 2984 } 2985 } 2986 } 2987 2988 static void fec_enet_free_queue(struct net_device *ndev) 2989 { 2990 struct fec_enet_private *fep = netdev_priv(ndev); 2991 int i; 2992 struct fec_enet_priv_tx_q *txq; 2993 2994 for (i = 0; i < fep->num_tx_queues; i++) 2995 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2996 txq = fep->tx_queue[i]; 2997 dma_free_coherent(&fep->pdev->dev, 2998 txq->bd.ring_size * TSO_HEADER_SIZE, 2999 txq->tso_hdrs, 3000 txq->tso_hdrs_dma); 3001 } 3002 3003 for (i = 0; i < fep->num_rx_queues; i++) 3004 kfree(fep->rx_queue[i]); 3005 for (i = 0; i < fep->num_tx_queues; i++) 3006 kfree(fep->tx_queue[i]); 3007 } 3008 3009 static int fec_enet_alloc_queue(struct net_device *ndev) 3010 { 3011 struct fec_enet_private *fep = netdev_priv(ndev); 3012 int i; 3013 int ret = 0; 3014 struct fec_enet_priv_tx_q *txq; 3015 3016 for (i = 0; i < fep->num_tx_queues; i++) { 3017 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3018 if (!txq) { 3019 ret = -ENOMEM; 3020 goto alloc_failed; 3021 } 3022 3023 fep->tx_queue[i] = txq; 3024 txq->bd.ring_size = TX_RING_SIZE; 3025 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3026 3027 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3028 txq->tx_wake_threshold = 3029 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 3030 3031 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 3032 txq->bd.ring_size * TSO_HEADER_SIZE, 3033 &txq->tso_hdrs_dma, 3034 GFP_KERNEL); 3035 if (!txq->tso_hdrs) { 3036 ret = -ENOMEM; 3037 goto alloc_failed; 3038 } 3039 } 3040 3041 for (i = 0; i < fep->num_rx_queues; i++) { 3042 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3043 GFP_KERNEL); 3044 if (!fep->rx_queue[i]) { 3045 ret = -ENOMEM; 3046 goto alloc_failed; 3047 } 3048 3049 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3050 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3051 } 3052 return ret; 3053 3054 alloc_failed: 3055 fec_enet_free_queue(ndev); 3056 return ret; 3057 } 3058 3059 static int 3060 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3061 { 3062 struct fec_enet_private *fep = netdev_priv(ndev); 3063 unsigned int i; 3064 struct sk_buff *skb; 3065 struct bufdesc *bdp; 3066 struct fec_enet_priv_rx_q *rxq; 3067 3068 rxq = fep->rx_queue[queue]; 3069 bdp = rxq->bd.base; 3070 for (i = 0; i < rxq->bd.ring_size; i++) { 3071 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 3072 if (!skb) 3073 goto err_alloc; 3074 3075 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 3076 dev_kfree_skb(skb); 3077 goto err_alloc; 3078 } 3079 3080 rxq->rx_skbuff[i] = skb; 3081 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3082 3083 if (fep->bufdesc_ex) { 3084 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3085 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3086 } 3087 3088 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3089 } 3090 3091 /* Set the last buffer to wrap. */ 3092 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3093 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3094 return 0; 3095 3096 err_alloc: 3097 fec_enet_free_buffers(ndev); 3098 return -ENOMEM; 3099 } 3100 3101 static int 3102 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3103 { 3104 struct fec_enet_private *fep = netdev_priv(ndev); 3105 unsigned int i; 3106 struct bufdesc *bdp; 3107 struct fec_enet_priv_tx_q *txq; 3108 3109 txq = fep->tx_queue[queue]; 3110 bdp = txq->bd.base; 3111 for (i = 0; i < txq->bd.ring_size; i++) { 3112 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3113 if (!txq->tx_bounce[i]) 3114 goto err_alloc; 3115 3116 bdp->cbd_sc = cpu_to_fec16(0); 3117 bdp->cbd_bufaddr = cpu_to_fec32(0); 3118 3119 if (fep->bufdesc_ex) { 3120 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3121 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3122 } 3123 3124 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3125 } 3126 3127 /* Set the last buffer to wrap. */ 3128 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3129 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3130 3131 return 0; 3132 3133 err_alloc: 3134 fec_enet_free_buffers(ndev); 3135 return -ENOMEM; 3136 } 3137 3138 static int fec_enet_alloc_buffers(struct net_device *ndev) 3139 { 3140 struct fec_enet_private *fep = netdev_priv(ndev); 3141 unsigned int i; 3142 3143 for (i = 0; i < fep->num_rx_queues; i++) 3144 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3145 return -ENOMEM; 3146 3147 for (i = 0; i < fep->num_tx_queues; i++) 3148 if (fec_enet_alloc_txq_buffers(ndev, i)) 3149 return -ENOMEM; 3150 return 0; 3151 } 3152 3153 static int 3154 fec_enet_open(struct net_device *ndev) 3155 { 3156 struct fec_enet_private *fep = netdev_priv(ndev); 3157 int ret; 3158 bool reset_again; 3159 3160 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3161 if (ret < 0) 3162 return ret; 3163 3164 pinctrl_pm_select_default_state(&fep->pdev->dev); 3165 ret = fec_enet_clk_enable(ndev, true); 3166 if (ret) 3167 goto clk_enable; 3168 3169 /* During the first fec_enet_open call the PHY isn't probed at this 3170 * point. Therefore the phy_reset_after_clk_enable() call within 3171 * fec_enet_clk_enable() fails. As we need this reset in order to be 3172 * sure the PHY is working correctly we check if we need to reset again 3173 * later when the PHY is probed 3174 */ 3175 if (ndev->phydev && ndev->phydev->drv) 3176 reset_again = false; 3177 else 3178 reset_again = true; 3179 3180 /* I should reset the ring buffers here, but I don't yet know 3181 * a simple way to do that. 3182 */ 3183 3184 ret = fec_enet_alloc_buffers(ndev); 3185 if (ret) 3186 goto err_enet_alloc; 3187 3188 /* Init MAC prior to mii bus probe */ 3189 fec_restart(ndev); 3190 3191 /* Call phy_reset_after_clk_enable() again if it failed during 3192 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3193 */ 3194 if (reset_again) 3195 fec_enet_phy_reset_after_clk_enable(ndev); 3196 3197 /* Probe and connect to PHY when open the interface */ 3198 ret = fec_enet_mii_probe(ndev); 3199 if (ret) 3200 goto err_enet_mii_probe; 3201 3202 if (fep->quirks & FEC_QUIRK_ERR006687) 3203 imx6q_cpuidle_fec_irqs_used(); 3204 3205 napi_enable(&fep->napi); 3206 phy_start(ndev->phydev); 3207 netif_tx_start_all_queues(ndev); 3208 3209 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3210 FEC_WOL_FLAG_ENABLE); 3211 3212 return 0; 3213 3214 err_enet_mii_probe: 3215 fec_enet_free_buffers(ndev); 3216 err_enet_alloc: 3217 fec_enet_clk_enable(ndev, false); 3218 clk_enable: 3219 pm_runtime_mark_last_busy(&fep->pdev->dev); 3220 pm_runtime_put_autosuspend(&fep->pdev->dev); 3221 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3222 return ret; 3223 } 3224 3225 static int 3226 fec_enet_close(struct net_device *ndev) 3227 { 3228 struct fec_enet_private *fep = netdev_priv(ndev); 3229 3230 phy_stop(ndev->phydev); 3231 3232 if (netif_device_present(ndev)) { 3233 napi_disable(&fep->napi); 3234 netif_tx_disable(ndev); 3235 fec_stop(ndev); 3236 } 3237 3238 phy_disconnect(ndev->phydev); 3239 3240 if (fep->quirks & FEC_QUIRK_ERR006687) 3241 imx6q_cpuidle_fec_irqs_unused(); 3242 3243 fec_enet_update_ethtool_stats(ndev); 3244 3245 fec_enet_clk_enable(ndev, false); 3246 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3247 pm_runtime_mark_last_busy(&fep->pdev->dev); 3248 pm_runtime_put_autosuspend(&fep->pdev->dev); 3249 3250 fec_enet_free_buffers(ndev); 3251 3252 return 0; 3253 } 3254 3255 /* Set or clear the multicast filter for this adaptor. 3256 * Skeleton taken from sunlance driver. 3257 * The CPM Ethernet implementation allows Multicast as well as individual 3258 * MAC address filtering. Some of the drivers check to make sure it is 3259 * a group multicast address, and discard those that are not. I guess I 3260 * will do the same for now, but just remove the test if you want 3261 * individual filtering as well (do the upper net layers want or support 3262 * this kind of feature?). 3263 */ 3264 3265 #define FEC_HASH_BITS 6 /* #bits in hash */ 3266 3267 static void set_multicast_list(struct net_device *ndev) 3268 { 3269 struct fec_enet_private *fep = netdev_priv(ndev); 3270 struct netdev_hw_addr *ha; 3271 unsigned int crc, tmp; 3272 unsigned char hash; 3273 unsigned int hash_high = 0, hash_low = 0; 3274 3275 if (ndev->flags & IFF_PROMISC) { 3276 tmp = readl(fep->hwp + FEC_R_CNTRL); 3277 tmp |= 0x8; 3278 writel(tmp, fep->hwp + FEC_R_CNTRL); 3279 return; 3280 } 3281 3282 tmp = readl(fep->hwp + FEC_R_CNTRL); 3283 tmp &= ~0x8; 3284 writel(tmp, fep->hwp + FEC_R_CNTRL); 3285 3286 if (ndev->flags & IFF_ALLMULTI) { 3287 /* Catch all multicast addresses, so set the 3288 * filter to all 1's 3289 */ 3290 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3291 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3292 3293 return; 3294 } 3295 3296 /* Add the addresses in hash register */ 3297 netdev_for_each_mc_addr(ha, ndev) { 3298 /* calculate crc32 value of mac address */ 3299 crc = ether_crc_le(ndev->addr_len, ha->addr); 3300 3301 /* only upper 6 bits (FEC_HASH_BITS) are used 3302 * which point to specific bit in the hash registers 3303 */ 3304 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3305 3306 if (hash > 31) 3307 hash_high |= 1 << (hash - 32); 3308 else 3309 hash_low |= 1 << hash; 3310 } 3311 3312 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3313 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3314 } 3315 3316 /* Set a MAC change in hardware. */ 3317 static int 3318 fec_set_mac_address(struct net_device *ndev, void *p) 3319 { 3320 struct fec_enet_private *fep = netdev_priv(ndev); 3321 struct sockaddr *addr = p; 3322 3323 if (addr) { 3324 if (!is_valid_ether_addr(addr->sa_data)) 3325 return -EADDRNOTAVAIL; 3326 eth_hw_addr_set(ndev, addr->sa_data); 3327 } 3328 3329 /* Add netif status check here to avoid system hang in below case: 3330 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3331 * After ethx down, fec all clocks are gated off and then register 3332 * access causes system hang. 3333 */ 3334 if (!netif_running(ndev)) 3335 return 0; 3336 3337 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3338 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3339 fep->hwp + FEC_ADDR_LOW); 3340 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3341 fep->hwp + FEC_ADDR_HIGH); 3342 return 0; 3343 } 3344 3345 #ifdef CONFIG_NET_POLL_CONTROLLER 3346 /** 3347 * fec_poll_controller - FEC Poll controller function 3348 * @dev: The FEC network adapter 3349 * 3350 * Polled functionality used by netconsole and others in non interrupt mode 3351 * 3352 */ 3353 static void fec_poll_controller(struct net_device *dev) 3354 { 3355 int i; 3356 struct fec_enet_private *fep = netdev_priv(dev); 3357 3358 for (i = 0; i < FEC_IRQ_NUM; i++) { 3359 if (fep->irq[i] > 0) { 3360 disable_irq(fep->irq[i]); 3361 fec_enet_interrupt(fep->irq[i], dev); 3362 enable_irq(fep->irq[i]); 3363 } 3364 } 3365 } 3366 #endif 3367 3368 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3369 netdev_features_t features) 3370 { 3371 struct fec_enet_private *fep = netdev_priv(netdev); 3372 netdev_features_t changed = features ^ netdev->features; 3373 3374 netdev->features = features; 3375 3376 /* Receive checksum has been changed */ 3377 if (changed & NETIF_F_RXCSUM) { 3378 if (features & NETIF_F_RXCSUM) 3379 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3380 else 3381 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3382 } 3383 } 3384 3385 static int fec_set_features(struct net_device *netdev, 3386 netdev_features_t features) 3387 { 3388 struct fec_enet_private *fep = netdev_priv(netdev); 3389 netdev_features_t changed = features ^ netdev->features; 3390 3391 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3392 napi_disable(&fep->napi); 3393 netif_tx_lock_bh(netdev); 3394 fec_stop(netdev); 3395 fec_enet_set_netdev_features(netdev, features); 3396 fec_restart(netdev); 3397 netif_tx_wake_all_queues(netdev); 3398 netif_tx_unlock_bh(netdev); 3399 napi_enable(&fep->napi); 3400 } else { 3401 fec_enet_set_netdev_features(netdev, features); 3402 } 3403 3404 return 0; 3405 } 3406 3407 static u16 fec_enet_get_raw_vlan_tci(struct sk_buff *skb) 3408 { 3409 struct vlan_ethhdr *vhdr; 3410 unsigned short vlan_TCI = 0; 3411 3412 if (skb->protocol == htons(ETH_P_ALL)) { 3413 vhdr = (struct vlan_ethhdr *)(skb->data); 3414 vlan_TCI = ntohs(vhdr->h_vlan_TCI); 3415 } 3416 3417 return vlan_TCI; 3418 } 3419 3420 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3421 struct net_device *sb_dev) 3422 { 3423 struct fec_enet_private *fep = netdev_priv(ndev); 3424 u16 vlan_tag; 3425 3426 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3427 return netdev_pick_tx(ndev, skb, NULL); 3428 3429 vlan_tag = fec_enet_get_raw_vlan_tci(skb); 3430 if (!vlan_tag) 3431 return vlan_tag; 3432 3433 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3434 } 3435 3436 static const struct net_device_ops fec_netdev_ops = { 3437 .ndo_open = fec_enet_open, 3438 .ndo_stop = fec_enet_close, 3439 .ndo_start_xmit = fec_enet_start_xmit, 3440 .ndo_select_queue = fec_enet_select_queue, 3441 .ndo_set_rx_mode = set_multicast_list, 3442 .ndo_validate_addr = eth_validate_addr, 3443 .ndo_tx_timeout = fec_timeout, 3444 .ndo_set_mac_address = fec_set_mac_address, 3445 .ndo_eth_ioctl = fec_enet_ioctl, 3446 #ifdef CONFIG_NET_POLL_CONTROLLER 3447 .ndo_poll_controller = fec_poll_controller, 3448 #endif 3449 .ndo_set_features = fec_set_features, 3450 }; 3451 3452 static const unsigned short offset_des_active_rxq[] = { 3453 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3454 }; 3455 3456 static const unsigned short offset_des_active_txq[] = { 3457 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3458 }; 3459 3460 /* 3461 * XXX: We need to clean up on failure exits here. 3462 * 3463 */ 3464 static int fec_enet_init(struct net_device *ndev) 3465 { 3466 struct fec_enet_private *fep = netdev_priv(ndev); 3467 struct bufdesc *cbd_base; 3468 dma_addr_t bd_dma; 3469 int bd_size; 3470 unsigned int i; 3471 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3472 sizeof(struct bufdesc); 3473 unsigned dsize_log2 = __fls(dsize); 3474 int ret; 3475 3476 WARN_ON(dsize != (1 << dsize_log2)); 3477 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 3478 fep->rx_align = 0xf; 3479 fep->tx_align = 0xf; 3480 #else 3481 fep->rx_align = 0x3; 3482 fep->tx_align = 0x3; 3483 #endif 3484 3485 /* Check mask of the streaming and coherent API */ 3486 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 3487 if (ret < 0) { 3488 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 3489 return ret; 3490 } 3491 3492 ret = fec_enet_alloc_queue(ndev); 3493 if (ret) 3494 return ret; 3495 3496 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3497 3498 /* Allocate memory for buffer descriptors. */ 3499 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3500 GFP_KERNEL); 3501 if (!cbd_base) { 3502 ret = -ENOMEM; 3503 goto free_queue_mem; 3504 } 3505 3506 /* Get the Ethernet address */ 3507 ret = fec_get_mac(ndev); 3508 if (ret) 3509 goto free_queue_mem; 3510 3511 /* make sure MAC we just acquired is programmed into the hw */ 3512 fec_set_mac_address(ndev, NULL); 3513 3514 /* Set receive and transmit descriptor base. */ 3515 for (i = 0; i < fep->num_rx_queues; i++) { 3516 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3517 unsigned size = dsize * rxq->bd.ring_size; 3518 3519 rxq->bd.qid = i; 3520 rxq->bd.base = cbd_base; 3521 rxq->bd.cur = cbd_base; 3522 rxq->bd.dma = bd_dma; 3523 rxq->bd.dsize = dsize; 3524 rxq->bd.dsize_log2 = dsize_log2; 3525 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3526 bd_dma += size; 3527 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3528 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3529 } 3530 3531 for (i = 0; i < fep->num_tx_queues; i++) { 3532 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3533 unsigned size = dsize * txq->bd.ring_size; 3534 3535 txq->bd.qid = i; 3536 txq->bd.base = cbd_base; 3537 txq->bd.cur = cbd_base; 3538 txq->bd.dma = bd_dma; 3539 txq->bd.dsize = dsize; 3540 txq->bd.dsize_log2 = dsize_log2; 3541 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3542 bd_dma += size; 3543 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3544 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3545 } 3546 3547 3548 /* The FEC Ethernet specific entries in the device structure */ 3549 ndev->watchdog_timeo = TX_TIMEOUT; 3550 ndev->netdev_ops = &fec_netdev_ops; 3551 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3552 3553 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3554 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3555 3556 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3557 /* enable hw VLAN support */ 3558 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3559 3560 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3561 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3562 3563 /* enable hw accelerator */ 3564 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3565 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3566 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3567 } 3568 3569 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 3570 fep->tx_align = 0; 3571 fep->rx_align = 0x3f; 3572 } 3573 3574 ndev->hw_features = ndev->features; 3575 3576 fec_restart(ndev); 3577 3578 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 3579 fec_enet_clear_ethtool_stats(ndev); 3580 else 3581 fec_enet_update_ethtool_stats(ndev); 3582 3583 return 0; 3584 3585 free_queue_mem: 3586 fec_enet_free_queue(ndev); 3587 return ret; 3588 } 3589 3590 #ifdef CONFIG_OF 3591 static int fec_reset_phy(struct platform_device *pdev) 3592 { 3593 int err, phy_reset; 3594 bool active_high = false; 3595 int msec = 1, phy_post_delay = 0; 3596 struct device_node *np = pdev->dev.of_node; 3597 3598 if (!np) 3599 return 0; 3600 3601 err = of_property_read_u32(np, "phy-reset-duration", &msec); 3602 /* A sane reset duration should not be longer than 1s */ 3603 if (!err && msec > 1000) 3604 msec = 1; 3605 3606 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3607 if (phy_reset == -EPROBE_DEFER) 3608 return phy_reset; 3609 else if (!gpio_is_valid(phy_reset)) 3610 return 0; 3611 3612 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 3613 /* valid reset duration should be less than 1s */ 3614 if (!err && phy_post_delay > 1000) 3615 return -EINVAL; 3616 3617 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3618 3619 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3620 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3621 "phy-reset"); 3622 if (err) { 3623 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3624 return err; 3625 } 3626 3627 if (msec > 20) 3628 msleep(msec); 3629 else 3630 usleep_range(msec * 1000, msec * 1000 + 1000); 3631 3632 gpio_set_value_cansleep(phy_reset, !active_high); 3633 3634 if (!phy_post_delay) 3635 return 0; 3636 3637 if (phy_post_delay > 20) 3638 msleep(phy_post_delay); 3639 else 3640 usleep_range(phy_post_delay * 1000, 3641 phy_post_delay * 1000 + 1000); 3642 3643 return 0; 3644 } 3645 #else /* CONFIG_OF */ 3646 static int fec_reset_phy(struct platform_device *pdev) 3647 { 3648 /* 3649 * In case of platform probe, the reset has been done 3650 * by machine code. 3651 */ 3652 return 0; 3653 } 3654 #endif /* CONFIG_OF */ 3655 3656 static void 3657 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3658 { 3659 struct device_node *np = pdev->dev.of_node; 3660 3661 *num_tx = *num_rx = 1; 3662 3663 if (!np || !of_device_is_available(np)) 3664 return; 3665 3666 /* parse the num of tx and rx queues */ 3667 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3668 3669 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3670 3671 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3672 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3673 *num_tx); 3674 *num_tx = 1; 3675 return; 3676 } 3677 3678 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3679 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3680 *num_rx); 3681 *num_rx = 1; 3682 return; 3683 } 3684 3685 } 3686 3687 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 3688 { 3689 int irq_cnt = platform_irq_count(pdev); 3690 3691 if (irq_cnt > FEC_IRQ_NUM) 3692 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 3693 else if (irq_cnt == 2) 3694 irq_cnt = 1; /* last for pps */ 3695 else if (irq_cnt <= 0) 3696 irq_cnt = 1; /* At least 1 irq is needed */ 3697 return irq_cnt; 3698 } 3699 3700 static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 3701 { 3702 struct net_device *ndev = platform_get_drvdata(pdev); 3703 struct fec_enet_private *fep = netdev_priv(ndev); 3704 3705 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 3706 fep->wake_irq = fep->irq[2]; 3707 else 3708 fep->wake_irq = fep->irq[0]; 3709 } 3710 3711 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 3712 struct device_node *np) 3713 { 3714 struct device_node *gpr_np; 3715 u32 out_val[3]; 3716 int ret = 0; 3717 3718 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 3719 if (!gpr_np) 3720 return 0; 3721 3722 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 3723 ARRAY_SIZE(out_val)); 3724 if (ret) { 3725 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 3726 return ret; 3727 } 3728 3729 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 3730 if (IS_ERR(fep->stop_gpr.gpr)) { 3731 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 3732 ret = PTR_ERR(fep->stop_gpr.gpr); 3733 fep->stop_gpr.gpr = NULL; 3734 goto out; 3735 } 3736 3737 fep->stop_gpr.reg = out_val[1]; 3738 fep->stop_gpr.bit = out_val[2]; 3739 3740 out: 3741 of_node_put(gpr_np); 3742 3743 return ret; 3744 } 3745 3746 static int 3747 fec_probe(struct platform_device *pdev) 3748 { 3749 struct fec_enet_private *fep; 3750 struct fec_platform_data *pdata; 3751 phy_interface_t interface; 3752 struct net_device *ndev; 3753 int i, irq, ret = 0; 3754 const struct of_device_id *of_id; 3755 static int dev_id; 3756 struct device_node *np = pdev->dev.of_node, *phy_node; 3757 int num_tx_qs; 3758 int num_rx_qs; 3759 char irq_name[8]; 3760 int irq_cnt; 3761 struct fec_devinfo *dev_info; 3762 3763 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3764 3765 /* Init network device */ 3766 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 3767 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 3768 if (!ndev) 3769 return -ENOMEM; 3770 3771 SET_NETDEV_DEV(ndev, &pdev->dev); 3772 3773 /* setup board info structure */ 3774 fep = netdev_priv(ndev); 3775 3776 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3777 if (of_id) 3778 pdev->id_entry = of_id->data; 3779 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; 3780 if (dev_info) 3781 fep->quirks = dev_info->quirks; 3782 3783 fep->netdev = ndev; 3784 fep->num_rx_queues = num_rx_qs; 3785 fep->num_tx_queues = num_tx_qs; 3786 3787 #if !defined(CONFIG_M5272) 3788 /* default enable pause frame auto negotiation */ 3789 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3790 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3791 #endif 3792 3793 /* Select default pin state */ 3794 pinctrl_pm_select_default_state(&pdev->dev); 3795 3796 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 3797 if (IS_ERR(fep->hwp)) { 3798 ret = PTR_ERR(fep->hwp); 3799 goto failed_ioremap; 3800 } 3801 3802 fep->pdev = pdev; 3803 fep->dev_id = dev_id++; 3804 3805 platform_set_drvdata(pdev, ndev); 3806 3807 if ((of_machine_is_compatible("fsl,imx6q") || 3808 of_machine_is_compatible("fsl,imx6dl")) && 3809 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3810 fep->quirks |= FEC_QUIRK_ERR006687; 3811 3812 if (of_get_property(np, "fsl,magic-packet", NULL)) 3813 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3814 3815 ret = fec_enet_init_stop_mode(fep, np); 3816 if (ret) 3817 goto failed_stop_mode; 3818 3819 phy_node = of_parse_phandle(np, "phy-handle", 0); 3820 if (!phy_node && of_phy_is_fixed_link(np)) { 3821 ret = of_phy_register_fixed_link(np); 3822 if (ret < 0) { 3823 dev_err(&pdev->dev, 3824 "broken fixed-link specification\n"); 3825 goto failed_phy; 3826 } 3827 phy_node = of_node_get(np); 3828 } 3829 fep->phy_node = phy_node; 3830 3831 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 3832 if (ret) { 3833 pdata = dev_get_platdata(&pdev->dev); 3834 if (pdata) 3835 fep->phy_interface = pdata->phy; 3836 else 3837 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3838 } else { 3839 fep->phy_interface = interface; 3840 } 3841 3842 ret = fec_enet_parse_rgmii_delay(fep, np); 3843 if (ret) 3844 goto failed_rgmii_delay; 3845 3846 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3847 if (IS_ERR(fep->clk_ipg)) { 3848 ret = PTR_ERR(fep->clk_ipg); 3849 goto failed_clk; 3850 } 3851 3852 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3853 if (IS_ERR(fep->clk_ahb)) { 3854 ret = PTR_ERR(fep->clk_ahb); 3855 goto failed_clk; 3856 } 3857 3858 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3859 3860 /* enet_out is optional, depends on board */ 3861 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3862 if (IS_ERR(fep->clk_enet_out)) 3863 fep->clk_enet_out = NULL; 3864 3865 fep->ptp_clk_on = false; 3866 mutex_init(&fep->ptp_clk_mutex); 3867 3868 /* clk_ref is optional, depends on board */ 3869 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3870 if (IS_ERR(fep->clk_ref)) 3871 fep->clk_ref = NULL; 3872 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 3873 3874 /* clk_2x_txclk is optional, depends on board */ 3875 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 3876 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 3877 if (IS_ERR(fep->clk_2x_txclk)) 3878 fep->clk_2x_txclk = NULL; 3879 } 3880 3881 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3882 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3883 if (IS_ERR(fep->clk_ptp)) { 3884 fep->clk_ptp = NULL; 3885 fep->bufdesc_ex = false; 3886 } 3887 3888 ret = fec_enet_clk_enable(ndev, true); 3889 if (ret) 3890 goto failed_clk; 3891 3892 ret = clk_prepare_enable(fep->clk_ipg); 3893 if (ret) 3894 goto failed_clk_ipg; 3895 ret = clk_prepare_enable(fep->clk_ahb); 3896 if (ret) 3897 goto failed_clk_ahb; 3898 3899 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 3900 if (!IS_ERR(fep->reg_phy)) { 3901 ret = regulator_enable(fep->reg_phy); 3902 if (ret) { 3903 dev_err(&pdev->dev, 3904 "Failed to enable phy regulator: %d\n", ret); 3905 goto failed_regulator; 3906 } 3907 } else { 3908 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 3909 ret = -EPROBE_DEFER; 3910 goto failed_regulator; 3911 } 3912 fep->reg_phy = NULL; 3913 } 3914 3915 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3916 pm_runtime_use_autosuspend(&pdev->dev); 3917 pm_runtime_get_noresume(&pdev->dev); 3918 pm_runtime_set_active(&pdev->dev); 3919 pm_runtime_enable(&pdev->dev); 3920 3921 ret = fec_reset_phy(pdev); 3922 if (ret) 3923 goto failed_reset; 3924 3925 irq_cnt = fec_enet_get_irq_cnt(pdev); 3926 if (fep->bufdesc_ex) 3927 fec_ptp_init(pdev, irq_cnt); 3928 3929 ret = fec_enet_init(ndev); 3930 if (ret) 3931 goto failed_init; 3932 3933 for (i = 0; i < irq_cnt; i++) { 3934 snprintf(irq_name, sizeof(irq_name), "int%d", i); 3935 irq = platform_get_irq_byname_optional(pdev, irq_name); 3936 if (irq < 0) 3937 irq = platform_get_irq(pdev, i); 3938 if (irq < 0) { 3939 ret = irq; 3940 goto failed_irq; 3941 } 3942 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3943 0, pdev->name, ndev); 3944 if (ret) 3945 goto failed_irq; 3946 3947 fep->irq[i] = irq; 3948 } 3949 3950 /* Decide which interrupt line is wakeup capable */ 3951 fec_enet_get_wakeup_irq(pdev); 3952 3953 ret = fec_enet_mii_init(pdev); 3954 if (ret) 3955 goto failed_mii_init; 3956 3957 /* Carrier starts down, phylib will bring it up */ 3958 netif_carrier_off(ndev); 3959 fec_enet_clk_enable(ndev, false); 3960 pinctrl_pm_select_sleep_state(&pdev->dev); 3961 3962 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN; 3963 3964 ret = register_netdev(ndev); 3965 if (ret) 3966 goto failed_register; 3967 3968 device_init_wakeup(&ndev->dev, fep->wol_flag & 3969 FEC_WOL_HAS_MAGIC_PACKET); 3970 3971 if (fep->bufdesc_ex && fep->ptp_clock) 3972 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3973 3974 fep->rx_copybreak = COPYBREAK_DEFAULT; 3975 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3976 3977 pm_runtime_mark_last_busy(&pdev->dev); 3978 pm_runtime_put_autosuspend(&pdev->dev); 3979 3980 return 0; 3981 3982 failed_register: 3983 fec_enet_mii_remove(fep); 3984 failed_mii_init: 3985 failed_irq: 3986 failed_init: 3987 fec_ptp_stop(pdev); 3988 failed_reset: 3989 pm_runtime_put_noidle(&pdev->dev); 3990 pm_runtime_disable(&pdev->dev); 3991 if (fep->reg_phy) 3992 regulator_disable(fep->reg_phy); 3993 failed_regulator: 3994 clk_disable_unprepare(fep->clk_ahb); 3995 failed_clk_ahb: 3996 clk_disable_unprepare(fep->clk_ipg); 3997 failed_clk_ipg: 3998 fec_enet_clk_enable(ndev, false); 3999 failed_clk: 4000 failed_rgmii_delay: 4001 if (of_phy_is_fixed_link(np)) 4002 of_phy_deregister_fixed_link(np); 4003 of_node_put(phy_node); 4004 failed_stop_mode: 4005 failed_phy: 4006 dev_id--; 4007 failed_ioremap: 4008 free_netdev(ndev); 4009 4010 return ret; 4011 } 4012 4013 static int 4014 fec_drv_remove(struct platform_device *pdev) 4015 { 4016 struct net_device *ndev = platform_get_drvdata(pdev); 4017 struct fec_enet_private *fep = netdev_priv(ndev); 4018 struct device_node *np = pdev->dev.of_node; 4019 int ret; 4020 4021 ret = pm_runtime_resume_and_get(&pdev->dev); 4022 if (ret < 0) 4023 return ret; 4024 4025 cancel_work_sync(&fep->tx_timeout_work); 4026 fec_ptp_stop(pdev); 4027 unregister_netdev(ndev); 4028 fec_enet_mii_remove(fep); 4029 if (fep->reg_phy) 4030 regulator_disable(fep->reg_phy); 4031 4032 if (of_phy_is_fixed_link(np)) 4033 of_phy_deregister_fixed_link(np); 4034 of_node_put(fep->phy_node); 4035 4036 clk_disable_unprepare(fep->clk_ahb); 4037 clk_disable_unprepare(fep->clk_ipg); 4038 pm_runtime_put_noidle(&pdev->dev); 4039 pm_runtime_disable(&pdev->dev); 4040 4041 free_netdev(ndev); 4042 return 0; 4043 } 4044 4045 static int __maybe_unused fec_suspend(struct device *dev) 4046 { 4047 struct net_device *ndev = dev_get_drvdata(dev); 4048 struct fec_enet_private *fep = netdev_priv(ndev); 4049 4050 rtnl_lock(); 4051 if (netif_running(ndev)) { 4052 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4053 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4054 phy_stop(ndev->phydev); 4055 napi_disable(&fep->napi); 4056 netif_tx_lock_bh(ndev); 4057 netif_device_detach(ndev); 4058 netif_tx_unlock_bh(ndev); 4059 fec_stop(ndev); 4060 fec_enet_clk_enable(ndev, false); 4061 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4062 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4063 } 4064 rtnl_unlock(); 4065 4066 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4067 regulator_disable(fep->reg_phy); 4068 4069 /* SOC supply clock to phy, when clock is disabled, phy link down 4070 * SOC control phy regulator, when regulator is disabled, phy link down 4071 */ 4072 if (fep->clk_enet_out || fep->reg_phy) 4073 fep->link = 0; 4074 4075 return 0; 4076 } 4077 4078 static int __maybe_unused fec_resume(struct device *dev) 4079 { 4080 struct net_device *ndev = dev_get_drvdata(dev); 4081 struct fec_enet_private *fep = netdev_priv(ndev); 4082 int ret; 4083 int val; 4084 4085 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4086 ret = regulator_enable(fep->reg_phy); 4087 if (ret) 4088 return ret; 4089 } 4090 4091 rtnl_lock(); 4092 if (netif_running(ndev)) { 4093 ret = fec_enet_clk_enable(ndev, true); 4094 if (ret) { 4095 rtnl_unlock(); 4096 goto failed_clk; 4097 } 4098 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4099 fec_enet_stop_mode(fep, false); 4100 4101 val = readl(fep->hwp + FEC_ECNTRL); 4102 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4103 writel(val, fep->hwp + FEC_ECNTRL); 4104 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4105 } else { 4106 pinctrl_pm_select_default_state(&fep->pdev->dev); 4107 } 4108 fec_restart(ndev); 4109 netif_tx_lock_bh(ndev); 4110 netif_device_attach(ndev); 4111 netif_tx_unlock_bh(ndev); 4112 napi_enable(&fep->napi); 4113 phy_init_hw(ndev->phydev); 4114 phy_start(ndev->phydev); 4115 } 4116 rtnl_unlock(); 4117 4118 return 0; 4119 4120 failed_clk: 4121 if (fep->reg_phy) 4122 regulator_disable(fep->reg_phy); 4123 return ret; 4124 } 4125 4126 static int __maybe_unused fec_runtime_suspend(struct device *dev) 4127 { 4128 struct net_device *ndev = dev_get_drvdata(dev); 4129 struct fec_enet_private *fep = netdev_priv(ndev); 4130 4131 clk_disable_unprepare(fep->clk_ahb); 4132 clk_disable_unprepare(fep->clk_ipg); 4133 4134 return 0; 4135 } 4136 4137 static int __maybe_unused fec_runtime_resume(struct device *dev) 4138 { 4139 struct net_device *ndev = dev_get_drvdata(dev); 4140 struct fec_enet_private *fep = netdev_priv(ndev); 4141 int ret; 4142 4143 ret = clk_prepare_enable(fep->clk_ahb); 4144 if (ret) 4145 return ret; 4146 ret = clk_prepare_enable(fep->clk_ipg); 4147 if (ret) 4148 goto failed_clk_ipg; 4149 4150 return 0; 4151 4152 failed_clk_ipg: 4153 clk_disable_unprepare(fep->clk_ahb); 4154 return ret; 4155 } 4156 4157 static const struct dev_pm_ops fec_pm_ops = { 4158 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4159 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4160 }; 4161 4162 static struct platform_driver fec_driver = { 4163 .driver = { 4164 .name = DRIVER_NAME, 4165 .pm = &fec_pm_ops, 4166 .of_match_table = fec_dt_ids, 4167 .suppress_bind_attrs = true, 4168 }, 4169 .id_table = fec_devtype, 4170 .probe = fec_probe, 4171 .remove = fec_drv_remove, 4172 }; 4173 4174 module_platform_driver(fec_driver); 4175 4176 MODULE_LICENSE("GPL"); 4177