1 /* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 * 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/string.h> 27 #include <linux/ptrace.h> 28 #include <linux/errno.h> 29 #include <linux/ioport.h> 30 #include <linux/slab.h> 31 #include <linux/interrupt.h> 32 #include <linux/delay.h> 33 #include <linux/netdevice.h> 34 #include <linux/etherdevice.h> 35 #include <linux/skbuff.h> 36 #include <linux/in.h> 37 #include <linux/ip.h> 38 #include <net/ip.h> 39 #include <net/tso.h> 40 #include <linux/tcp.h> 41 #include <linux/udp.h> 42 #include <linux/icmp.h> 43 #include <linux/spinlock.h> 44 #include <linux/workqueue.h> 45 #include <linux/bitops.h> 46 #include <linux/io.h> 47 #include <linux/irq.h> 48 #include <linux/clk.h> 49 #include <linux/platform_device.h> 50 #include <linux/phy.h> 51 #include <linux/fec.h> 52 #include <linux/of.h> 53 #include <linux/of_device.h> 54 #include <linux/of_gpio.h> 55 #include <linux/of_net.h> 56 #include <linux/regulator/consumer.h> 57 #include <linux/if_vlan.h> 58 #include <linux/pinctrl/consumer.h> 59 60 #include <asm/cacheflush.h> 61 62 #include "fec.h" 63 64 static void set_multicast_list(struct net_device *ndev); 65 66 #if defined(CONFIG_ARM) 67 #define FEC_ALIGNMENT 0xf 68 #else 69 #define FEC_ALIGNMENT 0x3 70 #endif 71 72 #define DRIVER_NAME "fec" 73 74 /* Pause frame feild and FIFO threshold */ 75 #define FEC_ENET_FCE (1 << 5) 76 #define FEC_ENET_RSEM_V 0x84 77 #define FEC_ENET_RSFL_V 16 78 #define FEC_ENET_RAEM_V 0x8 79 #define FEC_ENET_RAFL_V 0x8 80 #define FEC_ENET_OPD_V 0xFFF0 81 82 /* Controller is ENET-MAC */ 83 #define FEC_QUIRK_ENET_MAC (1 << 0) 84 /* Controller needs driver to swap frame */ 85 #define FEC_QUIRK_SWAP_FRAME (1 << 1) 86 /* Controller uses gasket */ 87 #define FEC_QUIRK_USE_GASKET (1 << 2) 88 /* Controller has GBIT support */ 89 #define FEC_QUIRK_HAS_GBIT (1 << 3) 90 /* Controller has extend desc buffer */ 91 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) 92 /* Controller has hardware checksum support */ 93 #define FEC_QUIRK_HAS_CSUM (1 << 5) 94 /* Controller has hardware vlan support */ 95 #define FEC_QUIRK_HAS_VLAN (1 << 6) 96 /* ENET IP errata ERR006358 97 * 98 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously 99 * detected as not set during a prior frame transmission, then the 100 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs 101 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in 102 * frames not being transmitted until there is a 0-to-1 transition on 103 * ENET_TDAR[TDAR]. 104 */ 105 #define FEC_QUIRK_ERR006358 (1 << 7) 106 107 static struct platform_device_id fec_devtype[] = { 108 { 109 /* keep it for coldfire */ 110 .name = DRIVER_NAME, 111 .driver_data = 0, 112 }, { 113 .name = "imx25-fec", 114 .driver_data = FEC_QUIRK_USE_GASKET, 115 }, { 116 .name = "imx27-fec", 117 .driver_data = 0, 118 }, { 119 .name = "imx28-fec", 120 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, 121 }, { 122 .name = "imx6q-fec", 123 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 124 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 125 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358, 126 }, { 127 .name = "mvf600-fec", 128 .driver_data = FEC_QUIRK_ENET_MAC, 129 }, { 130 /* sentinel */ 131 } 132 }; 133 MODULE_DEVICE_TABLE(platform, fec_devtype); 134 135 enum imx_fec_type { 136 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 137 IMX27_FEC, /* runs on i.mx27/35/51 */ 138 IMX28_FEC, 139 IMX6Q_FEC, 140 MVF600_FEC, 141 }; 142 143 static const struct of_device_id fec_dt_ids[] = { 144 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 145 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 146 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 147 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 148 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 149 { /* sentinel */ } 150 }; 151 MODULE_DEVICE_TABLE(of, fec_dt_ids); 152 153 static unsigned char macaddr[ETH_ALEN]; 154 module_param_array(macaddr, byte, NULL, 0); 155 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 156 157 #if defined(CONFIG_M5272) 158 /* 159 * Some hardware gets it MAC address out of local flash memory. 160 * if this is non-zero then assume it is the address to get MAC from. 161 */ 162 #if defined(CONFIG_NETtel) 163 #define FEC_FLASHMAC 0xf0006006 164 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 165 #define FEC_FLASHMAC 0xf0006000 166 #elif defined(CONFIG_CANCam) 167 #define FEC_FLASHMAC 0xf0020000 168 #elif defined (CONFIG_M5272C3) 169 #define FEC_FLASHMAC (0xffe04000 + 4) 170 #elif defined(CONFIG_MOD5272) 171 #define FEC_FLASHMAC 0xffc0406b 172 #else 173 #define FEC_FLASHMAC 0 174 #endif 175 #endif /* CONFIG_M5272 */ 176 177 /* Interrupt events/masks. */ 178 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ 179 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ 180 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ 181 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ 182 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ 183 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ 184 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ 185 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ 186 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ 187 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ 188 189 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) 190 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) 191 192 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 193 */ 194 #define PKT_MAXBUF_SIZE 1522 195 #define PKT_MINBUF_SIZE 64 196 #define PKT_MAXBLR_SIZE 1536 197 198 /* FEC receive acceleration */ 199 #define FEC_RACC_IPDIS (1 << 1) 200 #define FEC_RACC_PRODIS (1 << 2) 201 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 202 203 /* 204 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 205 * size bits. Other FEC hardware does not, so we need to take that into 206 * account when setting it. 207 */ 208 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 209 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 210 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 211 #else 212 #define OPT_FRAME_SIZE 0 213 #endif 214 215 /* FEC MII MMFR bits definition */ 216 #define FEC_MMFR_ST (1 << 30) 217 #define FEC_MMFR_OP_READ (2 << 28) 218 #define FEC_MMFR_OP_WRITE (1 << 28) 219 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 220 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 221 #define FEC_MMFR_TA (2 << 16) 222 #define FEC_MMFR_DATA(v) (v & 0xffff) 223 224 #define FEC_MII_TIMEOUT 30000 /* us */ 225 226 /* Transmitter timeout */ 227 #define TX_TIMEOUT (2 * HZ) 228 229 #define FEC_PAUSE_FLAG_AUTONEG 0x1 230 #define FEC_PAUSE_FLAG_ENABLE 0x2 231 232 #define TSO_HEADER_SIZE 128 233 /* Max number of allowed TCP segments for software TSO */ 234 #define FEC_MAX_TSO_SEGS 100 235 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 236 237 #define IS_TSO_HEADER(txq, addr) \ 238 ((addr >= txq->tso_hdrs_dma) && \ 239 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE)) 240 241 static int mii_cnt; 242 243 static inline 244 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep) 245 { 246 struct bufdesc *new_bd = bdp + 1; 247 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1; 248 struct bufdesc_ex *ex_base; 249 struct bufdesc *base; 250 int ring_size; 251 252 if (bdp >= fep->tx_bd_base) { 253 base = fep->tx_bd_base; 254 ring_size = fep->tx_ring_size; 255 ex_base = (struct bufdesc_ex *)fep->tx_bd_base; 256 } else { 257 base = fep->rx_bd_base; 258 ring_size = fep->rx_ring_size; 259 ex_base = (struct bufdesc_ex *)fep->rx_bd_base; 260 } 261 262 if (fep->bufdesc_ex) 263 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ? 264 ex_base : ex_new_bd); 265 else 266 return (new_bd >= (base + ring_size)) ? 267 base : new_bd; 268 } 269 270 static inline 271 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep) 272 { 273 struct bufdesc *new_bd = bdp - 1; 274 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1; 275 struct bufdesc_ex *ex_base; 276 struct bufdesc *base; 277 int ring_size; 278 279 if (bdp >= fep->tx_bd_base) { 280 base = fep->tx_bd_base; 281 ring_size = fep->tx_ring_size; 282 ex_base = (struct bufdesc_ex *)fep->tx_bd_base; 283 } else { 284 base = fep->rx_bd_base; 285 ring_size = fep->rx_ring_size; 286 ex_base = (struct bufdesc_ex *)fep->rx_bd_base; 287 } 288 289 if (fep->bufdesc_ex) 290 return (struct bufdesc *)((ex_new_bd < ex_base) ? 291 (ex_new_bd + ring_size) : ex_new_bd); 292 else 293 return (new_bd < base) ? (new_bd + ring_size) : new_bd; 294 } 295 296 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp, 297 struct fec_enet_private *fep) 298 { 299 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size; 300 } 301 302 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep) 303 { 304 int entries; 305 306 entries = ((const char *)fep->dirty_tx - 307 (const char *)fep->cur_tx) / fep->bufdesc_size - 1; 308 309 return entries > 0 ? entries : entries + fep->tx_ring_size; 310 } 311 312 static void *swap_buffer(void *bufaddr, int len) 313 { 314 int i; 315 unsigned int *buf = bufaddr; 316 317 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++) 318 *buf = cpu_to_be32(*buf); 319 320 return bufaddr; 321 } 322 323 static inline bool is_ipv4_pkt(struct sk_buff *skb) 324 { 325 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 326 } 327 328 static int 329 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 330 { 331 /* Only run for packets requiring a checksum. */ 332 if (skb->ip_summed != CHECKSUM_PARTIAL) 333 return 0; 334 335 if (unlikely(skb_cow_head(skb, 0))) 336 return -1; 337 338 if (is_ipv4_pkt(skb)) 339 ip_hdr(skb)->check = 0; 340 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 341 342 return 0; 343 } 344 345 static void 346 fec_enet_submit_work(struct bufdesc *bdp, struct fec_enet_private *fep) 347 { 348 const struct platform_device_id *id_entry = 349 platform_get_device_id(fep->pdev); 350 struct bufdesc *bdp_pre; 351 352 bdp_pre = fec_enet_get_prevdesc(bdp, fep); 353 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) && 354 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) { 355 fep->delay_work.trig_tx = true; 356 schedule_delayed_work(&(fep->delay_work.delay_work), 357 msecs_to_jiffies(1)); 358 } 359 } 360 361 static int 362 fec_enet_txq_submit_frag_skb(struct sk_buff *skb, struct net_device *ndev) 363 { 364 struct fec_enet_private *fep = netdev_priv(ndev); 365 const struct platform_device_id *id_entry = 366 platform_get_device_id(fep->pdev); 367 struct bufdesc *bdp = fep->cur_tx; 368 struct bufdesc_ex *ebdp; 369 int nr_frags = skb_shinfo(skb)->nr_frags; 370 int frag, frag_len; 371 unsigned short status; 372 unsigned int estatus = 0; 373 skb_frag_t *this_frag; 374 unsigned int index; 375 void *bufaddr; 376 int i; 377 378 for (frag = 0; frag < nr_frags; frag++) { 379 this_frag = &skb_shinfo(skb)->frags[frag]; 380 bdp = fec_enet_get_nextdesc(bdp, fep); 381 ebdp = (struct bufdesc_ex *)bdp; 382 383 status = bdp->cbd_sc; 384 status &= ~BD_ENET_TX_STATS; 385 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 386 frag_len = skb_shinfo(skb)->frags[frag].size; 387 388 /* Handle the last BD specially */ 389 if (frag == nr_frags - 1) { 390 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 391 if (fep->bufdesc_ex) { 392 estatus |= BD_ENET_TX_INT; 393 if (unlikely(skb_shinfo(skb)->tx_flags & 394 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 395 estatus |= BD_ENET_TX_TS; 396 } 397 } 398 399 if (fep->bufdesc_ex) { 400 if (skb->ip_summed == CHECKSUM_PARTIAL) 401 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 402 ebdp->cbd_bdu = 0; 403 ebdp->cbd_esc = estatus; 404 } 405 406 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset; 407 408 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep); 409 if (((unsigned long) bufaddr) & FEC_ALIGNMENT || 410 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) { 411 memcpy(fep->tx_bounce[index], bufaddr, frag_len); 412 bufaddr = fep->tx_bounce[index]; 413 414 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 415 swap_buffer(bufaddr, frag_len); 416 } 417 418 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, 419 frag_len, DMA_TO_DEVICE); 420 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) { 421 dev_kfree_skb_any(skb); 422 if (net_ratelimit()) 423 netdev_err(ndev, "Tx DMA memory map failed\n"); 424 goto dma_mapping_error; 425 } 426 427 bdp->cbd_datlen = frag_len; 428 bdp->cbd_sc = status; 429 } 430 431 fep->cur_tx = bdp; 432 433 return 0; 434 435 dma_mapping_error: 436 bdp = fep->cur_tx; 437 for (i = 0; i < frag; i++) { 438 bdp = fec_enet_get_nextdesc(bdp, fep); 439 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 440 bdp->cbd_datlen, DMA_TO_DEVICE); 441 } 442 return NETDEV_TX_OK; 443 } 444 445 static int fec_enet_txq_submit_skb(struct sk_buff *skb, struct net_device *ndev) 446 { 447 struct fec_enet_private *fep = netdev_priv(ndev); 448 const struct platform_device_id *id_entry = 449 platform_get_device_id(fep->pdev); 450 int nr_frags = skb_shinfo(skb)->nr_frags; 451 struct bufdesc *bdp, *last_bdp; 452 void *bufaddr; 453 unsigned short status; 454 unsigned short buflen; 455 unsigned int estatus = 0; 456 unsigned int index; 457 int entries_free; 458 int ret; 459 460 entries_free = fec_enet_get_free_txdesc_num(fep); 461 if (entries_free < MAX_SKB_FRAGS + 1) { 462 dev_kfree_skb_any(skb); 463 if (net_ratelimit()) 464 netdev_err(ndev, "NOT enough BD for SG!\n"); 465 return NETDEV_TX_OK; 466 } 467 468 /* Protocol checksum off-load for TCP and UDP. */ 469 if (fec_enet_clear_csum(skb, ndev)) { 470 dev_kfree_skb_any(skb); 471 return NETDEV_TX_OK; 472 } 473 474 /* Fill in a Tx ring entry */ 475 bdp = fep->cur_tx; 476 status = bdp->cbd_sc; 477 status &= ~BD_ENET_TX_STATS; 478 479 /* Set buffer length and buffer pointer */ 480 bufaddr = skb->data; 481 buflen = skb_headlen(skb); 482 483 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep); 484 if (((unsigned long) bufaddr) & FEC_ALIGNMENT || 485 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) { 486 memcpy(fep->tx_bounce[index], skb->data, buflen); 487 bufaddr = fep->tx_bounce[index]; 488 489 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 490 swap_buffer(bufaddr, buflen); 491 } 492 493 /* Push the data cache so the CPM does not get stale memory 494 * data. 495 */ 496 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, 497 buflen, DMA_TO_DEVICE); 498 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) { 499 dev_kfree_skb_any(skb); 500 if (net_ratelimit()) 501 netdev_err(ndev, "Tx DMA memory map failed\n"); 502 return NETDEV_TX_OK; 503 } 504 505 if (nr_frags) { 506 ret = fec_enet_txq_submit_frag_skb(skb, ndev); 507 if (ret) 508 return ret; 509 } else { 510 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 511 if (fep->bufdesc_ex) { 512 estatus = BD_ENET_TX_INT; 513 if (unlikely(skb_shinfo(skb)->tx_flags & 514 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 515 estatus |= BD_ENET_TX_TS; 516 } 517 } 518 519 if (fep->bufdesc_ex) { 520 521 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 522 523 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 524 fep->hwts_tx_en)) 525 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 526 527 if (skb->ip_summed == CHECKSUM_PARTIAL) 528 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 529 530 ebdp->cbd_bdu = 0; 531 ebdp->cbd_esc = estatus; 532 } 533 534 last_bdp = fep->cur_tx; 535 index = fec_enet_get_bd_index(fep->tx_bd_base, last_bdp, fep); 536 /* Save skb pointer */ 537 fep->tx_skbuff[index] = skb; 538 539 bdp->cbd_datlen = buflen; 540 541 /* Send it on its way. Tell FEC it's ready, interrupt when done, 542 * it's the last BD of the frame, and to put the CRC on the end. 543 */ 544 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 545 bdp->cbd_sc = status; 546 547 fec_enet_submit_work(bdp, fep); 548 549 /* If this was the last BD in the ring, start at the beginning again. */ 550 bdp = fec_enet_get_nextdesc(last_bdp, fep); 551 552 skb_tx_timestamp(skb); 553 554 fep->cur_tx = bdp; 555 556 /* Trigger transmission start */ 557 writel(0, fep->hwp + FEC_X_DES_ACTIVE); 558 559 return 0; 560 } 561 562 static int 563 fec_enet_txq_put_data_tso(struct sk_buff *skb, struct net_device *ndev, 564 struct bufdesc *bdp, int index, char *data, 565 int size, bool last_tcp, bool is_last) 566 { 567 struct fec_enet_private *fep = netdev_priv(ndev); 568 const struct platform_device_id *id_entry = 569 platform_get_device_id(fep->pdev); 570 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 571 unsigned short status; 572 unsigned int estatus = 0; 573 574 status = bdp->cbd_sc; 575 status &= ~BD_ENET_TX_STATS; 576 577 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 578 bdp->cbd_datlen = size; 579 580 if (((unsigned long) data) & FEC_ALIGNMENT || 581 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) { 582 memcpy(fep->tx_bounce[index], data, size); 583 data = fep->tx_bounce[index]; 584 585 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 586 swap_buffer(data, size); 587 } 588 589 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data, 590 size, DMA_TO_DEVICE); 591 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) { 592 dev_kfree_skb_any(skb); 593 if (net_ratelimit()) 594 netdev_err(ndev, "Tx DMA memory map failed\n"); 595 return NETDEV_TX_BUSY; 596 } 597 598 if (fep->bufdesc_ex) { 599 if (skb->ip_summed == CHECKSUM_PARTIAL) 600 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 601 ebdp->cbd_bdu = 0; 602 ebdp->cbd_esc = estatus; 603 } 604 605 /* Handle the last BD specially */ 606 if (last_tcp) 607 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 608 if (is_last) { 609 status |= BD_ENET_TX_INTR; 610 if (fep->bufdesc_ex) 611 ebdp->cbd_esc |= BD_ENET_TX_INT; 612 } 613 614 bdp->cbd_sc = status; 615 616 return 0; 617 } 618 619 static int 620 fec_enet_txq_put_hdr_tso(struct sk_buff *skb, struct net_device *ndev, 621 struct bufdesc *bdp, int index) 622 { 623 struct fec_enet_private *fep = netdev_priv(ndev); 624 const struct platform_device_id *id_entry = 625 platform_get_device_id(fep->pdev); 626 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 627 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 628 void *bufaddr; 629 unsigned long dmabuf; 630 unsigned short status; 631 unsigned int estatus = 0; 632 633 status = bdp->cbd_sc; 634 status &= ~BD_ENET_TX_STATS; 635 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 636 637 bufaddr = fep->tso_hdrs + index * TSO_HEADER_SIZE; 638 dmabuf = fep->tso_hdrs_dma + index * TSO_HEADER_SIZE; 639 if (((unsigned long) bufaddr) & FEC_ALIGNMENT || 640 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) { 641 memcpy(fep->tx_bounce[index], skb->data, hdr_len); 642 bufaddr = fep->tx_bounce[index]; 643 644 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 645 swap_buffer(bufaddr, hdr_len); 646 647 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 648 hdr_len, DMA_TO_DEVICE); 649 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 650 dev_kfree_skb_any(skb); 651 if (net_ratelimit()) 652 netdev_err(ndev, "Tx DMA memory map failed\n"); 653 return NETDEV_TX_BUSY; 654 } 655 } 656 657 bdp->cbd_bufaddr = dmabuf; 658 bdp->cbd_datlen = hdr_len; 659 660 if (fep->bufdesc_ex) { 661 if (skb->ip_summed == CHECKSUM_PARTIAL) 662 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 663 ebdp->cbd_bdu = 0; 664 ebdp->cbd_esc = estatus; 665 } 666 667 bdp->cbd_sc = status; 668 669 return 0; 670 } 671 672 static int fec_enet_txq_submit_tso(struct sk_buff *skb, struct net_device *ndev) 673 { 674 struct fec_enet_private *fep = netdev_priv(ndev); 675 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 676 int total_len, data_left; 677 struct bufdesc *bdp = fep->cur_tx; 678 struct tso_t tso; 679 unsigned int index = 0; 680 int ret; 681 682 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep)) { 683 dev_kfree_skb_any(skb); 684 if (net_ratelimit()) 685 netdev_err(ndev, "NOT enough BD for TSO!\n"); 686 return NETDEV_TX_OK; 687 } 688 689 /* Protocol checksum off-load for TCP and UDP. */ 690 if (fec_enet_clear_csum(skb, ndev)) { 691 dev_kfree_skb_any(skb); 692 return NETDEV_TX_OK; 693 } 694 695 /* Initialize the TSO handler, and prepare the first payload */ 696 tso_start(skb, &tso); 697 698 total_len = skb->len - hdr_len; 699 while (total_len > 0) { 700 char *hdr; 701 702 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep); 703 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 704 total_len -= data_left; 705 706 /* prepare packet headers: MAC + IP + TCP */ 707 hdr = fep->tso_hdrs + index * TSO_HEADER_SIZE; 708 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 709 ret = fec_enet_txq_put_hdr_tso(skb, ndev, bdp, index); 710 if (ret) 711 goto err_release; 712 713 while (data_left > 0) { 714 int size; 715 716 size = min_t(int, tso.size, data_left); 717 bdp = fec_enet_get_nextdesc(bdp, fep); 718 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep); 719 ret = fec_enet_txq_put_data_tso(skb, ndev, bdp, index, tso.data, 720 size, size == data_left, 721 total_len == 0); 722 if (ret) 723 goto err_release; 724 725 data_left -= size; 726 tso_build_data(skb, &tso, size); 727 } 728 729 bdp = fec_enet_get_nextdesc(bdp, fep); 730 } 731 732 /* Save skb pointer */ 733 fep->tx_skbuff[index] = skb; 734 735 fec_enet_submit_work(bdp, fep); 736 737 skb_tx_timestamp(skb); 738 fep->cur_tx = bdp; 739 740 /* Trigger transmission start */ 741 writel(0, fep->hwp + FEC_X_DES_ACTIVE); 742 743 return 0; 744 745 err_release: 746 /* TODO: Release all used data descriptors for TSO */ 747 return ret; 748 } 749 750 static netdev_tx_t 751 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 752 { 753 struct fec_enet_private *fep = netdev_priv(ndev); 754 int entries_free; 755 int ret; 756 757 if (skb_is_gso(skb)) 758 ret = fec_enet_txq_submit_tso(skb, ndev); 759 else 760 ret = fec_enet_txq_submit_skb(skb, ndev); 761 if (ret) 762 return ret; 763 764 entries_free = fec_enet_get_free_txdesc_num(fep); 765 if (entries_free <= fep->tx_stop_threshold) 766 netif_stop_queue(ndev); 767 768 return NETDEV_TX_OK; 769 } 770 771 /* Init RX & TX buffer descriptors 772 */ 773 static void fec_enet_bd_init(struct net_device *dev) 774 { 775 struct fec_enet_private *fep = netdev_priv(dev); 776 struct bufdesc *bdp; 777 unsigned int i; 778 779 /* Initialize the receive buffer descriptors. */ 780 bdp = fep->rx_bd_base; 781 for (i = 0; i < fep->rx_ring_size; i++) { 782 783 /* Initialize the BD for every fragment in the page. */ 784 if (bdp->cbd_bufaddr) 785 bdp->cbd_sc = BD_ENET_RX_EMPTY; 786 else 787 bdp->cbd_sc = 0; 788 bdp = fec_enet_get_nextdesc(bdp, fep); 789 } 790 791 /* Set the last buffer to wrap */ 792 bdp = fec_enet_get_prevdesc(bdp, fep); 793 bdp->cbd_sc |= BD_SC_WRAP; 794 795 fep->cur_rx = fep->rx_bd_base; 796 797 /* ...and the same for transmit */ 798 bdp = fep->tx_bd_base; 799 fep->cur_tx = bdp; 800 for (i = 0; i < fep->tx_ring_size; i++) { 801 802 /* Initialize the BD for every fragment in the page. */ 803 bdp->cbd_sc = 0; 804 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) { 805 dev_kfree_skb_any(fep->tx_skbuff[i]); 806 fep->tx_skbuff[i] = NULL; 807 } 808 bdp->cbd_bufaddr = 0; 809 bdp = fec_enet_get_nextdesc(bdp, fep); 810 } 811 812 /* Set the last buffer to wrap */ 813 bdp = fec_enet_get_prevdesc(bdp, fep); 814 bdp->cbd_sc |= BD_SC_WRAP; 815 fep->dirty_tx = bdp; 816 } 817 818 /* This function is called to start or restart the FEC during a link 819 * change. This only happens when switching between half and full 820 * duplex. 821 */ 822 static void 823 fec_restart(struct net_device *ndev, int duplex) 824 { 825 struct fec_enet_private *fep = netdev_priv(ndev); 826 const struct platform_device_id *id_entry = 827 platform_get_device_id(fep->pdev); 828 int i; 829 u32 val; 830 u32 temp_mac[2]; 831 u32 rcntl = OPT_FRAME_SIZE | 0x04; 832 u32 ecntl = 0x2; /* ETHEREN */ 833 834 if (netif_running(ndev)) { 835 netif_device_detach(ndev); 836 napi_disable(&fep->napi); 837 netif_stop_queue(ndev); 838 netif_tx_lock_bh(ndev); 839 } 840 841 /* Whack a reset. We should wait for this. */ 842 writel(1, fep->hwp + FEC_ECNTRL); 843 udelay(10); 844 845 /* 846 * enet-mac reset will reset mac address registers too, 847 * so need to reconfigure it. 848 */ 849 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 850 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 851 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); 852 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); 853 } 854 855 /* Clear any outstanding interrupt. */ 856 writel(0xffc00000, fep->hwp + FEC_IEVENT); 857 858 /* Set maximum receive buffer size. */ 859 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); 860 861 fec_enet_bd_init(ndev); 862 863 /* Set receive and transmit descriptor base. */ 864 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); 865 if (fep->bufdesc_ex) 866 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex) 867 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START); 868 else 869 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) 870 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START); 871 872 873 for (i = 0; i <= TX_RING_MOD_MASK; i++) { 874 if (fep->tx_skbuff[i]) { 875 dev_kfree_skb_any(fep->tx_skbuff[i]); 876 fep->tx_skbuff[i] = NULL; 877 } 878 } 879 880 /* Enable MII mode */ 881 if (duplex) { 882 /* FD enable */ 883 writel(0x04, fep->hwp + FEC_X_CNTRL); 884 } else { 885 /* No Rcv on Xmit */ 886 rcntl |= 0x02; 887 writel(0x0, fep->hwp + FEC_X_CNTRL); 888 } 889 890 fep->full_duplex = duplex; 891 892 /* Set MII speed */ 893 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 894 895 #if !defined(CONFIG_M5272) 896 /* set RX checksum */ 897 val = readl(fep->hwp + FEC_RACC); 898 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 899 val |= FEC_RACC_OPTIONS; 900 else 901 val &= ~FEC_RACC_OPTIONS; 902 writel(val, fep->hwp + FEC_RACC); 903 #endif 904 905 /* 906 * The phy interface and speed need to get configured 907 * differently on enet-mac. 908 */ 909 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 910 /* Enable flow control and length check */ 911 rcntl |= 0x40000000 | 0x00000020; 912 913 /* RGMII, RMII or MII */ 914 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) 915 rcntl |= (1 << 6); 916 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 917 rcntl |= (1 << 8); 918 else 919 rcntl &= ~(1 << 8); 920 921 /* 1G, 100M or 10M */ 922 if (fep->phy_dev) { 923 if (fep->phy_dev->speed == SPEED_1000) 924 ecntl |= (1 << 5); 925 else if (fep->phy_dev->speed == SPEED_100) 926 rcntl &= ~(1 << 9); 927 else 928 rcntl |= (1 << 9); 929 } 930 } else { 931 #ifdef FEC_MIIGSK_ENR 932 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { 933 u32 cfgr; 934 /* disable the gasket and wait */ 935 writel(0, fep->hwp + FEC_MIIGSK_ENR); 936 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 937 udelay(1); 938 939 /* 940 * configure the gasket: 941 * RMII, 50 MHz, no loopback, no echo 942 * MII, 25 MHz, no loopback, no echo 943 */ 944 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 945 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 946 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) 947 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 948 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 949 950 /* re-enable the gasket */ 951 writel(2, fep->hwp + FEC_MIIGSK_ENR); 952 } 953 #endif 954 } 955 956 #if !defined(CONFIG_M5272) 957 /* enable pause frame*/ 958 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 959 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 960 fep->phy_dev && fep->phy_dev->pause)) { 961 rcntl |= FEC_ENET_FCE; 962 963 /* set FIFO threshold parameter to reduce overrun */ 964 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 965 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 966 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 967 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 968 969 /* OPD */ 970 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 971 } else { 972 rcntl &= ~FEC_ENET_FCE; 973 } 974 #endif /* !defined(CONFIG_M5272) */ 975 976 writel(rcntl, fep->hwp + FEC_R_CNTRL); 977 978 /* Setup multicast filter. */ 979 set_multicast_list(ndev); 980 #ifndef CONFIG_M5272 981 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 982 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 983 #endif 984 985 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 986 /* enable ENET endian swap */ 987 ecntl |= (1 << 8); 988 /* enable ENET store and forward mode */ 989 writel(1 << 8, fep->hwp + FEC_X_WMRK); 990 } 991 992 if (fep->bufdesc_ex) 993 ecntl |= (1 << 4); 994 995 #ifndef CONFIG_M5272 996 /* Enable the MIB statistic event counters */ 997 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 998 #endif 999 1000 /* And last, enable the transmit and receive processing */ 1001 writel(ecntl, fep->hwp + FEC_ECNTRL); 1002 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 1003 1004 if (fep->bufdesc_ex) 1005 fec_ptp_start_cyclecounter(ndev); 1006 1007 /* Enable interrupts we wish to service */ 1008 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1009 1010 if (netif_running(ndev)) { 1011 netif_tx_unlock_bh(ndev); 1012 netif_wake_queue(ndev); 1013 napi_enable(&fep->napi); 1014 netif_device_attach(ndev); 1015 } 1016 } 1017 1018 static void 1019 fec_stop(struct net_device *ndev) 1020 { 1021 struct fec_enet_private *fep = netdev_priv(ndev); 1022 const struct platform_device_id *id_entry = 1023 platform_get_device_id(fep->pdev); 1024 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1025 1026 /* We cannot expect a graceful transmit stop without link !!! */ 1027 if (fep->link) { 1028 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1029 udelay(10); 1030 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1031 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1032 } 1033 1034 /* Whack a reset. We should wait for this. */ 1035 writel(1, fep->hwp + FEC_ECNTRL); 1036 udelay(10); 1037 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1038 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1039 1040 /* We have to keep ENET enabled to have MII interrupt stay working */ 1041 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 1042 writel(2, fep->hwp + FEC_ECNTRL); 1043 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1044 } 1045 } 1046 1047 1048 static void 1049 fec_timeout(struct net_device *ndev) 1050 { 1051 struct fec_enet_private *fep = netdev_priv(ndev); 1052 1053 ndev->stats.tx_errors++; 1054 1055 fep->delay_work.timeout = true; 1056 schedule_delayed_work(&(fep->delay_work.delay_work), 0); 1057 } 1058 1059 static void fec_enet_work(struct work_struct *work) 1060 { 1061 struct fec_enet_private *fep = 1062 container_of(work, 1063 struct fec_enet_private, 1064 delay_work.delay_work.work); 1065 1066 if (fep->delay_work.timeout) { 1067 fep->delay_work.timeout = false; 1068 fec_restart(fep->netdev, fep->full_duplex); 1069 netif_wake_queue(fep->netdev); 1070 } 1071 1072 if (fep->delay_work.trig_tx) { 1073 fep->delay_work.trig_tx = false; 1074 writel(0, fep->hwp + FEC_X_DES_ACTIVE); 1075 } 1076 } 1077 1078 static void 1079 fec_enet_tx(struct net_device *ndev) 1080 { 1081 struct fec_enet_private *fep; 1082 struct bufdesc *bdp; 1083 unsigned short status; 1084 struct sk_buff *skb; 1085 int index = 0; 1086 int entries_free; 1087 1088 fep = netdev_priv(ndev); 1089 bdp = fep->dirty_tx; 1090 1091 /* get next bdp of dirty_tx */ 1092 bdp = fec_enet_get_nextdesc(bdp, fep); 1093 1094 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { 1095 1096 /* current queue is empty */ 1097 if (bdp == fep->cur_tx) 1098 break; 1099 1100 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep); 1101 1102 skb = fep->tx_skbuff[index]; 1103 if (!IS_TSO_HEADER(fep, bdp->cbd_bufaddr)) 1104 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 1105 bdp->cbd_datlen, DMA_TO_DEVICE); 1106 bdp->cbd_bufaddr = 0; 1107 if (!skb) { 1108 bdp = fec_enet_get_nextdesc(bdp, fep); 1109 continue; 1110 } 1111 1112 /* Check for errors. */ 1113 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1114 BD_ENET_TX_RL | BD_ENET_TX_UN | 1115 BD_ENET_TX_CSL)) { 1116 ndev->stats.tx_errors++; 1117 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1118 ndev->stats.tx_heartbeat_errors++; 1119 if (status & BD_ENET_TX_LC) /* Late collision */ 1120 ndev->stats.tx_window_errors++; 1121 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1122 ndev->stats.tx_aborted_errors++; 1123 if (status & BD_ENET_TX_UN) /* Underrun */ 1124 ndev->stats.tx_fifo_errors++; 1125 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1126 ndev->stats.tx_carrier_errors++; 1127 } else { 1128 ndev->stats.tx_packets++; 1129 ndev->stats.tx_bytes += skb->len; 1130 } 1131 1132 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 1133 fep->bufdesc_ex) { 1134 struct skb_shared_hwtstamps shhwtstamps; 1135 unsigned long flags; 1136 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1137 1138 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 1139 spin_lock_irqsave(&fep->tmreg_lock, flags); 1140 shhwtstamps.hwtstamp = ns_to_ktime( 1141 timecounter_cyc2time(&fep->tc, ebdp->ts)); 1142 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1143 skb_tstamp_tx(skb, &shhwtstamps); 1144 } 1145 1146 if (status & BD_ENET_TX_READY) 1147 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n"); 1148 1149 /* Deferred means some collisions occurred during transmit, 1150 * but we eventually sent the packet OK. 1151 */ 1152 if (status & BD_ENET_TX_DEF) 1153 ndev->stats.collisions++; 1154 1155 /* Free the sk buffer associated with this last transmit */ 1156 dev_kfree_skb_any(skb); 1157 fep->tx_skbuff[index] = NULL; 1158 1159 fep->dirty_tx = bdp; 1160 1161 /* Update pointer to next buffer descriptor to be transmitted */ 1162 bdp = fec_enet_get_nextdesc(bdp, fep); 1163 1164 /* Since we have freed up a buffer, the ring is no longer full 1165 */ 1166 if (netif_queue_stopped(ndev)) { 1167 entries_free = fec_enet_get_free_txdesc_num(fep); 1168 if (entries_free >= fep->tx_wake_threshold) 1169 netif_wake_queue(ndev); 1170 } 1171 } 1172 return; 1173 } 1174 1175 /* During a receive, the cur_rx points to the current incoming buffer. 1176 * When we update through the ring, if the next incoming buffer has 1177 * not been given to the system, we just set the empty indicator, 1178 * effectively tossing the packet. 1179 */ 1180 static int 1181 fec_enet_rx(struct net_device *ndev, int budget) 1182 { 1183 struct fec_enet_private *fep = netdev_priv(ndev); 1184 const struct platform_device_id *id_entry = 1185 platform_get_device_id(fep->pdev); 1186 struct bufdesc *bdp; 1187 unsigned short status; 1188 struct sk_buff *skb; 1189 ushort pkt_len; 1190 __u8 *data; 1191 int pkt_received = 0; 1192 struct bufdesc_ex *ebdp = NULL; 1193 bool vlan_packet_rcvd = false; 1194 u16 vlan_tag; 1195 int index = 0; 1196 1197 #ifdef CONFIG_M532x 1198 flush_cache_all(); 1199 #endif 1200 1201 /* First, grab all of the stats for the incoming packet. 1202 * These get messed up if we get called due to a busy condition. 1203 */ 1204 bdp = fep->cur_rx; 1205 1206 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { 1207 1208 if (pkt_received >= budget) 1209 break; 1210 pkt_received++; 1211 1212 /* Since we have allocated space to hold a complete frame, 1213 * the last indicator should be set. 1214 */ 1215 if ((status & BD_ENET_RX_LAST) == 0) 1216 netdev_err(ndev, "rcv is not +last\n"); 1217 1218 if (!fep->opened) 1219 goto rx_processing_done; 1220 1221 /* Check for errors. */ 1222 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1223 BD_ENET_RX_CR | BD_ENET_RX_OV)) { 1224 ndev->stats.rx_errors++; 1225 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { 1226 /* Frame too long or too short. */ 1227 ndev->stats.rx_length_errors++; 1228 } 1229 if (status & BD_ENET_RX_NO) /* Frame alignment */ 1230 ndev->stats.rx_frame_errors++; 1231 if (status & BD_ENET_RX_CR) /* CRC Error */ 1232 ndev->stats.rx_crc_errors++; 1233 if (status & BD_ENET_RX_OV) /* FIFO overrun */ 1234 ndev->stats.rx_fifo_errors++; 1235 } 1236 1237 /* Report late collisions as a frame error. 1238 * On this error, the BD is closed, but we don't know what we 1239 * have in the buffer. So, just drop this frame on the floor. 1240 */ 1241 if (status & BD_ENET_RX_CL) { 1242 ndev->stats.rx_errors++; 1243 ndev->stats.rx_frame_errors++; 1244 goto rx_processing_done; 1245 } 1246 1247 /* Process the incoming frame. */ 1248 ndev->stats.rx_packets++; 1249 pkt_len = bdp->cbd_datlen; 1250 ndev->stats.rx_bytes += pkt_len; 1251 1252 index = fec_enet_get_bd_index(fep->rx_bd_base, bdp, fep); 1253 data = fep->rx_skbuff[index]->data; 1254 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr, 1255 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1256 1257 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 1258 swap_buffer(data, pkt_len); 1259 1260 /* Extract the enhanced buffer descriptor */ 1261 ebdp = NULL; 1262 if (fep->bufdesc_ex) 1263 ebdp = (struct bufdesc_ex *)bdp; 1264 1265 /* If this is a VLAN packet remove the VLAN Tag */ 1266 vlan_packet_rcvd = false; 1267 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1268 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) { 1269 /* Push and remove the vlan tag */ 1270 struct vlan_hdr *vlan_header = 1271 (struct vlan_hdr *) (data + ETH_HLEN); 1272 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1273 pkt_len -= VLAN_HLEN; 1274 1275 vlan_packet_rcvd = true; 1276 } 1277 1278 /* This does 16 byte alignment, exactly what we need. 1279 * The packet length includes FCS, but we don't want to 1280 * include that when passing upstream as it messes up 1281 * bridging applications. 1282 */ 1283 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); 1284 1285 if (unlikely(!skb)) { 1286 ndev->stats.rx_dropped++; 1287 } else { 1288 int payload_offset = (2 * ETH_ALEN); 1289 skb_reserve(skb, NET_IP_ALIGN); 1290 skb_put(skb, pkt_len - 4); /* Make room */ 1291 1292 /* Extract the frame data without the VLAN header. */ 1293 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN)); 1294 if (vlan_packet_rcvd) 1295 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN; 1296 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN), 1297 data + payload_offset, 1298 pkt_len - 4 - (2 * ETH_ALEN)); 1299 1300 skb->protocol = eth_type_trans(skb, ndev); 1301 1302 /* Get receive timestamp from the skb */ 1303 if (fep->hwts_rx_en && fep->bufdesc_ex) { 1304 struct skb_shared_hwtstamps *shhwtstamps = 1305 skb_hwtstamps(skb); 1306 unsigned long flags; 1307 1308 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 1309 1310 spin_lock_irqsave(&fep->tmreg_lock, flags); 1311 shhwtstamps->hwtstamp = ns_to_ktime( 1312 timecounter_cyc2time(&fep->tc, ebdp->ts)); 1313 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1314 } 1315 1316 if (fep->bufdesc_ex && 1317 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1318 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) { 1319 /* don't check it */ 1320 skb->ip_summed = CHECKSUM_UNNECESSARY; 1321 } else { 1322 skb_checksum_none_assert(skb); 1323 } 1324 } 1325 1326 /* Handle received VLAN packets */ 1327 if (vlan_packet_rcvd) 1328 __vlan_hwaccel_put_tag(skb, 1329 htons(ETH_P_8021Q), 1330 vlan_tag); 1331 1332 napi_gro_receive(&fep->napi, skb); 1333 } 1334 1335 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr, 1336 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1337 rx_processing_done: 1338 /* Clear the status flags for this buffer */ 1339 status &= ~BD_ENET_RX_STATS; 1340 1341 /* Mark the buffer empty */ 1342 status |= BD_ENET_RX_EMPTY; 1343 bdp->cbd_sc = status; 1344 1345 if (fep->bufdesc_ex) { 1346 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1347 1348 ebdp->cbd_esc = BD_ENET_RX_INT; 1349 ebdp->cbd_prot = 0; 1350 ebdp->cbd_bdu = 0; 1351 } 1352 1353 /* Update BD pointer to next entry */ 1354 bdp = fec_enet_get_nextdesc(bdp, fep); 1355 1356 /* Doing this here will keep the FEC running while we process 1357 * incoming frames. On a heavily loaded network, we should be 1358 * able to keep up at the expense of system resources. 1359 */ 1360 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 1361 } 1362 fep->cur_rx = bdp; 1363 1364 return pkt_received; 1365 } 1366 1367 static irqreturn_t 1368 fec_enet_interrupt(int irq, void *dev_id) 1369 { 1370 struct net_device *ndev = dev_id; 1371 struct fec_enet_private *fep = netdev_priv(ndev); 1372 uint int_events; 1373 irqreturn_t ret = IRQ_NONE; 1374 1375 do { 1376 int_events = readl(fep->hwp + FEC_IEVENT); 1377 writel(int_events, fep->hwp + FEC_IEVENT); 1378 1379 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) { 1380 ret = IRQ_HANDLED; 1381 1382 /* Disable the RX interrupt */ 1383 if (napi_schedule_prep(&fep->napi)) { 1384 writel(FEC_RX_DISABLED_IMASK, 1385 fep->hwp + FEC_IMASK); 1386 __napi_schedule(&fep->napi); 1387 } 1388 } 1389 1390 if (int_events & FEC_ENET_MII) { 1391 ret = IRQ_HANDLED; 1392 complete(&fep->mdio_done); 1393 } 1394 } while (int_events); 1395 1396 return ret; 1397 } 1398 1399 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1400 { 1401 struct net_device *ndev = napi->dev; 1402 int pkts = fec_enet_rx(ndev, budget); 1403 struct fec_enet_private *fep = netdev_priv(ndev); 1404 1405 fec_enet_tx(ndev); 1406 1407 if (pkts < budget) { 1408 napi_complete(napi); 1409 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1410 } 1411 return pkts; 1412 } 1413 1414 /* ------------------------------------------------------------------------- */ 1415 static void fec_get_mac(struct net_device *ndev) 1416 { 1417 struct fec_enet_private *fep = netdev_priv(ndev); 1418 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1419 unsigned char *iap, tmpaddr[ETH_ALEN]; 1420 1421 /* 1422 * try to get mac address in following order: 1423 * 1424 * 1) module parameter via kernel command line in form 1425 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1426 */ 1427 iap = macaddr; 1428 1429 /* 1430 * 2) from device tree data 1431 */ 1432 if (!is_valid_ether_addr(iap)) { 1433 struct device_node *np = fep->pdev->dev.of_node; 1434 if (np) { 1435 const char *mac = of_get_mac_address(np); 1436 if (mac) 1437 iap = (unsigned char *) mac; 1438 } 1439 } 1440 1441 /* 1442 * 3) from flash or fuse (via platform data) 1443 */ 1444 if (!is_valid_ether_addr(iap)) { 1445 #ifdef CONFIG_M5272 1446 if (FEC_FLASHMAC) 1447 iap = (unsigned char *)FEC_FLASHMAC; 1448 #else 1449 if (pdata) 1450 iap = (unsigned char *)&pdata->mac; 1451 #endif 1452 } 1453 1454 /* 1455 * 4) FEC mac registers set by bootloader 1456 */ 1457 if (!is_valid_ether_addr(iap)) { 1458 *((__be32 *) &tmpaddr[0]) = 1459 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1460 *((__be16 *) &tmpaddr[4]) = 1461 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1462 iap = &tmpaddr[0]; 1463 } 1464 1465 /* 1466 * 5) random mac address 1467 */ 1468 if (!is_valid_ether_addr(iap)) { 1469 /* Report it and use a random ethernet address instead */ 1470 netdev_err(ndev, "Invalid MAC address: %pM\n", iap); 1471 eth_hw_addr_random(ndev); 1472 netdev_info(ndev, "Using random MAC address: %pM\n", 1473 ndev->dev_addr); 1474 return; 1475 } 1476 1477 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1478 1479 /* Adjust MAC if using macaddr */ 1480 if (iap == macaddr) 1481 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1482 } 1483 1484 /* ------------------------------------------------------------------------- */ 1485 1486 /* 1487 * Phy section 1488 */ 1489 static void fec_enet_adjust_link(struct net_device *ndev) 1490 { 1491 struct fec_enet_private *fep = netdev_priv(ndev); 1492 struct phy_device *phy_dev = fep->phy_dev; 1493 int status_change = 0; 1494 1495 /* Prevent a state halted on mii error */ 1496 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 1497 phy_dev->state = PHY_RESUMING; 1498 return; 1499 } 1500 1501 if (phy_dev->link) { 1502 if (!fep->link) { 1503 fep->link = phy_dev->link; 1504 status_change = 1; 1505 } 1506 1507 if (fep->full_duplex != phy_dev->duplex) 1508 status_change = 1; 1509 1510 if (phy_dev->speed != fep->speed) { 1511 fep->speed = phy_dev->speed; 1512 status_change = 1; 1513 } 1514 1515 /* if any of the above changed restart the FEC */ 1516 if (status_change) 1517 fec_restart(ndev, phy_dev->duplex); 1518 } else { 1519 if (fep->link) { 1520 fec_stop(ndev); 1521 fep->link = phy_dev->link; 1522 status_change = 1; 1523 } 1524 } 1525 1526 if (status_change) 1527 phy_print_status(phy_dev); 1528 } 1529 1530 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1531 { 1532 struct fec_enet_private *fep = bus->priv; 1533 unsigned long time_left; 1534 1535 fep->mii_timeout = 0; 1536 init_completion(&fep->mdio_done); 1537 1538 /* start a read op */ 1539 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 1540 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1541 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1542 1543 /* wait for end of transfer */ 1544 time_left = wait_for_completion_timeout(&fep->mdio_done, 1545 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1546 if (time_left == 0) { 1547 fep->mii_timeout = 1; 1548 netdev_err(fep->netdev, "MDIO read timeout\n"); 1549 return -ETIMEDOUT; 1550 } 1551 1552 /* return value */ 1553 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1554 } 1555 1556 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1557 u16 value) 1558 { 1559 struct fec_enet_private *fep = bus->priv; 1560 unsigned long time_left; 1561 1562 fep->mii_timeout = 0; 1563 init_completion(&fep->mdio_done); 1564 1565 /* start a write op */ 1566 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 1567 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1568 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1569 fep->hwp + FEC_MII_DATA); 1570 1571 /* wait for end of transfer */ 1572 time_left = wait_for_completion_timeout(&fep->mdio_done, 1573 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1574 if (time_left == 0) { 1575 fep->mii_timeout = 1; 1576 netdev_err(fep->netdev, "MDIO write timeout\n"); 1577 return -ETIMEDOUT; 1578 } 1579 1580 return 0; 1581 } 1582 1583 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1584 { 1585 struct fec_enet_private *fep = netdev_priv(ndev); 1586 int ret; 1587 1588 if (enable) { 1589 ret = clk_prepare_enable(fep->clk_ahb); 1590 if (ret) 1591 return ret; 1592 ret = clk_prepare_enable(fep->clk_ipg); 1593 if (ret) 1594 goto failed_clk_ipg; 1595 if (fep->clk_enet_out) { 1596 ret = clk_prepare_enable(fep->clk_enet_out); 1597 if (ret) 1598 goto failed_clk_enet_out; 1599 } 1600 if (fep->clk_ptp) { 1601 ret = clk_prepare_enable(fep->clk_ptp); 1602 if (ret) 1603 goto failed_clk_ptp; 1604 } 1605 } else { 1606 clk_disable_unprepare(fep->clk_ahb); 1607 clk_disable_unprepare(fep->clk_ipg); 1608 if (fep->clk_enet_out) 1609 clk_disable_unprepare(fep->clk_enet_out); 1610 if (fep->clk_ptp) 1611 clk_disable_unprepare(fep->clk_ptp); 1612 } 1613 1614 return 0; 1615 failed_clk_ptp: 1616 if (fep->clk_enet_out) 1617 clk_disable_unprepare(fep->clk_enet_out); 1618 failed_clk_enet_out: 1619 clk_disable_unprepare(fep->clk_ipg); 1620 failed_clk_ipg: 1621 clk_disable_unprepare(fep->clk_ahb); 1622 1623 return ret; 1624 } 1625 1626 static int fec_enet_mii_probe(struct net_device *ndev) 1627 { 1628 struct fec_enet_private *fep = netdev_priv(ndev); 1629 const struct platform_device_id *id_entry = 1630 platform_get_device_id(fep->pdev); 1631 struct phy_device *phy_dev = NULL; 1632 char mdio_bus_id[MII_BUS_ID_SIZE]; 1633 char phy_name[MII_BUS_ID_SIZE + 3]; 1634 int phy_id; 1635 int dev_id = fep->dev_id; 1636 1637 fep->phy_dev = NULL; 1638 1639 /* check for attached phy */ 1640 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1641 if ((fep->mii_bus->phy_mask & (1 << phy_id))) 1642 continue; 1643 if (fep->mii_bus->phy_map[phy_id] == NULL) 1644 continue; 1645 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) 1646 continue; 1647 if (dev_id--) 1648 continue; 1649 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1650 break; 1651 } 1652 1653 if (phy_id >= PHY_MAX_ADDR) { 1654 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1655 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 1656 phy_id = 0; 1657 } 1658 1659 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); 1660 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 1661 fep->phy_interface); 1662 if (IS_ERR(phy_dev)) { 1663 netdev_err(ndev, "could not attach to PHY\n"); 1664 return PTR_ERR(phy_dev); 1665 } 1666 1667 /* mask with MAC supported features */ 1668 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) { 1669 phy_dev->supported &= PHY_GBIT_FEATURES; 1670 #if !defined(CONFIG_M5272) 1671 phy_dev->supported |= SUPPORTED_Pause; 1672 #endif 1673 } 1674 else 1675 phy_dev->supported &= PHY_BASIC_FEATURES; 1676 1677 phy_dev->advertising = phy_dev->supported; 1678 1679 fep->phy_dev = phy_dev; 1680 fep->link = 0; 1681 fep->full_duplex = 0; 1682 1683 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 1684 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), 1685 fep->phy_dev->irq); 1686 1687 return 0; 1688 } 1689 1690 static int fec_enet_mii_init(struct platform_device *pdev) 1691 { 1692 static struct mii_bus *fec0_mii_bus; 1693 struct net_device *ndev = platform_get_drvdata(pdev); 1694 struct fec_enet_private *fep = netdev_priv(ndev); 1695 const struct platform_device_id *id_entry = 1696 platform_get_device_id(fep->pdev); 1697 int err = -ENXIO, i; 1698 1699 /* 1700 * The dual fec interfaces are not equivalent with enet-mac. 1701 * Here are the differences: 1702 * 1703 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1704 * - fec0 acts as the 1588 time master while fec1 is slave 1705 * - external phys can only be configured by fec0 1706 * 1707 * That is to say fec1 can not work independently. It only works 1708 * when fec0 is working. The reason behind this design is that the 1709 * second interface is added primarily for Switch mode. 1710 * 1711 * Because of the last point above, both phys are attached on fec0 1712 * mdio interface in board design, and need to be configured by 1713 * fec0 mii_bus. 1714 */ 1715 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { 1716 /* fec1 uses fec0 mii_bus */ 1717 if (mii_cnt && fec0_mii_bus) { 1718 fep->mii_bus = fec0_mii_bus; 1719 mii_cnt++; 1720 return 0; 1721 } 1722 return -ENOENT; 1723 } 1724 1725 fep->mii_timeout = 0; 1726 1727 /* 1728 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 1729 * 1730 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 1731 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 1732 * Reference Manual has an error on this, and gets fixed on i.MX6Q 1733 * document. 1734 */ 1735 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000); 1736 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1737 fep->phy_speed--; 1738 fep->phy_speed <<= 1; 1739 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1740 1741 fep->mii_bus = mdiobus_alloc(); 1742 if (fep->mii_bus == NULL) { 1743 err = -ENOMEM; 1744 goto err_out; 1745 } 1746 1747 fep->mii_bus->name = "fec_enet_mii_bus"; 1748 fep->mii_bus->read = fec_enet_mdio_read; 1749 fep->mii_bus->write = fec_enet_mdio_write; 1750 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1751 pdev->name, fep->dev_id + 1); 1752 fep->mii_bus->priv = fep; 1753 fep->mii_bus->parent = &pdev->dev; 1754 1755 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 1756 if (!fep->mii_bus->irq) { 1757 err = -ENOMEM; 1758 goto err_out_free_mdiobus; 1759 } 1760 1761 for (i = 0; i < PHY_MAX_ADDR; i++) 1762 fep->mii_bus->irq[i] = PHY_POLL; 1763 1764 if (mdiobus_register(fep->mii_bus)) 1765 goto err_out_free_mdio_irq; 1766 1767 mii_cnt++; 1768 1769 /* save fec0 mii_bus */ 1770 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1771 fec0_mii_bus = fep->mii_bus; 1772 1773 return 0; 1774 1775 err_out_free_mdio_irq: 1776 kfree(fep->mii_bus->irq); 1777 err_out_free_mdiobus: 1778 mdiobus_free(fep->mii_bus); 1779 err_out: 1780 return err; 1781 } 1782 1783 static void fec_enet_mii_remove(struct fec_enet_private *fep) 1784 { 1785 if (--mii_cnt == 0) { 1786 mdiobus_unregister(fep->mii_bus); 1787 kfree(fep->mii_bus->irq); 1788 mdiobus_free(fep->mii_bus); 1789 } 1790 } 1791 1792 static int fec_enet_get_settings(struct net_device *ndev, 1793 struct ethtool_cmd *cmd) 1794 { 1795 struct fec_enet_private *fep = netdev_priv(ndev); 1796 struct phy_device *phydev = fep->phy_dev; 1797 1798 if (!phydev) 1799 return -ENODEV; 1800 1801 return phy_ethtool_gset(phydev, cmd); 1802 } 1803 1804 static int fec_enet_set_settings(struct net_device *ndev, 1805 struct ethtool_cmd *cmd) 1806 { 1807 struct fec_enet_private *fep = netdev_priv(ndev); 1808 struct phy_device *phydev = fep->phy_dev; 1809 1810 if (!phydev) 1811 return -ENODEV; 1812 1813 return phy_ethtool_sset(phydev, cmd); 1814 } 1815 1816 static void fec_enet_get_drvinfo(struct net_device *ndev, 1817 struct ethtool_drvinfo *info) 1818 { 1819 struct fec_enet_private *fep = netdev_priv(ndev); 1820 1821 strlcpy(info->driver, fep->pdev->dev.driver->name, 1822 sizeof(info->driver)); 1823 strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); 1824 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 1825 } 1826 1827 static int fec_enet_get_ts_info(struct net_device *ndev, 1828 struct ethtool_ts_info *info) 1829 { 1830 struct fec_enet_private *fep = netdev_priv(ndev); 1831 1832 if (fep->bufdesc_ex) { 1833 1834 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1835 SOF_TIMESTAMPING_RX_SOFTWARE | 1836 SOF_TIMESTAMPING_SOFTWARE | 1837 SOF_TIMESTAMPING_TX_HARDWARE | 1838 SOF_TIMESTAMPING_RX_HARDWARE | 1839 SOF_TIMESTAMPING_RAW_HARDWARE; 1840 if (fep->ptp_clock) 1841 info->phc_index = ptp_clock_index(fep->ptp_clock); 1842 else 1843 info->phc_index = -1; 1844 1845 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 1846 (1 << HWTSTAMP_TX_ON); 1847 1848 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 1849 (1 << HWTSTAMP_FILTER_ALL); 1850 return 0; 1851 } else { 1852 return ethtool_op_get_ts_info(ndev, info); 1853 } 1854 } 1855 1856 #if !defined(CONFIG_M5272) 1857 1858 static void fec_enet_get_pauseparam(struct net_device *ndev, 1859 struct ethtool_pauseparam *pause) 1860 { 1861 struct fec_enet_private *fep = netdev_priv(ndev); 1862 1863 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 1864 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 1865 pause->rx_pause = pause->tx_pause; 1866 } 1867 1868 static int fec_enet_set_pauseparam(struct net_device *ndev, 1869 struct ethtool_pauseparam *pause) 1870 { 1871 struct fec_enet_private *fep = netdev_priv(ndev); 1872 1873 if (pause->tx_pause != pause->rx_pause) { 1874 netdev_info(ndev, 1875 "hardware only support enable/disable both tx and rx"); 1876 return -EINVAL; 1877 } 1878 1879 fep->pause_flag = 0; 1880 1881 /* tx pause must be same as rx pause */ 1882 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 1883 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 1884 1885 if (pause->rx_pause || pause->autoneg) { 1886 fep->phy_dev->supported |= ADVERTISED_Pause; 1887 fep->phy_dev->advertising |= ADVERTISED_Pause; 1888 } else { 1889 fep->phy_dev->supported &= ~ADVERTISED_Pause; 1890 fep->phy_dev->advertising &= ~ADVERTISED_Pause; 1891 } 1892 1893 if (pause->autoneg) { 1894 if (netif_running(ndev)) 1895 fec_stop(ndev); 1896 phy_start_aneg(fep->phy_dev); 1897 } 1898 if (netif_running(ndev)) 1899 fec_restart(ndev, 0); 1900 1901 return 0; 1902 } 1903 1904 static const struct fec_stat { 1905 char name[ETH_GSTRING_LEN]; 1906 u16 offset; 1907 } fec_stats[] = { 1908 /* RMON TX */ 1909 { "tx_dropped", RMON_T_DROP }, 1910 { "tx_packets", RMON_T_PACKETS }, 1911 { "tx_broadcast", RMON_T_BC_PKT }, 1912 { "tx_multicast", RMON_T_MC_PKT }, 1913 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 1914 { "tx_undersize", RMON_T_UNDERSIZE }, 1915 { "tx_oversize", RMON_T_OVERSIZE }, 1916 { "tx_fragment", RMON_T_FRAG }, 1917 { "tx_jabber", RMON_T_JAB }, 1918 { "tx_collision", RMON_T_COL }, 1919 { "tx_64byte", RMON_T_P64 }, 1920 { "tx_65to127byte", RMON_T_P65TO127 }, 1921 { "tx_128to255byte", RMON_T_P128TO255 }, 1922 { "tx_256to511byte", RMON_T_P256TO511 }, 1923 { "tx_512to1023byte", RMON_T_P512TO1023 }, 1924 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 1925 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 1926 { "tx_octets", RMON_T_OCTETS }, 1927 1928 /* IEEE TX */ 1929 { "IEEE_tx_drop", IEEE_T_DROP }, 1930 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 1931 { "IEEE_tx_1col", IEEE_T_1COL }, 1932 { "IEEE_tx_mcol", IEEE_T_MCOL }, 1933 { "IEEE_tx_def", IEEE_T_DEF }, 1934 { "IEEE_tx_lcol", IEEE_T_LCOL }, 1935 { "IEEE_tx_excol", IEEE_T_EXCOL }, 1936 { "IEEE_tx_macerr", IEEE_T_MACERR }, 1937 { "IEEE_tx_cserr", IEEE_T_CSERR }, 1938 { "IEEE_tx_sqe", IEEE_T_SQE }, 1939 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 1940 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 1941 1942 /* RMON RX */ 1943 { "rx_packets", RMON_R_PACKETS }, 1944 { "rx_broadcast", RMON_R_BC_PKT }, 1945 { "rx_multicast", RMON_R_MC_PKT }, 1946 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 1947 { "rx_undersize", RMON_R_UNDERSIZE }, 1948 { "rx_oversize", RMON_R_OVERSIZE }, 1949 { "rx_fragment", RMON_R_FRAG }, 1950 { "rx_jabber", RMON_R_JAB }, 1951 { "rx_64byte", RMON_R_P64 }, 1952 { "rx_65to127byte", RMON_R_P65TO127 }, 1953 { "rx_128to255byte", RMON_R_P128TO255 }, 1954 { "rx_256to511byte", RMON_R_P256TO511 }, 1955 { "rx_512to1023byte", RMON_R_P512TO1023 }, 1956 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 1957 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 1958 { "rx_octets", RMON_R_OCTETS }, 1959 1960 /* IEEE RX */ 1961 { "IEEE_rx_drop", IEEE_R_DROP }, 1962 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 1963 { "IEEE_rx_crc", IEEE_R_CRC }, 1964 { "IEEE_rx_align", IEEE_R_ALIGN }, 1965 { "IEEE_rx_macerr", IEEE_R_MACERR }, 1966 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 1967 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 1968 }; 1969 1970 static void fec_enet_get_ethtool_stats(struct net_device *dev, 1971 struct ethtool_stats *stats, u64 *data) 1972 { 1973 struct fec_enet_private *fep = netdev_priv(dev); 1974 int i; 1975 1976 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 1977 data[i] = readl(fep->hwp + fec_stats[i].offset); 1978 } 1979 1980 static void fec_enet_get_strings(struct net_device *netdev, 1981 u32 stringset, u8 *data) 1982 { 1983 int i; 1984 switch (stringset) { 1985 case ETH_SS_STATS: 1986 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 1987 memcpy(data + i * ETH_GSTRING_LEN, 1988 fec_stats[i].name, ETH_GSTRING_LEN); 1989 break; 1990 } 1991 } 1992 1993 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 1994 { 1995 switch (sset) { 1996 case ETH_SS_STATS: 1997 return ARRAY_SIZE(fec_stats); 1998 default: 1999 return -EOPNOTSUPP; 2000 } 2001 } 2002 #endif /* !defined(CONFIG_M5272) */ 2003 2004 static int fec_enet_nway_reset(struct net_device *dev) 2005 { 2006 struct fec_enet_private *fep = netdev_priv(dev); 2007 struct phy_device *phydev = fep->phy_dev; 2008 2009 if (!phydev) 2010 return -ENODEV; 2011 2012 return genphy_restart_aneg(phydev); 2013 } 2014 2015 static const struct ethtool_ops fec_enet_ethtool_ops = { 2016 #if !defined(CONFIG_M5272) 2017 .get_pauseparam = fec_enet_get_pauseparam, 2018 .set_pauseparam = fec_enet_set_pauseparam, 2019 #endif 2020 .get_settings = fec_enet_get_settings, 2021 .set_settings = fec_enet_set_settings, 2022 .get_drvinfo = fec_enet_get_drvinfo, 2023 .get_link = ethtool_op_get_link, 2024 .get_ts_info = fec_enet_get_ts_info, 2025 .nway_reset = fec_enet_nway_reset, 2026 #ifndef CONFIG_M5272 2027 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2028 .get_strings = fec_enet_get_strings, 2029 .get_sset_count = fec_enet_get_sset_count, 2030 #endif 2031 }; 2032 2033 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2034 { 2035 struct fec_enet_private *fep = netdev_priv(ndev); 2036 struct phy_device *phydev = fep->phy_dev; 2037 2038 if (!netif_running(ndev)) 2039 return -EINVAL; 2040 2041 if (!phydev) 2042 return -ENODEV; 2043 2044 if (fep->bufdesc_ex) { 2045 if (cmd == SIOCSHWTSTAMP) 2046 return fec_ptp_set(ndev, rq); 2047 if (cmd == SIOCGHWTSTAMP) 2048 return fec_ptp_get(ndev, rq); 2049 } 2050 2051 return phy_mii_ioctl(phydev, rq, cmd); 2052 } 2053 2054 static void fec_enet_free_buffers(struct net_device *ndev) 2055 { 2056 struct fec_enet_private *fep = netdev_priv(ndev); 2057 unsigned int i; 2058 struct sk_buff *skb; 2059 struct bufdesc *bdp; 2060 2061 bdp = fep->rx_bd_base; 2062 for (i = 0; i < fep->rx_ring_size; i++) { 2063 skb = fep->rx_skbuff[i]; 2064 2065 if (bdp->cbd_bufaddr) 2066 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 2067 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 2068 if (skb) 2069 dev_kfree_skb(skb); 2070 bdp = fec_enet_get_nextdesc(bdp, fep); 2071 } 2072 2073 bdp = fep->tx_bd_base; 2074 for (i = 0; i < fep->tx_ring_size; i++) 2075 kfree(fep->tx_bounce[i]); 2076 } 2077 2078 static int fec_enet_alloc_buffers(struct net_device *ndev) 2079 { 2080 struct fec_enet_private *fep = netdev_priv(ndev); 2081 unsigned int i; 2082 struct sk_buff *skb; 2083 struct bufdesc *bdp; 2084 2085 bdp = fep->rx_bd_base; 2086 for (i = 0; i < fep->rx_ring_size; i++) { 2087 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2088 if (!skb) { 2089 fec_enet_free_buffers(ndev); 2090 return -ENOMEM; 2091 } 2092 fep->rx_skbuff[i] = skb; 2093 2094 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, 2095 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 2096 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) { 2097 fec_enet_free_buffers(ndev); 2098 if (net_ratelimit()) 2099 netdev_err(ndev, "Rx DMA memory map failed\n"); 2100 return -ENOMEM; 2101 } 2102 bdp->cbd_sc = BD_ENET_RX_EMPTY; 2103 2104 if (fep->bufdesc_ex) { 2105 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2106 ebdp->cbd_esc = BD_ENET_RX_INT; 2107 } 2108 2109 bdp = fec_enet_get_nextdesc(bdp, fep); 2110 } 2111 2112 /* Set the last buffer to wrap. */ 2113 bdp = fec_enet_get_prevdesc(bdp, fep); 2114 bdp->cbd_sc |= BD_SC_WRAP; 2115 2116 bdp = fep->tx_bd_base; 2117 for (i = 0; i < fep->tx_ring_size; i++) { 2118 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2119 2120 bdp->cbd_sc = 0; 2121 bdp->cbd_bufaddr = 0; 2122 2123 if (fep->bufdesc_ex) { 2124 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2125 ebdp->cbd_esc = BD_ENET_TX_INT; 2126 } 2127 2128 bdp = fec_enet_get_nextdesc(bdp, fep); 2129 } 2130 2131 /* Set the last buffer to wrap. */ 2132 bdp = fec_enet_get_prevdesc(bdp, fep); 2133 bdp->cbd_sc |= BD_SC_WRAP; 2134 2135 return 0; 2136 } 2137 2138 static int 2139 fec_enet_open(struct net_device *ndev) 2140 { 2141 struct fec_enet_private *fep = netdev_priv(ndev); 2142 int ret; 2143 2144 pinctrl_pm_select_default_state(&fep->pdev->dev); 2145 ret = fec_enet_clk_enable(ndev, true); 2146 if (ret) 2147 return ret; 2148 2149 /* I should reset the ring buffers here, but I don't yet know 2150 * a simple way to do that. 2151 */ 2152 2153 ret = fec_enet_alloc_buffers(ndev); 2154 if (ret) 2155 return ret; 2156 2157 /* Probe and connect to PHY when open the interface */ 2158 ret = fec_enet_mii_probe(ndev); 2159 if (ret) { 2160 fec_enet_free_buffers(ndev); 2161 return ret; 2162 } 2163 2164 napi_enable(&fep->napi); 2165 phy_start(fep->phy_dev); 2166 netif_start_queue(ndev); 2167 fep->opened = 1; 2168 return 0; 2169 } 2170 2171 static int 2172 fec_enet_close(struct net_device *ndev) 2173 { 2174 struct fec_enet_private *fep = netdev_priv(ndev); 2175 2176 /* Don't know what to do yet. */ 2177 napi_disable(&fep->napi); 2178 fep->opened = 0; 2179 netif_stop_queue(ndev); 2180 fec_stop(ndev); 2181 2182 if (fep->phy_dev) { 2183 phy_stop(fep->phy_dev); 2184 phy_disconnect(fep->phy_dev); 2185 } 2186 2187 fec_enet_clk_enable(ndev, false); 2188 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2189 fec_enet_free_buffers(ndev); 2190 2191 return 0; 2192 } 2193 2194 /* Set or clear the multicast filter for this adaptor. 2195 * Skeleton taken from sunlance driver. 2196 * The CPM Ethernet implementation allows Multicast as well as individual 2197 * MAC address filtering. Some of the drivers check to make sure it is 2198 * a group multicast address, and discard those that are not. I guess I 2199 * will do the same for now, but just remove the test if you want 2200 * individual filtering as well (do the upper net layers want or support 2201 * this kind of feature?). 2202 */ 2203 2204 #define HASH_BITS 6 /* #bits in hash */ 2205 #define CRC32_POLY 0xEDB88320 2206 2207 static void set_multicast_list(struct net_device *ndev) 2208 { 2209 struct fec_enet_private *fep = netdev_priv(ndev); 2210 struct netdev_hw_addr *ha; 2211 unsigned int i, bit, data, crc, tmp; 2212 unsigned char hash; 2213 2214 if (ndev->flags & IFF_PROMISC) { 2215 tmp = readl(fep->hwp + FEC_R_CNTRL); 2216 tmp |= 0x8; 2217 writel(tmp, fep->hwp + FEC_R_CNTRL); 2218 return; 2219 } 2220 2221 tmp = readl(fep->hwp + FEC_R_CNTRL); 2222 tmp &= ~0x8; 2223 writel(tmp, fep->hwp + FEC_R_CNTRL); 2224 2225 if (ndev->flags & IFF_ALLMULTI) { 2226 /* Catch all multicast addresses, so set the 2227 * filter to all 1's 2228 */ 2229 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2230 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2231 2232 return; 2233 } 2234 2235 /* Clear filter and add the addresses in hash register 2236 */ 2237 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2238 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2239 2240 netdev_for_each_mc_addr(ha, ndev) { 2241 /* calculate crc32 value of mac address */ 2242 crc = 0xffffffff; 2243 2244 for (i = 0; i < ndev->addr_len; i++) { 2245 data = ha->addr[i]; 2246 for (bit = 0; bit < 8; bit++, data >>= 1) { 2247 crc = (crc >> 1) ^ 2248 (((crc ^ data) & 1) ? CRC32_POLY : 0); 2249 } 2250 } 2251 2252 /* only upper 6 bits (HASH_BITS) are used 2253 * which point to specific bit in he hash registers 2254 */ 2255 hash = (crc >> (32 - HASH_BITS)) & 0x3f; 2256 2257 if (hash > 31) { 2258 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2259 tmp |= 1 << (hash - 32); 2260 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2261 } else { 2262 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2263 tmp |= 1 << hash; 2264 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2265 } 2266 } 2267 } 2268 2269 /* Set a MAC change in hardware. */ 2270 static int 2271 fec_set_mac_address(struct net_device *ndev, void *p) 2272 { 2273 struct fec_enet_private *fep = netdev_priv(ndev); 2274 struct sockaddr *addr = p; 2275 2276 if (addr) { 2277 if (!is_valid_ether_addr(addr->sa_data)) 2278 return -EADDRNOTAVAIL; 2279 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 2280 } 2281 2282 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 2283 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 2284 fep->hwp + FEC_ADDR_LOW); 2285 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 2286 fep->hwp + FEC_ADDR_HIGH); 2287 return 0; 2288 } 2289 2290 #ifdef CONFIG_NET_POLL_CONTROLLER 2291 /** 2292 * fec_poll_controller - FEC Poll controller function 2293 * @dev: The FEC network adapter 2294 * 2295 * Polled functionality used by netconsole and others in non interrupt mode 2296 * 2297 */ 2298 static void fec_poll_controller(struct net_device *dev) 2299 { 2300 int i; 2301 struct fec_enet_private *fep = netdev_priv(dev); 2302 2303 for (i = 0; i < FEC_IRQ_NUM; i++) { 2304 if (fep->irq[i] > 0) { 2305 disable_irq(fep->irq[i]); 2306 fec_enet_interrupt(fep->irq[i], dev); 2307 enable_irq(fep->irq[i]); 2308 } 2309 } 2310 } 2311 #endif 2312 2313 static int fec_set_features(struct net_device *netdev, 2314 netdev_features_t features) 2315 { 2316 struct fec_enet_private *fep = netdev_priv(netdev); 2317 netdev_features_t changed = features ^ netdev->features; 2318 2319 netdev->features = features; 2320 2321 /* Receive checksum has been changed */ 2322 if (changed & NETIF_F_RXCSUM) { 2323 if (features & NETIF_F_RXCSUM) 2324 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 2325 else 2326 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 2327 2328 if (netif_running(netdev)) { 2329 fec_stop(netdev); 2330 fec_restart(netdev, fep->phy_dev->duplex); 2331 netif_wake_queue(netdev); 2332 } else { 2333 fec_restart(netdev, fep->phy_dev->duplex); 2334 } 2335 } 2336 2337 return 0; 2338 } 2339 2340 static const struct net_device_ops fec_netdev_ops = { 2341 .ndo_open = fec_enet_open, 2342 .ndo_stop = fec_enet_close, 2343 .ndo_start_xmit = fec_enet_start_xmit, 2344 .ndo_set_rx_mode = set_multicast_list, 2345 .ndo_change_mtu = eth_change_mtu, 2346 .ndo_validate_addr = eth_validate_addr, 2347 .ndo_tx_timeout = fec_timeout, 2348 .ndo_set_mac_address = fec_set_mac_address, 2349 .ndo_do_ioctl = fec_enet_ioctl, 2350 #ifdef CONFIG_NET_POLL_CONTROLLER 2351 .ndo_poll_controller = fec_poll_controller, 2352 #endif 2353 .ndo_set_features = fec_set_features, 2354 }; 2355 2356 /* 2357 * XXX: We need to clean up on failure exits here. 2358 * 2359 */ 2360 static int fec_enet_init(struct net_device *ndev) 2361 { 2362 struct fec_enet_private *fep = netdev_priv(ndev); 2363 const struct platform_device_id *id_entry = 2364 platform_get_device_id(fep->pdev); 2365 struct bufdesc *cbd_base; 2366 int bd_size; 2367 2368 /* init the tx & rx ring size */ 2369 fep->tx_ring_size = TX_RING_SIZE; 2370 fep->rx_ring_size = RX_RING_SIZE; 2371 2372 fep->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2373 fep->tx_wake_threshold = (fep->tx_ring_size - fep->tx_stop_threshold) / 2; 2374 2375 if (fep->bufdesc_ex) 2376 fep->bufdesc_size = sizeof(struct bufdesc_ex); 2377 else 2378 fep->bufdesc_size = sizeof(struct bufdesc); 2379 bd_size = (fep->tx_ring_size + fep->rx_ring_size) * 2380 fep->bufdesc_size; 2381 2382 /* Allocate memory for buffer descriptors. */ 2383 cbd_base = dma_alloc_coherent(NULL, bd_size, &fep->bd_dma, 2384 GFP_KERNEL); 2385 if (!cbd_base) 2386 return -ENOMEM; 2387 2388 fep->tso_hdrs = dma_alloc_coherent(NULL, fep->tx_ring_size * TSO_HEADER_SIZE, 2389 &fep->tso_hdrs_dma, GFP_KERNEL); 2390 if (!fep->tso_hdrs) { 2391 dma_free_coherent(NULL, bd_size, cbd_base, fep->bd_dma); 2392 return -ENOMEM; 2393 } 2394 2395 memset(cbd_base, 0, PAGE_SIZE); 2396 2397 fep->netdev = ndev; 2398 2399 /* Get the Ethernet address */ 2400 fec_get_mac(ndev); 2401 /* make sure MAC we just acquired is programmed into the hw */ 2402 fec_set_mac_address(ndev, NULL); 2403 2404 /* Set receive and transmit descriptor base. */ 2405 fep->rx_bd_base = cbd_base; 2406 if (fep->bufdesc_ex) 2407 fep->tx_bd_base = (struct bufdesc *) 2408 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size); 2409 else 2410 fep->tx_bd_base = cbd_base + fep->rx_ring_size; 2411 2412 /* The FEC Ethernet specific entries in the device structure */ 2413 ndev->watchdog_timeo = TX_TIMEOUT; 2414 ndev->netdev_ops = &fec_netdev_ops; 2415 ndev->ethtool_ops = &fec_enet_ethtool_ops; 2416 2417 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 2418 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 2419 2420 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) 2421 /* enable hw VLAN support */ 2422 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 2423 2424 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) { 2425 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 2426 2427 /* enable hw accelerator */ 2428 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 2429 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 2430 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 2431 } 2432 2433 ndev->hw_features = ndev->features; 2434 2435 fec_restart(ndev, 0); 2436 2437 return 0; 2438 } 2439 2440 #ifdef CONFIG_OF 2441 static void fec_reset_phy(struct platform_device *pdev) 2442 { 2443 int err, phy_reset; 2444 int msec = 1; 2445 struct device_node *np = pdev->dev.of_node; 2446 2447 if (!np) 2448 return; 2449 2450 of_property_read_u32(np, "phy-reset-duration", &msec); 2451 /* A sane reset duration should not be longer than 1s */ 2452 if (msec > 1000) 2453 msec = 1; 2454 2455 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 2456 if (!gpio_is_valid(phy_reset)) 2457 return; 2458 2459 err = devm_gpio_request_one(&pdev->dev, phy_reset, 2460 GPIOF_OUT_INIT_LOW, "phy-reset"); 2461 if (err) { 2462 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 2463 return; 2464 } 2465 msleep(msec); 2466 gpio_set_value(phy_reset, 1); 2467 } 2468 #else /* CONFIG_OF */ 2469 static void fec_reset_phy(struct platform_device *pdev) 2470 { 2471 /* 2472 * In case of platform probe, the reset has been done 2473 * by machine code. 2474 */ 2475 } 2476 #endif /* CONFIG_OF */ 2477 2478 static int 2479 fec_probe(struct platform_device *pdev) 2480 { 2481 struct fec_enet_private *fep; 2482 struct fec_platform_data *pdata; 2483 struct net_device *ndev; 2484 int i, irq, ret = 0; 2485 struct resource *r; 2486 const struct of_device_id *of_id; 2487 static int dev_id; 2488 2489 of_id = of_match_device(fec_dt_ids, &pdev->dev); 2490 if (of_id) 2491 pdev->id_entry = of_id->data; 2492 2493 /* Init network device */ 2494 ndev = alloc_etherdev(sizeof(struct fec_enet_private)); 2495 if (!ndev) 2496 return -ENOMEM; 2497 2498 SET_NETDEV_DEV(ndev, &pdev->dev); 2499 2500 /* setup board info structure */ 2501 fep = netdev_priv(ndev); 2502 2503 #if !defined(CONFIG_M5272) 2504 /* default enable pause frame auto negotiation */ 2505 if (pdev->id_entry && 2506 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT)) 2507 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 2508 #endif 2509 2510 /* Select default pin state */ 2511 pinctrl_pm_select_default_state(&pdev->dev); 2512 2513 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2514 fep->hwp = devm_ioremap_resource(&pdev->dev, r); 2515 if (IS_ERR(fep->hwp)) { 2516 ret = PTR_ERR(fep->hwp); 2517 goto failed_ioremap; 2518 } 2519 2520 fep->pdev = pdev; 2521 fep->dev_id = dev_id++; 2522 2523 fep->bufdesc_ex = 0; 2524 2525 platform_set_drvdata(pdev, ndev); 2526 2527 ret = of_get_phy_mode(pdev->dev.of_node); 2528 if (ret < 0) { 2529 pdata = dev_get_platdata(&pdev->dev); 2530 if (pdata) 2531 fep->phy_interface = pdata->phy; 2532 else 2533 fep->phy_interface = PHY_INTERFACE_MODE_MII; 2534 } else { 2535 fep->phy_interface = ret; 2536 } 2537 2538 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2539 if (IS_ERR(fep->clk_ipg)) { 2540 ret = PTR_ERR(fep->clk_ipg); 2541 goto failed_clk; 2542 } 2543 2544 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 2545 if (IS_ERR(fep->clk_ahb)) { 2546 ret = PTR_ERR(fep->clk_ahb); 2547 goto failed_clk; 2548 } 2549 2550 /* enet_out is optional, depends on board */ 2551 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 2552 if (IS_ERR(fep->clk_enet_out)) 2553 fep->clk_enet_out = NULL; 2554 2555 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 2556 fep->bufdesc_ex = 2557 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX; 2558 if (IS_ERR(fep->clk_ptp)) { 2559 fep->clk_ptp = NULL; 2560 fep->bufdesc_ex = 0; 2561 } 2562 2563 ret = fec_enet_clk_enable(ndev, true); 2564 if (ret) 2565 goto failed_clk; 2566 2567 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); 2568 if (!IS_ERR(fep->reg_phy)) { 2569 ret = regulator_enable(fep->reg_phy); 2570 if (ret) { 2571 dev_err(&pdev->dev, 2572 "Failed to enable phy regulator: %d\n", ret); 2573 goto failed_regulator; 2574 } 2575 } else { 2576 fep->reg_phy = NULL; 2577 } 2578 2579 fec_reset_phy(pdev); 2580 2581 if (fep->bufdesc_ex) 2582 fec_ptp_init(pdev); 2583 2584 ret = fec_enet_init(ndev); 2585 if (ret) 2586 goto failed_init; 2587 2588 for (i = 0; i < FEC_IRQ_NUM; i++) { 2589 irq = platform_get_irq(pdev, i); 2590 if (irq < 0) { 2591 if (i) 2592 break; 2593 ret = irq; 2594 goto failed_irq; 2595 } 2596 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 2597 0, pdev->name, ndev); 2598 if (ret) 2599 goto failed_irq; 2600 } 2601 2602 ret = fec_enet_mii_init(pdev); 2603 if (ret) 2604 goto failed_mii_init; 2605 2606 /* Carrier starts down, phylib will bring it up */ 2607 netif_carrier_off(ndev); 2608 fec_enet_clk_enable(ndev, false); 2609 pinctrl_pm_select_sleep_state(&pdev->dev); 2610 2611 ret = register_netdev(ndev); 2612 if (ret) 2613 goto failed_register; 2614 2615 if (fep->bufdesc_ex && fep->ptp_clock) 2616 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 2617 2618 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work); 2619 return 0; 2620 2621 failed_register: 2622 fec_enet_mii_remove(fep); 2623 failed_mii_init: 2624 failed_irq: 2625 failed_init: 2626 if (fep->reg_phy) 2627 regulator_disable(fep->reg_phy); 2628 failed_regulator: 2629 fec_enet_clk_enable(ndev, false); 2630 failed_clk: 2631 failed_ioremap: 2632 free_netdev(ndev); 2633 2634 return ret; 2635 } 2636 2637 static int 2638 fec_drv_remove(struct platform_device *pdev) 2639 { 2640 struct net_device *ndev = platform_get_drvdata(pdev); 2641 struct fec_enet_private *fep = netdev_priv(ndev); 2642 2643 cancel_delayed_work_sync(&(fep->delay_work.delay_work)); 2644 unregister_netdev(ndev); 2645 fec_enet_mii_remove(fep); 2646 del_timer_sync(&fep->time_keep); 2647 if (fep->reg_phy) 2648 regulator_disable(fep->reg_phy); 2649 if (fep->ptp_clock) 2650 ptp_clock_unregister(fep->ptp_clock); 2651 fec_enet_clk_enable(ndev, false); 2652 free_netdev(ndev); 2653 2654 return 0; 2655 } 2656 2657 #ifdef CONFIG_PM_SLEEP 2658 static int 2659 fec_suspend(struct device *dev) 2660 { 2661 struct net_device *ndev = dev_get_drvdata(dev); 2662 struct fec_enet_private *fep = netdev_priv(ndev); 2663 2664 if (netif_running(ndev)) { 2665 fec_stop(ndev); 2666 netif_device_detach(ndev); 2667 } 2668 fec_enet_clk_enable(ndev, false); 2669 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2670 2671 if (fep->reg_phy) 2672 regulator_disable(fep->reg_phy); 2673 2674 return 0; 2675 } 2676 2677 static int 2678 fec_resume(struct device *dev) 2679 { 2680 struct net_device *ndev = dev_get_drvdata(dev); 2681 struct fec_enet_private *fep = netdev_priv(ndev); 2682 int ret; 2683 2684 if (fep->reg_phy) { 2685 ret = regulator_enable(fep->reg_phy); 2686 if (ret) 2687 return ret; 2688 } 2689 2690 pinctrl_pm_select_default_state(&fep->pdev->dev); 2691 ret = fec_enet_clk_enable(ndev, true); 2692 if (ret) 2693 goto failed_clk; 2694 2695 if (netif_running(ndev)) { 2696 fec_restart(ndev, fep->full_duplex); 2697 netif_device_attach(ndev); 2698 } 2699 2700 return 0; 2701 2702 failed_clk: 2703 if (fep->reg_phy) 2704 regulator_disable(fep->reg_phy); 2705 return ret; 2706 } 2707 #endif /* CONFIG_PM_SLEEP */ 2708 2709 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume); 2710 2711 static struct platform_driver fec_driver = { 2712 .driver = { 2713 .name = DRIVER_NAME, 2714 .owner = THIS_MODULE, 2715 .pm = &fec_pm_ops, 2716 .of_match_table = fec_dt_ids, 2717 }, 2718 .id_table = fec_devtype, 2719 .probe = fec_probe, 2720 .remove = fec_drv_remove, 2721 }; 2722 2723 module_platform_driver(fec_driver); 2724 2725 MODULE_ALIAS("platform:"DRIVER_NAME); 2726 MODULE_LICENSE("GPL"); 2727