1 /* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 * 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/string.h> 27 #include <linux/ptrace.h> 28 #include <linux/errno.h> 29 #include <linux/ioport.h> 30 #include <linux/slab.h> 31 #include <linux/interrupt.h> 32 #include <linux/init.h> 33 #include <linux/delay.h> 34 #include <linux/netdevice.h> 35 #include <linux/etherdevice.h> 36 #include <linux/skbuff.h> 37 #include <linux/in.h> 38 #include <linux/ip.h> 39 #include <net/ip.h> 40 #include <linux/tcp.h> 41 #include <linux/udp.h> 42 #include <linux/icmp.h> 43 #include <linux/spinlock.h> 44 #include <linux/workqueue.h> 45 #include <linux/bitops.h> 46 #include <linux/io.h> 47 #include <linux/irq.h> 48 #include <linux/clk.h> 49 #include <linux/platform_device.h> 50 #include <linux/phy.h> 51 #include <linux/fec.h> 52 #include <linux/of.h> 53 #include <linux/of_device.h> 54 #include <linux/of_gpio.h> 55 #include <linux/of_net.h> 56 #include <linux/pinctrl/consumer.h> 57 #include <linux/regulator/consumer.h> 58 59 #include <asm/cacheflush.h> 60 61 #include "fec.h" 62 63 #if defined(CONFIG_ARM) 64 #define FEC_ALIGNMENT 0xf 65 #else 66 #define FEC_ALIGNMENT 0x3 67 #endif 68 69 #define DRIVER_NAME "fec" 70 #define FEC_NAPI_WEIGHT 64 71 72 /* Pause frame feild and FIFO threshold */ 73 #define FEC_ENET_FCE (1 << 5) 74 #define FEC_ENET_RSEM_V 0x84 75 #define FEC_ENET_RSFL_V 16 76 #define FEC_ENET_RAEM_V 0x8 77 #define FEC_ENET_RAFL_V 0x8 78 #define FEC_ENET_OPD_V 0xFFF0 79 80 /* Controller is ENET-MAC */ 81 #define FEC_QUIRK_ENET_MAC (1 << 0) 82 /* Controller needs driver to swap frame */ 83 #define FEC_QUIRK_SWAP_FRAME (1 << 1) 84 /* Controller uses gasket */ 85 #define FEC_QUIRK_USE_GASKET (1 << 2) 86 /* Controller has GBIT support */ 87 #define FEC_QUIRK_HAS_GBIT (1 << 3) 88 /* Controller has extend desc buffer */ 89 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) 90 /* Controller has hardware checksum support */ 91 #define FEC_QUIRK_HAS_CSUM (1 << 5) 92 93 static struct platform_device_id fec_devtype[] = { 94 { 95 /* keep it for coldfire */ 96 .name = DRIVER_NAME, 97 .driver_data = 0, 98 }, { 99 .name = "imx25-fec", 100 .driver_data = FEC_QUIRK_USE_GASKET, 101 }, { 102 .name = "imx27-fec", 103 .driver_data = 0, 104 }, { 105 .name = "imx28-fec", 106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, 107 }, { 108 .name = "imx6q-fec", 109 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 110 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM, 111 }, { 112 .name = "mvf-fec", 113 .driver_data = FEC_QUIRK_ENET_MAC, 114 }, { 115 /* sentinel */ 116 } 117 }; 118 MODULE_DEVICE_TABLE(platform, fec_devtype); 119 120 enum imx_fec_type { 121 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 122 IMX27_FEC, /* runs on i.mx27/35/51 */ 123 IMX28_FEC, 124 IMX6Q_FEC, 125 MVF_FEC, 126 }; 127 128 static const struct of_device_id fec_dt_ids[] = { 129 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 130 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 131 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 132 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 133 { .compatible = "fsl,mvf-fec", .data = &fec_devtype[MVF_FEC], }, 134 { /* sentinel */ } 135 }; 136 MODULE_DEVICE_TABLE(of, fec_dt_ids); 137 138 static unsigned char macaddr[ETH_ALEN]; 139 module_param_array(macaddr, byte, NULL, 0); 140 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 141 142 #if defined(CONFIG_M5272) 143 /* 144 * Some hardware gets it MAC address out of local flash memory. 145 * if this is non-zero then assume it is the address to get MAC from. 146 */ 147 #if defined(CONFIG_NETtel) 148 #define FEC_FLASHMAC 0xf0006006 149 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 150 #define FEC_FLASHMAC 0xf0006000 151 #elif defined(CONFIG_CANCam) 152 #define FEC_FLASHMAC 0xf0020000 153 #elif defined (CONFIG_M5272C3) 154 #define FEC_FLASHMAC (0xffe04000 + 4) 155 #elif defined(CONFIG_MOD5272) 156 #define FEC_FLASHMAC 0xffc0406b 157 #else 158 #define FEC_FLASHMAC 0 159 #endif 160 #endif /* CONFIG_M5272 */ 161 162 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE) 163 #error "FEC: descriptor ring size constants too large" 164 #endif 165 166 /* Interrupt events/masks. */ 167 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ 168 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ 169 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ 170 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ 171 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ 172 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ 173 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ 174 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ 175 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ 176 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ 177 178 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) 179 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) 180 181 /* The FEC stores dest/src/type, data, and checksum for receive packets. 182 */ 183 #define PKT_MAXBUF_SIZE 1518 184 #define PKT_MINBUF_SIZE 64 185 #define PKT_MAXBLR_SIZE 1520 186 187 /* FEC receive acceleration */ 188 #define FEC_RACC_IPDIS (1 << 1) 189 #define FEC_RACC_PRODIS (1 << 2) 190 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 191 192 /* 193 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 194 * size bits. Other FEC hardware does not, so we need to take that into 195 * account when setting it. 196 */ 197 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 198 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 199 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 200 #else 201 #define OPT_FRAME_SIZE 0 202 #endif 203 204 /* FEC MII MMFR bits definition */ 205 #define FEC_MMFR_ST (1 << 30) 206 #define FEC_MMFR_OP_READ (2 << 28) 207 #define FEC_MMFR_OP_WRITE (1 << 28) 208 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 209 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 210 #define FEC_MMFR_TA (2 << 16) 211 #define FEC_MMFR_DATA(v) (v & 0xffff) 212 213 #define FEC_MII_TIMEOUT 30000 /* us */ 214 215 /* Transmitter timeout */ 216 #define TX_TIMEOUT (2 * HZ) 217 218 #define FEC_PAUSE_FLAG_AUTONEG 0x1 219 #define FEC_PAUSE_FLAG_ENABLE 0x2 220 221 static int mii_cnt; 222 223 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex) 224 { 225 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; 226 if (is_ex) 227 return (struct bufdesc *)(ex + 1); 228 else 229 return bdp + 1; 230 } 231 232 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex) 233 { 234 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; 235 if (is_ex) 236 return (struct bufdesc *)(ex - 1); 237 else 238 return bdp - 1; 239 } 240 241 static void *swap_buffer(void *bufaddr, int len) 242 { 243 int i; 244 unsigned int *buf = bufaddr; 245 246 for (i = 0; i < (len + 3) / 4; i++, buf++) 247 *buf = cpu_to_be32(*buf); 248 249 return bufaddr; 250 } 251 252 static int 253 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 254 { 255 /* Only run for packets requiring a checksum. */ 256 if (skb->ip_summed != CHECKSUM_PARTIAL) 257 return 0; 258 259 if (unlikely(skb_cow_head(skb, 0))) 260 return -1; 261 262 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 263 264 return 0; 265 } 266 267 static netdev_tx_t 268 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 269 { 270 struct fec_enet_private *fep = netdev_priv(ndev); 271 const struct platform_device_id *id_entry = 272 platform_get_device_id(fep->pdev); 273 struct bufdesc *bdp; 274 void *bufaddr; 275 unsigned short status; 276 unsigned int index; 277 278 if (!fep->link) { 279 /* Link is down or auto-negotiation is in progress. */ 280 return NETDEV_TX_BUSY; 281 } 282 283 /* Fill in a Tx ring entry */ 284 bdp = fep->cur_tx; 285 286 status = bdp->cbd_sc; 287 288 if (status & BD_ENET_TX_READY) { 289 /* Ooops. All transmit buffers are full. Bail out. 290 * This should not happen, since ndev->tbusy should be set. 291 */ 292 netdev_err(ndev, "tx queue full!\n"); 293 return NETDEV_TX_BUSY; 294 } 295 296 /* Protocol checksum off-load for TCP and UDP. */ 297 if (fec_enet_clear_csum(skb, ndev)) { 298 kfree_skb(skb); 299 return NETDEV_TX_OK; 300 } 301 302 /* Clear all of the status flags */ 303 status &= ~BD_ENET_TX_STATS; 304 305 /* Set buffer length and buffer pointer */ 306 bufaddr = skb->data; 307 bdp->cbd_datlen = skb->len; 308 309 /* 310 * On some FEC implementations data must be aligned on 311 * 4-byte boundaries. Use bounce buffers to copy data 312 * and get it aligned. Ugh. 313 */ 314 if (fep->bufdesc_ex) 315 index = (struct bufdesc_ex *)bdp - 316 (struct bufdesc_ex *)fep->tx_bd_base; 317 else 318 index = bdp - fep->tx_bd_base; 319 320 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { 321 memcpy(fep->tx_bounce[index], skb->data, skb->len); 322 bufaddr = fep->tx_bounce[index]; 323 } 324 325 /* 326 * Some design made an incorrect assumption on endian mode of 327 * the system that it's running on. As the result, driver has to 328 * swap every frame going to and coming from the controller. 329 */ 330 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 331 swap_buffer(bufaddr, skb->len); 332 333 /* Save skb pointer */ 334 fep->tx_skbuff[index] = skb; 335 336 /* Push the data cache so the CPM does not get stale memory 337 * data. 338 */ 339 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, 340 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); 341 342 /* Send it on its way. Tell FEC it's ready, interrupt when done, 343 * it's the last BD of the frame, and to put the CRC on the end. 344 */ 345 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR 346 | BD_ENET_TX_LAST | BD_ENET_TX_TC); 347 bdp->cbd_sc = status; 348 349 if (fep->bufdesc_ex) { 350 351 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 352 ebdp->cbd_bdu = 0; 353 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 354 fep->hwts_tx_en)) { 355 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT); 356 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 357 } else { 358 ebdp->cbd_esc = BD_ENET_TX_INT; 359 360 /* Enable protocol checksum flags 361 * We do not bother with the IP Checksum bits as they 362 * are done by the kernel 363 */ 364 if (skb->ip_summed == CHECKSUM_PARTIAL) 365 ebdp->cbd_esc |= BD_ENET_TX_PINS; 366 } 367 } 368 /* If this was the last BD in the ring, start at the beginning again. */ 369 if (status & BD_ENET_TX_WRAP) 370 bdp = fep->tx_bd_base; 371 else 372 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 373 374 fep->cur_tx = bdp; 375 376 if (fep->cur_tx == fep->dirty_tx) 377 netif_stop_queue(ndev); 378 379 /* Trigger transmission start */ 380 writel(0, fep->hwp + FEC_X_DES_ACTIVE); 381 382 skb_tx_timestamp(skb); 383 384 return NETDEV_TX_OK; 385 } 386 387 /* Init RX & TX buffer descriptors 388 */ 389 static void fec_enet_bd_init(struct net_device *dev) 390 { 391 struct fec_enet_private *fep = netdev_priv(dev); 392 struct bufdesc *bdp; 393 unsigned int i; 394 395 /* Initialize the receive buffer descriptors. */ 396 bdp = fep->rx_bd_base; 397 for (i = 0; i < RX_RING_SIZE; i++) { 398 399 /* Initialize the BD for every fragment in the page. */ 400 if (bdp->cbd_bufaddr) 401 bdp->cbd_sc = BD_ENET_RX_EMPTY; 402 else 403 bdp->cbd_sc = 0; 404 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 405 } 406 407 /* Set the last buffer to wrap */ 408 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); 409 bdp->cbd_sc |= BD_SC_WRAP; 410 411 fep->cur_rx = fep->rx_bd_base; 412 413 /* ...and the same for transmit */ 414 bdp = fep->tx_bd_base; 415 fep->cur_tx = bdp; 416 for (i = 0; i < TX_RING_SIZE; i++) { 417 418 /* Initialize the BD for every fragment in the page. */ 419 bdp->cbd_sc = 0; 420 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) { 421 dev_kfree_skb_any(fep->tx_skbuff[i]); 422 fep->tx_skbuff[i] = NULL; 423 } 424 bdp->cbd_bufaddr = 0; 425 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 426 } 427 428 /* Set the last buffer to wrap */ 429 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); 430 bdp->cbd_sc |= BD_SC_WRAP; 431 fep->dirty_tx = bdp; 432 } 433 434 /* This function is called to start or restart the FEC during a link 435 * change. This only happens when switching between half and full 436 * duplex. 437 */ 438 static void 439 fec_restart(struct net_device *ndev, int duplex) 440 { 441 struct fec_enet_private *fep = netdev_priv(ndev); 442 const struct platform_device_id *id_entry = 443 platform_get_device_id(fep->pdev); 444 int i; 445 u32 val; 446 u32 temp_mac[2]; 447 u32 rcntl = OPT_FRAME_SIZE | 0x04; 448 u32 ecntl = 0x2; /* ETHEREN */ 449 450 if (netif_running(ndev)) { 451 netif_device_detach(ndev); 452 napi_disable(&fep->napi); 453 netif_stop_queue(ndev); 454 netif_tx_lock(ndev); 455 } 456 457 /* Whack a reset. We should wait for this. */ 458 writel(1, fep->hwp + FEC_ECNTRL); 459 udelay(10); 460 461 /* 462 * enet-mac reset will reset mac address registers too, 463 * so need to reconfigure it. 464 */ 465 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 466 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 467 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); 468 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); 469 } 470 471 /* Clear any outstanding interrupt. */ 472 writel(0xffc00000, fep->hwp + FEC_IEVENT); 473 474 /* Reset all multicast. */ 475 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 476 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 477 #ifndef CONFIG_M5272 478 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 479 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 480 #endif 481 482 /* Set maximum receive buffer size. */ 483 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); 484 485 fec_enet_bd_init(ndev); 486 487 /* Set receive and transmit descriptor base. */ 488 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); 489 if (fep->bufdesc_ex) 490 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex) 491 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); 492 else 493 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) 494 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); 495 496 497 for (i = 0; i <= TX_RING_MOD_MASK; i++) { 498 if (fep->tx_skbuff[i]) { 499 dev_kfree_skb_any(fep->tx_skbuff[i]); 500 fep->tx_skbuff[i] = NULL; 501 } 502 } 503 504 /* Enable MII mode */ 505 if (duplex) { 506 /* FD enable */ 507 writel(0x04, fep->hwp + FEC_X_CNTRL); 508 } else { 509 /* No Rcv on Xmit */ 510 rcntl |= 0x02; 511 writel(0x0, fep->hwp + FEC_X_CNTRL); 512 } 513 514 fep->full_duplex = duplex; 515 516 /* Set MII speed */ 517 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 518 519 /* set RX checksum */ 520 val = readl(fep->hwp + FEC_RACC); 521 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 522 val |= FEC_RACC_OPTIONS; 523 else 524 val &= ~FEC_RACC_OPTIONS; 525 writel(val, fep->hwp + FEC_RACC); 526 527 /* 528 * The phy interface and speed need to get configured 529 * differently on enet-mac. 530 */ 531 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 532 /* Enable flow control and length check */ 533 rcntl |= 0x40000000 | 0x00000020; 534 535 /* RGMII, RMII or MII */ 536 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) 537 rcntl |= (1 << 6); 538 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 539 rcntl |= (1 << 8); 540 else 541 rcntl &= ~(1 << 8); 542 543 /* 1G, 100M or 10M */ 544 if (fep->phy_dev) { 545 if (fep->phy_dev->speed == SPEED_1000) 546 ecntl |= (1 << 5); 547 else if (fep->phy_dev->speed == SPEED_100) 548 rcntl &= ~(1 << 9); 549 else 550 rcntl |= (1 << 9); 551 } 552 } else { 553 #ifdef FEC_MIIGSK_ENR 554 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { 555 u32 cfgr; 556 /* disable the gasket and wait */ 557 writel(0, fep->hwp + FEC_MIIGSK_ENR); 558 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 559 udelay(1); 560 561 /* 562 * configure the gasket: 563 * RMII, 50 MHz, no loopback, no echo 564 * MII, 25 MHz, no loopback, no echo 565 */ 566 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 567 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 568 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) 569 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 570 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 571 572 /* re-enable the gasket */ 573 writel(2, fep->hwp + FEC_MIIGSK_ENR); 574 } 575 #endif 576 } 577 578 /* enable pause frame*/ 579 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 580 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 581 fep->phy_dev && fep->phy_dev->pause)) { 582 rcntl |= FEC_ENET_FCE; 583 584 /* set FIFO threshold parameter to reduce overrun */ 585 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 586 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 587 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 588 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 589 590 /* OPD */ 591 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 592 } else { 593 rcntl &= ~FEC_ENET_FCE; 594 } 595 596 writel(rcntl, fep->hwp + FEC_R_CNTRL); 597 598 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 599 /* enable ENET endian swap */ 600 ecntl |= (1 << 8); 601 /* enable ENET store and forward mode */ 602 writel(1 << 8, fep->hwp + FEC_X_WMRK); 603 } 604 605 if (fep->bufdesc_ex) 606 ecntl |= (1 << 4); 607 608 /* And last, enable the transmit and receive processing */ 609 writel(ecntl, fep->hwp + FEC_ECNTRL); 610 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 611 612 if (fep->bufdesc_ex) 613 fec_ptp_start_cyclecounter(ndev); 614 615 /* Enable interrupts we wish to service */ 616 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 617 618 if (netif_running(ndev)) { 619 netif_device_attach(ndev); 620 napi_enable(&fep->napi); 621 netif_wake_queue(ndev); 622 netif_tx_unlock(ndev); 623 } 624 } 625 626 static void 627 fec_stop(struct net_device *ndev) 628 { 629 struct fec_enet_private *fep = netdev_priv(ndev); 630 const struct platform_device_id *id_entry = 631 platform_get_device_id(fep->pdev); 632 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 633 634 /* We cannot expect a graceful transmit stop without link !!! */ 635 if (fep->link) { 636 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 637 udelay(10); 638 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 639 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 640 } 641 642 /* Whack a reset. We should wait for this. */ 643 writel(1, fep->hwp + FEC_ECNTRL); 644 udelay(10); 645 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 646 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 647 648 /* We have to keep ENET enabled to have MII interrupt stay working */ 649 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 650 writel(2, fep->hwp + FEC_ECNTRL); 651 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 652 } 653 } 654 655 656 static void 657 fec_timeout(struct net_device *ndev) 658 { 659 struct fec_enet_private *fep = netdev_priv(ndev); 660 661 ndev->stats.tx_errors++; 662 663 fep->delay_work.timeout = true; 664 schedule_delayed_work(&(fep->delay_work.delay_work), 0); 665 } 666 667 static void fec_enet_work(struct work_struct *work) 668 { 669 struct fec_enet_private *fep = 670 container_of(work, 671 struct fec_enet_private, 672 delay_work.delay_work.work); 673 674 if (fep->delay_work.timeout) { 675 fep->delay_work.timeout = false; 676 fec_restart(fep->netdev, fep->full_duplex); 677 netif_wake_queue(fep->netdev); 678 } 679 } 680 681 static void 682 fec_enet_tx(struct net_device *ndev) 683 { 684 struct fec_enet_private *fep; 685 struct bufdesc *bdp; 686 unsigned short status; 687 struct sk_buff *skb; 688 int index = 0; 689 690 fep = netdev_priv(ndev); 691 bdp = fep->dirty_tx; 692 693 /* get next bdp of dirty_tx */ 694 if (bdp->cbd_sc & BD_ENET_TX_WRAP) 695 bdp = fep->tx_bd_base; 696 else 697 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 698 699 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { 700 701 /* current queue is empty */ 702 if (bdp == fep->cur_tx) 703 break; 704 705 if (fep->bufdesc_ex) 706 index = (struct bufdesc_ex *)bdp - 707 (struct bufdesc_ex *)fep->tx_bd_base; 708 else 709 index = bdp - fep->tx_bd_base; 710 711 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 712 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); 713 bdp->cbd_bufaddr = 0; 714 715 skb = fep->tx_skbuff[index]; 716 717 /* Check for errors. */ 718 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 719 BD_ENET_TX_RL | BD_ENET_TX_UN | 720 BD_ENET_TX_CSL)) { 721 ndev->stats.tx_errors++; 722 if (status & BD_ENET_TX_HB) /* No heartbeat */ 723 ndev->stats.tx_heartbeat_errors++; 724 if (status & BD_ENET_TX_LC) /* Late collision */ 725 ndev->stats.tx_window_errors++; 726 if (status & BD_ENET_TX_RL) /* Retrans limit */ 727 ndev->stats.tx_aborted_errors++; 728 if (status & BD_ENET_TX_UN) /* Underrun */ 729 ndev->stats.tx_fifo_errors++; 730 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 731 ndev->stats.tx_carrier_errors++; 732 } else { 733 ndev->stats.tx_packets++; 734 } 735 736 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 737 fep->bufdesc_ex) { 738 struct skb_shared_hwtstamps shhwtstamps; 739 unsigned long flags; 740 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 741 742 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 743 spin_lock_irqsave(&fep->tmreg_lock, flags); 744 shhwtstamps.hwtstamp = ns_to_ktime( 745 timecounter_cyc2time(&fep->tc, ebdp->ts)); 746 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 747 skb_tstamp_tx(skb, &shhwtstamps); 748 } 749 750 if (status & BD_ENET_TX_READY) 751 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n"); 752 753 /* Deferred means some collisions occurred during transmit, 754 * but we eventually sent the packet OK. 755 */ 756 if (status & BD_ENET_TX_DEF) 757 ndev->stats.collisions++; 758 759 /* Free the sk buffer associated with this last transmit */ 760 dev_kfree_skb_any(skb); 761 fep->tx_skbuff[index] = NULL; 762 763 fep->dirty_tx = bdp; 764 765 /* Update pointer to next buffer descriptor to be transmitted */ 766 if (status & BD_ENET_TX_WRAP) 767 bdp = fep->tx_bd_base; 768 else 769 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 770 771 /* Since we have freed up a buffer, the ring is no longer full 772 */ 773 if (fep->dirty_tx != fep->cur_tx) { 774 if (netif_queue_stopped(ndev)) 775 netif_wake_queue(ndev); 776 } 777 } 778 return; 779 } 780 781 782 /* During a receive, the cur_rx points to the current incoming buffer. 783 * When we update through the ring, if the next incoming buffer has 784 * not been given to the system, we just set the empty indicator, 785 * effectively tossing the packet. 786 */ 787 static int 788 fec_enet_rx(struct net_device *ndev, int budget) 789 { 790 struct fec_enet_private *fep = netdev_priv(ndev); 791 const struct platform_device_id *id_entry = 792 platform_get_device_id(fep->pdev); 793 struct bufdesc *bdp; 794 unsigned short status; 795 struct sk_buff *skb; 796 ushort pkt_len; 797 __u8 *data; 798 int pkt_received = 0; 799 800 #ifdef CONFIG_M532x 801 flush_cache_all(); 802 #endif 803 804 /* First, grab all of the stats for the incoming packet. 805 * These get messed up if we get called due to a busy condition. 806 */ 807 bdp = fep->cur_rx; 808 809 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { 810 811 if (pkt_received >= budget) 812 break; 813 pkt_received++; 814 815 /* Since we have allocated space to hold a complete frame, 816 * the last indicator should be set. 817 */ 818 if ((status & BD_ENET_RX_LAST) == 0) 819 netdev_err(ndev, "rcv is not +last\n"); 820 821 if (!fep->opened) 822 goto rx_processing_done; 823 824 /* Check for errors. */ 825 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 826 BD_ENET_RX_CR | BD_ENET_RX_OV)) { 827 ndev->stats.rx_errors++; 828 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { 829 /* Frame too long or too short. */ 830 ndev->stats.rx_length_errors++; 831 } 832 if (status & BD_ENET_RX_NO) /* Frame alignment */ 833 ndev->stats.rx_frame_errors++; 834 if (status & BD_ENET_RX_CR) /* CRC Error */ 835 ndev->stats.rx_crc_errors++; 836 if (status & BD_ENET_RX_OV) /* FIFO overrun */ 837 ndev->stats.rx_fifo_errors++; 838 } 839 840 /* Report late collisions as a frame error. 841 * On this error, the BD is closed, but we don't know what we 842 * have in the buffer. So, just drop this frame on the floor. 843 */ 844 if (status & BD_ENET_RX_CL) { 845 ndev->stats.rx_errors++; 846 ndev->stats.rx_frame_errors++; 847 goto rx_processing_done; 848 } 849 850 /* Process the incoming frame. */ 851 ndev->stats.rx_packets++; 852 pkt_len = bdp->cbd_datlen; 853 ndev->stats.rx_bytes += pkt_len; 854 data = (__u8*)__va(bdp->cbd_bufaddr); 855 856 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 857 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); 858 859 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 860 swap_buffer(data, pkt_len); 861 862 /* This does 16 byte alignment, exactly what we need. 863 * The packet length includes FCS, but we don't want to 864 * include that when passing upstream as it messes up 865 * bridging applications. 866 */ 867 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); 868 869 if (unlikely(!skb)) { 870 ndev->stats.rx_dropped++; 871 } else { 872 skb_reserve(skb, NET_IP_ALIGN); 873 skb_put(skb, pkt_len - 4); /* Make room */ 874 skb_copy_to_linear_data(skb, data, pkt_len - 4); 875 skb->protocol = eth_type_trans(skb, ndev); 876 877 /* Get receive timestamp from the skb */ 878 if (fep->hwts_rx_en && fep->bufdesc_ex) { 879 struct skb_shared_hwtstamps *shhwtstamps = 880 skb_hwtstamps(skb); 881 unsigned long flags; 882 struct bufdesc_ex *ebdp = 883 (struct bufdesc_ex *)bdp; 884 885 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 886 887 spin_lock_irqsave(&fep->tmreg_lock, flags); 888 shhwtstamps->hwtstamp = ns_to_ktime( 889 timecounter_cyc2time(&fep->tc, ebdp->ts)); 890 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 891 } 892 893 if (fep->bufdesc_ex && 894 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 895 struct bufdesc_ex *ebdp = 896 (struct bufdesc_ex *)bdp; 897 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) { 898 /* don't check it */ 899 skb->ip_summed = CHECKSUM_UNNECESSARY; 900 } else { 901 skb_checksum_none_assert(skb); 902 } 903 } 904 905 if (!skb_defer_rx_timestamp(skb)) 906 napi_gro_receive(&fep->napi, skb); 907 } 908 909 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data, 910 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); 911 rx_processing_done: 912 /* Clear the status flags for this buffer */ 913 status &= ~BD_ENET_RX_STATS; 914 915 /* Mark the buffer empty */ 916 status |= BD_ENET_RX_EMPTY; 917 bdp->cbd_sc = status; 918 919 if (fep->bufdesc_ex) { 920 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 921 922 ebdp->cbd_esc = BD_ENET_RX_INT; 923 ebdp->cbd_prot = 0; 924 ebdp->cbd_bdu = 0; 925 } 926 927 /* Update BD pointer to next entry */ 928 if (status & BD_ENET_RX_WRAP) 929 bdp = fep->rx_bd_base; 930 else 931 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 932 /* Doing this here will keep the FEC running while we process 933 * incoming frames. On a heavily loaded network, we should be 934 * able to keep up at the expense of system resources. 935 */ 936 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 937 } 938 fep->cur_rx = bdp; 939 940 return pkt_received; 941 } 942 943 static irqreturn_t 944 fec_enet_interrupt(int irq, void *dev_id) 945 { 946 struct net_device *ndev = dev_id; 947 struct fec_enet_private *fep = netdev_priv(ndev); 948 uint int_events; 949 irqreturn_t ret = IRQ_NONE; 950 951 do { 952 int_events = readl(fep->hwp + FEC_IEVENT); 953 writel(int_events, fep->hwp + FEC_IEVENT); 954 955 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) { 956 ret = IRQ_HANDLED; 957 958 /* Disable the RX interrupt */ 959 if (napi_schedule_prep(&fep->napi)) { 960 writel(FEC_RX_DISABLED_IMASK, 961 fep->hwp + FEC_IMASK); 962 __napi_schedule(&fep->napi); 963 } 964 } 965 966 if (int_events & FEC_ENET_MII) { 967 ret = IRQ_HANDLED; 968 complete(&fep->mdio_done); 969 } 970 } while (int_events); 971 972 return ret; 973 } 974 975 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 976 { 977 struct net_device *ndev = napi->dev; 978 int pkts = fec_enet_rx(ndev, budget); 979 struct fec_enet_private *fep = netdev_priv(ndev); 980 981 fec_enet_tx(ndev); 982 983 if (pkts < budget) { 984 napi_complete(napi); 985 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 986 } 987 return pkts; 988 } 989 990 /* ------------------------------------------------------------------------- */ 991 static void fec_get_mac(struct net_device *ndev) 992 { 993 struct fec_enet_private *fep = netdev_priv(ndev); 994 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 995 unsigned char *iap, tmpaddr[ETH_ALEN]; 996 997 /* 998 * try to get mac address in following order: 999 * 1000 * 1) module parameter via kernel command line in form 1001 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1002 */ 1003 iap = macaddr; 1004 1005 /* 1006 * 2) from device tree data 1007 */ 1008 if (!is_valid_ether_addr(iap)) { 1009 struct device_node *np = fep->pdev->dev.of_node; 1010 if (np) { 1011 const char *mac = of_get_mac_address(np); 1012 if (mac) 1013 iap = (unsigned char *) mac; 1014 } 1015 } 1016 1017 /* 1018 * 3) from flash or fuse (via platform data) 1019 */ 1020 if (!is_valid_ether_addr(iap)) { 1021 #ifdef CONFIG_M5272 1022 if (FEC_FLASHMAC) 1023 iap = (unsigned char *)FEC_FLASHMAC; 1024 #else 1025 if (pdata) 1026 iap = (unsigned char *)&pdata->mac; 1027 #endif 1028 } 1029 1030 /* 1031 * 4) FEC mac registers set by bootloader 1032 */ 1033 if (!is_valid_ether_addr(iap)) { 1034 *((unsigned long *) &tmpaddr[0]) = 1035 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); 1036 *((unsigned short *) &tmpaddr[4]) = 1037 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1038 iap = &tmpaddr[0]; 1039 } 1040 1041 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1042 1043 /* Adjust MAC if using macaddr */ 1044 if (iap == macaddr) 1045 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1046 } 1047 1048 /* ------------------------------------------------------------------------- */ 1049 1050 /* 1051 * Phy section 1052 */ 1053 static void fec_enet_adjust_link(struct net_device *ndev) 1054 { 1055 struct fec_enet_private *fep = netdev_priv(ndev); 1056 struct phy_device *phy_dev = fep->phy_dev; 1057 int status_change = 0; 1058 1059 /* Prevent a state halted on mii error */ 1060 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 1061 phy_dev->state = PHY_RESUMING; 1062 return; 1063 } 1064 1065 if (phy_dev->link) { 1066 if (!fep->link) { 1067 fep->link = phy_dev->link; 1068 status_change = 1; 1069 } 1070 1071 if (fep->full_duplex != phy_dev->duplex) 1072 status_change = 1; 1073 1074 if (phy_dev->speed != fep->speed) { 1075 fep->speed = phy_dev->speed; 1076 status_change = 1; 1077 } 1078 1079 /* if any of the above changed restart the FEC */ 1080 if (status_change) 1081 fec_restart(ndev, phy_dev->duplex); 1082 } else { 1083 if (fep->link) { 1084 fec_stop(ndev); 1085 fep->link = phy_dev->link; 1086 status_change = 1; 1087 } 1088 } 1089 1090 if (status_change) 1091 phy_print_status(phy_dev); 1092 } 1093 1094 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1095 { 1096 struct fec_enet_private *fep = bus->priv; 1097 unsigned long time_left; 1098 1099 fep->mii_timeout = 0; 1100 init_completion(&fep->mdio_done); 1101 1102 /* start a read op */ 1103 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 1104 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1105 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1106 1107 /* wait for end of transfer */ 1108 time_left = wait_for_completion_timeout(&fep->mdio_done, 1109 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1110 if (time_left == 0) { 1111 fep->mii_timeout = 1; 1112 netdev_err(fep->netdev, "MDIO read timeout\n"); 1113 return -ETIMEDOUT; 1114 } 1115 1116 /* return value */ 1117 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1118 } 1119 1120 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1121 u16 value) 1122 { 1123 struct fec_enet_private *fep = bus->priv; 1124 unsigned long time_left; 1125 1126 fep->mii_timeout = 0; 1127 init_completion(&fep->mdio_done); 1128 1129 /* start a write op */ 1130 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 1131 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1132 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1133 fep->hwp + FEC_MII_DATA); 1134 1135 /* wait for end of transfer */ 1136 time_left = wait_for_completion_timeout(&fep->mdio_done, 1137 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1138 if (time_left == 0) { 1139 fep->mii_timeout = 1; 1140 netdev_err(fep->netdev, "MDIO write timeout\n"); 1141 return -ETIMEDOUT; 1142 } 1143 1144 return 0; 1145 } 1146 1147 static int fec_enet_mdio_reset(struct mii_bus *bus) 1148 { 1149 return 0; 1150 } 1151 1152 static int fec_enet_mii_probe(struct net_device *ndev) 1153 { 1154 struct fec_enet_private *fep = netdev_priv(ndev); 1155 const struct platform_device_id *id_entry = 1156 platform_get_device_id(fep->pdev); 1157 struct phy_device *phy_dev = NULL; 1158 char mdio_bus_id[MII_BUS_ID_SIZE]; 1159 char phy_name[MII_BUS_ID_SIZE + 3]; 1160 int phy_id; 1161 int dev_id = fep->dev_id; 1162 1163 fep->phy_dev = NULL; 1164 1165 /* check for attached phy */ 1166 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1167 if ((fep->mii_bus->phy_mask & (1 << phy_id))) 1168 continue; 1169 if (fep->mii_bus->phy_map[phy_id] == NULL) 1170 continue; 1171 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) 1172 continue; 1173 if (dev_id--) 1174 continue; 1175 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1176 break; 1177 } 1178 1179 if (phy_id >= PHY_MAX_ADDR) { 1180 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1181 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 1182 phy_id = 0; 1183 } 1184 1185 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); 1186 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 1187 fep->phy_interface); 1188 if (IS_ERR(phy_dev)) { 1189 netdev_err(ndev, "could not attach to PHY\n"); 1190 return PTR_ERR(phy_dev); 1191 } 1192 1193 /* mask with MAC supported features */ 1194 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) { 1195 phy_dev->supported &= PHY_GBIT_FEATURES; 1196 phy_dev->supported |= SUPPORTED_Pause; 1197 } 1198 else 1199 phy_dev->supported &= PHY_BASIC_FEATURES; 1200 1201 phy_dev->advertising = phy_dev->supported; 1202 1203 fep->phy_dev = phy_dev; 1204 fep->link = 0; 1205 fep->full_duplex = 0; 1206 1207 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 1208 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), 1209 fep->phy_dev->irq); 1210 1211 return 0; 1212 } 1213 1214 static int fec_enet_mii_init(struct platform_device *pdev) 1215 { 1216 static struct mii_bus *fec0_mii_bus; 1217 struct net_device *ndev = platform_get_drvdata(pdev); 1218 struct fec_enet_private *fep = netdev_priv(ndev); 1219 const struct platform_device_id *id_entry = 1220 platform_get_device_id(fep->pdev); 1221 int err = -ENXIO, i; 1222 1223 /* 1224 * The dual fec interfaces are not equivalent with enet-mac. 1225 * Here are the differences: 1226 * 1227 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1228 * - fec0 acts as the 1588 time master while fec1 is slave 1229 * - external phys can only be configured by fec0 1230 * 1231 * That is to say fec1 can not work independently. It only works 1232 * when fec0 is working. The reason behind this design is that the 1233 * second interface is added primarily for Switch mode. 1234 * 1235 * Because of the last point above, both phys are attached on fec0 1236 * mdio interface in board design, and need to be configured by 1237 * fec0 mii_bus. 1238 */ 1239 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { 1240 /* fec1 uses fec0 mii_bus */ 1241 if (mii_cnt && fec0_mii_bus) { 1242 fep->mii_bus = fec0_mii_bus; 1243 mii_cnt++; 1244 return 0; 1245 } 1246 return -ENOENT; 1247 } 1248 1249 fep->mii_timeout = 0; 1250 1251 /* 1252 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 1253 * 1254 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 1255 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 1256 * Reference Manual has an error on this, and gets fixed on i.MX6Q 1257 * document. 1258 */ 1259 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000); 1260 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1261 fep->phy_speed--; 1262 fep->phy_speed <<= 1; 1263 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1264 1265 fep->mii_bus = mdiobus_alloc(); 1266 if (fep->mii_bus == NULL) { 1267 err = -ENOMEM; 1268 goto err_out; 1269 } 1270 1271 fep->mii_bus->name = "fec_enet_mii_bus"; 1272 fep->mii_bus->read = fec_enet_mdio_read; 1273 fep->mii_bus->write = fec_enet_mdio_write; 1274 fep->mii_bus->reset = fec_enet_mdio_reset; 1275 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1276 pdev->name, fep->dev_id + 1); 1277 fep->mii_bus->priv = fep; 1278 fep->mii_bus->parent = &pdev->dev; 1279 1280 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 1281 if (!fep->mii_bus->irq) { 1282 err = -ENOMEM; 1283 goto err_out_free_mdiobus; 1284 } 1285 1286 for (i = 0; i < PHY_MAX_ADDR; i++) 1287 fep->mii_bus->irq[i] = PHY_POLL; 1288 1289 if (mdiobus_register(fep->mii_bus)) 1290 goto err_out_free_mdio_irq; 1291 1292 mii_cnt++; 1293 1294 /* save fec0 mii_bus */ 1295 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1296 fec0_mii_bus = fep->mii_bus; 1297 1298 return 0; 1299 1300 err_out_free_mdio_irq: 1301 kfree(fep->mii_bus->irq); 1302 err_out_free_mdiobus: 1303 mdiobus_free(fep->mii_bus); 1304 err_out: 1305 return err; 1306 } 1307 1308 static void fec_enet_mii_remove(struct fec_enet_private *fep) 1309 { 1310 if (--mii_cnt == 0) { 1311 mdiobus_unregister(fep->mii_bus); 1312 kfree(fep->mii_bus->irq); 1313 mdiobus_free(fep->mii_bus); 1314 } 1315 } 1316 1317 static int fec_enet_get_settings(struct net_device *ndev, 1318 struct ethtool_cmd *cmd) 1319 { 1320 struct fec_enet_private *fep = netdev_priv(ndev); 1321 struct phy_device *phydev = fep->phy_dev; 1322 1323 if (!phydev) 1324 return -ENODEV; 1325 1326 return phy_ethtool_gset(phydev, cmd); 1327 } 1328 1329 static int fec_enet_set_settings(struct net_device *ndev, 1330 struct ethtool_cmd *cmd) 1331 { 1332 struct fec_enet_private *fep = netdev_priv(ndev); 1333 struct phy_device *phydev = fep->phy_dev; 1334 1335 if (!phydev) 1336 return -ENODEV; 1337 1338 return phy_ethtool_sset(phydev, cmd); 1339 } 1340 1341 static void fec_enet_get_drvinfo(struct net_device *ndev, 1342 struct ethtool_drvinfo *info) 1343 { 1344 struct fec_enet_private *fep = netdev_priv(ndev); 1345 1346 strlcpy(info->driver, fep->pdev->dev.driver->name, 1347 sizeof(info->driver)); 1348 strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); 1349 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 1350 } 1351 1352 static int fec_enet_get_ts_info(struct net_device *ndev, 1353 struct ethtool_ts_info *info) 1354 { 1355 struct fec_enet_private *fep = netdev_priv(ndev); 1356 1357 if (fep->bufdesc_ex) { 1358 1359 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1360 SOF_TIMESTAMPING_RX_SOFTWARE | 1361 SOF_TIMESTAMPING_SOFTWARE | 1362 SOF_TIMESTAMPING_TX_HARDWARE | 1363 SOF_TIMESTAMPING_RX_HARDWARE | 1364 SOF_TIMESTAMPING_RAW_HARDWARE; 1365 if (fep->ptp_clock) 1366 info->phc_index = ptp_clock_index(fep->ptp_clock); 1367 else 1368 info->phc_index = -1; 1369 1370 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 1371 (1 << HWTSTAMP_TX_ON); 1372 1373 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 1374 (1 << HWTSTAMP_FILTER_ALL); 1375 return 0; 1376 } else { 1377 return ethtool_op_get_ts_info(ndev, info); 1378 } 1379 } 1380 1381 static void fec_enet_get_pauseparam(struct net_device *ndev, 1382 struct ethtool_pauseparam *pause) 1383 { 1384 struct fec_enet_private *fep = netdev_priv(ndev); 1385 1386 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 1387 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 1388 pause->rx_pause = pause->tx_pause; 1389 } 1390 1391 static int fec_enet_set_pauseparam(struct net_device *ndev, 1392 struct ethtool_pauseparam *pause) 1393 { 1394 struct fec_enet_private *fep = netdev_priv(ndev); 1395 1396 if (pause->tx_pause != pause->rx_pause) { 1397 netdev_info(ndev, 1398 "hardware only support enable/disable both tx and rx"); 1399 return -EINVAL; 1400 } 1401 1402 fep->pause_flag = 0; 1403 1404 /* tx pause must be same as rx pause */ 1405 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 1406 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 1407 1408 if (pause->rx_pause || pause->autoneg) { 1409 fep->phy_dev->supported |= ADVERTISED_Pause; 1410 fep->phy_dev->advertising |= ADVERTISED_Pause; 1411 } else { 1412 fep->phy_dev->supported &= ~ADVERTISED_Pause; 1413 fep->phy_dev->advertising &= ~ADVERTISED_Pause; 1414 } 1415 1416 if (pause->autoneg) { 1417 if (netif_running(ndev)) 1418 fec_stop(ndev); 1419 phy_start_aneg(fep->phy_dev); 1420 } 1421 if (netif_running(ndev)) 1422 fec_restart(ndev, 0); 1423 1424 return 0; 1425 } 1426 1427 static const struct ethtool_ops fec_enet_ethtool_ops = { 1428 .get_pauseparam = fec_enet_get_pauseparam, 1429 .set_pauseparam = fec_enet_set_pauseparam, 1430 .get_settings = fec_enet_get_settings, 1431 .set_settings = fec_enet_set_settings, 1432 .get_drvinfo = fec_enet_get_drvinfo, 1433 .get_link = ethtool_op_get_link, 1434 .get_ts_info = fec_enet_get_ts_info, 1435 }; 1436 1437 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 1438 { 1439 struct fec_enet_private *fep = netdev_priv(ndev); 1440 struct phy_device *phydev = fep->phy_dev; 1441 1442 if (!netif_running(ndev)) 1443 return -EINVAL; 1444 1445 if (!phydev) 1446 return -ENODEV; 1447 1448 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex) 1449 return fec_ptp_ioctl(ndev, rq, cmd); 1450 1451 return phy_mii_ioctl(phydev, rq, cmd); 1452 } 1453 1454 static void fec_enet_free_buffers(struct net_device *ndev) 1455 { 1456 struct fec_enet_private *fep = netdev_priv(ndev); 1457 unsigned int i; 1458 struct sk_buff *skb; 1459 struct bufdesc *bdp; 1460 1461 bdp = fep->rx_bd_base; 1462 for (i = 0; i < RX_RING_SIZE; i++) { 1463 skb = fep->rx_skbuff[i]; 1464 1465 if (bdp->cbd_bufaddr) 1466 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 1467 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1468 if (skb) 1469 dev_kfree_skb(skb); 1470 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 1471 } 1472 1473 bdp = fep->tx_bd_base; 1474 for (i = 0; i < TX_RING_SIZE; i++) 1475 kfree(fep->tx_bounce[i]); 1476 } 1477 1478 static int fec_enet_alloc_buffers(struct net_device *ndev) 1479 { 1480 struct fec_enet_private *fep = netdev_priv(ndev); 1481 unsigned int i; 1482 struct sk_buff *skb; 1483 struct bufdesc *bdp; 1484 1485 bdp = fep->rx_bd_base; 1486 for (i = 0; i < RX_RING_SIZE; i++) { 1487 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1488 if (!skb) { 1489 fec_enet_free_buffers(ndev); 1490 return -ENOMEM; 1491 } 1492 fep->rx_skbuff[i] = skb; 1493 1494 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, 1495 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1496 bdp->cbd_sc = BD_ENET_RX_EMPTY; 1497 1498 if (fep->bufdesc_ex) { 1499 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1500 ebdp->cbd_esc = BD_ENET_RX_INT; 1501 } 1502 1503 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 1504 } 1505 1506 /* Set the last buffer to wrap. */ 1507 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); 1508 bdp->cbd_sc |= BD_SC_WRAP; 1509 1510 bdp = fep->tx_bd_base; 1511 for (i = 0; i < TX_RING_SIZE; i++) { 1512 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 1513 1514 bdp->cbd_sc = 0; 1515 bdp->cbd_bufaddr = 0; 1516 1517 if (fep->bufdesc_ex) { 1518 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1519 ebdp->cbd_esc = BD_ENET_TX_INT; 1520 } 1521 1522 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 1523 } 1524 1525 /* Set the last buffer to wrap. */ 1526 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); 1527 bdp->cbd_sc |= BD_SC_WRAP; 1528 1529 return 0; 1530 } 1531 1532 static int 1533 fec_enet_open(struct net_device *ndev) 1534 { 1535 struct fec_enet_private *fep = netdev_priv(ndev); 1536 int ret; 1537 1538 napi_enable(&fep->napi); 1539 1540 /* I should reset the ring buffers here, but I don't yet know 1541 * a simple way to do that. 1542 */ 1543 1544 ret = fec_enet_alloc_buffers(ndev); 1545 if (ret) 1546 return ret; 1547 1548 /* Probe and connect to PHY when open the interface */ 1549 ret = fec_enet_mii_probe(ndev); 1550 if (ret) { 1551 fec_enet_free_buffers(ndev); 1552 return ret; 1553 } 1554 phy_start(fep->phy_dev); 1555 netif_start_queue(ndev); 1556 fep->opened = 1; 1557 return 0; 1558 } 1559 1560 static int 1561 fec_enet_close(struct net_device *ndev) 1562 { 1563 struct fec_enet_private *fep = netdev_priv(ndev); 1564 1565 /* Don't know what to do yet. */ 1566 napi_disable(&fep->napi); 1567 fep->opened = 0; 1568 netif_stop_queue(ndev); 1569 fec_stop(ndev); 1570 1571 if (fep->phy_dev) { 1572 phy_stop(fep->phy_dev); 1573 phy_disconnect(fep->phy_dev); 1574 } 1575 1576 fec_enet_free_buffers(ndev); 1577 1578 return 0; 1579 } 1580 1581 /* Set or clear the multicast filter for this adaptor. 1582 * Skeleton taken from sunlance driver. 1583 * The CPM Ethernet implementation allows Multicast as well as individual 1584 * MAC address filtering. Some of the drivers check to make sure it is 1585 * a group multicast address, and discard those that are not. I guess I 1586 * will do the same for now, but just remove the test if you want 1587 * individual filtering as well (do the upper net layers want or support 1588 * this kind of feature?). 1589 */ 1590 1591 #define HASH_BITS 6 /* #bits in hash */ 1592 #define CRC32_POLY 0xEDB88320 1593 1594 static void set_multicast_list(struct net_device *ndev) 1595 { 1596 struct fec_enet_private *fep = netdev_priv(ndev); 1597 struct netdev_hw_addr *ha; 1598 unsigned int i, bit, data, crc, tmp; 1599 unsigned char hash; 1600 1601 if (ndev->flags & IFF_PROMISC) { 1602 tmp = readl(fep->hwp + FEC_R_CNTRL); 1603 tmp |= 0x8; 1604 writel(tmp, fep->hwp + FEC_R_CNTRL); 1605 return; 1606 } 1607 1608 tmp = readl(fep->hwp + FEC_R_CNTRL); 1609 tmp &= ~0x8; 1610 writel(tmp, fep->hwp + FEC_R_CNTRL); 1611 1612 if (ndev->flags & IFF_ALLMULTI) { 1613 /* Catch all multicast addresses, so set the 1614 * filter to all 1's 1615 */ 1616 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1617 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1618 1619 return; 1620 } 1621 1622 /* Clear filter and add the addresses in hash register 1623 */ 1624 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1625 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1626 1627 netdev_for_each_mc_addr(ha, ndev) { 1628 /* calculate crc32 value of mac address */ 1629 crc = 0xffffffff; 1630 1631 for (i = 0; i < ndev->addr_len; i++) { 1632 data = ha->addr[i]; 1633 for (bit = 0; bit < 8; bit++, data >>= 1) { 1634 crc = (crc >> 1) ^ 1635 (((crc ^ data) & 1) ? CRC32_POLY : 0); 1636 } 1637 } 1638 1639 /* only upper 6 bits (HASH_BITS) are used 1640 * which point to specific bit in he hash registers 1641 */ 1642 hash = (crc >> (32 - HASH_BITS)) & 0x3f; 1643 1644 if (hash > 31) { 1645 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1646 tmp |= 1 << (hash - 32); 1647 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1648 } else { 1649 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1650 tmp |= 1 << hash; 1651 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1652 } 1653 } 1654 } 1655 1656 /* Set a MAC change in hardware. */ 1657 static int 1658 fec_set_mac_address(struct net_device *ndev, void *p) 1659 { 1660 struct fec_enet_private *fep = netdev_priv(ndev); 1661 struct sockaddr *addr = p; 1662 1663 if (!is_valid_ether_addr(addr->sa_data)) 1664 return -EADDRNOTAVAIL; 1665 1666 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 1667 1668 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 1669 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 1670 fep->hwp + FEC_ADDR_LOW); 1671 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 1672 fep->hwp + FEC_ADDR_HIGH); 1673 return 0; 1674 } 1675 1676 #ifdef CONFIG_NET_POLL_CONTROLLER 1677 /** 1678 * fec_poll_controller - FEC Poll controller function 1679 * @dev: The FEC network adapter 1680 * 1681 * Polled functionality used by netconsole and others in non interrupt mode 1682 * 1683 */ 1684 static void fec_poll_controller(struct net_device *dev) 1685 { 1686 int i; 1687 struct fec_enet_private *fep = netdev_priv(dev); 1688 1689 for (i = 0; i < FEC_IRQ_NUM; i++) { 1690 if (fep->irq[i] > 0) { 1691 disable_irq(fep->irq[i]); 1692 fec_enet_interrupt(fep->irq[i], dev); 1693 enable_irq(fep->irq[i]); 1694 } 1695 } 1696 } 1697 #endif 1698 1699 static int fec_set_features(struct net_device *netdev, 1700 netdev_features_t features) 1701 { 1702 struct fec_enet_private *fep = netdev_priv(netdev); 1703 netdev_features_t changed = features ^ netdev->features; 1704 1705 netdev->features = features; 1706 1707 /* Receive checksum has been changed */ 1708 if (changed & NETIF_F_RXCSUM) { 1709 if (features & NETIF_F_RXCSUM) 1710 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 1711 else 1712 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 1713 1714 if (netif_running(netdev)) { 1715 fec_stop(netdev); 1716 fec_restart(netdev, fep->phy_dev->duplex); 1717 netif_wake_queue(netdev); 1718 } else { 1719 fec_restart(netdev, fep->phy_dev->duplex); 1720 } 1721 } 1722 1723 return 0; 1724 } 1725 1726 static const struct net_device_ops fec_netdev_ops = { 1727 .ndo_open = fec_enet_open, 1728 .ndo_stop = fec_enet_close, 1729 .ndo_start_xmit = fec_enet_start_xmit, 1730 .ndo_set_rx_mode = set_multicast_list, 1731 .ndo_change_mtu = eth_change_mtu, 1732 .ndo_validate_addr = eth_validate_addr, 1733 .ndo_tx_timeout = fec_timeout, 1734 .ndo_set_mac_address = fec_set_mac_address, 1735 .ndo_do_ioctl = fec_enet_ioctl, 1736 #ifdef CONFIG_NET_POLL_CONTROLLER 1737 .ndo_poll_controller = fec_poll_controller, 1738 #endif 1739 .ndo_set_features = fec_set_features, 1740 }; 1741 1742 /* 1743 * XXX: We need to clean up on failure exits here. 1744 * 1745 */ 1746 static int fec_enet_init(struct net_device *ndev) 1747 { 1748 struct fec_enet_private *fep = netdev_priv(ndev); 1749 const struct platform_device_id *id_entry = 1750 platform_get_device_id(fep->pdev); 1751 struct bufdesc *cbd_base; 1752 1753 /* Allocate memory for buffer descriptors. */ 1754 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, 1755 GFP_KERNEL); 1756 if (!cbd_base) 1757 return -ENOMEM; 1758 1759 memset(cbd_base, 0, PAGE_SIZE); 1760 1761 fep->netdev = ndev; 1762 1763 /* Get the Ethernet address */ 1764 fec_get_mac(ndev); 1765 1766 /* Set receive and transmit descriptor base. */ 1767 fep->rx_bd_base = cbd_base; 1768 if (fep->bufdesc_ex) 1769 fep->tx_bd_base = (struct bufdesc *) 1770 (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE); 1771 else 1772 fep->tx_bd_base = cbd_base + RX_RING_SIZE; 1773 1774 /* The FEC Ethernet specific entries in the device structure */ 1775 ndev->watchdog_timeo = TX_TIMEOUT; 1776 ndev->netdev_ops = &fec_netdev_ops; 1777 ndev->ethtool_ops = &fec_enet_ethtool_ops; 1778 1779 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 1780 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT); 1781 1782 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) { 1783 /* enable hw accelerator */ 1784 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 1785 | NETIF_F_RXCSUM); 1786 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 1787 | NETIF_F_RXCSUM); 1788 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 1789 } 1790 1791 fec_restart(ndev, 0); 1792 1793 return 0; 1794 } 1795 1796 #ifdef CONFIG_OF 1797 static void fec_reset_phy(struct platform_device *pdev) 1798 { 1799 int err, phy_reset; 1800 int msec = 1; 1801 struct device_node *np = pdev->dev.of_node; 1802 1803 if (!np) 1804 return; 1805 1806 of_property_read_u32(np, "phy-reset-duration", &msec); 1807 /* A sane reset duration should not be longer than 1s */ 1808 if (msec > 1000) 1809 msec = 1; 1810 1811 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 1812 if (!gpio_is_valid(phy_reset)) 1813 return; 1814 1815 err = devm_gpio_request_one(&pdev->dev, phy_reset, 1816 GPIOF_OUT_INIT_LOW, "phy-reset"); 1817 if (err) { 1818 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 1819 return; 1820 } 1821 msleep(msec); 1822 gpio_set_value(phy_reset, 1); 1823 } 1824 #else /* CONFIG_OF */ 1825 static void fec_reset_phy(struct platform_device *pdev) 1826 { 1827 /* 1828 * In case of platform probe, the reset has been done 1829 * by machine code. 1830 */ 1831 } 1832 #endif /* CONFIG_OF */ 1833 1834 static int 1835 fec_probe(struct platform_device *pdev) 1836 { 1837 struct fec_enet_private *fep; 1838 struct fec_platform_data *pdata; 1839 struct net_device *ndev; 1840 int i, irq, ret = 0; 1841 struct resource *r; 1842 const struct of_device_id *of_id; 1843 static int dev_id; 1844 struct pinctrl *pinctrl; 1845 struct regulator *reg_phy; 1846 1847 of_id = of_match_device(fec_dt_ids, &pdev->dev); 1848 if (of_id) 1849 pdev->id_entry = of_id->data; 1850 1851 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1852 if (!r) 1853 return -ENXIO; 1854 1855 /* Init network device */ 1856 ndev = alloc_etherdev(sizeof(struct fec_enet_private)); 1857 if (!ndev) 1858 return -ENOMEM; 1859 1860 SET_NETDEV_DEV(ndev, &pdev->dev); 1861 1862 /* setup board info structure */ 1863 fep = netdev_priv(ndev); 1864 1865 /* default enable pause frame auto negotiation */ 1866 if (pdev->id_entry && 1867 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT)) 1868 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 1869 1870 fep->hwp = devm_request_and_ioremap(&pdev->dev, r); 1871 fep->pdev = pdev; 1872 fep->dev_id = dev_id++; 1873 1874 fep->bufdesc_ex = 0; 1875 1876 if (!fep->hwp) { 1877 ret = -ENOMEM; 1878 goto failed_ioremap; 1879 } 1880 1881 platform_set_drvdata(pdev, ndev); 1882 1883 ret = of_get_phy_mode(pdev->dev.of_node); 1884 if (ret < 0) { 1885 pdata = pdev->dev.platform_data; 1886 if (pdata) 1887 fep->phy_interface = pdata->phy; 1888 else 1889 fep->phy_interface = PHY_INTERFACE_MODE_MII; 1890 } else { 1891 fep->phy_interface = ret; 1892 } 1893 1894 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 1895 if (IS_ERR(pinctrl)) { 1896 ret = PTR_ERR(pinctrl); 1897 goto failed_pin; 1898 } 1899 1900 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1901 if (IS_ERR(fep->clk_ipg)) { 1902 ret = PTR_ERR(fep->clk_ipg); 1903 goto failed_clk; 1904 } 1905 1906 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1907 if (IS_ERR(fep->clk_ahb)) { 1908 ret = PTR_ERR(fep->clk_ahb); 1909 goto failed_clk; 1910 } 1911 1912 /* enet_out is optional, depends on board */ 1913 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 1914 if (IS_ERR(fep->clk_enet_out)) 1915 fep->clk_enet_out = NULL; 1916 1917 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 1918 fep->bufdesc_ex = 1919 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX; 1920 if (IS_ERR(fep->clk_ptp)) { 1921 fep->clk_ptp = NULL; 1922 fep->bufdesc_ex = 0; 1923 } 1924 1925 clk_prepare_enable(fep->clk_ahb); 1926 clk_prepare_enable(fep->clk_ipg); 1927 clk_prepare_enable(fep->clk_enet_out); 1928 clk_prepare_enable(fep->clk_ptp); 1929 1930 reg_phy = devm_regulator_get(&pdev->dev, "phy"); 1931 if (!IS_ERR(reg_phy)) { 1932 ret = regulator_enable(reg_phy); 1933 if (ret) { 1934 dev_err(&pdev->dev, 1935 "Failed to enable phy regulator: %d\n", ret); 1936 goto failed_regulator; 1937 } 1938 } 1939 1940 fec_reset_phy(pdev); 1941 1942 if (fep->bufdesc_ex) 1943 fec_ptp_init(ndev, pdev); 1944 1945 ret = fec_enet_init(ndev); 1946 if (ret) 1947 goto failed_init; 1948 1949 for (i = 0; i < FEC_IRQ_NUM; i++) { 1950 irq = platform_get_irq(pdev, i); 1951 if (irq < 0) { 1952 if (i) 1953 break; 1954 ret = irq; 1955 goto failed_irq; 1956 } 1957 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); 1958 if (ret) { 1959 while (--i >= 0) { 1960 irq = platform_get_irq(pdev, i); 1961 free_irq(irq, ndev); 1962 } 1963 goto failed_irq; 1964 } 1965 } 1966 1967 ret = fec_enet_mii_init(pdev); 1968 if (ret) 1969 goto failed_mii_init; 1970 1971 /* Carrier starts down, phylib will bring it up */ 1972 netif_carrier_off(ndev); 1973 1974 ret = register_netdev(ndev); 1975 if (ret) 1976 goto failed_register; 1977 1978 if (fep->bufdesc_ex && fep->ptp_clock) 1979 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 1980 1981 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work); 1982 return 0; 1983 1984 failed_register: 1985 fec_enet_mii_remove(fep); 1986 failed_mii_init: 1987 failed_init: 1988 for (i = 0; i < FEC_IRQ_NUM; i++) { 1989 irq = platform_get_irq(pdev, i); 1990 if (irq > 0) 1991 free_irq(irq, ndev); 1992 } 1993 failed_irq: 1994 failed_regulator: 1995 clk_disable_unprepare(fep->clk_ahb); 1996 clk_disable_unprepare(fep->clk_ipg); 1997 clk_disable_unprepare(fep->clk_enet_out); 1998 clk_disable_unprepare(fep->clk_ptp); 1999 failed_pin: 2000 failed_clk: 2001 failed_ioremap: 2002 free_netdev(ndev); 2003 2004 return ret; 2005 } 2006 2007 static int 2008 fec_drv_remove(struct platform_device *pdev) 2009 { 2010 struct net_device *ndev = platform_get_drvdata(pdev); 2011 struct fec_enet_private *fep = netdev_priv(ndev); 2012 int i; 2013 2014 cancel_delayed_work_sync(&(fep->delay_work.delay_work)); 2015 unregister_netdev(ndev); 2016 fec_enet_mii_remove(fep); 2017 del_timer_sync(&fep->time_keep); 2018 clk_disable_unprepare(fep->clk_ptp); 2019 if (fep->ptp_clock) 2020 ptp_clock_unregister(fep->ptp_clock); 2021 clk_disable_unprepare(fep->clk_enet_out); 2022 clk_disable_unprepare(fep->clk_ahb); 2023 clk_disable_unprepare(fep->clk_ipg); 2024 for (i = 0; i < FEC_IRQ_NUM; i++) { 2025 int irq = platform_get_irq(pdev, i); 2026 if (irq > 0) 2027 free_irq(irq, ndev); 2028 } 2029 free_netdev(ndev); 2030 2031 platform_set_drvdata(pdev, NULL); 2032 2033 return 0; 2034 } 2035 2036 #ifdef CONFIG_PM_SLEEP 2037 static int 2038 fec_suspend(struct device *dev) 2039 { 2040 struct net_device *ndev = dev_get_drvdata(dev); 2041 struct fec_enet_private *fep = netdev_priv(ndev); 2042 2043 if (netif_running(ndev)) { 2044 fec_stop(ndev); 2045 netif_device_detach(ndev); 2046 } 2047 clk_disable_unprepare(fep->clk_enet_out); 2048 clk_disable_unprepare(fep->clk_ahb); 2049 clk_disable_unprepare(fep->clk_ipg); 2050 2051 return 0; 2052 } 2053 2054 static int 2055 fec_resume(struct device *dev) 2056 { 2057 struct net_device *ndev = dev_get_drvdata(dev); 2058 struct fec_enet_private *fep = netdev_priv(ndev); 2059 2060 clk_prepare_enable(fep->clk_enet_out); 2061 clk_prepare_enable(fep->clk_ahb); 2062 clk_prepare_enable(fep->clk_ipg); 2063 if (netif_running(ndev)) { 2064 fec_restart(ndev, fep->full_duplex); 2065 netif_device_attach(ndev); 2066 } 2067 2068 return 0; 2069 } 2070 #endif /* CONFIG_PM_SLEEP */ 2071 2072 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume); 2073 2074 static struct platform_driver fec_driver = { 2075 .driver = { 2076 .name = DRIVER_NAME, 2077 .owner = THIS_MODULE, 2078 .pm = &fec_pm_ops, 2079 .of_match_table = fec_dt_ids, 2080 }, 2081 .id_table = fec_devtype, 2082 .probe = fec_probe, 2083 .remove = fec_drv_remove, 2084 }; 2085 2086 module_platform_driver(fec_driver); 2087 2088 MODULE_LICENSE("GPL"); 2089