1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
4  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5  *
6  * Right now, I am very wasteful with the buffers.  I allocate memory
7  * pages and then divide them into 2K frame buffers.  This way I know I
8  * have buffers large enough to hold one frame within one buffer descriptor.
9  * Once I get this working, I will use 64 or 128 byte CPM buffers, which
10  * will be much more memory efficient and will easily handle lots of
11  * small packets.
12  *
13  * Much better multiple PHY support by Magnus Damm.
14  * Copyright (c) 2000 Ericsson Radio Systems AB.
15  *
16  * Support for FEC controller of ColdFire processors.
17  * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18  *
19  * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
20  * Copyright (c) 2004-2006 Macq Electronique SA.
21  *
22  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
23  */
24 
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/string.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/ptrace.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/slab.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/in.h>
39 #include <linux/ip.h>
40 #include <net/ip.h>
41 #include <net/selftests.h>
42 #include <net/tso.h>
43 #include <linux/tcp.h>
44 #include <linux/udp.h>
45 #include <linux/icmp.h>
46 #include <linux/spinlock.h>
47 #include <linux/workqueue.h>
48 #include <linux/bitops.h>
49 #include <linux/io.h>
50 #include <linux/irq.h>
51 #include <linux/clk.h>
52 #include <linux/crc32.h>
53 #include <linux/platform_device.h>
54 #include <linux/mdio.h>
55 #include <linux/phy.h>
56 #include <linux/fec.h>
57 #include <linux/of.h>
58 #include <linux/of_device.h>
59 #include <linux/of_gpio.h>
60 #include <linux/of_mdio.h>
61 #include <linux/of_net.h>
62 #include <linux/regulator/consumer.h>
63 #include <linux/if_vlan.h>
64 #include <linux/pinctrl/consumer.h>
65 #include <linux/prefetch.h>
66 #include <linux/mfd/syscon.h>
67 #include <linux/regmap.h>
68 #include <soc/imx/cpuidle.h>
69 #include <linux/filter.h>
70 #include <linux/bpf.h>
71 
72 #include <asm/cacheflush.h>
73 
74 #include "fec.h"
75 
76 static void set_multicast_list(struct net_device *ndev);
77 static void fec_enet_itr_coal_init(struct net_device *ndev);
78 
79 #define DRIVER_NAME	"fec"
80 
81 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2};
82 
83 /* Pause frame feild and FIFO threshold */
84 #define FEC_ENET_FCE	(1 << 5)
85 #define FEC_ENET_RSEM_V	0x84
86 #define FEC_ENET_RSFL_V	16
87 #define FEC_ENET_RAEM_V	0x8
88 #define FEC_ENET_RAFL_V	0x8
89 #define FEC_ENET_OPD_V	0xFFF0
90 #define FEC_MDIO_PM_TIMEOUT  100 /* ms */
91 
92 struct fec_devinfo {
93 	u32 quirks;
94 };
95 
96 static const struct fec_devinfo fec_imx25_info = {
97 	.quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR |
98 		  FEC_QUIRK_HAS_FRREG,
99 };
100 
101 static const struct fec_devinfo fec_imx27_info = {
102 	.quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG,
103 };
104 
105 static const struct fec_devinfo fec_imx28_info = {
106 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
107 		  FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
108 		  FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII |
109 		  FEC_QUIRK_NO_HARD_RESET,
110 };
111 
112 static const struct fec_devinfo fec_imx6q_info = {
113 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
114 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
115 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
116 		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII |
117 		  FEC_QUIRK_HAS_PMQOS,
118 };
119 
120 static const struct fec_devinfo fec_mvf600_info = {
121 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
122 };
123 
124 static const struct fec_devinfo fec_imx6x_info = {
125 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
126 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
127 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
128 		  FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
129 		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
130 		  FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES,
131 };
132 
133 static const struct fec_devinfo fec_imx6ul_info = {
134 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
135 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
136 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
137 		  FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
138 		  FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII,
139 };
140 
141 static const struct fec_devinfo fec_imx8mq_info = {
142 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
143 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
144 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
145 		  FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
146 		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
147 		  FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
148 		  FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2,
149 };
150 
151 static const struct fec_devinfo fec_imx8qm_info = {
152 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
153 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
154 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
155 		  FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
156 		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
157 		  FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
158 		  FEC_QUIRK_DELAYED_CLKS_SUPPORT,
159 };
160 
161 static const struct fec_devinfo fec_s32v234_info = {
162 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
163 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
164 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
165 		  FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE,
166 };
167 
168 static struct platform_device_id fec_devtype[] = {
169 	{
170 		/* keep it for coldfire */
171 		.name = DRIVER_NAME,
172 		.driver_data = 0,
173 	}, {
174 		.name = "imx25-fec",
175 		.driver_data = (kernel_ulong_t)&fec_imx25_info,
176 	}, {
177 		.name = "imx27-fec",
178 		.driver_data = (kernel_ulong_t)&fec_imx27_info,
179 	}, {
180 		.name = "imx28-fec",
181 		.driver_data = (kernel_ulong_t)&fec_imx28_info,
182 	}, {
183 		.name = "imx6q-fec",
184 		.driver_data = (kernel_ulong_t)&fec_imx6q_info,
185 	}, {
186 		.name = "mvf600-fec",
187 		.driver_data = (kernel_ulong_t)&fec_mvf600_info,
188 	}, {
189 		.name = "imx6sx-fec",
190 		.driver_data = (kernel_ulong_t)&fec_imx6x_info,
191 	}, {
192 		.name = "imx6ul-fec",
193 		.driver_data = (kernel_ulong_t)&fec_imx6ul_info,
194 	}, {
195 		.name = "imx8mq-fec",
196 		.driver_data = (kernel_ulong_t)&fec_imx8mq_info,
197 	}, {
198 		.name = "imx8qm-fec",
199 		.driver_data = (kernel_ulong_t)&fec_imx8qm_info,
200 	}, {
201 		.name = "s32v234-fec",
202 		.driver_data = (kernel_ulong_t)&fec_s32v234_info,
203 	}, {
204 		/* sentinel */
205 	}
206 };
207 MODULE_DEVICE_TABLE(platform, fec_devtype);
208 
209 enum imx_fec_type {
210 	IMX25_FEC = 1,	/* runs on i.mx25/50/53 */
211 	IMX27_FEC,	/* runs on i.mx27/35/51 */
212 	IMX28_FEC,
213 	IMX6Q_FEC,
214 	MVF600_FEC,
215 	IMX6SX_FEC,
216 	IMX6UL_FEC,
217 	IMX8MQ_FEC,
218 	IMX8QM_FEC,
219 	S32V234_FEC,
220 };
221 
222 static const struct of_device_id fec_dt_ids[] = {
223 	{ .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
224 	{ .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
225 	{ .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
226 	{ .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
227 	{ .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
228 	{ .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
229 	{ .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
230 	{ .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], },
231 	{ .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], },
232 	{ .compatible = "fsl,s32v234-fec", .data = &fec_devtype[S32V234_FEC], },
233 	{ /* sentinel */ }
234 };
235 MODULE_DEVICE_TABLE(of, fec_dt_ids);
236 
237 static unsigned char macaddr[ETH_ALEN];
238 module_param_array(macaddr, byte, NULL, 0);
239 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
240 
241 #if defined(CONFIG_M5272)
242 /*
243  * Some hardware gets it MAC address out of local flash memory.
244  * if this is non-zero then assume it is the address to get MAC from.
245  */
246 #if defined(CONFIG_NETtel)
247 #define	FEC_FLASHMAC	0xf0006006
248 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
249 #define	FEC_FLASHMAC	0xf0006000
250 #elif defined(CONFIG_CANCam)
251 #define	FEC_FLASHMAC	0xf0020000
252 #elif defined (CONFIG_M5272C3)
253 #define	FEC_FLASHMAC	(0xffe04000 + 4)
254 #elif defined(CONFIG_MOD5272)
255 #define FEC_FLASHMAC	0xffc0406b
256 #else
257 #define	FEC_FLASHMAC	0
258 #endif
259 #endif /* CONFIG_M5272 */
260 
261 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
262  *
263  * 2048 byte skbufs are allocated. However, alignment requirements
264  * varies between FEC variants. Worst case is 64, so round down by 64.
265  */
266 #define PKT_MAXBUF_SIZE		(round_down(2048 - 64, 64))
267 #define PKT_MINBUF_SIZE		64
268 
269 /* FEC receive acceleration */
270 #define FEC_RACC_IPDIS		(1 << 1)
271 #define FEC_RACC_PRODIS		(1 << 2)
272 #define FEC_RACC_SHIFT16	BIT(7)
273 #define FEC_RACC_OPTIONS	(FEC_RACC_IPDIS | FEC_RACC_PRODIS)
274 
275 /* MIB Control Register */
276 #define FEC_MIB_CTRLSTAT_DISABLE	BIT(31)
277 
278 /*
279  * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
280  * size bits. Other FEC hardware does not, so we need to take that into
281  * account when setting it.
282  */
283 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
284     defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
285     defined(CONFIG_ARM64)
286 #define	OPT_FRAME_SIZE	(PKT_MAXBUF_SIZE << 16)
287 #else
288 #define	OPT_FRAME_SIZE	0
289 #endif
290 
291 /* FEC MII MMFR bits definition */
292 #define FEC_MMFR_ST		(1 << 30)
293 #define FEC_MMFR_ST_C45		(0)
294 #define FEC_MMFR_OP_READ	(2 << 28)
295 #define FEC_MMFR_OP_READ_C45	(3 << 28)
296 #define FEC_MMFR_OP_WRITE	(1 << 28)
297 #define FEC_MMFR_OP_ADDR_WRITE	(0)
298 #define FEC_MMFR_PA(v)		((v & 0x1f) << 23)
299 #define FEC_MMFR_RA(v)		((v & 0x1f) << 18)
300 #define FEC_MMFR_TA		(2 << 16)
301 #define FEC_MMFR_DATA(v)	(v & 0xffff)
302 /* FEC ECR bits definition */
303 #define FEC_ECR_MAGICEN		(1 << 2)
304 #define FEC_ECR_SLEEP		(1 << 3)
305 
306 #define FEC_MII_TIMEOUT		30000 /* us */
307 
308 /* Transmitter timeout */
309 #define TX_TIMEOUT (2 * HZ)
310 
311 #define FEC_PAUSE_FLAG_AUTONEG	0x1
312 #define FEC_PAUSE_FLAG_ENABLE	0x2
313 #define FEC_WOL_HAS_MAGIC_PACKET	(0x1 << 0)
314 #define FEC_WOL_FLAG_ENABLE		(0x1 << 1)
315 #define FEC_WOL_FLAG_SLEEP_ON		(0x1 << 2)
316 
317 #define COPYBREAK_DEFAULT	256
318 
319 /* Max number of allowed TCP segments for software TSO */
320 #define FEC_MAX_TSO_SEGS	100
321 #define FEC_MAX_SKB_DESCS	(FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
322 
323 #define IS_TSO_HEADER(txq, addr) \
324 	((addr >= txq->tso_hdrs_dma) && \
325 	(addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
326 
327 static int mii_cnt;
328 
329 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
330 					     struct bufdesc_prop *bd)
331 {
332 	return (bdp >= bd->last) ? bd->base
333 			: (struct bufdesc *)(((void *)bdp) + bd->dsize);
334 }
335 
336 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
337 					     struct bufdesc_prop *bd)
338 {
339 	return (bdp <= bd->base) ? bd->last
340 			: (struct bufdesc *)(((void *)bdp) - bd->dsize);
341 }
342 
343 static int fec_enet_get_bd_index(struct bufdesc *bdp,
344 				 struct bufdesc_prop *bd)
345 {
346 	return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
347 }
348 
349 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
350 {
351 	int entries;
352 
353 	entries = (((const char *)txq->dirty_tx -
354 			(const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
355 
356 	return entries >= 0 ? entries : entries + txq->bd.ring_size;
357 }
358 
359 static void swap_buffer(void *bufaddr, int len)
360 {
361 	int i;
362 	unsigned int *buf = bufaddr;
363 
364 	for (i = 0; i < len; i += 4, buf++)
365 		swab32s(buf);
366 }
367 
368 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
369 {
370 	int i;
371 	unsigned int *src = src_buf;
372 	unsigned int *dst = dst_buf;
373 
374 	for (i = 0; i < len; i += 4, src++, dst++)
375 		*dst = swab32p(src);
376 }
377 
378 static void fec_dump(struct net_device *ndev)
379 {
380 	struct fec_enet_private *fep = netdev_priv(ndev);
381 	struct bufdesc *bdp;
382 	struct fec_enet_priv_tx_q *txq;
383 	int index = 0;
384 
385 	netdev_info(ndev, "TX ring dump\n");
386 	pr_info("Nr     SC     addr       len  SKB\n");
387 
388 	txq = fep->tx_queue[0];
389 	bdp = txq->bd.base;
390 
391 	do {
392 		pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
393 			index,
394 			bdp == txq->bd.cur ? 'S' : ' ',
395 			bdp == txq->dirty_tx ? 'H' : ' ',
396 			fec16_to_cpu(bdp->cbd_sc),
397 			fec32_to_cpu(bdp->cbd_bufaddr),
398 			fec16_to_cpu(bdp->cbd_datlen),
399 			txq->tx_skbuff[index]);
400 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
401 		index++;
402 	} while (bdp != txq->bd.base);
403 }
404 
405 static inline bool is_ipv4_pkt(struct sk_buff *skb)
406 {
407 	return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
408 }
409 
410 static int
411 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
412 {
413 	/* Only run for packets requiring a checksum. */
414 	if (skb->ip_summed != CHECKSUM_PARTIAL)
415 		return 0;
416 
417 	if (unlikely(skb_cow_head(skb, 0)))
418 		return -1;
419 
420 	if (is_ipv4_pkt(skb))
421 		ip_hdr(skb)->check = 0;
422 	*(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
423 
424 	return 0;
425 }
426 
427 static int
428 fec_enet_create_page_pool(struct fec_enet_private *fep,
429 			  struct fec_enet_priv_rx_q *rxq, int size)
430 {
431 	struct page_pool_params pp_params = {
432 		.order = 0,
433 		.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
434 		.pool_size = size,
435 		.nid = dev_to_node(&fep->pdev->dev),
436 		.dev = &fep->pdev->dev,
437 		.dma_dir = DMA_FROM_DEVICE,
438 		.offset = FEC_ENET_XDP_HEADROOM,
439 		.max_len = FEC_ENET_RX_FRSIZE,
440 	};
441 	int err;
442 
443 	rxq->page_pool = page_pool_create(&pp_params);
444 	if (IS_ERR(rxq->page_pool)) {
445 		err = PTR_ERR(rxq->page_pool);
446 		rxq->page_pool = NULL;
447 		return err;
448 	}
449 
450 	err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0);
451 	if (err < 0)
452 		goto err_free_pp;
453 
454 	err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL,
455 					 rxq->page_pool);
456 	if (err)
457 		goto err_unregister_rxq;
458 
459 	return 0;
460 
461 err_unregister_rxq:
462 	xdp_rxq_info_unreg(&rxq->xdp_rxq);
463 err_free_pp:
464 	page_pool_destroy(rxq->page_pool);
465 	rxq->page_pool = NULL;
466 	return err;
467 }
468 
469 static struct bufdesc *
470 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
471 			     struct sk_buff *skb,
472 			     struct net_device *ndev)
473 {
474 	struct fec_enet_private *fep = netdev_priv(ndev);
475 	struct bufdesc *bdp = txq->bd.cur;
476 	struct bufdesc_ex *ebdp;
477 	int nr_frags = skb_shinfo(skb)->nr_frags;
478 	int frag, frag_len;
479 	unsigned short status;
480 	unsigned int estatus = 0;
481 	skb_frag_t *this_frag;
482 	unsigned int index;
483 	void *bufaddr;
484 	dma_addr_t addr;
485 	int i;
486 
487 	for (frag = 0; frag < nr_frags; frag++) {
488 		this_frag = &skb_shinfo(skb)->frags[frag];
489 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
490 		ebdp = (struct bufdesc_ex *)bdp;
491 
492 		status = fec16_to_cpu(bdp->cbd_sc);
493 		status &= ~BD_ENET_TX_STATS;
494 		status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
495 		frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]);
496 
497 		/* Handle the last BD specially */
498 		if (frag == nr_frags - 1) {
499 			status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
500 			if (fep->bufdesc_ex) {
501 				estatus |= BD_ENET_TX_INT;
502 				if (unlikely(skb_shinfo(skb)->tx_flags &
503 					SKBTX_HW_TSTAMP && fep->hwts_tx_en))
504 					estatus |= BD_ENET_TX_TS;
505 			}
506 		}
507 
508 		if (fep->bufdesc_ex) {
509 			if (fep->quirks & FEC_QUIRK_HAS_AVB)
510 				estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
511 			if (skb->ip_summed == CHECKSUM_PARTIAL)
512 				estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
513 
514 			ebdp->cbd_bdu = 0;
515 			ebdp->cbd_esc = cpu_to_fec32(estatus);
516 		}
517 
518 		bufaddr = skb_frag_address(this_frag);
519 
520 		index = fec_enet_get_bd_index(bdp, &txq->bd);
521 		if (((unsigned long) bufaddr) & fep->tx_align ||
522 			fep->quirks & FEC_QUIRK_SWAP_FRAME) {
523 			memcpy(txq->tx_bounce[index], bufaddr, frag_len);
524 			bufaddr = txq->tx_bounce[index];
525 
526 			if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
527 				swap_buffer(bufaddr, frag_len);
528 		}
529 
530 		addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
531 				      DMA_TO_DEVICE);
532 		if (dma_mapping_error(&fep->pdev->dev, addr)) {
533 			if (net_ratelimit())
534 				netdev_err(ndev, "Tx DMA memory map failed\n");
535 			goto dma_mapping_error;
536 		}
537 
538 		bdp->cbd_bufaddr = cpu_to_fec32(addr);
539 		bdp->cbd_datlen = cpu_to_fec16(frag_len);
540 		/* Make sure the updates to rest of the descriptor are
541 		 * performed before transferring ownership.
542 		 */
543 		wmb();
544 		bdp->cbd_sc = cpu_to_fec16(status);
545 	}
546 
547 	return bdp;
548 dma_mapping_error:
549 	bdp = txq->bd.cur;
550 	for (i = 0; i < frag; i++) {
551 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
552 		dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
553 				 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
554 	}
555 	return ERR_PTR(-ENOMEM);
556 }
557 
558 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
559 				   struct sk_buff *skb, struct net_device *ndev)
560 {
561 	struct fec_enet_private *fep = netdev_priv(ndev);
562 	int nr_frags = skb_shinfo(skb)->nr_frags;
563 	struct bufdesc *bdp, *last_bdp;
564 	void *bufaddr;
565 	dma_addr_t addr;
566 	unsigned short status;
567 	unsigned short buflen;
568 	unsigned int estatus = 0;
569 	unsigned int index;
570 	int entries_free;
571 
572 	entries_free = fec_enet_get_free_txdesc_num(txq);
573 	if (entries_free < MAX_SKB_FRAGS + 1) {
574 		dev_kfree_skb_any(skb);
575 		if (net_ratelimit())
576 			netdev_err(ndev, "NOT enough BD for SG!\n");
577 		return NETDEV_TX_OK;
578 	}
579 
580 	/* Protocol checksum off-load for TCP and UDP. */
581 	if (fec_enet_clear_csum(skb, ndev)) {
582 		dev_kfree_skb_any(skb);
583 		return NETDEV_TX_OK;
584 	}
585 
586 	/* Fill in a Tx ring entry */
587 	bdp = txq->bd.cur;
588 	last_bdp = bdp;
589 	status = fec16_to_cpu(bdp->cbd_sc);
590 	status &= ~BD_ENET_TX_STATS;
591 
592 	/* Set buffer length and buffer pointer */
593 	bufaddr = skb->data;
594 	buflen = skb_headlen(skb);
595 
596 	index = fec_enet_get_bd_index(bdp, &txq->bd);
597 	if (((unsigned long) bufaddr) & fep->tx_align ||
598 		fep->quirks & FEC_QUIRK_SWAP_FRAME) {
599 		memcpy(txq->tx_bounce[index], skb->data, buflen);
600 		bufaddr = txq->tx_bounce[index];
601 
602 		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
603 			swap_buffer(bufaddr, buflen);
604 	}
605 
606 	/* Push the data cache so the CPM does not get stale memory data. */
607 	addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
608 	if (dma_mapping_error(&fep->pdev->dev, addr)) {
609 		dev_kfree_skb_any(skb);
610 		if (net_ratelimit())
611 			netdev_err(ndev, "Tx DMA memory map failed\n");
612 		return NETDEV_TX_OK;
613 	}
614 
615 	if (nr_frags) {
616 		last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
617 		if (IS_ERR(last_bdp)) {
618 			dma_unmap_single(&fep->pdev->dev, addr,
619 					 buflen, DMA_TO_DEVICE);
620 			dev_kfree_skb_any(skb);
621 			return NETDEV_TX_OK;
622 		}
623 	} else {
624 		status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
625 		if (fep->bufdesc_ex) {
626 			estatus = BD_ENET_TX_INT;
627 			if (unlikely(skb_shinfo(skb)->tx_flags &
628 				SKBTX_HW_TSTAMP && fep->hwts_tx_en))
629 				estatus |= BD_ENET_TX_TS;
630 		}
631 	}
632 	bdp->cbd_bufaddr = cpu_to_fec32(addr);
633 	bdp->cbd_datlen = cpu_to_fec16(buflen);
634 
635 	if (fep->bufdesc_ex) {
636 
637 		struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
638 
639 		if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
640 			fep->hwts_tx_en))
641 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
642 
643 		if (fep->quirks & FEC_QUIRK_HAS_AVB)
644 			estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
645 
646 		if (skb->ip_summed == CHECKSUM_PARTIAL)
647 			estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
648 
649 		ebdp->cbd_bdu = 0;
650 		ebdp->cbd_esc = cpu_to_fec32(estatus);
651 	}
652 
653 	index = fec_enet_get_bd_index(last_bdp, &txq->bd);
654 	/* Save skb pointer */
655 	txq->tx_skbuff[index] = skb;
656 
657 	/* Make sure the updates to rest of the descriptor are performed before
658 	 * transferring ownership.
659 	 */
660 	wmb();
661 
662 	/* Send it on its way.  Tell FEC it's ready, interrupt when done,
663 	 * it's the last BD of the frame, and to put the CRC on the end.
664 	 */
665 	status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
666 	bdp->cbd_sc = cpu_to_fec16(status);
667 
668 	/* If this was the last BD in the ring, start at the beginning again. */
669 	bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
670 
671 	skb_tx_timestamp(skb);
672 
673 	/* Make sure the update to bdp and tx_skbuff are performed before
674 	 * txq->bd.cur.
675 	 */
676 	wmb();
677 	txq->bd.cur = bdp;
678 
679 	/* Trigger transmission start */
680 	writel(0, txq->bd.reg_desc_active);
681 
682 	return 0;
683 }
684 
685 static int
686 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
687 			  struct net_device *ndev,
688 			  struct bufdesc *bdp, int index, char *data,
689 			  int size, bool last_tcp, bool is_last)
690 {
691 	struct fec_enet_private *fep = netdev_priv(ndev);
692 	struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
693 	unsigned short status;
694 	unsigned int estatus = 0;
695 	dma_addr_t addr;
696 
697 	status = fec16_to_cpu(bdp->cbd_sc);
698 	status &= ~BD_ENET_TX_STATS;
699 
700 	status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
701 
702 	if (((unsigned long) data) & fep->tx_align ||
703 		fep->quirks & FEC_QUIRK_SWAP_FRAME) {
704 		memcpy(txq->tx_bounce[index], data, size);
705 		data = txq->tx_bounce[index];
706 
707 		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
708 			swap_buffer(data, size);
709 	}
710 
711 	addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
712 	if (dma_mapping_error(&fep->pdev->dev, addr)) {
713 		dev_kfree_skb_any(skb);
714 		if (net_ratelimit())
715 			netdev_err(ndev, "Tx DMA memory map failed\n");
716 		return NETDEV_TX_OK;
717 	}
718 
719 	bdp->cbd_datlen = cpu_to_fec16(size);
720 	bdp->cbd_bufaddr = cpu_to_fec32(addr);
721 
722 	if (fep->bufdesc_ex) {
723 		if (fep->quirks & FEC_QUIRK_HAS_AVB)
724 			estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
725 		if (skb->ip_summed == CHECKSUM_PARTIAL)
726 			estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
727 		ebdp->cbd_bdu = 0;
728 		ebdp->cbd_esc = cpu_to_fec32(estatus);
729 	}
730 
731 	/* Handle the last BD specially */
732 	if (last_tcp)
733 		status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
734 	if (is_last) {
735 		status |= BD_ENET_TX_INTR;
736 		if (fep->bufdesc_ex)
737 			ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
738 	}
739 
740 	bdp->cbd_sc = cpu_to_fec16(status);
741 
742 	return 0;
743 }
744 
745 static int
746 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
747 			 struct sk_buff *skb, struct net_device *ndev,
748 			 struct bufdesc *bdp, int index)
749 {
750 	struct fec_enet_private *fep = netdev_priv(ndev);
751 	int hdr_len = skb_tcp_all_headers(skb);
752 	struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
753 	void *bufaddr;
754 	unsigned long dmabuf;
755 	unsigned short status;
756 	unsigned int estatus = 0;
757 
758 	status = fec16_to_cpu(bdp->cbd_sc);
759 	status &= ~BD_ENET_TX_STATS;
760 	status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
761 
762 	bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
763 	dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
764 	if (((unsigned long)bufaddr) & fep->tx_align ||
765 		fep->quirks & FEC_QUIRK_SWAP_FRAME) {
766 		memcpy(txq->tx_bounce[index], skb->data, hdr_len);
767 		bufaddr = txq->tx_bounce[index];
768 
769 		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
770 			swap_buffer(bufaddr, hdr_len);
771 
772 		dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
773 					hdr_len, DMA_TO_DEVICE);
774 		if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
775 			dev_kfree_skb_any(skb);
776 			if (net_ratelimit())
777 				netdev_err(ndev, "Tx DMA memory map failed\n");
778 			return NETDEV_TX_OK;
779 		}
780 	}
781 
782 	bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
783 	bdp->cbd_datlen = cpu_to_fec16(hdr_len);
784 
785 	if (fep->bufdesc_ex) {
786 		if (fep->quirks & FEC_QUIRK_HAS_AVB)
787 			estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
788 		if (skb->ip_summed == CHECKSUM_PARTIAL)
789 			estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
790 		ebdp->cbd_bdu = 0;
791 		ebdp->cbd_esc = cpu_to_fec32(estatus);
792 	}
793 
794 	bdp->cbd_sc = cpu_to_fec16(status);
795 
796 	return 0;
797 }
798 
799 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
800 				   struct sk_buff *skb,
801 				   struct net_device *ndev)
802 {
803 	struct fec_enet_private *fep = netdev_priv(ndev);
804 	int hdr_len, total_len, data_left;
805 	struct bufdesc *bdp = txq->bd.cur;
806 	struct tso_t tso;
807 	unsigned int index = 0;
808 	int ret;
809 
810 	if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
811 		dev_kfree_skb_any(skb);
812 		if (net_ratelimit())
813 			netdev_err(ndev, "NOT enough BD for TSO!\n");
814 		return NETDEV_TX_OK;
815 	}
816 
817 	/* Protocol checksum off-load for TCP and UDP. */
818 	if (fec_enet_clear_csum(skb, ndev)) {
819 		dev_kfree_skb_any(skb);
820 		return NETDEV_TX_OK;
821 	}
822 
823 	/* Initialize the TSO handler, and prepare the first payload */
824 	hdr_len = tso_start(skb, &tso);
825 
826 	total_len = skb->len - hdr_len;
827 	while (total_len > 0) {
828 		char *hdr;
829 
830 		index = fec_enet_get_bd_index(bdp, &txq->bd);
831 		data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
832 		total_len -= data_left;
833 
834 		/* prepare packet headers: MAC + IP + TCP */
835 		hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
836 		tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
837 		ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
838 		if (ret)
839 			goto err_release;
840 
841 		while (data_left > 0) {
842 			int size;
843 
844 			size = min_t(int, tso.size, data_left);
845 			bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
846 			index = fec_enet_get_bd_index(bdp, &txq->bd);
847 			ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
848 							bdp, index,
849 							tso.data, size,
850 							size == data_left,
851 							total_len == 0);
852 			if (ret)
853 				goto err_release;
854 
855 			data_left -= size;
856 			tso_build_data(skb, &tso, size);
857 		}
858 
859 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
860 	}
861 
862 	/* Save skb pointer */
863 	txq->tx_skbuff[index] = skb;
864 
865 	skb_tx_timestamp(skb);
866 	txq->bd.cur = bdp;
867 
868 	/* Trigger transmission start */
869 	if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
870 	    !readl(txq->bd.reg_desc_active) ||
871 	    !readl(txq->bd.reg_desc_active) ||
872 	    !readl(txq->bd.reg_desc_active) ||
873 	    !readl(txq->bd.reg_desc_active))
874 		writel(0, txq->bd.reg_desc_active);
875 
876 	return 0;
877 
878 err_release:
879 	/* TODO: Release all used data descriptors for TSO */
880 	return ret;
881 }
882 
883 static netdev_tx_t
884 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
885 {
886 	struct fec_enet_private *fep = netdev_priv(ndev);
887 	int entries_free;
888 	unsigned short queue;
889 	struct fec_enet_priv_tx_q *txq;
890 	struct netdev_queue *nq;
891 	int ret;
892 
893 	queue = skb_get_queue_mapping(skb);
894 	txq = fep->tx_queue[queue];
895 	nq = netdev_get_tx_queue(ndev, queue);
896 
897 	if (skb_is_gso(skb))
898 		ret = fec_enet_txq_submit_tso(txq, skb, ndev);
899 	else
900 		ret = fec_enet_txq_submit_skb(txq, skb, ndev);
901 	if (ret)
902 		return ret;
903 
904 	entries_free = fec_enet_get_free_txdesc_num(txq);
905 	if (entries_free <= txq->tx_stop_threshold)
906 		netif_tx_stop_queue(nq);
907 
908 	return NETDEV_TX_OK;
909 }
910 
911 /* Init RX & TX buffer descriptors
912  */
913 static void fec_enet_bd_init(struct net_device *dev)
914 {
915 	struct fec_enet_private *fep = netdev_priv(dev);
916 	struct fec_enet_priv_tx_q *txq;
917 	struct fec_enet_priv_rx_q *rxq;
918 	struct bufdesc *bdp;
919 	unsigned int i;
920 	unsigned int q;
921 
922 	for (q = 0; q < fep->num_rx_queues; q++) {
923 		/* Initialize the receive buffer descriptors. */
924 		rxq = fep->rx_queue[q];
925 		bdp = rxq->bd.base;
926 
927 		for (i = 0; i < rxq->bd.ring_size; i++) {
928 
929 			/* Initialize the BD for every fragment in the page. */
930 			if (bdp->cbd_bufaddr)
931 				bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
932 			else
933 				bdp->cbd_sc = cpu_to_fec16(0);
934 			bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
935 		}
936 
937 		/* Set the last buffer to wrap */
938 		bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
939 		bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
940 
941 		rxq->bd.cur = rxq->bd.base;
942 	}
943 
944 	for (q = 0; q < fep->num_tx_queues; q++) {
945 		/* ...and the same for transmit */
946 		txq = fep->tx_queue[q];
947 		bdp = txq->bd.base;
948 		txq->bd.cur = bdp;
949 
950 		for (i = 0; i < txq->bd.ring_size; i++) {
951 			/* Initialize the BD for every fragment in the page. */
952 			bdp->cbd_sc = cpu_to_fec16(0);
953 			if (bdp->cbd_bufaddr &&
954 			    !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
955 				dma_unmap_single(&fep->pdev->dev,
956 						 fec32_to_cpu(bdp->cbd_bufaddr),
957 						 fec16_to_cpu(bdp->cbd_datlen),
958 						 DMA_TO_DEVICE);
959 			if (txq->tx_skbuff[i]) {
960 				dev_kfree_skb_any(txq->tx_skbuff[i]);
961 				txq->tx_skbuff[i] = NULL;
962 			}
963 			bdp->cbd_bufaddr = cpu_to_fec32(0);
964 			bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
965 		}
966 
967 		/* Set the last buffer to wrap */
968 		bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
969 		bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
970 		txq->dirty_tx = bdp;
971 	}
972 }
973 
974 static void fec_enet_active_rxring(struct net_device *ndev)
975 {
976 	struct fec_enet_private *fep = netdev_priv(ndev);
977 	int i;
978 
979 	for (i = 0; i < fep->num_rx_queues; i++)
980 		writel(0, fep->rx_queue[i]->bd.reg_desc_active);
981 }
982 
983 static void fec_enet_enable_ring(struct net_device *ndev)
984 {
985 	struct fec_enet_private *fep = netdev_priv(ndev);
986 	struct fec_enet_priv_tx_q *txq;
987 	struct fec_enet_priv_rx_q *rxq;
988 	int i;
989 
990 	for (i = 0; i < fep->num_rx_queues; i++) {
991 		rxq = fep->rx_queue[i];
992 		writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
993 		writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
994 
995 		/* enable DMA1/2 */
996 		if (i)
997 			writel(RCMR_MATCHEN | RCMR_CMP(i),
998 			       fep->hwp + FEC_RCMR(i));
999 	}
1000 
1001 	for (i = 0; i < fep->num_tx_queues; i++) {
1002 		txq = fep->tx_queue[i];
1003 		writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
1004 
1005 		/* enable DMA1/2 */
1006 		if (i)
1007 			writel(DMA_CLASS_EN | IDLE_SLOPE(i),
1008 			       fep->hwp + FEC_DMA_CFG(i));
1009 	}
1010 }
1011 
1012 static void fec_enet_reset_skb(struct net_device *ndev)
1013 {
1014 	struct fec_enet_private *fep = netdev_priv(ndev);
1015 	struct fec_enet_priv_tx_q *txq;
1016 	int i, j;
1017 
1018 	for (i = 0; i < fep->num_tx_queues; i++) {
1019 		txq = fep->tx_queue[i];
1020 
1021 		for (j = 0; j < txq->bd.ring_size; j++) {
1022 			if (txq->tx_skbuff[j]) {
1023 				dev_kfree_skb_any(txq->tx_skbuff[j]);
1024 				txq->tx_skbuff[j] = NULL;
1025 			}
1026 		}
1027 	}
1028 }
1029 
1030 /*
1031  * This function is called to start or restart the FEC during a link
1032  * change, transmit timeout, or to reconfigure the FEC.  The network
1033  * packet processing for this device must be stopped before this call.
1034  */
1035 static void
1036 fec_restart(struct net_device *ndev)
1037 {
1038 	struct fec_enet_private *fep = netdev_priv(ndev);
1039 	u32 temp_mac[2];
1040 	u32 rcntl = OPT_FRAME_SIZE | 0x04;
1041 	u32 ecntl = 0x2; /* ETHEREN */
1042 
1043 	/* Whack a reset.  We should wait for this.
1044 	 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1045 	 * instead of reset MAC itself.
1046 	 */
1047 	if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES ||
1048 	    ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) {
1049 		writel(0, fep->hwp + FEC_ECNTRL);
1050 	} else {
1051 		writel(1, fep->hwp + FEC_ECNTRL);
1052 		udelay(10);
1053 	}
1054 
1055 	/*
1056 	 * enet-mac reset will reset mac address registers too,
1057 	 * so need to reconfigure it.
1058 	 */
1059 	memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
1060 	writel((__force u32)cpu_to_be32(temp_mac[0]),
1061 	       fep->hwp + FEC_ADDR_LOW);
1062 	writel((__force u32)cpu_to_be32(temp_mac[1]),
1063 	       fep->hwp + FEC_ADDR_HIGH);
1064 
1065 	/* Clear any outstanding interrupt, except MDIO. */
1066 	writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT);
1067 
1068 	fec_enet_bd_init(ndev);
1069 
1070 	fec_enet_enable_ring(ndev);
1071 
1072 	/* Reset tx SKB buffers. */
1073 	fec_enet_reset_skb(ndev);
1074 
1075 	/* Enable MII mode */
1076 	if (fep->full_duplex == DUPLEX_FULL) {
1077 		/* FD enable */
1078 		writel(0x04, fep->hwp + FEC_X_CNTRL);
1079 	} else {
1080 		/* No Rcv on Xmit */
1081 		rcntl |= 0x02;
1082 		writel(0x0, fep->hwp + FEC_X_CNTRL);
1083 	}
1084 
1085 	/* Set MII speed */
1086 	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1087 
1088 #if !defined(CONFIG_M5272)
1089 	if (fep->quirks & FEC_QUIRK_HAS_RACC) {
1090 		u32 val = readl(fep->hwp + FEC_RACC);
1091 
1092 		/* align IP header */
1093 		val |= FEC_RACC_SHIFT16;
1094 		if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
1095 			/* set RX checksum */
1096 			val |= FEC_RACC_OPTIONS;
1097 		else
1098 			val &= ~FEC_RACC_OPTIONS;
1099 		writel(val, fep->hwp + FEC_RACC);
1100 		writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
1101 	}
1102 #endif
1103 
1104 	/*
1105 	 * The phy interface and speed need to get configured
1106 	 * differently on enet-mac.
1107 	 */
1108 	if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1109 		/* Enable flow control and length check */
1110 		rcntl |= 0x40000000 | 0x00000020;
1111 
1112 		/* RGMII, RMII or MII */
1113 		if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
1114 		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1115 		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1116 		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1117 			rcntl |= (1 << 6);
1118 		else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1119 			rcntl |= (1 << 8);
1120 		else
1121 			rcntl &= ~(1 << 8);
1122 
1123 		/* 1G, 100M or 10M */
1124 		if (ndev->phydev) {
1125 			if (ndev->phydev->speed == SPEED_1000)
1126 				ecntl |= (1 << 5);
1127 			else if (ndev->phydev->speed == SPEED_100)
1128 				rcntl &= ~(1 << 9);
1129 			else
1130 				rcntl |= (1 << 9);
1131 		}
1132 	} else {
1133 #ifdef FEC_MIIGSK_ENR
1134 		if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1135 			u32 cfgr;
1136 			/* disable the gasket and wait */
1137 			writel(0, fep->hwp + FEC_MIIGSK_ENR);
1138 			while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1139 				udelay(1);
1140 
1141 			/*
1142 			 * configure the gasket:
1143 			 *   RMII, 50 MHz, no loopback, no echo
1144 			 *   MII, 25 MHz, no loopback, no echo
1145 			 */
1146 			cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1147 				? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1148 			if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1149 				cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1150 			writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1151 
1152 			/* re-enable the gasket */
1153 			writel(2, fep->hwp + FEC_MIIGSK_ENR);
1154 		}
1155 #endif
1156 	}
1157 
1158 #if !defined(CONFIG_M5272)
1159 	/* enable pause frame*/
1160 	if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1161 	    ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1162 	     ndev->phydev && ndev->phydev->pause)) {
1163 		rcntl |= FEC_ENET_FCE;
1164 
1165 		/* set FIFO threshold parameter to reduce overrun */
1166 		writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1167 		writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1168 		writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1169 		writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1170 
1171 		/* OPD */
1172 		writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1173 	} else {
1174 		rcntl &= ~FEC_ENET_FCE;
1175 	}
1176 #endif /* !defined(CONFIG_M5272) */
1177 
1178 	writel(rcntl, fep->hwp + FEC_R_CNTRL);
1179 
1180 	/* Setup multicast filter. */
1181 	set_multicast_list(ndev);
1182 #ifndef CONFIG_M5272
1183 	writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1184 	writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1185 #endif
1186 
1187 	if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1188 		/* enable ENET endian swap */
1189 		ecntl |= (1 << 8);
1190 		/* enable ENET store and forward mode */
1191 		writel(1 << 8, fep->hwp + FEC_X_WMRK);
1192 	}
1193 
1194 	if (fep->bufdesc_ex)
1195 		ecntl |= (1 << 4);
1196 
1197 	if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT &&
1198 	    fep->rgmii_txc_dly)
1199 		ecntl |= FEC_ENET_TXC_DLY;
1200 	if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT &&
1201 	    fep->rgmii_rxc_dly)
1202 		ecntl |= FEC_ENET_RXC_DLY;
1203 
1204 #ifndef CONFIG_M5272
1205 	/* Enable the MIB statistic event counters */
1206 	writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1207 #endif
1208 
1209 	/* And last, enable the transmit and receive processing */
1210 	writel(ecntl, fep->hwp + FEC_ECNTRL);
1211 	fec_enet_active_rxring(ndev);
1212 
1213 	if (fep->bufdesc_ex)
1214 		fec_ptp_start_cyclecounter(ndev);
1215 
1216 	/* Enable interrupts we wish to service */
1217 	if (fep->link)
1218 		writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1219 	else
1220 		writel(0, fep->hwp + FEC_IMASK);
1221 
1222 	/* Init the interrupt coalescing */
1223 	fec_enet_itr_coal_init(ndev);
1224 
1225 }
1226 
1227 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep)
1228 {
1229 	if (!(of_machine_is_compatible("fsl,imx8qm") ||
1230 	      of_machine_is_compatible("fsl,imx8qxp") ||
1231 	      of_machine_is_compatible("fsl,imx8dxl")))
1232 		return 0;
1233 
1234 	return imx_scu_get_handle(&fep->ipc_handle);
1235 }
1236 
1237 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled)
1238 {
1239 	struct device_node *np = fep->pdev->dev.of_node;
1240 	u32 rsrc_id, val;
1241 	int idx;
1242 
1243 	if (!np || !fep->ipc_handle)
1244 		return;
1245 
1246 	idx = of_alias_get_id(np, "ethernet");
1247 	if (idx < 0)
1248 		idx = 0;
1249 	rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0;
1250 
1251 	val = enabled ? 1 : 0;
1252 	imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val);
1253 }
1254 
1255 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled)
1256 {
1257 	struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1258 	struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr;
1259 
1260 	if (stop_gpr->gpr) {
1261 		if (enabled)
1262 			regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1263 					   BIT(stop_gpr->bit),
1264 					   BIT(stop_gpr->bit));
1265 		else
1266 			regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1267 					   BIT(stop_gpr->bit), 0);
1268 	} else if (pdata && pdata->sleep_mode_enable) {
1269 		pdata->sleep_mode_enable(enabled);
1270 	} else {
1271 		fec_enet_ipg_stop_set(fep, enabled);
1272 	}
1273 }
1274 
1275 static void fec_irqs_disable(struct net_device *ndev)
1276 {
1277 	struct fec_enet_private *fep = netdev_priv(ndev);
1278 
1279 	writel(0, fep->hwp + FEC_IMASK);
1280 }
1281 
1282 static void fec_irqs_disable_except_wakeup(struct net_device *ndev)
1283 {
1284 	struct fec_enet_private *fep = netdev_priv(ndev);
1285 
1286 	writel(0, fep->hwp + FEC_IMASK);
1287 	writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1288 }
1289 
1290 static void
1291 fec_stop(struct net_device *ndev)
1292 {
1293 	struct fec_enet_private *fep = netdev_priv(ndev);
1294 	u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1295 	u32 val;
1296 
1297 	/* We cannot expect a graceful transmit stop without link !!! */
1298 	if (fep->link) {
1299 		writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1300 		udelay(10);
1301 		if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1302 			netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1303 	}
1304 
1305 	/* Whack a reset.  We should wait for this.
1306 	 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1307 	 * instead of reset MAC itself.
1308 	 */
1309 	if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1310 		if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
1311 			writel(0, fep->hwp + FEC_ECNTRL);
1312 		} else {
1313 			writel(1, fep->hwp + FEC_ECNTRL);
1314 			udelay(10);
1315 		}
1316 	} else {
1317 		val = readl(fep->hwp + FEC_ECNTRL);
1318 		val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1319 		writel(val, fep->hwp + FEC_ECNTRL);
1320 	}
1321 	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1322 	writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1323 
1324 	/* We have to keep ENET enabled to have MII interrupt stay working */
1325 	if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1326 		!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1327 		writel(2, fep->hwp + FEC_ECNTRL);
1328 		writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1329 	}
1330 }
1331 
1332 
1333 static void
1334 fec_timeout(struct net_device *ndev, unsigned int txqueue)
1335 {
1336 	struct fec_enet_private *fep = netdev_priv(ndev);
1337 
1338 	fec_dump(ndev);
1339 
1340 	ndev->stats.tx_errors++;
1341 
1342 	schedule_work(&fep->tx_timeout_work);
1343 }
1344 
1345 static void fec_enet_timeout_work(struct work_struct *work)
1346 {
1347 	struct fec_enet_private *fep =
1348 		container_of(work, struct fec_enet_private, tx_timeout_work);
1349 	struct net_device *ndev = fep->netdev;
1350 
1351 	rtnl_lock();
1352 	if (netif_device_present(ndev) || netif_running(ndev)) {
1353 		napi_disable(&fep->napi);
1354 		netif_tx_lock_bh(ndev);
1355 		fec_restart(ndev);
1356 		netif_tx_wake_all_queues(ndev);
1357 		netif_tx_unlock_bh(ndev);
1358 		napi_enable(&fep->napi);
1359 	}
1360 	rtnl_unlock();
1361 }
1362 
1363 static void
1364 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1365 	struct skb_shared_hwtstamps *hwtstamps)
1366 {
1367 	unsigned long flags;
1368 	u64 ns;
1369 
1370 	spin_lock_irqsave(&fep->tmreg_lock, flags);
1371 	ns = timecounter_cyc2time(&fep->tc, ts);
1372 	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1373 
1374 	memset(hwtstamps, 0, sizeof(*hwtstamps));
1375 	hwtstamps->hwtstamp = ns_to_ktime(ns);
1376 }
1377 
1378 static void
1379 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1380 {
1381 	struct	fec_enet_private *fep;
1382 	struct bufdesc *bdp;
1383 	unsigned short status;
1384 	struct	sk_buff	*skb;
1385 	struct fec_enet_priv_tx_q *txq;
1386 	struct netdev_queue *nq;
1387 	int	index = 0;
1388 	int	entries_free;
1389 
1390 	fep = netdev_priv(ndev);
1391 
1392 	txq = fep->tx_queue[queue_id];
1393 	/* get next bdp of dirty_tx */
1394 	nq = netdev_get_tx_queue(ndev, queue_id);
1395 	bdp = txq->dirty_tx;
1396 
1397 	/* get next bdp of dirty_tx */
1398 	bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1399 
1400 	while (bdp != READ_ONCE(txq->bd.cur)) {
1401 		/* Order the load of bd.cur and cbd_sc */
1402 		rmb();
1403 		status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1404 		if (status & BD_ENET_TX_READY)
1405 			break;
1406 
1407 		index = fec_enet_get_bd_index(bdp, &txq->bd);
1408 
1409 		skb = txq->tx_skbuff[index];
1410 		txq->tx_skbuff[index] = NULL;
1411 		if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1412 			dma_unmap_single(&fep->pdev->dev,
1413 					 fec32_to_cpu(bdp->cbd_bufaddr),
1414 					 fec16_to_cpu(bdp->cbd_datlen),
1415 					 DMA_TO_DEVICE);
1416 		bdp->cbd_bufaddr = cpu_to_fec32(0);
1417 		if (!skb)
1418 			goto skb_done;
1419 
1420 		/* Check for errors. */
1421 		if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1422 				   BD_ENET_TX_RL | BD_ENET_TX_UN |
1423 				   BD_ENET_TX_CSL)) {
1424 			ndev->stats.tx_errors++;
1425 			if (status & BD_ENET_TX_HB)  /* No heartbeat */
1426 				ndev->stats.tx_heartbeat_errors++;
1427 			if (status & BD_ENET_TX_LC)  /* Late collision */
1428 				ndev->stats.tx_window_errors++;
1429 			if (status & BD_ENET_TX_RL)  /* Retrans limit */
1430 				ndev->stats.tx_aborted_errors++;
1431 			if (status & BD_ENET_TX_UN)  /* Underrun */
1432 				ndev->stats.tx_fifo_errors++;
1433 			if (status & BD_ENET_TX_CSL) /* Carrier lost */
1434 				ndev->stats.tx_carrier_errors++;
1435 		} else {
1436 			ndev->stats.tx_packets++;
1437 			ndev->stats.tx_bytes += skb->len;
1438 		}
1439 
1440 		/* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who
1441 		 * are to time stamp the packet, so we still need to check time
1442 		 * stamping enabled flag.
1443 		 */
1444 		if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS &&
1445 			     fep->hwts_tx_en) &&
1446 		    fep->bufdesc_ex) {
1447 			struct skb_shared_hwtstamps shhwtstamps;
1448 			struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1449 
1450 			fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1451 			skb_tstamp_tx(skb, &shhwtstamps);
1452 		}
1453 
1454 		/* Deferred means some collisions occurred during transmit,
1455 		 * but we eventually sent the packet OK.
1456 		 */
1457 		if (status & BD_ENET_TX_DEF)
1458 			ndev->stats.collisions++;
1459 
1460 		/* Free the sk buffer associated with this last transmit */
1461 		dev_kfree_skb_any(skb);
1462 skb_done:
1463 		/* Make sure the update to bdp and tx_skbuff are performed
1464 		 * before dirty_tx
1465 		 */
1466 		wmb();
1467 		txq->dirty_tx = bdp;
1468 
1469 		/* Update pointer to next buffer descriptor to be transmitted */
1470 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1471 
1472 		/* Since we have freed up a buffer, the ring is no longer full
1473 		 */
1474 		if (netif_tx_queue_stopped(nq)) {
1475 			entries_free = fec_enet_get_free_txdesc_num(txq);
1476 			if (entries_free >= txq->tx_wake_threshold)
1477 				netif_tx_wake_queue(nq);
1478 		}
1479 	}
1480 
1481 	/* ERR006358: Keep the transmitter going */
1482 	if (bdp != txq->bd.cur &&
1483 	    readl(txq->bd.reg_desc_active) == 0)
1484 		writel(0, txq->bd.reg_desc_active);
1485 }
1486 
1487 static void fec_enet_tx(struct net_device *ndev)
1488 {
1489 	struct fec_enet_private *fep = netdev_priv(ndev);
1490 	int i;
1491 
1492 	/* Make sure that AVB queues are processed first. */
1493 	for (i = fep->num_tx_queues - 1; i >= 0; i--)
1494 		fec_enet_tx_queue(ndev, i);
1495 }
1496 
1497 static int __maybe_unused
1498 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1499 {
1500 	struct  fec_enet_private *fep = netdev_priv(ndev);
1501 	int off;
1502 
1503 	off = ((unsigned long)skb->data) & fep->rx_align;
1504 	if (off)
1505 		skb_reserve(skb, fep->rx_align + 1 - off);
1506 
1507 	bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1508 	if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1509 		if (net_ratelimit())
1510 			netdev_err(ndev, "Rx DMA memory map failed\n");
1511 		return -ENOMEM;
1512 	}
1513 
1514 	return 0;
1515 }
1516 
1517 static bool __maybe_unused
1518 fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1519 		   struct bufdesc *bdp, u32 length, bool swap)
1520 {
1521 	struct  fec_enet_private *fep = netdev_priv(ndev);
1522 	struct sk_buff *new_skb;
1523 
1524 	if (length > fep->rx_copybreak)
1525 		return false;
1526 
1527 	new_skb = netdev_alloc_skb(ndev, length);
1528 	if (!new_skb)
1529 		return false;
1530 
1531 	dma_sync_single_for_cpu(&fep->pdev->dev,
1532 				fec32_to_cpu(bdp->cbd_bufaddr),
1533 				FEC_ENET_RX_FRSIZE - fep->rx_align,
1534 				DMA_FROM_DEVICE);
1535 	if (!swap)
1536 		memcpy(new_skb->data, (*skb)->data, length);
1537 	else
1538 		swap_buffer2(new_skb->data, (*skb)->data, length);
1539 	*skb = new_skb;
1540 
1541 	return true;
1542 }
1543 
1544 static void fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq,
1545 				struct bufdesc *bdp, int index)
1546 {
1547 	struct page *new_page;
1548 	dma_addr_t phys_addr;
1549 
1550 	new_page = page_pool_dev_alloc_pages(rxq->page_pool);
1551 	WARN_ON(!new_page);
1552 	rxq->rx_skb_info[index].page = new_page;
1553 
1554 	rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM;
1555 	phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM;
1556 	bdp->cbd_bufaddr = cpu_to_fec32(phys_addr);
1557 }
1558 
1559 /* During a receive, the bd_rx.cur points to the current incoming buffer.
1560  * When we update through the ring, if the next incoming buffer has
1561  * not been given to the system, we just set the empty indicator,
1562  * effectively tossing the packet.
1563  */
1564 static int
1565 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1566 {
1567 	struct fec_enet_private *fep = netdev_priv(ndev);
1568 	struct fec_enet_priv_rx_q *rxq;
1569 	struct bufdesc *bdp;
1570 	unsigned short status;
1571 	struct  sk_buff *skb;
1572 	ushort	pkt_len;
1573 	__u8 *data;
1574 	int	pkt_received = 0;
1575 	struct	bufdesc_ex *ebdp = NULL;
1576 	bool	vlan_packet_rcvd = false;
1577 	u16	vlan_tag;
1578 	int	index = 0;
1579 	bool	need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1580 	struct page *page;
1581 
1582 #ifdef CONFIG_M532x
1583 	flush_cache_all();
1584 #endif
1585 	rxq = fep->rx_queue[queue_id];
1586 
1587 	/* First, grab all of the stats for the incoming packet.
1588 	 * These get messed up if we get called due to a busy condition.
1589 	 */
1590 	bdp = rxq->bd.cur;
1591 
1592 	while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1593 
1594 		if (pkt_received >= budget)
1595 			break;
1596 		pkt_received++;
1597 
1598 		writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT);
1599 
1600 		/* Check for errors. */
1601 		status ^= BD_ENET_RX_LAST;
1602 		if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1603 			   BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1604 			   BD_ENET_RX_CL)) {
1605 			ndev->stats.rx_errors++;
1606 			if (status & BD_ENET_RX_OV) {
1607 				/* FIFO overrun */
1608 				ndev->stats.rx_fifo_errors++;
1609 				goto rx_processing_done;
1610 			}
1611 			if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1612 						| BD_ENET_RX_LAST)) {
1613 				/* Frame too long or too short. */
1614 				ndev->stats.rx_length_errors++;
1615 				if (status & BD_ENET_RX_LAST)
1616 					netdev_err(ndev, "rcv is not +last\n");
1617 			}
1618 			if (status & BD_ENET_RX_CR)	/* CRC Error */
1619 				ndev->stats.rx_crc_errors++;
1620 			/* Report late collisions as a frame error. */
1621 			if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1622 				ndev->stats.rx_frame_errors++;
1623 			goto rx_processing_done;
1624 		}
1625 
1626 		/* Process the incoming frame. */
1627 		ndev->stats.rx_packets++;
1628 		pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1629 		ndev->stats.rx_bytes += pkt_len;
1630 
1631 		index = fec_enet_get_bd_index(bdp, &rxq->bd);
1632 		page = rxq->rx_skb_info[index].page;
1633 		dma_sync_single_for_cpu(&fep->pdev->dev,
1634 					fec32_to_cpu(bdp->cbd_bufaddr),
1635 					pkt_len,
1636 					DMA_FROM_DEVICE);
1637 		prefetch(page_address(page));
1638 		fec_enet_update_cbd(rxq, bdp, index);
1639 
1640 		/* The packet length includes FCS, but we don't want to
1641 		 * include that when passing upstream as it messes up
1642 		 * bridging applications.
1643 		 */
1644 		skb = build_skb(page_address(page), PAGE_SIZE);
1645 		skb_reserve(skb, FEC_ENET_XDP_HEADROOM);
1646 		skb_put(skb, pkt_len - 4);
1647 		skb_mark_for_recycle(skb);
1648 		data = skb->data;
1649 
1650 		if (need_swap)
1651 			swap_buffer(data, pkt_len);
1652 
1653 #if !defined(CONFIG_M5272)
1654 		if (fep->quirks & FEC_QUIRK_HAS_RACC)
1655 			data = skb_pull_inline(skb, 2);
1656 #endif
1657 
1658 		/* Extract the enhanced buffer descriptor */
1659 		ebdp = NULL;
1660 		if (fep->bufdesc_ex)
1661 			ebdp = (struct bufdesc_ex *)bdp;
1662 
1663 		/* If this is a VLAN packet remove the VLAN Tag */
1664 		vlan_packet_rcvd = false;
1665 		if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1666 		    fep->bufdesc_ex &&
1667 		    (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1668 			/* Push and remove the vlan tag */
1669 			struct vlan_hdr *vlan_header =
1670 					(struct vlan_hdr *) (data + ETH_HLEN);
1671 			vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1672 
1673 			vlan_packet_rcvd = true;
1674 
1675 			memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1676 			skb_pull(skb, VLAN_HLEN);
1677 		}
1678 
1679 		skb->protocol = eth_type_trans(skb, ndev);
1680 
1681 		/* Get receive timestamp from the skb */
1682 		if (fep->hwts_rx_en && fep->bufdesc_ex)
1683 			fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1684 					  skb_hwtstamps(skb));
1685 
1686 		if (fep->bufdesc_ex &&
1687 		    (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1688 			if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1689 				/* don't check it */
1690 				skb->ip_summed = CHECKSUM_UNNECESSARY;
1691 			} else {
1692 				skb_checksum_none_assert(skb);
1693 			}
1694 		}
1695 
1696 		/* Handle received VLAN packets */
1697 		if (vlan_packet_rcvd)
1698 			__vlan_hwaccel_put_tag(skb,
1699 					       htons(ETH_P_8021Q),
1700 					       vlan_tag);
1701 
1702 		skb_record_rx_queue(skb, queue_id);
1703 		napi_gro_receive(&fep->napi, skb);
1704 
1705 rx_processing_done:
1706 		/* Clear the status flags for this buffer */
1707 		status &= ~BD_ENET_RX_STATS;
1708 
1709 		/* Mark the buffer empty */
1710 		status |= BD_ENET_RX_EMPTY;
1711 
1712 		if (fep->bufdesc_ex) {
1713 			struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1714 
1715 			ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1716 			ebdp->cbd_prot = 0;
1717 			ebdp->cbd_bdu = 0;
1718 		}
1719 		/* Make sure the updates to rest of the descriptor are
1720 		 * performed before transferring ownership.
1721 		 */
1722 		wmb();
1723 		bdp->cbd_sc = cpu_to_fec16(status);
1724 
1725 		/* Update BD pointer to next entry */
1726 		bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1727 
1728 		/* Doing this here will keep the FEC running while we process
1729 		 * incoming frames.  On a heavily loaded network, we should be
1730 		 * able to keep up at the expense of system resources.
1731 		 */
1732 		writel(0, rxq->bd.reg_desc_active);
1733 	}
1734 	rxq->bd.cur = bdp;
1735 	return pkt_received;
1736 }
1737 
1738 static int fec_enet_rx(struct net_device *ndev, int budget)
1739 {
1740 	struct fec_enet_private *fep = netdev_priv(ndev);
1741 	int i, done = 0;
1742 
1743 	/* Make sure that AVB queues are processed first. */
1744 	for (i = fep->num_rx_queues - 1; i >= 0; i--)
1745 		done += fec_enet_rx_queue(ndev, budget - done, i);
1746 
1747 	return done;
1748 }
1749 
1750 static bool fec_enet_collect_events(struct fec_enet_private *fep)
1751 {
1752 	uint int_events;
1753 
1754 	int_events = readl(fep->hwp + FEC_IEVENT);
1755 
1756 	/* Don't clear MDIO events, we poll for those */
1757 	int_events &= ~FEC_ENET_MII;
1758 
1759 	writel(int_events, fep->hwp + FEC_IEVENT);
1760 
1761 	return int_events != 0;
1762 }
1763 
1764 static irqreturn_t
1765 fec_enet_interrupt(int irq, void *dev_id)
1766 {
1767 	struct net_device *ndev = dev_id;
1768 	struct fec_enet_private *fep = netdev_priv(ndev);
1769 	irqreturn_t ret = IRQ_NONE;
1770 
1771 	if (fec_enet_collect_events(fep) && fep->link) {
1772 		ret = IRQ_HANDLED;
1773 
1774 		if (napi_schedule_prep(&fep->napi)) {
1775 			/* Disable interrupts */
1776 			writel(0, fep->hwp + FEC_IMASK);
1777 			__napi_schedule(&fep->napi);
1778 		}
1779 	}
1780 
1781 	return ret;
1782 }
1783 
1784 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1785 {
1786 	struct net_device *ndev = napi->dev;
1787 	struct fec_enet_private *fep = netdev_priv(ndev);
1788 	int done = 0;
1789 
1790 	do {
1791 		done += fec_enet_rx(ndev, budget - done);
1792 		fec_enet_tx(ndev);
1793 	} while ((done < budget) && fec_enet_collect_events(fep));
1794 
1795 	if (done < budget) {
1796 		napi_complete_done(napi, done);
1797 		writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1798 	}
1799 
1800 	return done;
1801 }
1802 
1803 /* ------------------------------------------------------------------------- */
1804 static int fec_get_mac(struct net_device *ndev)
1805 {
1806 	struct fec_enet_private *fep = netdev_priv(ndev);
1807 	unsigned char *iap, tmpaddr[ETH_ALEN];
1808 	int ret;
1809 
1810 	/*
1811 	 * try to get mac address in following order:
1812 	 *
1813 	 * 1) module parameter via kernel command line in form
1814 	 *    fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1815 	 */
1816 	iap = macaddr;
1817 
1818 	/*
1819 	 * 2) from device tree data
1820 	 */
1821 	if (!is_valid_ether_addr(iap)) {
1822 		struct device_node *np = fep->pdev->dev.of_node;
1823 		if (np) {
1824 			ret = of_get_mac_address(np, tmpaddr);
1825 			if (!ret)
1826 				iap = tmpaddr;
1827 			else if (ret == -EPROBE_DEFER)
1828 				return ret;
1829 		}
1830 	}
1831 
1832 	/*
1833 	 * 3) from flash or fuse (via platform data)
1834 	 */
1835 	if (!is_valid_ether_addr(iap)) {
1836 #ifdef CONFIG_M5272
1837 		if (FEC_FLASHMAC)
1838 			iap = (unsigned char *)FEC_FLASHMAC;
1839 #else
1840 		struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1841 
1842 		if (pdata)
1843 			iap = (unsigned char *)&pdata->mac;
1844 #endif
1845 	}
1846 
1847 	/*
1848 	 * 4) FEC mac registers set by bootloader
1849 	 */
1850 	if (!is_valid_ether_addr(iap)) {
1851 		*((__be32 *) &tmpaddr[0]) =
1852 			cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1853 		*((__be16 *) &tmpaddr[4]) =
1854 			cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1855 		iap = &tmpaddr[0];
1856 	}
1857 
1858 	/*
1859 	 * 5) random mac address
1860 	 */
1861 	if (!is_valid_ether_addr(iap)) {
1862 		/* Report it and use a random ethernet address instead */
1863 		dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap);
1864 		eth_hw_addr_random(ndev);
1865 		dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n",
1866 			 ndev->dev_addr);
1867 		return 0;
1868 	}
1869 
1870 	/* Adjust MAC if using macaddr */
1871 	eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0);
1872 
1873 	return 0;
1874 }
1875 
1876 /* ------------------------------------------------------------------------- */
1877 
1878 /*
1879  * Phy section
1880  */
1881 static void fec_enet_adjust_link(struct net_device *ndev)
1882 {
1883 	struct fec_enet_private *fep = netdev_priv(ndev);
1884 	struct phy_device *phy_dev = ndev->phydev;
1885 	int status_change = 0;
1886 
1887 	/*
1888 	 * If the netdev is down, or is going down, we're not interested
1889 	 * in link state events, so just mark our idea of the link as down
1890 	 * and ignore the event.
1891 	 */
1892 	if (!netif_running(ndev) || !netif_device_present(ndev)) {
1893 		fep->link = 0;
1894 	} else if (phy_dev->link) {
1895 		if (!fep->link) {
1896 			fep->link = phy_dev->link;
1897 			status_change = 1;
1898 		}
1899 
1900 		if (fep->full_duplex != phy_dev->duplex) {
1901 			fep->full_duplex = phy_dev->duplex;
1902 			status_change = 1;
1903 		}
1904 
1905 		if (phy_dev->speed != fep->speed) {
1906 			fep->speed = phy_dev->speed;
1907 			status_change = 1;
1908 		}
1909 
1910 		/* if any of the above changed restart the FEC */
1911 		if (status_change) {
1912 			napi_disable(&fep->napi);
1913 			netif_tx_lock_bh(ndev);
1914 			fec_restart(ndev);
1915 			netif_tx_wake_all_queues(ndev);
1916 			netif_tx_unlock_bh(ndev);
1917 			napi_enable(&fep->napi);
1918 		}
1919 	} else {
1920 		if (fep->link) {
1921 			napi_disable(&fep->napi);
1922 			netif_tx_lock_bh(ndev);
1923 			fec_stop(ndev);
1924 			netif_tx_unlock_bh(ndev);
1925 			napi_enable(&fep->napi);
1926 			fep->link = phy_dev->link;
1927 			status_change = 1;
1928 		}
1929 	}
1930 
1931 	if (status_change)
1932 		phy_print_status(phy_dev);
1933 }
1934 
1935 static int fec_enet_mdio_wait(struct fec_enet_private *fep)
1936 {
1937 	uint ievent;
1938 	int ret;
1939 
1940 	ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent,
1941 					ievent & FEC_ENET_MII, 2, 30000);
1942 
1943 	if (!ret)
1944 		writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
1945 
1946 	return ret;
1947 }
1948 
1949 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1950 {
1951 	struct fec_enet_private *fep = bus->priv;
1952 	struct device *dev = &fep->pdev->dev;
1953 	int ret = 0, frame_start, frame_addr, frame_op;
1954 	bool is_c45 = !!(regnum & MII_ADDR_C45);
1955 
1956 	ret = pm_runtime_resume_and_get(dev);
1957 	if (ret < 0)
1958 		return ret;
1959 
1960 	if (is_c45) {
1961 		frame_start = FEC_MMFR_ST_C45;
1962 
1963 		/* write address */
1964 		frame_addr = (regnum >> 16);
1965 		writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
1966 		       FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1967 		       FEC_MMFR_TA | (regnum & 0xFFFF),
1968 		       fep->hwp + FEC_MII_DATA);
1969 
1970 		/* wait for end of transfer */
1971 		ret = fec_enet_mdio_wait(fep);
1972 		if (ret) {
1973 			netdev_err(fep->netdev, "MDIO address write timeout\n");
1974 			goto out;
1975 		}
1976 
1977 		frame_op = FEC_MMFR_OP_READ_C45;
1978 
1979 	} else {
1980 		/* C22 read */
1981 		frame_op = FEC_MMFR_OP_READ;
1982 		frame_start = FEC_MMFR_ST;
1983 		frame_addr = regnum;
1984 	}
1985 
1986 	/* start a read op */
1987 	writel(frame_start | frame_op |
1988 		FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1989 		FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1990 
1991 	/* wait for end of transfer */
1992 	ret = fec_enet_mdio_wait(fep);
1993 	if (ret) {
1994 		netdev_err(fep->netdev, "MDIO read timeout\n");
1995 		goto out;
1996 	}
1997 
1998 	ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1999 
2000 out:
2001 	pm_runtime_mark_last_busy(dev);
2002 	pm_runtime_put_autosuspend(dev);
2003 
2004 	return ret;
2005 }
2006 
2007 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
2008 			   u16 value)
2009 {
2010 	struct fec_enet_private *fep = bus->priv;
2011 	struct device *dev = &fep->pdev->dev;
2012 	int ret, frame_start, frame_addr;
2013 	bool is_c45 = !!(regnum & MII_ADDR_C45);
2014 
2015 	ret = pm_runtime_resume_and_get(dev);
2016 	if (ret < 0)
2017 		return ret;
2018 
2019 	if (is_c45) {
2020 		frame_start = FEC_MMFR_ST_C45;
2021 
2022 		/* write address */
2023 		frame_addr = (regnum >> 16);
2024 		writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
2025 		       FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
2026 		       FEC_MMFR_TA | (regnum & 0xFFFF),
2027 		       fep->hwp + FEC_MII_DATA);
2028 
2029 		/* wait for end of transfer */
2030 		ret = fec_enet_mdio_wait(fep);
2031 		if (ret) {
2032 			netdev_err(fep->netdev, "MDIO address write timeout\n");
2033 			goto out;
2034 		}
2035 	} else {
2036 		/* C22 write */
2037 		frame_start = FEC_MMFR_ST;
2038 		frame_addr = regnum;
2039 	}
2040 
2041 	/* start a write op */
2042 	writel(frame_start | FEC_MMFR_OP_WRITE |
2043 		FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
2044 		FEC_MMFR_TA | FEC_MMFR_DATA(value),
2045 		fep->hwp + FEC_MII_DATA);
2046 
2047 	/* wait for end of transfer */
2048 	ret = fec_enet_mdio_wait(fep);
2049 	if (ret)
2050 		netdev_err(fep->netdev, "MDIO write timeout\n");
2051 
2052 out:
2053 	pm_runtime_mark_last_busy(dev);
2054 	pm_runtime_put_autosuspend(dev);
2055 
2056 	return ret;
2057 }
2058 
2059 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev)
2060 {
2061 	struct fec_enet_private *fep = netdev_priv(ndev);
2062 	struct phy_device *phy_dev = ndev->phydev;
2063 
2064 	if (phy_dev) {
2065 		phy_reset_after_clk_enable(phy_dev);
2066 	} else if (fep->phy_node) {
2067 		/*
2068 		 * If the PHY still is not bound to the MAC, but there is
2069 		 * OF PHY node and a matching PHY device instance already,
2070 		 * use the OF PHY node to obtain the PHY device instance,
2071 		 * and then use that PHY device instance when triggering
2072 		 * the PHY reset.
2073 		 */
2074 		phy_dev = of_phy_find_device(fep->phy_node);
2075 		phy_reset_after_clk_enable(phy_dev);
2076 		put_device(&phy_dev->mdio.dev);
2077 	}
2078 }
2079 
2080 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
2081 {
2082 	struct fec_enet_private *fep = netdev_priv(ndev);
2083 	int ret;
2084 
2085 	if (enable) {
2086 		ret = clk_prepare_enable(fep->clk_enet_out);
2087 		if (ret)
2088 			return ret;
2089 
2090 		if (fep->clk_ptp) {
2091 			mutex_lock(&fep->ptp_clk_mutex);
2092 			ret = clk_prepare_enable(fep->clk_ptp);
2093 			if (ret) {
2094 				mutex_unlock(&fep->ptp_clk_mutex);
2095 				goto failed_clk_ptp;
2096 			} else {
2097 				fep->ptp_clk_on = true;
2098 			}
2099 			mutex_unlock(&fep->ptp_clk_mutex);
2100 		}
2101 
2102 		ret = clk_prepare_enable(fep->clk_ref);
2103 		if (ret)
2104 			goto failed_clk_ref;
2105 
2106 		ret = clk_prepare_enable(fep->clk_2x_txclk);
2107 		if (ret)
2108 			goto failed_clk_2x_txclk;
2109 
2110 		fec_enet_phy_reset_after_clk_enable(ndev);
2111 	} else {
2112 		clk_disable_unprepare(fep->clk_enet_out);
2113 		if (fep->clk_ptp) {
2114 			mutex_lock(&fep->ptp_clk_mutex);
2115 			clk_disable_unprepare(fep->clk_ptp);
2116 			fep->ptp_clk_on = false;
2117 			mutex_unlock(&fep->ptp_clk_mutex);
2118 		}
2119 		clk_disable_unprepare(fep->clk_ref);
2120 		clk_disable_unprepare(fep->clk_2x_txclk);
2121 	}
2122 
2123 	return 0;
2124 
2125 failed_clk_2x_txclk:
2126 	if (fep->clk_ref)
2127 		clk_disable_unprepare(fep->clk_ref);
2128 failed_clk_ref:
2129 	if (fep->clk_ptp) {
2130 		mutex_lock(&fep->ptp_clk_mutex);
2131 		clk_disable_unprepare(fep->clk_ptp);
2132 		fep->ptp_clk_on = false;
2133 		mutex_unlock(&fep->ptp_clk_mutex);
2134 	}
2135 failed_clk_ptp:
2136 	clk_disable_unprepare(fep->clk_enet_out);
2137 
2138 	return ret;
2139 }
2140 
2141 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep,
2142 				      struct device_node *np)
2143 {
2144 	u32 rgmii_tx_delay, rgmii_rx_delay;
2145 
2146 	/* For rgmii tx internal delay, valid values are 0ps and 2000ps */
2147 	if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) {
2148 		if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) {
2149 			dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps");
2150 			return -EINVAL;
2151 		} else if (rgmii_tx_delay == 2000) {
2152 			fep->rgmii_txc_dly = true;
2153 		}
2154 	}
2155 
2156 	/* For rgmii rx internal delay, valid values are 0ps and 2000ps */
2157 	if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) {
2158 		if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) {
2159 			dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps");
2160 			return -EINVAL;
2161 		} else if (rgmii_rx_delay == 2000) {
2162 			fep->rgmii_rxc_dly = true;
2163 		}
2164 	}
2165 
2166 	return 0;
2167 }
2168 
2169 static int fec_enet_mii_probe(struct net_device *ndev)
2170 {
2171 	struct fec_enet_private *fep = netdev_priv(ndev);
2172 	struct phy_device *phy_dev = NULL;
2173 	char mdio_bus_id[MII_BUS_ID_SIZE];
2174 	char phy_name[MII_BUS_ID_SIZE + 3];
2175 	int phy_id;
2176 	int dev_id = fep->dev_id;
2177 
2178 	if (fep->phy_node) {
2179 		phy_dev = of_phy_connect(ndev, fep->phy_node,
2180 					 &fec_enet_adjust_link, 0,
2181 					 fep->phy_interface);
2182 		if (!phy_dev) {
2183 			netdev_err(ndev, "Unable to connect to phy\n");
2184 			return -ENODEV;
2185 		}
2186 	} else {
2187 		/* check for attached phy */
2188 		for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
2189 			if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
2190 				continue;
2191 			if (dev_id--)
2192 				continue;
2193 			strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
2194 			break;
2195 		}
2196 
2197 		if (phy_id >= PHY_MAX_ADDR) {
2198 			netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
2199 			strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
2200 			phy_id = 0;
2201 		}
2202 
2203 		snprintf(phy_name, sizeof(phy_name),
2204 			 PHY_ID_FMT, mdio_bus_id, phy_id);
2205 		phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
2206 				      fep->phy_interface);
2207 	}
2208 
2209 	if (IS_ERR(phy_dev)) {
2210 		netdev_err(ndev, "could not attach to PHY\n");
2211 		return PTR_ERR(phy_dev);
2212 	}
2213 
2214 	/* mask with MAC supported features */
2215 	if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
2216 		phy_set_max_speed(phy_dev, 1000);
2217 		phy_remove_link_mode(phy_dev,
2218 				     ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
2219 #if !defined(CONFIG_M5272)
2220 		phy_support_sym_pause(phy_dev);
2221 #endif
2222 	}
2223 	else
2224 		phy_set_max_speed(phy_dev, 100);
2225 
2226 	fep->link = 0;
2227 	fep->full_duplex = 0;
2228 
2229 	phy_dev->mac_managed_pm = 1;
2230 
2231 	phy_attached_info(phy_dev);
2232 
2233 	return 0;
2234 }
2235 
2236 static int fec_enet_mii_init(struct platform_device *pdev)
2237 {
2238 	static struct mii_bus *fec0_mii_bus;
2239 	struct net_device *ndev = platform_get_drvdata(pdev);
2240 	struct fec_enet_private *fep = netdev_priv(ndev);
2241 	bool suppress_preamble = false;
2242 	struct device_node *node;
2243 	int err = -ENXIO;
2244 	u32 mii_speed, holdtime;
2245 	u32 bus_freq;
2246 
2247 	/*
2248 	 * The i.MX28 dual fec interfaces are not equal.
2249 	 * Here are the differences:
2250 	 *
2251 	 *  - fec0 supports MII & RMII modes while fec1 only supports RMII
2252 	 *  - fec0 acts as the 1588 time master while fec1 is slave
2253 	 *  - external phys can only be configured by fec0
2254 	 *
2255 	 * That is to say fec1 can not work independently. It only works
2256 	 * when fec0 is working. The reason behind this design is that the
2257 	 * second interface is added primarily for Switch mode.
2258 	 *
2259 	 * Because of the last point above, both phys are attached on fec0
2260 	 * mdio interface in board design, and need to be configured by
2261 	 * fec0 mii_bus.
2262 	 */
2263 	if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
2264 		/* fec1 uses fec0 mii_bus */
2265 		if (mii_cnt && fec0_mii_bus) {
2266 			fep->mii_bus = fec0_mii_bus;
2267 			mii_cnt++;
2268 			return 0;
2269 		}
2270 		return -ENOENT;
2271 	}
2272 
2273 	bus_freq = 2500000; /* 2.5MHz by default */
2274 	node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2275 	if (node) {
2276 		of_property_read_u32(node, "clock-frequency", &bus_freq);
2277 		suppress_preamble = of_property_read_bool(node,
2278 							  "suppress-preamble");
2279 	}
2280 
2281 	/*
2282 	 * Set MII speed (= clk_get_rate() / 2 * phy_speed)
2283 	 *
2284 	 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2285 	 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'.  The i.MX28
2286 	 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2287 	 * document.
2288 	 */
2289 	mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2);
2290 	if (fep->quirks & FEC_QUIRK_ENET_MAC)
2291 		mii_speed--;
2292 	if (mii_speed > 63) {
2293 		dev_err(&pdev->dev,
2294 			"fec clock (%lu) too fast to get right mii speed\n",
2295 			clk_get_rate(fep->clk_ipg));
2296 		err = -EINVAL;
2297 		goto err_out;
2298 	}
2299 
2300 	/*
2301 	 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2302 	 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2303 	 * versions are RAZ there, so just ignore the difference and write the
2304 	 * register always.
2305 	 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2306 	 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2307 	 * output.
2308 	 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2309 	 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2310 	 * holdtime cannot result in a value greater than 3.
2311 	 */
2312 	holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2313 
2314 	fep->phy_speed = mii_speed << 1 | holdtime << 8;
2315 
2316 	if (suppress_preamble)
2317 		fep->phy_speed |= BIT(7);
2318 
2319 	if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) {
2320 		/* Clear MMFR to avoid to generate MII event by writing MSCR.
2321 		 * MII event generation condition:
2322 		 * - writing MSCR:
2323 		 *	- mmfr[31:0]_not_zero & mscr[7:0]_is_zero &
2324 		 *	  mscr_reg_data_in[7:0] != 0
2325 		 * - writing MMFR:
2326 		 *	- mscr[7:0]_not_zero
2327 		 */
2328 		writel(0, fep->hwp + FEC_MII_DATA);
2329 	}
2330 
2331 	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2332 
2333 	/* Clear any pending transaction complete indication */
2334 	writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
2335 
2336 	fep->mii_bus = mdiobus_alloc();
2337 	if (fep->mii_bus == NULL) {
2338 		err = -ENOMEM;
2339 		goto err_out;
2340 	}
2341 
2342 	fep->mii_bus->name = "fec_enet_mii_bus";
2343 	fep->mii_bus->read = fec_enet_mdio_read;
2344 	fep->mii_bus->write = fec_enet_mdio_write;
2345 	snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2346 		pdev->name, fep->dev_id + 1);
2347 	fep->mii_bus->priv = fep;
2348 	fep->mii_bus->parent = &pdev->dev;
2349 
2350 	err = of_mdiobus_register(fep->mii_bus, node);
2351 	if (err)
2352 		goto err_out_free_mdiobus;
2353 	of_node_put(node);
2354 
2355 	mii_cnt++;
2356 
2357 	/* save fec0 mii_bus */
2358 	if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2359 		fec0_mii_bus = fep->mii_bus;
2360 
2361 	return 0;
2362 
2363 err_out_free_mdiobus:
2364 	mdiobus_free(fep->mii_bus);
2365 err_out:
2366 	of_node_put(node);
2367 	return err;
2368 }
2369 
2370 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2371 {
2372 	if (--mii_cnt == 0) {
2373 		mdiobus_unregister(fep->mii_bus);
2374 		mdiobus_free(fep->mii_bus);
2375 	}
2376 }
2377 
2378 static void fec_enet_get_drvinfo(struct net_device *ndev,
2379 				 struct ethtool_drvinfo *info)
2380 {
2381 	struct fec_enet_private *fep = netdev_priv(ndev);
2382 
2383 	strscpy(info->driver, fep->pdev->dev.driver->name,
2384 		sizeof(info->driver));
2385 	strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2386 }
2387 
2388 static int fec_enet_get_regs_len(struct net_device *ndev)
2389 {
2390 	struct fec_enet_private *fep = netdev_priv(ndev);
2391 	struct resource *r;
2392 	int s = 0;
2393 
2394 	r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2395 	if (r)
2396 		s = resource_size(r);
2397 
2398 	return s;
2399 }
2400 
2401 /* List of registers that can be safety be read to dump them with ethtool */
2402 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2403 	defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2404 	defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2405 static __u32 fec_enet_register_version = 2;
2406 static u32 fec_enet_register_offset[] = {
2407 	FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2408 	FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2409 	FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2410 	FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2411 	FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2412 	FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2413 	FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2414 	FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2415 	FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2416 	FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2417 	FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2418 	FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2419 	RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2420 	RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2421 	RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2422 	RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2423 	RMON_T_P_GTE2048, RMON_T_OCTETS,
2424 	IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2425 	IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2426 	IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2427 	RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2428 	RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2429 	RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2430 	RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2431 	RMON_R_P_GTE2048, RMON_R_OCTETS,
2432 	IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2433 	IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2434 };
2435 /* for i.MX6ul */
2436 static u32 fec_enet_register_offset_6ul[] = {
2437 	FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2438 	FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2439 	FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0,
2440 	FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH,
2441 	FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0,
2442 	FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2443 	FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC,
2444 	RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2445 	RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2446 	RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2447 	RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2448 	RMON_T_P_GTE2048, RMON_T_OCTETS,
2449 	IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2450 	IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2451 	IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2452 	RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2453 	RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2454 	RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2455 	RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2456 	RMON_R_P_GTE2048, RMON_R_OCTETS,
2457 	IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2458 	IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2459 };
2460 #else
2461 static __u32 fec_enet_register_version = 1;
2462 static u32 fec_enet_register_offset[] = {
2463 	FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2464 	FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2465 	FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2466 	FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2467 	FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2468 	FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2469 	FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2470 	FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2471 	FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2472 };
2473 #endif
2474 
2475 static void fec_enet_get_regs(struct net_device *ndev,
2476 			      struct ethtool_regs *regs, void *regbuf)
2477 {
2478 	struct fec_enet_private *fep = netdev_priv(ndev);
2479 	u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2480 	struct device *dev = &fep->pdev->dev;
2481 	u32 *buf = (u32 *)regbuf;
2482 	u32 i, off;
2483 	int ret;
2484 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2485 	defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2486 	defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2487 	u32 *reg_list;
2488 	u32 reg_cnt;
2489 
2490 	if (!of_machine_is_compatible("fsl,imx6ul")) {
2491 		reg_list = fec_enet_register_offset;
2492 		reg_cnt = ARRAY_SIZE(fec_enet_register_offset);
2493 	} else {
2494 		reg_list = fec_enet_register_offset_6ul;
2495 		reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul);
2496 	}
2497 #else
2498 	/* coldfire */
2499 	static u32 *reg_list = fec_enet_register_offset;
2500 	static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset);
2501 #endif
2502 	ret = pm_runtime_resume_and_get(dev);
2503 	if (ret < 0)
2504 		return;
2505 
2506 	regs->version = fec_enet_register_version;
2507 
2508 	memset(buf, 0, regs->len);
2509 
2510 	for (i = 0; i < reg_cnt; i++) {
2511 		off = reg_list[i];
2512 
2513 		if ((off == FEC_R_BOUND || off == FEC_R_FSTART) &&
2514 		    !(fep->quirks & FEC_QUIRK_HAS_FRREG))
2515 			continue;
2516 
2517 		off >>= 2;
2518 		buf[off] = readl(&theregs[off]);
2519 	}
2520 
2521 	pm_runtime_mark_last_busy(dev);
2522 	pm_runtime_put_autosuspend(dev);
2523 }
2524 
2525 static int fec_enet_get_ts_info(struct net_device *ndev,
2526 				struct ethtool_ts_info *info)
2527 {
2528 	struct fec_enet_private *fep = netdev_priv(ndev);
2529 
2530 	if (fep->bufdesc_ex) {
2531 
2532 		info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2533 					SOF_TIMESTAMPING_RX_SOFTWARE |
2534 					SOF_TIMESTAMPING_SOFTWARE |
2535 					SOF_TIMESTAMPING_TX_HARDWARE |
2536 					SOF_TIMESTAMPING_RX_HARDWARE |
2537 					SOF_TIMESTAMPING_RAW_HARDWARE;
2538 		if (fep->ptp_clock)
2539 			info->phc_index = ptp_clock_index(fep->ptp_clock);
2540 		else
2541 			info->phc_index = -1;
2542 
2543 		info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2544 				 (1 << HWTSTAMP_TX_ON);
2545 
2546 		info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2547 				   (1 << HWTSTAMP_FILTER_ALL);
2548 		return 0;
2549 	} else {
2550 		return ethtool_op_get_ts_info(ndev, info);
2551 	}
2552 }
2553 
2554 #if !defined(CONFIG_M5272)
2555 
2556 static void fec_enet_get_pauseparam(struct net_device *ndev,
2557 				    struct ethtool_pauseparam *pause)
2558 {
2559 	struct fec_enet_private *fep = netdev_priv(ndev);
2560 
2561 	pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2562 	pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2563 	pause->rx_pause = pause->tx_pause;
2564 }
2565 
2566 static int fec_enet_set_pauseparam(struct net_device *ndev,
2567 				   struct ethtool_pauseparam *pause)
2568 {
2569 	struct fec_enet_private *fep = netdev_priv(ndev);
2570 
2571 	if (!ndev->phydev)
2572 		return -ENODEV;
2573 
2574 	if (pause->tx_pause != pause->rx_pause) {
2575 		netdev_info(ndev,
2576 			"hardware only support enable/disable both tx and rx");
2577 		return -EINVAL;
2578 	}
2579 
2580 	fep->pause_flag = 0;
2581 
2582 	/* tx pause must be same as rx pause */
2583 	fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2584 	fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2585 
2586 	phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause,
2587 			  pause->autoneg);
2588 
2589 	if (pause->autoneg) {
2590 		if (netif_running(ndev))
2591 			fec_stop(ndev);
2592 		phy_start_aneg(ndev->phydev);
2593 	}
2594 	if (netif_running(ndev)) {
2595 		napi_disable(&fep->napi);
2596 		netif_tx_lock_bh(ndev);
2597 		fec_restart(ndev);
2598 		netif_tx_wake_all_queues(ndev);
2599 		netif_tx_unlock_bh(ndev);
2600 		napi_enable(&fep->napi);
2601 	}
2602 
2603 	return 0;
2604 }
2605 
2606 static const struct fec_stat {
2607 	char name[ETH_GSTRING_LEN];
2608 	u16 offset;
2609 } fec_stats[] = {
2610 	/* RMON TX */
2611 	{ "tx_dropped", RMON_T_DROP },
2612 	{ "tx_packets", RMON_T_PACKETS },
2613 	{ "tx_broadcast", RMON_T_BC_PKT },
2614 	{ "tx_multicast", RMON_T_MC_PKT },
2615 	{ "tx_crc_errors", RMON_T_CRC_ALIGN },
2616 	{ "tx_undersize", RMON_T_UNDERSIZE },
2617 	{ "tx_oversize", RMON_T_OVERSIZE },
2618 	{ "tx_fragment", RMON_T_FRAG },
2619 	{ "tx_jabber", RMON_T_JAB },
2620 	{ "tx_collision", RMON_T_COL },
2621 	{ "tx_64byte", RMON_T_P64 },
2622 	{ "tx_65to127byte", RMON_T_P65TO127 },
2623 	{ "tx_128to255byte", RMON_T_P128TO255 },
2624 	{ "tx_256to511byte", RMON_T_P256TO511 },
2625 	{ "tx_512to1023byte", RMON_T_P512TO1023 },
2626 	{ "tx_1024to2047byte", RMON_T_P1024TO2047 },
2627 	{ "tx_GTE2048byte", RMON_T_P_GTE2048 },
2628 	{ "tx_octets", RMON_T_OCTETS },
2629 
2630 	/* IEEE TX */
2631 	{ "IEEE_tx_drop", IEEE_T_DROP },
2632 	{ "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2633 	{ "IEEE_tx_1col", IEEE_T_1COL },
2634 	{ "IEEE_tx_mcol", IEEE_T_MCOL },
2635 	{ "IEEE_tx_def", IEEE_T_DEF },
2636 	{ "IEEE_tx_lcol", IEEE_T_LCOL },
2637 	{ "IEEE_tx_excol", IEEE_T_EXCOL },
2638 	{ "IEEE_tx_macerr", IEEE_T_MACERR },
2639 	{ "IEEE_tx_cserr", IEEE_T_CSERR },
2640 	{ "IEEE_tx_sqe", IEEE_T_SQE },
2641 	{ "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2642 	{ "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2643 
2644 	/* RMON RX */
2645 	{ "rx_packets", RMON_R_PACKETS },
2646 	{ "rx_broadcast", RMON_R_BC_PKT },
2647 	{ "rx_multicast", RMON_R_MC_PKT },
2648 	{ "rx_crc_errors", RMON_R_CRC_ALIGN },
2649 	{ "rx_undersize", RMON_R_UNDERSIZE },
2650 	{ "rx_oversize", RMON_R_OVERSIZE },
2651 	{ "rx_fragment", RMON_R_FRAG },
2652 	{ "rx_jabber", RMON_R_JAB },
2653 	{ "rx_64byte", RMON_R_P64 },
2654 	{ "rx_65to127byte", RMON_R_P65TO127 },
2655 	{ "rx_128to255byte", RMON_R_P128TO255 },
2656 	{ "rx_256to511byte", RMON_R_P256TO511 },
2657 	{ "rx_512to1023byte", RMON_R_P512TO1023 },
2658 	{ "rx_1024to2047byte", RMON_R_P1024TO2047 },
2659 	{ "rx_GTE2048byte", RMON_R_P_GTE2048 },
2660 	{ "rx_octets", RMON_R_OCTETS },
2661 
2662 	/* IEEE RX */
2663 	{ "IEEE_rx_drop", IEEE_R_DROP },
2664 	{ "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2665 	{ "IEEE_rx_crc", IEEE_R_CRC },
2666 	{ "IEEE_rx_align", IEEE_R_ALIGN },
2667 	{ "IEEE_rx_macerr", IEEE_R_MACERR },
2668 	{ "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2669 	{ "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2670 };
2671 
2672 #define FEC_STATS_SIZE		(ARRAY_SIZE(fec_stats) * sizeof(u64))
2673 
2674 static void fec_enet_update_ethtool_stats(struct net_device *dev)
2675 {
2676 	struct fec_enet_private *fep = netdev_priv(dev);
2677 	int i;
2678 
2679 	for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2680 		fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2681 }
2682 
2683 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2684 				       struct ethtool_stats *stats, u64 *data)
2685 {
2686 	struct fec_enet_private *fep = netdev_priv(dev);
2687 
2688 	if (netif_running(dev))
2689 		fec_enet_update_ethtool_stats(dev);
2690 
2691 	memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2692 }
2693 
2694 static void fec_enet_get_strings(struct net_device *netdev,
2695 	u32 stringset, u8 *data)
2696 {
2697 	int i;
2698 	switch (stringset) {
2699 	case ETH_SS_STATS:
2700 		for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2701 			memcpy(data + i * ETH_GSTRING_LEN,
2702 				fec_stats[i].name, ETH_GSTRING_LEN);
2703 		break;
2704 	case ETH_SS_TEST:
2705 		net_selftest_get_strings(data);
2706 		break;
2707 	}
2708 }
2709 
2710 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2711 {
2712 	switch (sset) {
2713 	case ETH_SS_STATS:
2714 		return ARRAY_SIZE(fec_stats);
2715 	case ETH_SS_TEST:
2716 		return net_selftest_get_count();
2717 	default:
2718 		return -EOPNOTSUPP;
2719 	}
2720 }
2721 
2722 static void fec_enet_clear_ethtool_stats(struct net_device *dev)
2723 {
2724 	struct fec_enet_private *fep = netdev_priv(dev);
2725 	int i;
2726 
2727 	/* Disable MIB statistics counters */
2728 	writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
2729 
2730 	for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2731 		writel(0, fep->hwp + fec_stats[i].offset);
2732 
2733 	/* Don't disable MIB statistics counters */
2734 	writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
2735 }
2736 
2737 #else	/* !defined(CONFIG_M5272) */
2738 #define FEC_STATS_SIZE	0
2739 static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2740 {
2741 }
2742 
2743 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
2744 {
2745 }
2746 #endif /* !defined(CONFIG_M5272) */
2747 
2748 /* ITR clock source is enet system clock (clk_ahb).
2749  * TCTT unit is cycle_ns * 64 cycle
2750  * So, the ICTT value = X us / (cycle_ns * 64)
2751  */
2752 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2753 {
2754 	struct fec_enet_private *fep = netdev_priv(ndev);
2755 
2756 	return us * (fep->itr_clk_rate / 64000) / 1000;
2757 }
2758 
2759 /* Set threshold for interrupt coalescing */
2760 static void fec_enet_itr_coal_set(struct net_device *ndev)
2761 {
2762 	struct fec_enet_private *fep = netdev_priv(ndev);
2763 	int rx_itr, tx_itr;
2764 
2765 	/* Must be greater than zero to avoid unpredictable behavior */
2766 	if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2767 	    !fep->tx_time_itr || !fep->tx_pkts_itr)
2768 		return;
2769 
2770 	/* Select enet system clock as Interrupt Coalescing
2771 	 * timer Clock Source
2772 	 */
2773 	rx_itr = FEC_ITR_CLK_SEL;
2774 	tx_itr = FEC_ITR_CLK_SEL;
2775 
2776 	/* set ICFT and ICTT */
2777 	rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2778 	rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2779 	tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2780 	tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2781 
2782 	rx_itr |= FEC_ITR_EN;
2783 	tx_itr |= FEC_ITR_EN;
2784 
2785 	writel(tx_itr, fep->hwp + FEC_TXIC0);
2786 	writel(rx_itr, fep->hwp + FEC_RXIC0);
2787 	if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
2788 		writel(tx_itr, fep->hwp + FEC_TXIC1);
2789 		writel(rx_itr, fep->hwp + FEC_RXIC1);
2790 		writel(tx_itr, fep->hwp + FEC_TXIC2);
2791 		writel(rx_itr, fep->hwp + FEC_RXIC2);
2792 	}
2793 }
2794 
2795 static int fec_enet_get_coalesce(struct net_device *ndev,
2796 				 struct ethtool_coalesce *ec,
2797 				 struct kernel_ethtool_coalesce *kernel_coal,
2798 				 struct netlink_ext_ack *extack)
2799 {
2800 	struct fec_enet_private *fep = netdev_priv(ndev);
2801 
2802 	if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2803 		return -EOPNOTSUPP;
2804 
2805 	ec->rx_coalesce_usecs = fep->rx_time_itr;
2806 	ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2807 
2808 	ec->tx_coalesce_usecs = fep->tx_time_itr;
2809 	ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2810 
2811 	return 0;
2812 }
2813 
2814 static int fec_enet_set_coalesce(struct net_device *ndev,
2815 				 struct ethtool_coalesce *ec,
2816 				 struct kernel_ethtool_coalesce *kernel_coal,
2817 				 struct netlink_ext_ack *extack)
2818 {
2819 	struct fec_enet_private *fep = netdev_priv(ndev);
2820 	struct device *dev = &fep->pdev->dev;
2821 	unsigned int cycle;
2822 
2823 	if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2824 		return -EOPNOTSUPP;
2825 
2826 	if (ec->rx_max_coalesced_frames > 255) {
2827 		dev_err(dev, "Rx coalesced frames exceed hardware limitation\n");
2828 		return -EINVAL;
2829 	}
2830 
2831 	if (ec->tx_max_coalesced_frames > 255) {
2832 		dev_err(dev, "Tx coalesced frame exceed hardware limitation\n");
2833 		return -EINVAL;
2834 	}
2835 
2836 	cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs);
2837 	if (cycle > 0xFFFF) {
2838 		dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");
2839 		return -EINVAL;
2840 	}
2841 
2842 	cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs);
2843 	if (cycle > 0xFFFF) {
2844 		dev_err(dev, "Tx coalesced usec exceed hardware limitation\n");
2845 		return -EINVAL;
2846 	}
2847 
2848 	fep->rx_time_itr = ec->rx_coalesce_usecs;
2849 	fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2850 
2851 	fep->tx_time_itr = ec->tx_coalesce_usecs;
2852 	fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2853 
2854 	fec_enet_itr_coal_set(ndev);
2855 
2856 	return 0;
2857 }
2858 
2859 static void fec_enet_itr_coal_init(struct net_device *ndev)
2860 {
2861 	struct ethtool_coalesce ec;
2862 
2863 	ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2864 	ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2865 
2866 	ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2867 	ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2868 
2869 	fec_enet_set_coalesce(ndev, &ec, NULL, NULL);
2870 }
2871 
2872 static int fec_enet_get_tunable(struct net_device *netdev,
2873 				const struct ethtool_tunable *tuna,
2874 				void *data)
2875 {
2876 	struct fec_enet_private *fep = netdev_priv(netdev);
2877 	int ret = 0;
2878 
2879 	switch (tuna->id) {
2880 	case ETHTOOL_RX_COPYBREAK:
2881 		*(u32 *)data = fep->rx_copybreak;
2882 		break;
2883 	default:
2884 		ret = -EINVAL;
2885 		break;
2886 	}
2887 
2888 	return ret;
2889 }
2890 
2891 static int fec_enet_set_tunable(struct net_device *netdev,
2892 				const struct ethtool_tunable *tuna,
2893 				const void *data)
2894 {
2895 	struct fec_enet_private *fep = netdev_priv(netdev);
2896 	int ret = 0;
2897 
2898 	switch (tuna->id) {
2899 	case ETHTOOL_RX_COPYBREAK:
2900 		fep->rx_copybreak = *(u32 *)data;
2901 		break;
2902 	default:
2903 		ret = -EINVAL;
2904 		break;
2905 	}
2906 
2907 	return ret;
2908 }
2909 
2910 /* LPI Sleep Ts count base on tx clk (clk_ref).
2911  * The lpi sleep cnt value = X us / (cycle_ns).
2912  */
2913 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us)
2914 {
2915 	struct fec_enet_private *fep = netdev_priv(ndev);
2916 
2917 	return us * (fep->clk_ref_rate / 1000) / 1000;
2918 }
2919 
2920 static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable)
2921 {
2922 	struct fec_enet_private *fep = netdev_priv(ndev);
2923 	struct ethtool_eee *p = &fep->eee;
2924 	unsigned int sleep_cycle, wake_cycle;
2925 	int ret = 0;
2926 
2927 	if (enable) {
2928 		ret = phy_init_eee(ndev->phydev, false);
2929 		if (ret)
2930 			return ret;
2931 
2932 		sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer);
2933 		wake_cycle = sleep_cycle;
2934 	} else {
2935 		sleep_cycle = 0;
2936 		wake_cycle = 0;
2937 	}
2938 
2939 	p->tx_lpi_enabled = enable;
2940 	p->eee_enabled = enable;
2941 	p->eee_active = enable;
2942 
2943 	writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP);
2944 	writel(wake_cycle, fep->hwp + FEC_LPI_WAKE);
2945 
2946 	return 0;
2947 }
2948 
2949 static int
2950 fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2951 {
2952 	struct fec_enet_private *fep = netdev_priv(ndev);
2953 	struct ethtool_eee *p = &fep->eee;
2954 
2955 	if (!(fep->quirks & FEC_QUIRK_HAS_EEE))
2956 		return -EOPNOTSUPP;
2957 
2958 	if (!netif_running(ndev))
2959 		return -ENETDOWN;
2960 
2961 	edata->eee_enabled = p->eee_enabled;
2962 	edata->eee_active = p->eee_active;
2963 	edata->tx_lpi_timer = p->tx_lpi_timer;
2964 	edata->tx_lpi_enabled = p->tx_lpi_enabled;
2965 
2966 	return phy_ethtool_get_eee(ndev->phydev, edata);
2967 }
2968 
2969 static int
2970 fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2971 {
2972 	struct fec_enet_private *fep = netdev_priv(ndev);
2973 	struct ethtool_eee *p = &fep->eee;
2974 	int ret = 0;
2975 
2976 	if (!(fep->quirks & FEC_QUIRK_HAS_EEE))
2977 		return -EOPNOTSUPP;
2978 
2979 	if (!netif_running(ndev))
2980 		return -ENETDOWN;
2981 
2982 	p->tx_lpi_timer = edata->tx_lpi_timer;
2983 
2984 	if (!edata->eee_enabled || !edata->tx_lpi_enabled ||
2985 	    !edata->tx_lpi_timer)
2986 		ret = fec_enet_eee_mode_set(ndev, false);
2987 	else
2988 		ret = fec_enet_eee_mode_set(ndev, true);
2989 
2990 	if (ret)
2991 		return ret;
2992 
2993 	return phy_ethtool_set_eee(ndev->phydev, edata);
2994 }
2995 
2996 static void
2997 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2998 {
2999 	struct fec_enet_private *fep = netdev_priv(ndev);
3000 
3001 	if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
3002 		wol->supported = WAKE_MAGIC;
3003 		wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
3004 	} else {
3005 		wol->supported = wol->wolopts = 0;
3006 	}
3007 }
3008 
3009 static int
3010 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
3011 {
3012 	struct fec_enet_private *fep = netdev_priv(ndev);
3013 
3014 	if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
3015 		return -EINVAL;
3016 
3017 	if (wol->wolopts & ~WAKE_MAGIC)
3018 		return -EINVAL;
3019 
3020 	device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
3021 	if (device_may_wakeup(&ndev->dev))
3022 		fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
3023 	else
3024 		fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
3025 
3026 	return 0;
3027 }
3028 
3029 static const struct ethtool_ops fec_enet_ethtool_ops = {
3030 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |
3031 				     ETHTOOL_COALESCE_MAX_FRAMES,
3032 	.get_drvinfo		= fec_enet_get_drvinfo,
3033 	.get_regs_len		= fec_enet_get_regs_len,
3034 	.get_regs		= fec_enet_get_regs,
3035 	.nway_reset		= phy_ethtool_nway_reset,
3036 	.get_link		= ethtool_op_get_link,
3037 	.get_coalesce		= fec_enet_get_coalesce,
3038 	.set_coalesce		= fec_enet_set_coalesce,
3039 #ifndef CONFIG_M5272
3040 	.get_pauseparam		= fec_enet_get_pauseparam,
3041 	.set_pauseparam		= fec_enet_set_pauseparam,
3042 	.get_strings		= fec_enet_get_strings,
3043 	.get_ethtool_stats	= fec_enet_get_ethtool_stats,
3044 	.get_sset_count		= fec_enet_get_sset_count,
3045 #endif
3046 	.get_ts_info		= fec_enet_get_ts_info,
3047 	.get_tunable		= fec_enet_get_tunable,
3048 	.set_tunable		= fec_enet_set_tunable,
3049 	.get_wol		= fec_enet_get_wol,
3050 	.set_wol		= fec_enet_set_wol,
3051 	.get_eee		= fec_enet_get_eee,
3052 	.set_eee		= fec_enet_set_eee,
3053 	.get_link_ksettings	= phy_ethtool_get_link_ksettings,
3054 	.set_link_ksettings	= phy_ethtool_set_link_ksettings,
3055 	.self_test		= net_selftest,
3056 };
3057 
3058 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
3059 {
3060 	struct fec_enet_private *fep = netdev_priv(ndev);
3061 	struct phy_device *phydev = ndev->phydev;
3062 
3063 	if (!netif_running(ndev))
3064 		return -EINVAL;
3065 
3066 	if (!phydev)
3067 		return -ENODEV;
3068 
3069 	if (fep->bufdesc_ex) {
3070 		bool use_fec_hwts = !phy_has_hwtstamp(phydev);
3071 
3072 		if (cmd == SIOCSHWTSTAMP) {
3073 			if (use_fec_hwts)
3074 				return fec_ptp_set(ndev, rq);
3075 			fec_ptp_disable_hwts(ndev);
3076 		} else if (cmd == SIOCGHWTSTAMP) {
3077 			if (use_fec_hwts)
3078 				return fec_ptp_get(ndev, rq);
3079 		}
3080 	}
3081 
3082 	return phy_mii_ioctl(phydev, rq, cmd);
3083 }
3084 
3085 static void fec_enet_free_buffers(struct net_device *ndev)
3086 {
3087 	struct fec_enet_private *fep = netdev_priv(ndev);
3088 	unsigned int i;
3089 	struct sk_buff *skb;
3090 	struct fec_enet_priv_tx_q *txq;
3091 	struct fec_enet_priv_rx_q *rxq;
3092 	unsigned int q;
3093 
3094 	for (q = 0; q < fep->num_rx_queues; q++) {
3095 		rxq = fep->rx_queue[q];
3096 		for (i = 0; i < rxq->bd.ring_size; i++)
3097 			page_pool_release_page(rxq->page_pool, rxq->rx_skb_info[i].page);
3098 
3099 		if (xdp_rxq_info_is_reg(&rxq->xdp_rxq))
3100 			xdp_rxq_info_unreg(&rxq->xdp_rxq);
3101 		page_pool_destroy(rxq->page_pool);
3102 		rxq->page_pool = NULL;
3103 	}
3104 
3105 	for (q = 0; q < fep->num_tx_queues; q++) {
3106 		txq = fep->tx_queue[q];
3107 		for (i = 0; i < txq->bd.ring_size; i++) {
3108 			kfree(txq->tx_bounce[i]);
3109 			txq->tx_bounce[i] = NULL;
3110 			skb = txq->tx_skbuff[i];
3111 			txq->tx_skbuff[i] = NULL;
3112 			dev_kfree_skb(skb);
3113 		}
3114 	}
3115 }
3116 
3117 static void fec_enet_free_queue(struct net_device *ndev)
3118 {
3119 	struct fec_enet_private *fep = netdev_priv(ndev);
3120 	int i;
3121 	struct fec_enet_priv_tx_q *txq;
3122 
3123 	for (i = 0; i < fep->num_tx_queues; i++)
3124 		if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
3125 			txq = fep->tx_queue[i];
3126 			dma_free_coherent(&fep->pdev->dev,
3127 					  txq->bd.ring_size * TSO_HEADER_SIZE,
3128 					  txq->tso_hdrs,
3129 					  txq->tso_hdrs_dma);
3130 		}
3131 
3132 	for (i = 0; i < fep->num_rx_queues; i++)
3133 		kfree(fep->rx_queue[i]);
3134 	for (i = 0; i < fep->num_tx_queues; i++)
3135 		kfree(fep->tx_queue[i]);
3136 }
3137 
3138 static int fec_enet_alloc_queue(struct net_device *ndev)
3139 {
3140 	struct fec_enet_private *fep = netdev_priv(ndev);
3141 	int i;
3142 	int ret = 0;
3143 	struct fec_enet_priv_tx_q *txq;
3144 
3145 	for (i = 0; i < fep->num_tx_queues; i++) {
3146 		txq = kzalloc(sizeof(*txq), GFP_KERNEL);
3147 		if (!txq) {
3148 			ret = -ENOMEM;
3149 			goto alloc_failed;
3150 		}
3151 
3152 		fep->tx_queue[i] = txq;
3153 		txq->bd.ring_size = TX_RING_SIZE;
3154 		fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
3155 
3156 		txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
3157 		txq->tx_wake_threshold =
3158 			(txq->bd.ring_size - txq->tx_stop_threshold) / 2;
3159 
3160 		txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev,
3161 					txq->bd.ring_size * TSO_HEADER_SIZE,
3162 					&txq->tso_hdrs_dma,
3163 					GFP_KERNEL);
3164 		if (!txq->tso_hdrs) {
3165 			ret = -ENOMEM;
3166 			goto alloc_failed;
3167 		}
3168 	}
3169 
3170 	for (i = 0; i < fep->num_rx_queues; i++) {
3171 		fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
3172 					   GFP_KERNEL);
3173 		if (!fep->rx_queue[i]) {
3174 			ret = -ENOMEM;
3175 			goto alloc_failed;
3176 		}
3177 
3178 		fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
3179 		fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
3180 	}
3181 	return ret;
3182 
3183 alloc_failed:
3184 	fec_enet_free_queue(ndev);
3185 	return ret;
3186 }
3187 
3188 static int
3189 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
3190 {
3191 	struct fec_enet_private *fep = netdev_priv(ndev);
3192 	struct fec_enet_priv_rx_q *rxq;
3193 	dma_addr_t phys_addr;
3194 	struct bufdesc	*bdp;
3195 	struct page *page;
3196 	int i, err;
3197 
3198 	rxq = fep->rx_queue[queue];
3199 	bdp = rxq->bd.base;
3200 
3201 	err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size);
3202 	if (err < 0) {
3203 		netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err);
3204 		return err;
3205 	}
3206 
3207 	for (i = 0; i < rxq->bd.ring_size; i++) {
3208 		page = page_pool_dev_alloc_pages(rxq->page_pool);
3209 		if (!page)
3210 			goto err_alloc;
3211 
3212 		phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM;
3213 		bdp->cbd_bufaddr = cpu_to_fec32(phys_addr);
3214 
3215 		rxq->rx_skb_info[i].page = page;
3216 		rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM;
3217 		bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
3218 
3219 		if (fep->bufdesc_ex) {
3220 			struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3221 			ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
3222 		}
3223 
3224 		bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
3225 	}
3226 
3227 	/* Set the last buffer to wrap. */
3228 	bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
3229 	bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
3230 	return 0;
3231 
3232  err_alloc:
3233 	fec_enet_free_buffers(ndev);
3234 	return -ENOMEM;
3235 }
3236 
3237 static int
3238 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
3239 {
3240 	struct fec_enet_private *fep = netdev_priv(ndev);
3241 	unsigned int i;
3242 	struct bufdesc  *bdp;
3243 	struct fec_enet_priv_tx_q *txq;
3244 
3245 	txq = fep->tx_queue[queue];
3246 	bdp = txq->bd.base;
3247 	for (i = 0; i < txq->bd.ring_size; i++) {
3248 		txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
3249 		if (!txq->tx_bounce[i])
3250 			goto err_alloc;
3251 
3252 		bdp->cbd_sc = cpu_to_fec16(0);
3253 		bdp->cbd_bufaddr = cpu_to_fec32(0);
3254 
3255 		if (fep->bufdesc_ex) {
3256 			struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3257 			ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
3258 		}
3259 
3260 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
3261 	}
3262 
3263 	/* Set the last buffer to wrap. */
3264 	bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
3265 	bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
3266 
3267 	return 0;
3268 
3269  err_alloc:
3270 	fec_enet_free_buffers(ndev);
3271 	return -ENOMEM;
3272 }
3273 
3274 static int fec_enet_alloc_buffers(struct net_device *ndev)
3275 {
3276 	struct fec_enet_private *fep = netdev_priv(ndev);
3277 	unsigned int i;
3278 
3279 	for (i = 0; i < fep->num_rx_queues; i++)
3280 		if (fec_enet_alloc_rxq_buffers(ndev, i))
3281 			return -ENOMEM;
3282 
3283 	for (i = 0; i < fep->num_tx_queues; i++)
3284 		if (fec_enet_alloc_txq_buffers(ndev, i))
3285 			return -ENOMEM;
3286 	return 0;
3287 }
3288 
3289 static int
3290 fec_enet_open(struct net_device *ndev)
3291 {
3292 	struct fec_enet_private *fep = netdev_priv(ndev);
3293 	int ret;
3294 	bool reset_again;
3295 
3296 	ret = pm_runtime_resume_and_get(&fep->pdev->dev);
3297 	if (ret < 0)
3298 		return ret;
3299 
3300 	pinctrl_pm_select_default_state(&fep->pdev->dev);
3301 	ret = fec_enet_clk_enable(ndev, true);
3302 	if (ret)
3303 		goto clk_enable;
3304 
3305 	/* During the first fec_enet_open call the PHY isn't probed at this
3306 	 * point. Therefore the phy_reset_after_clk_enable() call within
3307 	 * fec_enet_clk_enable() fails. As we need this reset in order to be
3308 	 * sure the PHY is working correctly we check if we need to reset again
3309 	 * later when the PHY is probed
3310 	 */
3311 	if (ndev->phydev && ndev->phydev->drv)
3312 		reset_again = false;
3313 	else
3314 		reset_again = true;
3315 
3316 	/* I should reset the ring buffers here, but I don't yet know
3317 	 * a simple way to do that.
3318 	 */
3319 
3320 	ret = fec_enet_alloc_buffers(ndev);
3321 	if (ret)
3322 		goto err_enet_alloc;
3323 
3324 	/* Init MAC prior to mii bus probe */
3325 	fec_restart(ndev);
3326 
3327 	/* Call phy_reset_after_clk_enable() again if it failed during
3328 	 * phy_reset_after_clk_enable() before because the PHY wasn't probed.
3329 	 */
3330 	if (reset_again)
3331 		fec_enet_phy_reset_after_clk_enable(ndev);
3332 
3333 	/* Probe and connect to PHY when open the interface */
3334 	ret = fec_enet_mii_probe(ndev);
3335 	if (ret)
3336 		goto err_enet_mii_probe;
3337 
3338 	if (fep->quirks & FEC_QUIRK_ERR006687)
3339 		imx6q_cpuidle_fec_irqs_used();
3340 
3341 	if (fep->quirks & FEC_QUIRK_HAS_PMQOS)
3342 		cpu_latency_qos_add_request(&fep->pm_qos_req, 0);
3343 
3344 	napi_enable(&fep->napi);
3345 	phy_start(ndev->phydev);
3346 	netif_tx_start_all_queues(ndev);
3347 
3348 	device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
3349 				 FEC_WOL_FLAG_ENABLE);
3350 
3351 	return 0;
3352 
3353 err_enet_mii_probe:
3354 	fec_enet_free_buffers(ndev);
3355 err_enet_alloc:
3356 	fec_enet_clk_enable(ndev, false);
3357 clk_enable:
3358 	pm_runtime_mark_last_busy(&fep->pdev->dev);
3359 	pm_runtime_put_autosuspend(&fep->pdev->dev);
3360 	pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3361 	return ret;
3362 }
3363 
3364 static int
3365 fec_enet_close(struct net_device *ndev)
3366 {
3367 	struct fec_enet_private *fep = netdev_priv(ndev);
3368 
3369 	phy_stop(ndev->phydev);
3370 
3371 	if (netif_device_present(ndev)) {
3372 		napi_disable(&fep->napi);
3373 		netif_tx_disable(ndev);
3374 		fec_stop(ndev);
3375 	}
3376 
3377 	phy_disconnect(ndev->phydev);
3378 
3379 	if (fep->quirks & FEC_QUIRK_ERR006687)
3380 		imx6q_cpuidle_fec_irqs_unused();
3381 
3382 	fec_enet_update_ethtool_stats(ndev);
3383 
3384 	fec_enet_clk_enable(ndev, false);
3385 	if (fep->quirks & FEC_QUIRK_HAS_PMQOS)
3386 		cpu_latency_qos_remove_request(&fep->pm_qos_req);
3387 
3388 	pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3389 	pm_runtime_mark_last_busy(&fep->pdev->dev);
3390 	pm_runtime_put_autosuspend(&fep->pdev->dev);
3391 
3392 	fec_enet_free_buffers(ndev);
3393 
3394 	return 0;
3395 }
3396 
3397 /* Set or clear the multicast filter for this adaptor.
3398  * Skeleton taken from sunlance driver.
3399  * The CPM Ethernet implementation allows Multicast as well as individual
3400  * MAC address filtering.  Some of the drivers check to make sure it is
3401  * a group multicast address, and discard those that are not.  I guess I
3402  * will do the same for now, but just remove the test if you want
3403  * individual filtering as well (do the upper net layers want or support
3404  * this kind of feature?).
3405  */
3406 
3407 #define FEC_HASH_BITS	6		/* #bits in hash */
3408 
3409 static void set_multicast_list(struct net_device *ndev)
3410 {
3411 	struct fec_enet_private *fep = netdev_priv(ndev);
3412 	struct netdev_hw_addr *ha;
3413 	unsigned int crc, tmp;
3414 	unsigned char hash;
3415 	unsigned int hash_high = 0, hash_low = 0;
3416 
3417 	if (ndev->flags & IFF_PROMISC) {
3418 		tmp = readl(fep->hwp + FEC_R_CNTRL);
3419 		tmp |= 0x8;
3420 		writel(tmp, fep->hwp + FEC_R_CNTRL);
3421 		return;
3422 	}
3423 
3424 	tmp = readl(fep->hwp + FEC_R_CNTRL);
3425 	tmp &= ~0x8;
3426 	writel(tmp, fep->hwp + FEC_R_CNTRL);
3427 
3428 	if (ndev->flags & IFF_ALLMULTI) {
3429 		/* Catch all multicast addresses, so set the
3430 		 * filter to all 1's
3431 		 */
3432 		writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3433 		writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3434 
3435 		return;
3436 	}
3437 
3438 	/* Add the addresses in hash register */
3439 	netdev_for_each_mc_addr(ha, ndev) {
3440 		/* calculate crc32 value of mac address */
3441 		crc = ether_crc_le(ndev->addr_len, ha->addr);
3442 
3443 		/* only upper 6 bits (FEC_HASH_BITS) are used
3444 		 * which point to specific bit in the hash registers
3445 		 */
3446 		hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
3447 
3448 		if (hash > 31)
3449 			hash_high |= 1 << (hash - 32);
3450 		else
3451 			hash_low |= 1 << hash;
3452 	}
3453 
3454 	writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3455 	writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3456 }
3457 
3458 /* Set a MAC change in hardware. */
3459 static int
3460 fec_set_mac_address(struct net_device *ndev, void *p)
3461 {
3462 	struct fec_enet_private *fep = netdev_priv(ndev);
3463 	struct sockaddr *addr = p;
3464 
3465 	if (addr) {
3466 		if (!is_valid_ether_addr(addr->sa_data))
3467 			return -EADDRNOTAVAIL;
3468 		eth_hw_addr_set(ndev, addr->sa_data);
3469 	}
3470 
3471 	/* Add netif status check here to avoid system hang in below case:
3472 	 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3473 	 * After ethx down, fec all clocks are gated off and then register
3474 	 * access causes system hang.
3475 	 */
3476 	if (!netif_running(ndev))
3477 		return 0;
3478 
3479 	writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3480 		(ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3481 		fep->hwp + FEC_ADDR_LOW);
3482 	writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3483 		fep->hwp + FEC_ADDR_HIGH);
3484 	return 0;
3485 }
3486 
3487 #ifdef CONFIG_NET_POLL_CONTROLLER
3488 /**
3489  * fec_poll_controller - FEC Poll controller function
3490  * @dev: The FEC network adapter
3491  *
3492  * Polled functionality used by netconsole and others in non interrupt mode
3493  *
3494  */
3495 static void fec_poll_controller(struct net_device *dev)
3496 {
3497 	int i;
3498 	struct fec_enet_private *fep = netdev_priv(dev);
3499 
3500 	for (i = 0; i < FEC_IRQ_NUM; i++) {
3501 		if (fep->irq[i] > 0) {
3502 			disable_irq(fep->irq[i]);
3503 			fec_enet_interrupt(fep->irq[i], dev);
3504 			enable_irq(fep->irq[i]);
3505 		}
3506 	}
3507 }
3508 #endif
3509 
3510 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3511 	netdev_features_t features)
3512 {
3513 	struct fec_enet_private *fep = netdev_priv(netdev);
3514 	netdev_features_t changed = features ^ netdev->features;
3515 
3516 	netdev->features = features;
3517 
3518 	/* Receive checksum has been changed */
3519 	if (changed & NETIF_F_RXCSUM) {
3520 		if (features & NETIF_F_RXCSUM)
3521 			fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3522 		else
3523 			fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3524 	}
3525 }
3526 
3527 static int fec_set_features(struct net_device *netdev,
3528 	netdev_features_t features)
3529 {
3530 	struct fec_enet_private *fep = netdev_priv(netdev);
3531 	netdev_features_t changed = features ^ netdev->features;
3532 
3533 	if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3534 		napi_disable(&fep->napi);
3535 		netif_tx_lock_bh(netdev);
3536 		fec_stop(netdev);
3537 		fec_enet_set_netdev_features(netdev, features);
3538 		fec_restart(netdev);
3539 		netif_tx_wake_all_queues(netdev);
3540 		netif_tx_unlock_bh(netdev);
3541 		napi_enable(&fep->napi);
3542 	} else {
3543 		fec_enet_set_netdev_features(netdev, features);
3544 	}
3545 
3546 	return 0;
3547 }
3548 
3549 static u16 fec_enet_get_raw_vlan_tci(struct sk_buff *skb)
3550 {
3551 	struct vlan_ethhdr *vhdr;
3552 	unsigned short vlan_TCI = 0;
3553 
3554 	if (skb->protocol == htons(ETH_P_ALL)) {
3555 		vhdr = (struct vlan_ethhdr *)(skb->data);
3556 		vlan_TCI = ntohs(vhdr->h_vlan_TCI);
3557 	}
3558 
3559 	return vlan_TCI;
3560 }
3561 
3562 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb,
3563 				 struct net_device *sb_dev)
3564 {
3565 	struct fec_enet_private *fep = netdev_priv(ndev);
3566 	u16 vlan_tag;
3567 
3568 	if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
3569 		return netdev_pick_tx(ndev, skb, NULL);
3570 
3571 	vlan_tag = fec_enet_get_raw_vlan_tci(skb);
3572 	if (!vlan_tag)
3573 		return vlan_tag;
3574 
3575 	return fec_enet_vlan_pri_to_queue[vlan_tag >> 13];
3576 }
3577 
3578 static const struct net_device_ops fec_netdev_ops = {
3579 	.ndo_open		= fec_enet_open,
3580 	.ndo_stop		= fec_enet_close,
3581 	.ndo_start_xmit		= fec_enet_start_xmit,
3582 	.ndo_select_queue       = fec_enet_select_queue,
3583 	.ndo_set_rx_mode	= set_multicast_list,
3584 	.ndo_validate_addr	= eth_validate_addr,
3585 	.ndo_tx_timeout		= fec_timeout,
3586 	.ndo_set_mac_address	= fec_set_mac_address,
3587 	.ndo_eth_ioctl		= fec_enet_ioctl,
3588 #ifdef CONFIG_NET_POLL_CONTROLLER
3589 	.ndo_poll_controller	= fec_poll_controller,
3590 #endif
3591 	.ndo_set_features	= fec_set_features,
3592 };
3593 
3594 static const unsigned short offset_des_active_rxq[] = {
3595 	FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3596 };
3597 
3598 static const unsigned short offset_des_active_txq[] = {
3599 	FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3600 };
3601 
3602  /*
3603   * XXX:  We need to clean up on failure exits here.
3604   *
3605   */
3606 static int fec_enet_init(struct net_device *ndev)
3607 {
3608 	struct fec_enet_private *fep = netdev_priv(ndev);
3609 	struct bufdesc *cbd_base;
3610 	dma_addr_t bd_dma;
3611 	int bd_size;
3612 	unsigned int i;
3613 	unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3614 			sizeof(struct bufdesc);
3615 	unsigned dsize_log2 = __fls(dsize);
3616 	int ret;
3617 
3618 	WARN_ON(dsize != (1 << dsize_log2));
3619 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
3620 	fep->rx_align = 0xf;
3621 	fep->tx_align = 0xf;
3622 #else
3623 	fep->rx_align = 0x3;
3624 	fep->tx_align = 0x3;
3625 #endif
3626 
3627 	/* Check mask of the streaming and coherent API */
3628 	ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32));
3629 	if (ret < 0) {
3630 		dev_warn(&fep->pdev->dev, "No suitable DMA available\n");
3631 		return ret;
3632 	}
3633 
3634 	ret = fec_enet_alloc_queue(ndev);
3635 	if (ret)
3636 		return ret;
3637 
3638 	bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
3639 
3640 	/* Allocate memory for buffer descriptors. */
3641 	cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3642 				       GFP_KERNEL);
3643 	if (!cbd_base) {
3644 		ret = -ENOMEM;
3645 		goto free_queue_mem;
3646 	}
3647 
3648 	/* Get the Ethernet address */
3649 	ret = fec_get_mac(ndev);
3650 	if (ret)
3651 		goto free_queue_mem;
3652 
3653 	/* make sure MAC we just acquired is programmed into the hw */
3654 	fec_set_mac_address(ndev, NULL);
3655 
3656 	/* Set receive and transmit descriptor base. */
3657 	for (i = 0; i < fep->num_rx_queues; i++) {
3658 		struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3659 		unsigned size = dsize * rxq->bd.ring_size;
3660 
3661 		rxq->bd.qid = i;
3662 		rxq->bd.base = cbd_base;
3663 		rxq->bd.cur = cbd_base;
3664 		rxq->bd.dma = bd_dma;
3665 		rxq->bd.dsize = dsize;
3666 		rxq->bd.dsize_log2 = dsize_log2;
3667 		rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
3668 		bd_dma += size;
3669 		cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3670 		rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3671 	}
3672 
3673 	for (i = 0; i < fep->num_tx_queues; i++) {
3674 		struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3675 		unsigned size = dsize * txq->bd.ring_size;
3676 
3677 		txq->bd.qid = i;
3678 		txq->bd.base = cbd_base;
3679 		txq->bd.cur = cbd_base;
3680 		txq->bd.dma = bd_dma;
3681 		txq->bd.dsize = dsize;
3682 		txq->bd.dsize_log2 = dsize_log2;
3683 		txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
3684 		bd_dma += size;
3685 		cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3686 		txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3687 	}
3688 
3689 
3690 	/* The FEC Ethernet specific entries in the device structure */
3691 	ndev->watchdog_timeo = TX_TIMEOUT;
3692 	ndev->netdev_ops = &fec_netdev_ops;
3693 	ndev->ethtool_ops = &fec_enet_ethtool_ops;
3694 
3695 	writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3696 	netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi);
3697 
3698 	if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3699 		/* enable hw VLAN support */
3700 		ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3701 
3702 	if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3703 		netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS);
3704 
3705 		/* enable hw accelerator */
3706 		ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3707 				| NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3708 		fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3709 	}
3710 
3711 	if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
3712 		fep->tx_align = 0;
3713 		fep->rx_align = 0x3f;
3714 	}
3715 
3716 	ndev->hw_features = ndev->features;
3717 
3718 	fec_restart(ndev);
3719 
3720 	if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
3721 		fec_enet_clear_ethtool_stats(ndev);
3722 	else
3723 		fec_enet_update_ethtool_stats(ndev);
3724 
3725 	return 0;
3726 
3727 free_queue_mem:
3728 	fec_enet_free_queue(ndev);
3729 	return ret;
3730 }
3731 
3732 #ifdef CONFIG_OF
3733 static int fec_reset_phy(struct platform_device *pdev)
3734 {
3735 	int err, phy_reset;
3736 	bool active_high = false;
3737 	int msec = 1, phy_post_delay = 0;
3738 	struct device_node *np = pdev->dev.of_node;
3739 
3740 	if (!np)
3741 		return 0;
3742 
3743 	err = of_property_read_u32(np, "phy-reset-duration", &msec);
3744 	/* A sane reset duration should not be longer than 1s */
3745 	if (!err && msec > 1000)
3746 		msec = 1;
3747 
3748 	phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3749 	if (phy_reset == -EPROBE_DEFER)
3750 		return phy_reset;
3751 	else if (!gpio_is_valid(phy_reset))
3752 		return 0;
3753 
3754 	err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
3755 	/* valid reset duration should be less than 1s */
3756 	if (!err && phy_post_delay > 1000)
3757 		return -EINVAL;
3758 
3759 	active_high = of_property_read_bool(np, "phy-reset-active-high");
3760 
3761 	err = devm_gpio_request_one(&pdev->dev, phy_reset,
3762 			active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
3763 			"phy-reset");
3764 	if (err) {
3765 		dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3766 		return err;
3767 	}
3768 
3769 	if (msec > 20)
3770 		msleep(msec);
3771 	else
3772 		usleep_range(msec * 1000, msec * 1000 + 1000);
3773 
3774 	gpio_set_value_cansleep(phy_reset, !active_high);
3775 
3776 	if (!phy_post_delay)
3777 		return 0;
3778 
3779 	if (phy_post_delay > 20)
3780 		msleep(phy_post_delay);
3781 	else
3782 		usleep_range(phy_post_delay * 1000,
3783 			     phy_post_delay * 1000 + 1000);
3784 
3785 	return 0;
3786 }
3787 #else /* CONFIG_OF */
3788 static int fec_reset_phy(struct platform_device *pdev)
3789 {
3790 	/*
3791 	 * In case of platform probe, the reset has been done
3792 	 * by machine code.
3793 	 */
3794 	return 0;
3795 }
3796 #endif /* CONFIG_OF */
3797 
3798 static void
3799 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3800 {
3801 	struct device_node *np = pdev->dev.of_node;
3802 
3803 	*num_tx = *num_rx = 1;
3804 
3805 	if (!np || !of_device_is_available(np))
3806 		return;
3807 
3808 	/* parse the num of tx and rx queues */
3809 	of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3810 
3811 	of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3812 
3813 	if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3814 		dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3815 			 *num_tx);
3816 		*num_tx = 1;
3817 		return;
3818 	}
3819 
3820 	if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3821 		dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3822 			 *num_rx);
3823 		*num_rx = 1;
3824 		return;
3825 	}
3826 
3827 }
3828 
3829 static int fec_enet_get_irq_cnt(struct platform_device *pdev)
3830 {
3831 	int irq_cnt = platform_irq_count(pdev);
3832 
3833 	if (irq_cnt > FEC_IRQ_NUM)
3834 		irq_cnt = FEC_IRQ_NUM;	/* last for pps */
3835 	else if (irq_cnt == 2)
3836 		irq_cnt = 1;	/* last for pps */
3837 	else if (irq_cnt <= 0)
3838 		irq_cnt = 1;	/* At least 1 irq is needed */
3839 	return irq_cnt;
3840 }
3841 
3842 static void fec_enet_get_wakeup_irq(struct platform_device *pdev)
3843 {
3844 	struct net_device *ndev = platform_get_drvdata(pdev);
3845 	struct fec_enet_private *fep = netdev_priv(ndev);
3846 
3847 	if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2)
3848 		fep->wake_irq = fep->irq[2];
3849 	else
3850 		fep->wake_irq = fep->irq[0];
3851 }
3852 
3853 static int fec_enet_init_stop_mode(struct fec_enet_private *fep,
3854 				   struct device_node *np)
3855 {
3856 	struct device_node *gpr_np;
3857 	u32 out_val[3];
3858 	int ret = 0;
3859 
3860 	gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0);
3861 	if (!gpr_np)
3862 		return 0;
3863 
3864 	ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
3865 					 ARRAY_SIZE(out_val));
3866 	if (ret) {
3867 		dev_dbg(&fep->pdev->dev, "no stop mode property\n");
3868 		goto out;
3869 	}
3870 
3871 	fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np);
3872 	if (IS_ERR(fep->stop_gpr.gpr)) {
3873 		dev_err(&fep->pdev->dev, "could not find gpr regmap\n");
3874 		ret = PTR_ERR(fep->stop_gpr.gpr);
3875 		fep->stop_gpr.gpr = NULL;
3876 		goto out;
3877 	}
3878 
3879 	fep->stop_gpr.reg = out_val[1];
3880 	fep->stop_gpr.bit = out_val[2];
3881 
3882 out:
3883 	of_node_put(gpr_np);
3884 
3885 	return ret;
3886 }
3887 
3888 static int
3889 fec_probe(struct platform_device *pdev)
3890 {
3891 	struct fec_enet_private *fep;
3892 	struct fec_platform_data *pdata;
3893 	phy_interface_t interface;
3894 	struct net_device *ndev;
3895 	int i, irq, ret = 0;
3896 	const struct of_device_id *of_id;
3897 	static int dev_id;
3898 	struct device_node *np = pdev->dev.of_node, *phy_node;
3899 	int num_tx_qs;
3900 	int num_rx_qs;
3901 	char irq_name[8];
3902 	int irq_cnt;
3903 	struct fec_devinfo *dev_info;
3904 
3905 	fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3906 
3907 	/* Init network device */
3908 	ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
3909 				  FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
3910 	if (!ndev)
3911 		return -ENOMEM;
3912 
3913 	SET_NETDEV_DEV(ndev, &pdev->dev);
3914 
3915 	/* setup board info structure */
3916 	fep = netdev_priv(ndev);
3917 
3918 	of_id = of_match_device(fec_dt_ids, &pdev->dev);
3919 	if (of_id)
3920 		pdev->id_entry = of_id->data;
3921 	dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data;
3922 	if (dev_info)
3923 		fep->quirks = dev_info->quirks;
3924 
3925 	fep->netdev = ndev;
3926 	fep->num_rx_queues = num_rx_qs;
3927 	fep->num_tx_queues = num_tx_qs;
3928 
3929 #if !defined(CONFIG_M5272)
3930 	/* default enable pause frame auto negotiation */
3931 	if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3932 		fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3933 #endif
3934 
3935 	/* Select default pin state */
3936 	pinctrl_pm_select_default_state(&pdev->dev);
3937 
3938 	fep->hwp = devm_platform_ioremap_resource(pdev, 0);
3939 	if (IS_ERR(fep->hwp)) {
3940 		ret = PTR_ERR(fep->hwp);
3941 		goto failed_ioremap;
3942 	}
3943 
3944 	fep->pdev = pdev;
3945 	fep->dev_id = dev_id++;
3946 
3947 	platform_set_drvdata(pdev, ndev);
3948 
3949 	if ((of_machine_is_compatible("fsl,imx6q") ||
3950 	     of_machine_is_compatible("fsl,imx6dl")) &&
3951 	    !of_property_read_bool(np, "fsl,err006687-workaround-present"))
3952 		fep->quirks |= FEC_QUIRK_ERR006687;
3953 
3954 	ret = fec_enet_ipc_handle_init(fep);
3955 	if (ret)
3956 		goto failed_ipc_init;
3957 
3958 	if (of_get_property(np, "fsl,magic-packet", NULL))
3959 		fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3960 
3961 	ret = fec_enet_init_stop_mode(fep, np);
3962 	if (ret)
3963 		goto failed_stop_mode;
3964 
3965 	phy_node = of_parse_phandle(np, "phy-handle", 0);
3966 	if (!phy_node && of_phy_is_fixed_link(np)) {
3967 		ret = of_phy_register_fixed_link(np);
3968 		if (ret < 0) {
3969 			dev_err(&pdev->dev,
3970 				"broken fixed-link specification\n");
3971 			goto failed_phy;
3972 		}
3973 		phy_node = of_node_get(np);
3974 	}
3975 	fep->phy_node = phy_node;
3976 
3977 	ret = of_get_phy_mode(pdev->dev.of_node, &interface);
3978 	if (ret) {
3979 		pdata = dev_get_platdata(&pdev->dev);
3980 		if (pdata)
3981 			fep->phy_interface = pdata->phy;
3982 		else
3983 			fep->phy_interface = PHY_INTERFACE_MODE_MII;
3984 	} else {
3985 		fep->phy_interface = interface;
3986 	}
3987 
3988 	ret = fec_enet_parse_rgmii_delay(fep, np);
3989 	if (ret)
3990 		goto failed_rgmii_delay;
3991 
3992 	fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3993 	if (IS_ERR(fep->clk_ipg)) {
3994 		ret = PTR_ERR(fep->clk_ipg);
3995 		goto failed_clk;
3996 	}
3997 
3998 	fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3999 	if (IS_ERR(fep->clk_ahb)) {
4000 		ret = PTR_ERR(fep->clk_ahb);
4001 		goto failed_clk;
4002 	}
4003 
4004 	fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
4005 
4006 	/* enet_out is optional, depends on board */
4007 	fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out");
4008 	if (IS_ERR(fep->clk_enet_out)) {
4009 		ret = PTR_ERR(fep->clk_enet_out);
4010 		goto failed_clk;
4011 	}
4012 
4013 	fep->ptp_clk_on = false;
4014 	mutex_init(&fep->ptp_clk_mutex);
4015 
4016 	/* clk_ref is optional, depends on board */
4017 	fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref");
4018 	if (IS_ERR(fep->clk_ref)) {
4019 		ret = PTR_ERR(fep->clk_ref);
4020 		goto failed_clk;
4021 	}
4022 	fep->clk_ref_rate = clk_get_rate(fep->clk_ref);
4023 
4024 	/* clk_2x_txclk is optional, depends on board */
4025 	if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) {
4026 		fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk");
4027 		if (IS_ERR(fep->clk_2x_txclk))
4028 			fep->clk_2x_txclk = NULL;
4029 	}
4030 
4031 	fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
4032 	fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
4033 	if (IS_ERR(fep->clk_ptp)) {
4034 		fep->clk_ptp = NULL;
4035 		fep->bufdesc_ex = false;
4036 	}
4037 
4038 	ret = fec_enet_clk_enable(ndev, true);
4039 	if (ret)
4040 		goto failed_clk;
4041 
4042 	ret = clk_prepare_enable(fep->clk_ipg);
4043 	if (ret)
4044 		goto failed_clk_ipg;
4045 	ret = clk_prepare_enable(fep->clk_ahb);
4046 	if (ret)
4047 		goto failed_clk_ahb;
4048 
4049 	fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy");
4050 	if (!IS_ERR(fep->reg_phy)) {
4051 		ret = regulator_enable(fep->reg_phy);
4052 		if (ret) {
4053 			dev_err(&pdev->dev,
4054 				"Failed to enable phy regulator: %d\n", ret);
4055 			goto failed_regulator;
4056 		}
4057 	} else {
4058 		if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
4059 			ret = -EPROBE_DEFER;
4060 			goto failed_regulator;
4061 		}
4062 		fep->reg_phy = NULL;
4063 	}
4064 
4065 	pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
4066 	pm_runtime_use_autosuspend(&pdev->dev);
4067 	pm_runtime_get_noresume(&pdev->dev);
4068 	pm_runtime_set_active(&pdev->dev);
4069 	pm_runtime_enable(&pdev->dev);
4070 
4071 	ret = fec_reset_phy(pdev);
4072 	if (ret)
4073 		goto failed_reset;
4074 
4075 	irq_cnt = fec_enet_get_irq_cnt(pdev);
4076 	if (fep->bufdesc_ex)
4077 		fec_ptp_init(pdev, irq_cnt);
4078 
4079 	ret = fec_enet_init(ndev);
4080 	if (ret)
4081 		goto failed_init;
4082 
4083 	for (i = 0; i < irq_cnt; i++) {
4084 		snprintf(irq_name, sizeof(irq_name), "int%d", i);
4085 		irq = platform_get_irq_byname_optional(pdev, irq_name);
4086 		if (irq < 0)
4087 			irq = platform_get_irq(pdev, i);
4088 		if (irq < 0) {
4089 			ret = irq;
4090 			goto failed_irq;
4091 		}
4092 		ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
4093 				       0, pdev->name, ndev);
4094 		if (ret)
4095 			goto failed_irq;
4096 
4097 		fep->irq[i] = irq;
4098 	}
4099 
4100 	/* Decide which interrupt line is wakeup capable */
4101 	fec_enet_get_wakeup_irq(pdev);
4102 
4103 	ret = fec_enet_mii_init(pdev);
4104 	if (ret)
4105 		goto failed_mii_init;
4106 
4107 	/* Carrier starts down, phylib will bring it up */
4108 	netif_carrier_off(ndev);
4109 	fec_enet_clk_enable(ndev, false);
4110 	pinctrl_pm_select_sleep_state(&pdev->dev);
4111 
4112 	ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN;
4113 
4114 	ret = register_netdev(ndev);
4115 	if (ret)
4116 		goto failed_register;
4117 
4118 	device_init_wakeup(&ndev->dev, fep->wol_flag &
4119 			   FEC_WOL_HAS_MAGIC_PACKET);
4120 
4121 	if (fep->bufdesc_ex && fep->ptp_clock)
4122 		netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
4123 
4124 	fep->rx_copybreak = COPYBREAK_DEFAULT;
4125 	INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
4126 
4127 	pm_runtime_mark_last_busy(&pdev->dev);
4128 	pm_runtime_put_autosuspend(&pdev->dev);
4129 
4130 	return 0;
4131 
4132 failed_register:
4133 	fec_enet_mii_remove(fep);
4134 failed_mii_init:
4135 failed_irq:
4136 failed_init:
4137 	fec_ptp_stop(pdev);
4138 failed_reset:
4139 	pm_runtime_put_noidle(&pdev->dev);
4140 	pm_runtime_disable(&pdev->dev);
4141 	if (fep->reg_phy)
4142 		regulator_disable(fep->reg_phy);
4143 failed_regulator:
4144 	clk_disable_unprepare(fep->clk_ahb);
4145 failed_clk_ahb:
4146 	clk_disable_unprepare(fep->clk_ipg);
4147 failed_clk_ipg:
4148 	fec_enet_clk_enable(ndev, false);
4149 failed_clk:
4150 failed_rgmii_delay:
4151 	if (of_phy_is_fixed_link(np))
4152 		of_phy_deregister_fixed_link(np);
4153 	of_node_put(phy_node);
4154 failed_stop_mode:
4155 failed_ipc_init:
4156 failed_phy:
4157 	dev_id--;
4158 failed_ioremap:
4159 	free_netdev(ndev);
4160 
4161 	return ret;
4162 }
4163 
4164 static int
4165 fec_drv_remove(struct platform_device *pdev)
4166 {
4167 	struct net_device *ndev = platform_get_drvdata(pdev);
4168 	struct fec_enet_private *fep = netdev_priv(ndev);
4169 	struct device_node *np = pdev->dev.of_node;
4170 	int ret;
4171 
4172 	ret = pm_runtime_resume_and_get(&pdev->dev);
4173 	if (ret < 0)
4174 		return ret;
4175 
4176 	cancel_work_sync(&fep->tx_timeout_work);
4177 	fec_ptp_stop(pdev);
4178 	unregister_netdev(ndev);
4179 	fec_enet_mii_remove(fep);
4180 	if (fep->reg_phy)
4181 		regulator_disable(fep->reg_phy);
4182 
4183 	if (of_phy_is_fixed_link(np))
4184 		of_phy_deregister_fixed_link(np);
4185 	of_node_put(fep->phy_node);
4186 
4187 	clk_disable_unprepare(fep->clk_ahb);
4188 	clk_disable_unprepare(fep->clk_ipg);
4189 	pm_runtime_put_noidle(&pdev->dev);
4190 	pm_runtime_disable(&pdev->dev);
4191 
4192 	free_netdev(ndev);
4193 	return 0;
4194 }
4195 
4196 static int __maybe_unused fec_suspend(struct device *dev)
4197 {
4198 	struct net_device *ndev = dev_get_drvdata(dev);
4199 	struct fec_enet_private *fep = netdev_priv(ndev);
4200 	int ret;
4201 
4202 	rtnl_lock();
4203 	if (netif_running(ndev)) {
4204 		if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
4205 			fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
4206 		phy_stop(ndev->phydev);
4207 		napi_disable(&fep->napi);
4208 		netif_tx_lock_bh(ndev);
4209 		netif_device_detach(ndev);
4210 		netif_tx_unlock_bh(ndev);
4211 		fec_stop(ndev);
4212 		if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
4213 			fec_irqs_disable(ndev);
4214 			pinctrl_pm_select_sleep_state(&fep->pdev->dev);
4215 		} else {
4216 			fec_irqs_disable_except_wakeup(ndev);
4217 			if (fep->wake_irq > 0) {
4218 				disable_irq(fep->wake_irq);
4219 				enable_irq_wake(fep->wake_irq);
4220 			}
4221 			fec_enet_stop_mode(fep, true);
4222 		}
4223 		/* It's safe to disable clocks since interrupts are masked */
4224 		fec_enet_clk_enable(ndev, false);
4225 
4226 		fep->rpm_active = !pm_runtime_status_suspended(dev);
4227 		if (fep->rpm_active) {
4228 			ret = pm_runtime_force_suspend(dev);
4229 			if (ret < 0) {
4230 				rtnl_unlock();
4231 				return ret;
4232 			}
4233 		}
4234 	}
4235 	rtnl_unlock();
4236 
4237 	if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
4238 		regulator_disable(fep->reg_phy);
4239 
4240 	/* SOC supply clock to phy, when clock is disabled, phy link down
4241 	 * SOC control phy regulator, when regulator is disabled, phy link down
4242 	 */
4243 	if (fep->clk_enet_out || fep->reg_phy)
4244 		fep->link = 0;
4245 
4246 	return 0;
4247 }
4248 
4249 static int __maybe_unused fec_resume(struct device *dev)
4250 {
4251 	struct net_device *ndev = dev_get_drvdata(dev);
4252 	struct fec_enet_private *fep = netdev_priv(ndev);
4253 	int ret;
4254 	int val;
4255 
4256 	if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
4257 		ret = regulator_enable(fep->reg_phy);
4258 		if (ret)
4259 			return ret;
4260 	}
4261 
4262 	rtnl_lock();
4263 	if (netif_running(ndev)) {
4264 		if (fep->rpm_active)
4265 			pm_runtime_force_resume(dev);
4266 
4267 		ret = fec_enet_clk_enable(ndev, true);
4268 		if (ret) {
4269 			rtnl_unlock();
4270 			goto failed_clk;
4271 		}
4272 		if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
4273 			fec_enet_stop_mode(fep, false);
4274 			if (fep->wake_irq) {
4275 				disable_irq_wake(fep->wake_irq);
4276 				enable_irq(fep->wake_irq);
4277 			}
4278 
4279 			val = readl(fep->hwp + FEC_ECNTRL);
4280 			val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
4281 			writel(val, fep->hwp + FEC_ECNTRL);
4282 			fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
4283 		} else {
4284 			pinctrl_pm_select_default_state(&fep->pdev->dev);
4285 		}
4286 		fec_restart(ndev);
4287 		netif_tx_lock_bh(ndev);
4288 		netif_device_attach(ndev);
4289 		netif_tx_unlock_bh(ndev);
4290 		napi_enable(&fep->napi);
4291 		phy_init_hw(ndev->phydev);
4292 		phy_start(ndev->phydev);
4293 	}
4294 	rtnl_unlock();
4295 
4296 	return 0;
4297 
4298 failed_clk:
4299 	if (fep->reg_phy)
4300 		regulator_disable(fep->reg_phy);
4301 	return ret;
4302 }
4303 
4304 static int __maybe_unused fec_runtime_suspend(struct device *dev)
4305 {
4306 	struct net_device *ndev = dev_get_drvdata(dev);
4307 	struct fec_enet_private *fep = netdev_priv(ndev);
4308 
4309 	clk_disable_unprepare(fep->clk_ahb);
4310 	clk_disable_unprepare(fep->clk_ipg);
4311 
4312 	return 0;
4313 }
4314 
4315 static int __maybe_unused fec_runtime_resume(struct device *dev)
4316 {
4317 	struct net_device *ndev = dev_get_drvdata(dev);
4318 	struct fec_enet_private *fep = netdev_priv(ndev);
4319 	int ret;
4320 
4321 	ret = clk_prepare_enable(fep->clk_ahb);
4322 	if (ret)
4323 		return ret;
4324 	ret = clk_prepare_enable(fep->clk_ipg);
4325 	if (ret)
4326 		goto failed_clk_ipg;
4327 
4328 	return 0;
4329 
4330 failed_clk_ipg:
4331 	clk_disable_unprepare(fep->clk_ahb);
4332 	return ret;
4333 }
4334 
4335 static const struct dev_pm_ops fec_pm_ops = {
4336 	SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
4337 	SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
4338 };
4339 
4340 static struct platform_driver fec_driver = {
4341 	.driver	= {
4342 		.name	= DRIVER_NAME,
4343 		.pm	= &fec_pm_ops,
4344 		.of_match_table = fec_dt_ids,
4345 		.suppress_bind_attrs = true,
4346 	},
4347 	.id_table = fec_devtype,
4348 	.probe	= fec_probe,
4349 	.remove	= fec_drv_remove,
4350 };
4351 
4352 module_platform_driver(fec_driver);
4353 
4354 MODULE_LICENSE("GPL");
4355