1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/selftests.h> 42 #include <net/tso.h> 43 #include <linux/tcp.h> 44 #include <linux/udp.h> 45 #include <linux/icmp.h> 46 #include <linux/spinlock.h> 47 #include <linux/workqueue.h> 48 #include <linux/bitops.h> 49 #include <linux/io.h> 50 #include <linux/irq.h> 51 #include <linux/clk.h> 52 #include <linux/crc32.h> 53 #include <linux/platform_device.h> 54 #include <linux/mdio.h> 55 #include <linux/phy.h> 56 #include <linux/fec.h> 57 #include <linux/of.h> 58 #include <linux/of_device.h> 59 #include <linux/of_gpio.h> 60 #include <linux/of_mdio.h> 61 #include <linux/of_net.h> 62 #include <linux/regulator/consumer.h> 63 #include <linux/if_vlan.h> 64 #include <linux/pinctrl/consumer.h> 65 #include <linux/prefetch.h> 66 #include <linux/mfd/syscon.h> 67 #include <linux/regmap.h> 68 #include <soc/imx/cpuidle.h> 69 70 #include <asm/cacheflush.h> 71 72 #include "fec.h" 73 74 static void set_multicast_list(struct net_device *ndev); 75 static void fec_enet_itr_coal_init(struct net_device *ndev); 76 77 #define DRIVER_NAME "fec" 78 79 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 80 81 /* Pause frame feild and FIFO threshold */ 82 #define FEC_ENET_FCE (1 << 5) 83 #define FEC_ENET_RSEM_V 0x84 84 #define FEC_ENET_RSFL_V 16 85 #define FEC_ENET_RAEM_V 0x8 86 #define FEC_ENET_RAFL_V 0x8 87 #define FEC_ENET_OPD_V 0xFFF0 88 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 89 90 struct fec_devinfo { 91 u32 quirks; 92 }; 93 94 static const struct fec_devinfo fec_imx25_info = { 95 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 96 FEC_QUIRK_HAS_FRREG, 97 }; 98 99 static const struct fec_devinfo fec_imx27_info = { 100 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG, 101 }; 102 103 static const struct fec_devinfo fec_imx28_info = { 104 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 105 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 106 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 107 FEC_QUIRK_NO_HARD_RESET, 108 }; 109 110 static const struct fec_devinfo fec_imx6q_info = { 111 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 112 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 113 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 114 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII | 115 FEC_QUIRK_HAS_PMQOS, 116 }; 117 118 static const struct fec_devinfo fec_mvf600_info = { 119 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 120 }; 121 122 static const struct fec_devinfo fec_imx6x_info = { 123 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 124 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 125 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 126 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 127 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 128 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES, 129 }; 130 131 static const struct fec_devinfo fec_imx6ul_info = { 132 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 133 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 134 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 135 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 136 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII, 137 }; 138 139 static const struct fec_devinfo fec_imx8mq_info = { 140 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 141 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 142 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 143 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 144 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 145 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 146 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2, 147 }; 148 149 static const struct fec_devinfo fec_imx8qm_info = { 150 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 151 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 152 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 153 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 154 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 155 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 156 FEC_QUIRK_DELAYED_CLKS_SUPPORT, 157 }; 158 159 static const struct fec_devinfo fec_s32v234_info = { 160 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 161 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 162 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 163 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE, 164 }; 165 166 static struct platform_device_id fec_devtype[] = { 167 { 168 /* keep it for coldfire */ 169 .name = DRIVER_NAME, 170 .driver_data = 0, 171 }, { 172 .name = "imx25-fec", 173 .driver_data = (kernel_ulong_t)&fec_imx25_info, 174 }, { 175 .name = "imx27-fec", 176 .driver_data = (kernel_ulong_t)&fec_imx27_info, 177 }, { 178 .name = "imx28-fec", 179 .driver_data = (kernel_ulong_t)&fec_imx28_info, 180 }, { 181 .name = "imx6q-fec", 182 .driver_data = (kernel_ulong_t)&fec_imx6q_info, 183 }, { 184 .name = "mvf600-fec", 185 .driver_data = (kernel_ulong_t)&fec_mvf600_info, 186 }, { 187 .name = "imx6sx-fec", 188 .driver_data = (kernel_ulong_t)&fec_imx6x_info, 189 }, { 190 .name = "imx6ul-fec", 191 .driver_data = (kernel_ulong_t)&fec_imx6ul_info, 192 }, { 193 .name = "imx8mq-fec", 194 .driver_data = (kernel_ulong_t)&fec_imx8mq_info, 195 }, { 196 .name = "imx8qm-fec", 197 .driver_data = (kernel_ulong_t)&fec_imx8qm_info, 198 }, { 199 .name = "s32v234-fec", 200 .driver_data = (kernel_ulong_t)&fec_s32v234_info, 201 }, { 202 /* sentinel */ 203 } 204 }; 205 MODULE_DEVICE_TABLE(platform, fec_devtype); 206 207 enum imx_fec_type { 208 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 209 IMX27_FEC, /* runs on i.mx27/35/51 */ 210 IMX28_FEC, 211 IMX6Q_FEC, 212 MVF600_FEC, 213 IMX6SX_FEC, 214 IMX6UL_FEC, 215 IMX8MQ_FEC, 216 IMX8QM_FEC, 217 S32V234_FEC, 218 }; 219 220 static const struct of_device_id fec_dt_ids[] = { 221 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 222 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 223 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 224 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 225 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 226 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 227 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 228 { .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], }, 229 { .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], }, 230 { .compatible = "fsl,s32v234-fec", .data = &fec_devtype[S32V234_FEC], }, 231 { /* sentinel */ } 232 }; 233 MODULE_DEVICE_TABLE(of, fec_dt_ids); 234 235 static unsigned char macaddr[ETH_ALEN]; 236 module_param_array(macaddr, byte, NULL, 0); 237 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 238 239 #if defined(CONFIG_M5272) 240 /* 241 * Some hardware gets it MAC address out of local flash memory. 242 * if this is non-zero then assume it is the address to get MAC from. 243 */ 244 #if defined(CONFIG_NETtel) 245 #define FEC_FLASHMAC 0xf0006006 246 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 247 #define FEC_FLASHMAC 0xf0006000 248 #elif defined(CONFIG_CANCam) 249 #define FEC_FLASHMAC 0xf0020000 250 #elif defined (CONFIG_M5272C3) 251 #define FEC_FLASHMAC (0xffe04000 + 4) 252 #elif defined(CONFIG_MOD5272) 253 #define FEC_FLASHMAC 0xffc0406b 254 #else 255 #define FEC_FLASHMAC 0 256 #endif 257 #endif /* CONFIG_M5272 */ 258 259 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 260 * 261 * 2048 byte skbufs are allocated. However, alignment requirements 262 * varies between FEC variants. Worst case is 64, so round down by 64. 263 */ 264 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 265 #define PKT_MINBUF_SIZE 64 266 267 /* FEC receive acceleration */ 268 #define FEC_RACC_IPDIS (1 << 1) 269 #define FEC_RACC_PRODIS (1 << 2) 270 #define FEC_RACC_SHIFT16 BIT(7) 271 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 272 273 /* MIB Control Register */ 274 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 275 276 /* 277 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 278 * size bits. Other FEC hardware does not, so we need to take that into 279 * account when setting it. 280 */ 281 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 282 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 283 defined(CONFIG_ARM64) 284 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 285 #else 286 #define OPT_FRAME_SIZE 0 287 #endif 288 289 /* FEC MII MMFR bits definition */ 290 #define FEC_MMFR_ST (1 << 30) 291 #define FEC_MMFR_ST_C45 (0) 292 #define FEC_MMFR_OP_READ (2 << 28) 293 #define FEC_MMFR_OP_READ_C45 (3 << 28) 294 #define FEC_MMFR_OP_WRITE (1 << 28) 295 #define FEC_MMFR_OP_ADDR_WRITE (0) 296 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 297 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 298 #define FEC_MMFR_TA (2 << 16) 299 #define FEC_MMFR_DATA(v) (v & 0xffff) 300 /* FEC ECR bits definition */ 301 #define FEC_ECR_MAGICEN (1 << 2) 302 #define FEC_ECR_SLEEP (1 << 3) 303 304 #define FEC_MII_TIMEOUT 30000 /* us */ 305 306 /* Transmitter timeout */ 307 #define TX_TIMEOUT (2 * HZ) 308 309 #define FEC_PAUSE_FLAG_AUTONEG 0x1 310 #define FEC_PAUSE_FLAG_ENABLE 0x2 311 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 312 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 313 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 314 315 #define COPYBREAK_DEFAULT 256 316 317 /* Max number of allowed TCP segments for software TSO */ 318 #define FEC_MAX_TSO_SEGS 100 319 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 320 321 #define IS_TSO_HEADER(txq, addr) \ 322 ((addr >= txq->tso_hdrs_dma) && \ 323 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 324 325 static int mii_cnt; 326 327 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 328 struct bufdesc_prop *bd) 329 { 330 return (bdp >= bd->last) ? bd->base 331 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 332 } 333 334 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 335 struct bufdesc_prop *bd) 336 { 337 return (bdp <= bd->base) ? bd->last 338 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 339 } 340 341 static int fec_enet_get_bd_index(struct bufdesc *bdp, 342 struct bufdesc_prop *bd) 343 { 344 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 345 } 346 347 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 348 { 349 int entries; 350 351 entries = (((const char *)txq->dirty_tx - 352 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 353 354 return entries >= 0 ? entries : entries + txq->bd.ring_size; 355 } 356 357 static void swap_buffer(void *bufaddr, int len) 358 { 359 int i; 360 unsigned int *buf = bufaddr; 361 362 for (i = 0; i < len; i += 4, buf++) 363 swab32s(buf); 364 } 365 366 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 367 { 368 int i; 369 unsigned int *src = src_buf; 370 unsigned int *dst = dst_buf; 371 372 for (i = 0; i < len; i += 4, src++, dst++) 373 *dst = swab32p(src); 374 } 375 376 static void fec_dump(struct net_device *ndev) 377 { 378 struct fec_enet_private *fep = netdev_priv(ndev); 379 struct bufdesc *bdp; 380 struct fec_enet_priv_tx_q *txq; 381 int index = 0; 382 383 netdev_info(ndev, "TX ring dump\n"); 384 pr_info("Nr SC addr len SKB\n"); 385 386 txq = fep->tx_queue[0]; 387 bdp = txq->bd.base; 388 389 do { 390 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 391 index, 392 bdp == txq->bd.cur ? 'S' : ' ', 393 bdp == txq->dirty_tx ? 'H' : ' ', 394 fec16_to_cpu(bdp->cbd_sc), 395 fec32_to_cpu(bdp->cbd_bufaddr), 396 fec16_to_cpu(bdp->cbd_datlen), 397 txq->tx_skbuff[index]); 398 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 399 index++; 400 } while (bdp != txq->bd.base); 401 } 402 403 static inline bool is_ipv4_pkt(struct sk_buff *skb) 404 { 405 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 406 } 407 408 static int 409 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 410 { 411 /* Only run for packets requiring a checksum. */ 412 if (skb->ip_summed != CHECKSUM_PARTIAL) 413 return 0; 414 415 if (unlikely(skb_cow_head(skb, 0))) 416 return -1; 417 418 if (is_ipv4_pkt(skb)) 419 ip_hdr(skb)->check = 0; 420 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 421 422 return 0; 423 } 424 425 static struct bufdesc * 426 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 427 struct sk_buff *skb, 428 struct net_device *ndev) 429 { 430 struct fec_enet_private *fep = netdev_priv(ndev); 431 struct bufdesc *bdp = txq->bd.cur; 432 struct bufdesc_ex *ebdp; 433 int nr_frags = skb_shinfo(skb)->nr_frags; 434 int frag, frag_len; 435 unsigned short status; 436 unsigned int estatus = 0; 437 skb_frag_t *this_frag; 438 unsigned int index; 439 void *bufaddr; 440 dma_addr_t addr; 441 int i; 442 443 for (frag = 0; frag < nr_frags; frag++) { 444 this_frag = &skb_shinfo(skb)->frags[frag]; 445 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 446 ebdp = (struct bufdesc_ex *)bdp; 447 448 status = fec16_to_cpu(bdp->cbd_sc); 449 status &= ~BD_ENET_TX_STATS; 450 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 451 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 452 453 /* Handle the last BD specially */ 454 if (frag == nr_frags - 1) { 455 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 456 if (fep->bufdesc_ex) { 457 estatus |= BD_ENET_TX_INT; 458 if (unlikely(skb_shinfo(skb)->tx_flags & 459 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 460 estatus |= BD_ENET_TX_TS; 461 } 462 } 463 464 if (fep->bufdesc_ex) { 465 if (fep->quirks & FEC_QUIRK_HAS_AVB) 466 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 467 if (skb->ip_summed == CHECKSUM_PARTIAL) 468 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 469 470 ebdp->cbd_bdu = 0; 471 ebdp->cbd_esc = cpu_to_fec32(estatus); 472 } 473 474 bufaddr = skb_frag_address(this_frag); 475 476 index = fec_enet_get_bd_index(bdp, &txq->bd); 477 if (((unsigned long) bufaddr) & fep->tx_align || 478 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 479 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 480 bufaddr = txq->tx_bounce[index]; 481 482 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 483 swap_buffer(bufaddr, frag_len); 484 } 485 486 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 487 DMA_TO_DEVICE); 488 if (dma_mapping_error(&fep->pdev->dev, addr)) { 489 if (net_ratelimit()) 490 netdev_err(ndev, "Tx DMA memory map failed\n"); 491 goto dma_mapping_error; 492 } 493 494 bdp->cbd_bufaddr = cpu_to_fec32(addr); 495 bdp->cbd_datlen = cpu_to_fec16(frag_len); 496 /* Make sure the updates to rest of the descriptor are 497 * performed before transferring ownership. 498 */ 499 wmb(); 500 bdp->cbd_sc = cpu_to_fec16(status); 501 } 502 503 return bdp; 504 dma_mapping_error: 505 bdp = txq->bd.cur; 506 for (i = 0; i < frag; i++) { 507 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 508 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 509 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 510 } 511 return ERR_PTR(-ENOMEM); 512 } 513 514 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 515 struct sk_buff *skb, struct net_device *ndev) 516 { 517 struct fec_enet_private *fep = netdev_priv(ndev); 518 int nr_frags = skb_shinfo(skb)->nr_frags; 519 struct bufdesc *bdp, *last_bdp; 520 void *bufaddr; 521 dma_addr_t addr; 522 unsigned short status; 523 unsigned short buflen; 524 unsigned int estatus = 0; 525 unsigned int index; 526 int entries_free; 527 528 entries_free = fec_enet_get_free_txdesc_num(txq); 529 if (entries_free < MAX_SKB_FRAGS + 1) { 530 dev_kfree_skb_any(skb); 531 if (net_ratelimit()) 532 netdev_err(ndev, "NOT enough BD for SG!\n"); 533 return NETDEV_TX_OK; 534 } 535 536 /* Protocol checksum off-load for TCP and UDP. */ 537 if (fec_enet_clear_csum(skb, ndev)) { 538 dev_kfree_skb_any(skb); 539 return NETDEV_TX_OK; 540 } 541 542 /* Fill in a Tx ring entry */ 543 bdp = txq->bd.cur; 544 last_bdp = bdp; 545 status = fec16_to_cpu(bdp->cbd_sc); 546 status &= ~BD_ENET_TX_STATS; 547 548 /* Set buffer length and buffer pointer */ 549 bufaddr = skb->data; 550 buflen = skb_headlen(skb); 551 552 index = fec_enet_get_bd_index(bdp, &txq->bd); 553 if (((unsigned long) bufaddr) & fep->tx_align || 554 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 555 memcpy(txq->tx_bounce[index], skb->data, buflen); 556 bufaddr = txq->tx_bounce[index]; 557 558 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 559 swap_buffer(bufaddr, buflen); 560 } 561 562 /* Push the data cache so the CPM does not get stale memory data. */ 563 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 564 if (dma_mapping_error(&fep->pdev->dev, addr)) { 565 dev_kfree_skb_any(skb); 566 if (net_ratelimit()) 567 netdev_err(ndev, "Tx DMA memory map failed\n"); 568 return NETDEV_TX_OK; 569 } 570 571 if (nr_frags) { 572 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 573 if (IS_ERR(last_bdp)) { 574 dma_unmap_single(&fep->pdev->dev, addr, 575 buflen, DMA_TO_DEVICE); 576 dev_kfree_skb_any(skb); 577 return NETDEV_TX_OK; 578 } 579 } else { 580 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 581 if (fep->bufdesc_ex) { 582 estatus = BD_ENET_TX_INT; 583 if (unlikely(skb_shinfo(skb)->tx_flags & 584 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 585 estatus |= BD_ENET_TX_TS; 586 } 587 } 588 bdp->cbd_bufaddr = cpu_to_fec32(addr); 589 bdp->cbd_datlen = cpu_to_fec16(buflen); 590 591 if (fep->bufdesc_ex) { 592 593 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 594 595 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 596 fep->hwts_tx_en)) 597 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 598 599 if (fep->quirks & FEC_QUIRK_HAS_AVB) 600 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 601 602 if (skb->ip_summed == CHECKSUM_PARTIAL) 603 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 604 605 ebdp->cbd_bdu = 0; 606 ebdp->cbd_esc = cpu_to_fec32(estatus); 607 } 608 609 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 610 /* Save skb pointer */ 611 txq->tx_skbuff[index] = skb; 612 613 /* Make sure the updates to rest of the descriptor are performed before 614 * transferring ownership. 615 */ 616 wmb(); 617 618 /* Send it on its way. Tell FEC it's ready, interrupt when done, 619 * it's the last BD of the frame, and to put the CRC on the end. 620 */ 621 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 622 bdp->cbd_sc = cpu_to_fec16(status); 623 624 /* If this was the last BD in the ring, start at the beginning again. */ 625 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 626 627 skb_tx_timestamp(skb); 628 629 /* Make sure the update to bdp and tx_skbuff are performed before 630 * txq->bd.cur. 631 */ 632 wmb(); 633 txq->bd.cur = bdp; 634 635 /* Trigger transmission start */ 636 writel(0, txq->bd.reg_desc_active); 637 638 return 0; 639 } 640 641 static int 642 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 643 struct net_device *ndev, 644 struct bufdesc *bdp, int index, char *data, 645 int size, bool last_tcp, bool is_last) 646 { 647 struct fec_enet_private *fep = netdev_priv(ndev); 648 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 649 unsigned short status; 650 unsigned int estatus = 0; 651 dma_addr_t addr; 652 653 status = fec16_to_cpu(bdp->cbd_sc); 654 status &= ~BD_ENET_TX_STATS; 655 656 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 657 658 if (((unsigned long) data) & fep->tx_align || 659 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 660 memcpy(txq->tx_bounce[index], data, size); 661 data = txq->tx_bounce[index]; 662 663 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 664 swap_buffer(data, size); 665 } 666 667 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 668 if (dma_mapping_error(&fep->pdev->dev, addr)) { 669 dev_kfree_skb_any(skb); 670 if (net_ratelimit()) 671 netdev_err(ndev, "Tx DMA memory map failed\n"); 672 return NETDEV_TX_BUSY; 673 } 674 675 bdp->cbd_datlen = cpu_to_fec16(size); 676 bdp->cbd_bufaddr = cpu_to_fec32(addr); 677 678 if (fep->bufdesc_ex) { 679 if (fep->quirks & FEC_QUIRK_HAS_AVB) 680 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 681 if (skb->ip_summed == CHECKSUM_PARTIAL) 682 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 683 ebdp->cbd_bdu = 0; 684 ebdp->cbd_esc = cpu_to_fec32(estatus); 685 } 686 687 /* Handle the last BD specially */ 688 if (last_tcp) 689 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 690 if (is_last) { 691 status |= BD_ENET_TX_INTR; 692 if (fep->bufdesc_ex) 693 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 694 } 695 696 bdp->cbd_sc = cpu_to_fec16(status); 697 698 return 0; 699 } 700 701 static int 702 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 703 struct sk_buff *skb, struct net_device *ndev, 704 struct bufdesc *bdp, int index) 705 { 706 struct fec_enet_private *fep = netdev_priv(ndev); 707 int hdr_len = skb_tcp_all_headers(skb); 708 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 709 void *bufaddr; 710 unsigned long dmabuf; 711 unsigned short status; 712 unsigned int estatus = 0; 713 714 status = fec16_to_cpu(bdp->cbd_sc); 715 status &= ~BD_ENET_TX_STATS; 716 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 717 718 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 719 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 720 if (((unsigned long)bufaddr) & fep->tx_align || 721 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 722 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 723 bufaddr = txq->tx_bounce[index]; 724 725 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 726 swap_buffer(bufaddr, hdr_len); 727 728 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 729 hdr_len, DMA_TO_DEVICE); 730 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 731 dev_kfree_skb_any(skb); 732 if (net_ratelimit()) 733 netdev_err(ndev, "Tx DMA memory map failed\n"); 734 return NETDEV_TX_BUSY; 735 } 736 } 737 738 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 739 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 740 741 if (fep->bufdesc_ex) { 742 if (fep->quirks & FEC_QUIRK_HAS_AVB) 743 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 744 if (skb->ip_summed == CHECKSUM_PARTIAL) 745 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 746 ebdp->cbd_bdu = 0; 747 ebdp->cbd_esc = cpu_to_fec32(estatus); 748 } 749 750 bdp->cbd_sc = cpu_to_fec16(status); 751 752 return 0; 753 } 754 755 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 756 struct sk_buff *skb, 757 struct net_device *ndev) 758 { 759 struct fec_enet_private *fep = netdev_priv(ndev); 760 int hdr_len, total_len, data_left; 761 struct bufdesc *bdp = txq->bd.cur; 762 struct tso_t tso; 763 unsigned int index = 0; 764 int ret; 765 766 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 767 dev_kfree_skb_any(skb); 768 if (net_ratelimit()) 769 netdev_err(ndev, "NOT enough BD for TSO!\n"); 770 return NETDEV_TX_OK; 771 } 772 773 /* Protocol checksum off-load for TCP and UDP. */ 774 if (fec_enet_clear_csum(skb, ndev)) { 775 dev_kfree_skb_any(skb); 776 return NETDEV_TX_OK; 777 } 778 779 /* Initialize the TSO handler, and prepare the first payload */ 780 hdr_len = tso_start(skb, &tso); 781 782 total_len = skb->len - hdr_len; 783 while (total_len > 0) { 784 char *hdr; 785 786 index = fec_enet_get_bd_index(bdp, &txq->bd); 787 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 788 total_len -= data_left; 789 790 /* prepare packet headers: MAC + IP + TCP */ 791 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 792 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 793 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 794 if (ret) 795 goto err_release; 796 797 while (data_left > 0) { 798 int size; 799 800 size = min_t(int, tso.size, data_left); 801 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 802 index = fec_enet_get_bd_index(bdp, &txq->bd); 803 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 804 bdp, index, 805 tso.data, size, 806 size == data_left, 807 total_len == 0); 808 if (ret) 809 goto err_release; 810 811 data_left -= size; 812 tso_build_data(skb, &tso, size); 813 } 814 815 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 816 } 817 818 /* Save skb pointer */ 819 txq->tx_skbuff[index] = skb; 820 821 skb_tx_timestamp(skb); 822 txq->bd.cur = bdp; 823 824 /* Trigger transmission start */ 825 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 826 !readl(txq->bd.reg_desc_active) || 827 !readl(txq->bd.reg_desc_active) || 828 !readl(txq->bd.reg_desc_active) || 829 !readl(txq->bd.reg_desc_active)) 830 writel(0, txq->bd.reg_desc_active); 831 832 return 0; 833 834 err_release: 835 /* TODO: Release all used data descriptors for TSO */ 836 return ret; 837 } 838 839 static netdev_tx_t 840 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 841 { 842 struct fec_enet_private *fep = netdev_priv(ndev); 843 int entries_free; 844 unsigned short queue; 845 struct fec_enet_priv_tx_q *txq; 846 struct netdev_queue *nq; 847 int ret; 848 849 queue = skb_get_queue_mapping(skb); 850 txq = fep->tx_queue[queue]; 851 nq = netdev_get_tx_queue(ndev, queue); 852 853 if (skb_is_gso(skb)) 854 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 855 else 856 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 857 if (ret) 858 return ret; 859 860 entries_free = fec_enet_get_free_txdesc_num(txq); 861 if (entries_free <= txq->tx_stop_threshold) 862 netif_tx_stop_queue(nq); 863 864 return NETDEV_TX_OK; 865 } 866 867 /* Init RX & TX buffer descriptors 868 */ 869 static void fec_enet_bd_init(struct net_device *dev) 870 { 871 struct fec_enet_private *fep = netdev_priv(dev); 872 struct fec_enet_priv_tx_q *txq; 873 struct fec_enet_priv_rx_q *rxq; 874 struct bufdesc *bdp; 875 unsigned int i; 876 unsigned int q; 877 878 for (q = 0; q < fep->num_rx_queues; q++) { 879 /* Initialize the receive buffer descriptors. */ 880 rxq = fep->rx_queue[q]; 881 bdp = rxq->bd.base; 882 883 for (i = 0; i < rxq->bd.ring_size; i++) { 884 885 /* Initialize the BD for every fragment in the page. */ 886 if (bdp->cbd_bufaddr) 887 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 888 else 889 bdp->cbd_sc = cpu_to_fec16(0); 890 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 891 } 892 893 /* Set the last buffer to wrap */ 894 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 895 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 896 897 rxq->bd.cur = rxq->bd.base; 898 } 899 900 for (q = 0; q < fep->num_tx_queues; q++) { 901 /* ...and the same for transmit */ 902 txq = fep->tx_queue[q]; 903 bdp = txq->bd.base; 904 txq->bd.cur = bdp; 905 906 for (i = 0; i < txq->bd.ring_size; i++) { 907 /* Initialize the BD for every fragment in the page. */ 908 bdp->cbd_sc = cpu_to_fec16(0); 909 if (bdp->cbd_bufaddr && 910 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 911 dma_unmap_single(&fep->pdev->dev, 912 fec32_to_cpu(bdp->cbd_bufaddr), 913 fec16_to_cpu(bdp->cbd_datlen), 914 DMA_TO_DEVICE); 915 if (txq->tx_skbuff[i]) { 916 dev_kfree_skb_any(txq->tx_skbuff[i]); 917 txq->tx_skbuff[i] = NULL; 918 } 919 bdp->cbd_bufaddr = cpu_to_fec32(0); 920 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 921 } 922 923 /* Set the last buffer to wrap */ 924 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 925 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 926 txq->dirty_tx = bdp; 927 } 928 } 929 930 static void fec_enet_active_rxring(struct net_device *ndev) 931 { 932 struct fec_enet_private *fep = netdev_priv(ndev); 933 int i; 934 935 for (i = 0; i < fep->num_rx_queues; i++) 936 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 937 } 938 939 static void fec_enet_enable_ring(struct net_device *ndev) 940 { 941 struct fec_enet_private *fep = netdev_priv(ndev); 942 struct fec_enet_priv_tx_q *txq; 943 struct fec_enet_priv_rx_q *rxq; 944 int i; 945 946 for (i = 0; i < fep->num_rx_queues; i++) { 947 rxq = fep->rx_queue[i]; 948 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 949 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 950 951 /* enable DMA1/2 */ 952 if (i) 953 writel(RCMR_MATCHEN | RCMR_CMP(i), 954 fep->hwp + FEC_RCMR(i)); 955 } 956 957 for (i = 0; i < fep->num_tx_queues; i++) { 958 txq = fep->tx_queue[i]; 959 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 960 961 /* enable DMA1/2 */ 962 if (i) 963 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 964 fep->hwp + FEC_DMA_CFG(i)); 965 } 966 } 967 968 static void fec_enet_reset_skb(struct net_device *ndev) 969 { 970 struct fec_enet_private *fep = netdev_priv(ndev); 971 struct fec_enet_priv_tx_q *txq; 972 int i, j; 973 974 for (i = 0; i < fep->num_tx_queues; i++) { 975 txq = fep->tx_queue[i]; 976 977 for (j = 0; j < txq->bd.ring_size; j++) { 978 if (txq->tx_skbuff[j]) { 979 dev_kfree_skb_any(txq->tx_skbuff[j]); 980 txq->tx_skbuff[j] = NULL; 981 } 982 } 983 } 984 } 985 986 /* 987 * This function is called to start or restart the FEC during a link 988 * change, transmit timeout, or to reconfigure the FEC. The network 989 * packet processing for this device must be stopped before this call. 990 */ 991 static void 992 fec_restart(struct net_device *ndev) 993 { 994 struct fec_enet_private *fep = netdev_priv(ndev); 995 u32 temp_mac[2]; 996 u32 rcntl = OPT_FRAME_SIZE | 0x04; 997 u32 ecntl = 0x2; /* ETHEREN */ 998 999 /* Whack a reset. We should wait for this. 1000 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1001 * instead of reset MAC itself. 1002 */ 1003 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 1004 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 1005 writel(0, fep->hwp + FEC_ECNTRL); 1006 } else { 1007 writel(1, fep->hwp + FEC_ECNTRL); 1008 udelay(10); 1009 } 1010 1011 /* 1012 * enet-mac reset will reset mac address registers too, 1013 * so need to reconfigure it. 1014 */ 1015 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 1016 writel((__force u32)cpu_to_be32(temp_mac[0]), 1017 fep->hwp + FEC_ADDR_LOW); 1018 writel((__force u32)cpu_to_be32(temp_mac[1]), 1019 fep->hwp + FEC_ADDR_HIGH); 1020 1021 /* Clear any outstanding interrupt, except MDIO. */ 1022 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1023 1024 fec_enet_bd_init(ndev); 1025 1026 fec_enet_enable_ring(ndev); 1027 1028 /* Reset tx SKB buffers. */ 1029 fec_enet_reset_skb(ndev); 1030 1031 /* Enable MII mode */ 1032 if (fep->full_duplex == DUPLEX_FULL) { 1033 /* FD enable */ 1034 writel(0x04, fep->hwp + FEC_X_CNTRL); 1035 } else { 1036 /* No Rcv on Xmit */ 1037 rcntl |= 0x02; 1038 writel(0x0, fep->hwp + FEC_X_CNTRL); 1039 } 1040 1041 /* Set MII speed */ 1042 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1043 1044 #if !defined(CONFIG_M5272) 1045 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1046 u32 val = readl(fep->hwp + FEC_RACC); 1047 1048 /* align IP header */ 1049 val |= FEC_RACC_SHIFT16; 1050 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1051 /* set RX checksum */ 1052 val |= FEC_RACC_OPTIONS; 1053 else 1054 val &= ~FEC_RACC_OPTIONS; 1055 writel(val, fep->hwp + FEC_RACC); 1056 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1057 } 1058 #endif 1059 1060 /* 1061 * The phy interface and speed need to get configured 1062 * differently on enet-mac. 1063 */ 1064 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1065 /* Enable flow control and length check */ 1066 rcntl |= 0x40000000 | 0x00000020; 1067 1068 /* RGMII, RMII or MII */ 1069 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1070 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1071 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1072 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1073 rcntl |= (1 << 6); 1074 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1075 rcntl |= (1 << 8); 1076 else 1077 rcntl &= ~(1 << 8); 1078 1079 /* 1G, 100M or 10M */ 1080 if (ndev->phydev) { 1081 if (ndev->phydev->speed == SPEED_1000) 1082 ecntl |= (1 << 5); 1083 else if (ndev->phydev->speed == SPEED_100) 1084 rcntl &= ~(1 << 9); 1085 else 1086 rcntl |= (1 << 9); 1087 } 1088 } else { 1089 #ifdef FEC_MIIGSK_ENR 1090 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1091 u32 cfgr; 1092 /* disable the gasket and wait */ 1093 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1094 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1095 udelay(1); 1096 1097 /* 1098 * configure the gasket: 1099 * RMII, 50 MHz, no loopback, no echo 1100 * MII, 25 MHz, no loopback, no echo 1101 */ 1102 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1103 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1104 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1105 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1106 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1107 1108 /* re-enable the gasket */ 1109 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1110 } 1111 #endif 1112 } 1113 1114 #if !defined(CONFIG_M5272) 1115 /* enable pause frame*/ 1116 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1117 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1118 ndev->phydev && ndev->phydev->pause)) { 1119 rcntl |= FEC_ENET_FCE; 1120 1121 /* set FIFO threshold parameter to reduce overrun */ 1122 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1123 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1124 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1125 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1126 1127 /* OPD */ 1128 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1129 } else { 1130 rcntl &= ~FEC_ENET_FCE; 1131 } 1132 #endif /* !defined(CONFIG_M5272) */ 1133 1134 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1135 1136 /* Setup multicast filter. */ 1137 set_multicast_list(ndev); 1138 #ifndef CONFIG_M5272 1139 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1140 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1141 #endif 1142 1143 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1144 /* enable ENET endian swap */ 1145 ecntl |= (1 << 8); 1146 /* enable ENET store and forward mode */ 1147 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1148 } 1149 1150 if (fep->bufdesc_ex) 1151 ecntl |= (1 << 4); 1152 1153 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1154 fep->rgmii_txc_dly) 1155 ecntl |= FEC_ENET_TXC_DLY; 1156 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1157 fep->rgmii_rxc_dly) 1158 ecntl |= FEC_ENET_RXC_DLY; 1159 1160 #ifndef CONFIG_M5272 1161 /* Enable the MIB statistic event counters */ 1162 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1163 #endif 1164 1165 /* And last, enable the transmit and receive processing */ 1166 writel(ecntl, fep->hwp + FEC_ECNTRL); 1167 fec_enet_active_rxring(ndev); 1168 1169 if (fep->bufdesc_ex) 1170 fec_ptp_start_cyclecounter(ndev); 1171 1172 /* Enable interrupts we wish to service */ 1173 if (fep->link) 1174 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1175 else 1176 writel(0, fep->hwp + FEC_IMASK); 1177 1178 /* Init the interrupt coalescing */ 1179 fec_enet_itr_coal_init(ndev); 1180 1181 } 1182 1183 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep) 1184 { 1185 if (!(of_machine_is_compatible("fsl,imx8qm") || 1186 of_machine_is_compatible("fsl,imx8qxp") || 1187 of_machine_is_compatible("fsl,imx8dxl"))) 1188 return 0; 1189 1190 return imx_scu_get_handle(&fep->ipc_handle); 1191 } 1192 1193 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled) 1194 { 1195 struct device_node *np = fep->pdev->dev.of_node; 1196 u32 rsrc_id, val; 1197 int idx; 1198 1199 if (!np || !fep->ipc_handle) 1200 return; 1201 1202 idx = of_alias_get_id(np, "ethernet"); 1203 if (idx < 0) 1204 idx = 0; 1205 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0; 1206 1207 val = enabled ? 1 : 0; 1208 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val); 1209 } 1210 1211 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1212 { 1213 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1214 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1215 1216 if (stop_gpr->gpr) { 1217 if (enabled) 1218 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1219 BIT(stop_gpr->bit), 1220 BIT(stop_gpr->bit)); 1221 else 1222 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1223 BIT(stop_gpr->bit), 0); 1224 } else if (pdata && pdata->sleep_mode_enable) { 1225 pdata->sleep_mode_enable(enabled); 1226 } else { 1227 fec_enet_ipg_stop_set(fep, enabled); 1228 } 1229 } 1230 1231 static void fec_irqs_disable(struct net_device *ndev) 1232 { 1233 struct fec_enet_private *fep = netdev_priv(ndev); 1234 1235 writel(0, fep->hwp + FEC_IMASK); 1236 } 1237 1238 static void fec_irqs_disable_except_wakeup(struct net_device *ndev) 1239 { 1240 struct fec_enet_private *fep = netdev_priv(ndev); 1241 1242 writel(0, fep->hwp + FEC_IMASK); 1243 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1244 } 1245 1246 static void 1247 fec_stop(struct net_device *ndev) 1248 { 1249 struct fec_enet_private *fep = netdev_priv(ndev); 1250 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1251 u32 val; 1252 1253 /* We cannot expect a graceful transmit stop without link !!! */ 1254 if (fep->link) { 1255 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1256 udelay(10); 1257 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1258 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1259 } 1260 1261 /* Whack a reset. We should wait for this. 1262 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1263 * instead of reset MAC itself. 1264 */ 1265 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1266 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 1267 writel(0, fep->hwp + FEC_ECNTRL); 1268 } else { 1269 writel(1, fep->hwp + FEC_ECNTRL); 1270 udelay(10); 1271 } 1272 } else { 1273 val = readl(fep->hwp + FEC_ECNTRL); 1274 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1275 writel(val, fep->hwp + FEC_ECNTRL); 1276 } 1277 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1278 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1279 1280 /* We have to keep ENET enabled to have MII interrupt stay working */ 1281 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1282 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1283 writel(2, fep->hwp + FEC_ECNTRL); 1284 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1285 } 1286 } 1287 1288 1289 static void 1290 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1291 { 1292 struct fec_enet_private *fep = netdev_priv(ndev); 1293 1294 fec_dump(ndev); 1295 1296 ndev->stats.tx_errors++; 1297 1298 schedule_work(&fep->tx_timeout_work); 1299 } 1300 1301 static void fec_enet_timeout_work(struct work_struct *work) 1302 { 1303 struct fec_enet_private *fep = 1304 container_of(work, struct fec_enet_private, tx_timeout_work); 1305 struct net_device *ndev = fep->netdev; 1306 1307 rtnl_lock(); 1308 if (netif_device_present(ndev) || netif_running(ndev)) { 1309 napi_disable(&fep->napi); 1310 netif_tx_lock_bh(ndev); 1311 fec_restart(ndev); 1312 netif_tx_wake_all_queues(ndev); 1313 netif_tx_unlock_bh(ndev); 1314 napi_enable(&fep->napi); 1315 } 1316 rtnl_unlock(); 1317 } 1318 1319 static void 1320 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1321 struct skb_shared_hwtstamps *hwtstamps) 1322 { 1323 unsigned long flags; 1324 u64 ns; 1325 1326 spin_lock_irqsave(&fep->tmreg_lock, flags); 1327 ns = timecounter_cyc2time(&fep->tc, ts); 1328 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1329 1330 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1331 hwtstamps->hwtstamp = ns_to_ktime(ns); 1332 } 1333 1334 static void 1335 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1336 { 1337 struct fec_enet_private *fep; 1338 struct bufdesc *bdp; 1339 unsigned short status; 1340 struct sk_buff *skb; 1341 struct fec_enet_priv_tx_q *txq; 1342 struct netdev_queue *nq; 1343 int index = 0; 1344 int entries_free; 1345 1346 fep = netdev_priv(ndev); 1347 1348 txq = fep->tx_queue[queue_id]; 1349 /* get next bdp of dirty_tx */ 1350 nq = netdev_get_tx_queue(ndev, queue_id); 1351 bdp = txq->dirty_tx; 1352 1353 /* get next bdp of dirty_tx */ 1354 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1355 1356 while (bdp != READ_ONCE(txq->bd.cur)) { 1357 /* Order the load of bd.cur and cbd_sc */ 1358 rmb(); 1359 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1360 if (status & BD_ENET_TX_READY) 1361 break; 1362 1363 index = fec_enet_get_bd_index(bdp, &txq->bd); 1364 1365 skb = txq->tx_skbuff[index]; 1366 txq->tx_skbuff[index] = NULL; 1367 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1368 dma_unmap_single(&fep->pdev->dev, 1369 fec32_to_cpu(bdp->cbd_bufaddr), 1370 fec16_to_cpu(bdp->cbd_datlen), 1371 DMA_TO_DEVICE); 1372 bdp->cbd_bufaddr = cpu_to_fec32(0); 1373 if (!skb) 1374 goto skb_done; 1375 1376 /* Check for errors. */ 1377 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1378 BD_ENET_TX_RL | BD_ENET_TX_UN | 1379 BD_ENET_TX_CSL)) { 1380 ndev->stats.tx_errors++; 1381 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1382 ndev->stats.tx_heartbeat_errors++; 1383 if (status & BD_ENET_TX_LC) /* Late collision */ 1384 ndev->stats.tx_window_errors++; 1385 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1386 ndev->stats.tx_aborted_errors++; 1387 if (status & BD_ENET_TX_UN) /* Underrun */ 1388 ndev->stats.tx_fifo_errors++; 1389 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1390 ndev->stats.tx_carrier_errors++; 1391 } else { 1392 ndev->stats.tx_packets++; 1393 ndev->stats.tx_bytes += skb->len; 1394 } 1395 1396 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1397 * are to time stamp the packet, so we still need to check time 1398 * stamping enabled flag. 1399 */ 1400 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1401 fep->hwts_tx_en) && 1402 fep->bufdesc_ex) { 1403 struct skb_shared_hwtstamps shhwtstamps; 1404 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1405 1406 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1407 skb_tstamp_tx(skb, &shhwtstamps); 1408 } 1409 1410 /* Deferred means some collisions occurred during transmit, 1411 * but we eventually sent the packet OK. 1412 */ 1413 if (status & BD_ENET_TX_DEF) 1414 ndev->stats.collisions++; 1415 1416 /* Free the sk buffer associated with this last transmit */ 1417 dev_kfree_skb_any(skb); 1418 skb_done: 1419 /* Make sure the update to bdp and tx_skbuff are performed 1420 * before dirty_tx 1421 */ 1422 wmb(); 1423 txq->dirty_tx = bdp; 1424 1425 /* Update pointer to next buffer descriptor to be transmitted */ 1426 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1427 1428 /* Since we have freed up a buffer, the ring is no longer full 1429 */ 1430 if (netif_tx_queue_stopped(nq)) { 1431 entries_free = fec_enet_get_free_txdesc_num(txq); 1432 if (entries_free >= txq->tx_wake_threshold) 1433 netif_tx_wake_queue(nq); 1434 } 1435 } 1436 1437 /* ERR006358: Keep the transmitter going */ 1438 if (bdp != txq->bd.cur && 1439 readl(txq->bd.reg_desc_active) == 0) 1440 writel(0, txq->bd.reg_desc_active); 1441 } 1442 1443 static void fec_enet_tx(struct net_device *ndev) 1444 { 1445 struct fec_enet_private *fep = netdev_priv(ndev); 1446 int i; 1447 1448 /* Make sure that AVB queues are processed first. */ 1449 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1450 fec_enet_tx_queue(ndev, i); 1451 } 1452 1453 static int 1454 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1455 { 1456 struct fec_enet_private *fep = netdev_priv(ndev); 1457 int off; 1458 1459 off = ((unsigned long)skb->data) & fep->rx_align; 1460 if (off) 1461 skb_reserve(skb, fep->rx_align + 1 - off); 1462 1463 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1464 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1465 if (net_ratelimit()) 1466 netdev_err(ndev, "Rx DMA memory map failed\n"); 1467 return -ENOMEM; 1468 } 1469 1470 return 0; 1471 } 1472 1473 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1474 struct bufdesc *bdp, u32 length, bool swap) 1475 { 1476 struct fec_enet_private *fep = netdev_priv(ndev); 1477 struct sk_buff *new_skb; 1478 1479 if (length > fep->rx_copybreak) 1480 return false; 1481 1482 new_skb = netdev_alloc_skb(ndev, length); 1483 if (!new_skb) 1484 return false; 1485 1486 dma_sync_single_for_cpu(&fep->pdev->dev, 1487 fec32_to_cpu(bdp->cbd_bufaddr), 1488 FEC_ENET_RX_FRSIZE - fep->rx_align, 1489 DMA_FROM_DEVICE); 1490 if (!swap) 1491 memcpy(new_skb->data, (*skb)->data, length); 1492 else 1493 swap_buffer2(new_skb->data, (*skb)->data, length); 1494 *skb = new_skb; 1495 1496 return true; 1497 } 1498 1499 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1500 * When we update through the ring, if the next incoming buffer has 1501 * not been given to the system, we just set the empty indicator, 1502 * effectively tossing the packet. 1503 */ 1504 static int 1505 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1506 { 1507 struct fec_enet_private *fep = netdev_priv(ndev); 1508 struct fec_enet_priv_rx_q *rxq; 1509 struct bufdesc *bdp; 1510 unsigned short status; 1511 struct sk_buff *skb_new = NULL; 1512 struct sk_buff *skb; 1513 ushort pkt_len; 1514 __u8 *data; 1515 int pkt_received = 0; 1516 struct bufdesc_ex *ebdp = NULL; 1517 bool vlan_packet_rcvd = false; 1518 u16 vlan_tag; 1519 int index = 0; 1520 bool is_copybreak; 1521 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1522 1523 #ifdef CONFIG_M532x 1524 flush_cache_all(); 1525 #endif 1526 rxq = fep->rx_queue[queue_id]; 1527 1528 /* First, grab all of the stats for the incoming packet. 1529 * These get messed up if we get called due to a busy condition. 1530 */ 1531 bdp = rxq->bd.cur; 1532 1533 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1534 1535 if (pkt_received >= budget) 1536 break; 1537 pkt_received++; 1538 1539 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); 1540 1541 /* Check for errors. */ 1542 status ^= BD_ENET_RX_LAST; 1543 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1544 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1545 BD_ENET_RX_CL)) { 1546 ndev->stats.rx_errors++; 1547 if (status & BD_ENET_RX_OV) { 1548 /* FIFO overrun */ 1549 ndev->stats.rx_fifo_errors++; 1550 goto rx_processing_done; 1551 } 1552 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1553 | BD_ENET_RX_LAST)) { 1554 /* Frame too long or too short. */ 1555 ndev->stats.rx_length_errors++; 1556 if (status & BD_ENET_RX_LAST) 1557 netdev_err(ndev, "rcv is not +last\n"); 1558 } 1559 if (status & BD_ENET_RX_CR) /* CRC Error */ 1560 ndev->stats.rx_crc_errors++; 1561 /* Report late collisions as a frame error. */ 1562 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1563 ndev->stats.rx_frame_errors++; 1564 goto rx_processing_done; 1565 } 1566 1567 /* Process the incoming frame. */ 1568 ndev->stats.rx_packets++; 1569 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1570 ndev->stats.rx_bytes += pkt_len; 1571 1572 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1573 skb = rxq->rx_skbuff[index]; 1574 1575 /* The packet length includes FCS, but we don't want to 1576 * include that when passing upstream as it messes up 1577 * bridging applications. 1578 */ 1579 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1580 need_swap); 1581 if (!is_copybreak) { 1582 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1583 if (unlikely(!skb_new)) { 1584 ndev->stats.rx_dropped++; 1585 goto rx_processing_done; 1586 } 1587 dma_unmap_single(&fep->pdev->dev, 1588 fec32_to_cpu(bdp->cbd_bufaddr), 1589 FEC_ENET_RX_FRSIZE - fep->rx_align, 1590 DMA_FROM_DEVICE); 1591 } 1592 1593 prefetch(skb->data - NET_IP_ALIGN); 1594 skb_put(skb, pkt_len - 4); 1595 data = skb->data; 1596 1597 if (!is_copybreak && need_swap) 1598 swap_buffer(data, pkt_len); 1599 1600 #if !defined(CONFIG_M5272) 1601 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1602 data = skb_pull_inline(skb, 2); 1603 #endif 1604 1605 /* Extract the enhanced buffer descriptor */ 1606 ebdp = NULL; 1607 if (fep->bufdesc_ex) 1608 ebdp = (struct bufdesc_ex *)bdp; 1609 1610 /* If this is a VLAN packet remove the VLAN Tag */ 1611 vlan_packet_rcvd = false; 1612 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1613 fep->bufdesc_ex && 1614 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1615 /* Push and remove the vlan tag */ 1616 struct vlan_hdr *vlan_header = 1617 (struct vlan_hdr *) (data + ETH_HLEN); 1618 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1619 1620 vlan_packet_rcvd = true; 1621 1622 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1623 skb_pull(skb, VLAN_HLEN); 1624 } 1625 1626 skb->protocol = eth_type_trans(skb, ndev); 1627 1628 /* Get receive timestamp from the skb */ 1629 if (fep->hwts_rx_en && fep->bufdesc_ex) 1630 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1631 skb_hwtstamps(skb)); 1632 1633 if (fep->bufdesc_ex && 1634 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1635 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1636 /* don't check it */ 1637 skb->ip_summed = CHECKSUM_UNNECESSARY; 1638 } else { 1639 skb_checksum_none_assert(skb); 1640 } 1641 } 1642 1643 /* Handle received VLAN packets */ 1644 if (vlan_packet_rcvd) 1645 __vlan_hwaccel_put_tag(skb, 1646 htons(ETH_P_8021Q), 1647 vlan_tag); 1648 1649 skb_record_rx_queue(skb, queue_id); 1650 napi_gro_receive(&fep->napi, skb); 1651 1652 if (is_copybreak) { 1653 dma_sync_single_for_device(&fep->pdev->dev, 1654 fec32_to_cpu(bdp->cbd_bufaddr), 1655 FEC_ENET_RX_FRSIZE - fep->rx_align, 1656 DMA_FROM_DEVICE); 1657 } else { 1658 rxq->rx_skbuff[index] = skb_new; 1659 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1660 } 1661 1662 rx_processing_done: 1663 /* Clear the status flags for this buffer */ 1664 status &= ~BD_ENET_RX_STATS; 1665 1666 /* Mark the buffer empty */ 1667 status |= BD_ENET_RX_EMPTY; 1668 1669 if (fep->bufdesc_ex) { 1670 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1671 1672 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1673 ebdp->cbd_prot = 0; 1674 ebdp->cbd_bdu = 0; 1675 } 1676 /* Make sure the updates to rest of the descriptor are 1677 * performed before transferring ownership. 1678 */ 1679 wmb(); 1680 bdp->cbd_sc = cpu_to_fec16(status); 1681 1682 /* Update BD pointer to next entry */ 1683 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1684 1685 /* Doing this here will keep the FEC running while we process 1686 * incoming frames. On a heavily loaded network, we should be 1687 * able to keep up at the expense of system resources. 1688 */ 1689 writel(0, rxq->bd.reg_desc_active); 1690 } 1691 rxq->bd.cur = bdp; 1692 return pkt_received; 1693 } 1694 1695 static int fec_enet_rx(struct net_device *ndev, int budget) 1696 { 1697 struct fec_enet_private *fep = netdev_priv(ndev); 1698 int i, done = 0; 1699 1700 /* Make sure that AVB queues are processed first. */ 1701 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1702 done += fec_enet_rx_queue(ndev, budget - done, i); 1703 1704 return done; 1705 } 1706 1707 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1708 { 1709 uint int_events; 1710 1711 int_events = readl(fep->hwp + FEC_IEVENT); 1712 1713 /* Don't clear MDIO events, we poll for those */ 1714 int_events &= ~FEC_ENET_MII; 1715 1716 writel(int_events, fep->hwp + FEC_IEVENT); 1717 1718 return int_events != 0; 1719 } 1720 1721 static irqreturn_t 1722 fec_enet_interrupt(int irq, void *dev_id) 1723 { 1724 struct net_device *ndev = dev_id; 1725 struct fec_enet_private *fep = netdev_priv(ndev); 1726 irqreturn_t ret = IRQ_NONE; 1727 1728 if (fec_enet_collect_events(fep) && fep->link) { 1729 ret = IRQ_HANDLED; 1730 1731 if (napi_schedule_prep(&fep->napi)) { 1732 /* Disable interrupts */ 1733 writel(0, fep->hwp + FEC_IMASK); 1734 __napi_schedule(&fep->napi); 1735 } 1736 } 1737 1738 return ret; 1739 } 1740 1741 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1742 { 1743 struct net_device *ndev = napi->dev; 1744 struct fec_enet_private *fep = netdev_priv(ndev); 1745 int done = 0; 1746 1747 do { 1748 done += fec_enet_rx(ndev, budget - done); 1749 fec_enet_tx(ndev); 1750 } while ((done < budget) && fec_enet_collect_events(fep)); 1751 1752 if (done < budget) { 1753 napi_complete_done(napi, done); 1754 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1755 } 1756 1757 return done; 1758 } 1759 1760 /* ------------------------------------------------------------------------- */ 1761 static int fec_get_mac(struct net_device *ndev) 1762 { 1763 struct fec_enet_private *fep = netdev_priv(ndev); 1764 unsigned char *iap, tmpaddr[ETH_ALEN]; 1765 int ret; 1766 1767 /* 1768 * try to get mac address in following order: 1769 * 1770 * 1) module parameter via kernel command line in form 1771 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1772 */ 1773 iap = macaddr; 1774 1775 /* 1776 * 2) from device tree data 1777 */ 1778 if (!is_valid_ether_addr(iap)) { 1779 struct device_node *np = fep->pdev->dev.of_node; 1780 if (np) { 1781 ret = of_get_mac_address(np, tmpaddr); 1782 if (!ret) 1783 iap = tmpaddr; 1784 else if (ret == -EPROBE_DEFER) 1785 return ret; 1786 } 1787 } 1788 1789 /* 1790 * 3) from flash or fuse (via platform data) 1791 */ 1792 if (!is_valid_ether_addr(iap)) { 1793 #ifdef CONFIG_M5272 1794 if (FEC_FLASHMAC) 1795 iap = (unsigned char *)FEC_FLASHMAC; 1796 #else 1797 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1798 1799 if (pdata) 1800 iap = (unsigned char *)&pdata->mac; 1801 #endif 1802 } 1803 1804 /* 1805 * 4) FEC mac registers set by bootloader 1806 */ 1807 if (!is_valid_ether_addr(iap)) { 1808 *((__be32 *) &tmpaddr[0]) = 1809 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1810 *((__be16 *) &tmpaddr[4]) = 1811 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1812 iap = &tmpaddr[0]; 1813 } 1814 1815 /* 1816 * 5) random mac address 1817 */ 1818 if (!is_valid_ether_addr(iap)) { 1819 /* Report it and use a random ethernet address instead */ 1820 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1821 eth_hw_addr_random(ndev); 1822 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1823 ndev->dev_addr); 1824 return 0; 1825 } 1826 1827 /* Adjust MAC if using macaddr */ 1828 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); 1829 1830 return 0; 1831 } 1832 1833 /* ------------------------------------------------------------------------- */ 1834 1835 /* 1836 * Phy section 1837 */ 1838 static void fec_enet_adjust_link(struct net_device *ndev) 1839 { 1840 struct fec_enet_private *fep = netdev_priv(ndev); 1841 struct phy_device *phy_dev = ndev->phydev; 1842 int status_change = 0; 1843 1844 /* 1845 * If the netdev is down, or is going down, we're not interested 1846 * in link state events, so just mark our idea of the link as down 1847 * and ignore the event. 1848 */ 1849 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1850 fep->link = 0; 1851 } else if (phy_dev->link) { 1852 if (!fep->link) { 1853 fep->link = phy_dev->link; 1854 status_change = 1; 1855 } 1856 1857 if (fep->full_duplex != phy_dev->duplex) { 1858 fep->full_duplex = phy_dev->duplex; 1859 status_change = 1; 1860 } 1861 1862 if (phy_dev->speed != fep->speed) { 1863 fep->speed = phy_dev->speed; 1864 status_change = 1; 1865 } 1866 1867 /* if any of the above changed restart the FEC */ 1868 if (status_change) { 1869 napi_disable(&fep->napi); 1870 netif_tx_lock_bh(ndev); 1871 fec_restart(ndev); 1872 netif_tx_wake_all_queues(ndev); 1873 netif_tx_unlock_bh(ndev); 1874 napi_enable(&fep->napi); 1875 } 1876 } else { 1877 if (fep->link) { 1878 napi_disable(&fep->napi); 1879 netif_tx_lock_bh(ndev); 1880 fec_stop(ndev); 1881 netif_tx_unlock_bh(ndev); 1882 napi_enable(&fep->napi); 1883 fep->link = phy_dev->link; 1884 status_change = 1; 1885 } 1886 } 1887 1888 if (status_change) 1889 phy_print_status(phy_dev); 1890 } 1891 1892 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 1893 { 1894 uint ievent; 1895 int ret; 1896 1897 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 1898 ievent & FEC_ENET_MII, 2, 30000); 1899 1900 if (!ret) 1901 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 1902 1903 return ret; 1904 } 1905 1906 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1907 { 1908 struct fec_enet_private *fep = bus->priv; 1909 struct device *dev = &fep->pdev->dev; 1910 int ret = 0, frame_start, frame_addr, frame_op; 1911 bool is_c45 = !!(regnum & MII_ADDR_C45); 1912 1913 ret = pm_runtime_resume_and_get(dev); 1914 if (ret < 0) 1915 return ret; 1916 1917 if (is_c45) { 1918 frame_start = FEC_MMFR_ST_C45; 1919 1920 /* write address */ 1921 frame_addr = (regnum >> 16); 1922 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1923 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1924 FEC_MMFR_TA | (regnum & 0xFFFF), 1925 fep->hwp + FEC_MII_DATA); 1926 1927 /* wait for end of transfer */ 1928 ret = fec_enet_mdio_wait(fep); 1929 if (ret) { 1930 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1931 goto out; 1932 } 1933 1934 frame_op = FEC_MMFR_OP_READ_C45; 1935 1936 } else { 1937 /* C22 read */ 1938 frame_op = FEC_MMFR_OP_READ; 1939 frame_start = FEC_MMFR_ST; 1940 frame_addr = regnum; 1941 } 1942 1943 /* start a read op */ 1944 writel(frame_start | frame_op | 1945 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1946 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1947 1948 /* wait for end of transfer */ 1949 ret = fec_enet_mdio_wait(fep); 1950 if (ret) { 1951 netdev_err(fep->netdev, "MDIO read timeout\n"); 1952 goto out; 1953 } 1954 1955 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1956 1957 out: 1958 pm_runtime_mark_last_busy(dev); 1959 pm_runtime_put_autosuspend(dev); 1960 1961 return ret; 1962 } 1963 1964 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1965 u16 value) 1966 { 1967 struct fec_enet_private *fep = bus->priv; 1968 struct device *dev = &fep->pdev->dev; 1969 int ret, frame_start, frame_addr; 1970 bool is_c45 = !!(regnum & MII_ADDR_C45); 1971 1972 ret = pm_runtime_resume_and_get(dev); 1973 if (ret < 0) 1974 return ret; 1975 1976 if (is_c45) { 1977 frame_start = FEC_MMFR_ST_C45; 1978 1979 /* write address */ 1980 frame_addr = (regnum >> 16); 1981 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1982 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1983 FEC_MMFR_TA | (regnum & 0xFFFF), 1984 fep->hwp + FEC_MII_DATA); 1985 1986 /* wait for end of transfer */ 1987 ret = fec_enet_mdio_wait(fep); 1988 if (ret) { 1989 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1990 goto out; 1991 } 1992 } else { 1993 /* C22 write */ 1994 frame_start = FEC_MMFR_ST; 1995 frame_addr = regnum; 1996 } 1997 1998 /* start a write op */ 1999 writel(frame_start | FEC_MMFR_OP_WRITE | 2000 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2001 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2002 fep->hwp + FEC_MII_DATA); 2003 2004 /* wait for end of transfer */ 2005 ret = fec_enet_mdio_wait(fep); 2006 if (ret) 2007 netdev_err(fep->netdev, "MDIO write timeout\n"); 2008 2009 out: 2010 pm_runtime_mark_last_busy(dev); 2011 pm_runtime_put_autosuspend(dev); 2012 2013 return ret; 2014 } 2015 2016 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 2017 { 2018 struct fec_enet_private *fep = netdev_priv(ndev); 2019 struct phy_device *phy_dev = ndev->phydev; 2020 2021 if (phy_dev) { 2022 phy_reset_after_clk_enable(phy_dev); 2023 } else if (fep->phy_node) { 2024 /* 2025 * If the PHY still is not bound to the MAC, but there is 2026 * OF PHY node and a matching PHY device instance already, 2027 * use the OF PHY node to obtain the PHY device instance, 2028 * and then use that PHY device instance when triggering 2029 * the PHY reset. 2030 */ 2031 phy_dev = of_phy_find_device(fep->phy_node); 2032 phy_reset_after_clk_enable(phy_dev); 2033 put_device(&phy_dev->mdio.dev); 2034 } 2035 } 2036 2037 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 2038 { 2039 struct fec_enet_private *fep = netdev_priv(ndev); 2040 int ret; 2041 2042 if (enable) { 2043 ret = clk_prepare_enable(fep->clk_enet_out); 2044 if (ret) 2045 return ret; 2046 2047 if (fep->clk_ptp) { 2048 mutex_lock(&fep->ptp_clk_mutex); 2049 ret = clk_prepare_enable(fep->clk_ptp); 2050 if (ret) { 2051 mutex_unlock(&fep->ptp_clk_mutex); 2052 goto failed_clk_ptp; 2053 } else { 2054 fep->ptp_clk_on = true; 2055 } 2056 mutex_unlock(&fep->ptp_clk_mutex); 2057 } 2058 2059 ret = clk_prepare_enable(fep->clk_ref); 2060 if (ret) 2061 goto failed_clk_ref; 2062 2063 ret = clk_prepare_enable(fep->clk_2x_txclk); 2064 if (ret) 2065 goto failed_clk_2x_txclk; 2066 2067 fec_enet_phy_reset_after_clk_enable(ndev); 2068 } else { 2069 clk_disable_unprepare(fep->clk_enet_out); 2070 if (fep->clk_ptp) { 2071 mutex_lock(&fep->ptp_clk_mutex); 2072 clk_disable_unprepare(fep->clk_ptp); 2073 fep->ptp_clk_on = false; 2074 mutex_unlock(&fep->ptp_clk_mutex); 2075 } 2076 clk_disable_unprepare(fep->clk_ref); 2077 clk_disable_unprepare(fep->clk_2x_txclk); 2078 } 2079 2080 return 0; 2081 2082 failed_clk_2x_txclk: 2083 if (fep->clk_ref) 2084 clk_disable_unprepare(fep->clk_ref); 2085 failed_clk_ref: 2086 if (fep->clk_ptp) { 2087 mutex_lock(&fep->ptp_clk_mutex); 2088 clk_disable_unprepare(fep->clk_ptp); 2089 fep->ptp_clk_on = false; 2090 mutex_unlock(&fep->ptp_clk_mutex); 2091 } 2092 failed_clk_ptp: 2093 clk_disable_unprepare(fep->clk_enet_out); 2094 2095 return ret; 2096 } 2097 2098 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2099 struct device_node *np) 2100 { 2101 u32 rgmii_tx_delay, rgmii_rx_delay; 2102 2103 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2104 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2105 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2106 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2107 return -EINVAL; 2108 } else if (rgmii_tx_delay == 2000) { 2109 fep->rgmii_txc_dly = true; 2110 } 2111 } 2112 2113 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2114 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2115 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2116 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2117 return -EINVAL; 2118 } else if (rgmii_rx_delay == 2000) { 2119 fep->rgmii_rxc_dly = true; 2120 } 2121 } 2122 2123 return 0; 2124 } 2125 2126 static int fec_enet_mii_probe(struct net_device *ndev) 2127 { 2128 struct fec_enet_private *fep = netdev_priv(ndev); 2129 struct phy_device *phy_dev = NULL; 2130 char mdio_bus_id[MII_BUS_ID_SIZE]; 2131 char phy_name[MII_BUS_ID_SIZE + 3]; 2132 int phy_id; 2133 int dev_id = fep->dev_id; 2134 2135 if (fep->phy_node) { 2136 phy_dev = of_phy_connect(ndev, fep->phy_node, 2137 &fec_enet_adjust_link, 0, 2138 fep->phy_interface); 2139 if (!phy_dev) { 2140 netdev_err(ndev, "Unable to connect to phy\n"); 2141 return -ENODEV; 2142 } 2143 } else { 2144 /* check for attached phy */ 2145 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2146 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2147 continue; 2148 if (dev_id--) 2149 continue; 2150 strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2151 break; 2152 } 2153 2154 if (phy_id >= PHY_MAX_ADDR) { 2155 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2156 strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2157 phy_id = 0; 2158 } 2159 2160 snprintf(phy_name, sizeof(phy_name), 2161 PHY_ID_FMT, mdio_bus_id, phy_id); 2162 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2163 fep->phy_interface); 2164 } 2165 2166 if (IS_ERR(phy_dev)) { 2167 netdev_err(ndev, "could not attach to PHY\n"); 2168 return PTR_ERR(phy_dev); 2169 } 2170 2171 /* mask with MAC supported features */ 2172 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2173 phy_set_max_speed(phy_dev, 1000); 2174 phy_remove_link_mode(phy_dev, 2175 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2176 #if !defined(CONFIG_M5272) 2177 phy_support_sym_pause(phy_dev); 2178 #endif 2179 } 2180 else 2181 phy_set_max_speed(phy_dev, 100); 2182 2183 fep->link = 0; 2184 fep->full_duplex = 0; 2185 2186 phy_dev->mac_managed_pm = 1; 2187 2188 phy_attached_info(phy_dev); 2189 2190 return 0; 2191 } 2192 2193 static int fec_enet_mii_init(struct platform_device *pdev) 2194 { 2195 static struct mii_bus *fec0_mii_bus; 2196 struct net_device *ndev = platform_get_drvdata(pdev); 2197 struct fec_enet_private *fep = netdev_priv(ndev); 2198 bool suppress_preamble = false; 2199 struct device_node *node; 2200 int err = -ENXIO; 2201 u32 mii_speed, holdtime; 2202 u32 bus_freq; 2203 2204 /* 2205 * The i.MX28 dual fec interfaces are not equal. 2206 * Here are the differences: 2207 * 2208 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2209 * - fec0 acts as the 1588 time master while fec1 is slave 2210 * - external phys can only be configured by fec0 2211 * 2212 * That is to say fec1 can not work independently. It only works 2213 * when fec0 is working. The reason behind this design is that the 2214 * second interface is added primarily for Switch mode. 2215 * 2216 * Because of the last point above, both phys are attached on fec0 2217 * mdio interface in board design, and need to be configured by 2218 * fec0 mii_bus. 2219 */ 2220 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2221 /* fec1 uses fec0 mii_bus */ 2222 if (mii_cnt && fec0_mii_bus) { 2223 fep->mii_bus = fec0_mii_bus; 2224 mii_cnt++; 2225 return 0; 2226 } 2227 return -ENOENT; 2228 } 2229 2230 bus_freq = 2500000; /* 2.5MHz by default */ 2231 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2232 if (node) { 2233 of_property_read_u32(node, "clock-frequency", &bus_freq); 2234 suppress_preamble = of_property_read_bool(node, 2235 "suppress-preamble"); 2236 } 2237 2238 /* 2239 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2240 * 2241 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2242 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2243 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2244 * document. 2245 */ 2246 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2247 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2248 mii_speed--; 2249 if (mii_speed > 63) { 2250 dev_err(&pdev->dev, 2251 "fec clock (%lu) too fast to get right mii speed\n", 2252 clk_get_rate(fep->clk_ipg)); 2253 err = -EINVAL; 2254 goto err_out; 2255 } 2256 2257 /* 2258 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2259 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2260 * versions are RAZ there, so just ignore the difference and write the 2261 * register always. 2262 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2263 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2264 * output. 2265 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2266 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2267 * holdtime cannot result in a value greater than 3. 2268 */ 2269 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2270 2271 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2272 2273 if (suppress_preamble) 2274 fep->phy_speed |= BIT(7); 2275 2276 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2277 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2278 * MII event generation condition: 2279 * - writing MSCR: 2280 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2281 * mscr_reg_data_in[7:0] != 0 2282 * - writing MMFR: 2283 * - mscr[7:0]_not_zero 2284 */ 2285 writel(0, fep->hwp + FEC_MII_DATA); 2286 } 2287 2288 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2289 2290 /* Clear any pending transaction complete indication */ 2291 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2292 2293 fep->mii_bus = mdiobus_alloc(); 2294 if (fep->mii_bus == NULL) { 2295 err = -ENOMEM; 2296 goto err_out; 2297 } 2298 2299 fep->mii_bus->name = "fec_enet_mii_bus"; 2300 fep->mii_bus->read = fec_enet_mdio_read; 2301 fep->mii_bus->write = fec_enet_mdio_write; 2302 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2303 pdev->name, fep->dev_id + 1); 2304 fep->mii_bus->priv = fep; 2305 fep->mii_bus->parent = &pdev->dev; 2306 2307 err = of_mdiobus_register(fep->mii_bus, node); 2308 if (err) 2309 goto err_out_free_mdiobus; 2310 of_node_put(node); 2311 2312 mii_cnt++; 2313 2314 /* save fec0 mii_bus */ 2315 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2316 fec0_mii_bus = fep->mii_bus; 2317 2318 return 0; 2319 2320 err_out_free_mdiobus: 2321 mdiobus_free(fep->mii_bus); 2322 err_out: 2323 of_node_put(node); 2324 return err; 2325 } 2326 2327 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2328 { 2329 if (--mii_cnt == 0) { 2330 mdiobus_unregister(fep->mii_bus); 2331 mdiobus_free(fep->mii_bus); 2332 } 2333 } 2334 2335 static void fec_enet_get_drvinfo(struct net_device *ndev, 2336 struct ethtool_drvinfo *info) 2337 { 2338 struct fec_enet_private *fep = netdev_priv(ndev); 2339 2340 strscpy(info->driver, fep->pdev->dev.driver->name, 2341 sizeof(info->driver)); 2342 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2343 } 2344 2345 static int fec_enet_get_regs_len(struct net_device *ndev) 2346 { 2347 struct fec_enet_private *fep = netdev_priv(ndev); 2348 struct resource *r; 2349 int s = 0; 2350 2351 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2352 if (r) 2353 s = resource_size(r); 2354 2355 return s; 2356 } 2357 2358 /* List of registers that can be safety be read to dump them with ethtool */ 2359 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2360 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2361 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2362 static __u32 fec_enet_register_version = 2; 2363 static u32 fec_enet_register_offset[] = { 2364 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2365 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2366 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2367 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2368 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2369 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2370 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2371 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2372 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2373 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2374 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2375 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2376 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2377 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2378 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2379 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2380 RMON_T_P_GTE2048, RMON_T_OCTETS, 2381 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2382 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2383 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2384 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2385 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2386 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2387 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2388 RMON_R_P_GTE2048, RMON_R_OCTETS, 2389 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2390 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2391 }; 2392 #else 2393 static __u32 fec_enet_register_version = 1; 2394 static u32 fec_enet_register_offset[] = { 2395 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2396 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2397 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2398 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2399 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2400 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2401 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2402 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2403 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2404 }; 2405 #endif 2406 2407 static void fec_enet_get_regs(struct net_device *ndev, 2408 struct ethtool_regs *regs, void *regbuf) 2409 { 2410 struct fec_enet_private *fep = netdev_priv(ndev); 2411 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2412 struct device *dev = &fep->pdev->dev; 2413 u32 *buf = (u32 *)regbuf; 2414 u32 i, off; 2415 int ret; 2416 2417 ret = pm_runtime_resume_and_get(dev); 2418 if (ret < 0) 2419 return; 2420 2421 regs->version = fec_enet_register_version; 2422 2423 memset(buf, 0, regs->len); 2424 2425 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2426 off = fec_enet_register_offset[i]; 2427 2428 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2429 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2430 continue; 2431 2432 off >>= 2; 2433 buf[off] = readl(&theregs[off]); 2434 } 2435 2436 pm_runtime_mark_last_busy(dev); 2437 pm_runtime_put_autosuspend(dev); 2438 } 2439 2440 static int fec_enet_get_ts_info(struct net_device *ndev, 2441 struct ethtool_ts_info *info) 2442 { 2443 struct fec_enet_private *fep = netdev_priv(ndev); 2444 2445 if (fep->bufdesc_ex) { 2446 2447 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2448 SOF_TIMESTAMPING_RX_SOFTWARE | 2449 SOF_TIMESTAMPING_SOFTWARE | 2450 SOF_TIMESTAMPING_TX_HARDWARE | 2451 SOF_TIMESTAMPING_RX_HARDWARE | 2452 SOF_TIMESTAMPING_RAW_HARDWARE; 2453 if (fep->ptp_clock) 2454 info->phc_index = ptp_clock_index(fep->ptp_clock); 2455 else 2456 info->phc_index = -1; 2457 2458 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2459 (1 << HWTSTAMP_TX_ON); 2460 2461 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2462 (1 << HWTSTAMP_FILTER_ALL); 2463 return 0; 2464 } else { 2465 return ethtool_op_get_ts_info(ndev, info); 2466 } 2467 } 2468 2469 #if !defined(CONFIG_M5272) 2470 2471 static void fec_enet_get_pauseparam(struct net_device *ndev, 2472 struct ethtool_pauseparam *pause) 2473 { 2474 struct fec_enet_private *fep = netdev_priv(ndev); 2475 2476 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2477 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2478 pause->rx_pause = pause->tx_pause; 2479 } 2480 2481 static int fec_enet_set_pauseparam(struct net_device *ndev, 2482 struct ethtool_pauseparam *pause) 2483 { 2484 struct fec_enet_private *fep = netdev_priv(ndev); 2485 2486 if (!ndev->phydev) 2487 return -ENODEV; 2488 2489 if (pause->tx_pause != pause->rx_pause) { 2490 netdev_info(ndev, 2491 "hardware only support enable/disable both tx and rx"); 2492 return -EINVAL; 2493 } 2494 2495 fep->pause_flag = 0; 2496 2497 /* tx pause must be same as rx pause */ 2498 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2499 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2500 2501 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2502 pause->autoneg); 2503 2504 if (pause->autoneg) { 2505 if (netif_running(ndev)) 2506 fec_stop(ndev); 2507 phy_start_aneg(ndev->phydev); 2508 } 2509 if (netif_running(ndev)) { 2510 napi_disable(&fep->napi); 2511 netif_tx_lock_bh(ndev); 2512 fec_restart(ndev); 2513 netif_tx_wake_all_queues(ndev); 2514 netif_tx_unlock_bh(ndev); 2515 napi_enable(&fep->napi); 2516 } 2517 2518 return 0; 2519 } 2520 2521 static const struct fec_stat { 2522 char name[ETH_GSTRING_LEN]; 2523 u16 offset; 2524 } fec_stats[] = { 2525 /* RMON TX */ 2526 { "tx_dropped", RMON_T_DROP }, 2527 { "tx_packets", RMON_T_PACKETS }, 2528 { "tx_broadcast", RMON_T_BC_PKT }, 2529 { "tx_multicast", RMON_T_MC_PKT }, 2530 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2531 { "tx_undersize", RMON_T_UNDERSIZE }, 2532 { "tx_oversize", RMON_T_OVERSIZE }, 2533 { "tx_fragment", RMON_T_FRAG }, 2534 { "tx_jabber", RMON_T_JAB }, 2535 { "tx_collision", RMON_T_COL }, 2536 { "tx_64byte", RMON_T_P64 }, 2537 { "tx_65to127byte", RMON_T_P65TO127 }, 2538 { "tx_128to255byte", RMON_T_P128TO255 }, 2539 { "tx_256to511byte", RMON_T_P256TO511 }, 2540 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2541 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2542 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2543 { "tx_octets", RMON_T_OCTETS }, 2544 2545 /* IEEE TX */ 2546 { "IEEE_tx_drop", IEEE_T_DROP }, 2547 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2548 { "IEEE_tx_1col", IEEE_T_1COL }, 2549 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2550 { "IEEE_tx_def", IEEE_T_DEF }, 2551 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2552 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2553 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2554 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2555 { "IEEE_tx_sqe", IEEE_T_SQE }, 2556 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2557 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2558 2559 /* RMON RX */ 2560 { "rx_packets", RMON_R_PACKETS }, 2561 { "rx_broadcast", RMON_R_BC_PKT }, 2562 { "rx_multicast", RMON_R_MC_PKT }, 2563 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2564 { "rx_undersize", RMON_R_UNDERSIZE }, 2565 { "rx_oversize", RMON_R_OVERSIZE }, 2566 { "rx_fragment", RMON_R_FRAG }, 2567 { "rx_jabber", RMON_R_JAB }, 2568 { "rx_64byte", RMON_R_P64 }, 2569 { "rx_65to127byte", RMON_R_P65TO127 }, 2570 { "rx_128to255byte", RMON_R_P128TO255 }, 2571 { "rx_256to511byte", RMON_R_P256TO511 }, 2572 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2573 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2574 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2575 { "rx_octets", RMON_R_OCTETS }, 2576 2577 /* IEEE RX */ 2578 { "IEEE_rx_drop", IEEE_R_DROP }, 2579 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2580 { "IEEE_rx_crc", IEEE_R_CRC }, 2581 { "IEEE_rx_align", IEEE_R_ALIGN }, 2582 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2583 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2584 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2585 }; 2586 2587 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2588 2589 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2590 { 2591 struct fec_enet_private *fep = netdev_priv(dev); 2592 int i; 2593 2594 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2595 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2596 } 2597 2598 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2599 struct ethtool_stats *stats, u64 *data) 2600 { 2601 struct fec_enet_private *fep = netdev_priv(dev); 2602 2603 if (netif_running(dev)) 2604 fec_enet_update_ethtool_stats(dev); 2605 2606 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2607 } 2608 2609 static void fec_enet_get_strings(struct net_device *netdev, 2610 u32 stringset, u8 *data) 2611 { 2612 int i; 2613 switch (stringset) { 2614 case ETH_SS_STATS: 2615 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2616 memcpy(data + i * ETH_GSTRING_LEN, 2617 fec_stats[i].name, ETH_GSTRING_LEN); 2618 break; 2619 case ETH_SS_TEST: 2620 net_selftest_get_strings(data); 2621 break; 2622 } 2623 } 2624 2625 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2626 { 2627 switch (sset) { 2628 case ETH_SS_STATS: 2629 return ARRAY_SIZE(fec_stats); 2630 case ETH_SS_TEST: 2631 return net_selftest_get_count(); 2632 default: 2633 return -EOPNOTSUPP; 2634 } 2635 } 2636 2637 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2638 { 2639 struct fec_enet_private *fep = netdev_priv(dev); 2640 int i; 2641 2642 /* Disable MIB statistics counters */ 2643 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2644 2645 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2646 writel(0, fep->hwp + fec_stats[i].offset); 2647 2648 /* Don't disable MIB statistics counters */ 2649 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2650 } 2651 2652 #else /* !defined(CONFIG_M5272) */ 2653 #define FEC_STATS_SIZE 0 2654 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2655 { 2656 } 2657 2658 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2659 { 2660 } 2661 #endif /* !defined(CONFIG_M5272) */ 2662 2663 /* ITR clock source is enet system clock (clk_ahb). 2664 * TCTT unit is cycle_ns * 64 cycle 2665 * So, the ICTT value = X us / (cycle_ns * 64) 2666 */ 2667 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2668 { 2669 struct fec_enet_private *fep = netdev_priv(ndev); 2670 2671 return us * (fep->itr_clk_rate / 64000) / 1000; 2672 } 2673 2674 /* Set threshold for interrupt coalescing */ 2675 static void fec_enet_itr_coal_set(struct net_device *ndev) 2676 { 2677 struct fec_enet_private *fep = netdev_priv(ndev); 2678 int rx_itr, tx_itr; 2679 2680 /* Must be greater than zero to avoid unpredictable behavior */ 2681 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2682 !fep->tx_time_itr || !fep->tx_pkts_itr) 2683 return; 2684 2685 /* Select enet system clock as Interrupt Coalescing 2686 * timer Clock Source 2687 */ 2688 rx_itr = FEC_ITR_CLK_SEL; 2689 tx_itr = FEC_ITR_CLK_SEL; 2690 2691 /* set ICFT and ICTT */ 2692 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2693 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2694 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2695 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2696 2697 rx_itr |= FEC_ITR_EN; 2698 tx_itr |= FEC_ITR_EN; 2699 2700 writel(tx_itr, fep->hwp + FEC_TXIC0); 2701 writel(rx_itr, fep->hwp + FEC_RXIC0); 2702 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 2703 writel(tx_itr, fep->hwp + FEC_TXIC1); 2704 writel(rx_itr, fep->hwp + FEC_RXIC1); 2705 writel(tx_itr, fep->hwp + FEC_TXIC2); 2706 writel(rx_itr, fep->hwp + FEC_RXIC2); 2707 } 2708 } 2709 2710 static int fec_enet_get_coalesce(struct net_device *ndev, 2711 struct ethtool_coalesce *ec, 2712 struct kernel_ethtool_coalesce *kernel_coal, 2713 struct netlink_ext_ack *extack) 2714 { 2715 struct fec_enet_private *fep = netdev_priv(ndev); 2716 2717 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2718 return -EOPNOTSUPP; 2719 2720 ec->rx_coalesce_usecs = fep->rx_time_itr; 2721 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2722 2723 ec->tx_coalesce_usecs = fep->tx_time_itr; 2724 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2725 2726 return 0; 2727 } 2728 2729 static int fec_enet_set_coalesce(struct net_device *ndev, 2730 struct ethtool_coalesce *ec, 2731 struct kernel_ethtool_coalesce *kernel_coal, 2732 struct netlink_ext_ack *extack) 2733 { 2734 struct fec_enet_private *fep = netdev_priv(ndev); 2735 struct device *dev = &fep->pdev->dev; 2736 unsigned int cycle; 2737 2738 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2739 return -EOPNOTSUPP; 2740 2741 if (ec->rx_max_coalesced_frames > 255) { 2742 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 2743 return -EINVAL; 2744 } 2745 2746 if (ec->tx_max_coalesced_frames > 255) { 2747 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 2748 return -EINVAL; 2749 } 2750 2751 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 2752 if (cycle > 0xFFFF) { 2753 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 2754 return -EINVAL; 2755 } 2756 2757 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 2758 if (cycle > 0xFFFF) { 2759 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 2760 return -EINVAL; 2761 } 2762 2763 fep->rx_time_itr = ec->rx_coalesce_usecs; 2764 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2765 2766 fep->tx_time_itr = ec->tx_coalesce_usecs; 2767 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2768 2769 fec_enet_itr_coal_set(ndev); 2770 2771 return 0; 2772 } 2773 2774 static void fec_enet_itr_coal_init(struct net_device *ndev) 2775 { 2776 struct ethtool_coalesce ec; 2777 2778 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2779 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2780 2781 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2782 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2783 2784 fec_enet_set_coalesce(ndev, &ec, NULL, NULL); 2785 } 2786 2787 static int fec_enet_get_tunable(struct net_device *netdev, 2788 const struct ethtool_tunable *tuna, 2789 void *data) 2790 { 2791 struct fec_enet_private *fep = netdev_priv(netdev); 2792 int ret = 0; 2793 2794 switch (tuna->id) { 2795 case ETHTOOL_RX_COPYBREAK: 2796 *(u32 *)data = fep->rx_copybreak; 2797 break; 2798 default: 2799 ret = -EINVAL; 2800 break; 2801 } 2802 2803 return ret; 2804 } 2805 2806 static int fec_enet_set_tunable(struct net_device *netdev, 2807 const struct ethtool_tunable *tuna, 2808 const void *data) 2809 { 2810 struct fec_enet_private *fep = netdev_priv(netdev); 2811 int ret = 0; 2812 2813 switch (tuna->id) { 2814 case ETHTOOL_RX_COPYBREAK: 2815 fep->rx_copybreak = *(u32 *)data; 2816 break; 2817 default: 2818 ret = -EINVAL; 2819 break; 2820 } 2821 2822 return ret; 2823 } 2824 2825 /* LPI Sleep Ts count base on tx clk (clk_ref). 2826 * The lpi sleep cnt value = X us / (cycle_ns). 2827 */ 2828 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 2829 { 2830 struct fec_enet_private *fep = netdev_priv(ndev); 2831 2832 return us * (fep->clk_ref_rate / 1000) / 1000; 2833 } 2834 2835 static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable) 2836 { 2837 struct fec_enet_private *fep = netdev_priv(ndev); 2838 struct ethtool_eee *p = &fep->eee; 2839 unsigned int sleep_cycle, wake_cycle; 2840 int ret = 0; 2841 2842 if (enable) { 2843 ret = phy_init_eee(ndev->phydev, false); 2844 if (ret) 2845 return ret; 2846 2847 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer); 2848 wake_cycle = sleep_cycle; 2849 } else { 2850 sleep_cycle = 0; 2851 wake_cycle = 0; 2852 } 2853 2854 p->tx_lpi_enabled = enable; 2855 p->eee_enabled = enable; 2856 p->eee_active = enable; 2857 2858 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 2859 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 2860 2861 return 0; 2862 } 2863 2864 static int 2865 fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata) 2866 { 2867 struct fec_enet_private *fep = netdev_priv(ndev); 2868 struct ethtool_eee *p = &fep->eee; 2869 2870 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 2871 return -EOPNOTSUPP; 2872 2873 if (!netif_running(ndev)) 2874 return -ENETDOWN; 2875 2876 edata->eee_enabled = p->eee_enabled; 2877 edata->eee_active = p->eee_active; 2878 edata->tx_lpi_timer = p->tx_lpi_timer; 2879 edata->tx_lpi_enabled = p->tx_lpi_enabled; 2880 2881 return phy_ethtool_get_eee(ndev->phydev, edata); 2882 } 2883 2884 static int 2885 fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata) 2886 { 2887 struct fec_enet_private *fep = netdev_priv(ndev); 2888 struct ethtool_eee *p = &fep->eee; 2889 int ret = 0; 2890 2891 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 2892 return -EOPNOTSUPP; 2893 2894 if (!netif_running(ndev)) 2895 return -ENETDOWN; 2896 2897 p->tx_lpi_timer = edata->tx_lpi_timer; 2898 2899 if (!edata->eee_enabled || !edata->tx_lpi_enabled || 2900 !edata->tx_lpi_timer) 2901 ret = fec_enet_eee_mode_set(ndev, false); 2902 else 2903 ret = fec_enet_eee_mode_set(ndev, true); 2904 2905 if (ret) 2906 return ret; 2907 2908 return phy_ethtool_set_eee(ndev->phydev, edata); 2909 } 2910 2911 static void 2912 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2913 { 2914 struct fec_enet_private *fep = netdev_priv(ndev); 2915 2916 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2917 wol->supported = WAKE_MAGIC; 2918 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2919 } else { 2920 wol->supported = wol->wolopts = 0; 2921 } 2922 } 2923 2924 static int 2925 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2926 { 2927 struct fec_enet_private *fep = netdev_priv(ndev); 2928 2929 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2930 return -EINVAL; 2931 2932 if (wol->wolopts & ~WAKE_MAGIC) 2933 return -EINVAL; 2934 2935 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2936 if (device_may_wakeup(&ndev->dev)) 2937 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2938 else 2939 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2940 2941 return 0; 2942 } 2943 2944 static const struct ethtool_ops fec_enet_ethtool_ops = { 2945 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2946 ETHTOOL_COALESCE_MAX_FRAMES, 2947 .get_drvinfo = fec_enet_get_drvinfo, 2948 .get_regs_len = fec_enet_get_regs_len, 2949 .get_regs = fec_enet_get_regs, 2950 .nway_reset = phy_ethtool_nway_reset, 2951 .get_link = ethtool_op_get_link, 2952 .get_coalesce = fec_enet_get_coalesce, 2953 .set_coalesce = fec_enet_set_coalesce, 2954 #ifndef CONFIG_M5272 2955 .get_pauseparam = fec_enet_get_pauseparam, 2956 .set_pauseparam = fec_enet_set_pauseparam, 2957 .get_strings = fec_enet_get_strings, 2958 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2959 .get_sset_count = fec_enet_get_sset_count, 2960 #endif 2961 .get_ts_info = fec_enet_get_ts_info, 2962 .get_tunable = fec_enet_get_tunable, 2963 .set_tunable = fec_enet_set_tunable, 2964 .get_wol = fec_enet_get_wol, 2965 .set_wol = fec_enet_set_wol, 2966 .get_eee = fec_enet_get_eee, 2967 .set_eee = fec_enet_set_eee, 2968 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2969 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2970 .self_test = net_selftest, 2971 }; 2972 2973 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2974 { 2975 struct fec_enet_private *fep = netdev_priv(ndev); 2976 struct phy_device *phydev = ndev->phydev; 2977 2978 if (!netif_running(ndev)) 2979 return -EINVAL; 2980 2981 if (!phydev) 2982 return -ENODEV; 2983 2984 if (fep->bufdesc_ex) { 2985 bool use_fec_hwts = !phy_has_hwtstamp(phydev); 2986 2987 if (cmd == SIOCSHWTSTAMP) { 2988 if (use_fec_hwts) 2989 return fec_ptp_set(ndev, rq); 2990 fec_ptp_disable_hwts(ndev); 2991 } else if (cmd == SIOCGHWTSTAMP) { 2992 if (use_fec_hwts) 2993 return fec_ptp_get(ndev, rq); 2994 } 2995 } 2996 2997 return phy_mii_ioctl(phydev, rq, cmd); 2998 } 2999 3000 static void fec_enet_free_buffers(struct net_device *ndev) 3001 { 3002 struct fec_enet_private *fep = netdev_priv(ndev); 3003 unsigned int i; 3004 struct sk_buff *skb; 3005 struct bufdesc *bdp; 3006 struct fec_enet_priv_tx_q *txq; 3007 struct fec_enet_priv_rx_q *rxq; 3008 unsigned int q; 3009 3010 for (q = 0; q < fep->num_rx_queues; q++) { 3011 rxq = fep->rx_queue[q]; 3012 bdp = rxq->bd.base; 3013 for (i = 0; i < rxq->bd.ring_size; i++) { 3014 skb = rxq->rx_skbuff[i]; 3015 rxq->rx_skbuff[i] = NULL; 3016 if (skb) { 3017 dma_unmap_single(&fep->pdev->dev, 3018 fec32_to_cpu(bdp->cbd_bufaddr), 3019 FEC_ENET_RX_FRSIZE - fep->rx_align, 3020 DMA_FROM_DEVICE); 3021 dev_kfree_skb(skb); 3022 } 3023 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3024 } 3025 } 3026 3027 for (q = 0; q < fep->num_tx_queues; q++) { 3028 txq = fep->tx_queue[q]; 3029 for (i = 0; i < txq->bd.ring_size; i++) { 3030 kfree(txq->tx_bounce[i]); 3031 txq->tx_bounce[i] = NULL; 3032 skb = txq->tx_skbuff[i]; 3033 txq->tx_skbuff[i] = NULL; 3034 dev_kfree_skb(skb); 3035 } 3036 } 3037 } 3038 3039 static void fec_enet_free_queue(struct net_device *ndev) 3040 { 3041 struct fec_enet_private *fep = netdev_priv(ndev); 3042 int i; 3043 struct fec_enet_priv_tx_q *txq; 3044 3045 for (i = 0; i < fep->num_tx_queues; i++) 3046 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 3047 txq = fep->tx_queue[i]; 3048 dma_free_coherent(&fep->pdev->dev, 3049 txq->bd.ring_size * TSO_HEADER_SIZE, 3050 txq->tso_hdrs, 3051 txq->tso_hdrs_dma); 3052 } 3053 3054 for (i = 0; i < fep->num_rx_queues; i++) 3055 kfree(fep->rx_queue[i]); 3056 for (i = 0; i < fep->num_tx_queues; i++) 3057 kfree(fep->tx_queue[i]); 3058 } 3059 3060 static int fec_enet_alloc_queue(struct net_device *ndev) 3061 { 3062 struct fec_enet_private *fep = netdev_priv(ndev); 3063 int i; 3064 int ret = 0; 3065 struct fec_enet_priv_tx_q *txq; 3066 3067 for (i = 0; i < fep->num_tx_queues; i++) { 3068 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3069 if (!txq) { 3070 ret = -ENOMEM; 3071 goto alloc_failed; 3072 } 3073 3074 fep->tx_queue[i] = txq; 3075 txq->bd.ring_size = TX_RING_SIZE; 3076 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3077 3078 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3079 txq->tx_wake_threshold = 3080 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 3081 3082 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 3083 txq->bd.ring_size * TSO_HEADER_SIZE, 3084 &txq->tso_hdrs_dma, 3085 GFP_KERNEL); 3086 if (!txq->tso_hdrs) { 3087 ret = -ENOMEM; 3088 goto alloc_failed; 3089 } 3090 } 3091 3092 for (i = 0; i < fep->num_rx_queues; i++) { 3093 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3094 GFP_KERNEL); 3095 if (!fep->rx_queue[i]) { 3096 ret = -ENOMEM; 3097 goto alloc_failed; 3098 } 3099 3100 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3101 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3102 } 3103 return ret; 3104 3105 alloc_failed: 3106 fec_enet_free_queue(ndev); 3107 return ret; 3108 } 3109 3110 static int 3111 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3112 { 3113 struct fec_enet_private *fep = netdev_priv(ndev); 3114 unsigned int i; 3115 struct sk_buff *skb; 3116 struct bufdesc *bdp; 3117 struct fec_enet_priv_rx_q *rxq; 3118 3119 rxq = fep->rx_queue[queue]; 3120 bdp = rxq->bd.base; 3121 for (i = 0; i < rxq->bd.ring_size; i++) { 3122 skb = __netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE, GFP_KERNEL); 3123 if (!skb) 3124 goto err_alloc; 3125 3126 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 3127 dev_kfree_skb(skb); 3128 goto err_alloc; 3129 } 3130 3131 rxq->rx_skbuff[i] = skb; 3132 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3133 3134 if (fep->bufdesc_ex) { 3135 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3136 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3137 } 3138 3139 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3140 } 3141 3142 /* Set the last buffer to wrap. */ 3143 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3144 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3145 return 0; 3146 3147 err_alloc: 3148 fec_enet_free_buffers(ndev); 3149 return -ENOMEM; 3150 } 3151 3152 static int 3153 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3154 { 3155 struct fec_enet_private *fep = netdev_priv(ndev); 3156 unsigned int i; 3157 struct bufdesc *bdp; 3158 struct fec_enet_priv_tx_q *txq; 3159 3160 txq = fep->tx_queue[queue]; 3161 bdp = txq->bd.base; 3162 for (i = 0; i < txq->bd.ring_size; i++) { 3163 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3164 if (!txq->tx_bounce[i]) 3165 goto err_alloc; 3166 3167 bdp->cbd_sc = cpu_to_fec16(0); 3168 bdp->cbd_bufaddr = cpu_to_fec32(0); 3169 3170 if (fep->bufdesc_ex) { 3171 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3172 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3173 } 3174 3175 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3176 } 3177 3178 /* Set the last buffer to wrap. */ 3179 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3180 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3181 3182 return 0; 3183 3184 err_alloc: 3185 fec_enet_free_buffers(ndev); 3186 return -ENOMEM; 3187 } 3188 3189 static int fec_enet_alloc_buffers(struct net_device *ndev) 3190 { 3191 struct fec_enet_private *fep = netdev_priv(ndev); 3192 unsigned int i; 3193 3194 for (i = 0; i < fep->num_rx_queues; i++) 3195 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3196 return -ENOMEM; 3197 3198 for (i = 0; i < fep->num_tx_queues; i++) 3199 if (fec_enet_alloc_txq_buffers(ndev, i)) 3200 return -ENOMEM; 3201 return 0; 3202 } 3203 3204 static int 3205 fec_enet_open(struct net_device *ndev) 3206 { 3207 struct fec_enet_private *fep = netdev_priv(ndev); 3208 int ret; 3209 bool reset_again; 3210 3211 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3212 if (ret < 0) 3213 return ret; 3214 3215 pinctrl_pm_select_default_state(&fep->pdev->dev); 3216 ret = fec_enet_clk_enable(ndev, true); 3217 if (ret) 3218 goto clk_enable; 3219 3220 /* During the first fec_enet_open call the PHY isn't probed at this 3221 * point. Therefore the phy_reset_after_clk_enable() call within 3222 * fec_enet_clk_enable() fails. As we need this reset in order to be 3223 * sure the PHY is working correctly we check if we need to reset again 3224 * later when the PHY is probed 3225 */ 3226 if (ndev->phydev && ndev->phydev->drv) 3227 reset_again = false; 3228 else 3229 reset_again = true; 3230 3231 /* I should reset the ring buffers here, but I don't yet know 3232 * a simple way to do that. 3233 */ 3234 3235 ret = fec_enet_alloc_buffers(ndev); 3236 if (ret) 3237 goto err_enet_alloc; 3238 3239 /* Init MAC prior to mii bus probe */ 3240 fec_restart(ndev); 3241 3242 /* Call phy_reset_after_clk_enable() again if it failed during 3243 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3244 */ 3245 if (reset_again) 3246 fec_enet_phy_reset_after_clk_enable(ndev); 3247 3248 /* Probe and connect to PHY when open the interface */ 3249 ret = fec_enet_mii_probe(ndev); 3250 if (ret) 3251 goto err_enet_mii_probe; 3252 3253 if (fep->quirks & FEC_QUIRK_ERR006687) 3254 imx6q_cpuidle_fec_irqs_used(); 3255 3256 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3257 cpu_latency_qos_add_request(&fep->pm_qos_req, 0); 3258 3259 napi_enable(&fep->napi); 3260 phy_start(ndev->phydev); 3261 netif_tx_start_all_queues(ndev); 3262 3263 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3264 FEC_WOL_FLAG_ENABLE); 3265 3266 return 0; 3267 3268 err_enet_mii_probe: 3269 fec_enet_free_buffers(ndev); 3270 err_enet_alloc: 3271 fec_enet_clk_enable(ndev, false); 3272 clk_enable: 3273 pm_runtime_mark_last_busy(&fep->pdev->dev); 3274 pm_runtime_put_autosuspend(&fep->pdev->dev); 3275 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3276 return ret; 3277 } 3278 3279 static int 3280 fec_enet_close(struct net_device *ndev) 3281 { 3282 struct fec_enet_private *fep = netdev_priv(ndev); 3283 3284 phy_stop(ndev->phydev); 3285 3286 if (netif_device_present(ndev)) { 3287 napi_disable(&fep->napi); 3288 netif_tx_disable(ndev); 3289 fec_stop(ndev); 3290 } 3291 3292 phy_disconnect(ndev->phydev); 3293 3294 if (fep->quirks & FEC_QUIRK_ERR006687) 3295 imx6q_cpuidle_fec_irqs_unused(); 3296 3297 fec_enet_update_ethtool_stats(ndev); 3298 3299 fec_enet_clk_enable(ndev, false); 3300 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3301 cpu_latency_qos_remove_request(&fep->pm_qos_req); 3302 3303 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3304 pm_runtime_mark_last_busy(&fep->pdev->dev); 3305 pm_runtime_put_autosuspend(&fep->pdev->dev); 3306 3307 fec_enet_free_buffers(ndev); 3308 3309 return 0; 3310 } 3311 3312 /* Set or clear the multicast filter for this adaptor. 3313 * Skeleton taken from sunlance driver. 3314 * The CPM Ethernet implementation allows Multicast as well as individual 3315 * MAC address filtering. Some of the drivers check to make sure it is 3316 * a group multicast address, and discard those that are not. I guess I 3317 * will do the same for now, but just remove the test if you want 3318 * individual filtering as well (do the upper net layers want or support 3319 * this kind of feature?). 3320 */ 3321 3322 #define FEC_HASH_BITS 6 /* #bits in hash */ 3323 3324 static void set_multicast_list(struct net_device *ndev) 3325 { 3326 struct fec_enet_private *fep = netdev_priv(ndev); 3327 struct netdev_hw_addr *ha; 3328 unsigned int crc, tmp; 3329 unsigned char hash; 3330 unsigned int hash_high = 0, hash_low = 0; 3331 3332 if (ndev->flags & IFF_PROMISC) { 3333 tmp = readl(fep->hwp + FEC_R_CNTRL); 3334 tmp |= 0x8; 3335 writel(tmp, fep->hwp + FEC_R_CNTRL); 3336 return; 3337 } 3338 3339 tmp = readl(fep->hwp + FEC_R_CNTRL); 3340 tmp &= ~0x8; 3341 writel(tmp, fep->hwp + FEC_R_CNTRL); 3342 3343 if (ndev->flags & IFF_ALLMULTI) { 3344 /* Catch all multicast addresses, so set the 3345 * filter to all 1's 3346 */ 3347 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3348 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3349 3350 return; 3351 } 3352 3353 /* Add the addresses in hash register */ 3354 netdev_for_each_mc_addr(ha, ndev) { 3355 /* calculate crc32 value of mac address */ 3356 crc = ether_crc_le(ndev->addr_len, ha->addr); 3357 3358 /* only upper 6 bits (FEC_HASH_BITS) are used 3359 * which point to specific bit in the hash registers 3360 */ 3361 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3362 3363 if (hash > 31) 3364 hash_high |= 1 << (hash - 32); 3365 else 3366 hash_low |= 1 << hash; 3367 } 3368 3369 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3370 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3371 } 3372 3373 /* Set a MAC change in hardware. */ 3374 static int 3375 fec_set_mac_address(struct net_device *ndev, void *p) 3376 { 3377 struct fec_enet_private *fep = netdev_priv(ndev); 3378 struct sockaddr *addr = p; 3379 3380 if (addr) { 3381 if (!is_valid_ether_addr(addr->sa_data)) 3382 return -EADDRNOTAVAIL; 3383 eth_hw_addr_set(ndev, addr->sa_data); 3384 } 3385 3386 /* Add netif status check here to avoid system hang in below case: 3387 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3388 * After ethx down, fec all clocks are gated off and then register 3389 * access causes system hang. 3390 */ 3391 if (!netif_running(ndev)) 3392 return 0; 3393 3394 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3395 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3396 fep->hwp + FEC_ADDR_LOW); 3397 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3398 fep->hwp + FEC_ADDR_HIGH); 3399 return 0; 3400 } 3401 3402 #ifdef CONFIG_NET_POLL_CONTROLLER 3403 /** 3404 * fec_poll_controller - FEC Poll controller function 3405 * @dev: The FEC network adapter 3406 * 3407 * Polled functionality used by netconsole and others in non interrupt mode 3408 * 3409 */ 3410 static void fec_poll_controller(struct net_device *dev) 3411 { 3412 int i; 3413 struct fec_enet_private *fep = netdev_priv(dev); 3414 3415 for (i = 0; i < FEC_IRQ_NUM; i++) { 3416 if (fep->irq[i] > 0) { 3417 disable_irq(fep->irq[i]); 3418 fec_enet_interrupt(fep->irq[i], dev); 3419 enable_irq(fep->irq[i]); 3420 } 3421 } 3422 } 3423 #endif 3424 3425 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3426 netdev_features_t features) 3427 { 3428 struct fec_enet_private *fep = netdev_priv(netdev); 3429 netdev_features_t changed = features ^ netdev->features; 3430 3431 netdev->features = features; 3432 3433 /* Receive checksum has been changed */ 3434 if (changed & NETIF_F_RXCSUM) { 3435 if (features & NETIF_F_RXCSUM) 3436 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3437 else 3438 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3439 } 3440 } 3441 3442 static int fec_set_features(struct net_device *netdev, 3443 netdev_features_t features) 3444 { 3445 struct fec_enet_private *fep = netdev_priv(netdev); 3446 netdev_features_t changed = features ^ netdev->features; 3447 3448 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3449 napi_disable(&fep->napi); 3450 netif_tx_lock_bh(netdev); 3451 fec_stop(netdev); 3452 fec_enet_set_netdev_features(netdev, features); 3453 fec_restart(netdev); 3454 netif_tx_wake_all_queues(netdev); 3455 netif_tx_unlock_bh(netdev); 3456 napi_enable(&fep->napi); 3457 } else { 3458 fec_enet_set_netdev_features(netdev, features); 3459 } 3460 3461 return 0; 3462 } 3463 3464 static u16 fec_enet_get_raw_vlan_tci(struct sk_buff *skb) 3465 { 3466 struct vlan_ethhdr *vhdr; 3467 unsigned short vlan_TCI = 0; 3468 3469 if (skb->protocol == htons(ETH_P_ALL)) { 3470 vhdr = (struct vlan_ethhdr *)(skb->data); 3471 vlan_TCI = ntohs(vhdr->h_vlan_TCI); 3472 } 3473 3474 return vlan_TCI; 3475 } 3476 3477 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3478 struct net_device *sb_dev) 3479 { 3480 struct fec_enet_private *fep = netdev_priv(ndev); 3481 u16 vlan_tag; 3482 3483 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3484 return netdev_pick_tx(ndev, skb, NULL); 3485 3486 vlan_tag = fec_enet_get_raw_vlan_tci(skb); 3487 if (!vlan_tag) 3488 return vlan_tag; 3489 3490 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3491 } 3492 3493 static const struct net_device_ops fec_netdev_ops = { 3494 .ndo_open = fec_enet_open, 3495 .ndo_stop = fec_enet_close, 3496 .ndo_start_xmit = fec_enet_start_xmit, 3497 .ndo_select_queue = fec_enet_select_queue, 3498 .ndo_set_rx_mode = set_multicast_list, 3499 .ndo_validate_addr = eth_validate_addr, 3500 .ndo_tx_timeout = fec_timeout, 3501 .ndo_set_mac_address = fec_set_mac_address, 3502 .ndo_eth_ioctl = fec_enet_ioctl, 3503 #ifdef CONFIG_NET_POLL_CONTROLLER 3504 .ndo_poll_controller = fec_poll_controller, 3505 #endif 3506 .ndo_set_features = fec_set_features, 3507 }; 3508 3509 static const unsigned short offset_des_active_rxq[] = { 3510 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3511 }; 3512 3513 static const unsigned short offset_des_active_txq[] = { 3514 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3515 }; 3516 3517 /* 3518 * XXX: We need to clean up on failure exits here. 3519 * 3520 */ 3521 static int fec_enet_init(struct net_device *ndev) 3522 { 3523 struct fec_enet_private *fep = netdev_priv(ndev); 3524 struct bufdesc *cbd_base; 3525 dma_addr_t bd_dma; 3526 int bd_size; 3527 unsigned int i; 3528 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3529 sizeof(struct bufdesc); 3530 unsigned dsize_log2 = __fls(dsize); 3531 int ret; 3532 3533 WARN_ON(dsize != (1 << dsize_log2)); 3534 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 3535 fep->rx_align = 0xf; 3536 fep->tx_align = 0xf; 3537 #else 3538 fep->rx_align = 0x3; 3539 fep->tx_align = 0x3; 3540 #endif 3541 3542 /* Check mask of the streaming and coherent API */ 3543 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 3544 if (ret < 0) { 3545 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 3546 return ret; 3547 } 3548 3549 ret = fec_enet_alloc_queue(ndev); 3550 if (ret) 3551 return ret; 3552 3553 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3554 3555 /* Allocate memory for buffer descriptors. */ 3556 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3557 GFP_KERNEL); 3558 if (!cbd_base) { 3559 ret = -ENOMEM; 3560 goto free_queue_mem; 3561 } 3562 3563 /* Get the Ethernet address */ 3564 ret = fec_get_mac(ndev); 3565 if (ret) 3566 goto free_queue_mem; 3567 3568 /* make sure MAC we just acquired is programmed into the hw */ 3569 fec_set_mac_address(ndev, NULL); 3570 3571 /* Set receive and transmit descriptor base. */ 3572 for (i = 0; i < fep->num_rx_queues; i++) { 3573 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3574 unsigned size = dsize * rxq->bd.ring_size; 3575 3576 rxq->bd.qid = i; 3577 rxq->bd.base = cbd_base; 3578 rxq->bd.cur = cbd_base; 3579 rxq->bd.dma = bd_dma; 3580 rxq->bd.dsize = dsize; 3581 rxq->bd.dsize_log2 = dsize_log2; 3582 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3583 bd_dma += size; 3584 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3585 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3586 } 3587 3588 for (i = 0; i < fep->num_tx_queues; i++) { 3589 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3590 unsigned size = dsize * txq->bd.ring_size; 3591 3592 txq->bd.qid = i; 3593 txq->bd.base = cbd_base; 3594 txq->bd.cur = cbd_base; 3595 txq->bd.dma = bd_dma; 3596 txq->bd.dsize = dsize; 3597 txq->bd.dsize_log2 = dsize_log2; 3598 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3599 bd_dma += size; 3600 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3601 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3602 } 3603 3604 3605 /* The FEC Ethernet specific entries in the device structure */ 3606 ndev->watchdog_timeo = TX_TIMEOUT; 3607 ndev->netdev_ops = &fec_netdev_ops; 3608 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3609 3610 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3611 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi); 3612 3613 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3614 /* enable hw VLAN support */ 3615 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3616 3617 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3618 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS); 3619 3620 /* enable hw accelerator */ 3621 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3622 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3623 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3624 } 3625 3626 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 3627 fep->tx_align = 0; 3628 fep->rx_align = 0x3f; 3629 } 3630 3631 ndev->hw_features = ndev->features; 3632 3633 fec_restart(ndev); 3634 3635 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 3636 fec_enet_clear_ethtool_stats(ndev); 3637 else 3638 fec_enet_update_ethtool_stats(ndev); 3639 3640 return 0; 3641 3642 free_queue_mem: 3643 fec_enet_free_queue(ndev); 3644 return ret; 3645 } 3646 3647 #ifdef CONFIG_OF 3648 static int fec_reset_phy(struct platform_device *pdev) 3649 { 3650 int err, phy_reset; 3651 bool active_high = false; 3652 int msec = 1, phy_post_delay = 0; 3653 struct device_node *np = pdev->dev.of_node; 3654 3655 if (!np) 3656 return 0; 3657 3658 err = of_property_read_u32(np, "phy-reset-duration", &msec); 3659 /* A sane reset duration should not be longer than 1s */ 3660 if (!err && msec > 1000) 3661 msec = 1; 3662 3663 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3664 if (phy_reset == -EPROBE_DEFER) 3665 return phy_reset; 3666 else if (!gpio_is_valid(phy_reset)) 3667 return 0; 3668 3669 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 3670 /* valid reset duration should be less than 1s */ 3671 if (!err && phy_post_delay > 1000) 3672 return -EINVAL; 3673 3674 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3675 3676 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3677 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3678 "phy-reset"); 3679 if (err) { 3680 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3681 return err; 3682 } 3683 3684 if (msec > 20) 3685 msleep(msec); 3686 else 3687 usleep_range(msec * 1000, msec * 1000 + 1000); 3688 3689 gpio_set_value_cansleep(phy_reset, !active_high); 3690 3691 if (!phy_post_delay) 3692 return 0; 3693 3694 if (phy_post_delay > 20) 3695 msleep(phy_post_delay); 3696 else 3697 usleep_range(phy_post_delay * 1000, 3698 phy_post_delay * 1000 + 1000); 3699 3700 return 0; 3701 } 3702 #else /* CONFIG_OF */ 3703 static int fec_reset_phy(struct platform_device *pdev) 3704 { 3705 /* 3706 * In case of platform probe, the reset has been done 3707 * by machine code. 3708 */ 3709 return 0; 3710 } 3711 #endif /* CONFIG_OF */ 3712 3713 static void 3714 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3715 { 3716 struct device_node *np = pdev->dev.of_node; 3717 3718 *num_tx = *num_rx = 1; 3719 3720 if (!np || !of_device_is_available(np)) 3721 return; 3722 3723 /* parse the num of tx and rx queues */ 3724 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3725 3726 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3727 3728 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3729 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3730 *num_tx); 3731 *num_tx = 1; 3732 return; 3733 } 3734 3735 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3736 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3737 *num_rx); 3738 *num_rx = 1; 3739 return; 3740 } 3741 3742 } 3743 3744 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 3745 { 3746 int irq_cnt = platform_irq_count(pdev); 3747 3748 if (irq_cnt > FEC_IRQ_NUM) 3749 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 3750 else if (irq_cnt == 2) 3751 irq_cnt = 1; /* last for pps */ 3752 else if (irq_cnt <= 0) 3753 irq_cnt = 1; /* At least 1 irq is needed */ 3754 return irq_cnt; 3755 } 3756 3757 static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 3758 { 3759 struct net_device *ndev = platform_get_drvdata(pdev); 3760 struct fec_enet_private *fep = netdev_priv(ndev); 3761 3762 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 3763 fep->wake_irq = fep->irq[2]; 3764 else 3765 fep->wake_irq = fep->irq[0]; 3766 } 3767 3768 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 3769 struct device_node *np) 3770 { 3771 struct device_node *gpr_np; 3772 u32 out_val[3]; 3773 int ret = 0; 3774 3775 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 3776 if (!gpr_np) 3777 return 0; 3778 3779 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 3780 ARRAY_SIZE(out_val)); 3781 if (ret) { 3782 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 3783 goto out; 3784 } 3785 3786 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 3787 if (IS_ERR(fep->stop_gpr.gpr)) { 3788 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 3789 ret = PTR_ERR(fep->stop_gpr.gpr); 3790 fep->stop_gpr.gpr = NULL; 3791 goto out; 3792 } 3793 3794 fep->stop_gpr.reg = out_val[1]; 3795 fep->stop_gpr.bit = out_val[2]; 3796 3797 out: 3798 of_node_put(gpr_np); 3799 3800 return ret; 3801 } 3802 3803 static int 3804 fec_probe(struct platform_device *pdev) 3805 { 3806 struct fec_enet_private *fep; 3807 struct fec_platform_data *pdata; 3808 phy_interface_t interface; 3809 struct net_device *ndev; 3810 int i, irq, ret = 0; 3811 const struct of_device_id *of_id; 3812 static int dev_id; 3813 struct device_node *np = pdev->dev.of_node, *phy_node; 3814 int num_tx_qs; 3815 int num_rx_qs; 3816 char irq_name[8]; 3817 int irq_cnt; 3818 struct fec_devinfo *dev_info; 3819 3820 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3821 3822 /* Init network device */ 3823 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 3824 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 3825 if (!ndev) 3826 return -ENOMEM; 3827 3828 SET_NETDEV_DEV(ndev, &pdev->dev); 3829 3830 /* setup board info structure */ 3831 fep = netdev_priv(ndev); 3832 3833 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3834 if (of_id) 3835 pdev->id_entry = of_id->data; 3836 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; 3837 if (dev_info) 3838 fep->quirks = dev_info->quirks; 3839 3840 fep->netdev = ndev; 3841 fep->num_rx_queues = num_rx_qs; 3842 fep->num_tx_queues = num_tx_qs; 3843 3844 #if !defined(CONFIG_M5272) 3845 /* default enable pause frame auto negotiation */ 3846 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3847 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3848 #endif 3849 3850 /* Select default pin state */ 3851 pinctrl_pm_select_default_state(&pdev->dev); 3852 3853 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 3854 if (IS_ERR(fep->hwp)) { 3855 ret = PTR_ERR(fep->hwp); 3856 goto failed_ioremap; 3857 } 3858 3859 fep->pdev = pdev; 3860 fep->dev_id = dev_id++; 3861 3862 platform_set_drvdata(pdev, ndev); 3863 3864 if ((of_machine_is_compatible("fsl,imx6q") || 3865 of_machine_is_compatible("fsl,imx6dl")) && 3866 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3867 fep->quirks |= FEC_QUIRK_ERR006687; 3868 3869 ret = fec_enet_ipc_handle_init(fep); 3870 if (ret) 3871 goto failed_ipc_init; 3872 3873 if (of_get_property(np, "fsl,magic-packet", NULL)) 3874 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3875 3876 ret = fec_enet_init_stop_mode(fep, np); 3877 if (ret) 3878 goto failed_stop_mode; 3879 3880 phy_node = of_parse_phandle(np, "phy-handle", 0); 3881 if (!phy_node && of_phy_is_fixed_link(np)) { 3882 ret = of_phy_register_fixed_link(np); 3883 if (ret < 0) { 3884 dev_err(&pdev->dev, 3885 "broken fixed-link specification\n"); 3886 goto failed_phy; 3887 } 3888 phy_node = of_node_get(np); 3889 } 3890 fep->phy_node = phy_node; 3891 3892 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 3893 if (ret) { 3894 pdata = dev_get_platdata(&pdev->dev); 3895 if (pdata) 3896 fep->phy_interface = pdata->phy; 3897 else 3898 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3899 } else { 3900 fep->phy_interface = interface; 3901 } 3902 3903 ret = fec_enet_parse_rgmii_delay(fep, np); 3904 if (ret) 3905 goto failed_rgmii_delay; 3906 3907 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3908 if (IS_ERR(fep->clk_ipg)) { 3909 ret = PTR_ERR(fep->clk_ipg); 3910 goto failed_clk; 3911 } 3912 3913 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3914 if (IS_ERR(fep->clk_ahb)) { 3915 ret = PTR_ERR(fep->clk_ahb); 3916 goto failed_clk; 3917 } 3918 3919 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3920 3921 /* enet_out is optional, depends on board */ 3922 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out"); 3923 if (IS_ERR(fep->clk_enet_out)) { 3924 ret = PTR_ERR(fep->clk_enet_out); 3925 goto failed_clk; 3926 } 3927 3928 fep->ptp_clk_on = false; 3929 mutex_init(&fep->ptp_clk_mutex); 3930 3931 /* clk_ref is optional, depends on board */ 3932 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref"); 3933 if (IS_ERR(fep->clk_ref)) { 3934 ret = PTR_ERR(fep->clk_ref); 3935 goto failed_clk; 3936 } 3937 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 3938 3939 /* clk_2x_txclk is optional, depends on board */ 3940 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 3941 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 3942 if (IS_ERR(fep->clk_2x_txclk)) 3943 fep->clk_2x_txclk = NULL; 3944 } 3945 3946 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3947 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3948 if (IS_ERR(fep->clk_ptp)) { 3949 fep->clk_ptp = NULL; 3950 fep->bufdesc_ex = false; 3951 } 3952 3953 ret = fec_enet_clk_enable(ndev, true); 3954 if (ret) 3955 goto failed_clk; 3956 3957 ret = clk_prepare_enable(fep->clk_ipg); 3958 if (ret) 3959 goto failed_clk_ipg; 3960 ret = clk_prepare_enable(fep->clk_ahb); 3961 if (ret) 3962 goto failed_clk_ahb; 3963 3964 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 3965 if (!IS_ERR(fep->reg_phy)) { 3966 ret = regulator_enable(fep->reg_phy); 3967 if (ret) { 3968 dev_err(&pdev->dev, 3969 "Failed to enable phy regulator: %d\n", ret); 3970 goto failed_regulator; 3971 } 3972 } else { 3973 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 3974 ret = -EPROBE_DEFER; 3975 goto failed_regulator; 3976 } 3977 fep->reg_phy = NULL; 3978 } 3979 3980 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3981 pm_runtime_use_autosuspend(&pdev->dev); 3982 pm_runtime_get_noresume(&pdev->dev); 3983 pm_runtime_set_active(&pdev->dev); 3984 pm_runtime_enable(&pdev->dev); 3985 3986 ret = fec_reset_phy(pdev); 3987 if (ret) 3988 goto failed_reset; 3989 3990 irq_cnt = fec_enet_get_irq_cnt(pdev); 3991 if (fep->bufdesc_ex) 3992 fec_ptp_init(pdev, irq_cnt); 3993 3994 ret = fec_enet_init(ndev); 3995 if (ret) 3996 goto failed_init; 3997 3998 for (i = 0; i < irq_cnt; i++) { 3999 snprintf(irq_name, sizeof(irq_name), "int%d", i); 4000 irq = platform_get_irq_byname_optional(pdev, irq_name); 4001 if (irq < 0) 4002 irq = platform_get_irq(pdev, i); 4003 if (irq < 0) { 4004 ret = irq; 4005 goto failed_irq; 4006 } 4007 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 4008 0, pdev->name, ndev); 4009 if (ret) 4010 goto failed_irq; 4011 4012 fep->irq[i] = irq; 4013 } 4014 4015 /* Decide which interrupt line is wakeup capable */ 4016 fec_enet_get_wakeup_irq(pdev); 4017 4018 ret = fec_enet_mii_init(pdev); 4019 if (ret) 4020 goto failed_mii_init; 4021 4022 /* Carrier starts down, phylib will bring it up */ 4023 netif_carrier_off(ndev); 4024 fec_enet_clk_enable(ndev, false); 4025 pinctrl_pm_select_sleep_state(&pdev->dev); 4026 4027 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN; 4028 4029 ret = register_netdev(ndev); 4030 if (ret) 4031 goto failed_register; 4032 4033 device_init_wakeup(&ndev->dev, fep->wol_flag & 4034 FEC_WOL_HAS_MAGIC_PACKET); 4035 4036 if (fep->bufdesc_ex && fep->ptp_clock) 4037 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 4038 4039 fep->rx_copybreak = COPYBREAK_DEFAULT; 4040 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 4041 4042 pm_runtime_mark_last_busy(&pdev->dev); 4043 pm_runtime_put_autosuspend(&pdev->dev); 4044 4045 return 0; 4046 4047 failed_register: 4048 fec_enet_mii_remove(fep); 4049 failed_mii_init: 4050 failed_irq: 4051 failed_init: 4052 fec_ptp_stop(pdev); 4053 failed_reset: 4054 pm_runtime_put_noidle(&pdev->dev); 4055 pm_runtime_disable(&pdev->dev); 4056 if (fep->reg_phy) 4057 regulator_disable(fep->reg_phy); 4058 failed_regulator: 4059 clk_disable_unprepare(fep->clk_ahb); 4060 failed_clk_ahb: 4061 clk_disable_unprepare(fep->clk_ipg); 4062 failed_clk_ipg: 4063 fec_enet_clk_enable(ndev, false); 4064 failed_clk: 4065 failed_rgmii_delay: 4066 if (of_phy_is_fixed_link(np)) 4067 of_phy_deregister_fixed_link(np); 4068 of_node_put(phy_node); 4069 failed_stop_mode: 4070 failed_ipc_init: 4071 failed_phy: 4072 dev_id--; 4073 failed_ioremap: 4074 free_netdev(ndev); 4075 4076 return ret; 4077 } 4078 4079 static int 4080 fec_drv_remove(struct platform_device *pdev) 4081 { 4082 struct net_device *ndev = platform_get_drvdata(pdev); 4083 struct fec_enet_private *fep = netdev_priv(ndev); 4084 struct device_node *np = pdev->dev.of_node; 4085 int ret; 4086 4087 ret = pm_runtime_resume_and_get(&pdev->dev); 4088 if (ret < 0) 4089 return ret; 4090 4091 cancel_work_sync(&fep->tx_timeout_work); 4092 fec_ptp_stop(pdev); 4093 unregister_netdev(ndev); 4094 fec_enet_mii_remove(fep); 4095 if (fep->reg_phy) 4096 regulator_disable(fep->reg_phy); 4097 4098 if (of_phy_is_fixed_link(np)) 4099 of_phy_deregister_fixed_link(np); 4100 of_node_put(fep->phy_node); 4101 4102 clk_disable_unprepare(fep->clk_ahb); 4103 clk_disable_unprepare(fep->clk_ipg); 4104 pm_runtime_put_noidle(&pdev->dev); 4105 pm_runtime_disable(&pdev->dev); 4106 4107 free_netdev(ndev); 4108 return 0; 4109 } 4110 4111 static int __maybe_unused fec_suspend(struct device *dev) 4112 { 4113 struct net_device *ndev = dev_get_drvdata(dev); 4114 struct fec_enet_private *fep = netdev_priv(ndev); 4115 int ret; 4116 4117 rtnl_lock(); 4118 if (netif_running(ndev)) { 4119 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4120 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4121 phy_stop(ndev->phydev); 4122 napi_disable(&fep->napi); 4123 netif_tx_lock_bh(ndev); 4124 netif_device_detach(ndev); 4125 netif_tx_unlock_bh(ndev); 4126 fec_stop(ndev); 4127 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4128 fec_irqs_disable(ndev); 4129 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4130 } else { 4131 fec_irqs_disable_except_wakeup(ndev); 4132 if (fep->wake_irq > 0) { 4133 disable_irq(fep->wake_irq); 4134 enable_irq_wake(fep->wake_irq); 4135 } 4136 fec_enet_stop_mode(fep, true); 4137 } 4138 /* It's safe to disable clocks since interrupts are masked */ 4139 fec_enet_clk_enable(ndev, false); 4140 4141 fep->rpm_active = !pm_runtime_status_suspended(dev); 4142 if (fep->rpm_active) { 4143 ret = pm_runtime_force_suspend(dev); 4144 if (ret < 0) { 4145 rtnl_unlock(); 4146 return ret; 4147 } 4148 } 4149 } 4150 rtnl_unlock(); 4151 4152 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4153 regulator_disable(fep->reg_phy); 4154 4155 /* SOC supply clock to phy, when clock is disabled, phy link down 4156 * SOC control phy regulator, when regulator is disabled, phy link down 4157 */ 4158 if (fep->clk_enet_out || fep->reg_phy) 4159 fep->link = 0; 4160 4161 return 0; 4162 } 4163 4164 static int __maybe_unused fec_resume(struct device *dev) 4165 { 4166 struct net_device *ndev = dev_get_drvdata(dev); 4167 struct fec_enet_private *fep = netdev_priv(ndev); 4168 int ret; 4169 int val; 4170 4171 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4172 ret = regulator_enable(fep->reg_phy); 4173 if (ret) 4174 return ret; 4175 } 4176 4177 rtnl_lock(); 4178 if (netif_running(ndev)) { 4179 if (fep->rpm_active) 4180 pm_runtime_force_resume(dev); 4181 4182 ret = fec_enet_clk_enable(ndev, true); 4183 if (ret) { 4184 rtnl_unlock(); 4185 goto failed_clk; 4186 } 4187 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4188 fec_enet_stop_mode(fep, false); 4189 if (fep->wake_irq) { 4190 disable_irq_wake(fep->wake_irq); 4191 enable_irq(fep->wake_irq); 4192 } 4193 4194 val = readl(fep->hwp + FEC_ECNTRL); 4195 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4196 writel(val, fep->hwp + FEC_ECNTRL); 4197 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4198 } else { 4199 pinctrl_pm_select_default_state(&fep->pdev->dev); 4200 } 4201 fec_restart(ndev); 4202 netif_tx_lock_bh(ndev); 4203 netif_device_attach(ndev); 4204 netif_tx_unlock_bh(ndev); 4205 napi_enable(&fep->napi); 4206 phy_init_hw(ndev->phydev); 4207 phy_start(ndev->phydev); 4208 } 4209 rtnl_unlock(); 4210 4211 return 0; 4212 4213 failed_clk: 4214 if (fep->reg_phy) 4215 regulator_disable(fep->reg_phy); 4216 return ret; 4217 } 4218 4219 static int __maybe_unused fec_runtime_suspend(struct device *dev) 4220 { 4221 struct net_device *ndev = dev_get_drvdata(dev); 4222 struct fec_enet_private *fep = netdev_priv(ndev); 4223 4224 clk_disable_unprepare(fep->clk_ahb); 4225 clk_disable_unprepare(fep->clk_ipg); 4226 4227 return 0; 4228 } 4229 4230 static int __maybe_unused fec_runtime_resume(struct device *dev) 4231 { 4232 struct net_device *ndev = dev_get_drvdata(dev); 4233 struct fec_enet_private *fep = netdev_priv(ndev); 4234 int ret; 4235 4236 ret = clk_prepare_enable(fep->clk_ahb); 4237 if (ret) 4238 return ret; 4239 ret = clk_prepare_enable(fep->clk_ipg); 4240 if (ret) 4241 goto failed_clk_ipg; 4242 4243 return 0; 4244 4245 failed_clk_ipg: 4246 clk_disable_unprepare(fep->clk_ahb); 4247 return ret; 4248 } 4249 4250 static const struct dev_pm_ops fec_pm_ops = { 4251 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4252 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4253 }; 4254 4255 static struct platform_driver fec_driver = { 4256 .driver = { 4257 .name = DRIVER_NAME, 4258 .pm = &fec_pm_ops, 4259 .of_match_table = fec_dt_ids, 4260 .suppress_bind_attrs = true, 4261 }, 4262 .id_table = fec_devtype, 4263 .probe = fec_probe, 4264 .remove = fec_drv_remove, 4265 }; 4266 4267 module_platform_driver(fec_driver); 4268 4269 MODULE_LICENSE("GPL"); 4270