1 /* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 * 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/string.h> 27 #include <linux/ptrace.h> 28 #include <linux/errno.h> 29 #include <linux/ioport.h> 30 #include <linux/slab.h> 31 #include <linux/interrupt.h> 32 #include <linux/delay.h> 33 #include <linux/netdevice.h> 34 #include <linux/etherdevice.h> 35 #include <linux/skbuff.h> 36 #include <linux/in.h> 37 #include <linux/ip.h> 38 #include <net/ip.h> 39 #include <linux/tcp.h> 40 #include <linux/udp.h> 41 #include <linux/icmp.h> 42 #include <linux/spinlock.h> 43 #include <linux/workqueue.h> 44 #include <linux/bitops.h> 45 #include <linux/io.h> 46 #include <linux/irq.h> 47 #include <linux/clk.h> 48 #include <linux/platform_device.h> 49 #include <linux/phy.h> 50 #include <linux/fec.h> 51 #include <linux/of.h> 52 #include <linux/of_device.h> 53 #include <linux/of_gpio.h> 54 #include <linux/of_net.h> 55 #include <linux/regulator/consumer.h> 56 #include <linux/if_vlan.h> 57 58 #include <asm/cacheflush.h> 59 60 #include "fec.h" 61 62 static void set_multicast_list(struct net_device *ndev); 63 64 #if defined(CONFIG_ARM) 65 #define FEC_ALIGNMENT 0xf 66 #else 67 #define FEC_ALIGNMENT 0x3 68 #endif 69 70 #define DRIVER_NAME "fec" 71 72 /* Pause frame feild and FIFO threshold */ 73 #define FEC_ENET_FCE (1 << 5) 74 #define FEC_ENET_RSEM_V 0x84 75 #define FEC_ENET_RSFL_V 16 76 #define FEC_ENET_RAEM_V 0x8 77 #define FEC_ENET_RAFL_V 0x8 78 #define FEC_ENET_OPD_V 0xFFF0 79 80 /* Controller is ENET-MAC */ 81 #define FEC_QUIRK_ENET_MAC (1 << 0) 82 /* Controller needs driver to swap frame */ 83 #define FEC_QUIRK_SWAP_FRAME (1 << 1) 84 /* Controller uses gasket */ 85 #define FEC_QUIRK_USE_GASKET (1 << 2) 86 /* Controller has GBIT support */ 87 #define FEC_QUIRK_HAS_GBIT (1 << 3) 88 /* Controller has extend desc buffer */ 89 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) 90 /* Controller has hardware checksum support */ 91 #define FEC_QUIRK_HAS_CSUM (1 << 5) 92 /* Controller has hardware vlan support */ 93 #define FEC_QUIRK_HAS_VLAN (1 << 6) 94 /* ENET IP errata ERR006358 95 * 96 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously 97 * detected as not set during a prior frame transmission, then the 98 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs 99 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in 100 * frames not being transmitted until there is a 0-to-1 transition on 101 * ENET_TDAR[TDAR]. 102 */ 103 #define FEC_QUIRK_ERR006358 (1 << 7) 104 105 static struct platform_device_id fec_devtype[] = { 106 { 107 /* keep it for coldfire */ 108 .name = DRIVER_NAME, 109 .driver_data = 0, 110 }, { 111 .name = "imx25-fec", 112 .driver_data = FEC_QUIRK_USE_GASKET, 113 }, { 114 .name = "imx27-fec", 115 .driver_data = 0, 116 }, { 117 .name = "imx28-fec", 118 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, 119 }, { 120 .name = "imx6q-fec", 121 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 122 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 123 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358, 124 }, { 125 .name = "mvf600-fec", 126 .driver_data = FEC_QUIRK_ENET_MAC, 127 }, { 128 /* sentinel */ 129 } 130 }; 131 MODULE_DEVICE_TABLE(platform, fec_devtype); 132 133 enum imx_fec_type { 134 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 135 IMX27_FEC, /* runs on i.mx27/35/51 */ 136 IMX28_FEC, 137 IMX6Q_FEC, 138 MVF600_FEC, 139 }; 140 141 static const struct of_device_id fec_dt_ids[] = { 142 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 143 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 144 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 145 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 146 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 147 { /* sentinel */ } 148 }; 149 MODULE_DEVICE_TABLE(of, fec_dt_ids); 150 151 static unsigned char macaddr[ETH_ALEN]; 152 module_param_array(macaddr, byte, NULL, 0); 153 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 154 155 #if defined(CONFIG_M5272) 156 /* 157 * Some hardware gets it MAC address out of local flash memory. 158 * if this is non-zero then assume it is the address to get MAC from. 159 */ 160 #if defined(CONFIG_NETtel) 161 #define FEC_FLASHMAC 0xf0006006 162 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 163 #define FEC_FLASHMAC 0xf0006000 164 #elif defined(CONFIG_CANCam) 165 #define FEC_FLASHMAC 0xf0020000 166 #elif defined (CONFIG_M5272C3) 167 #define FEC_FLASHMAC (0xffe04000 + 4) 168 #elif defined(CONFIG_MOD5272) 169 #define FEC_FLASHMAC 0xffc0406b 170 #else 171 #define FEC_FLASHMAC 0 172 #endif 173 #endif /* CONFIG_M5272 */ 174 175 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE) 176 #error "FEC: descriptor ring size constants too large" 177 #endif 178 179 /* Interrupt events/masks. */ 180 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ 181 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ 182 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ 183 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ 184 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ 185 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ 186 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ 187 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ 188 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ 189 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ 190 191 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) 192 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) 193 194 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 195 */ 196 #define PKT_MAXBUF_SIZE 1522 197 #define PKT_MINBUF_SIZE 64 198 #define PKT_MAXBLR_SIZE 1536 199 200 /* FEC receive acceleration */ 201 #define FEC_RACC_IPDIS (1 << 1) 202 #define FEC_RACC_PRODIS (1 << 2) 203 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 204 205 /* 206 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 207 * size bits. Other FEC hardware does not, so we need to take that into 208 * account when setting it. 209 */ 210 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 211 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 212 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 213 #else 214 #define OPT_FRAME_SIZE 0 215 #endif 216 217 /* FEC MII MMFR bits definition */ 218 #define FEC_MMFR_ST (1 << 30) 219 #define FEC_MMFR_OP_READ (2 << 28) 220 #define FEC_MMFR_OP_WRITE (1 << 28) 221 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 222 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 223 #define FEC_MMFR_TA (2 << 16) 224 #define FEC_MMFR_DATA(v) (v & 0xffff) 225 226 #define FEC_MII_TIMEOUT 30000 /* us */ 227 228 /* Transmitter timeout */ 229 #define TX_TIMEOUT (2 * HZ) 230 231 #define FEC_PAUSE_FLAG_AUTONEG 0x1 232 #define FEC_PAUSE_FLAG_ENABLE 0x2 233 234 static int mii_cnt; 235 236 static inline 237 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep) 238 { 239 struct bufdesc *new_bd = bdp + 1; 240 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1; 241 struct bufdesc_ex *ex_base; 242 struct bufdesc *base; 243 int ring_size; 244 245 if (bdp >= fep->tx_bd_base) { 246 base = fep->tx_bd_base; 247 ring_size = fep->tx_ring_size; 248 ex_base = (struct bufdesc_ex *)fep->tx_bd_base; 249 } else { 250 base = fep->rx_bd_base; 251 ring_size = fep->rx_ring_size; 252 ex_base = (struct bufdesc_ex *)fep->rx_bd_base; 253 } 254 255 if (fep->bufdesc_ex) 256 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ? 257 ex_base : ex_new_bd); 258 else 259 return (new_bd >= (base + ring_size)) ? 260 base : new_bd; 261 } 262 263 static inline 264 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep) 265 { 266 struct bufdesc *new_bd = bdp - 1; 267 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1; 268 struct bufdesc_ex *ex_base; 269 struct bufdesc *base; 270 int ring_size; 271 272 if (bdp >= fep->tx_bd_base) { 273 base = fep->tx_bd_base; 274 ring_size = fep->tx_ring_size; 275 ex_base = (struct bufdesc_ex *)fep->tx_bd_base; 276 } else { 277 base = fep->rx_bd_base; 278 ring_size = fep->rx_ring_size; 279 ex_base = (struct bufdesc_ex *)fep->rx_bd_base; 280 } 281 282 if (fep->bufdesc_ex) 283 return (struct bufdesc *)((ex_new_bd < ex_base) ? 284 (ex_new_bd + ring_size) : ex_new_bd); 285 else 286 return (new_bd < base) ? (new_bd + ring_size) : new_bd; 287 } 288 289 static void *swap_buffer(void *bufaddr, int len) 290 { 291 int i; 292 unsigned int *buf = bufaddr; 293 294 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++) 295 *buf = cpu_to_be32(*buf); 296 297 return bufaddr; 298 } 299 300 static int 301 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 302 { 303 /* Only run for packets requiring a checksum. */ 304 if (skb->ip_summed != CHECKSUM_PARTIAL) 305 return 0; 306 307 if (unlikely(skb_cow_head(skb, 0))) 308 return -1; 309 310 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 311 312 return 0; 313 } 314 315 static netdev_tx_t 316 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 317 { 318 struct fec_enet_private *fep = netdev_priv(ndev); 319 const struct platform_device_id *id_entry = 320 platform_get_device_id(fep->pdev); 321 struct bufdesc *bdp, *bdp_pre; 322 void *bufaddr; 323 unsigned short status; 324 unsigned int index; 325 326 /* Fill in a Tx ring entry */ 327 bdp = fep->cur_tx; 328 329 status = bdp->cbd_sc; 330 331 if (status & BD_ENET_TX_READY) { 332 /* Ooops. All transmit buffers are full. Bail out. 333 * This should not happen, since ndev->tbusy should be set. 334 */ 335 netdev_err(ndev, "tx queue full!\n"); 336 return NETDEV_TX_BUSY; 337 } 338 339 /* Protocol checksum off-load for TCP and UDP. */ 340 if (fec_enet_clear_csum(skb, ndev)) { 341 kfree_skb(skb); 342 return NETDEV_TX_OK; 343 } 344 345 /* Clear all of the status flags */ 346 status &= ~BD_ENET_TX_STATS; 347 348 /* Set buffer length and buffer pointer */ 349 bufaddr = skb->data; 350 bdp->cbd_datlen = skb->len; 351 352 /* 353 * On some FEC implementations data must be aligned on 354 * 4-byte boundaries. Use bounce buffers to copy data 355 * and get it aligned. Ugh. 356 */ 357 if (fep->bufdesc_ex) 358 index = (struct bufdesc_ex *)bdp - 359 (struct bufdesc_ex *)fep->tx_bd_base; 360 else 361 index = bdp - fep->tx_bd_base; 362 363 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { 364 memcpy(fep->tx_bounce[index], skb->data, skb->len); 365 bufaddr = fep->tx_bounce[index]; 366 } 367 368 /* 369 * Some design made an incorrect assumption on endian mode of 370 * the system that it's running on. As the result, driver has to 371 * swap every frame going to and coming from the controller. 372 */ 373 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 374 swap_buffer(bufaddr, skb->len); 375 376 /* Save skb pointer */ 377 fep->tx_skbuff[index] = skb; 378 379 /* Push the data cache so the CPM does not get stale memory 380 * data. 381 */ 382 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, 383 skb->len, DMA_TO_DEVICE); 384 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) { 385 bdp->cbd_bufaddr = 0; 386 fep->tx_skbuff[index] = NULL; 387 dev_kfree_skb_any(skb); 388 if (net_ratelimit()) 389 netdev_err(ndev, "Tx DMA memory map failed\n"); 390 return NETDEV_TX_OK; 391 } 392 393 if (fep->bufdesc_ex) { 394 395 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 396 ebdp->cbd_bdu = 0; 397 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 398 fep->hwts_tx_en)) { 399 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT); 400 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 401 } else { 402 ebdp->cbd_esc = BD_ENET_TX_INT; 403 404 /* Enable protocol checksum flags 405 * We do not bother with the IP Checksum bits as they 406 * are done by the kernel 407 */ 408 if (skb->ip_summed == CHECKSUM_PARTIAL) 409 ebdp->cbd_esc |= BD_ENET_TX_PINS; 410 } 411 } 412 413 /* Send it on its way. Tell FEC it's ready, interrupt when done, 414 * it's the last BD of the frame, and to put the CRC on the end. 415 */ 416 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR 417 | BD_ENET_TX_LAST | BD_ENET_TX_TC); 418 bdp->cbd_sc = status; 419 420 bdp_pre = fec_enet_get_prevdesc(bdp, fep); 421 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) && 422 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) { 423 fep->delay_work.trig_tx = true; 424 schedule_delayed_work(&(fep->delay_work.delay_work), 425 msecs_to_jiffies(1)); 426 } 427 428 /* If this was the last BD in the ring, start at the beginning again. */ 429 bdp = fec_enet_get_nextdesc(bdp, fep); 430 431 skb_tx_timestamp(skb); 432 433 fep->cur_tx = bdp; 434 435 if (fep->cur_tx == fep->dirty_tx) 436 netif_stop_queue(ndev); 437 438 /* Trigger transmission start */ 439 writel(0, fep->hwp + FEC_X_DES_ACTIVE); 440 441 return NETDEV_TX_OK; 442 } 443 444 /* Init RX & TX buffer descriptors 445 */ 446 static void fec_enet_bd_init(struct net_device *dev) 447 { 448 struct fec_enet_private *fep = netdev_priv(dev); 449 struct bufdesc *bdp; 450 unsigned int i; 451 452 /* Initialize the receive buffer descriptors. */ 453 bdp = fep->rx_bd_base; 454 for (i = 0; i < fep->rx_ring_size; i++) { 455 456 /* Initialize the BD for every fragment in the page. */ 457 if (bdp->cbd_bufaddr) 458 bdp->cbd_sc = BD_ENET_RX_EMPTY; 459 else 460 bdp->cbd_sc = 0; 461 bdp = fec_enet_get_nextdesc(bdp, fep); 462 } 463 464 /* Set the last buffer to wrap */ 465 bdp = fec_enet_get_prevdesc(bdp, fep); 466 bdp->cbd_sc |= BD_SC_WRAP; 467 468 fep->cur_rx = fep->rx_bd_base; 469 470 /* ...and the same for transmit */ 471 bdp = fep->tx_bd_base; 472 fep->cur_tx = bdp; 473 for (i = 0; i < fep->tx_ring_size; i++) { 474 475 /* Initialize the BD for every fragment in the page. */ 476 bdp->cbd_sc = 0; 477 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) { 478 dev_kfree_skb_any(fep->tx_skbuff[i]); 479 fep->tx_skbuff[i] = NULL; 480 } 481 bdp->cbd_bufaddr = 0; 482 bdp = fec_enet_get_nextdesc(bdp, fep); 483 } 484 485 /* Set the last buffer to wrap */ 486 bdp = fec_enet_get_prevdesc(bdp, fep); 487 bdp->cbd_sc |= BD_SC_WRAP; 488 fep->dirty_tx = bdp; 489 } 490 491 /* This function is called to start or restart the FEC during a link 492 * change. This only happens when switching between half and full 493 * duplex. 494 */ 495 static void 496 fec_restart(struct net_device *ndev, int duplex) 497 { 498 struct fec_enet_private *fep = netdev_priv(ndev); 499 const struct platform_device_id *id_entry = 500 platform_get_device_id(fep->pdev); 501 int i; 502 u32 val; 503 u32 temp_mac[2]; 504 u32 rcntl = OPT_FRAME_SIZE | 0x04; 505 u32 ecntl = 0x2; /* ETHEREN */ 506 507 if (netif_running(ndev)) { 508 netif_device_detach(ndev); 509 napi_disable(&fep->napi); 510 netif_stop_queue(ndev); 511 netif_tx_lock_bh(ndev); 512 } 513 514 /* Whack a reset. We should wait for this. */ 515 writel(1, fep->hwp + FEC_ECNTRL); 516 udelay(10); 517 518 /* 519 * enet-mac reset will reset mac address registers too, 520 * so need to reconfigure it. 521 */ 522 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 523 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 524 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); 525 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); 526 } 527 528 /* Clear any outstanding interrupt. */ 529 writel(0xffc00000, fep->hwp + FEC_IEVENT); 530 531 /* Set maximum receive buffer size. */ 532 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); 533 534 fec_enet_bd_init(ndev); 535 536 /* Set receive and transmit descriptor base. */ 537 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); 538 if (fep->bufdesc_ex) 539 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex) 540 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START); 541 else 542 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) 543 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START); 544 545 546 for (i = 0; i <= TX_RING_MOD_MASK; i++) { 547 if (fep->tx_skbuff[i]) { 548 dev_kfree_skb_any(fep->tx_skbuff[i]); 549 fep->tx_skbuff[i] = NULL; 550 } 551 } 552 553 /* Enable MII mode */ 554 if (duplex) { 555 /* FD enable */ 556 writel(0x04, fep->hwp + FEC_X_CNTRL); 557 } else { 558 /* No Rcv on Xmit */ 559 rcntl |= 0x02; 560 writel(0x0, fep->hwp + FEC_X_CNTRL); 561 } 562 563 fep->full_duplex = duplex; 564 565 /* Set MII speed */ 566 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 567 568 #if !defined(CONFIG_M5272) 569 /* set RX checksum */ 570 val = readl(fep->hwp + FEC_RACC); 571 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 572 val |= FEC_RACC_OPTIONS; 573 else 574 val &= ~FEC_RACC_OPTIONS; 575 writel(val, fep->hwp + FEC_RACC); 576 #endif 577 578 /* 579 * The phy interface and speed need to get configured 580 * differently on enet-mac. 581 */ 582 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 583 /* Enable flow control and length check */ 584 rcntl |= 0x40000000 | 0x00000020; 585 586 /* RGMII, RMII or MII */ 587 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) 588 rcntl |= (1 << 6); 589 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 590 rcntl |= (1 << 8); 591 else 592 rcntl &= ~(1 << 8); 593 594 /* 1G, 100M or 10M */ 595 if (fep->phy_dev) { 596 if (fep->phy_dev->speed == SPEED_1000) 597 ecntl |= (1 << 5); 598 else if (fep->phy_dev->speed == SPEED_100) 599 rcntl &= ~(1 << 9); 600 else 601 rcntl |= (1 << 9); 602 } 603 } else { 604 #ifdef FEC_MIIGSK_ENR 605 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { 606 u32 cfgr; 607 /* disable the gasket and wait */ 608 writel(0, fep->hwp + FEC_MIIGSK_ENR); 609 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 610 udelay(1); 611 612 /* 613 * configure the gasket: 614 * RMII, 50 MHz, no loopback, no echo 615 * MII, 25 MHz, no loopback, no echo 616 */ 617 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 618 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 619 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) 620 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 621 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 622 623 /* re-enable the gasket */ 624 writel(2, fep->hwp + FEC_MIIGSK_ENR); 625 } 626 #endif 627 } 628 629 #if !defined(CONFIG_M5272) 630 /* enable pause frame*/ 631 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 632 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 633 fep->phy_dev && fep->phy_dev->pause)) { 634 rcntl |= FEC_ENET_FCE; 635 636 /* set FIFO threshold parameter to reduce overrun */ 637 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 638 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 639 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 640 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 641 642 /* OPD */ 643 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 644 } else { 645 rcntl &= ~FEC_ENET_FCE; 646 } 647 #endif /* !defined(CONFIG_M5272) */ 648 649 writel(rcntl, fep->hwp + FEC_R_CNTRL); 650 651 /* Setup multicast filter. */ 652 set_multicast_list(ndev); 653 #ifndef CONFIG_M5272 654 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 655 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 656 #endif 657 658 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 659 /* enable ENET endian swap */ 660 ecntl |= (1 << 8); 661 /* enable ENET store and forward mode */ 662 writel(1 << 8, fep->hwp + FEC_X_WMRK); 663 } 664 665 if (fep->bufdesc_ex) 666 ecntl |= (1 << 4); 667 668 #ifndef CONFIG_M5272 669 /* Enable the MIB statistic event counters */ 670 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 671 #endif 672 673 /* And last, enable the transmit and receive processing */ 674 writel(ecntl, fep->hwp + FEC_ECNTRL); 675 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 676 677 if (fep->bufdesc_ex) 678 fec_ptp_start_cyclecounter(ndev); 679 680 /* Enable interrupts we wish to service */ 681 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 682 683 if (netif_running(ndev)) { 684 netif_tx_unlock_bh(ndev); 685 netif_wake_queue(ndev); 686 napi_enable(&fep->napi); 687 netif_device_attach(ndev); 688 } 689 } 690 691 static void 692 fec_stop(struct net_device *ndev) 693 { 694 struct fec_enet_private *fep = netdev_priv(ndev); 695 const struct platform_device_id *id_entry = 696 platform_get_device_id(fep->pdev); 697 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 698 699 /* We cannot expect a graceful transmit stop without link !!! */ 700 if (fep->link) { 701 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 702 udelay(10); 703 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 704 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 705 } 706 707 /* Whack a reset. We should wait for this. */ 708 writel(1, fep->hwp + FEC_ECNTRL); 709 udelay(10); 710 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 711 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 712 713 /* We have to keep ENET enabled to have MII interrupt stay working */ 714 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 715 writel(2, fep->hwp + FEC_ECNTRL); 716 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 717 } 718 } 719 720 721 static void 722 fec_timeout(struct net_device *ndev) 723 { 724 struct fec_enet_private *fep = netdev_priv(ndev); 725 726 ndev->stats.tx_errors++; 727 728 fep->delay_work.timeout = true; 729 schedule_delayed_work(&(fep->delay_work.delay_work), 0); 730 } 731 732 static void fec_enet_work(struct work_struct *work) 733 { 734 struct fec_enet_private *fep = 735 container_of(work, 736 struct fec_enet_private, 737 delay_work.delay_work.work); 738 739 if (fep->delay_work.timeout) { 740 fep->delay_work.timeout = false; 741 fec_restart(fep->netdev, fep->full_duplex); 742 netif_wake_queue(fep->netdev); 743 } 744 745 if (fep->delay_work.trig_tx) { 746 fep->delay_work.trig_tx = false; 747 writel(0, fep->hwp + FEC_X_DES_ACTIVE); 748 } 749 } 750 751 static void 752 fec_enet_tx(struct net_device *ndev) 753 { 754 struct fec_enet_private *fep; 755 struct bufdesc *bdp; 756 unsigned short status; 757 struct sk_buff *skb; 758 int index = 0; 759 760 fep = netdev_priv(ndev); 761 bdp = fep->dirty_tx; 762 763 /* get next bdp of dirty_tx */ 764 bdp = fec_enet_get_nextdesc(bdp, fep); 765 766 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { 767 768 /* current queue is empty */ 769 if (bdp == fep->cur_tx) 770 break; 771 772 if (fep->bufdesc_ex) 773 index = (struct bufdesc_ex *)bdp - 774 (struct bufdesc_ex *)fep->tx_bd_base; 775 else 776 index = bdp - fep->tx_bd_base; 777 778 skb = fep->tx_skbuff[index]; 779 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, skb->len, 780 DMA_TO_DEVICE); 781 bdp->cbd_bufaddr = 0; 782 783 /* Check for errors. */ 784 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 785 BD_ENET_TX_RL | BD_ENET_TX_UN | 786 BD_ENET_TX_CSL)) { 787 ndev->stats.tx_errors++; 788 if (status & BD_ENET_TX_HB) /* No heartbeat */ 789 ndev->stats.tx_heartbeat_errors++; 790 if (status & BD_ENET_TX_LC) /* Late collision */ 791 ndev->stats.tx_window_errors++; 792 if (status & BD_ENET_TX_RL) /* Retrans limit */ 793 ndev->stats.tx_aborted_errors++; 794 if (status & BD_ENET_TX_UN) /* Underrun */ 795 ndev->stats.tx_fifo_errors++; 796 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 797 ndev->stats.tx_carrier_errors++; 798 } else { 799 ndev->stats.tx_packets++; 800 ndev->stats.tx_bytes += bdp->cbd_datlen; 801 } 802 803 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 804 fep->bufdesc_ex) { 805 struct skb_shared_hwtstamps shhwtstamps; 806 unsigned long flags; 807 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 808 809 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 810 spin_lock_irqsave(&fep->tmreg_lock, flags); 811 shhwtstamps.hwtstamp = ns_to_ktime( 812 timecounter_cyc2time(&fep->tc, ebdp->ts)); 813 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 814 skb_tstamp_tx(skb, &shhwtstamps); 815 } 816 817 if (status & BD_ENET_TX_READY) 818 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n"); 819 820 /* Deferred means some collisions occurred during transmit, 821 * but we eventually sent the packet OK. 822 */ 823 if (status & BD_ENET_TX_DEF) 824 ndev->stats.collisions++; 825 826 /* Free the sk buffer associated with this last transmit */ 827 dev_kfree_skb_any(skb); 828 fep->tx_skbuff[index] = NULL; 829 830 fep->dirty_tx = bdp; 831 832 /* Update pointer to next buffer descriptor to be transmitted */ 833 bdp = fec_enet_get_nextdesc(bdp, fep); 834 835 /* Since we have freed up a buffer, the ring is no longer full 836 */ 837 if (fep->dirty_tx != fep->cur_tx) { 838 if (netif_queue_stopped(ndev)) 839 netif_wake_queue(ndev); 840 } 841 } 842 return; 843 } 844 845 846 /* During a receive, the cur_rx points to the current incoming buffer. 847 * When we update through the ring, if the next incoming buffer has 848 * not been given to the system, we just set the empty indicator, 849 * effectively tossing the packet. 850 */ 851 static int 852 fec_enet_rx(struct net_device *ndev, int budget) 853 { 854 struct fec_enet_private *fep = netdev_priv(ndev); 855 const struct platform_device_id *id_entry = 856 platform_get_device_id(fep->pdev); 857 struct bufdesc *bdp; 858 unsigned short status; 859 struct sk_buff *skb; 860 ushort pkt_len; 861 __u8 *data; 862 int pkt_received = 0; 863 struct bufdesc_ex *ebdp = NULL; 864 bool vlan_packet_rcvd = false; 865 u16 vlan_tag; 866 int index = 0; 867 868 #ifdef CONFIG_M532x 869 flush_cache_all(); 870 #endif 871 872 /* First, grab all of the stats for the incoming packet. 873 * These get messed up if we get called due to a busy condition. 874 */ 875 bdp = fep->cur_rx; 876 877 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { 878 879 if (pkt_received >= budget) 880 break; 881 pkt_received++; 882 883 /* Since we have allocated space to hold a complete frame, 884 * the last indicator should be set. 885 */ 886 if ((status & BD_ENET_RX_LAST) == 0) 887 netdev_err(ndev, "rcv is not +last\n"); 888 889 if (!fep->opened) 890 goto rx_processing_done; 891 892 /* Check for errors. */ 893 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 894 BD_ENET_RX_CR | BD_ENET_RX_OV)) { 895 ndev->stats.rx_errors++; 896 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { 897 /* Frame too long or too short. */ 898 ndev->stats.rx_length_errors++; 899 } 900 if (status & BD_ENET_RX_NO) /* Frame alignment */ 901 ndev->stats.rx_frame_errors++; 902 if (status & BD_ENET_RX_CR) /* CRC Error */ 903 ndev->stats.rx_crc_errors++; 904 if (status & BD_ENET_RX_OV) /* FIFO overrun */ 905 ndev->stats.rx_fifo_errors++; 906 } 907 908 /* Report late collisions as a frame error. 909 * On this error, the BD is closed, but we don't know what we 910 * have in the buffer. So, just drop this frame on the floor. 911 */ 912 if (status & BD_ENET_RX_CL) { 913 ndev->stats.rx_errors++; 914 ndev->stats.rx_frame_errors++; 915 goto rx_processing_done; 916 } 917 918 /* Process the incoming frame. */ 919 ndev->stats.rx_packets++; 920 pkt_len = bdp->cbd_datlen; 921 ndev->stats.rx_bytes += pkt_len; 922 923 if (fep->bufdesc_ex) 924 index = (struct bufdesc_ex *)bdp - 925 (struct bufdesc_ex *)fep->rx_bd_base; 926 else 927 index = bdp - fep->rx_bd_base; 928 data = fep->rx_skbuff[index]->data; 929 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr, 930 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 931 932 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 933 swap_buffer(data, pkt_len); 934 935 /* Extract the enhanced buffer descriptor */ 936 ebdp = NULL; 937 if (fep->bufdesc_ex) 938 ebdp = (struct bufdesc_ex *)bdp; 939 940 /* If this is a VLAN packet remove the VLAN Tag */ 941 vlan_packet_rcvd = false; 942 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 943 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) { 944 /* Push and remove the vlan tag */ 945 struct vlan_hdr *vlan_header = 946 (struct vlan_hdr *) (data + ETH_HLEN); 947 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 948 pkt_len -= VLAN_HLEN; 949 950 vlan_packet_rcvd = true; 951 } 952 953 /* This does 16 byte alignment, exactly what we need. 954 * The packet length includes FCS, but we don't want to 955 * include that when passing upstream as it messes up 956 * bridging applications. 957 */ 958 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); 959 960 if (unlikely(!skb)) { 961 ndev->stats.rx_dropped++; 962 } else { 963 int payload_offset = (2 * ETH_ALEN); 964 skb_reserve(skb, NET_IP_ALIGN); 965 skb_put(skb, pkt_len - 4); /* Make room */ 966 967 /* Extract the frame data without the VLAN header. */ 968 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN)); 969 if (vlan_packet_rcvd) 970 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN; 971 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN), 972 data + payload_offset, 973 pkt_len - 4 - (2 * ETH_ALEN)); 974 975 skb->protocol = eth_type_trans(skb, ndev); 976 977 /* Get receive timestamp from the skb */ 978 if (fep->hwts_rx_en && fep->bufdesc_ex) { 979 struct skb_shared_hwtstamps *shhwtstamps = 980 skb_hwtstamps(skb); 981 unsigned long flags; 982 983 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 984 985 spin_lock_irqsave(&fep->tmreg_lock, flags); 986 shhwtstamps->hwtstamp = ns_to_ktime( 987 timecounter_cyc2time(&fep->tc, ebdp->ts)); 988 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 989 } 990 991 if (fep->bufdesc_ex && 992 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 993 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) { 994 /* don't check it */ 995 skb->ip_summed = CHECKSUM_UNNECESSARY; 996 } else { 997 skb_checksum_none_assert(skb); 998 } 999 } 1000 1001 /* Handle received VLAN packets */ 1002 if (vlan_packet_rcvd) 1003 __vlan_hwaccel_put_tag(skb, 1004 htons(ETH_P_8021Q), 1005 vlan_tag); 1006 1007 napi_gro_receive(&fep->napi, skb); 1008 } 1009 1010 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr, 1011 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1012 rx_processing_done: 1013 /* Clear the status flags for this buffer */ 1014 status &= ~BD_ENET_RX_STATS; 1015 1016 /* Mark the buffer empty */ 1017 status |= BD_ENET_RX_EMPTY; 1018 bdp->cbd_sc = status; 1019 1020 if (fep->bufdesc_ex) { 1021 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1022 1023 ebdp->cbd_esc = BD_ENET_RX_INT; 1024 ebdp->cbd_prot = 0; 1025 ebdp->cbd_bdu = 0; 1026 } 1027 1028 /* Update BD pointer to next entry */ 1029 bdp = fec_enet_get_nextdesc(bdp, fep); 1030 1031 /* Doing this here will keep the FEC running while we process 1032 * incoming frames. On a heavily loaded network, we should be 1033 * able to keep up at the expense of system resources. 1034 */ 1035 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 1036 } 1037 fep->cur_rx = bdp; 1038 1039 return pkt_received; 1040 } 1041 1042 static irqreturn_t 1043 fec_enet_interrupt(int irq, void *dev_id) 1044 { 1045 struct net_device *ndev = dev_id; 1046 struct fec_enet_private *fep = netdev_priv(ndev); 1047 uint int_events; 1048 irqreturn_t ret = IRQ_NONE; 1049 1050 do { 1051 int_events = readl(fep->hwp + FEC_IEVENT); 1052 writel(int_events, fep->hwp + FEC_IEVENT); 1053 1054 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) { 1055 ret = IRQ_HANDLED; 1056 1057 /* Disable the RX interrupt */ 1058 if (napi_schedule_prep(&fep->napi)) { 1059 writel(FEC_RX_DISABLED_IMASK, 1060 fep->hwp + FEC_IMASK); 1061 __napi_schedule(&fep->napi); 1062 } 1063 } 1064 1065 if (int_events & FEC_ENET_MII) { 1066 ret = IRQ_HANDLED; 1067 complete(&fep->mdio_done); 1068 } 1069 } while (int_events); 1070 1071 return ret; 1072 } 1073 1074 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1075 { 1076 struct net_device *ndev = napi->dev; 1077 int pkts = fec_enet_rx(ndev, budget); 1078 struct fec_enet_private *fep = netdev_priv(ndev); 1079 1080 fec_enet_tx(ndev); 1081 1082 if (pkts < budget) { 1083 napi_complete(napi); 1084 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1085 } 1086 return pkts; 1087 } 1088 1089 /* ------------------------------------------------------------------------- */ 1090 static void fec_get_mac(struct net_device *ndev) 1091 { 1092 struct fec_enet_private *fep = netdev_priv(ndev); 1093 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1094 unsigned char *iap, tmpaddr[ETH_ALEN]; 1095 1096 /* 1097 * try to get mac address in following order: 1098 * 1099 * 1) module parameter via kernel command line in form 1100 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1101 */ 1102 iap = macaddr; 1103 1104 /* 1105 * 2) from device tree data 1106 */ 1107 if (!is_valid_ether_addr(iap)) { 1108 struct device_node *np = fep->pdev->dev.of_node; 1109 if (np) { 1110 const char *mac = of_get_mac_address(np); 1111 if (mac) 1112 iap = (unsigned char *) mac; 1113 } 1114 } 1115 1116 /* 1117 * 3) from flash or fuse (via platform data) 1118 */ 1119 if (!is_valid_ether_addr(iap)) { 1120 #ifdef CONFIG_M5272 1121 if (FEC_FLASHMAC) 1122 iap = (unsigned char *)FEC_FLASHMAC; 1123 #else 1124 if (pdata) 1125 iap = (unsigned char *)&pdata->mac; 1126 #endif 1127 } 1128 1129 /* 1130 * 4) FEC mac registers set by bootloader 1131 */ 1132 if (!is_valid_ether_addr(iap)) { 1133 *((__be32 *) &tmpaddr[0]) = 1134 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1135 *((__be16 *) &tmpaddr[4]) = 1136 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1137 iap = &tmpaddr[0]; 1138 } 1139 1140 /* 1141 * 5) random mac address 1142 */ 1143 if (!is_valid_ether_addr(iap)) { 1144 /* Report it and use a random ethernet address instead */ 1145 netdev_err(ndev, "Invalid MAC address: %pM\n", iap); 1146 eth_hw_addr_random(ndev); 1147 netdev_info(ndev, "Using random MAC address: %pM\n", 1148 ndev->dev_addr); 1149 return; 1150 } 1151 1152 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1153 1154 /* Adjust MAC if using macaddr */ 1155 if (iap == macaddr) 1156 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1157 } 1158 1159 /* ------------------------------------------------------------------------- */ 1160 1161 /* 1162 * Phy section 1163 */ 1164 static void fec_enet_adjust_link(struct net_device *ndev) 1165 { 1166 struct fec_enet_private *fep = netdev_priv(ndev); 1167 struct phy_device *phy_dev = fep->phy_dev; 1168 int status_change = 0; 1169 1170 /* Prevent a state halted on mii error */ 1171 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 1172 phy_dev->state = PHY_RESUMING; 1173 return; 1174 } 1175 1176 if (phy_dev->link) { 1177 if (!fep->link) { 1178 fep->link = phy_dev->link; 1179 status_change = 1; 1180 } 1181 1182 if (fep->full_duplex != phy_dev->duplex) 1183 status_change = 1; 1184 1185 if (phy_dev->speed != fep->speed) { 1186 fep->speed = phy_dev->speed; 1187 status_change = 1; 1188 } 1189 1190 /* if any of the above changed restart the FEC */ 1191 if (status_change) 1192 fec_restart(ndev, phy_dev->duplex); 1193 } else { 1194 if (fep->link) { 1195 fec_stop(ndev); 1196 fep->link = phy_dev->link; 1197 status_change = 1; 1198 } 1199 } 1200 1201 if (status_change) 1202 phy_print_status(phy_dev); 1203 } 1204 1205 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1206 { 1207 struct fec_enet_private *fep = bus->priv; 1208 unsigned long time_left; 1209 1210 fep->mii_timeout = 0; 1211 init_completion(&fep->mdio_done); 1212 1213 /* start a read op */ 1214 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 1215 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1216 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1217 1218 /* wait for end of transfer */ 1219 time_left = wait_for_completion_timeout(&fep->mdio_done, 1220 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1221 if (time_left == 0) { 1222 fep->mii_timeout = 1; 1223 netdev_err(fep->netdev, "MDIO read timeout\n"); 1224 return -ETIMEDOUT; 1225 } 1226 1227 /* return value */ 1228 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1229 } 1230 1231 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1232 u16 value) 1233 { 1234 struct fec_enet_private *fep = bus->priv; 1235 unsigned long time_left; 1236 1237 fep->mii_timeout = 0; 1238 init_completion(&fep->mdio_done); 1239 1240 /* start a write op */ 1241 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 1242 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1243 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1244 fep->hwp + FEC_MII_DATA); 1245 1246 /* wait for end of transfer */ 1247 time_left = wait_for_completion_timeout(&fep->mdio_done, 1248 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1249 if (time_left == 0) { 1250 fep->mii_timeout = 1; 1251 netdev_err(fep->netdev, "MDIO write timeout\n"); 1252 return -ETIMEDOUT; 1253 } 1254 1255 return 0; 1256 } 1257 1258 static int fec_enet_mdio_reset(struct mii_bus *bus) 1259 { 1260 return 0; 1261 } 1262 1263 static int fec_enet_mii_probe(struct net_device *ndev) 1264 { 1265 struct fec_enet_private *fep = netdev_priv(ndev); 1266 const struct platform_device_id *id_entry = 1267 platform_get_device_id(fep->pdev); 1268 struct phy_device *phy_dev = NULL; 1269 char mdio_bus_id[MII_BUS_ID_SIZE]; 1270 char phy_name[MII_BUS_ID_SIZE + 3]; 1271 int phy_id; 1272 int dev_id = fep->dev_id; 1273 1274 fep->phy_dev = NULL; 1275 1276 /* check for attached phy */ 1277 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1278 if ((fep->mii_bus->phy_mask & (1 << phy_id))) 1279 continue; 1280 if (fep->mii_bus->phy_map[phy_id] == NULL) 1281 continue; 1282 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) 1283 continue; 1284 if (dev_id--) 1285 continue; 1286 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1287 break; 1288 } 1289 1290 if (phy_id >= PHY_MAX_ADDR) { 1291 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1292 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 1293 phy_id = 0; 1294 } 1295 1296 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); 1297 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 1298 fep->phy_interface); 1299 if (IS_ERR(phy_dev)) { 1300 netdev_err(ndev, "could not attach to PHY\n"); 1301 return PTR_ERR(phy_dev); 1302 } 1303 1304 /* mask with MAC supported features */ 1305 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) { 1306 phy_dev->supported &= PHY_GBIT_FEATURES; 1307 #if !defined(CONFIG_M5272) 1308 phy_dev->supported |= SUPPORTED_Pause; 1309 #endif 1310 } 1311 else 1312 phy_dev->supported &= PHY_BASIC_FEATURES; 1313 1314 phy_dev->advertising = phy_dev->supported; 1315 1316 fep->phy_dev = phy_dev; 1317 fep->link = 0; 1318 fep->full_duplex = 0; 1319 1320 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 1321 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), 1322 fep->phy_dev->irq); 1323 1324 return 0; 1325 } 1326 1327 static int fec_enet_mii_init(struct platform_device *pdev) 1328 { 1329 static struct mii_bus *fec0_mii_bus; 1330 struct net_device *ndev = platform_get_drvdata(pdev); 1331 struct fec_enet_private *fep = netdev_priv(ndev); 1332 const struct platform_device_id *id_entry = 1333 platform_get_device_id(fep->pdev); 1334 int err = -ENXIO, i; 1335 1336 /* 1337 * The dual fec interfaces are not equivalent with enet-mac. 1338 * Here are the differences: 1339 * 1340 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1341 * - fec0 acts as the 1588 time master while fec1 is slave 1342 * - external phys can only be configured by fec0 1343 * 1344 * That is to say fec1 can not work independently. It only works 1345 * when fec0 is working. The reason behind this design is that the 1346 * second interface is added primarily for Switch mode. 1347 * 1348 * Because of the last point above, both phys are attached on fec0 1349 * mdio interface in board design, and need to be configured by 1350 * fec0 mii_bus. 1351 */ 1352 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { 1353 /* fec1 uses fec0 mii_bus */ 1354 if (mii_cnt && fec0_mii_bus) { 1355 fep->mii_bus = fec0_mii_bus; 1356 mii_cnt++; 1357 return 0; 1358 } 1359 return -ENOENT; 1360 } 1361 1362 fep->mii_timeout = 0; 1363 1364 /* 1365 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 1366 * 1367 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 1368 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 1369 * Reference Manual has an error on this, and gets fixed on i.MX6Q 1370 * document. 1371 */ 1372 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000); 1373 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1374 fep->phy_speed--; 1375 fep->phy_speed <<= 1; 1376 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1377 1378 fep->mii_bus = mdiobus_alloc(); 1379 if (fep->mii_bus == NULL) { 1380 err = -ENOMEM; 1381 goto err_out; 1382 } 1383 1384 fep->mii_bus->name = "fec_enet_mii_bus"; 1385 fep->mii_bus->read = fec_enet_mdio_read; 1386 fep->mii_bus->write = fec_enet_mdio_write; 1387 fep->mii_bus->reset = fec_enet_mdio_reset; 1388 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1389 pdev->name, fep->dev_id + 1); 1390 fep->mii_bus->priv = fep; 1391 fep->mii_bus->parent = &pdev->dev; 1392 1393 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 1394 if (!fep->mii_bus->irq) { 1395 err = -ENOMEM; 1396 goto err_out_free_mdiobus; 1397 } 1398 1399 for (i = 0; i < PHY_MAX_ADDR; i++) 1400 fep->mii_bus->irq[i] = PHY_POLL; 1401 1402 if (mdiobus_register(fep->mii_bus)) 1403 goto err_out_free_mdio_irq; 1404 1405 mii_cnt++; 1406 1407 /* save fec0 mii_bus */ 1408 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1409 fec0_mii_bus = fep->mii_bus; 1410 1411 return 0; 1412 1413 err_out_free_mdio_irq: 1414 kfree(fep->mii_bus->irq); 1415 err_out_free_mdiobus: 1416 mdiobus_free(fep->mii_bus); 1417 err_out: 1418 return err; 1419 } 1420 1421 static void fec_enet_mii_remove(struct fec_enet_private *fep) 1422 { 1423 if (--mii_cnt == 0) { 1424 mdiobus_unregister(fep->mii_bus); 1425 kfree(fep->mii_bus->irq); 1426 mdiobus_free(fep->mii_bus); 1427 } 1428 } 1429 1430 static int fec_enet_get_settings(struct net_device *ndev, 1431 struct ethtool_cmd *cmd) 1432 { 1433 struct fec_enet_private *fep = netdev_priv(ndev); 1434 struct phy_device *phydev = fep->phy_dev; 1435 1436 if (!phydev) 1437 return -ENODEV; 1438 1439 return phy_ethtool_gset(phydev, cmd); 1440 } 1441 1442 static int fec_enet_set_settings(struct net_device *ndev, 1443 struct ethtool_cmd *cmd) 1444 { 1445 struct fec_enet_private *fep = netdev_priv(ndev); 1446 struct phy_device *phydev = fep->phy_dev; 1447 1448 if (!phydev) 1449 return -ENODEV; 1450 1451 return phy_ethtool_sset(phydev, cmd); 1452 } 1453 1454 static void fec_enet_get_drvinfo(struct net_device *ndev, 1455 struct ethtool_drvinfo *info) 1456 { 1457 struct fec_enet_private *fep = netdev_priv(ndev); 1458 1459 strlcpy(info->driver, fep->pdev->dev.driver->name, 1460 sizeof(info->driver)); 1461 strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); 1462 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 1463 } 1464 1465 static int fec_enet_get_ts_info(struct net_device *ndev, 1466 struct ethtool_ts_info *info) 1467 { 1468 struct fec_enet_private *fep = netdev_priv(ndev); 1469 1470 if (fep->bufdesc_ex) { 1471 1472 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1473 SOF_TIMESTAMPING_RX_SOFTWARE | 1474 SOF_TIMESTAMPING_SOFTWARE | 1475 SOF_TIMESTAMPING_TX_HARDWARE | 1476 SOF_TIMESTAMPING_RX_HARDWARE | 1477 SOF_TIMESTAMPING_RAW_HARDWARE; 1478 if (fep->ptp_clock) 1479 info->phc_index = ptp_clock_index(fep->ptp_clock); 1480 else 1481 info->phc_index = -1; 1482 1483 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 1484 (1 << HWTSTAMP_TX_ON); 1485 1486 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 1487 (1 << HWTSTAMP_FILTER_ALL); 1488 return 0; 1489 } else { 1490 return ethtool_op_get_ts_info(ndev, info); 1491 } 1492 } 1493 1494 #if !defined(CONFIG_M5272) 1495 1496 static void fec_enet_get_pauseparam(struct net_device *ndev, 1497 struct ethtool_pauseparam *pause) 1498 { 1499 struct fec_enet_private *fep = netdev_priv(ndev); 1500 1501 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 1502 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 1503 pause->rx_pause = pause->tx_pause; 1504 } 1505 1506 static int fec_enet_set_pauseparam(struct net_device *ndev, 1507 struct ethtool_pauseparam *pause) 1508 { 1509 struct fec_enet_private *fep = netdev_priv(ndev); 1510 1511 if (pause->tx_pause != pause->rx_pause) { 1512 netdev_info(ndev, 1513 "hardware only support enable/disable both tx and rx"); 1514 return -EINVAL; 1515 } 1516 1517 fep->pause_flag = 0; 1518 1519 /* tx pause must be same as rx pause */ 1520 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 1521 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 1522 1523 if (pause->rx_pause || pause->autoneg) { 1524 fep->phy_dev->supported |= ADVERTISED_Pause; 1525 fep->phy_dev->advertising |= ADVERTISED_Pause; 1526 } else { 1527 fep->phy_dev->supported &= ~ADVERTISED_Pause; 1528 fep->phy_dev->advertising &= ~ADVERTISED_Pause; 1529 } 1530 1531 if (pause->autoneg) { 1532 if (netif_running(ndev)) 1533 fec_stop(ndev); 1534 phy_start_aneg(fep->phy_dev); 1535 } 1536 if (netif_running(ndev)) 1537 fec_restart(ndev, 0); 1538 1539 return 0; 1540 } 1541 1542 static const struct fec_stat { 1543 char name[ETH_GSTRING_LEN]; 1544 u16 offset; 1545 } fec_stats[] = { 1546 /* RMON TX */ 1547 { "tx_dropped", RMON_T_DROP }, 1548 { "tx_packets", RMON_T_PACKETS }, 1549 { "tx_broadcast", RMON_T_BC_PKT }, 1550 { "tx_multicast", RMON_T_MC_PKT }, 1551 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 1552 { "tx_undersize", RMON_T_UNDERSIZE }, 1553 { "tx_oversize", RMON_T_OVERSIZE }, 1554 { "tx_fragment", RMON_T_FRAG }, 1555 { "tx_jabber", RMON_T_JAB }, 1556 { "tx_collision", RMON_T_COL }, 1557 { "tx_64byte", RMON_T_P64 }, 1558 { "tx_65to127byte", RMON_T_P65TO127 }, 1559 { "tx_128to255byte", RMON_T_P128TO255 }, 1560 { "tx_256to511byte", RMON_T_P256TO511 }, 1561 { "tx_512to1023byte", RMON_T_P512TO1023 }, 1562 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 1563 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 1564 { "tx_octets", RMON_T_OCTETS }, 1565 1566 /* IEEE TX */ 1567 { "IEEE_tx_drop", IEEE_T_DROP }, 1568 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 1569 { "IEEE_tx_1col", IEEE_T_1COL }, 1570 { "IEEE_tx_mcol", IEEE_T_MCOL }, 1571 { "IEEE_tx_def", IEEE_T_DEF }, 1572 { "IEEE_tx_lcol", IEEE_T_LCOL }, 1573 { "IEEE_tx_excol", IEEE_T_EXCOL }, 1574 { "IEEE_tx_macerr", IEEE_T_MACERR }, 1575 { "IEEE_tx_cserr", IEEE_T_CSERR }, 1576 { "IEEE_tx_sqe", IEEE_T_SQE }, 1577 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 1578 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 1579 1580 /* RMON RX */ 1581 { "rx_packets", RMON_R_PACKETS }, 1582 { "rx_broadcast", RMON_R_BC_PKT }, 1583 { "rx_multicast", RMON_R_MC_PKT }, 1584 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 1585 { "rx_undersize", RMON_R_UNDERSIZE }, 1586 { "rx_oversize", RMON_R_OVERSIZE }, 1587 { "rx_fragment", RMON_R_FRAG }, 1588 { "rx_jabber", RMON_R_JAB }, 1589 { "rx_64byte", RMON_R_P64 }, 1590 { "rx_65to127byte", RMON_R_P65TO127 }, 1591 { "rx_128to255byte", RMON_R_P128TO255 }, 1592 { "rx_256to511byte", RMON_R_P256TO511 }, 1593 { "rx_512to1023byte", RMON_R_P512TO1023 }, 1594 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 1595 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 1596 { "rx_octets", RMON_R_OCTETS }, 1597 1598 /* IEEE RX */ 1599 { "IEEE_rx_drop", IEEE_R_DROP }, 1600 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 1601 { "IEEE_rx_crc", IEEE_R_CRC }, 1602 { "IEEE_rx_align", IEEE_R_ALIGN }, 1603 { "IEEE_rx_macerr", IEEE_R_MACERR }, 1604 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 1605 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 1606 }; 1607 1608 static void fec_enet_get_ethtool_stats(struct net_device *dev, 1609 struct ethtool_stats *stats, u64 *data) 1610 { 1611 struct fec_enet_private *fep = netdev_priv(dev); 1612 int i; 1613 1614 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 1615 data[i] = readl(fep->hwp + fec_stats[i].offset); 1616 } 1617 1618 static void fec_enet_get_strings(struct net_device *netdev, 1619 u32 stringset, u8 *data) 1620 { 1621 int i; 1622 switch (stringset) { 1623 case ETH_SS_STATS: 1624 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 1625 memcpy(data + i * ETH_GSTRING_LEN, 1626 fec_stats[i].name, ETH_GSTRING_LEN); 1627 break; 1628 } 1629 } 1630 1631 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 1632 { 1633 switch (sset) { 1634 case ETH_SS_STATS: 1635 return ARRAY_SIZE(fec_stats); 1636 default: 1637 return -EOPNOTSUPP; 1638 } 1639 } 1640 #endif /* !defined(CONFIG_M5272) */ 1641 1642 static int fec_enet_nway_reset(struct net_device *dev) 1643 { 1644 struct fec_enet_private *fep = netdev_priv(dev); 1645 struct phy_device *phydev = fep->phy_dev; 1646 1647 if (!phydev) 1648 return -ENODEV; 1649 1650 return genphy_restart_aneg(phydev); 1651 } 1652 1653 static const struct ethtool_ops fec_enet_ethtool_ops = { 1654 #if !defined(CONFIG_M5272) 1655 .get_pauseparam = fec_enet_get_pauseparam, 1656 .set_pauseparam = fec_enet_set_pauseparam, 1657 #endif 1658 .get_settings = fec_enet_get_settings, 1659 .set_settings = fec_enet_set_settings, 1660 .get_drvinfo = fec_enet_get_drvinfo, 1661 .get_link = ethtool_op_get_link, 1662 .get_ts_info = fec_enet_get_ts_info, 1663 .nway_reset = fec_enet_nway_reset, 1664 #ifndef CONFIG_M5272 1665 .get_ethtool_stats = fec_enet_get_ethtool_stats, 1666 .get_strings = fec_enet_get_strings, 1667 .get_sset_count = fec_enet_get_sset_count, 1668 #endif 1669 }; 1670 1671 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 1672 { 1673 struct fec_enet_private *fep = netdev_priv(ndev); 1674 struct phy_device *phydev = fep->phy_dev; 1675 1676 if (!netif_running(ndev)) 1677 return -EINVAL; 1678 1679 if (!phydev) 1680 return -ENODEV; 1681 1682 if (fep->bufdesc_ex) { 1683 if (cmd == SIOCSHWTSTAMP) 1684 return fec_ptp_set(ndev, rq); 1685 if (cmd == SIOCGHWTSTAMP) 1686 return fec_ptp_get(ndev, rq); 1687 } 1688 1689 return phy_mii_ioctl(phydev, rq, cmd); 1690 } 1691 1692 static void fec_enet_free_buffers(struct net_device *ndev) 1693 { 1694 struct fec_enet_private *fep = netdev_priv(ndev); 1695 unsigned int i; 1696 struct sk_buff *skb; 1697 struct bufdesc *bdp; 1698 1699 bdp = fep->rx_bd_base; 1700 for (i = 0; i < fep->rx_ring_size; i++) { 1701 skb = fep->rx_skbuff[i]; 1702 1703 if (bdp->cbd_bufaddr) 1704 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 1705 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1706 if (skb) 1707 dev_kfree_skb(skb); 1708 bdp = fec_enet_get_nextdesc(bdp, fep); 1709 } 1710 1711 bdp = fep->tx_bd_base; 1712 for (i = 0; i < fep->tx_ring_size; i++) 1713 kfree(fep->tx_bounce[i]); 1714 } 1715 1716 static int fec_enet_alloc_buffers(struct net_device *ndev) 1717 { 1718 struct fec_enet_private *fep = netdev_priv(ndev); 1719 unsigned int i; 1720 struct sk_buff *skb; 1721 struct bufdesc *bdp; 1722 1723 bdp = fep->rx_bd_base; 1724 for (i = 0; i < fep->rx_ring_size; i++) { 1725 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1726 if (!skb) { 1727 fec_enet_free_buffers(ndev); 1728 return -ENOMEM; 1729 } 1730 fep->rx_skbuff[i] = skb; 1731 1732 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, 1733 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1734 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) { 1735 fec_enet_free_buffers(ndev); 1736 if (net_ratelimit()) 1737 netdev_err(ndev, "Rx DMA memory map failed\n"); 1738 return -ENOMEM; 1739 } 1740 bdp->cbd_sc = BD_ENET_RX_EMPTY; 1741 1742 if (fep->bufdesc_ex) { 1743 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1744 ebdp->cbd_esc = BD_ENET_RX_INT; 1745 } 1746 1747 bdp = fec_enet_get_nextdesc(bdp, fep); 1748 } 1749 1750 /* Set the last buffer to wrap. */ 1751 bdp = fec_enet_get_prevdesc(bdp, fep); 1752 bdp->cbd_sc |= BD_SC_WRAP; 1753 1754 bdp = fep->tx_bd_base; 1755 for (i = 0; i < fep->tx_ring_size; i++) { 1756 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 1757 1758 bdp->cbd_sc = 0; 1759 bdp->cbd_bufaddr = 0; 1760 1761 if (fep->bufdesc_ex) { 1762 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1763 ebdp->cbd_esc = BD_ENET_TX_INT; 1764 } 1765 1766 bdp = fec_enet_get_nextdesc(bdp, fep); 1767 } 1768 1769 /* Set the last buffer to wrap. */ 1770 bdp = fec_enet_get_prevdesc(bdp, fep); 1771 bdp->cbd_sc |= BD_SC_WRAP; 1772 1773 return 0; 1774 } 1775 1776 static int 1777 fec_enet_open(struct net_device *ndev) 1778 { 1779 struct fec_enet_private *fep = netdev_priv(ndev); 1780 int ret; 1781 1782 /* I should reset the ring buffers here, but I don't yet know 1783 * a simple way to do that. 1784 */ 1785 1786 ret = fec_enet_alloc_buffers(ndev); 1787 if (ret) 1788 return ret; 1789 1790 /* Probe and connect to PHY when open the interface */ 1791 ret = fec_enet_mii_probe(ndev); 1792 if (ret) { 1793 fec_enet_free_buffers(ndev); 1794 return ret; 1795 } 1796 1797 napi_enable(&fep->napi); 1798 phy_start(fep->phy_dev); 1799 netif_start_queue(ndev); 1800 fep->opened = 1; 1801 return 0; 1802 } 1803 1804 static int 1805 fec_enet_close(struct net_device *ndev) 1806 { 1807 struct fec_enet_private *fep = netdev_priv(ndev); 1808 1809 /* Don't know what to do yet. */ 1810 napi_disable(&fep->napi); 1811 fep->opened = 0; 1812 netif_stop_queue(ndev); 1813 fec_stop(ndev); 1814 1815 if (fep->phy_dev) { 1816 phy_stop(fep->phy_dev); 1817 phy_disconnect(fep->phy_dev); 1818 } 1819 1820 fec_enet_free_buffers(ndev); 1821 1822 return 0; 1823 } 1824 1825 /* Set or clear the multicast filter for this adaptor. 1826 * Skeleton taken from sunlance driver. 1827 * The CPM Ethernet implementation allows Multicast as well as individual 1828 * MAC address filtering. Some of the drivers check to make sure it is 1829 * a group multicast address, and discard those that are not. I guess I 1830 * will do the same for now, but just remove the test if you want 1831 * individual filtering as well (do the upper net layers want or support 1832 * this kind of feature?). 1833 */ 1834 1835 #define HASH_BITS 6 /* #bits in hash */ 1836 #define CRC32_POLY 0xEDB88320 1837 1838 static void set_multicast_list(struct net_device *ndev) 1839 { 1840 struct fec_enet_private *fep = netdev_priv(ndev); 1841 struct netdev_hw_addr *ha; 1842 unsigned int i, bit, data, crc, tmp; 1843 unsigned char hash; 1844 1845 if (ndev->flags & IFF_PROMISC) { 1846 tmp = readl(fep->hwp + FEC_R_CNTRL); 1847 tmp |= 0x8; 1848 writel(tmp, fep->hwp + FEC_R_CNTRL); 1849 return; 1850 } 1851 1852 tmp = readl(fep->hwp + FEC_R_CNTRL); 1853 tmp &= ~0x8; 1854 writel(tmp, fep->hwp + FEC_R_CNTRL); 1855 1856 if (ndev->flags & IFF_ALLMULTI) { 1857 /* Catch all multicast addresses, so set the 1858 * filter to all 1's 1859 */ 1860 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1861 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1862 1863 return; 1864 } 1865 1866 /* Clear filter and add the addresses in hash register 1867 */ 1868 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1869 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1870 1871 netdev_for_each_mc_addr(ha, ndev) { 1872 /* calculate crc32 value of mac address */ 1873 crc = 0xffffffff; 1874 1875 for (i = 0; i < ndev->addr_len; i++) { 1876 data = ha->addr[i]; 1877 for (bit = 0; bit < 8; bit++, data >>= 1) { 1878 crc = (crc >> 1) ^ 1879 (((crc ^ data) & 1) ? CRC32_POLY : 0); 1880 } 1881 } 1882 1883 /* only upper 6 bits (HASH_BITS) are used 1884 * which point to specific bit in he hash registers 1885 */ 1886 hash = (crc >> (32 - HASH_BITS)) & 0x3f; 1887 1888 if (hash > 31) { 1889 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1890 tmp |= 1 << (hash - 32); 1891 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1892 } else { 1893 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1894 tmp |= 1 << hash; 1895 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1896 } 1897 } 1898 } 1899 1900 /* Set a MAC change in hardware. */ 1901 static int 1902 fec_set_mac_address(struct net_device *ndev, void *p) 1903 { 1904 struct fec_enet_private *fep = netdev_priv(ndev); 1905 struct sockaddr *addr = p; 1906 1907 if (!is_valid_ether_addr(addr->sa_data)) 1908 return -EADDRNOTAVAIL; 1909 1910 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 1911 1912 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 1913 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 1914 fep->hwp + FEC_ADDR_LOW); 1915 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 1916 fep->hwp + FEC_ADDR_HIGH); 1917 return 0; 1918 } 1919 1920 #ifdef CONFIG_NET_POLL_CONTROLLER 1921 /** 1922 * fec_poll_controller - FEC Poll controller function 1923 * @dev: The FEC network adapter 1924 * 1925 * Polled functionality used by netconsole and others in non interrupt mode 1926 * 1927 */ 1928 static void fec_poll_controller(struct net_device *dev) 1929 { 1930 int i; 1931 struct fec_enet_private *fep = netdev_priv(dev); 1932 1933 for (i = 0; i < FEC_IRQ_NUM; i++) { 1934 if (fep->irq[i] > 0) { 1935 disable_irq(fep->irq[i]); 1936 fec_enet_interrupt(fep->irq[i], dev); 1937 enable_irq(fep->irq[i]); 1938 } 1939 } 1940 } 1941 #endif 1942 1943 static int fec_set_features(struct net_device *netdev, 1944 netdev_features_t features) 1945 { 1946 struct fec_enet_private *fep = netdev_priv(netdev); 1947 netdev_features_t changed = features ^ netdev->features; 1948 1949 netdev->features = features; 1950 1951 /* Receive checksum has been changed */ 1952 if (changed & NETIF_F_RXCSUM) { 1953 if (features & NETIF_F_RXCSUM) 1954 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 1955 else 1956 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 1957 1958 if (netif_running(netdev)) { 1959 fec_stop(netdev); 1960 fec_restart(netdev, fep->phy_dev->duplex); 1961 netif_wake_queue(netdev); 1962 } else { 1963 fec_restart(netdev, fep->phy_dev->duplex); 1964 } 1965 } 1966 1967 return 0; 1968 } 1969 1970 static const struct net_device_ops fec_netdev_ops = { 1971 .ndo_open = fec_enet_open, 1972 .ndo_stop = fec_enet_close, 1973 .ndo_start_xmit = fec_enet_start_xmit, 1974 .ndo_set_rx_mode = set_multicast_list, 1975 .ndo_change_mtu = eth_change_mtu, 1976 .ndo_validate_addr = eth_validate_addr, 1977 .ndo_tx_timeout = fec_timeout, 1978 .ndo_set_mac_address = fec_set_mac_address, 1979 .ndo_do_ioctl = fec_enet_ioctl, 1980 #ifdef CONFIG_NET_POLL_CONTROLLER 1981 .ndo_poll_controller = fec_poll_controller, 1982 #endif 1983 .ndo_set_features = fec_set_features, 1984 }; 1985 1986 /* 1987 * XXX: We need to clean up on failure exits here. 1988 * 1989 */ 1990 static int fec_enet_init(struct net_device *ndev) 1991 { 1992 struct fec_enet_private *fep = netdev_priv(ndev); 1993 const struct platform_device_id *id_entry = 1994 platform_get_device_id(fep->pdev); 1995 struct bufdesc *cbd_base; 1996 1997 /* Allocate memory for buffer descriptors. */ 1998 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, 1999 GFP_KERNEL); 2000 if (!cbd_base) 2001 return -ENOMEM; 2002 2003 memset(cbd_base, 0, PAGE_SIZE); 2004 2005 fep->netdev = ndev; 2006 2007 /* Get the Ethernet address */ 2008 fec_get_mac(ndev); 2009 2010 /* init the tx & rx ring size */ 2011 fep->tx_ring_size = TX_RING_SIZE; 2012 fep->rx_ring_size = RX_RING_SIZE; 2013 2014 /* Set receive and transmit descriptor base. */ 2015 fep->rx_bd_base = cbd_base; 2016 if (fep->bufdesc_ex) 2017 fep->tx_bd_base = (struct bufdesc *) 2018 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size); 2019 else 2020 fep->tx_bd_base = cbd_base + fep->rx_ring_size; 2021 2022 /* The FEC Ethernet specific entries in the device structure */ 2023 ndev->watchdog_timeo = TX_TIMEOUT; 2024 ndev->netdev_ops = &fec_netdev_ops; 2025 ndev->ethtool_ops = &fec_enet_ethtool_ops; 2026 2027 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 2028 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 2029 2030 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) { 2031 /* enable hw VLAN support */ 2032 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 2033 ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 2034 } 2035 2036 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) { 2037 /* enable hw accelerator */ 2038 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 2039 | NETIF_F_RXCSUM); 2040 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 2041 | NETIF_F_RXCSUM); 2042 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 2043 } 2044 2045 fec_restart(ndev, 0); 2046 2047 return 0; 2048 } 2049 2050 #ifdef CONFIG_OF 2051 static void fec_reset_phy(struct platform_device *pdev) 2052 { 2053 int err, phy_reset; 2054 int msec = 1; 2055 struct device_node *np = pdev->dev.of_node; 2056 2057 if (!np) 2058 return; 2059 2060 of_property_read_u32(np, "phy-reset-duration", &msec); 2061 /* A sane reset duration should not be longer than 1s */ 2062 if (msec > 1000) 2063 msec = 1; 2064 2065 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 2066 if (!gpio_is_valid(phy_reset)) 2067 return; 2068 2069 err = devm_gpio_request_one(&pdev->dev, phy_reset, 2070 GPIOF_OUT_INIT_LOW, "phy-reset"); 2071 if (err) { 2072 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 2073 return; 2074 } 2075 msleep(msec); 2076 gpio_set_value(phy_reset, 1); 2077 } 2078 #else /* CONFIG_OF */ 2079 static void fec_reset_phy(struct platform_device *pdev) 2080 { 2081 /* 2082 * In case of platform probe, the reset has been done 2083 * by machine code. 2084 */ 2085 } 2086 #endif /* CONFIG_OF */ 2087 2088 static int 2089 fec_probe(struct platform_device *pdev) 2090 { 2091 struct fec_enet_private *fep; 2092 struct fec_platform_data *pdata; 2093 struct net_device *ndev; 2094 int i, irq, ret = 0; 2095 struct resource *r; 2096 const struct of_device_id *of_id; 2097 static int dev_id; 2098 2099 of_id = of_match_device(fec_dt_ids, &pdev->dev); 2100 if (of_id) 2101 pdev->id_entry = of_id->data; 2102 2103 /* Init network device */ 2104 ndev = alloc_etherdev(sizeof(struct fec_enet_private)); 2105 if (!ndev) 2106 return -ENOMEM; 2107 2108 SET_NETDEV_DEV(ndev, &pdev->dev); 2109 2110 /* setup board info structure */ 2111 fep = netdev_priv(ndev); 2112 2113 #if !defined(CONFIG_M5272) 2114 /* default enable pause frame auto negotiation */ 2115 if (pdev->id_entry && 2116 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT)) 2117 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 2118 #endif 2119 2120 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2121 fep->hwp = devm_ioremap_resource(&pdev->dev, r); 2122 if (IS_ERR(fep->hwp)) { 2123 ret = PTR_ERR(fep->hwp); 2124 goto failed_ioremap; 2125 } 2126 2127 fep->pdev = pdev; 2128 fep->dev_id = dev_id++; 2129 2130 fep->bufdesc_ex = 0; 2131 2132 platform_set_drvdata(pdev, ndev); 2133 2134 ret = of_get_phy_mode(pdev->dev.of_node); 2135 if (ret < 0) { 2136 pdata = dev_get_platdata(&pdev->dev); 2137 if (pdata) 2138 fep->phy_interface = pdata->phy; 2139 else 2140 fep->phy_interface = PHY_INTERFACE_MODE_MII; 2141 } else { 2142 fep->phy_interface = ret; 2143 } 2144 2145 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2146 if (IS_ERR(fep->clk_ipg)) { 2147 ret = PTR_ERR(fep->clk_ipg); 2148 goto failed_clk; 2149 } 2150 2151 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 2152 if (IS_ERR(fep->clk_ahb)) { 2153 ret = PTR_ERR(fep->clk_ahb); 2154 goto failed_clk; 2155 } 2156 2157 /* enet_out is optional, depends on board */ 2158 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 2159 if (IS_ERR(fep->clk_enet_out)) 2160 fep->clk_enet_out = NULL; 2161 2162 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 2163 fep->bufdesc_ex = 2164 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX; 2165 if (IS_ERR(fep->clk_ptp)) { 2166 fep->clk_ptp = NULL; 2167 fep->bufdesc_ex = 0; 2168 } 2169 2170 ret = clk_prepare_enable(fep->clk_ahb); 2171 if (ret) 2172 goto failed_clk; 2173 2174 ret = clk_prepare_enable(fep->clk_ipg); 2175 if (ret) 2176 goto failed_clk_ipg; 2177 2178 if (fep->clk_enet_out) { 2179 ret = clk_prepare_enable(fep->clk_enet_out); 2180 if (ret) 2181 goto failed_clk_enet_out; 2182 } 2183 2184 if (fep->clk_ptp) { 2185 ret = clk_prepare_enable(fep->clk_ptp); 2186 if (ret) 2187 goto failed_clk_ptp; 2188 } 2189 2190 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); 2191 if (!IS_ERR(fep->reg_phy)) { 2192 ret = regulator_enable(fep->reg_phy); 2193 if (ret) { 2194 dev_err(&pdev->dev, 2195 "Failed to enable phy regulator: %d\n", ret); 2196 goto failed_regulator; 2197 } 2198 } else { 2199 fep->reg_phy = NULL; 2200 } 2201 2202 fec_reset_phy(pdev); 2203 2204 if (fep->bufdesc_ex) 2205 fec_ptp_init(pdev); 2206 2207 ret = fec_enet_init(ndev); 2208 if (ret) 2209 goto failed_init; 2210 2211 for (i = 0; i < FEC_IRQ_NUM; i++) { 2212 irq = platform_get_irq(pdev, i); 2213 if (irq < 0) { 2214 if (i) 2215 break; 2216 ret = irq; 2217 goto failed_irq; 2218 } 2219 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 2220 0, pdev->name, ndev); 2221 if (ret) 2222 goto failed_irq; 2223 } 2224 2225 ret = fec_enet_mii_init(pdev); 2226 if (ret) 2227 goto failed_mii_init; 2228 2229 /* Carrier starts down, phylib will bring it up */ 2230 netif_carrier_off(ndev); 2231 2232 ret = register_netdev(ndev); 2233 if (ret) 2234 goto failed_register; 2235 2236 if (fep->bufdesc_ex && fep->ptp_clock) 2237 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 2238 2239 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work); 2240 return 0; 2241 2242 failed_register: 2243 fec_enet_mii_remove(fep); 2244 failed_mii_init: 2245 failed_irq: 2246 failed_init: 2247 if (fep->reg_phy) 2248 regulator_disable(fep->reg_phy); 2249 failed_regulator: 2250 if (fep->clk_ptp) 2251 clk_disable_unprepare(fep->clk_ptp); 2252 failed_clk_ptp: 2253 if (fep->clk_enet_out) 2254 clk_disable_unprepare(fep->clk_enet_out); 2255 failed_clk_enet_out: 2256 clk_disable_unprepare(fep->clk_ipg); 2257 failed_clk_ipg: 2258 clk_disable_unprepare(fep->clk_ahb); 2259 failed_clk: 2260 failed_ioremap: 2261 free_netdev(ndev); 2262 2263 return ret; 2264 } 2265 2266 static int 2267 fec_drv_remove(struct platform_device *pdev) 2268 { 2269 struct net_device *ndev = platform_get_drvdata(pdev); 2270 struct fec_enet_private *fep = netdev_priv(ndev); 2271 2272 cancel_delayed_work_sync(&(fep->delay_work.delay_work)); 2273 unregister_netdev(ndev); 2274 fec_enet_mii_remove(fep); 2275 del_timer_sync(&fep->time_keep); 2276 if (fep->reg_phy) 2277 regulator_disable(fep->reg_phy); 2278 if (fep->clk_ptp) 2279 clk_disable_unprepare(fep->clk_ptp); 2280 if (fep->ptp_clock) 2281 ptp_clock_unregister(fep->ptp_clock); 2282 if (fep->clk_enet_out) 2283 clk_disable_unprepare(fep->clk_enet_out); 2284 clk_disable_unprepare(fep->clk_ipg); 2285 clk_disable_unprepare(fep->clk_ahb); 2286 free_netdev(ndev); 2287 2288 return 0; 2289 } 2290 2291 #ifdef CONFIG_PM_SLEEP 2292 static int 2293 fec_suspend(struct device *dev) 2294 { 2295 struct net_device *ndev = dev_get_drvdata(dev); 2296 struct fec_enet_private *fep = netdev_priv(ndev); 2297 2298 if (netif_running(ndev)) { 2299 fec_stop(ndev); 2300 netif_device_detach(ndev); 2301 } 2302 if (fep->clk_ptp) 2303 clk_disable_unprepare(fep->clk_ptp); 2304 if (fep->clk_enet_out) 2305 clk_disable_unprepare(fep->clk_enet_out); 2306 clk_disable_unprepare(fep->clk_ipg); 2307 clk_disable_unprepare(fep->clk_ahb); 2308 2309 if (fep->reg_phy) 2310 regulator_disable(fep->reg_phy); 2311 2312 return 0; 2313 } 2314 2315 static int 2316 fec_resume(struct device *dev) 2317 { 2318 struct net_device *ndev = dev_get_drvdata(dev); 2319 struct fec_enet_private *fep = netdev_priv(ndev); 2320 int ret; 2321 2322 if (fep->reg_phy) { 2323 ret = regulator_enable(fep->reg_phy); 2324 if (ret) 2325 return ret; 2326 } 2327 2328 ret = clk_prepare_enable(fep->clk_ahb); 2329 if (ret) 2330 goto failed_clk_ahb; 2331 2332 ret = clk_prepare_enable(fep->clk_ipg); 2333 if (ret) 2334 goto failed_clk_ipg; 2335 2336 if (fep->clk_enet_out) { 2337 ret = clk_prepare_enable(fep->clk_enet_out); 2338 if (ret) 2339 goto failed_clk_enet_out; 2340 } 2341 2342 if (fep->clk_ptp) { 2343 ret = clk_prepare_enable(fep->clk_ptp); 2344 if (ret) 2345 goto failed_clk_ptp; 2346 } 2347 2348 if (netif_running(ndev)) { 2349 fec_restart(ndev, fep->full_duplex); 2350 netif_device_attach(ndev); 2351 } 2352 2353 return 0; 2354 2355 failed_clk_ptp: 2356 if (fep->clk_enet_out) 2357 clk_disable_unprepare(fep->clk_enet_out); 2358 failed_clk_enet_out: 2359 clk_disable_unprepare(fep->clk_ipg); 2360 failed_clk_ipg: 2361 clk_disable_unprepare(fep->clk_ahb); 2362 failed_clk_ahb: 2363 if (fep->reg_phy) 2364 regulator_disable(fep->reg_phy); 2365 return ret; 2366 } 2367 #endif /* CONFIG_PM_SLEEP */ 2368 2369 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume); 2370 2371 static struct platform_driver fec_driver = { 2372 .driver = { 2373 .name = DRIVER_NAME, 2374 .owner = THIS_MODULE, 2375 .pm = &fec_pm_ops, 2376 .of_match_table = fec_dt_ids, 2377 }, 2378 .id_table = fec_devtype, 2379 .probe = fec_probe, 2380 .remove = fec_drv_remove, 2381 }; 2382 2383 module_platform_driver(fec_driver); 2384 2385 MODULE_ALIAS("platform:"DRIVER_NAME); 2386 MODULE_LICENSE("GPL"); 2387