1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
4  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5  *
6  * Right now, I am very wasteful with the buffers.  I allocate memory
7  * pages and then divide them into 2K frame buffers.  This way I know I
8  * have buffers large enough to hold one frame within one buffer descriptor.
9  * Once I get this working, I will use 64 or 128 byte CPM buffers, which
10  * will be much more memory efficient and will easily handle lots of
11  * small packets.
12  *
13  * Much better multiple PHY support by Magnus Damm.
14  * Copyright (c) 2000 Ericsson Radio Systems AB.
15  *
16  * Support for FEC controller of ColdFire processors.
17  * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18  *
19  * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
20  * Copyright (c) 2004-2006 Macq Electronique SA.
21  *
22  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
23  */
24 
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/string.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/ptrace.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/slab.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/in.h>
39 #include <linux/ip.h>
40 #include <net/ip.h>
41 #include <net/tso.h>
42 #include <linux/tcp.h>
43 #include <linux/udp.h>
44 #include <linux/icmp.h>
45 #include <linux/spinlock.h>
46 #include <linux/workqueue.h>
47 #include <linux/bitops.h>
48 #include <linux/io.h>
49 #include <linux/irq.h>
50 #include <linux/clk.h>
51 #include <linux/crc32.h>
52 #include <linux/platform_device.h>
53 #include <linux/mdio.h>
54 #include <linux/phy.h>
55 #include <linux/fec.h>
56 #include <linux/of.h>
57 #include <linux/of_device.h>
58 #include <linux/of_gpio.h>
59 #include <linux/of_mdio.h>
60 #include <linux/of_net.h>
61 #include <linux/regulator/consumer.h>
62 #include <linux/if_vlan.h>
63 #include <linux/pinctrl/consumer.h>
64 #include <linux/prefetch.h>
65 #include <soc/imx/cpuidle.h>
66 
67 #include <asm/cacheflush.h>
68 
69 #include "fec.h"
70 
71 static void set_multicast_list(struct net_device *ndev);
72 static void fec_enet_itr_coal_init(struct net_device *ndev);
73 
74 #define DRIVER_NAME	"fec"
75 
76 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
77 
78 /* Pause frame feild and FIFO threshold */
79 #define FEC_ENET_FCE	(1 << 5)
80 #define FEC_ENET_RSEM_V	0x84
81 #define FEC_ENET_RSFL_V	16
82 #define FEC_ENET_RAEM_V	0x8
83 #define FEC_ENET_RAFL_V	0x8
84 #define FEC_ENET_OPD_V	0xFFF0
85 #define FEC_MDIO_PM_TIMEOUT  100 /* ms */
86 
87 static struct platform_device_id fec_devtype[] = {
88 	{
89 		/* keep it for coldfire */
90 		.name = DRIVER_NAME,
91 		.driver_data = 0,
92 	}, {
93 		.name = "imx25-fec",
94 		.driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR |
95 			       FEC_QUIRK_HAS_FRREG,
96 	}, {
97 		.name = "imx27-fec",
98 		.driver_data = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG,
99 	}, {
100 		.name = "imx28-fec",
101 		.driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
102 				FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
103 				FEC_QUIRK_HAS_FRREG,
104 	}, {
105 		.name = "imx6q-fec",
106 		.driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
107 				FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
108 				FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
109 				FEC_QUIRK_HAS_RACC,
110 	}, {
111 		.name = "mvf600-fec",
112 		.driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
113 	}, {
114 		.name = "imx6sx-fec",
115 		.driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
116 				FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
117 				FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
118 				FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
119 				FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE,
120 	}, {
121 		.name = "imx6ul-fec",
122 		.driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
123 				FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
124 				FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
125 				FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
126 				FEC_QUIRK_HAS_COALESCE,
127 	}, {
128 		/* sentinel */
129 	}
130 };
131 MODULE_DEVICE_TABLE(platform, fec_devtype);
132 
133 enum imx_fec_type {
134 	IMX25_FEC = 1,	/* runs on i.mx25/50/53 */
135 	IMX27_FEC,	/* runs on i.mx27/35/51 */
136 	IMX28_FEC,
137 	IMX6Q_FEC,
138 	MVF600_FEC,
139 	IMX6SX_FEC,
140 	IMX6UL_FEC,
141 };
142 
143 static const struct of_device_id fec_dt_ids[] = {
144 	{ .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
145 	{ .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
146 	{ .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
147 	{ .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
148 	{ .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
149 	{ .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
150 	{ .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
151 	{ /* sentinel */ }
152 };
153 MODULE_DEVICE_TABLE(of, fec_dt_ids);
154 
155 static unsigned char macaddr[ETH_ALEN];
156 module_param_array(macaddr, byte, NULL, 0);
157 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
158 
159 #if defined(CONFIG_M5272)
160 /*
161  * Some hardware gets it MAC address out of local flash memory.
162  * if this is non-zero then assume it is the address to get MAC from.
163  */
164 #if defined(CONFIG_NETtel)
165 #define	FEC_FLASHMAC	0xf0006006
166 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
167 #define	FEC_FLASHMAC	0xf0006000
168 #elif defined(CONFIG_CANCam)
169 #define	FEC_FLASHMAC	0xf0020000
170 #elif defined (CONFIG_M5272C3)
171 #define	FEC_FLASHMAC	(0xffe04000 + 4)
172 #elif defined(CONFIG_MOD5272)
173 #define FEC_FLASHMAC	0xffc0406b
174 #else
175 #define	FEC_FLASHMAC	0
176 #endif
177 #endif /* CONFIG_M5272 */
178 
179 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
180  *
181  * 2048 byte skbufs are allocated. However, alignment requirements
182  * varies between FEC variants. Worst case is 64, so round down by 64.
183  */
184 #define PKT_MAXBUF_SIZE		(round_down(2048 - 64, 64))
185 #define PKT_MINBUF_SIZE		64
186 
187 /* FEC receive acceleration */
188 #define FEC_RACC_IPDIS		(1 << 1)
189 #define FEC_RACC_PRODIS		(1 << 2)
190 #define FEC_RACC_SHIFT16	BIT(7)
191 #define FEC_RACC_OPTIONS	(FEC_RACC_IPDIS | FEC_RACC_PRODIS)
192 
193 /* MIB Control Register */
194 #define FEC_MIB_CTRLSTAT_DISABLE	BIT(31)
195 
196 /*
197  * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
198  * size bits. Other FEC hardware does not, so we need to take that into
199  * account when setting it.
200  */
201 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
202     defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
203     defined(CONFIG_ARM64)
204 #define	OPT_FRAME_SIZE	(PKT_MAXBUF_SIZE << 16)
205 #else
206 #define	OPT_FRAME_SIZE	0
207 #endif
208 
209 /* FEC MII MMFR bits definition */
210 #define FEC_MMFR_ST		(1 << 30)
211 #define FEC_MMFR_OP_READ	(2 << 28)
212 #define FEC_MMFR_OP_WRITE	(1 << 28)
213 #define FEC_MMFR_PA(v)		((v & 0x1f) << 23)
214 #define FEC_MMFR_RA(v)		((v & 0x1f) << 18)
215 #define FEC_MMFR_TA		(2 << 16)
216 #define FEC_MMFR_DATA(v)	(v & 0xffff)
217 /* FEC ECR bits definition */
218 #define FEC_ECR_MAGICEN		(1 << 2)
219 #define FEC_ECR_SLEEP		(1 << 3)
220 
221 #define FEC_MII_TIMEOUT		30000 /* us */
222 
223 /* Transmitter timeout */
224 #define TX_TIMEOUT (2 * HZ)
225 
226 #define FEC_PAUSE_FLAG_AUTONEG	0x1
227 #define FEC_PAUSE_FLAG_ENABLE	0x2
228 #define FEC_WOL_HAS_MAGIC_PACKET	(0x1 << 0)
229 #define FEC_WOL_FLAG_ENABLE		(0x1 << 1)
230 #define FEC_WOL_FLAG_SLEEP_ON		(0x1 << 2)
231 
232 #define COPYBREAK_DEFAULT	256
233 
234 /* Max number of allowed TCP segments for software TSO */
235 #define FEC_MAX_TSO_SEGS	100
236 #define FEC_MAX_SKB_DESCS	(FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
237 
238 #define IS_TSO_HEADER(txq, addr) \
239 	((addr >= txq->tso_hdrs_dma) && \
240 	(addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
241 
242 static int mii_cnt;
243 
244 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
245 					     struct bufdesc_prop *bd)
246 {
247 	return (bdp >= bd->last) ? bd->base
248 			: (struct bufdesc *)(((void *)bdp) + bd->dsize);
249 }
250 
251 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
252 					     struct bufdesc_prop *bd)
253 {
254 	return (bdp <= bd->base) ? bd->last
255 			: (struct bufdesc *)(((void *)bdp) - bd->dsize);
256 }
257 
258 static int fec_enet_get_bd_index(struct bufdesc *bdp,
259 				 struct bufdesc_prop *bd)
260 {
261 	return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
262 }
263 
264 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
265 {
266 	int entries;
267 
268 	entries = (((const char *)txq->dirty_tx -
269 			(const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
270 
271 	return entries >= 0 ? entries : entries + txq->bd.ring_size;
272 }
273 
274 static void swap_buffer(void *bufaddr, int len)
275 {
276 	int i;
277 	unsigned int *buf = bufaddr;
278 
279 	for (i = 0; i < len; i += 4, buf++)
280 		swab32s(buf);
281 }
282 
283 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
284 {
285 	int i;
286 	unsigned int *src = src_buf;
287 	unsigned int *dst = dst_buf;
288 
289 	for (i = 0; i < len; i += 4, src++, dst++)
290 		*dst = swab32p(src);
291 }
292 
293 static void fec_dump(struct net_device *ndev)
294 {
295 	struct fec_enet_private *fep = netdev_priv(ndev);
296 	struct bufdesc *bdp;
297 	struct fec_enet_priv_tx_q *txq;
298 	int index = 0;
299 
300 	netdev_info(ndev, "TX ring dump\n");
301 	pr_info("Nr     SC     addr       len  SKB\n");
302 
303 	txq = fep->tx_queue[0];
304 	bdp = txq->bd.base;
305 
306 	do {
307 		pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
308 			index,
309 			bdp == txq->bd.cur ? 'S' : ' ',
310 			bdp == txq->dirty_tx ? 'H' : ' ',
311 			fec16_to_cpu(bdp->cbd_sc),
312 			fec32_to_cpu(bdp->cbd_bufaddr),
313 			fec16_to_cpu(bdp->cbd_datlen),
314 			txq->tx_skbuff[index]);
315 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
316 		index++;
317 	} while (bdp != txq->bd.base);
318 }
319 
320 static inline bool is_ipv4_pkt(struct sk_buff *skb)
321 {
322 	return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
323 }
324 
325 static int
326 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
327 {
328 	/* Only run for packets requiring a checksum. */
329 	if (skb->ip_summed != CHECKSUM_PARTIAL)
330 		return 0;
331 
332 	if (unlikely(skb_cow_head(skb, 0)))
333 		return -1;
334 
335 	if (is_ipv4_pkt(skb))
336 		ip_hdr(skb)->check = 0;
337 	*(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
338 
339 	return 0;
340 }
341 
342 static struct bufdesc *
343 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
344 			     struct sk_buff *skb,
345 			     struct net_device *ndev)
346 {
347 	struct fec_enet_private *fep = netdev_priv(ndev);
348 	struct bufdesc *bdp = txq->bd.cur;
349 	struct bufdesc_ex *ebdp;
350 	int nr_frags = skb_shinfo(skb)->nr_frags;
351 	int frag, frag_len;
352 	unsigned short status;
353 	unsigned int estatus = 0;
354 	skb_frag_t *this_frag;
355 	unsigned int index;
356 	void *bufaddr;
357 	dma_addr_t addr;
358 	int i;
359 
360 	for (frag = 0; frag < nr_frags; frag++) {
361 		this_frag = &skb_shinfo(skb)->frags[frag];
362 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
363 		ebdp = (struct bufdesc_ex *)bdp;
364 
365 		status = fec16_to_cpu(bdp->cbd_sc);
366 		status &= ~BD_ENET_TX_STATS;
367 		status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
368 		frag_len = skb_shinfo(skb)->frags[frag].size;
369 
370 		/* Handle the last BD specially */
371 		if (frag == nr_frags - 1) {
372 			status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
373 			if (fep->bufdesc_ex) {
374 				estatus |= BD_ENET_TX_INT;
375 				if (unlikely(skb_shinfo(skb)->tx_flags &
376 					SKBTX_HW_TSTAMP && fep->hwts_tx_en))
377 					estatus |= BD_ENET_TX_TS;
378 			}
379 		}
380 
381 		if (fep->bufdesc_ex) {
382 			if (fep->quirks & FEC_QUIRK_HAS_AVB)
383 				estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
384 			if (skb->ip_summed == CHECKSUM_PARTIAL)
385 				estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
386 			ebdp->cbd_bdu = 0;
387 			ebdp->cbd_esc = cpu_to_fec32(estatus);
388 		}
389 
390 		bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
391 
392 		index = fec_enet_get_bd_index(bdp, &txq->bd);
393 		if (((unsigned long) bufaddr) & fep->tx_align ||
394 			fep->quirks & FEC_QUIRK_SWAP_FRAME) {
395 			memcpy(txq->tx_bounce[index], bufaddr, frag_len);
396 			bufaddr = txq->tx_bounce[index];
397 
398 			if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
399 				swap_buffer(bufaddr, frag_len);
400 		}
401 
402 		addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
403 				      DMA_TO_DEVICE);
404 		if (dma_mapping_error(&fep->pdev->dev, addr)) {
405 			if (net_ratelimit())
406 				netdev_err(ndev, "Tx DMA memory map failed\n");
407 			goto dma_mapping_error;
408 		}
409 
410 		bdp->cbd_bufaddr = cpu_to_fec32(addr);
411 		bdp->cbd_datlen = cpu_to_fec16(frag_len);
412 		/* Make sure the updates to rest of the descriptor are
413 		 * performed before transferring ownership.
414 		 */
415 		wmb();
416 		bdp->cbd_sc = cpu_to_fec16(status);
417 	}
418 
419 	return bdp;
420 dma_mapping_error:
421 	bdp = txq->bd.cur;
422 	for (i = 0; i < frag; i++) {
423 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
424 		dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
425 				 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
426 	}
427 	return ERR_PTR(-ENOMEM);
428 }
429 
430 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
431 				   struct sk_buff *skb, struct net_device *ndev)
432 {
433 	struct fec_enet_private *fep = netdev_priv(ndev);
434 	int nr_frags = skb_shinfo(skb)->nr_frags;
435 	struct bufdesc *bdp, *last_bdp;
436 	void *bufaddr;
437 	dma_addr_t addr;
438 	unsigned short status;
439 	unsigned short buflen;
440 	unsigned int estatus = 0;
441 	unsigned int index;
442 	int entries_free;
443 
444 	entries_free = fec_enet_get_free_txdesc_num(txq);
445 	if (entries_free < MAX_SKB_FRAGS + 1) {
446 		dev_kfree_skb_any(skb);
447 		if (net_ratelimit())
448 			netdev_err(ndev, "NOT enough BD for SG!\n");
449 		return NETDEV_TX_OK;
450 	}
451 
452 	/* Protocol checksum off-load for TCP and UDP. */
453 	if (fec_enet_clear_csum(skb, ndev)) {
454 		dev_kfree_skb_any(skb);
455 		return NETDEV_TX_OK;
456 	}
457 
458 	/* Fill in a Tx ring entry */
459 	bdp = txq->bd.cur;
460 	last_bdp = bdp;
461 	status = fec16_to_cpu(bdp->cbd_sc);
462 	status &= ~BD_ENET_TX_STATS;
463 
464 	/* Set buffer length and buffer pointer */
465 	bufaddr = skb->data;
466 	buflen = skb_headlen(skb);
467 
468 	index = fec_enet_get_bd_index(bdp, &txq->bd);
469 	if (((unsigned long) bufaddr) & fep->tx_align ||
470 		fep->quirks & FEC_QUIRK_SWAP_FRAME) {
471 		memcpy(txq->tx_bounce[index], skb->data, buflen);
472 		bufaddr = txq->tx_bounce[index];
473 
474 		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
475 			swap_buffer(bufaddr, buflen);
476 	}
477 
478 	/* Push the data cache so the CPM does not get stale memory data. */
479 	addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
480 	if (dma_mapping_error(&fep->pdev->dev, addr)) {
481 		dev_kfree_skb_any(skb);
482 		if (net_ratelimit())
483 			netdev_err(ndev, "Tx DMA memory map failed\n");
484 		return NETDEV_TX_OK;
485 	}
486 
487 	if (nr_frags) {
488 		last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
489 		if (IS_ERR(last_bdp)) {
490 			dma_unmap_single(&fep->pdev->dev, addr,
491 					 buflen, DMA_TO_DEVICE);
492 			dev_kfree_skb_any(skb);
493 			return NETDEV_TX_OK;
494 		}
495 	} else {
496 		status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
497 		if (fep->bufdesc_ex) {
498 			estatus = BD_ENET_TX_INT;
499 			if (unlikely(skb_shinfo(skb)->tx_flags &
500 				SKBTX_HW_TSTAMP && fep->hwts_tx_en))
501 				estatus |= BD_ENET_TX_TS;
502 		}
503 	}
504 	bdp->cbd_bufaddr = cpu_to_fec32(addr);
505 	bdp->cbd_datlen = cpu_to_fec16(buflen);
506 
507 	if (fep->bufdesc_ex) {
508 
509 		struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
510 
511 		if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
512 			fep->hwts_tx_en))
513 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
514 
515 		if (fep->quirks & FEC_QUIRK_HAS_AVB)
516 			estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
517 
518 		if (skb->ip_summed == CHECKSUM_PARTIAL)
519 			estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
520 
521 		ebdp->cbd_bdu = 0;
522 		ebdp->cbd_esc = cpu_to_fec32(estatus);
523 	}
524 
525 	index = fec_enet_get_bd_index(last_bdp, &txq->bd);
526 	/* Save skb pointer */
527 	txq->tx_skbuff[index] = skb;
528 
529 	/* Make sure the updates to rest of the descriptor are performed before
530 	 * transferring ownership.
531 	 */
532 	wmb();
533 
534 	/* Send it on its way.  Tell FEC it's ready, interrupt when done,
535 	 * it's the last BD of the frame, and to put the CRC on the end.
536 	 */
537 	status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
538 	bdp->cbd_sc = cpu_to_fec16(status);
539 
540 	/* If this was the last BD in the ring, start at the beginning again. */
541 	bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
542 
543 	skb_tx_timestamp(skb);
544 
545 	/* Make sure the update to bdp and tx_skbuff are performed before
546 	 * txq->bd.cur.
547 	 */
548 	wmb();
549 	txq->bd.cur = bdp;
550 
551 	/* Trigger transmission start */
552 	writel(0, txq->bd.reg_desc_active);
553 
554 	return 0;
555 }
556 
557 static int
558 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
559 			  struct net_device *ndev,
560 			  struct bufdesc *bdp, int index, char *data,
561 			  int size, bool last_tcp, bool is_last)
562 {
563 	struct fec_enet_private *fep = netdev_priv(ndev);
564 	struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
565 	unsigned short status;
566 	unsigned int estatus = 0;
567 	dma_addr_t addr;
568 
569 	status = fec16_to_cpu(bdp->cbd_sc);
570 	status &= ~BD_ENET_TX_STATS;
571 
572 	status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
573 
574 	if (((unsigned long) data) & fep->tx_align ||
575 		fep->quirks & FEC_QUIRK_SWAP_FRAME) {
576 		memcpy(txq->tx_bounce[index], data, size);
577 		data = txq->tx_bounce[index];
578 
579 		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
580 			swap_buffer(data, size);
581 	}
582 
583 	addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
584 	if (dma_mapping_error(&fep->pdev->dev, addr)) {
585 		dev_kfree_skb_any(skb);
586 		if (net_ratelimit())
587 			netdev_err(ndev, "Tx DMA memory map failed\n");
588 		return NETDEV_TX_BUSY;
589 	}
590 
591 	bdp->cbd_datlen = cpu_to_fec16(size);
592 	bdp->cbd_bufaddr = cpu_to_fec32(addr);
593 
594 	if (fep->bufdesc_ex) {
595 		if (fep->quirks & FEC_QUIRK_HAS_AVB)
596 			estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
597 		if (skb->ip_summed == CHECKSUM_PARTIAL)
598 			estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
599 		ebdp->cbd_bdu = 0;
600 		ebdp->cbd_esc = cpu_to_fec32(estatus);
601 	}
602 
603 	/* Handle the last BD specially */
604 	if (last_tcp)
605 		status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
606 	if (is_last) {
607 		status |= BD_ENET_TX_INTR;
608 		if (fep->bufdesc_ex)
609 			ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
610 	}
611 
612 	bdp->cbd_sc = cpu_to_fec16(status);
613 
614 	return 0;
615 }
616 
617 static int
618 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
619 			 struct sk_buff *skb, struct net_device *ndev,
620 			 struct bufdesc *bdp, int index)
621 {
622 	struct fec_enet_private *fep = netdev_priv(ndev);
623 	int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
624 	struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
625 	void *bufaddr;
626 	unsigned long dmabuf;
627 	unsigned short status;
628 	unsigned int estatus = 0;
629 
630 	status = fec16_to_cpu(bdp->cbd_sc);
631 	status &= ~BD_ENET_TX_STATS;
632 	status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
633 
634 	bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
635 	dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
636 	if (((unsigned long)bufaddr) & fep->tx_align ||
637 		fep->quirks & FEC_QUIRK_SWAP_FRAME) {
638 		memcpy(txq->tx_bounce[index], skb->data, hdr_len);
639 		bufaddr = txq->tx_bounce[index];
640 
641 		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
642 			swap_buffer(bufaddr, hdr_len);
643 
644 		dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
645 					hdr_len, DMA_TO_DEVICE);
646 		if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
647 			dev_kfree_skb_any(skb);
648 			if (net_ratelimit())
649 				netdev_err(ndev, "Tx DMA memory map failed\n");
650 			return NETDEV_TX_BUSY;
651 		}
652 	}
653 
654 	bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
655 	bdp->cbd_datlen = cpu_to_fec16(hdr_len);
656 
657 	if (fep->bufdesc_ex) {
658 		if (fep->quirks & FEC_QUIRK_HAS_AVB)
659 			estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
660 		if (skb->ip_summed == CHECKSUM_PARTIAL)
661 			estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
662 		ebdp->cbd_bdu = 0;
663 		ebdp->cbd_esc = cpu_to_fec32(estatus);
664 	}
665 
666 	bdp->cbd_sc = cpu_to_fec16(status);
667 
668 	return 0;
669 }
670 
671 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
672 				   struct sk_buff *skb,
673 				   struct net_device *ndev)
674 {
675 	struct fec_enet_private *fep = netdev_priv(ndev);
676 	int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
677 	int total_len, data_left;
678 	struct bufdesc *bdp = txq->bd.cur;
679 	struct tso_t tso;
680 	unsigned int index = 0;
681 	int ret;
682 
683 	if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
684 		dev_kfree_skb_any(skb);
685 		if (net_ratelimit())
686 			netdev_err(ndev, "NOT enough BD for TSO!\n");
687 		return NETDEV_TX_OK;
688 	}
689 
690 	/* Protocol checksum off-load for TCP and UDP. */
691 	if (fec_enet_clear_csum(skb, ndev)) {
692 		dev_kfree_skb_any(skb);
693 		return NETDEV_TX_OK;
694 	}
695 
696 	/* Initialize the TSO handler, and prepare the first payload */
697 	tso_start(skb, &tso);
698 
699 	total_len = skb->len - hdr_len;
700 	while (total_len > 0) {
701 		char *hdr;
702 
703 		index = fec_enet_get_bd_index(bdp, &txq->bd);
704 		data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
705 		total_len -= data_left;
706 
707 		/* prepare packet headers: MAC + IP + TCP */
708 		hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
709 		tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
710 		ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
711 		if (ret)
712 			goto err_release;
713 
714 		while (data_left > 0) {
715 			int size;
716 
717 			size = min_t(int, tso.size, data_left);
718 			bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
719 			index = fec_enet_get_bd_index(bdp, &txq->bd);
720 			ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
721 							bdp, index,
722 							tso.data, size,
723 							size == data_left,
724 							total_len == 0);
725 			if (ret)
726 				goto err_release;
727 
728 			data_left -= size;
729 			tso_build_data(skb, &tso, size);
730 		}
731 
732 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
733 	}
734 
735 	/* Save skb pointer */
736 	txq->tx_skbuff[index] = skb;
737 
738 	skb_tx_timestamp(skb);
739 	txq->bd.cur = bdp;
740 
741 	/* Trigger transmission start */
742 	if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
743 	    !readl(txq->bd.reg_desc_active) ||
744 	    !readl(txq->bd.reg_desc_active) ||
745 	    !readl(txq->bd.reg_desc_active) ||
746 	    !readl(txq->bd.reg_desc_active))
747 		writel(0, txq->bd.reg_desc_active);
748 
749 	return 0;
750 
751 err_release:
752 	/* TODO: Release all used data descriptors for TSO */
753 	return ret;
754 }
755 
756 static netdev_tx_t
757 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
758 {
759 	struct fec_enet_private *fep = netdev_priv(ndev);
760 	int entries_free;
761 	unsigned short queue;
762 	struct fec_enet_priv_tx_q *txq;
763 	struct netdev_queue *nq;
764 	int ret;
765 
766 	queue = skb_get_queue_mapping(skb);
767 	txq = fep->tx_queue[queue];
768 	nq = netdev_get_tx_queue(ndev, queue);
769 
770 	if (skb_is_gso(skb))
771 		ret = fec_enet_txq_submit_tso(txq, skb, ndev);
772 	else
773 		ret = fec_enet_txq_submit_skb(txq, skb, ndev);
774 	if (ret)
775 		return ret;
776 
777 	entries_free = fec_enet_get_free_txdesc_num(txq);
778 	if (entries_free <= txq->tx_stop_threshold)
779 		netif_tx_stop_queue(nq);
780 
781 	return NETDEV_TX_OK;
782 }
783 
784 /* Init RX & TX buffer descriptors
785  */
786 static void fec_enet_bd_init(struct net_device *dev)
787 {
788 	struct fec_enet_private *fep = netdev_priv(dev);
789 	struct fec_enet_priv_tx_q *txq;
790 	struct fec_enet_priv_rx_q *rxq;
791 	struct bufdesc *bdp;
792 	unsigned int i;
793 	unsigned int q;
794 
795 	for (q = 0; q < fep->num_rx_queues; q++) {
796 		/* Initialize the receive buffer descriptors. */
797 		rxq = fep->rx_queue[q];
798 		bdp = rxq->bd.base;
799 
800 		for (i = 0; i < rxq->bd.ring_size; i++) {
801 
802 			/* Initialize the BD for every fragment in the page. */
803 			if (bdp->cbd_bufaddr)
804 				bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
805 			else
806 				bdp->cbd_sc = cpu_to_fec16(0);
807 			bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
808 		}
809 
810 		/* Set the last buffer to wrap */
811 		bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
812 		bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
813 
814 		rxq->bd.cur = rxq->bd.base;
815 	}
816 
817 	for (q = 0; q < fep->num_tx_queues; q++) {
818 		/* ...and the same for transmit */
819 		txq = fep->tx_queue[q];
820 		bdp = txq->bd.base;
821 		txq->bd.cur = bdp;
822 
823 		for (i = 0; i < txq->bd.ring_size; i++) {
824 			/* Initialize the BD for every fragment in the page. */
825 			bdp->cbd_sc = cpu_to_fec16(0);
826 			if (bdp->cbd_bufaddr &&
827 			    !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
828 				dma_unmap_single(&fep->pdev->dev,
829 						 fec32_to_cpu(bdp->cbd_bufaddr),
830 						 fec16_to_cpu(bdp->cbd_datlen),
831 						 DMA_TO_DEVICE);
832 			if (txq->tx_skbuff[i]) {
833 				dev_kfree_skb_any(txq->tx_skbuff[i]);
834 				txq->tx_skbuff[i] = NULL;
835 			}
836 			bdp->cbd_bufaddr = cpu_to_fec32(0);
837 			bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
838 		}
839 
840 		/* Set the last buffer to wrap */
841 		bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
842 		bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
843 		txq->dirty_tx = bdp;
844 	}
845 }
846 
847 static void fec_enet_active_rxring(struct net_device *ndev)
848 {
849 	struct fec_enet_private *fep = netdev_priv(ndev);
850 	int i;
851 
852 	for (i = 0; i < fep->num_rx_queues; i++)
853 		writel(0, fep->rx_queue[i]->bd.reg_desc_active);
854 }
855 
856 static void fec_enet_enable_ring(struct net_device *ndev)
857 {
858 	struct fec_enet_private *fep = netdev_priv(ndev);
859 	struct fec_enet_priv_tx_q *txq;
860 	struct fec_enet_priv_rx_q *rxq;
861 	int i;
862 
863 	for (i = 0; i < fep->num_rx_queues; i++) {
864 		rxq = fep->rx_queue[i];
865 		writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
866 		writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
867 
868 		/* enable DMA1/2 */
869 		if (i)
870 			writel(RCMR_MATCHEN | RCMR_CMP(i),
871 			       fep->hwp + FEC_RCMR(i));
872 	}
873 
874 	for (i = 0; i < fep->num_tx_queues; i++) {
875 		txq = fep->tx_queue[i];
876 		writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
877 
878 		/* enable DMA1/2 */
879 		if (i)
880 			writel(DMA_CLASS_EN | IDLE_SLOPE(i),
881 			       fep->hwp + FEC_DMA_CFG(i));
882 	}
883 }
884 
885 static void fec_enet_reset_skb(struct net_device *ndev)
886 {
887 	struct fec_enet_private *fep = netdev_priv(ndev);
888 	struct fec_enet_priv_tx_q *txq;
889 	int i, j;
890 
891 	for (i = 0; i < fep->num_tx_queues; i++) {
892 		txq = fep->tx_queue[i];
893 
894 		for (j = 0; j < txq->bd.ring_size; j++) {
895 			if (txq->tx_skbuff[j]) {
896 				dev_kfree_skb_any(txq->tx_skbuff[j]);
897 				txq->tx_skbuff[j] = NULL;
898 			}
899 		}
900 	}
901 }
902 
903 /*
904  * This function is called to start or restart the FEC during a link
905  * change, transmit timeout, or to reconfigure the FEC.  The network
906  * packet processing for this device must be stopped before this call.
907  */
908 static void
909 fec_restart(struct net_device *ndev)
910 {
911 	struct fec_enet_private *fep = netdev_priv(ndev);
912 	u32 val;
913 	u32 temp_mac[2];
914 	u32 rcntl = OPT_FRAME_SIZE | 0x04;
915 	u32 ecntl = 0x2; /* ETHEREN */
916 
917 	/* Whack a reset.  We should wait for this.
918 	 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
919 	 * instead of reset MAC itself.
920 	 */
921 	if (fep->quirks & FEC_QUIRK_HAS_AVB) {
922 		writel(0, fep->hwp + FEC_ECNTRL);
923 	} else {
924 		writel(1, fep->hwp + FEC_ECNTRL);
925 		udelay(10);
926 	}
927 
928 	/*
929 	 * enet-mac reset will reset mac address registers too,
930 	 * so need to reconfigure it.
931 	 */
932 	memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
933 	writel((__force u32)cpu_to_be32(temp_mac[0]),
934 	       fep->hwp + FEC_ADDR_LOW);
935 	writel((__force u32)cpu_to_be32(temp_mac[1]),
936 	       fep->hwp + FEC_ADDR_HIGH);
937 
938 	/* Clear any outstanding interrupt. */
939 	writel(0xffffffff, fep->hwp + FEC_IEVENT);
940 
941 	fec_enet_bd_init(ndev);
942 
943 	fec_enet_enable_ring(ndev);
944 
945 	/* Reset tx SKB buffers. */
946 	fec_enet_reset_skb(ndev);
947 
948 	/* Enable MII mode */
949 	if (fep->full_duplex == DUPLEX_FULL) {
950 		/* FD enable */
951 		writel(0x04, fep->hwp + FEC_X_CNTRL);
952 	} else {
953 		/* No Rcv on Xmit */
954 		rcntl |= 0x02;
955 		writel(0x0, fep->hwp + FEC_X_CNTRL);
956 	}
957 
958 	/* Set MII speed */
959 	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
960 
961 #if !defined(CONFIG_M5272)
962 	if (fep->quirks & FEC_QUIRK_HAS_RACC) {
963 		val = readl(fep->hwp + FEC_RACC);
964 		/* align IP header */
965 		val |= FEC_RACC_SHIFT16;
966 		if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
967 			/* set RX checksum */
968 			val |= FEC_RACC_OPTIONS;
969 		else
970 			val &= ~FEC_RACC_OPTIONS;
971 		writel(val, fep->hwp + FEC_RACC);
972 		writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
973 	}
974 #endif
975 
976 	/*
977 	 * The phy interface and speed need to get configured
978 	 * differently on enet-mac.
979 	 */
980 	if (fep->quirks & FEC_QUIRK_ENET_MAC) {
981 		/* Enable flow control and length check */
982 		rcntl |= 0x40000000 | 0x00000020;
983 
984 		/* RGMII, RMII or MII */
985 		if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
986 		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
987 		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
988 		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
989 			rcntl |= (1 << 6);
990 		else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
991 			rcntl |= (1 << 8);
992 		else
993 			rcntl &= ~(1 << 8);
994 
995 		/* 1G, 100M or 10M */
996 		if (ndev->phydev) {
997 			if (ndev->phydev->speed == SPEED_1000)
998 				ecntl |= (1 << 5);
999 			else if (ndev->phydev->speed == SPEED_100)
1000 				rcntl &= ~(1 << 9);
1001 			else
1002 				rcntl |= (1 << 9);
1003 		}
1004 	} else {
1005 #ifdef FEC_MIIGSK_ENR
1006 		if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1007 			u32 cfgr;
1008 			/* disable the gasket and wait */
1009 			writel(0, fep->hwp + FEC_MIIGSK_ENR);
1010 			while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1011 				udelay(1);
1012 
1013 			/*
1014 			 * configure the gasket:
1015 			 *   RMII, 50 MHz, no loopback, no echo
1016 			 *   MII, 25 MHz, no loopback, no echo
1017 			 */
1018 			cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1019 				? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1020 			if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1021 				cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1022 			writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1023 
1024 			/* re-enable the gasket */
1025 			writel(2, fep->hwp + FEC_MIIGSK_ENR);
1026 		}
1027 #endif
1028 	}
1029 
1030 #if !defined(CONFIG_M5272)
1031 	/* enable pause frame*/
1032 	if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1033 	    ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1034 	     ndev->phydev && ndev->phydev->pause)) {
1035 		rcntl |= FEC_ENET_FCE;
1036 
1037 		/* set FIFO threshold parameter to reduce overrun */
1038 		writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1039 		writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1040 		writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1041 		writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1042 
1043 		/* OPD */
1044 		writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1045 	} else {
1046 		rcntl &= ~FEC_ENET_FCE;
1047 	}
1048 #endif /* !defined(CONFIG_M5272) */
1049 
1050 	writel(rcntl, fep->hwp + FEC_R_CNTRL);
1051 
1052 	/* Setup multicast filter. */
1053 	set_multicast_list(ndev);
1054 #ifndef CONFIG_M5272
1055 	writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1056 	writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1057 #endif
1058 
1059 	if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1060 		/* enable ENET endian swap */
1061 		ecntl |= (1 << 8);
1062 		/* enable ENET store and forward mode */
1063 		writel(1 << 8, fep->hwp + FEC_X_WMRK);
1064 	}
1065 
1066 	if (fep->bufdesc_ex)
1067 		ecntl |= (1 << 4);
1068 
1069 #ifndef CONFIG_M5272
1070 	/* Enable the MIB statistic event counters */
1071 	writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1072 #endif
1073 
1074 	/* And last, enable the transmit and receive processing */
1075 	writel(ecntl, fep->hwp + FEC_ECNTRL);
1076 	fec_enet_active_rxring(ndev);
1077 
1078 	if (fep->bufdesc_ex)
1079 		fec_ptp_start_cyclecounter(ndev);
1080 
1081 	/* Enable interrupts we wish to service */
1082 	if (fep->link)
1083 		writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1084 	else
1085 		writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1086 
1087 	/* Init the interrupt coalescing */
1088 	fec_enet_itr_coal_init(ndev);
1089 
1090 }
1091 
1092 static void
1093 fec_stop(struct net_device *ndev)
1094 {
1095 	struct fec_enet_private *fep = netdev_priv(ndev);
1096 	struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1097 	u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1098 	u32 val;
1099 
1100 	/* We cannot expect a graceful transmit stop without link !!! */
1101 	if (fep->link) {
1102 		writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1103 		udelay(10);
1104 		if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1105 			netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1106 	}
1107 
1108 	/* Whack a reset.  We should wait for this.
1109 	 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1110 	 * instead of reset MAC itself.
1111 	 */
1112 	if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1113 		if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1114 			writel(0, fep->hwp + FEC_ECNTRL);
1115 		} else {
1116 			writel(1, fep->hwp + FEC_ECNTRL);
1117 			udelay(10);
1118 		}
1119 		writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1120 	} else {
1121 		writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1122 		val = readl(fep->hwp + FEC_ECNTRL);
1123 		val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1124 		writel(val, fep->hwp + FEC_ECNTRL);
1125 
1126 		if (pdata && pdata->sleep_mode_enable)
1127 			pdata->sleep_mode_enable(true);
1128 	}
1129 	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1130 
1131 	/* We have to keep ENET enabled to have MII interrupt stay working */
1132 	if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1133 		!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1134 		writel(2, fep->hwp + FEC_ECNTRL);
1135 		writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1136 	}
1137 }
1138 
1139 
1140 static void
1141 fec_timeout(struct net_device *ndev)
1142 {
1143 	struct fec_enet_private *fep = netdev_priv(ndev);
1144 
1145 	fec_dump(ndev);
1146 
1147 	ndev->stats.tx_errors++;
1148 
1149 	schedule_work(&fep->tx_timeout_work);
1150 }
1151 
1152 static void fec_enet_timeout_work(struct work_struct *work)
1153 {
1154 	struct fec_enet_private *fep =
1155 		container_of(work, struct fec_enet_private, tx_timeout_work);
1156 	struct net_device *ndev = fep->netdev;
1157 
1158 	rtnl_lock();
1159 	if (netif_device_present(ndev) || netif_running(ndev)) {
1160 		napi_disable(&fep->napi);
1161 		netif_tx_lock_bh(ndev);
1162 		fec_restart(ndev);
1163 		netif_tx_wake_all_queues(ndev);
1164 		netif_tx_unlock_bh(ndev);
1165 		napi_enable(&fep->napi);
1166 	}
1167 	rtnl_unlock();
1168 }
1169 
1170 static void
1171 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1172 	struct skb_shared_hwtstamps *hwtstamps)
1173 {
1174 	unsigned long flags;
1175 	u64 ns;
1176 
1177 	spin_lock_irqsave(&fep->tmreg_lock, flags);
1178 	ns = timecounter_cyc2time(&fep->tc, ts);
1179 	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1180 
1181 	memset(hwtstamps, 0, sizeof(*hwtstamps));
1182 	hwtstamps->hwtstamp = ns_to_ktime(ns);
1183 }
1184 
1185 static void
1186 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1187 {
1188 	struct	fec_enet_private *fep;
1189 	struct bufdesc *bdp;
1190 	unsigned short status;
1191 	struct	sk_buff	*skb;
1192 	struct fec_enet_priv_tx_q *txq;
1193 	struct netdev_queue *nq;
1194 	int	index = 0;
1195 	int	entries_free;
1196 
1197 	fep = netdev_priv(ndev);
1198 
1199 	queue_id = FEC_ENET_GET_QUQUE(queue_id);
1200 
1201 	txq = fep->tx_queue[queue_id];
1202 	/* get next bdp of dirty_tx */
1203 	nq = netdev_get_tx_queue(ndev, queue_id);
1204 	bdp = txq->dirty_tx;
1205 
1206 	/* get next bdp of dirty_tx */
1207 	bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1208 
1209 	while (bdp != READ_ONCE(txq->bd.cur)) {
1210 		/* Order the load of bd.cur and cbd_sc */
1211 		rmb();
1212 		status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1213 		if (status & BD_ENET_TX_READY)
1214 			break;
1215 
1216 		index = fec_enet_get_bd_index(bdp, &txq->bd);
1217 
1218 		skb = txq->tx_skbuff[index];
1219 		txq->tx_skbuff[index] = NULL;
1220 		if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1221 			dma_unmap_single(&fep->pdev->dev,
1222 					 fec32_to_cpu(bdp->cbd_bufaddr),
1223 					 fec16_to_cpu(bdp->cbd_datlen),
1224 					 DMA_TO_DEVICE);
1225 		bdp->cbd_bufaddr = cpu_to_fec32(0);
1226 		if (!skb)
1227 			goto skb_done;
1228 
1229 		/* Check for errors. */
1230 		if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1231 				   BD_ENET_TX_RL | BD_ENET_TX_UN |
1232 				   BD_ENET_TX_CSL)) {
1233 			ndev->stats.tx_errors++;
1234 			if (status & BD_ENET_TX_HB)  /* No heartbeat */
1235 				ndev->stats.tx_heartbeat_errors++;
1236 			if (status & BD_ENET_TX_LC)  /* Late collision */
1237 				ndev->stats.tx_window_errors++;
1238 			if (status & BD_ENET_TX_RL)  /* Retrans limit */
1239 				ndev->stats.tx_aborted_errors++;
1240 			if (status & BD_ENET_TX_UN)  /* Underrun */
1241 				ndev->stats.tx_fifo_errors++;
1242 			if (status & BD_ENET_TX_CSL) /* Carrier lost */
1243 				ndev->stats.tx_carrier_errors++;
1244 		} else {
1245 			ndev->stats.tx_packets++;
1246 			ndev->stats.tx_bytes += skb->len;
1247 		}
1248 
1249 		if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1250 			fep->bufdesc_ex) {
1251 			struct skb_shared_hwtstamps shhwtstamps;
1252 			struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1253 
1254 			fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1255 			skb_tstamp_tx(skb, &shhwtstamps);
1256 		}
1257 
1258 		/* Deferred means some collisions occurred during transmit,
1259 		 * but we eventually sent the packet OK.
1260 		 */
1261 		if (status & BD_ENET_TX_DEF)
1262 			ndev->stats.collisions++;
1263 
1264 		/* Free the sk buffer associated with this last transmit */
1265 		dev_kfree_skb_any(skb);
1266 skb_done:
1267 		/* Make sure the update to bdp and tx_skbuff are performed
1268 		 * before dirty_tx
1269 		 */
1270 		wmb();
1271 		txq->dirty_tx = bdp;
1272 
1273 		/* Update pointer to next buffer descriptor to be transmitted */
1274 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1275 
1276 		/* Since we have freed up a buffer, the ring is no longer full
1277 		 */
1278 		if (netif_tx_queue_stopped(nq)) {
1279 			entries_free = fec_enet_get_free_txdesc_num(txq);
1280 			if (entries_free >= txq->tx_wake_threshold)
1281 				netif_tx_wake_queue(nq);
1282 		}
1283 	}
1284 
1285 	/* ERR006358: Keep the transmitter going */
1286 	if (bdp != txq->bd.cur &&
1287 	    readl(txq->bd.reg_desc_active) == 0)
1288 		writel(0, txq->bd.reg_desc_active);
1289 }
1290 
1291 static void
1292 fec_enet_tx(struct net_device *ndev)
1293 {
1294 	struct fec_enet_private *fep = netdev_priv(ndev);
1295 	u16 queue_id;
1296 	/* First process class A queue, then Class B and Best Effort queue */
1297 	for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1298 		clear_bit(queue_id, &fep->work_tx);
1299 		fec_enet_tx_queue(ndev, queue_id);
1300 	}
1301 	return;
1302 }
1303 
1304 static int
1305 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1306 {
1307 	struct  fec_enet_private *fep = netdev_priv(ndev);
1308 	int off;
1309 
1310 	off = ((unsigned long)skb->data) & fep->rx_align;
1311 	if (off)
1312 		skb_reserve(skb, fep->rx_align + 1 - off);
1313 
1314 	bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1315 	if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1316 		if (net_ratelimit())
1317 			netdev_err(ndev, "Rx DMA memory map failed\n");
1318 		return -ENOMEM;
1319 	}
1320 
1321 	return 0;
1322 }
1323 
1324 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1325 			       struct bufdesc *bdp, u32 length, bool swap)
1326 {
1327 	struct  fec_enet_private *fep = netdev_priv(ndev);
1328 	struct sk_buff *new_skb;
1329 
1330 	if (length > fep->rx_copybreak)
1331 		return false;
1332 
1333 	new_skb = netdev_alloc_skb(ndev, length);
1334 	if (!new_skb)
1335 		return false;
1336 
1337 	dma_sync_single_for_cpu(&fep->pdev->dev,
1338 				fec32_to_cpu(bdp->cbd_bufaddr),
1339 				FEC_ENET_RX_FRSIZE - fep->rx_align,
1340 				DMA_FROM_DEVICE);
1341 	if (!swap)
1342 		memcpy(new_skb->data, (*skb)->data, length);
1343 	else
1344 		swap_buffer2(new_skb->data, (*skb)->data, length);
1345 	*skb = new_skb;
1346 
1347 	return true;
1348 }
1349 
1350 /* During a receive, the bd_rx.cur points to the current incoming buffer.
1351  * When we update through the ring, if the next incoming buffer has
1352  * not been given to the system, we just set the empty indicator,
1353  * effectively tossing the packet.
1354  */
1355 static int
1356 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1357 {
1358 	struct fec_enet_private *fep = netdev_priv(ndev);
1359 	struct fec_enet_priv_rx_q *rxq;
1360 	struct bufdesc *bdp;
1361 	unsigned short status;
1362 	struct  sk_buff *skb_new = NULL;
1363 	struct  sk_buff *skb;
1364 	ushort	pkt_len;
1365 	__u8 *data;
1366 	int	pkt_received = 0;
1367 	struct	bufdesc_ex *ebdp = NULL;
1368 	bool	vlan_packet_rcvd = false;
1369 	u16	vlan_tag;
1370 	int	index = 0;
1371 	bool	is_copybreak;
1372 	bool	need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1373 
1374 #ifdef CONFIG_M532x
1375 	flush_cache_all();
1376 #endif
1377 	queue_id = FEC_ENET_GET_QUQUE(queue_id);
1378 	rxq = fep->rx_queue[queue_id];
1379 
1380 	/* First, grab all of the stats for the incoming packet.
1381 	 * These get messed up if we get called due to a busy condition.
1382 	 */
1383 	bdp = rxq->bd.cur;
1384 
1385 	while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1386 
1387 		if (pkt_received >= budget)
1388 			break;
1389 		pkt_received++;
1390 
1391 		writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1392 
1393 		/* Check for errors. */
1394 		status ^= BD_ENET_RX_LAST;
1395 		if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1396 			   BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1397 			   BD_ENET_RX_CL)) {
1398 			ndev->stats.rx_errors++;
1399 			if (status & BD_ENET_RX_OV) {
1400 				/* FIFO overrun */
1401 				ndev->stats.rx_fifo_errors++;
1402 				goto rx_processing_done;
1403 			}
1404 			if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1405 						| BD_ENET_RX_LAST)) {
1406 				/* Frame too long or too short. */
1407 				ndev->stats.rx_length_errors++;
1408 				if (status & BD_ENET_RX_LAST)
1409 					netdev_err(ndev, "rcv is not +last\n");
1410 			}
1411 			if (status & BD_ENET_RX_CR)	/* CRC Error */
1412 				ndev->stats.rx_crc_errors++;
1413 			/* Report late collisions as a frame error. */
1414 			if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1415 				ndev->stats.rx_frame_errors++;
1416 			goto rx_processing_done;
1417 		}
1418 
1419 		/* Process the incoming frame. */
1420 		ndev->stats.rx_packets++;
1421 		pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1422 		ndev->stats.rx_bytes += pkt_len;
1423 
1424 		index = fec_enet_get_bd_index(bdp, &rxq->bd);
1425 		skb = rxq->rx_skbuff[index];
1426 
1427 		/* The packet length includes FCS, but we don't want to
1428 		 * include that when passing upstream as it messes up
1429 		 * bridging applications.
1430 		 */
1431 		is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1432 						  need_swap);
1433 		if (!is_copybreak) {
1434 			skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1435 			if (unlikely(!skb_new)) {
1436 				ndev->stats.rx_dropped++;
1437 				goto rx_processing_done;
1438 			}
1439 			dma_unmap_single(&fep->pdev->dev,
1440 					 fec32_to_cpu(bdp->cbd_bufaddr),
1441 					 FEC_ENET_RX_FRSIZE - fep->rx_align,
1442 					 DMA_FROM_DEVICE);
1443 		}
1444 
1445 		prefetch(skb->data - NET_IP_ALIGN);
1446 		skb_put(skb, pkt_len - 4);
1447 		data = skb->data;
1448 
1449 		if (!is_copybreak && need_swap)
1450 			swap_buffer(data, pkt_len);
1451 
1452 #if !defined(CONFIG_M5272)
1453 		if (fep->quirks & FEC_QUIRK_HAS_RACC)
1454 			data = skb_pull_inline(skb, 2);
1455 #endif
1456 
1457 		/* Extract the enhanced buffer descriptor */
1458 		ebdp = NULL;
1459 		if (fep->bufdesc_ex)
1460 			ebdp = (struct bufdesc_ex *)bdp;
1461 
1462 		/* If this is a VLAN packet remove the VLAN Tag */
1463 		vlan_packet_rcvd = false;
1464 		if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1465 		    fep->bufdesc_ex &&
1466 		    (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1467 			/* Push and remove the vlan tag */
1468 			struct vlan_hdr *vlan_header =
1469 					(struct vlan_hdr *) (data + ETH_HLEN);
1470 			vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1471 
1472 			vlan_packet_rcvd = true;
1473 
1474 			memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1475 			skb_pull(skb, VLAN_HLEN);
1476 		}
1477 
1478 		skb->protocol = eth_type_trans(skb, ndev);
1479 
1480 		/* Get receive timestamp from the skb */
1481 		if (fep->hwts_rx_en && fep->bufdesc_ex)
1482 			fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1483 					  skb_hwtstamps(skb));
1484 
1485 		if (fep->bufdesc_ex &&
1486 		    (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1487 			if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1488 				/* don't check it */
1489 				skb->ip_summed = CHECKSUM_UNNECESSARY;
1490 			} else {
1491 				skb_checksum_none_assert(skb);
1492 			}
1493 		}
1494 
1495 		/* Handle received VLAN packets */
1496 		if (vlan_packet_rcvd)
1497 			__vlan_hwaccel_put_tag(skb,
1498 					       htons(ETH_P_8021Q),
1499 					       vlan_tag);
1500 
1501 		napi_gro_receive(&fep->napi, skb);
1502 
1503 		if (is_copybreak) {
1504 			dma_sync_single_for_device(&fep->pdev->dev,
1505 						   fec32_to_cpu(bdp->cbd_bufaddr),
1506 						   FEC_ENET_RX_FRSIZE - fep->rx_align,
1507 						   DMA_FROM_DEVICE);
1508 		} else {
1509 			rxq->rx_skbuff[index] = skb_new;
1510 			fec_enet_new_rxbdp(ndev, bdp, skb_new);
1511 		}
1512 
1513 rx_processing_done:
1514 		/* Clear the status flags for this buffer */
1515 		status &= ~BD_ENET_RX_STATS;
1516 
1517 		/* Mark the buffer empty */
1518 		status |= BD_ENET_RX_EMPTY;
1519 
1520 		if (fep->bufdesc_ex) {
1521 			struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1522 
1523 			ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1524 			ebdp->cbd_prot = 0;
1525 			ebdp->cbd_bdu = 0;
1526 		}
1527 		/* Make sure the updates to rest of the descriptor are
1528 		 * performed before transferring ownership.
1529 		 */
1530 		wmb();
1531 		bdp->cbd_sc = cpu_to_fec16(status);
1532 
1533 		/* Update BD pointer to next entry */
1534 		bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1535 
1536 		/* Doing this here will keep the FEC running while we process
1537 		 * incoming frames.  On a heavily loaded network, we should be
1538 		 * able to keep up at the expense of system resources.
1539 		 */
1540 		writel(0, rxq->bd.reg_desc_active);
1541 	}
1542 	rxq->bd.cur = bdp;
1543 	return pkt_received;
1544 }
1545 
1546 static int
1547 fec_enet_rx(struct net_device *ndev, int budget)
1548 {
1549 	int     pkt_received = 0;
1550 	u16	queue_id;
1551 	struct fec_enet_private *fep = netdev_priv(ndev);
1552 
1553 	for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1554 		int ret;
1555 
1556 		ret = fec_enet_rx_queue(ndev,
1557 					budget - pkt_received, queue_id);
1558 
1559 		if (ret < budget - pkt_received)
1560 			clear_bit(queue_id, &fep->work_rx);
1561 
1562 		pkt_received += ret;
1563 	}
1564 	return pkt_received;
1565 }
1566 
1567 static bool
1568 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1569 {
1570 	if (int_events == 0)
1571 		return false;
1572 
1573 	if (int_events & FEC_ENET_RXF_0)
1574 		fep->work_rx |= (1 << 2);
1575 	if (int_events & FEC_ENET_RXF_1)
1576 		fep->work_rx |= (1 << 0);
1577 	if (int_events & FEC_ENET_RXF_2)
1578 		fep->work_rx |= (1 << 1);
1579 
1580 	if (int_events & FEC_ENET_TXF_0)
1581 		fep->work_tx |= (1 << 2);
1582 	if (int_events & FEC_ENET_TXF_1)
1583 		fep->work_tx |= (1 << 0);
1584 	if (int_events & FEC_ENET_TXF_2)
1585 		fep->work_tx |= (1 << 1);
1586 
1587 	return true;
1588 }
1589 
1590 static irqreturn_t
1591 fec_enet_interrupt(int irq, void *dev_id)
1592 {
1593 	struct net_device *ndev = dev_id;
1594 	struct fec_enet_private *fep = netdev_priv(ndev);
1595 	uint int_events;
1596 	irqreturn_t ret = IRQ_NONE;
1597 
1598 	int_events = readl(fep->hwp + FEC_IEVENT);
1599 	writel(int_events, fep->hwp + FEC_IEVENT);
1600 	fec_enet_collect_events(fep, int_events);
1601 
1602 	if ((fep->work_tx || fep->work_rx) && fep->link) {
1603 		ret = IRQ_HANDLED;
1604 
1605 		if (napi_schedule_prep(&fep->napi)) {
1606 			/* Disable the NAPI interrupts */
1607 			writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK);
1608 			__napi_schedule(&fep->napi);
1609 		}
1610 	}
1611 
1612 	if (int_events & FEC_ENET_MII) {
1613 		ret = IRQ_HANDLED;
1614 		complete(&fep->mdio_done);
1615 	}
1616 	return ret;
1617 }
1618 
1619 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1620 {
1621 	struct net_device *ndev = napi->dev;
1622 	struct fec_enet_private *fep = netdev_priv(ndev);
1623 	int pkts;
1624 
1625 	pkts = fec_enet_rx(ndev, budget);
1626 
1627 	fec_enet_tx(ndev);
1628 
1629 	if (pkts < budget) {
1630 		napi_complete_done(napi, pkts);
1631 		writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1632 	}
1633 	return pkts;
1634 }
1635 
1636 /* ------------------------------------------------------------------------- */
1637 static void fec_get_mac(struct net_device *ndev)
1638 {
1639 	struct fec_enet_private *fep = netdev_priv(ndev);
1640 	struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1641 	unsigned char *iap, tmpaddr[ETH_ALEN];
1642 
1643 	/*
1644 	 * try to get mac address in following order:
1645 	 *
1646 	 * 1) module parameter via kernel command line in form
1647 	 *    fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1648 	 */
1649 	iap = macaddr;
1650 
1651 	/*
1652 	 * 2) from device tree data
1653 	 */
1654 	if (!is_valid_ether_addr(iap)) {
1655 		struct device_node *np = fep->pdev->dev.of_node;
1656 		if (np) {
1657 			const char *mac = of_get_mac_address(np);
1658 			if (mac)
1659 				iap = (unsigned char *) mac;
1660 		}
1661 	}
1662 
1663 	/*
1664 	 * 3) from flash or fuse (via platform data)
1665 	 */
1666 	if (!is_valid_ether_addr(iap)) {
1667 #ifdef CONFIG_M5272
1668 		if (FEC_FLASHMAC)
1669 			iap = (unsigned char *)FEC_FLASHMAC;
1670 #else
1671 		if (pdata)
1672 			iap = (unsigned char *)&pdata->mac;
1673 #endif
1674 	}
1675 
1676 	/*
1677 	 * 4) FEC mac registers set by bootloader
1678 	 */
1679 	if (!is_valid_ether_addr(iap)) {
1680 		*((__be32 *) &tmpaddr[0]) =
1681 			cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1682 		*((__be16 *) &tmpaddr[4]) =
1683 			cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1684 		iap = &tmpaddr[0];
1685 	}
1686 
1687 	/*
1688 	 * 5) random mac address
1689 	 */
1690 	if (!is_valid_ether_addr(iap)) {
1691 		/* Report it and use a random ethernet address instead */
1692 		netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1693 		eth_hw_addr_random(ndev);
1694 		netdev_info(ndev, "Using random MAC address: %pM\n",
1695 			    ndev->dev_addr);
1696 		return;
1697 	}
1698 
1699 	memcpy(ndev->dev_addr, iap, ETH_ALEN);
1700 
1701 	/* Adjust MAC if using macaddr */
1702 	if (iap == macaddr)
1703 		 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1704 }
1705 
1706 /* ------------------------------------------------------------------------- */
1707 
1708 /*
1709  * Phy section
1710  */
1711 static void fec_enet_adjust_link(struct net_device *ndev)
1712 {
1713 	struct fec_enet_private *fep = netdev_priv(ndev);
1714 	struct phy_device *phy_dev = ndev->phydev;
1715 	int status_change = 0;
1716 
1717 	/*
1718 	 * If the netdev is down, or is going down, we're not interested
1719 	 * in link state events, so just mark our idea of the link as down
1720 	 * and ignore the event.
1721 	 */
1722 	if (!netif_running(ndev) || !netif_device_present(ndev)) {
1723 		fep->link = 0;
1724 	} else if (phy_dev->link) {
1725 		if (!fep->link) {
1726 			fep->link = phy_dev->link;
1727 			status_change = 1;
1728 		}
1729 
1730 		if (fep->full_duplex != phy_dev->duplex) {
1731 			fep->full_duplex = phy_dev->duplex;
1732 			status_change = 1;
1733 		}
1734 
1735 		if (phy_dev->speed != fep->speed) {
1736 			fep->speed = phy_dev->speed;
1737 			status_change = 1;
1738 		}
1739 
1740 		/* if any of the above changed restart the FEC */
1741 		if (status_change) {
1742 			napi_disable(&fep->napi);
1743 			netif_tx_lock_bh(ndev);
1744 			fec_restart(ndev);
1745 			netif_tx_wake_all_queues(ndev);
1746 			netif_tx_unlock_bh(ndev);
1747 			napi_enable(&fep->napi);
1748 		}
1749 	} else {
1750 		if (fep->link) {
1751 			napi_disable(&fep->napi);
1752 			netif_tx_lock_bh(ndev);
1753 			fec_stop(ndev);
1754 			netif_tx_unlock_bh(ndev);
1755 			napi_enable(&fep->napi);
1756 			fep->link = phy_dev->link;
1757 			status_change = 1;
1758 		}
1759 	}
1760 
1761 	if (status_change)
1762 		phy_print_status(phy_dev);
1763 }
1764 
1765 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1766 {
1767 	struct fec_enet_private *fep = bus->priv;
1768 	struct device *dev = &fep->pdev->dev;
1769 	unsigned long time_left;
1770 	int ret = 0;
1771 
1772 	ret = pm_runtime_get_sync(dev);
1773 	if (ret < 0)
1774 		return ret;
1775 
1776 	reinit_completion(&fep->mdio_done);
1777 
1778 	/* start a read op */
1779 	writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1780 		FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1781 		FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1782 
1783 	/* wait for end of transfer */
1784 	time_left = wait_for_completion_timeout(&fep->mdio_done,
1785 			usecs_to_jiffies(FEC_MII_TIMEOUT));
1786 	if (time_left == 0) {
1787 		netdev_err(fep->netdev, "MDIO read timeout\n");
1788 		ret = -ETIMEDOUT;
1789 		goto out;
1790 	}
1791 
1792 	ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1793 
1794 out:
1795 	pm_runtime_mark_last_busy(dev);
1796 	pm_runtime_put_autosuspend(dev);
1797 
1798 	return ret;
1799 }
1800 
1801 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1802 			   u16 value)
1803 {
1804 	struct fec_enet_private *fep = bus->priv;
1805 	struct device *dev = &fep->pdev->dev;
1806 	unsigned long time_left;
1807 	int ret;
1808 
1809 	ret = pm_runtime_get_sync(dev);
1810 	if (ret < 0)
1811 		return ret;
1812 	else
1813 		ret = 0;
1814 
1815 	reinit_completion(&fep->mdio_done);
1816 
1817 	/* start a write op */
1818 	writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1819 		FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1820 		FEC_MMFR_TA | FEC_MMFR_DATA(value),
1821 		fep->hwp + FEC_MII_DATA);
1822 
1823 	/* wait for end of transfer */
1824 	time_left = wait_for_completion_timeout(&fep->mdio_done,
1825 			usecs_to_jiffies(FEC_MII_TIMEOUT));
1826 	if (time_left == 0) {
1827 		netdev_err(fep->netdev, "MDIO write timeout\n");
1828 		ret  = -ETIMEDOUT;
1829 	}
1830 
1831 	pm_runtime_mark_last_busy(dev);
1832 	pm_runtime_put_autosuspend(dev);
1833 
1834 	return ret;
1835 }
1836 
1837 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1838 {
1839 	struct fec_enet_private *fep = netdev_priv(ndev);
1840 	int ret;
1841 
1842 	if (enable) {
1843 		ret = clk_prepare_enable(fep->clk_ahb);
1844 		if (ret)
1845 			return ret;
1846 
1847 		ret = clk_prepare_enable(fep->clk_enet_out);
1848 		if (ret)
1849 			goto failed_clk_enet_out;
1850 
1851 		if (fep->clk_ptp) {
1852 			mutex_lock(&fep->ptp_clk_mutex);
1853 			ret = clk_prepare_enable(fep->clk_ptp);
1854 			if (ret) {
1855 				mutex_unlock(&fep->ptp_clk_mutex);
1856 				goto failed_clk_ptp;
1857 			} else {
1858 				fep->ptp_clk_on = true;
1859 			}
1860 			mutex_unlock(&fep->ptp_clk_mutex);
1861 		}
1862 
1863 		ret = clk_prepare_enable(fep->clk_ref);
1864 		if (ret)
1865 			goto failed_clk_ref;
1866 
1867 		phy_reset_after_clk_enable(ndev->phydev);
1868 	} else {
1869 		clk_disable_unprepare(fep->clk_ahb);
1870 		clk_disable_unprepare(fep->clk_enet_out);
1871 		if (fep->clk_ptp) {
1872 			mutex_lock(&fep->ptp_clk_mutex);
1873 			clk_disable_unprepare(fep->clk_ptp);
1874 			fep->ptp_clk_on = false;
1875 			mutex_unlock(&fep->ptp_clk_mutex);
1876 		}
1877 		clk_disable_unprepare(fep->clk_ref);
1878 	}
1879 
1880 	return 0;
1881 
1882 failed_clk_ref:
1883 	if (fep->clk_ref)
1884 		clk_disable_unprepare(fep->clk_ref);
1885 failed_clk_ptp:
1886 	if (fep->clk_enet_out)
1887 		clk_disable_unprepare(fep->clk_enet_out);
1888 failed_clk_enet_out:
1889 		clk_disable_unprepare(fep->clk_ahb);
1890 
1891 	return ret;
1892 }
1893 
1894 static int fec_enet_mii_probe(struct net_device *ndev)
1895 {
1896 	struct fec_enet_private *fep = netdev_priv(ndev);
1897 	struct phy_device *phy_dev = NULL;
1898 	char mdio_bus_id[MII_BUS_ID_SIZE];
1899 	char phy_name[MII_BUS_ID_SIZE + 3];
1900 	int phy_id;
1901 	int dev_id = fep->dev_id;
1902 
1903 	if (fep->phy_node) {
1904 		phy_dev = of_phy_connect(ndev, fep->phy_node,
1905 					 &fec_enet_adjust_link, 0,
1906 					 fep->phy_interface);
1907 		if (!phy_dev) {
1908 			netdev_err(ndev, "Unable to connect to phy\n");
1909 			return -ENODEV;
1910 		}
1911 	} else {
1912 		/* check for attached phy */
1913 		for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1914 			if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
1915 				continue;
1916 			if (dev_id--)
1917 				continue;
1918 			strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1919 			break;
1920 		}
1921 
1922 		if (phy_id >= PHY_MAX_ADDR) {
1923 			netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1924 			strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1925 			phy_id = 0;
1926 		}
1927 
1928 		snprintf(phy_name, sizeof(phy_name),
1929 			 PHY_ID_FMT, mdio_bus_id, phy_id);
1930 		phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1931 				      fep->phy_interface);
1932 	}
1933 
1934 	if (IS_ERR(phy_dev)) {
1935 		netdev_err(ndev, "could not attach to PHY\n");
1936 		return PTR_ERR(phy_dev);
1937 	}
1938 
1939 	/* mask with MAC supported features */
1940 	if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1941 		phy_set_max_speed(phy_dev, 1000);
1942 		phy_remove_link_mode(phy_dev,
1943 				     ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1944 #if !defined(CONFIG_M5272)
1945 		phy_support_sym_pause(phy_dev);
1946 #endif
1947 	}
1948 	else
1949 		phy_set_max_speed(phy_dev, 100);
1950 
1951 	fep->link = 0;
1952 	fep->full_duplex = 0;
1953 
1954 	phy_attached_info(phy_dev);
1955 
1956 	return 0;
1957 }
1958 
1959 static int fec_enet_mii_init(struct platform_device *pdev)
1960 {
1961 	static struct mii_bus *fec0_mii_bus;
1962 	struct net_device *ndev = platform_get_drvdata(pdev);
1963 	struct fec_enet_private *fep = netdev_priv(ndev);
1964 	struct device_node *node;
1965 	int err = -ENXIO;
1966 	u32 mii_speed, holdtime;
1967 
1968 	/*
1969 	 * The i.MX28 dual fec interfaces are not equal.
1970 	 * Here are the differences:
1971 	 *
1972 	 *  - fec0 supports MII & RMII modes while fec1 only supports RMII
1973 	 *  - fec0 acts as the 1588 time master while fec1 is slave
1974 	 *  - external phys can only be configured by fec0
1975 	 *
1976 	 * That is to say fec1 can not work independently. It only works
1977 	 * when fec0 is working. The reason behind this design is that the
1978 	 * second interface is added primarily for Switch mode.
1979 	 *
1980 	 * Because of the last point above, both phys are attached on fec0
1981 	 * mdio interface in board design, and need to be configured by
1982 	 * fec0 mii_bus.
1983 	 */
1984 	if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
1985 		/* fec1 uses fec0 mii_bus */
1986 		if (mii_cnt && fec0_mii_bus) {
1987 			fep->mii_bus = fec0_mii_bus;
1988 			mii_cnt++;
1989 			return 0;
1990 		}
1991 		return -ENOENT;
1992 	}
1993 
1994 	/*
1995 	 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1996 	 *
1997 	 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1998 	 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'.  The i.MX28
1999 	 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2000 	 * document.
2001 	 */
2002 	mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
2003 	if (fep->quirks & FEC_QUIRK_ENET_MAC)
2004 		mii_speed--;
2005 	if (mii_speed > 63) {
2006 		dev_err(&pdev->dev,
2007 			"fec clock (%lu) too fast to get right mii speed\n",
2008 			clk_get_rate(fep->clk_ipg));
2009 		err = -EINVAL;
2010 		goto err_out;
2011 	}
2012 
2013 	/*
2014 	 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2015 	 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2016 	 * versions are RAZ there, so just ignore the difference and write the
2017 	 * register always.
2018 	 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2019 	 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2020 	 * output.
2021 	 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2022 	 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2023 	 * holdtime cannot result in a value greater than 3.
2024 	 */
2025 	holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2026 
2027 	fep->phy_speed = mii_speed << 1 | holdtime << 8;
2028 
2029 	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2030 
2031 	fep->mii_bus = mdiobus_alloc();
2032 	if (fep->mii_bus == NULL) {
2033 		err = -ENOMEM;
2034 		goto err_out;
2035 	}
2036 
2037 	fep->mii_bus->name = "fec_enet_mii_bus";
2038 	fep->mii_bus->read = fec_enet_mdio_read;
2039 	fep->mii_bus->write = fec_enet_mdio_write;
2040 	snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2041 		pdev->name, fep->dev_id + 1);
2042 	fep->mii_bus->priv = fep;
2043 	fep->mii_bus->parent = &pdev->dev;
2044 
2045 	node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2046 	err = of_mdiobus_register(fep->mii_bus, node);
2047 	of_node_put(node);
2048 	if (err)
2049 		goto err_out_free_mdiobus;
2050 
2051 	mii_cnt++;
2052 
2053 	/* save fec0 mii_bus */
2054 	if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2055 		fec0_mii_bus = fep->mii_bus;
2056 
2057 	return 0;
2058 
2059 err_out_free_mdiobus:
2060 	mdiobus_free(fep->mii_bus);
2061 err_out:
2062 	return err;
2063 }
2064 
2065 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2066 {
2067 	if (--mii_cnt == 0) {
2068 		mdiobus_unregister(fep->mii_bus);
2069 		mdiobus_free(fep->mii_bus);
2070 	}
2071 }
2072 
2073 static void fec_enet_get_drvinfo(struct net_device *ndev,
2074 				 struct ethtool_drvinfo *info)
2075 {
2076 	struct fec_enet_private *fep = netdev_priv(ndev);
2077 
2078 	strlcpy(info->driver, fep->pdev->dev.driver->name,
2079 		sizeof(info->driver));
2080 	strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2081 	strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2082 }
2083 
2084 static int fec_enet_get_regs_len(struct net_device *ndev)
2085 {
2086 	struct fec_enet_private *fep = netdev_priv(ndev);
2087 	struct resource *r;
2088 	int s = 0;
2089 
2090 	r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2091 	if (r)
2092 		s = resource_size(r);
2093 
2094 	return s;
2095 }
2096 
2097 /* List of registers that can be safety be read to dump them with ethtool */
2098 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2099 	defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2100 	defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2101 static u32 fec_enet_register_offset[] = {
2102 	FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2103 	FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2104 	FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2105 	FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2106 	FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2107 	FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2108 	FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2109 	FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2110 	FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2111 	FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2112 	FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2113 	FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2114 	RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2115 	RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2116 	RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2117 	RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2118 	RMON_T_P_GTE2048, RMON_T_OCTETS,
2119 	IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2120 	IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2121 	IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2122 	RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2123 	RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2124 	RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2125 	RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2126 	RMON_R_P_GTE2048, RMON_R_OCTETS,
2127 	IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2128 	IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2129 };
2130 #else
2131 static u32 fec_enet_register_offset[] = {
2132 	FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2133 	FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2134 	FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2135 	FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2136 	FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2137 	FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2138 	FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2139 	FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2140 	FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2141 };
2142 #endif
2143 
2144 static void fec_enet_get_regs(struct net_device *ndev,
2145 			      struct ethtool_regs *regs, void *regbuf)
2146 {
2147 	struct fec_enet_private *fep = netdev_priv(ndev);
2148 	u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2149 	u32 *buf = (u32 *)regbuf;
2150 	u32 i, off;
2151 
2152 	memset(buf, 0, regs->len);
2153 
2154 	for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2155 		off = fec_enet_register_offset[i];
2156 
2157 		if ((off == FEC_R_BOUND || off == FEC_R_FSTART) &&
2158 		    !(fep->quirks & FEC_QUIRK_HAS_FRREG))
2159 			continue;
2160 
2161 		off >>= 2;
2162 		buf[off] = readl(&theregs[off]);
2163 	}
2164 }
2165 
2166 static int fec_enet_get_ts_info(struct net_device *ndev,
2167 				struct ethtool_ts_info *info)
2168 {
2169 	struct fec_enet_private *fep = netdev_priv(ndev);
2170 
2171 	if (fep->bufdesc_ex) {
2172 
2173 		info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2174 					SOF_TIMESTAMPING_RX_SOFTWARE |
2175 					SOF_TIMESTAMPING_SOFTWARE |
2176 					SOF_TIMESTAMPING_TX_HARDWARE |
2177 					SOF_TIMESTAMPING_RX_HARDWARE |
2178 					SOF_TIMESTAMPING_RAW_HARDWARE;
2179 		if (fep->ptp_clock)
2180 			info->phc_index = ptp_clock_index(fep->ptp_clock);
2181 		else
2182 			info->phc_index = -1;
2183 
2184 		info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2185 				 (1 << HWTSTAMP_TX_ON);
2186 
2187 		info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2188 				   (1 << HWTSTAMP_FILTER_ALL);
2189 		return 0;
2190 	} else {
2191 		return ethtool_op_get_ts_info(ndev, info);
2192 	}
2193 }
2194 
2195 #if !defined(CONFIG_M5272)
2196 
2197 static void fec_enet_get_pauseparam(struct net_device *ndev,
2198 				    struct ethtool_pauseparam *pause)
2199 {
2200 	struct fec_enet_private *fep = netdev_priv(ndev);
2201 
2202 	pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2203 	pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2204 	pause->rx_pause = pause->tx_pause;
2205 }
2206 
2207 static int fec_enet_set_pauseparam(struct net_device *ndev,
2208 				   struct ethtool_pauseparam *pause)
2209 {
2210 	struct fec_enet_private *fep = netdev_priv(ndev);
2211 
2212 	if (!ndev->phydev)
2213 		return -ENODEV;
2214 
2215 	if (pause->tx_pause != pause->rx_pause) {
2216 		netdev_info(ndev,
2217 			"hardware only support enable/disable both tx and rx");
2218 		return -EINVAL;
2219 	}
2220 
2221 	fep->pause_flag = 0;
2222 
2223 	/* tx pause must be same as rx pause */
2224 	fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2225 	fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2226 
2227 	phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause,
2228 			  pause->autoneg);
2229 
2230 	if (pause->autoneg) {
2231 		if (netif_running(ndev))
2232 			fec_stop(ndev);
2233 		phy_start_aneg(ndev->phydev);
2234 	}
2235 	if (netif_running(ndev)) {
2236 		napi_disable(&fep->napi);
2237 		netif_tx_lock_bh(ndev);
2238 		fec_restart(ndev);
2239 		netif_tx_wake_all_queues(ndev);
2240 		netif_tx_unlock_bh(ndev);
2241 		napi_enable(&fep->napi);
2242 	}
2243 
2244 	return 0;
2245 }
2246 
2247 static const struct fec_stat {
2248 	char name[ETH_GSTRING_LEN];
2249 	u16 offset;
2250 } fec_stats[] = {
2251 	/* RMON TX */
2252 	{ "tx_dropped", RMON_T_DROP },
2253 	{ "tx_packets", RMON_T_PACKETS },
2254 	{ "tx_broadcast", RMON_T_BC_PKT },
2255 	{ "tx_multicast", RMON_T_MC_PKT },
2256 	{ "tx_crc_errors", RMON_T_CRC_ALIGN },
2257 	{ "tx_undersize", RMON_T_UNDERSIZE },
2258 	{ "tx_oversize", RMON_T_OVERSIZE },
2259 	{ "tx_fragment", RMON_T_FRAG },
2260 	{ "tx_jabber", RMON_T_JAB },
2261 	{ "tx_collision", RMON_T_COL },
2262 	{ "tx_64byte", RMON_T_P64 },
2263 	{ "tx_65to127byte", RMON_T_P65TO127 },
2264 	{ "tx_128to255byte", RMON_T_P128TO255 },
2265 	{ "tx_256to511byte", RMON_T_P256TO511 },
2266 	{ "tx_512to1023byte", RMON_T_P512TO1023 },
2267 	{ "tx_1024to2047byte", RMON_T_P1024TO2047 },
2268 	{ "tx_GTE2048byte", RMON_T_P_GTE2048 },
2269 	{ "tx_octets", RMON_T_OCTETS },
2270 
2271 	/* IEEE TX */
2272 	{ "IEEE_tx_drop", IEEE_T_DROP },
2273 	{ "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2274 	{ "IEEE_tx_1col", IEEE_T_1COL },
2275 	{ "IEEE_tx_mcol", IEEE_T_MCOL },
2276 	{ "IEEE_tx_def", IEEE_T_DEF },
2277 	{ "IEEE_tx_lcol", IEEE_T_LCOL },
2278 	{ "IEEE_tx_excol", IEEE_T_EXCOL },
2279 	{ "IEEE_tx_macerr", IEEE_T_MACERR },
2280 	{ "IEEE_tx_cserr", IEEE_T_CSERR },
2281 	{ "IEEE_tx_sqe", IEEE_T_SQE },
2282 	{ "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2283 	{ "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2284 
2285 	/* RMON RX */
2286 	{ "rx_packets", RMON_R_PACKETS },
2287 	{ "rx_broadcast", RMON_R_BC_PKT },
2288 	{ "rx_multicast", RMON_R_MC_PKT },
2289 	{ "rx_crc_errors", RMON_R_CRC_ALIGN },
2290 	{ "rx_undersize", RMON_R_UNDERSIZE },
2291 	{ "rx_oversize", RMON_R_OVERSIZE },
2292 	{ "rx_fragment", RMON_R_FRAG },
2293 	{ "rx_jabber", RMON_R_JAB },
2294 	{ "rx_64byte", RMON_R_P64 },
2295 	{ "rx_65to127byte", RMON_R_P65TO127 },
2296 	{ "rx_128to255byte", RMON_R_P128TO255 },
2297 	{ "rx_256to511byte", RMON_R_P256TO511 },
2298 	{ "rx_512to1023byte", RMON_R_P512TO1023 },
2299 	{ "rx_1024to2047byte", RMON_R_P1024TO2047 },
2300 	{ "rx_GTE2048byte", RMON_R_P_GTE2048 },
2301 	{ "rx_octets", RMON_R_OCTETS },
2302 
2303 	/* IEEE RX */
2304 	{ "IEEE_rx_drop", IEEE_R_DROP },
2305 	{ "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2306 	{ "IEEE_rx_crc", IEEE_R_CRC },
2307 	{ "IEEE_rx_align", IEEE_R_ALIGN },
2308 	{ "IEEE_rx_macerr", IEEE_R_MACERR },
2309 	{ "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2310 	{ "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2311 };
2312 
2313 #define FEC_STATS_SIZE		(ARRAY_SIZE(fec_stats) * sizeof(u64))
2314 
2315 static void fec_enet_update_ethtool_stats(struct net_device *dev)
2316 {
2317 	struct fec_enet_private *fep = netdev_priv(dev);
2318 	int i;
2319 
2320 	for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2321 		fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2322 }
2323 
2324 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2325 				       struct ethtool_stats *stats, u64 *data)
2326 {
2327 	struct fec_enet_private *fep = netdev_priv(dev);
2328 
2329 	if (netif_running(dev))
2330 		fec_enet_update_ethtool_stats(dev);
2331 
2332 	memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2333 }
2334 
2335 static void fec_enet_get_strings(struct net_device *netdev,
2336 	u32 stringset, u8 *data)
2337 {
2338 	int i;
2339 	switch (stringset) {
2340 	case ETH_SS_STATS:
2341 		for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2342 			memcpy(data + i * ETH_GSTRING_LEN,
2343 				fec_stats[i].name, ETH_GSTRING_LEN);
2344 		break;
2345 	}
2346 }
2347 
2348 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2349 {
2350 	switch (sset) {
2351 	case ETH_SS_STATS:
2352 		return ARRAY_SIZE(fec_stats);
2353 	default:
2354 		return -EOPNOTSUPP;
2355 	}
2356 }
2357 
2358 static void fec_enet_clear_ethtool_stats(struct net_device *dev)
2359 {
2360 	struct fec_enet_private *fep = netdev_priv(dev);
2361 	int i;
2362 
2363 	/* Disable MIB statistics counters */
2364 	writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
2365 
2366 	for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2367 		writel(0, fep->hwp + fec_stats[i].offset);
2368 
2369 	/* Don't disable MIB statistics counters */
2370 	writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
2371 }
2372 
2373 #else	/* !defined(CONFIG_M5272) */
2374 #define FEC_STATS_SIZE	0
2375 static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2376 {
2377 }
2378 
2379 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
2380 {
2381 }
2382 #endif /* !defined(CONFIG_M5272) */
2383 
2384 /* ITR clock source is enet system clock (clk_ahb).
2385  * TCTT unit is cycle_ns * 64 cycle
2386  * So, the ICTT value = X us / (cycle_ns * 64)
2387  */
2388 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2389 {
2390 	struct fec_enet_private *fep = netdev_priv(ndev);
2391 
2392 	return us * (fep->itr_clk_rate / 64000) / 1000;
2393 }
2394 
2395 /* Set threshold for interrupt coalescing */
2396 static void fec_enet_itr_coal_set(struct net_device *ndev)
2397 {
2398 	struct fec_enet_private *fep = netdev_priv(ndev);
2399 	int rx_itr, tx_itr;
2400 
2401 	/* Must be greater than zero to avoid unpredictable behavior */
2402 	if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2403 	    !fep->tx_time_itr || !fep->tx_pkts_itr)
2404 		return;
2405 
2406 	/* Select enet system clock as Interrupt Coalescing
2407 	 * timer Clock Source
2408 	 */
2409 	rx_itr = FEC_ITR_CLK_SEL;
2410 	tx_itr = FEC_ITR_CLK_SEL;
2411 
2412 	/* set ICFT and ICTT */
2413 	rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2414 	rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2415 	tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2416 	tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2417 
2418 	rx_itr |= FEC_ITR_EN;
2419 	tx_itr |= FEC_ITR_EN;
2420 
2421 	writel(tx_itr, fep->hwp + FEC_TXIC0);
2422 	writel(rx_itr, fep->hwp + FEC_RXIC0);
2423 	if (fep->quirks & FEC_QUIRK_HAS_AVB) {
2424 		writel(tx_itr, fep->hwp + FEC_TXIC1);
2425 		writel(rx_itr, fep->hwp + FEC_RXIC1);
2426 		writel(tx_itr, fep->hwp + FEC_TXIC2);
2427 		writel(rx_itr, fep->hwp + FEC_RXIC2);
2428 	}
2429 }
2430 
2431 static int
2432 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2433 {
2434 	struct fec_enet_private *fep = netdev_priv(ndev);
2435 
2436 	if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2437 		return -EOPNOTSUPP;
2438 
2439 	ec->rx_coalesce_usecs = fep->rx_time_itr;
2440 	ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2441 
2442 	ec->tx_coalesce_usecs = fep->tx_time_itr;
2443 	ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2444 
2445 	return 0;
2446 }
2447 
2448 static int
2449 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2450 {
2451 	struct fec_enet_private *fep = netdev_priv(ndev);
2452 	unsigned int cycle;
2453 
2454 	if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2455 		return -EOPNOTSUPP;
2456 
2457 	if (ec->rx_max_coalesced_frames > 255) {
2458 		pr_err("Rx coalesced frames exceed hardware limitation\n");
2459 		return -EINVAL;
2460 	}
2461 
2462 	if (ec->tx_max_coalesced_frames > 255) {
2463 		pr_err("Tx coalesced frame exceed hardware limitation\n");
2464 		return -EINVAL;
2465 	}
2466 
2467 	cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2468 	if (cycle > 0xFFFF) {
2469 		pr_err("Rx coalesced usec exceed hardware limitation\n");
2470 		return -EINVAL;
2471 	}
2472 
2473 	cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2474 	if (cycle > 0xFFFF) {
2475 		pr_err("Rx coalesced usec exceed hardware limitation\n");
2476 		return -EINVAL;
2477 	}
2478 
2479 	fep->rx_time_itr = ec->rx_coalesce_usecs;
2480 	fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2481 
2482 	fep->tx_time_itr = ec->tx_coalesce_usecs;
2483 	fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2484 
2485 	fec_enet_itr_coal_set(ndev);
2486 
2487 	return 0;
2488 }
2489 
2490 static void fec_enet_itr_coal_init(struct net_device *ndev)
2491 {
2492 	struct ethtool_coalesce ec;
2493 
2494 	ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2495 	ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2496 
2497 	ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2498 	ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2499 
2500 	fec_enet_set_coalesce(ndev, &ec);
2501 }
2502 
2503 static int fec_enet_get_tunable(struct net_device *netdev,
2504 				const struct ethtool_tunable *tuna,
2505 				void *data)
2506 {
2507 	struct fec_enet_private *fep = netdev_priv(netdev);
2508 	int ret = 0;
2509 
2510 	switch (tuna->id) {
2511 	case ETHTOOL_RX_COPYBREAK:
2512 		*(u32 *)data = fep->rx_copybreak;
2513 		break;
2514 	default:
2515 		ret = -EINVAL;
2516 		break;
2517 	}
2518 
2519 	return ret;
2520 }
2521 
2522 static int fec_enet_set_tunable(struct net_device *netdev,
2523 				const struct ethtool_tunable *tuna,
2524 				const void *data)
2525 {
2526 	struct fec_enet_private *fep = netdev_priv(netdev);
2527 	int ret = 0;
2528 
2529 	switch (tuna->id) {
2530 	case ETHTOOL_RX_COPYBREAK:
2531 		fep->rx_copybreak = *(u32 *)data;
2532 		break;
2533 	default:
2534 		ret = -EINVAL;
2535 		break;
2536 	}
2537 
2538 	return ret;
2539 }
2540 
2541 static void
2542 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2543 {
2544 	struct fec_enet_private *fep = netdev_priv(ndev);
2545 
2546 	if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2547 		wol->supported = WAKE_MAGIC;
2548 		wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2549 	} else {
2550 		wol->supported = wol->wolopts = 0;
2551 	}
2552 }
2553 
2554 static int
2555 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2556 {
2557 	struct fec_enet_private *fep = netdev_priv(ndev);
2558 
2559 	if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2560 		return -EINVAL;
2561 
2562 	if (wol->wolopts & ~WAKE_MAGIC)
2563 		return -EINVAL;
2564 
2565 	device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2566 	if (device_may_wakeup(&ndev->dev)) {
2567 		fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2568 		if (fep->irq[0] > 0)
2569 			enable_irq_wake(fep->irq[0]);
2570 	} else {
2571 		fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2572 		if (fep->irq[0] > 0)
2573 			disable_irq_wake(fep->irq[0]);
2574 	}
2575 
2576 	return 0;
2577 }
2578 
2579 static const struct ethtool_ops fec_enet_ethtool_ops = {
2580 	.get_drvinfo		= fec_enet_get_drvinfo,
2581 	.get_regs_len		= fec_enet_get_regs_len,
2582 	.get_regs		= fec_enet_get_regs,
2583 	.nway_reset		= phy_ethtool_nway_reset,
2584 	.get_link		= ethtool_op_get_link,
2585 	.get_coalesce		= fec_enet_get_coalesce,
2586 	.set_coalesce		= fec_enet_set_coalesce,
2587 #ifndef CONFIG_M5272
2588 	.get_pauseparam		= fec_enet_get_pauseparam,
2589 	.set_pauseparam		= fec_enet_set_pauseparam,
2590 	.get_strings		= fec_enet_get_strings,
2591 	.get_ethtool_stats	= fec_enet_get_ethtool_stats,
2592 	.get_sset_count		= fec_enet_get_sset_count,
2593 #endif
2594 	.get_ts_info		= fec_enet_get_ts_info,
2595 	.get_tunable		= fec_enet_get_tunable,
2596 	.set_tunable		= fec_enet_set_tunable,
2597 	.get_wol		= fec_enet_get_wol,
2598 	.set_wol		= fec_enet_set_wol,
2599 	.get_link_ksettings	= phy_ethtool_get_link_ksettings,
2600 	.set_link_ksettings	= phy_ethtool_set_link_ksettings,
2601 };
2602 
2603 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2604 {
2605 	struct fec_enet_private *fep = netdev_priv(ndev);
2606 	struct phy_device *phydev = ndev->phydev;
2607 
2608 	if (!netif_running(ndev))
2609 		return -EINVAL;
2610 
2611 	if (!phydev)
2612 		return -ENODEV;
2613 
2614 	if (fep->bufdesc_ex) {
2615 		if (cmd == SIOCSHWTSTAMP)
2616 			return fec_ptp_set(ndev, rq);
2617 		if (cmd == SIOCGHWTSTAMP)
2618 			return fec_ptp_get(ndev, rq);
2619 	}
2620 
2621 	return phy_mii_ioctl(phydev, rq, cmd);
2622 }
2623 
2624 static void fec_enet_free_buffers(struct net_device *ndev)
2625 {
2626 	struct fec_enet_private *fep = netdev_priv(ndev);
2627 	unsigned int i;
2628 	struct sk_buff *skb;
2629 	struct bufdesc	*bdp;
2630 	struct fec_enet_priv_tx_q *txq;
2631 	struct fec_enet_priv_rx_q *rxq;
2632 	unsigned int q;
2633 
2634 	for (q = 0; q < fep->num_rx_queues; q++) {
2635 		rxq = fep->rx_queue[q];
2636 		bdp = rxq->bd.base;
2637 		for (i = 0; i < rxq->bd.ring_size; i++) {
2638 			skb = rxq->rx_skbuff[i];
2639 			rxq->rx_skbuff[i] = NULL;
2640 			if (skb) {
2641 				dma_unmap_single(&fep->pdev->dev,
2642 						 fec32_to_cpu(bdp->cbd_bufaddr),
2643 						 FEC_ENET_RX_FRSIZE - fep->rx_align,
2644 						 DMA_FROM_DEVICE);
2645 				dev_kfree_skb(skb);
2646 			}
2647 			bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2648 		}
2649 	}
2650 
2651 	for (q = 0; q < fep->num_tx_queues; q++) {
2652 		txq = fep->tx_queue[q];
2653 		bdp = txq->bd.base;
2654 		for (i = 0; i < txq->bd.ring_size; i++) {
2655 			kfree(txq->tx_bounce[i]);
2656 			txq->tx_bounce[i] = NULL;
2657 			skb = txq->tx_skbuff[i];
2658 			txq->tx_skbuff[i] = NULL;
2659 			dev_kfree_skb(skb);
2660 		}
2661 	}
2662 }
2663 
2664 static void fec_enet_free_queue(struct net_device *ndev)
2665 {
2666 	struct fec_enet_private *fep = netdev_priv(ndev);
2667 	int i;
2668 	struct fec_enet_priv_tx_q *txq;
2669 
2670 	for (i = 0; i < fep->num_tx_queues; i++)
2671 		if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2672 			txq = fep->tx_queue[i];
2673 			dma_free_coherent(&fep->pdev->dev,
2674 					  txq->bd.ring_size * TSO_HEADER_SIZE,
2675 					  txq->tso_hdrs,
2676 					  txq->tso_hdrs_dma);
2677 		}
2678 
2679 	for (i = 0; i < fep->num_rx_queues; i++)
2680 		kfree(fep->rx_queue[i]);
2681 	for (i = 0; i < fep->num_tx_queues; i++)
2682 		kfree(fep->tx_queue[i]);
2683 }
2684 
2685 static int fec_enet_alloc_queue(struct net_device *ndev)
2686 {
2687 	struct fec_enet_private *fep = netdev_priv(ndev);
2688 	int i;
2689 	int ret = 0;
2690 	struct fec_enet_priv_tx_q *txq;
2691 
2692 	for (i = 0; i < fep->num_tx_queues; i++) {
2693 		txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2694 		if (!txq) {
2695 			ret = -ENOMEM;
2696 			goto alloc_failed;
2697 		}
2698 
2699 		fep->tx_queue[i] = txq;
2700 		txq->bd.ring_size = TX_RING_SIZE;
2701 		fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
2702 
2703 		txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2704 		txq->tx_wake_threshold =
2705 			(txq->bd.ring_size - txq->tx_stop_threshold) / 2;
2706 
2707 		txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev,
2708 					txq->bd.ring_size * TSO_HEADER_SIZE,
2709 					&txq->tso_hdrs_dma,
2710 					GFP_KERNEL);
2711 		if (!txq->tso_hdrs) {
2712 			ret = -ENOMEM;
2713 			goto alloc_failed;
2714 		}
2715 	}
2716 
2717 	for (i = 0; i < fep->num_rx_queues; i++) {
2718 		fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2719 					   GFP_KERNEL);
2720 		if (!fep->rx_queue[i]) {
2721 			ret = -ENOMEM;
2722 			goto alloc_failed;
2723 		}
2724 
2725 		fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2726 		fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
2727 	}
2728 	return ret;
2729 
2730 alloc_failed:
2731 	fec_enet_free_queue(ndev);
2732 	return ret;
2733 }
2734 
2735 static int
2736 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2737 {
2738 	struct fec_enet_private *fep = netdev_priv(ndev);
2739 	unsigned int i;
2740 	struct sk_buff *skb;
2741 	struct bufdesc	*bdp;
2742 	struct fec_enet_priv_rx_q *rxq;
2743 
2744 	rxq = fep->rx_queue[queue];
2745 	bdp = rxq->bd.base;
2746 	for (i = 0; i < rxq->bd.ring_size; i++) {
2747 		skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2748 		if (!skb)
2749 			goto err_alloc;
2750 
2751 		if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2752 			dev_kfree_skb(skb);
2753 			goto err_alloc;
2754 		}
2755 
2756 		rxq->rx_skbuff[i] = skb;
2757 		bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
2758 
2759 		if (fep->bufdesc_ex) {
2760 			struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2761 			ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
2762 		}
2763 
2764 		bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2765 	}
2766 
2767 	/* Set the last buffer to wrap. */
2768 	bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
2769 	bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2770 	return 0;
2771 
2772  err_alloc:
2773 	fec_enet_free_buffers(ndev);
2774 	return -ENOMEM;
2775 }
2776 
2777 static int
2778 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2779 {
2780 	struct fec_enet_private *fep = netdev_priv(ndev);
2781 	unsigned int i;
2782 	struct bufdesc  *bdp;
2783 	struct fec_enet_priv_tx_q *txq;
2784 
2785 	txq = fep->tx_queue[queue];
2786 	bdp = txq->bd.base;
2787 	for (i = 0; i < txq->bd.ring_size; i++) {
2788 		txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2789 		if (!txq->tx_bounce[i])
2790 			goto err_alloc;
2791 
2792 		bdp->cbd_sc = cpu_to_fec16(0);
2793 		bdp->cbd_bufaddr = cpu_to_fec32(0);
2794 
2795 		if (fep->bufdesc_ex) {
2796 			struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2797 			ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
2798 		}
2799 
2800 		bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
2801 	}
2802 
2803 	/* Set the last buffer to wrap. */
2804 	bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
2805 	bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2806 
2807 	return 0;
2808 
2809  err_alloc:
2810 	fec_enet_free_buffers(ndev);
2811 	return -ENOMEM;
2812 }
2813 
2814 static int fec_enet_alloc_buffers(struct net_device *ndev)
2815 {
2816 	struct fec_enet_private *fep = netdev_priv(ndev);
2817 	unsigned int i;
2818 
2819 	for (i = 0; i < fep->num_rx_queues; i++)
2820 		if (fec_enet_alloc_rxq_buffers(ndev, i))
2821 			return -ENOMEM;
2822 
2823 	for (i = 0; i < fep->num_tx_queues; i++)
2824 		if (fec_enet_alloc_txq_buffers(ndev, i))
2825 			return -ENOMEM;
2826 	return 0;
2827 }
2828 
2829 static int
2830 fec_enet_open(struct net_device *ndev)
2831 {
2832 	struct fec_enet_private *fep = netdev_priv(ndev);
2833 	int ret;
2834 	bool reset_again;
2835 
2836 	ret = pm_runtime_get_sync(&fep->pdev->dev);
2837 	if (ret < 0)
2838 		return ret;
2839 
2840 	pinctrl_pm_select_default_state(&fep->pdev->dev);
2841 	ret = fec_enet_clk_enable(ndev, true);
2842 	if (ret)
2843 		goto clk_enable;
2844 
2845 	/* During the first fec_enet_open call the PHY isn't probed at this
2846 	 * point. Therefore the phy_reset_after_clk_enable() call within
2847 	 * fec_enet_clk_enable() fails. As we need this reset in order to be
2848 	 * sure the PHY is working correctly we check if we need to reset again
2849 	 * later when the PHY is probed
2850 	 */
2851 	if (ndev->phydev && ndev->phydev->drv)
2852 		reset_again = false;
2853 	else
2854 		reset_again = true;
2855 
2856 	/* I should reset the ring buffers here, but I don't yet know
2857 	 * a simple way to do that.
2858 	 */
2859 
2860 	ret = fec_enet_alloc_buffers(ndev);
2861 	if (ret)
2862 		goto err_enet_alloc;
2863 
2864 	/* Init MAC prior to mii bus probe */
2865 	fec_restart(ndev);
2866 
2867 	/* Probe and connect to PHY when open the interface */
2868 	ret = fec_enet_mii_probe(ndev);
2869 	if (ret)
2870 		goto err_enet_mii_probe;
2871 
2872 	/* Call phy_reset_after_clk_enable() again if it failed during
2873 	 * phy_reset_after_clk_enable() before because the PHY wasn't probed.
2874 	 */
2875 	if (reset_again)
2876 		phy_reset_after_clk_enable(ndev->phydev);
2877 
2878 	if (fep->quirks & FEC_QUIRK_ERR006687)
2879 		imx6q_cpuidle_fec_irqs_used();
2880 
2881 	napi_enable(&fep->napi);
2882 	phy_start(ndev->phydev);
2883 	netif_tx_start_all_queues(ndev);
2884 
2885 	device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2886 				 FEC_WOL_FLAG_ENABLE);
2887 
2888 	return 0;
2889 
2890 err_enet_mii_probe:
2891 	fec_enet_free_buffers(ndev);
2892 err_enet_alloc:
2893 	fec_enet_clk_enable(ndev, false);
2894 clk_enable:
2895 	pm_runtime_mark_last_busy(&fep->pdev->dev);
2896 	pm_runtime_put_autosuspend(&fep->pdev->dev);
2897 	pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2898 	return ret;
2899 }
2900 
2901 static int
2902 fec_enet_close(struct net_device *ndev)
2903 {
2904 	struct fec_enet_private *fep = netdev_priv(ndev);
2905 
2906 	phy_stop(ndev->phydev);
2907 
2908 	if (netif_device_present(ndev)) {
2909 		napi_disable(&fep->napi);
2910 		netif_tx_disable(ndev);
2911 		fec_stop(ndev);
2912 	}
2913 
2914 	phy_disconnect(ndev->phydev);
2915 
2916 	if (fep->quirks & FEC_QUIRK_ERR006687)
2917 		imx6q_cpuidle_fec_irqs_unused();
2918 
2919 	fec_enet_update_ethtool_stats(ndev);
2920 
2921 	fec_enet_clk_enable(ndev, false);
2922 	pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2923 	pm_runtime_mark_last_busy(&fep->pdev->dev);
2924 	pm_runtime_put_autosuspend(&fep->pdev->dev);
2925 
2926 	fec_enet_free_buffers(ndev);
2927 
2928 	return 0;
2929 }
2930 
2931 /* Set or clear the multicast filter for this adaptor.
2932  * Skeleton taken from sunlance driver.
2933  * The CPM Ethernet implementation allows Multicast as well as individual
2934  * MAC address filtering.  Some of the drivers check to make sure it is
2935  * a group multicast address, and discard those that are not.  I guess I
2936  * will do the same for now, but just remove the test if you want
2937  * individual filtering as well (do the upper net layers want or support
2938  * this kind of feature?).
2939  */
2940 
2941 #define FEC_HASH_BITS	6		/* #bits in hash */
2942 
2943 static void set_multicast_list(struct net_device *ndev)
2944 {
2945 	struct fec_enet_private *fep = netdev_priv(ndev);
2946 	struct netdev_hw_addr *ha;
2947 	unsigned int crc, tmp;
2948 	unsigned char hash;
2949 	unsigned int hash_high = 0, hash_low = 0;
2950 
2951 	if (ndev->flags & IFF_PROMISC) {
2952 		tmp = readl(fep->hwp + FEC_R_CNTRL);
2953 		tmp |= 0x8;
2954 		writel(tmp, fep->hwp + FEC_R_CNTRL);
2955 		return;
2956 	}
2957 
2958 	tmp = readl(fep->hwp + FEC_R_CNTRL);
2959 	tmp &= ~0x8;
2960 	writel(tmp, fep->hwp + FEC_R_CNTRL);
2961 
2962 	if (ndev->flags & IFF_ALLMULTI) {
2963 		/* Catch all multicast addresses, so set the
2964 		 * filter to all 1's
2965 		 */
2966 		writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2967 		writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2968 
2969 		return;
2970 	}
2971 
2972 	/* Add the addresses in hash register */
2973 	netdev_for_each_mc_addr(ha, ndev) {
2974 		/* calculate crc32 value of mac address */
2975 		crc = ether_crc_le(ndev->addr_len, ha->addr);
2976 
2977 		/* only upper 6 bits (FEC_HASH_BITS) are used
2978 		 * which point to specific bit in the hash registers
2979 		 */
2980 		hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
2981 
2982 		if (hash > 31)
2983 			hash_high |= 1 << (hash - 32);
2984 		else
2985 			hash_low |= 1 << hash;
2986 	}
2987 
2988 	writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2989 	writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2990 }
2991 
2992 /* Set a MAC change in hardware. */
2993 static int
2994 fec_set_mac_address(struct net_device *ndev, void *p)
2995 {
2996 	struct fec_enet_private *fep = netdev_priv(ndev);
2997 	struct sockaddr *addr = p;
2998 
2999 	if (addr) {
3000 		if (!is_valid_ether_addr(addr->sa_data))
3001 			return -EADDRNOTAVAIL;
3002 		memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3003 	}
3004 
3005 	/* Add netif status check here to avoid system hang in below case:
3006 	 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3007 	 * After ethx down, fec all clocks are gated off and then register
3008 	 * access causes system hang.
3009 	 */
3010 	if (!netif_running(ndev))
3011 		return 0;
3012 
3013 	writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3014 		(ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3015 		fep->hwp + FEC_ADDR_LOW);
3016 	writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3017 		fep->hwp + FEC_ADDR_HIGH);
3018 	return 0;
3019 }
3020 
3021 #ifdef CONFIG_NET_POLL_CONTROLLER
3022 /**
3023  * fec_poll_controller - FEC Poll controller function
3024  * @dev: The FEC network adapter
3025  *
3026  * Polled functionality used by netconsole and others in non interrupt mode
3027  *
3028  */
3029 static void fec_poll_controller(struct net_device *dev)
3030 {
3031 	int i;
3032 	struct fec_enet_private *fep = netdev_priv(dev);
3033 
3034 	for (i = 0; i < FEC_IRQ_NUM; i++) {
3035 		if (fep->irq[i] > 0) {
3036 			disable_irq(fep->irq[i]);
3037 			fec_enet_interrupt(fep->irq[i], dev);
3038 			enable_irq(fep->irq[i]);
3039 		}
3040 	}
3041 }
3042 #endif
3043 
3044 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3045 	netdev_features_t features)
3046 {
3047 	struct fec_enet_private *fep = netdev_priv(netdev);
3048 	netdev_features_t changed = features ^ netdev->features;
3049 
3050 	netdev->features = features;
3051 
3052 	/* Receive checksum has been changed */
3053 	if (changed & NETIF_F_RXCSUM) {
3054 		if (features & NETIF_F_RXCSUM)
3055 			fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3056 		else
3057 			fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3058 	}
3059 }
3060 
3061 static int fec_set_features(struct net_device *netdev,
3062 	netdev_features_t features)
3063 {
3064 	struct fec_enet_private *fep = netdev_priv(netdev);
3065 	netdev_features_t changed = features ^ netdev->features;
3066 
3067 	if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3068 		napi_disable(&fep->napi);
3069 		netif_tx_lock_bh(netdev);
3070 		fec_stop(netdev);
3071 		fec_enet_set_netdev_features(netdev, features);
3072 		fec_restart(netdev);
3073 		netif_tx_wake_all_queues(netdev);
3074 		netif_tx_unlock_bh(netdev);
3075 		napi_enable(&fep->napi);
3076 	} else {
3077 		fec_enet_set_netdev_features(netdev, features);
3078 	}
3079 
3080 	return 0;
3081 }
3082 
3083 static const struct net_device_ops fec_netdev_ops = {
3084 	.ndo_open		= fec_enet_open,
3085 	.ndo_stop		= fec_enet_close,
3086 	.ndo_start_xmit		= fec_enet_start_xmit,
3087 	.ndo_set_rx_mode	= set_multicast_list,
3088 	.ndo_validate_addr	= eth_validate_addr,
3089 	.ndo_tx_timeout		= fec_timeout,
3090 	.ndo_set_mac_address	= fec_set_mac_address,
3091 	.ndo_do_ioctl		= fec_enet_ioctl,
3092 #ifdef CONFIG_NET_POLL_CONTROLLER
3093 	.ndo_poll_controller	= fec_poll_controller,
3094 #endif
3095 	.ndo_set_features	= fec_set_features,
3096 };
3097 
3098 static const unsigned short offset_des_active_rxq[] = {
3099 	FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3100 };
3101 
3102 static const unsigned short offset_des_active_txq[] = {
3103 	FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3104 };
3105 
3106  /*
3107   * XXX:  We need to clean up on failure exits here.
3108   *
3109   */
3110 static int fec_enet_init(struct net_device *ndev)
3111 {
3112 	struct fec_enet_private *fep = netdev_priv(ndev);
3113 	struct bufdesc *cbd_base;
3114 	dma_addr_t bd_dma;
3115 	int bd_size;
3116 	unsigned int i;
3117 	unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3118 			sizeof(struct bufdesc);
3119 	unsigned dsize_log2 = __fls(dsize);
3120 	int ret;
3121 
3122 	WARN_ON(dsize != (1 << dsize_log2));
3123 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
3124 	fep->rx_align = 0xf;
3125 	fep->tx_align = 0xf;
3126 #else
3127 	fep->rx_align = 0x3;
3128 	fep->tx_align = 0x3;
3129 #endif
3130 
3131 	/* Check mask of the streaming and coherent API */
3132 	ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32));
3133 	if (ret < 0) {
3134 		dev_warn(&fep->pdev->dev, "No suitable DMA available\n");
3135 		return ret;
3136 	}
3137 
3138 	fec_enet_alloc_queue(ndev);
3139 
3140 	bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
3141 
3142 	/* Allocate memory for buffer descriptors. */
3143 	cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3144 				       GFP_KERNEL);
3145 	if (!cbd_base) {
3146 		return -ENOMEM;
3147 	}
3148 
3149 	memset(cbd_base, 0, bd_size);
3150 
3151 	/* Get the Ethernet address */
3152 	fec_get_mac(ndev);
3153 	/* make sure MAC we just acquired is programmed into the hw */
3154 	fec_set_mac_address(ndev, NULL);
3155 
3156 	/* Set receive and transmit descriptor base. */
3157 	for (i = 0; i < fep->num_rx_queues; i++) {
3158 		struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3159 		unsigned size = dsize * rxq->bd.ring_size;
3160 
3161 		rxq->bd.qid = i;
3162 		rxq->bd.base = cbd_base;
3163 		rxq->bd.cur = cbd_base;
3164 		rxq->bd.dma = bd_dma;
3165 		rxq->bd.dsize = dsize;
3166 		rxq->bd.dsize_log2 = dsize_log2;
3167 		rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
3168 		bd_dma += size;
3169 		cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3170 		rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3171 	}
3172 
3173 	for (i = 0; i < fep->num_tx_queues; i++) {
3174 		struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3175 		unsigned size = dsize * txq->bd.ring_size;
3176 
3177 		txq->bd.qid = i;
3178 		txq->bd.base = cbd_base;
3179 		txq->bd.cur = cbd_base;
3180 		txq->bd.dma = bd_dma;
3181 		txq->bd.dsize = dsize;
3182 		txq->bd.dsize_log2 = dsize_log2;
3183 		txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
3184 		bd_dma += size;
3185 		cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3186 		txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3187 	}
3188 
3189 
3190 	/* The FEC Ethernet specific entries in the device structure */
3191 	ndev->watchdog_timeo = TX_TIMEOUT;
3192 	ndev->netdev_ops = &fec_netdev_ops;
3193 	ndev->ethtool_ops = &fec_enet_ethtool_ops;
3194 
3195 	writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3196 	netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3197 
3198 	if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3199 		/* enable hw VLAN support */
3200 		ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3201 
3202 	if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3203 		ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3204 
3205 		/* enable hw accelerator */
3206 		ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3207 				| NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3208 		fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3209 	}
3210 
3211 	if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3212 		fep->tx_align = 0;
3213 		fep->rx_align = 0x3f;
3214 	}
3215 
3216 	ndev->hw_features = ndev->features;
3217 
3218 	fec_restart(ndev);
3219 
3220 	if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
3221 		fec_enet_clear_ethtool_stats(ndev);
3222 	else
3223 		fec_enet_update_ethtool_stats(ndev);
3224 
3225 	return 0;
3226 }
3227 
3228 #ifdef CONFIG_OF
3229 static int fec_reset_phy(struct platform_device *pdev)
3230 {
3231 	int err, phy_reset;
3232 	bool active_high = false;
3233 	int msec = 1, phy_post_delay = 0;
3234 	struct device_node *np = pdev->dev.of_node;
3235 
3236 	if (!np)
3237 		return 0;
3238 
3239 	err = of_property_read_u32(np, "phy-reset-duration", &msec);
3240 	/* A sane reset duration should not be longer than 1s */
3241 	if (!err && msec > 1000)
3242 		msec = 1;
3243 
3244 	phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3245 	if (phy_reset == -EPROBE_DEFER)
3246 		return phy_reset;
3247 	else if (!gpio_is_valid(phy_reset))
3248 		return 0;
3249 
3250 	err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
3251 	/* valid reset duration should be less than 1s */
3252 	if (!err && phy_post_delay > 1000)
3253 		return -EINVAL;
3254 
3255 	active_high = of_property_read_bool(np, "phy-reset-active-high");
3256 
3257 	err = devm_gpio_request_one(&pdev->dev, phy_reset,
3258 			active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
3259 			"phy-reset");
3260 	if (err) {
3261 		dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3262 		return err;
3263 	}
3264 
3265 	if (msec > 20)
3266 		msleep(msec);
3267 	else
3268 		usleep_range(msec * 1000, msec * 1000 + 1000);
3269 
3270 	gpio_set_value_cansleep(phy_reset, !active_high);
3271 
3272 	if (!phy_post_delay)
3273 		return 0;
3274 
3275 	if (phy_post_delay > 20)
3276 		msleep(phy_post_delay);
3277 	else
3278 		usleep_range(phy_post_delay * 1000,
3279 			     phy_post_delay * 1000 + 1000);
3280 
3281 	return 0;
3282 }
3283 #else /* CONFIG_OF */
3284 static int fec_reset_phy(struct platform_device *pdev)
3285 {
3286 	/*
3287 	 * In case of platform probe, the reset has been done
3288 	 * by machine code.
3289 	 */
3290 	return 0;
3291 }
3292 #endif /* CONFIG_OF */
3293 
3294 static void
3295 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3296 {
3297 	struct device_node *np = pdev->dev.of_node;
3298 
3299 	*num_tx = *num_rx = 1;
3300 
3301 	if (!np || !of_device_is_available(np))
3302 		return;
3303 
3304 	/* parse the num of tx and rx queues */
3305 	of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3306 
3307 	of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3308 
3309 	if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3310 		dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3311 			 *num_tx);
3312 		*num_tx = 1;
3313 		return;
3314 	}
3315 
3316 	if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3317 		dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3318 			 *num_rx);
3319 		*num_rx = 1;
3320 		return;
3321 	}
3322 
3323 }
3324 
3325 static int fec_enet_get_irq_cnt(struct platform_device *pdev)
3326 {
3327 	int irq_cnt = platform_irq_count(pdev);
3328 
3329 	if (irq_cnt > FEC_IRQ_NUM)
3330 		irq_cnt = FEC_IRQ_NUM;	/* last for pps */
3331 	else if (irq_cnt == 2)
3332 		irq_cnt = 1;	/* last for pps */
3333 	else if (irq_cnt <= 0)
3334 		irq_cnt = 1;	/* At least 1 irq is needed */
3335 	return irq_cnt;
3336 }
3337 
3338 static int
3339 fec_probe(struct platform_device *pdev)
3340 {
3341 	struct fec_enet_private *fep;
3342 	struct fec_platform_data *pdata;
3343 	struct net_device *ndev;
3344 	int i, irq, ret = 0;
3345 	struct resource *r;
3346 	const struct of_device_id *of_id;
3347 	static int dev_id;
3348 	struct device_node *np = pdev->dev.of_node, *phy_node;
3349 	int num_tx_qs;
3350 	int num_rx_qs;
3351 	char irq_name[8];
3352 	int irq_cnt;
3353 
3354 	fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3355 
3356 	/* Init network device */
3357 	ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
3358 				  FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
3359 	if (!ndev)
3360 		return -ENOMEM;
3361 
3362 	SET_NETDEV_DEV(ndev, &pdev->dev);
3363 
3364 	/* setup board info structure */
3365 	fep = netdev_priv(ndev);
3366 
3367 	of_id = of_match_device(fec_dt_ids, &pdev->dev);
3368 	if (of_id)
3369 		pdev->id_entry = of_id->data;
3370 	fep->quirks = pdev->id_entry->driver_data;
3371 
3372 	fep->netdev = ndev;
3373 	fep->num_rx_queues = num_rx_qs;
3374 	fep->num_tx_queues = num_tx_qs;
3375 
3376 #if !defined(CONFIG_M5272)
3377 	/* default enable pause frame auto negotiation */
3378 	if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3379 		fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3380 #endif
3381 
3382 	/* Select default pin state */
3383 	pinctrl_pm_select_default_state(&pdev->dev);
3384 
3385 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3386 	fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3387 	if (IS_ERR(fep->hwp)) {
3388 		ret = PTR_ERR(fep->hwp);
3389 		goto failed_ioremap;
3390 	}
3391 
3392 	fep->pdev = pdev;
3393 	fep->dev_id = dev_id++;
3394 
3395 	platform_set_drvdata(pdev, ndev);
3396 
3397 	if ((of_machine_is_compatible("fsl,imx6q") ||
3398 	     of_machine_is_compatible("fsl,imx6dl")) &&
3399 	    !of_property_read_bool(np, "fsl,err006687-workaround-present"))
3400 		fep->quirks |= FEC_QUIRK_ERR006687;
3401 
3402 	if (of_get_property(np, "fsl,magic-packet", NULL))
3403 		fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3404 
3405 	phy_node = of_parse_phandle(np, "phy-handle", 0);
3406 	if (!phy_node && of_phy_is_fixed_link(np)) {
3407 		ret = of_phy_register_fixed_link(np);
3408 		if (ret < 0) {
3409 			dev_err(&pdev->dev,
3410 				"broken fixed-link specification\n");
3411 			goto failed_phy;
3412 		}
3413 		phy_node = of_node_get(np);
3414 	}
3415 	fep->phy_node = phy_node;
3416 
3417 	ret = of_get_phy_mode(pdev->dev.of_node);
3418 	if (ret < 0) {
3419 		pdata = dev_get_platdata(&pdev->dev);
3420 		if (pdata)
3421 			fep->phy_interface = pdata->phy;
3422 		else
3423 			fep->phy_interface = PHY_INTERFACE_MODE_MII;
3424 	} else {
3425 		fep->phy_interface = ret;
3426 	}
3427 
3428 	fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3429 	if (IS_ERR(fep->clk_ipg)) {
3430 		ret = PTR_ERR(fep->clk_ipg);
3431 		goto failed_clk;
3432 	}
3433 
3434 	fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3435 	if (IS_ERR(fep->clk_ahb)) {
3436 		ret = PTR_ERR(fep->clk_ahb);
3437 		goto failed_clk;
3438 	}
3439 
3440 	fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3441 
3442 	/* enet_out is optional, depends on board */
3443 	fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3444 	if (IS_ERR(fep->clk_enet_out))
3445 		fep->clk_enet_out = NULL;
3446 
3447 	fep->ptp_clk_on = false;
3448 	mutex_init(&fep->ptp_clk_mutex);
3449 
3450 	/* clk_ref is optional, depends on board */
3451 	fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3452 	if (IS_ERR(fep->clk_ref))
3453 		fep->clk_ref = NULL;
3454 
3455 	fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3456 	fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3457 	if (IS_ERR(fep->clk_ptp)) {
3458 		fep->clk_ptp = NULL;
3459 		fep->bufdesc_ex = false;
3460 	}
3461 
3462 	ret = fec_enet_clk_enable(ndev, true);
3463 	if (ret)
3464 		goto failed_clk;
3465 
3466 	ret = clk_prepare_enable(fep->clk_ipg);
3467 	if (ret)
3468 		goto failed_clk_ipg;
3469 
3470 	fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3471 	if (!IS_ERR(fep->reg_phy)) {
3472 		ret = regulator_enable(fep->reg_phy);
3473 		if (ret) {
3474 			dev_err(&pdev->dev,
3475 				"Failed to enable phy regulator: %d\n", ret);
3476 			clk_disable_unprepare(fep->clk_ipg);
3477 			goto failed_regulator;
3478 		}
3479 	} else {
3480 		if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
3481 			ret = -EPROBE_DEFER;
3482 			goto failed_regulator;
3483 		}
3484 		fep->reg_phy = NULL;
3485 	}
3486 
3487 	pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3488 	pm_runtime_use_autosuspend(&pdev->dev);
3489 	pm_runtime_get_noresume(&pdev->dev);
3490 	pm_runtime_set_active(&pdev->dev);
3491 	pm_runtime_enable(&pdev->dev);
3492 
3493 	ret = fec_reset_phy(pdev);
3494 	if (ret)
3495 		goto failed_reset;
3496 
3497 	irq_cnt = fec_enet_get_irq_cnt(pdev);
3498 	if (fep->bufdesc_ex)
3499 		fec_ptp_init(pdev, irq_cnt);
3500 
3501 	ret = fec_enet_init(ndev);
3502 	if (ret)
3503 		goto failed_init;
3504 
3505 	for (i = 0; i < irq_cnt; i++) {
3506 		snprintf(irq_name, sizeof(irq_name), "int%d", i);
3507 		irq = platform_get_irq_byname(pdev, irq_name);
3508 		if (irq < 0)
3509 			irq = platform_get_irq(pdev, i);
3510 		if (irq < 0) {
3511 			ret = irq;
3512 			goto failed_irq;
3513 		}
3514 		ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3515 				       0, pdev->name, ndev);
3516 		if (ret)
3517 			goto failed_irq;
3518 
3519 		fep->irq[i] = irq;
3520 	}
3521 
3522 	init_completion(&fep->mdio_done);
3523 	ret = fec_enet_mii_init(pdev);
3524 	if (ret)
3525 		goto failed_mii_init;
3526 
3527 	/* Carrier starts down, phylib will bring it up */
3528 	netif_carrier_off(ndev);
3529 	fec_enet_clk_enable(ndev, false);
3530 	pinctrl_pm_select_sleep_state(&pdev->dev);
3531 
3532 	ret = register_netdev(ndev);
3533 	if (ret)
3534 		goto failed_register;
3535 
3536 	device_init_wakeup(&ndev->dev, fep->wol_flag &
3537 			   FEC_WOL_HAS_MAGIC_PACKET);
3538 
3539 	if (fep->bufdesc_ex && fep->ptp_clock)
3540 		netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3541 
3542 	fep->rx_copybreak = COPYBREAK_DEFAULT;
3543 	INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3544 
3545 	pm_runtime_mark_last_busy(&pdev->dev);
3546 	pm_runtime_put_autosuspend(&pdev->dev);
3547 
3548 	return 0;
3549 
3550 failed_register:
3551 	fec_enet_mii_remove(fep);
3552 failed_mii_init:
3553 failed_irq:
3554 failed_init:
3555 	fec_ptp_stop(pdev);
3556 	if (fep->reg_phy)
3557 		regulator_disable(fep->reg_phy);
3558 failed_reset:
3559 	pm_runtime_put(&pdev->dev);
3560 	pm_runtime_disable(&pdev->dev);
3561 failed_regulator:
3562 failed_clk_ipg:
3563 	fec_enet_clk_enable(ndev, false);
3564 failed_clk:
3565 	if (of_phy_is_fixed_link(np))
3566 		of_phy_deregister_fixed_link(np);
3567 	of_node_put(phy_node);
3568 failed_phy:
3569 	dev_id--;
3570 failed_ioremap:
3571 	free_netdev(ndev);
3572 
3573 	return ret;
3574 }
3575 
3576 static int
3577 fec_drv_remove(struct platform_device *pdev)
3578 {
3579 	struct net_device *ndev = platform_get_drvdata(pdev);
3580 	struct fec_enet_private *fep = netdev_priv(ndev);
3581 	struct device_node *np = pdev->dev.of_node;
3582 
3583 	cancel_work_sync(&fep->tx_timeout_work);
3584 	fec_ptp_stop(pdev);
3585 	unregister_netdev(ndev);
3586 	fec_enet_mii_remove(fep);
3587 	if (fep->reg_phy)
3588 		regulator_disable(fep->reg_phy);
3589 	pm_runtime_put(&pdev->dev);
3590 	pm_runtime_disable(&pdev->dev);
3591 	if (of_phy_is_fixed_link(np))
3592 		of_phy_deregister_fixed_link(np);
3593 	of_node_put(fep->phy_node);
3594 	free_netdev(ndev);
3595 
3596 	return 0;
3597 }
3598 
3599 static int __maybe_unused fec_suspend(struct device *dev)
3600 {
3601 	struct net_device *ndev = dev_get_drvdata(dev);
3602 	struct fec_enet_private *fep = netdev_priv(ndev);
3603 
3604 	rtnl_lock();
3605 	if (netif_running(ndev)) {
3606 		if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3607 			fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3608 		phy_stop(ndev->phydev);
3609 		napi_disable(&fep->napi);
3610 		netif_tx_lock_bh(ndev);
3611 		netif_device_detach(ndev);
3612 		netif_tx_unlock_bh(ndev);
3613 		fec_stop(ndev);
3614 		fec_enet_clk_enable(ndev, false);
3615 		if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3616 			pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3617 	}
3618 	rtnl_unlock();
3619 
3620 	if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3621 		regulator_disable(fep->reg_phy);
3622 
3623 	/* SOC supply clock to phy, when clock is disabled, phy link down
3624 	 * SOC control phy regulator, when regulator is disabled, phy link down
3625 	 */
3626 	if (fep->clk_enet_out || fep->reg_phy)
3627 		fep->link = 0;
3628 
3629 	return 0;
3630 }
3631 
3632 static int __maybe_unused fec_resume(struct device *dev)
3633 {
3634 	struct net_device *ndev = dev_get_drvdata(dev);
3635 	struct fec_enet_private *fep = netdev_priv(ndev);
3636 	struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3637 	int ret;
3638 	int val;
3639 
3640 	if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3641 		ret = regulator_enable(fep->reg_phy);
3642 		if (ret)
3643 			return ret;
3644 	}
3645 
3646 	rtnl_lock();
3647 	if (netif_running(ndev)) {
3648 		ret = fec_enet_clk_enable(ndev, true);
3649 		if (ret) {
3650 			rtnl_unlock();
3651 			goto failed_clk;
3652 		}
3653 		if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3654 			if (pdata && pdata->sleep_mode_enable)
3655 				pdata->sleep_mode_enable(false);
3656 			val = readl(fep->hwp + FEC_ECNTRL);
3657 			val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3658 			writel(val, fep->hwp + FEC_ECNTRL);
3659 			fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3660 		} else {
3661 			pinctrl_pm_select_default_state(&fep->pdev->dev);
3662 		}
3663 		fec_restart(ndev);
3664 		netif_tx_lock_bh(ndev);
3665 		netif_device_attach(ndev);
3666 		netif_tx_unlock_bh(ndev);
3667 		napi_enable(&fep->napi);
3668 		phy_start(ndev->phydev);
3669 	}
3670 	rtnl_unlock();
3671 
3672 	return 0;
3673 
3674 failed_clk:
3675 	if (fep->reg_phy)
3676 		regulator_disable(fep->reg_phy);
3677 	return ret;
3678 }
3679 
3680 static int __maybe_unused fec_runtime_suspend(struct device *dev)
3681 {
3682 	struct net_device *ndev = dev_get_drvdata(dev);
3683 	struct fec_enet_private *fep = netdev_priv(ndev);
3684 
3685 	clk_disable_unprepare(fep->clk_ipg);
3686 
3687 	return 0;
3688 }
3689 
3690 static int __maybe_unused fec_runtime_resume(struct device *dev)
3691 {
3692 	struct net_device *ndev = dev_get_drvdata(dev);
3693 	struct fec_enet_private *fep = netdev_priv(ndev);
3694 
3695 	return clk_prepare_enable(fep->clk_ipg);
3696 }
3697 
3698 static const struct dev_pm_ops fec_pm_ops = {
3699 	SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3700 	SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3701 };
3702 
3703 static struct platform_driver fec_driver = {
3704 	.driver	= {
3705 		.name	= DRIVER_NAME,
3706 		.pm	= &fec_pm_ops,
3707 		.of_match_table = fec_dt_ids,
3708 	},
3709 	.id_table = fec_devtype,
3710 	.probe	= fec_probe,
3711 	.remove	= fec_drv_remove,
3712 };
3713 
3714 module_platform_driver(fec_driver);
3715 
3716 MODULE_ALIAS("platform:"DRIVER_NAME);
3717 MODULE_LICENSE("GPL");
3718