1 /* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 * 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/string.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/ptrace.h> 29 #include <linux/errno.h> 30 #include <linux/ioport.h> 31 #include <linux/slab.h> 32 #include <linux/interrupt.h> 33 #include <linux/delay.h> 34 #include <linux/netdevice.h> 35 #include <linux/etherdevice.h> 36 #include <linux/skbuff.h> 37 #include <linux/in.h> 38 #include <linux/ip.h> 39 #include <net/ip.h> 40 #include <net/tso.h> 41 #include <linux/tcp.h> 42 #include <linux/udp.h> 43 #include <linux/icmp.h> 44 #include <linux/spinlock.h> 45 #include <linux/workqueue.h> 46 #include <linux/bitops.h> 47 #include <linux/io.h> 48 #include <linux/irq.h> 49 #include <linux/clk.h> 50 #include <linux/platform_device.h> 51 #include <linux/mdio.h> 52 #include <linux/phy.h> 53 #include <linux/fec.h> 54 #include <linux/of.h> 55 #include <linux/of_device.h> 56 #include <linux/of_gpio.h> 57 #include <linux/of_mdio.h> 58 #include <linux/of_net.h> 59 #include <linux/regulator/consumer.h> 60 #include <linux/if_vlan.h> 61 #include <linux/pinctrl/consumer.h> 62 #include <linux/prefetch.h> 63 #include <soc/imx/cpuidle.h> 64 65 #include <asm/cacheflush.h> 66 67 #include "fec.h" 68 69 static void set_multicast_list(struct net_device *ndev); 70 static void fec_enet_itr_coal_init(struct net_device *ndev); 71 72 #define DRIVER_NAME "fec" 73 74 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0)) 75 76 /* Pause frame feild and FIFO threshold */ 77 #define FEC_ENET_FCE (1 << 5) 78 #define FEC_ENET_RSEM_V 0x84 79 #define FEC_ENET_RSFL_V 16 80 #define FEC_ENET_RAEM_V 0x8 81 #define FEC_ENET_RAFL_V 0x8 82 #define FEC_ENET_OPD_V 0xFFF0 83 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 84 85 static struct platform_device_id fec_devtype[] = { 86 { 87 /* keep it for coldfire */ 88 .name = DRIVER_NAME, 89 .driver_data = 0, 90 }, { 91 .name = "imx25-fec", 92 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR, 93 }, { 94 .name = "imx27-fec", 95 .driver_data = FEC_QUIRK_MIB_CLEAR, 96 }, { 97 .name = "imx28-fec", 98 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 99 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC, 100 }, { 101 .name = "imx6q-fec", 102 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 103 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 104 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 105 FEC_QUIRK_HAS_RACC, 106 }, { 107 .name = "mvf600-fec", 108 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 109 }, { 110 .name = "imx6sx-fec", 111 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 112 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 113 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 114 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 115 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE, 116 }, { 117 .name = "imx6ul-fec", 118 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 119 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 120 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 121 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 122 FEC_QUIRK_HAS_COALESCE, 123 }, { 124 /* sentinel */ 125 } 126 }; 127 MODULE_DEVICE_TABLE(platform, fec_devtype); 128 129 enum imx_fec_type { 130 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 131 IMX27_FEC, /* runs on i.mx27/35/51 */ 132 IMX28_FEC, 133 IMX6Q_FEC, 134 MVF600_FEC, 135 IMX6SX_FEC, 136 IMX6UL_FEC, 137 }; 138 139 static const struct of_device_id fec_dt_ids[] = { 140 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 141 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 142 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 143 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 144 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 145 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 146 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 147 { /* sentinel */ } 148 }; 149 MODULE_DEVICE_TABLE(of, fec_dt_ids); 150 151 static unsigned char macaddr[ETH_ALEN]; 152 module_param_array(macaddr, byte, NULL, 0); 153 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 154 155 #if defined(CONFIG_M5272) 156 /* 157 * Some hardware gets it MAC address out of local flash memory. 158 * if this is non-zero then assume it is the address to get MAC from. 159 */ 160 #if defined(CONFIG_NETtel) 161 #define FEC_FLASHMAC 0xf0006006 162 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 163 #define FEC_FLASHMAC 0xf0006000 164 #elif defined(CONFIG_CANCam) 165 #define FEC_FLASHMAC 0xf0020000 166 #elif defined (CONFIG_M5272C3) 167 #define FEC_FLASHMAC (0xffe04000 + 4) 168 #elif defined(CONFIG_MOD5272) 169 #define FEC_FLASHMAC 0xffc0406b 170 #else 171 #define FEC_FLASHMAC 0 172 #endif 173 #endif /* CONFIG_M5272 */ 174 175 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 176 * 177 * 2048 byte skbufs are allocated. However, alignment requirements 178 * varies between FEC variants. Worst case is 64, so round down by 64. 179 */ 180 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 181 #define PKT_MINBUF_SIZE 64 182 183 /* FEC receive acceleration */ 184 #define FEC_RACC_IPDIS (1 << 1) 185 #define FEC_RACC_PRODIS (1 << 2) 186 #define FEC_RACC_SHIFT16 BIT(7) 187 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 188 189 /* MIB Control Register */ 190 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 191 192 /* 193 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 194 * size bits. Other FEC hardware does not, so we need to take that into 195 * account when setting it. 196 */ 197 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 198 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 199 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 200 #else 201 #define OPT_FRAME_SIZE 0 202 #endif 203 204 /* FEC MII MMFR bits definition */ 205 #define FEC_MMFR_ST (1 << 30) 206 #define FEC_MMFR_OP_READ (2 << 28) 207 #define FEC_MMFR_OP_WRITE (1 << 28) 208 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 209 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 210 #define FEC_MMFR_TA (2 << 16) 211 #define FEC_MMFR_DATA(v) (v & 0xffff) 212 /* FEC ECR bits definition */ 213 #define FEC_ECR_MAGICEN (1 << 2) 214 #define FEC_ECR_SLEEP (1 << 3) 215 216 #define FEC_MII_TIMEOUT 30000 /* us */ 217 218 /* Transmitter timeout */ 219 #define TX_TIMEOUT (2 * HZ) 220 221 #define FEC_PAUSE_FLAG_AUTONEG 0x1 222 #define FEC_PAUSE_FLAG_ENABLE 0x2 223 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 224 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 225 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 226 227 #define COPYBREAK_DEFAULT 256 228 229 /* Max number of allowed TCP segments for software TSO */ 230 #define FEC_MAX_TSO_SEGS 100 231 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 232 233 #define IS_TSO_HEADER(txq, addr) \ 234 ((addr >= txq->tso_hdrs_dma) && \ 235 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 236 237 static int mii_cnt; 238 239 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 240 struct bufdesc_prop *bd) 241 { 242 return (bdp >= bd->last) ? bd->base 243 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 244 } 245 246 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 247 struct bufdesc_prop *bd) 248 { 249 return (bdp <= bd->base) ? bd->last 250 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 251 } 252 253 static int fec_enet_get_bd_index(struct bufdesc *bdp, 254 struct bufdesc_prop *bd) 255 { 256 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 257 } 258 259 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 260 { 261 int entries; 262 263 entries = (((const char *)txq->dirty_tx - 264 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 265 266 return entries >= 0 ? entries : entries + txq->bd.ring_size; 267 } 268 269 static void swap_buffer(void *bufaddr, int len) 270 { 271 int i; 272 unsigned int *buf = bufaddr; 273 274 for (i = 0; i < len; i += 4, buf++) 275 swab32s(buf); 276 } 277 278 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 279 { 280 int i; 281 unsigned int *src = src_buf; 282 unsigned int *dst = dst_buf; 283 284 for (i = 0; i < len; i += 4, src++, dst++) 285 *dst = swab32p(src); 286 } 287 288 static void fec_dump(struct net_device *ndev) 289 { 290 struct fec_enet_private *fep = netdev_priv(ndev); 291 struct bufdesc *bdp; 292 struct fec_enet_priv_tx_q *txq; 293 int index = 0; 294 295 netdev_info(ndev, "TX ring dump\n"); 296 pr_info("Nr SC addr len SKB\n"); 297 298 txq = fep->tx_queue[0]; 299 bdp = txq->bd.base; 300 301 do { 302 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 303 index, 304 bdp == txq->bd.cur ? 'S' : ' ', 305 bdp == txq->dirty_tx ? 'H' : ' ', 306 fec16_to_cpu(bdp->cbd_sc), 307 fec32_to_cpu(bdp->cbd_bufaddr), 308 fec16_to_cpu(bdp->cbd_datlen), 309 txq->tx_skbuff[index]); 310 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 311 index++; 312 } while (bdp != txq->bd.base); 313 } 314 315 static inline bool is_ipv4_pkt(struct sk_buff *skb) 316 { 317 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 318 } 319 320 static int 321 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 322 { 323 /* Only run for packets requiring a checksum. */ 324 if (skb->ip_summed != CHECKSUM_PARTIAL) 325 return 0; 326 327 if (unlikely(skb_cow_head(skb, 0))) 328 return -1; 329 330 if (is_ipv4_pkt(skb)) 331 ip_hdr(skb)->check = 0; 332 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 333 334 return 0; 335 } 336 337 static struct bufdesc * 338 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 339 struct sk_buff *skb, 340 struct net_device *ndev) 341 { 342 struct fec_enet_private *fep = netdev_priv(ndev); 343 struct bufdesc *bdp = txq->bd.cur; 344 struct bufdesc_ex *ebdp; 345 int nr_frags = skb_shinfo(skb)->nr_frags; 346 int frag, frag_len; 347 unsigned short status; 348 unsigned int estatus = 0; 349 skb_frag_t *this_frag; 350 unsigned int index; 351 void *bufaddr; 352 dma_addr_t addr; 353 int i; 354 355 for (frag = 0; frag < nr_frags; frag++) { 356 this_frag = &skb_shinfo(skb)->frags[frag]; 357 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 358 ebdp = (struct bufdesc_ex *)bdp; 359 360 status = fec16_to_cpu(bdp->cbd_sc); 361 status &= ~BD_ENET_TX_STATS; 362 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 363 frag_len = skb_shinfo(skb)->frags[frag].size; 364 365 /* Handle the last BD specially */ 366 if (frag == nr_frags - 1) { 367 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 368 if (fep->bufdesc_ex) { 369 estatus |= BD_ENET_TX_INT; 370 if (unlikely(skb_shinfo(skb)->tx_flags & 371 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 372 estatus |= BD_ENET_TX_TS; 373 } 374 } 375 376 if (fep->bufdesc_ex) { 377 if (fep->quirks & FEC_QUIRK_HAS_AVB) 378 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 379 if (skb->ip_summed == CHECKSUM_PARTIAL) 380 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 381 ebdp->cbd_bdu = 0; 382 ebdp->cbd_esc = cpu_to_fec32(estatus); 383 } 384 385 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset; 386 387 index = fec_enet_get_bd_index(bdp, &txq->bd); 388 if (((unsigned long) bufaddr) & fep->tx_align || 389 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 390 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 391 bufaddr = txq->tx_bounce[index]; 392 393 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 394 swap_buffer(bufaddr, frag_len); 395 } 396 397 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 398 DMA_TO_DEVICE); 399 if (dma_mapping_error(&fep->pdev->dev, addr)) { 400 if (net_ratelimit()) 401 netdev_err(ndev, "Tx DMA memory map failed\n"); 402 goto dma_mapping_error; 403 } 404 405 bdp->cbd_bufaddr = cpu_to_fec32(addr); 406 bdp->cbd_datlen = cpu_to_fec16(frag_len); 407 /* Make sure the updates to rest of the descriptor are 408 * performed before transferring ownership. 409 */ 410 wmb(); 411 bdp->cbd_sc = cpu_to_fec16(status); 412 } 413 414 return bdp; 415 dma_mapping_error: 416 bdp = txq->bd.cur; 417 for (i = 0; i < frag; i++) { 418 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 419 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 420 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 421 } 422 return ERR_PTR(-ENOMEM); 423 } 424 425 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 426 struct sk_buff *skb, struct net_device *ndev) 427 { 428 struct fec_enet_private *fep = netdev_priv(ndev); 429 int nr_frags = skb_shinfo(skb)->nr_frags; 430 struct bufdesc *bdp, *last_bdp; 431 void *bufaddr; 432 dma_addr_t addr; 433 unsigned short status; 434 unsigned short buflen; 435 unsigned int estatus = 0; 436 unsigned int index; 437 int entries_free; 438 439 entries_free = fec_enet_get_free_txdesc_num(txq); 440 if (entries_free < MAX_SKB_FRAGS + 1) { 441 dev_kfree_skb_any(skb); 442 if (net_ratelimit()) 443 netdev_err(ndev, "NOT enough BD for SG!\n"); 444 return NETDEV_TX_OK; 445 } 446 447 /* Protocol checksum off-load for TCP and UDP. */ 448 if (fec_enet_clear_csum(skb, ndev)) { 449 dev_kfree_skb_any(skb); 450 return NETDEV_TX_OK; 451 } 452 453 /* Fill in a Tx ring entry */ 454 bdp = txq->bd.cur; 455 last_bdp = bdp; 456 status = fec16_to_cpu(bdp->cbd_sc); 457 status &= ~BD_ENET_TX_STATS; 458 459 /* Set buffer length and buffer pointer */ 460 bufaddr = skb->data; 461 buflen = skb_headlen(skb); 462 463 index = fec_enet_get_bd_index(bdp, &txq->bd); 464 if (((unsigned long) bufaddr) & fep->tx_align || 465 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 466 memcpy(txq->tx_bounce[index], skb->data, buflen); 467 bufaddr = txq->tx_bounce[index]; 468 469 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 470 swap_buffer(bufaddr, buflen); 471 } 472 473 /* Push the data cache so the CPM does not get stale memory data. */ 474 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 475 if (dma_mapping_error(&fep->pdev->dev, addr)) { 476 dev_kfree_skb_any(skb); 477 if (net_ratelimit()) 478 netdev_err(ndev, "Tx DMA memory map failed\n"); 479 return NETDEV_TX_OK; 480 } 481 482 if (nr_frags) { 483 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 484 if (IS_ERR(last_bdp)) { 485 dma_unmap_single(&fep->pdev->dev, addr, 486 buflen, DMA_TO_DEVICE); 487 dev_kfree_skb_any(skb); 488 return NETDEV_TX_OK; 489 } 490 } else { 491 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 492 if (fep->bufdesc_ex) { 493 estatus = BD_ENET_TX_INT; 494 if (unlikely(skb_shinfo(skb)->tx_flags & 495 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 496 estatus |= BD_ENET_TX_TS; 497 } 498 } 499 bdp->cbd_bufaddr = cpu_to_fec32(addr); 500 bdp->cbd_datlen = cpu_to_fec16(buflen); 501 502 if (fep->bufdesc_ex) { 503 504 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 505 506 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 507 fep->hwts_tx_en)) 508 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 509 510 if (fep->quirks & FEC_QUIRK_HAS_AVB) 511 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 512 513 if (skb->ip_summed == CHECKSUM_PARTIAL) 514 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 515 516 ebdp->cbd_bdu = 0; 517 ebdp->cbd_esc = cpu_to_fec32(estatus); 518 } 519 520 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 521 /* Save skb pointer */ 522 txq->tx_skbuff[index] = skb; 523 524 /* Make sure the updates to rest of the descriptor are performed before 525 * transferring ownership. 526 */ 527 wmb(); 528 529 /* Send it on its way. Tell FEC it's ready, interrupt when done, 530 * it's the last BD of the frame, and to put the CRC on the end. 531 */ 532 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 533 bdp->cbd_sc = cpu_to_fec16(status); 534 535 /* If this was the last BD in the ring, start at the beginning again. */ 536 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 537 538 skb_tx_timestamp(skb); 539 540 /* Make sure the update to bdp and tx_skbuff are performed before 541 * txq->bd.cur. 542 */ 543 wmb(); 544 txq->bd.cur = bdp; 545 546 /* Trigger transmission start */ 547 writel(0, txq->bd.reg_desc_active); 548 549 return 0; 550 } 551 552 static int 553 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 554 struct net_device *ndev, 555 struct bufdesc *bdp, int index, char *data, 556 int size, bool last_tcp, bool is_last) 557 { 558 struct fec_enet_private *fep = netdev_priv(ndev); 559 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 560 unsigned short status; 561 unsigned int estatus = 0; 562 dma_addr_t addr; 563 564 status = fec16_to_cpu(bdp->cbd_sc); 565 status &= ~BD_ENET_TX_STATS; 566 567 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 568 569 if (((unsigned long) data) & fep->tx_align || 570 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 571 memcpy(txq->tx_bounce[index], data, size); 572 data = txq->tx_bounce[index]; 573 574 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 575 swap_buffer(data, size); 576 } 577 578 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 579 if (dma_mapping_error(&fep->pdev->dev, addr)) { 580 dev_kfree_skb_any(skb); 581 if (net_ratelimit()) 582 netdev_err(ndev, "Tx DMA memory map failed\n"); 583 return NETDEV_TX_BUSY; 584 } 585 586 bdp->cbd_datlen = cpu_to_fec16(size); 587 bdp->cbd_bufaddr = cpu_to_fec32(addr); 588 589 if (fep->bufdesc_ex) { 590 if (fep->quirks & FEC_QUIRK_HAS_AVB) 591 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 592 if (skb->ip_summed == CHECKSUM_PARTIAL) 593 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 594 ebdp->cbd_bdu = 0; 595 ebdp->cbd_esc = cpu_to_fec32(estatus); 596 } 597 598 /* Handle the last BD specially */ 599 if (last_tcp) 600 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 601 if (is_last) { 602 status |= BD_ENET_TX_INTR; 603 if (fep->bufdesc_ex) 604 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 605 } 606 607 bdp->cbd_sc = cpu_to_fec16(status); 608 609 return 0; 610 } 611 612 static int 613 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 614 struct sk_buff *skb, struct net_device *ndev, 615 struct bufdesc *bdp, int index) 616 { 617 struct fec_enet_private *fep = netdev_priv(ndev); 618 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 619 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 620 void *bufaddr; 621 unsigned long dmabuf; 622 unsigned short status; 623 unsigned int estatus = 0; 624 625 status = fec16_to_cpu(bdp->cbd_sc); 626 status &= ~BD_ENET_TX_STATS; 627 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 628 629 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 630 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 631 if (((unsigned long)bufaddr) & fep->tx_align || 632 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 633 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 634 bufaddr = txq->tx_bounce[index]; 635 636 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 637 swap_buffer(bufaddr, hdr_len); 638 639 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 640 hdr_len, DMA_TO_DEVICE); 641 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 642 dev_kfree_skb_any(skb); 643 if (net_ratelimit()) 644 netdev_err(ndev, "Tx DMA memory map failed\n"); 645 return NETDEV_TX_BUSY; 646 } 647 } 648 649 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 650 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 651 652 if (fep->bufdesc_ex) { 653 if (fep->quirks & FEC_QUIRK_HAS_AVB) 654 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 655 if (skb->ip_summed == CHECKSUM_PARTIAL) 656 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 657 ebdp->cbd_bdu = 0; 658 ebdp->cbd_esc = cpu_to_fec32(estatus); 659 } 660 661 bdp->cbd_sc = cpu_to_fec16(status); 662 663 return 0; 664 } 665 666 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 667 struct sk_buff *skb, 668 struct net_device *ndev) 669 { 670 struct fec_enet_private *fep = netdev_priv(ndev); 671 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 672 int total_len, data_left; 673 struct bufdesc *bdp = txq->bd.cur; 674 struct tso_t tso; 675 unsigned int index = 0; 676 int ret; 677 678 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 679 dev_kfree_skb_any(skb); 680 if (net_ratelimit()) 681 netdev_err(ndev, "NOT enough BD for TSO!\n"); 682 return NETDEV_TX_OK; 683 } 684 685 /* Protocol checksum off-load for TCP and UDP. */ 686 if (fec_enet_clear_csum(skb, ndev)) { 687 dev_kfree_skb_any(skb); 688 return NETDEV_TX_OK; 689 } 690 691 /* Initialize the TSO handler, and prepare the first payload */ 692 tso_start(skb, &tso); 693 694 total_len = skb->len - hdr_len; 695 while (total_len > 0) { 696 char *hdr; 697 698 index = fec_enet_get_bd_index(bdp, &txq->bd); 699 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 700 total_len -= data_left; 701 702 /* prepare packet headers: MAC + IP + TCP */ 703 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 704 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 705 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 706 if (ret) 707 goto err_release; 708 709 while (data_left > 0) { 710 int size; 711 712 size = min_t(int, tso.size, data_left); 713 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 714 index = fec_enet_get_bd_index(bdp, &txq->bd); 715 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 716 bdp, index, 717 tso.data, size, 718 size == data_left, 719 total_len == 0); 720 if (ret) 721 goto err_release; 722 723 data_left -= size; 724 tso_build_data(skb, &tso, size); 725 } 726 727 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 728 } 729 730 /* Save skb pointer */ 731 txq->tx_skbuff[index] = skb; 732 733 skb_tx_timestamp(skb); 734 txq->bd.cur = bdp; 735 736 /* Trigger transmission start */ 737 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 738 !readl(txq->bd.reg_desc_active) || 739 !readl(txq->bd.reg_desc_active) || 740 !readl(txq->bd.reg_desc_active) || 741 !readl(txq->bd.reg_desc_active)) 742 writel(0, txq->bd.reg_desc_active); 743 744 return 0; 745 746 err_release: 747 /* TODO: Release all used data descriptors for TSO */ 748 return ret; 749 } 750 751 static netdev_tx_t 752 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 753 { 754 struct fec_enet_private *fep = netdev_priv(ndev); 755 int entries_free; 756 unsigned short queue; 757 struct fec_enet_priv_tx_q *txq; 758 struct netdev_queue *nq; 759 int ret; 760 761 queue = skb_get_queue_mapping(skb); 762 txq = fep->tx_queue[queue]; 763 nq = netdev_get_tx_queue(ndev, queue); 764 765 if (skb_is_gso(skb)) 766 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 767 else 768 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 769 if (ret) 770 return ret; 771 772 entries_free = fec_enet_get_free_txdesc_num(txq); 773 if (entries_free <= txq->tx_stop_threshold) 774 netif_tx_stop_queue(nq); 775 776 return NETDEV_TX_OK; 777 } 778 779 /* Init RX & TX buffer descriptors 780 */ 781 static void fec_enet_bd_init(struct net_device *dev) 782 { 783 struct fec_enet_private *fep = netdev_priv(dev); 784 struct fec_enet_priv_tx_q *txq; 785 struct fec_enet_priv_rx_q *rxq; 786 struct bufdesc *bdp; 787 unsigned int i; 788 unsigned int q; 789 790 for (q = 0; q < fep->num_rx_queues; q++) { 791 /* Initialize the receive buffer descriptors. */ 792 rxq = fep->rx_queue[q]; 793 bdp = rxq->bd.base; 794 795 for (i = 0; i < rxq->bd.ring_size; i++) { 796 797 /* Initialize the BD for every fragment in the page. */ 798 if (bdp->cbd_bufaddr) 799 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 800 else 801 bdp->cbd_sc = cpu_to_fec16(0); 802 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 803 } 804 805 /* Set the last buffer to wrap */ 806 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 807 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 808 809 rxq->bd.cur = rxq->bd.base; 810 } 811 812 for (q = 0; q < fep->num_tx_queues; q++) { 813 /* ...and the same for transmit */ 814 txq = fep->tx_queue[q]; 815 bdp = txq->bd.base; 816 txq->bd.cur = bdp; 817 818 for (i = 0; i < txq->bd.ring_size; i++) { 819 /* Initialize the BD for every fragment in the page. */ 820 bdp->cbd_sc = cpu_to_fec16(0); 821 if (bdp->cbd_bufaddr && 822 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 823 dma_unmap_single(&fep->pdev->dev, 824 fec32_to_cpu(bdp->cbd_bufaddr), 825 fec16_to_cpu(bdp->cbd_datlen), 826 DMA_TO_DEVICE); 827 if (txq->tx_skbuff[i]) { 828 dev_kfree_skb_any(txq->tx_skbuff[i]); 829 txq->tx_skbuff[i] = NULL; 830 } 831 bdp->cbd_bufaddr = cpu_to_fec32(0); 832 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 833 } 834 835 /* Set the last buffer to wrap */ 836 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 837 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 838 txq->dirty_tx = bdp; 839 } 840 } 841 842 static void fec_enet_active_rxring(struct net_device *ndev) 843 { 844 struct fec_enet_private *fep = netdev_priv(ndev); 845 int i; 846 847 for (i = 0; i < fep->num_rx_queues; i++) 848 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 849 } 850 851 static void fec_enet_enable_ring(struct net_device *ndev) 852 { 853 struct fec_enet_private *fep = netdev_priv(ndev); 854 struct fec_enet_priv_tx_q *txq; 855 struct fec_enet_priv_rx_q *rxq; 856 int i; 857 858 for (i = 0; i < fep->num_rx_queues; i++) { 859 rxq = fep->rx_queue[i]; 860 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 861 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 862 863 /* enable DMA1/2 */ 864 if (i) 865 writel(RCMR_MATCHEN | RCMR_CMP(i), 866 fep->hwp + FEC_RCMR(i)); 867 } 868 869 for (i = 0; i < fep->num_tx_queues; i++) { 870 txq = fep->tx_queue[i]; 871 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 872 873 /* enable DMA1/2 */ 874 if (i) 875 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 876 fep->hwp + FEC_DMA_CFG(i)); 877 } 878 } 879 880 static void fec_enet_reset_skb(struct net_device *ndev) 881 { 882 struct fec_enet_private *fep = netdev_priv(ndev); 883 struct fec_enet_priv_tx_q *txq; 884 int i, j; 885 886 for (i = 0; i < fep->num_tx_queues; i++) { 887 txq = fep->tx_queue[i]; 888 889 for (j = 0; j < txq->bd.ring_size; j++) { 890 if (txq->tx_skbuff[j]) { 891 dev_kfree_skb_any(txq->tx_skbuff[j]); 892 txq->tx_skbuff[j] = NULL; 893 } 894 } 895 } 896 } 897 898 /* 899 * This function is called to start or restart the FEC during a link 900 * change, transmit timeout, or to reconfigure the FEC. The network 901 * packet processing for this device must be stopped before this call. 902 */ 903 static void 904 fec_restart(struct net_device *ndev) 905 { 906 struct fec_enet_private *fep = netdev_priv(ndev); 907 u32 val; 908 u32 temp_mac[2]; 909 u32 rcntl = OPT_FRAME_SIZE | 0x04; 910 u32 ecntl = 0x2; /* ETHEREN */ 911 912 /* Whack a reset. We should wait for this. 913 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 914 * instead of reset MAC itself. 915 */ 916 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 917 writel(0, fep->hwp + FEC_ECNTRL); 918 } else { 919 writel(1, fep->hwp + FEC_ECNTRL); 920 udelay(10); 921 } 922 923 /* 924 * enet-mac reset will reset mac address registers too, 925 * so need to reconfigure it. 926 */ 927 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 928 writel((__force u32)cpu_to_be32(temp_mac[0]), 929 fep->hwp + FEC_ADDR_LOW); 930 writel((__force u32)cpu_to_be32(temp_mac[1]), 931 fep->hwp + FEC_ADDR_HIGH); 932 933 /* Clear any outstanding interrupt. */ 934 writel(0xffffffff, fep->hwp + FEC_IEVENT); 935 936 fec_enet_bd_init(ndev); 937 938 fec_enet_enable_ring(ndev); 939 940 /* Reset tx SKB buffers. */ 941 fec_enet_reset_skb(ndev); 942 943 /* Enable MII mode */ 944 if (fep->full_duplex == DUPLEX_FULL) { 945 /* FD enable */ 946 writel(0x04, fep->hwp + FEC_X_CNTRL); 947 } else { 948 /* No Rcv on Xmit */ 949 rcntl |= 0x02; 950 writel(0x0, fep->hwp + FEC_X_CNTRL); 951 } 952 953 /* Set MII speed */ 954 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 955 956 #if !defined(CONFIG_M5272) 957 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 958 val = readl(fep->hwp + FEC_RACC); 959 /* align IP header */ 960 val |= FEC_RACC_SHIFT16; 961 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 962 /* set RX checksum */ 963 val |= FEC_RACC_OPTIONS; 964 else 965 val &= ~FEC_RACC_OPTIONS; 966 writel(val, fep->hwp + FEC_RACC); 967 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 968 } 969 #endif 970 971 /* 972 * The phy interface and speed need to get configured 973 * differently on enet-mac. 974 */ 975 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 976 /* Enable flow control and length check */ 977 rcntl |= 0x40000000 | 0x00000020; 978 979 /* RGMII, RMII or MII */ 980 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 981 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 982 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 983 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 984 rcntl |= (1 << 6); 985 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 986 rcntl |= (1 << 8); 987 else 988 rcntl &= ~(1 << 8); 989 990 /* 1G, 100M or 10M */ 991 if (ndev->phydev) { 992 if (ndev->phydev->speed == SPEED_1000) 993 ecntl |= (1 << 5); 994 else if (ndev->phydev->speed == SPEED_100) 995 rcntl &= ~(1 << 9); 996 else 997 rcntl |= (1 << 9); 998 } 999 } else { 1000 #ifdef FEC_MIIGSK_ENR 1001 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1002 u32 cfgr; 1003 /* disable the gasket and wait */ 1004 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1005 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1006 udelay(1); 1007 1008 /* 1009 * configure the gasket: 1010 * RMII, 50 MHz, no loopback, no echo 1011 * MII, 25 MHz, no loopback, no echo 1012 */ 1013 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1014 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1015 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1016 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1017 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1018 1019 /* re-enable the gasket */ 1020 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1021 } 1022 #endif 1023 } 1024 1025 #if !defined(CONFIG_M5272) 1026 /* enable pause frame*/ 1027 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1028 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1029 ndev->phydev && ndev->phydev->pause)) { 1030 rcntl |= FEC_ENET_FCE; 1031 1032 /* set FIFO threshold parameter to reduce overrun */ 1033 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1034 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1035 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1036 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1037 1038 /* OPD */ 1039 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1040 } else { 1041 rcntl &= ~FEC_ENET_FCE; 1042 } 1043 #endif /* !defined(CONFIG_M5272) */ 1044 1045 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1046 1047 /* Setup multicast filter. */ 1048 set_multicast_list(ndev); 1049 #ifndef CONFIG_M5272 1050 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1051 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1052 #endif 1053 1054 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1055 /* enable ENET endian swap */ 1056 ecntl |= (1 << 8); 1057 /* enable ENET store and forward mode */ 1058 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1059 } 1060 1061 if (fep->bufdesc_ex) 1062 ecntl |= (1 << 4); 1063 1064 #ifndef CONFIG_M5272 1065 /* Enable the MIB statistic event counters */ 1066 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1067 #endif 1068 1069 /* And last, enable the transmit and receive processing */ 1070 writel(ecntl, fep->hwp + FEC_ECNTRL); 1071 fec_enet_active_rxring(ndev); 1072 1073 if (fep->bufdesc_ex) 1074 fec_ptp_start_cyclecounter(ndev); 1075 1076 /* Enable interrupts we wish to service */ 1077 if (fep->link) 1078 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1079 else 1080 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); 1081 1082 /* Init the interrupt coalescing */ 1083 fec_enet_itr_coal_init(ndev); 1084 1085 } 1086 1087 static void 1088 fec_stop(struct net_device *ndev) 1089 { 1090 struct fec_enet_private *fep = netdev_priv(ndev); 1091 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1092 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1093 u32 val; 1094 1095 /* We cannot expect a graceful transmit stop without link !!! */ 1096 if (fep->link) { 1097 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1098 udelay(10); 1099 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1100 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1101 } 1102 1103 /* Whack a reset. We should wait for this. 1104 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1105 * instead of reset MAC itself. 1106 */ 1107 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1108 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 1109 writel(0, fep->hwp + FEC_ECNTRL); 1110 } else { 1111 writel(1, fep->hwp + FEC_ECNTRL); 1112 udelay(10); 1113 } 1114 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1115 } else { 1116 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1117 val = readl(fep->hwp + FEC_ECNTRL); 1118 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1119 writel(val, fep->hwp + FEC_ECNTRL); 1120 1121 if (pdata && pdata->sleep_mode_enable) 1122 pdata->sleep_mode_enable(true); 1123 } 1124 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1125 1126 /* We have to keep ENET enabled to have MII interrupt stay working */ 1127 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1128 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1129 writel(2, fep->hwp + FEC_ECNTRL); 1130 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1131 } 1132 } 1133 1134 1135 static void 1136 fec_timeout(struct net_device *ndev) 1137 { 1138 struct fec_enet_private *fep = netdev_priv(ndev); 1139 1140 fec_dump(ndev); 1141 1142 ndev->stats.tx_errors++; 1143 1144 schedule_work(&fep->tx_timeout_work); 1145 } 1146 1147 static void fec_enet_timeout_work(struct work_struct *work) 1148 { 1149 struct fec_enet_private *fep = 1150 container_of(work, struct fec_enet_private, tx_timeout_work); 1151 struct net_device *ndev = fep->netdev; 1152 1153 rtnl_lock(); 1154 if (netif_device_present(ndev) || netif_running(ndev)) { 1155 napi_disable(&fep->napi); 1156 netif_tx_lock_bh(ndev); 1157 fec_restart(ndev); 1158 netif_wake_queue(ndev); 1159 netif_tx_unlock_bh(ndev); 1160 napi_enable(&fep->napi); 1161 } 1162 rtnl_unlock(); 1163 } 1164 1165 static void 1166 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1167 struct skb_shared_hwtstamps *hwtstamps) 1168 { 1169 unsigned long flags; 1170 u64 ns; 1171 1172 spin_lock_irqsave(&fep->tmreg_lock, flags); 1173 ns = timecounter_cyc2time(&fep->tc, ts); 1174 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1175 1176 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1177 hwtstamps->hwtstamp = ns_to_ktime(ns); 1178 } 1179 1180 static void 1181 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1182 { 1183 struct fec_enet_private *fep; 1184 struct bufdesc *bdp; 1185 unsigned short status; 1186 struct sk_buff *skb; 1187 struct fec_enet_priv_tx_q *txq; 1188 struct netdev_queue *nq; 1189 int index = 0; 1190 int entries_free; 1191 1192 fep = netdev_priv(ndev); 1193 1194 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1195 1196 txq = fep->tx_queue[queue_id]; 1197 /* get next bdp of dirty_tx */ 1198 nq = netdev_get_tx_queue(ndev, queue_id); 1199 bdp = txq->dirty_tx; 1200 1201 /* get next bdp of dirty_tx */ 1202 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1203 1204 while (bdp != READ_ONCE(txq->bd.cur)) { 1205 /* Order the load of bd.cur and cbd_sc */ 1206 rmb(); 1207 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1208 if (status & BD_ENET_TX_READY) 1209 break; 1210 1211 index = fec_enet_get_bd_index(bdp, &txq->bd); 1212 1213 skb = txq->tx_skbuff[index]; 1214 txq->tx_skbuff[index] = NULL; 1215 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1216 dma_unmap_single(&fep->pdev->dev, 1217 fec32_to_cpu(bdp->cbd_bufaddr), 1218 fec16_to_cpu(bdp->cbd_datlen), 1219 DMA_TO_DEVICE); 1220 bdp->cbd_bufaddr = cpu_to_fec32(0); 1221 if (!skb) 1222 goto skb_done; 1223 1224 /* Check for errors. */ 1225 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1226 BD_ENET_TX_RL | BD_ENET_TX_UN | 1227 BD_ENET_TX_CSL)) { 1228 ndev->stats.tx_errors++; 1229 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1230 ndev->stats.tx_heartbeat_errors++; 1231 if (status & BD_ENET_TX_LC) /* Late collision */ 1232 ndev->stats.tx_window_errors++; 1233 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1234 ndev->stats.tx_aborted_errors++; 1235 if (status & BD_ENET_TX_UN) /* Underrun */ 1236 ndev->stats.tx_fifo_errors++; 1237 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1238 ndev->stats.tx_carrier_errors++; 1239 } else { 1240 ndev->stats.tx_packets++; 1241 ndev->stats.tx_bytes += skb->len; 1242 } 1243 1244 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 1245 fep->bufdesc_ex) { 1246 struct skb_shared_hwtstamps shhwtstamps; 1247 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1248 1249 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1250 skb_tstamp_tx(skb, &shhwtstamps); 1251 } 1252 1253 /* Deferred means some collisions occurred during transmit, 1254 * but we eventually sent the packet OK. 1255 */ 1256 if (status & BD_ENET_TX_DEF) 1257 ndev->stats.collisions++; 1258 1259 /* Free the sk buffer associated with this last transmit */ 1260 dev_kfree_skb_any(skb); 1261 skb_done: 1262 /* Make sure the update to bdp and tx_skbuff are performed 1263 * before dirty_tx 1264 */ 1265 wmb(); 1266 txq->dirty_tx = bdp; 1267 1268 /* Update pointer to next buffer descriptor to be transmitted */ 1269 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1270 1271 /* Since we have freed up a buffer, the ring is no longer full 1272 */ 1273 if (netif_queue_stopped(ndev)) { 1274 entries_free = fec_enet_get_free_txdesc_num(txq); 1275 if (entries_free >= txq->tx_wake_threshold) 1276 netif_tx_wake_queue(nq); 1277 } 1278 } 1279 1280 /* ERR006358: Keep the transmitter going */ 1281 if (bdp != txq->bd.cur && 1282 readl(txq->bd.reg_desc_active) == 0) 1283 writel(0, txq->bd.reg_desc_active); 1284 } 1285 1286 static void 1287 fec_enet_tx(struct net_device *ndev) 1288 { 1289 struct fec_enet_private *fep = netdev_priv(ndev); 1290 u16 queue_id; 1291 /* First process class A queue, then Class B and Best Effort queue */ 1292 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) { 1293 clear_bit(queue_id, &fep->work_tx); 1294 fec_enet_tx_queue(ndev, queue_id); 1295 } 1296 return; 1297 } 1298 1299 static int 1300 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1301 { 1302 struct fec_enet_private *fep = netdev_priv(ndev); 1303 int off; 1304 1305 off = ((unsigned long)skb->data) & fep->rx_align; 1306 if (off) 1307 skb_reserve(skb, fep->rx_align + 1 - off); 1308 1309 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1310 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1311 if (net_ratelimit()) 1312 netdev_err(ndev, "Rx DMA memory map failed\n"); 1313 return -ENOMEM; 1314 } 1315 1316 return 0; 1317 } 1318 1319 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1320 struct bufdesc *bdp, u32 length, bool swap) 1321 { 1322 struct fec_enet_private *fep = netdev_priv(ndev); 1323 struct sk_buff *new_skb; 1324 1325 if (length > fep->rx_copybreak) 1326 return false; 1327 1328 new_skb = netdev_alloc_skb(ndev, length); 1329 if (!new_skb) 1330 return false; 1331 1332 dma_sync_single_for_cpu(&fep->pdev->dev, 1333 fec32_to_cpu(bdp->cbd_bufaddr), 1334 FEC_ENET_RX_FRSIZE - fep->rx_align, 1335 DMA_FROM_DEVICE); 1336 if (!swap) 1337 memcpy(new_skb->data, (*skb)->data, length); 1338 else 1339 swap_buffer2(new_skb->data, (*skb)->data, length); 1340 *skb = new_skb; 1341 1342 return true; 1343 } 1344 1345 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1346 * When we update through the ring, if the next incoming buffer has 1347 * not been given to the system, we just set the empty indicator, 1348 * effectively tossing the packet. 1349 */ 1350 static int 1351 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1352 { 1353 struct fec_enet_private *fep = netdev_priv(ndev); 1354 struct fec_enet_priv_rx_q *rxq; 1355 struct bufdesc *bdp; 1356 unsigned short status; 1357 struct sk_buff *skb_new = NULL; 1358 struct sk_buff *skb; 1359 ushort pkt_len; 1360 __u8 *data; 1361 int pkt_received = 0; 1362 struct bufdesc_ex *ebdp = NULL; 1363 bool vlan_packet_rcvd = false; 1364 u16 vlan_tag; 1365 int index = 0; 1366 bool is_copybreak; 1367 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1368 1369 #ifdef CONFIG_M532x 1370 flush_cache_all(); 1371 #endif 1372 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1373 rxq = fep->rx_queue[queue_id]; 1374 1375 /* First, grab all of the stats for the incoming packet. 1376 * These get messed up if we get called due to a busy condition. 1377 */ 1378 bdp = rxq->bd.cur; 1379 1380 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1381 1382 if (pkt_received >= budget) 1383 break; 1384 pkt_received++; 1385 1386 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); 1387 1388 /* Check for errors. */ 1389 status ^= BD_ENET_RX_LAST; 1390 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1391 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1392 BD_ENET_RX_CL)) { 1393 ndev->stats.rx_errors++; 1394 if (status & BD_ENET_RX_OV) { 1395 /* FIFO overrun */ 1396 ndev->stats.rx_fifo_errors++; 1397 goto rx_processing_done; 1398 } 1399 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1400 | BD_ENET_RX_LAST)) { 1401 /* Frame too long or too short. */ 1402 ndev->stats.rx_length_errors++; 1403 if (status & BD_ENET_RX_LAST) 1404 netdev_err(ndev, "rcv is not +last\n"); 1405 } 1406 if (status & BD_ENET_RX_CR) /* CRC Error */ 1407 ndev->stats.rx_crc_errors++; 1408 /* Report late collisions as a frame error. */ 1409 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1410 ndev->stats.rx_frame_errors++; 1411 goto rx_processing_done; 1412 } 1413 1414 /* Process the incoming frame. */ 1415 ndev->stats.rx_packets++; 1416 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1417 ndev->stats.rx_bytes += pkt_len; 1418 1419 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1420 skb = rxq->rx_skbuff[index]; 1421 1422 /* The packet length includes FCS, but we don't want to 1423 * include that when passing upstream as it messes up 1424 * bridging applications. 1425 */ 1426 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1427 need_swap); 1428 if (!is_copybreak) { 1429 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1430 if (unlikely(!skb_new)) { 1431 ndev->stats.rx_dropped++; 1432 goto rx_processing_done; 1433 } 1434 dma_unmap_single(&fep->pdev->dev, 1435 fec32_to_cpu(bdp->cbd_bufaddr), 1436 FEC_ENET_RX_FRSIZE - fep->rx_align, 1437 DMA_FROM_DEVICE); 1438 } 1439 1440 prefetch(skb->data - NET_IP_ALIGN); 1441 skb_put(skb, pkt_len - 4); 1442 data = skb->data; 1443 1444 if (!is_copybreak && need_swap) 1445 swap_buffer(data, pkt_len); 1446 1447 #if !defined(CONFIG_M5272) 1448 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1449 data = skb_pull_inline(skb, 2); 1450 #endif 1451 1452 /* Extract the enhanced buffer descriptor */ 1453 ebdp = NULL; 1454 if (fep->bufdesc_ex) 1455 ebdp = (struct bufdesc_ex *)bdp; 1456 1457 /* If this is a VLAN packet remove the VLAN Tag */ 1458 vlan_packet_rcvd = false; 1459 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1460 fep->bufdesc_ex && 1461 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1462 /* Push and remove the vlan tag */ 1463 struct vlan_hdr *vlan_header = 1464 (struct vlan_hdr *) (data + ETH_HLEN); 1465 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1466 1467 vlan_packet_rcvd = true; 1468 1469 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1470 skb_pull(skb, VLAN_HLEN); 1471 } 1472 1473 skb->protocol = eth_type_trans(skb, ndev); 1474 1475 /* Get receive timestamp from the skb */ 1476 if (fep->hwts_rx_en && fep->bufdesc_ex) 1477 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1478 skb_hwtstamps(skb)); 1479 1480 if (fep->bufdesc_ex && 1481 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1482 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1483 /* don't check it */ 1484 skb->ip_summed = CHECKSUM_UNNECESSARY; 1485 } else { 1486 skb_checksum_none_assert(skb); 1487 } 1488 } 1489 1490 /* Handle received VLAN packets */ 1491 if (vlan_packet_rcvd) 1492 __vlan_hwaccel_put_tag(skb, 1493 htons(ETH_P_8021Q), 1494 vlan_tag); 1495 1496 napi_gro_receive(&fep->napi, skb); 1497 1498 if (is_copybreak) { 1499 dma_sync_single_for_device(&fep->pdev->dev, 1500 fec32_to_cpu(bdp->cbd_bufaddr), 1501 FEC_ENET_RX_FRSIZE - fep->rx_align, 1502 DMA_FROM_DEVICE); 1503 } else { 1504 rxq->rx_skbuff[index] = skb_new; 1505 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1506 } 1507 1508 rx_processing_done: 1509 /* Clear the status flags for this buffer */ 1510 status &= ~BD_ENET_RX_STATS; 1511 1512 /* Mark the buffer empty */ 1513 status |= BD_ENET_RX_EMPTY; 1514 1515 if (fep->bufdesc_ex) { 1516 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1517 1518 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1519 ebdp->cbd_prot = 0; 1520 ebdp->cbd_bdu = 0; 1521 } 1522 /* Make sure the updates to rest of the descriptor are 1523 * performed before transferring ownership. 1524 */ 1525 wmb(); 1526 bdp->cbd_sc = cpu_to_fec16(status); 1527 1528 /* Update BD pointer to next entry */ 1529 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1530 1531 /* Doing this here will keep the FEC running while we process 1532 * incoming frames. On a heavily loaded network, we should be 1533 * able to keep up at the expense of system resources. 1534 */ 1535 writel(0, rxq->bd.reg_desc_active); 1536 } 1537 rxq->bd.cur = bdp; 1538 return pkt_received; 1539 } 1540 1541 static int 1542 fec_enet_rx(struct net_device *ndev, int budget) 1543 { 1544 int pkt_received = 0; 1545 u16 queue_id; 1546 struct fec_enet_private *fep = netdev_priv(ndev); 1547 1548 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) { 1549 int ret; 1550 1551 ret = fec_enet_rx_queue(ndev, 1552 budget - pkt_received, queue_id); 1553 1554 if (ret < budget - pkt_received) 1555 clear_bit(queue_id, &fep->work_rx); 1556 1557 pkt_received += ret; 1558 } 1559 return pkt_received; 1560 } 1561 1562 static bool 1563 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events) 1564 { 1565 if (int_events == 0) 1566 return false; 1567 1568 if (int_events & FEC_ENET_RXF_0) 1569 fep->work_rx |= (1 << 2); 1570 if (int_events & FEC_ENET_RXF_1) 1571 fep->work_rx |= (1 << 0); 1572 if (int_events & FEC_ENET_RXF_2) 1573 fep->work_rx |= (1 << 1); 1574 1575 if (int_events & FEC_ENET_TXF_0) 1576 fep->work_tx |= (1 << 2); 1577 if (int_events & FEC_ENET_TXF_1) 1578 fep->work_tx |= (1 << 0); 1579 if (int_events & FEC_ENET_TXF_2) 1580 fep->work_tx |= (1 << 1); 1581 1582 return true; 1583 } 1584 1585 static irqreturn_t 1586 fec_enet_interrupt(int irq, void *dev_id) 1587 { 1588 struct net_device *ndev = dev_id; 1589 struct fec_enet_private *fep = netdev_priv(ndev); 1590 uint int_events; 1591 irqreturn_t ret = IRQ_NONE; 1592 1593 int_events = readl(fep->hwp + FEC_IEVENT); 1594 writel(int_events, fep->hwp + FEC_IEVENT); 1595 fec_enet_collect_events(fep, int_events); 1596 1597 if ((fep->work_tx || fep->work_rx) && fep->link) { 1598 ret = IRQ_HANDLED; 1599 1600 if (napi_schedule_prep(&fep->napi)) { 1601 /* Disable the NAPI interrupts */ 1602 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK); 1603 __napi_schedule(&fep->napi); 1604 } 1605 } 1606 1607 if (int_events & FEC_ENET_MII) { 1608 ret = IRQ_HANDLED; 1609 complete(&fep->mdio_done); 1610 } 1611 return ret; 1612 } 1613 1614 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1615 { 1616 struct net_device *ndev = napi->dev; 1617 struct fec_enet_private *fep = netdev_priv(ndev); 1618 int pkts; 1619 1620 pkts = fec_enet_rx(ndev, budget); 1621 1622 fec_enet_tx(ndev); 1623 1624 if (pkts < budget) { 1625 napi_complete_done(napi, pkts); 1626 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1627 } 1628 return pkts; 1629 } 1630 1631 /* ------------------------------------------------------------------------- */ 1632 static void fec_get_mac(struct net_device *ndev) 1633 { 1634 struct fec_enet_private *fep = netdev_priv(ndev); 1635 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1636 unsigned char *iap, tmpaddr[ETH_ALEN]; 1637 1638 /* 1639 * try to get mac address in following order: 1640 * 1641 * 1) module parameter via kernel command line in form 1642 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1643 */ 1644 iap = macaddr; 1645 1646 /* 1647 * 2) from device tree data 1648 */ 1649 if (!is_valid_ether_addr(iap)) { 1650 struct device_node *np = fep->pdev->dev.of_node; 1651 if (np) { 1652 const char *mac = of_get_mac_address(np); 1653 if (mac) 1654 iap = (unsigned char *) mac; 1655 } 1656 } 1657 1658 /* 1659 * 3) from flash or fuse (via platform data) 1660 */ 1661 if (!is_valid_ether_addr(iap)) { 1662 #ifdef CONFIG_M5272 1663 if (FEC_FLASHMAC) 1664 iap = (unsigned char *)FEC_FLASHMAC; 1665 #else 1666 if (pdata) 1667 iap = (unsigned char *)&pdata->mac; 1668 #endif 1669 } 1670 1671 /* 1672 * 4) FEC mac registers set by bootloader 1673 */ 1674 if (!is_valid_ether_addr(iap)) { 1675 *((__be32 *) &tmpaddr[0]) = 1676 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1677 *((__be16 *) &tmpaddr[4]) = 1678 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1679 iap = &tmpaddr[0]; 1680 } 1681 1682 /* 1683 * 5) random mac address 1684 */ 1685 if (!is_valid_ether_addr(iap)) { 1686 /* Report it and use a random ethernet address instead */ 1687 netdev_err(ndev, "Invalid MAC address: %pM\n", iap); 1688 eth_hw_addr_random(ndev); 1689 netdev_info(ndev, "Using random MAC address: %pM\n", 1690 ndev->dev_addr); 1691 return; 1692 } 1693 1694 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1695 1696 /* Adjust MAC if using macaddr */ 1697 if (iap == macaddr) 1698 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1699 } 1700 1701 /* ------------------------------------------------------------------------- */ 1702 1703 /* 1704 * Phy section 1705 */ 1706 static void fec_enet_adjust_link(struct net_device *ndev) 1707 { 1708 struct fec_enet_private *fep = netdev_priv(ndev); 1709 struct phy_device *phy_dev = ndev->phydev; 1710 int status_change = 0; 1711 1712 /* Prevent a state halted on mii error */ 1713 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 1714 phy_dev->state = PHY_RESUMING; 1715 return; 1716 } 1717 1718 /* 1719 * If the netdev is down, or is going down, we're not interested 1720 * in link state events, so just mark our idea of the link as down 1721 * and ignore the event. 1722 */ 1723 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1724 fep->link = 0; 1725 } else if (phy_dev->link) { 1726 if (!fep->link) { 1727 fep->link = phy_dev->link; 1728 status_change = 1; 1729 } 1730 1731 if (fep->full_duplex != phy_dev->duplex) { 1732 fep->full_duplex = phy_dev->duplex; 1733 status_change = 1; 1734 } 1735 1736 if (phy_dev->speed != fep->speed) { 1737 fep->speed = phy_dev->speed; 1738 status_change = 1; 1739 } 1740 1741 /* if any of the above changed restart the FEC */ 1742 if (status_change) { 1743 napi_disable(&fep->napi); 1744 netif_tx_lock_bh(ndev); 1745 fec_restart(ndev); 1746 netif_wake_queue(ndev); 1747 netif_tx_unlock_bh(ndev); 1748 napi_enable(&fep->napi); 1749 } 1750 } else { 1751 if (fep->link) { 1752 napi_disable(&fep->napi); 1753 netif_tx_lock_bh(ndev); 1754 fec_stop(ndev); 1755 netif_tx_unlock_bh(ndev); 1756 napi_enable(&fep->napi); 1757 fep->link = phy_dev->link; 1758 status_change = 1; 1759 } 1760 } 1761 1762 if (status_change) 1763 phy_print_status(phy_dev); 1764 } 1765 1766 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1767 { 1768 struct fec_enet_private *fep = bus->priv; 1769 struct device *dev = &fep->pdev->dev; 1770 unsigned long time_left; 1771 int ret = 0; 1772 1773 ret = pm_runtime_get_sync(dev); 1774 if (ret < 0) 1775 return ret; 1776 1777 fep->mii_timeout = 0; 1778 reinit_completion(&fep->mdio_done); 1779 1780 /* start a read op */ 1781 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 1782 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1783 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1784 1785 /* wait for end of transfer */ 1786 time_left = wait_for_completion_timeout(&fep->mdio_done, 1787 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1788 if (time_left == 0) { 1789 fep->mii_timeout = 1; 1790 netdev_err(fep->netdev, "MDIO read timeout\n"); 1791 ret = -ETIMEDOUT; 1792 goto out; 1793 } 1794 1795 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1796 1797 out: 1798 pm_runtime_mark_last_busy(dev); 1799 pm_runtime_put_autosuspend(dev); 1800 1801 return ret; 1802 } 1803 1804 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1805 u16 value) 1806 { 1807 struct fec_enet_private *fep = bus->priv; 1808 struct device *dev = &fep->pdev->dev; 1809 unsigned long time_left; 1810 int ret; 1811 1812 ret = pm_runtime_get_sync(dev); 1813 if (ret < 0) 1814 return ret; 1815 else 1816 ret = 0; 1817 1818 fep->mii_timeout = 0; 1819 reinit_completion(&fep->mdio_done); 1820 1821 /* start a write op */ 1822 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 1823 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1824 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1825 fep->hwp + FEC_MII_DATA); 1826 1827 /* wait for end of transfer */ 1828 time_left = wait_for_completion_timeout(&fep->mdio_done, 1829 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1830 if (time_left == 0) { 1831 fep->mii_timeout = 1; 1832 netdev_err(fep->netdev, "MDIO write timeout\n"); 1833 ret = -ETIMEDOUT; 1834 } 1835 1836 pm_runtime_mark_last_busy(dev); 1837 pm_runtime_put_autosuspend(dev); 1838 1839 return ret; 1840 } 1841 1842 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1843 { 1844 struct fec_enet_private *fep = netdev_priv(ndev); 1845 int ret; 1846 1847 if (enable) { 1848 ret = clk_prepare_enable(fep->clk_ahb); 1849 if (ret) 1850 return ret; 1851 1852 ret = clk_prepare_enable(fep->clk_enet_out); 1853 if (ret) 1854 goto failed_clk_enet_out; 1855 1856 if (fep->clk_ptp) { 1857 mutex_lock(&fep->ptp_clk_mutex); 1858 ret = clk_prepare_enable(fep->clk_ptp); 1859 if (ret) { 1860 mutex_unlock(&fep->ptp_clk_mutex); 1861 goto failed_clk_ptp; 1862 } else { 1863 fep->ptp_clk_on = true; 1864 } 1865 mutex_unlock(&fep->ptp_clk_mutex); 1866 } 1867 1868 ret = clk_prepare_enable(fep->clk_ref); 1869 if (ret) 1870 goto failed_clk_ref; 1871 1872 phy_reset_after_clk_enable(ndev->phydev); 1873 } else { 1874 clk_disable_unprepare(fep->clk_ahb); 1875 clk_disable_unprepare(fep->clk_enet_out); 1876 if (fep->clk_ptp) { 1877 mutex_lock(&fep->ptp_clk_mutex); 1878 clk_disable_unprepare(fep->clk_ptp); 1879 fep->ptp_clk_on = false; 1880 mutex_unlock(&fep->ptp_clk_mutex); 1881 } 1882 clk_disable_unprepare(fep->clk_ref); 1883 } 1884 1885 return 0; 1886 1887 failed_clk_ref: 1888 if (fep->clk_ref) 1889 clk_disable_unprepare(fep->clk_ref); 1890 failed_clk_ptp: 1891 if (fep->clk_enet_out) 1892 clk_disable_unprepare(fep->clk_enet_out); 1893 failed_clk_enet_out: 1894 clk_disable_unprepare(fep->clk_ahb); 1895 1896 return ret; 1897 } 1898 1899 static int fec_enet_mii_probe(struct net_device *ndev) 1900 { 1901 struct fec_enet_private *fep = netdev_priv(ndev); 1902 struct phy_device *phy_dev = NULL; 1903 char mdio_bus_id[MII_BUS_ID_SIZE]; 1904 char phy_name[MII_BUS_ID_SIZE + 3]; 1905 int phy_id; 1906 int dev_id = fep->dev_id; 1907 1908 if (fep->phy_node) { 1909 phy_dev = of_phy_connect(ndev, fep->phy_node, 1910 &fec_enet_adjust_link, 0, 1911 fep->phy_interface); 1912 if (!phy_dev) { 1913 netdev_err(ndev, "Unable to connect to phy\n"); 1914 return -ENODEV; 1915 } 1916 } else { 1917 /* check for attached phy */ 1918 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1919 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 1920 continue; 1921 if (dev_id--) 1922 continue; 1923 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1924 break; 1925 } 1926 1927 if (phy_id >= PHY_MAX_ADDR) { 1928 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1929 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 1930 phy_id = 0; 1931 } 1932 1933 snprintf(phy_name, sizeof(phy_name), 1934 PHY_ID_FMT, mdio_bus_id, phy_id); 1935 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 1936 fep->phy_interface); 1937 } 1938 1939 if (IS_ERR(phy_dev)) { 1940 netdev_err(ndev, "could not attach to PHY\n"); 1941 return PTR_ERR(phy_dev); 1942 } 1943 1944 /* mask with MAC supported features */ 1945 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 1946 phy_dev->supported &= PHY_GBIT_FEATURES; 1947 phy_dev->supported &= ~SUPPORTED_1000baseT_Half; 1948 #if !defined(CONFIG_M5272) 1949 phy_dev->supported |= SUPPORTED_Pause; 1950 #endif 1951 } 1952 else 1953 phy_dev->supported &= PHY_BASIC_FEATURES; 1954 1955 phy_dev->advertising = phy_dev->supported; 1956 1957 fep->link = 0; 1958 fep->full_duplex = 0; 1959 1960 phy_attached_info(phy_dev); 1961 1962 return 0; 1963 } 1964 1965 static int fec_enet_mii_init(struct platform_device *pdev) 1966 { 1967 static struct mii_bus *fec0_mii_bus; 1968 struct net_device *ndev = platform_get_drvdata(pdev); 1969 struct fec_enet_private *fep = netdev_priv(ndev); 1970 struct device_node *node; 1971 int err = -ENXIO; 1972 u32 mii_speed, holdtime; 1973 1974 /* 1975 * The i.MX28 dual fec interfaces are not equal. 1976 * Here are the differences: 1977 * 1978 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1979 * - fec0 acts as the 1588 time master while fec1 is slave 1980 * - external phys can only be configured by fec0 1981 * 1982 * That is to say fec1 can not work independently. It only works 1983 * when fec0 is working. The reason behind this design is that the 1984 * second interface is added primarily for Switch mode. 1985 * 1986 * Because of the last point above, both phys are attached on fec0 1987 * mdio interface in board design, and need to be configured by 1988 * fec0 mii_bus. 1989 */ 1990 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 1991 /* fec1 uses fec0 mii_bus */ 1992 if (mii_cnt && fec0_mii_bus) { 1993 fep->mii_bus = fec0_mii_bus; 1994 mii_cnt++; 1995 return 0; 1996 } 1997 return -ENOENT; 1998 } 1999 2000 fep->mii_timeout = 0; 2001 2002 /* 2003 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 2004 * 2005 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2006 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2007 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2008 * document. 2009 */ 2010 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000); 2011 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2012 mii_speed--; 2013 if (mii_speed > 63) { 2014 dev_err(&pdev->dev, 2015 "fec clock (%lu) too fast to get right mii speed\n", 2016 clk_get_rate(fep->clk_ipg)); 2017 err = -EINVAL; 2018 goto err_out; 2019 } 2020 2021 /* 2022 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2023 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2024 * versions are RAZ there, so just ignore the difference and write the 2025 * register always. 2026 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2027 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2028 * output. 2029 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2030 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2031 * holdtime cannot result in a value greater than 3. 2032 */ 2033 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2034 2035 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2036 2037 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2038 2039 fep->mii_bus = mdiobus_alloc(); 2040 if (fep->mii_bus == NULL) { 2041 err = -ENOMEM; 2042 goto err_out; 2043 } 2044 2045 fep->mii_bus->name = "fec_enet_mii_bus"; 2046 fep->mii_bus->read = fec_enet_mdio_read; 2047 fep->mii_bus->write = fec_enet_mdio_write; 2048 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2049 pdev->name, fep->dev_id + 1); 2050 fep->mii_bus->priv = fep; 2051 fep->mii_bus->parent = &pdev->dev; 2052 2053 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2054 if (node) { 2055 err = of_mdiobus_register(fep->mii_bus, node); 2056 of_node_put(node); 2057 } else { 2058 err = mdiobus_register(fep->mii_bus); 2059 } 2060 2061 if (err) 2062 goto err_out_free_mdiobus; 2063 2064 mii_cnt++; 2065 2066 /* save fec0 mii_bus */ 2067 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2068 fec0_mii_bus = fep->mii_bus; 2069 2070 return 0; 2071 2072 err_out_free_mdiobus: 2073 mdiobus_free(fep->mii_bus); 2074 err_out: 2075 return err; 2076 } 2077 2078 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2079 { 2080 if (--mii_cnt == 0) { 2081 mdiobus_unregister(fep->mii_bus); 2082 mdiobus_free(fep->mii_bus); 2083 } 2084 } 2085 2086 static void fec_enet_get_drvinfo(struct net_device *ndev, 2087 struct ethtool_drvinfo *info) 2088 { 2089 struct fec_enet_private *fep = netdev_priv(ndev); 2090 2091 strlcpy(info->driver, fep->pdev->dev.driver->name, 2092 sizeof(info->driver)); 2093 strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); 2094 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2095 } 2096 2097 static int fec_enet_get_regs_len(struct net_device *ndev) 2098 { 2099 struct fec_enet_private *fep = netdev_priv(ndev); 2100 struct resource *r; 2101 int s = 0; 2102 2103 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2104 if (r) 2105 s = resource_size(r); 2106 2107 return s; 2108 } 2109 2110 /* List of registers that can be safety be read to dump them with ethtool */ 2111 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2112 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 2113 static u32 fec_enet_register_offset[] = { 2114 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2115 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2116 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2117 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2118 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2119 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2120 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2121 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2122 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2123 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2124 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2125 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2126 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2127 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2128 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2129 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2130 RMON_T_P_GTE2048, RMON_T_OCTETS, 2131 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2132 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2133 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2134 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2135 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2136 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2137 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2138 RMON_R_P_GTE2048, RMON_R_OCTETS, 2139 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2140 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2141 }; 2142 #else 2143 static u32 fec_enet_register_offset[] = { 2144 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2145 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2146 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2147 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2148 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2149 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2150 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2151 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2152 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2153 }; 2154 #endif 2155 2156 static void fec_enet_get_regs(struct net_device *ndev, 2157 struct ethtool_regs *regs, void *regbuf) 2158 { 2159 struct fec_enet_private *fep = netdev_priv(ndev); 2160 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2161 u32 *buf = (u32 *)regbuf; 2162 u32 i, off; 2163 2164 memset(buf, 0, regs->len); 2165 2166 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2167 off = fec_enet_register_offset[i] / 4; 2168 buf[off] = readl(&theregs[off]); 2169 } 2170 } 2171 2172 static int fec_enet_get_ts_info(struct net_device *ndev, 2173 struct ethtool_ts_info *info) 2174 { 2175 struct fec_enet_private *fep = netdev_priv(ndev); 2176 2177 if (fep->bufdesc_ex) { 2178 2179 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2180 SOF_TIMESTAMPING_RX_SOFTWARE | 2181 SOF_TIMESTAMPING_SOFTWARE | 2182 SOF_TIMESTAMPING_TX_HARDWARE | 2183 SOF_TIMESTAMPING_RX_HARDWARE | 2184 SOF_TIMESTAMPING_RAW_HARDWARE; 2185 if (fep->ptp_clock) 2186 info->phc_index = ptp_clock_index(fep->ptp_clock); 2187 else 2188 info->phc_index = -1; 2189 2190 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2191 (1 << HWTSTAMP_TX_ON); 2192 2193 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2194 (1 << HWTSTAMP_FILTER_ALL); 2195 return 0; 2196 } else { 2197 return ethtool_op_get_ts_info(ndev, info); 2198 } 2199 } 2200 2201 #if !defined(CONFIG_M5272) 2202 2203 static void fec_enet_get_pauseparam(struct net_device *ndev, 2204 struct ethtool_pauseparam *pause) 2205 { 2206 struct fec_enet_private *fep = netdev_priv(ndev); 2207 2208 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2209 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2210 pause->rx_pause = pause->tx_pause; 2211 } 2212 2213 static int fec_enet_set_pauseparam(struct net_device *ndev, 2214 struct ethtool_pauseparam *pause) 2215 { 2216 struct fec_enet_private *fep = netdev_priv(ndev); 2217 2218 if (!ndev->phydev) 2219 return -ENODEV; 2220 2221 if (pause->tx_pause != pause->rx_pause) { 2222 netdev_info(ndev, 2223 "hardware only support enable/disable both tx and rx"); 2224 return -EINVAL; 2225 } 2226 2227 fep->pause_flag = 0; 2228 2229 /* tx pause must be same as rx pause */ 2230 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2231 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2232 2233 if (pause->rx_pause || pause->autoneg) { 2234 ndev->phydev->supported |= ADVERTISED_Pause; 2235 ndev->phydev->advertising |= ADVERTISED_Pause; 2236 } else { 2237 ndev->phydev->supported &= ~ADVERTISED_Pause; 2238 ndev->phydev->advertising &= ~ADVERTISED_Pause; 2239 } 2240 2241 if (pause->autoneg) { 2242 if (netif_running(ndev)) 2243 fec_stop(ndev); 2244 phy_start_aneg(ndev->phydev); 2245 } 2246 if (netif_running(ndev)) { 2247 napi_disable(&fep->napi); 2248 netif_tx_lock_bh(ndev); 2249 fec_restart(ndev); 2250 netif_wake_queue(ndev); 2251 netif_tx_unlock_bh(ndev); 2252 napi_enable(&fep->napi); 2253 } 2254 2255 return 0; 2256 } 2257 2258 static const struct fec_stat { 2259 char name[ETH_GSTRING_LEN]; 2260 u16 offset; 2261 } fec_stats[] = { 2262 /* RMON TX */ 2263 { "tx_dropped", RMON_T_DROP }, 2264 { "tx_packets", RMON_T_PACKETS }, 2265 { "tx_broadcast", RMON_T_BC_PKT }, 2266 { "tx_multicast", RMON_T_MC_PKT }, 2267 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2268 { "tx_undersize", RMON_T_UNDERSIZE }, 2269 { "tx_oversize", RMON_T_OVERSIZE }, 2270 { "tx_fragment", RMON_T_FRAG }, 2271 { "tx_jabber", RMON_T_JAB }, 2272 { "tx_collision", RMON_T_COL }, 2273 { "tx_64byte", RMON_T_P64 }, 2274 { "tx_65to127byte", RMON_T_P65TO127 }, 2275 { "tx_128to255byte", RMON_T_P128TO255 }, 2276 { "tx_256to511byte", RMON_T_P256TO511 }, 2277 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2278 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2279 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2280 { "tx_octets", RMON_T_OCTETS }, 2281 2282 /* IEEE TX */ 2283 { "IEEE_tx_drop", IEEE_T_DROP }, 2284 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2285 { "IEEE_tx_1col", IEEE_T_1COL }, 2286 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2287 { "IEEE_tx_def", IEEE_T_DEF }, 2288 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2289 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2290 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2291 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2292 { "IEEE_tx_sqe", IEEE_T_SQE }, 2293 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2294 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2295 2296 /* RMON RX */ 2297 { "rx_packets", RMON_R_PACKETS }, 2298 { "rx_broadcast", RMON_R_BC_PKT }, 2299 { "rx_multicast", RMON_R_MC_PKT }, 2300 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2301 { "rx_undersize", RMON_R_UNDERSIZE }, 2302 { "rx_oversize", RMON_R_OVERSIZE }, 2303 { "rx_fragment", RMON_R_FRAG }, 2304 { "rx_jabber", RMON_R_JAB }, 2305 { "rx_64byte", RMON_R_P64 }, 2306 { "rx_65to127byte", RMON_R_P65TO127 }, 2307 { "rx_128to255byte", RMON_R_P128TO255 }, 2308 { "rx_256to511byte", RMON_R_P256TO511 }, 2309 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2310 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2311 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2312 { "rx_octets", RMON_R_OCTETS }, 2313 2314 /* IEEE RX */ 2315 { "IEEE_rx_drop", IEEE_R_DROP }, 2316 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2317 { "IEEE_rx_crc", IEEE_R_CRC }, 2318 { "IEEE_rx_align", IEEE_R_ALIGN }, 2319 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2320 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2321 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2322 }; 2323 2324 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2325 2326 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2327 { 2328 struct fec_enet_private *fep = netdev_priv(dev); 2329 int i; 2330 2331 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2332 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2333 } 2334 2335 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2336 struct ethtool_stats *stats, u64 *data) 2337 { 2338 struct fec_enet_private *fep = netdev_priv(dev); 2339 2340 if (netif_running(dev)) 2341 fec_enet_update_ethtool_stats(dev); 2342 2343 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2344 } 2345 2346 static void fec_enet_get_strings(struct net_device *netdev, 2347 u32 stringset, u8 *data) 2348 { 2349 int i; 2350 switch (stringset) { 2351 case ETH_SS_STATS: 2352 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2353 memcpy(data + i * ETH_GSTRING_LEN, 2354 fec_stats[i].name, ETH_GSTRING_LEN); 2355 break; 2356 } 2357 } 2358 2359 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2360 { 2361 switch (sset) { 2362 case ETH_SS_STATS: 2363 return ARRAY_SIZE(fec_stats); 2364 default: 2365 return -EOPNOTSUPP; 2366 } 2367 } 2368 2369 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2370 { 2371 struct fec_enet_private *fep = netdev_priv(dev); 2372 int i; 2373 2374 /* Disable MIB statistics counters */ 2375 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2376 2377 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2378 writel(0, fep->hwp + fec_stats[i].offset); 2379 2380 /* Don't disable MIB statistics counters */ 2381 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2382 } 2383 2384 #else /* !defined(CONFIG_M5272) */ 2385 #define FEC_STATS_SIZE 0 2386 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2387 { 2388 } 2389 2390 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2391 { 2392 } 2393 #endif /* !defined(CONFIG_M5272) */ 2394 2395 /* ITR clock source is enet system clock (clk_ahb). 2396 * TCTT unit is cycle_ns * 64 cycle 2397 * So, the ICTT value = X us / (cycle_ns * 64) 2398 */ 2399 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2400 { 2401 struct fec_enet_private *fep = netdev_priv(ndev); 2402 2403 return us * (fep->itr_clk_rate / 64000) / 1000; 2404 } 2405 2406 /* Set threshold for interrupt coalescing */ 2407 static void fec_enet_itr_coal_set(struct net_device *ndev) 2408 { 2409 struct fec_enet_private *fep = netdev_priv(ndev); 2410 int rx_itr, tx_itr; 2411 2412 /* Must be greater than zero to avoid unpredictable behavior */ 2413 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2414 !fep->tx_time_itr || !fep->tx_pkts_itr) 2415 return; 2416 2417 /* Select enet system clock as Interrupt Coalescing 2418 * timer Clock Source 2419 */ 2420 rx_itr = FEC_ITR_CLK_SEL; 2421 tx_itr = FEC_ITR_CLK_SEL; 2422 2423 /* set ICFT and ICTT */ 2424 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2425 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2426 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2427 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2428 2429 rx_itr |= FEC_ITR_EN; 2430 tx_itr |= FEC_ITR_EN; 2431 2432 writel(tx_itr, fep->hwp + FEC_TXIC0); 2433 writel(rx_itr, fep->hwp + FEC_RXIC0); 2434 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 2435 writel(tx_itr, fep->hwp + FEC_TXIC1); 2436 writel(rx_itr, fep->hwp + FEC_RXIC1); 2437 writel(tx_itr, fep->hwp + FEC_TXIC2); 2438 writel(rx_itr, fep->hwp + FEC_RXIC2); 2439 } 2440 } 2441 2442 static int 2443 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2444 { 2445 struct fec_enet_private *fep = netdev_priv(ndev); 2446 2447 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2448 return -EOPNOTSUPP; 2449 2450 ec->rx_coalesce_usecs = fep->rx_time_itr; 2451 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2452 2453 ec->tx_coalesce_usecs = fep->tx_time_itr; 2454 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2455 2456 return 0; 2457 } 2458 2459 static int 2460 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2461 { 2462 struct fec_enet_private *fep = netdev_priv(ndev); 2463 unsigned int cycle; 2464 2465 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2466 return -EOPNOTSUPP; 2467 2468 if (ec->rx_max_coalesced_frames > 255) { 2469 pr_err("Rx coalesced frames exceed hardware limitation\n"); 2470 return -EINVAL; 2471 } 2472 2473 if (ec->tx_max_coalesced_frames > 255) { 2474 pr_err("Tx coalesced frame exceed hardware limitation\n"); 2475 return -EINVAL; 2476 } 2477 2478 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); 2479 if (cycle > 0xFFFF) { 2480 pr_err("Rx coalesced usec exceed hardware limitation\n"); 2481 return -EINVAL; 2482 } 2483 2484 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); 2485 if (cycle > 0xFFFF) { 2486 pr_err("Rx coalesced usec exceed hardware limitation\n"); 2487 return -EINVAL; 2488 } 2489 2490 fep->rx_time_itr = ec->rx_coalesce_usecs; 2491 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2492 2493 fep->tx_time_itr = ec->tx_coalesce_usecs; 2494 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2495 2496 fec_enet_itr_coal_set(ndev); 2497 2498 return 0; 2499 } 2500 2501 static void fec_enet_itr_coal_init(struct net_device *ndev) 2502 { 2503 struct ethtool_coalesce ec; 2504 2505 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2506 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2507 2508 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2509 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2510 2511 fec_enet_set_coalesce(ndev, &ec); 2512 } 2513 2514 static int fec_enet_get_tunable(struct net_device *netdev, 2515 const struct ethtool_tunable *tuna, 2516 void *data) 2517 { 2518 struct fec_enet_private *fep = netdev_priv(netdev); 2519 int ret = 0; 2520 2521 switch (tuna->id) { 2522 case ETHTOOL_RX_COPYBREAK: 2523 *(u32 *)data = fep->rx_copybreak; 2524 break; 2525 default: 2526 ret = -EINVAL; 2527 break; 2528 } 2529 2530 return ret; 2531 } 2532 2533 static int fec_enet_set_tunable(struct net_device *netdev, 2534 const struct ethtool_tunable *tuna, 2535 const void *data) 2536 { 2537 struct fec_enet_private *fep = netdev_priv(netdev); 2538 int ret = 0; 2539 2540 switch (tuna->id) { 2541 case ETHTOOL_RX_COPYBREAK: 2542 fep->rx_copybreak = *(u32 *)data; 2543 break; 2544 default: 2545 ret = -EINVAL; 2546 break; 2547 } 2548 2549 return ret; 2550 } 2551 2552 static void 2553 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2554 { 2555 struct fec_enet_private *fep = netdev_priv(ndev); 2556 2557 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2558 wol->supported = WAKE_MAGIC; 2559 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2560 } else { 2561 wol->supported = wol->wolopts = 0; 2562 } 2563 } 2564 2565 static int 2566 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2567 { 2568 struct fec_enet_private *fep = netdev_priv(ndev); 2569 2570 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2571 return -EINVAL; 2572 2573 if (wol->wolopts & ~WAKE_MAGIC) 2574 return -EINVAL; 2575 2576 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2577 if (device_may_wakeup(&ndev->dev)) { 2578 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2579 if (fep->irq[0] > 0) 2580 enable_irq_wake(fep->irq[0]); 2581 } else { 2582 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2583 if (fep->irq[0] > 0) 2584 disable_irq_wake(fep->irq[0]); 2585 } 2586 2587 return 0; 2588 } 2589 2590 static const struct ethtool_ops fec_enet_ethtool_ops = { 2591 .get_drvinfo = fec_enet_get_drvinfo, 2592 .get_regs_len = fec_enet_get_regs_len, 2593 .get_regs = fec_enet_get_regs, 2594 .nway_reset = phy_ethtool_nway_reset, 2595 .get_link = ethtool_op_get_link, 2596 .get_coalesce = fec_enet_get_coalesce, 2597 .set_coalesce = fec_enet_set_coalesce, 2598 #ifndef CONFIG_M5272 2599 .get_pauseparam = fec_enet_get_pauseparam, 2600 .set_pauseparam = fec_enet_set_pauseparam, 2601 .get_strings = fec_enet_get_strings, 2602 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2603 .get_sset_count = fec_enet_get_sset_count, 2604 #endif 2605 .get_ts_info = fec_enet_get_ts_info, 2606 .get_tunable = fec_enet_get_tunable, 2607 .set_tunable = fec_enet_set_tunable, 2608 .get_wol = fec_enet_get_wol, 2609 .set_wol = fec_enet_set_wol, 2610 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2611 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2612 }; 2613 2614 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2615 { 2616 struct fec_enet_private *fep = netdev_priv(ndev); 2617 struct phy_device *phydev = ndev->phydev; 2618 2619 if (!netif_running(ndev)) 2620 return -EINVAL; 2621 2622 if (!phydev) 2623 return -ENODEV; 2624 2625 if (fep->bufdesc_ex) { 2626 if (cmd == SIOCSHWTSTAMP) 2627 return fec_ptp_set(ndev, rq); 2628 if (cmd == SIOCGHWTSTAMP) 2629 return fec_ptp_get(ndev, rq); 2630 } 2631 2632 return phy_mii_ioctl(phydev, rq, cmd); 2633 } 2634 2635 static void fec_enet_free_buffers(struct net_device *ndev) 2636 { 2637 struct fec_enet_private *fep = netdev_priv(ndev); 2638 unsigned int i; 2639 struct sk_buff *skb; 2640 struct bufdesc *bdp; 2641 struct fec_enet_priv_tx_q *txq; 2642 struct fec_enet_priv_rx_q *rxq; 2643 unsigned int q; 2644 2645 for (q = 0; q < fep->num_rx_queues; q++) { 2646 rxq = fep->rx_queue[q]; 2647 bdp = rxq->bd.base; 2648 for (i = 0; i < rxq->bd.ring_size; i++) { 2649 skb = rxq->rx_skbuff[i]; 2650 rxq->rx_skbuff[i] = NULL; 2651 if (skb) { 2652 dma_unmap_single(&fep->pdev->dev, 2653 fec32_to_cpu(bdp->cbd_bufaddr), 2654 FEC_ENET_RX_FRSIZE - fep->rx_align, 2655 DMA_FROM_DEVICE); 2656 dev_kfree_skb(skb); 2657 } 2658 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2659 } 2660 } 2661 2662 for (q = 0; q < fep->num_tx_queues; q++) { 2663 txq = fep->tx_queue[q]; 2664 bdp = txq->bd.base; 2665 for (i = 0; i < txq->bd.ring_size; i++) { 2666 kfree(txq->tx_bounce[i]); 2667 txq->tx_bounce[i] = NULL; 2668 skb = txq->tx_skbuff[i]; 2669 txq->tx_skbuff[i] = NULL; 2670 dev_kfree_skb(skb); 2671 } 2672 } 2673 } 2674 2675 static void fec_enet_free_queue(struct net_device *ndev) 2676 { 2677 struct fec_enet_private *fep = netdev_priv(ndev); 2678 int i; 2679 struct fec_enet_priv_tx_q *txq; 2680 2681 for (i = 0; i < fep->num_tx_queues; i++) 2682 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2683 txq = fep->tx_queue[i]; 2684 dma_free_coherent(&fep->pdev->dev, 2685 txq->bd.ring_size * TSO_HEADER_SIZE, 2686 txq->tso_hdrs, 2687 txq->tso_hdrs_dma); 2688 } 2689 2690 for (i = 0; i < fep->num_rx_queues; i++) 2691 kfree(fep->rx_queue[i]); 2692 for (i = 0; i < fep->num_tx_queues; i++) 2693 kfree(fep->tx_queue[i]); 2694 } 2695 2696 static int fec_enet_alloc_queue(struct net_device *ndev) 2697 { 2698 struct fec_enet_private *fep = netdev_priv(ndev); 2699 int i; 2700 int ret = 0; 2701 struct fec_enet_priv_tx_q *txq; 2702 2703 for (i = 0; i < fep->num_tx_queues; i++) { 2704 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 2705 if (!txq) { 2706 ret = -ENOMEM; 2707 goto alloc_failed; 2708 } 2709 2710 fep->tx_queue[i] = txq; 2711 txq->bd.ring_size = TX_RING_SIZE; 2712 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 2713 2714 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2715 txq->tx_wake_threshold = 2716 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 2717 2718 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 2719 txq->bd.ring_size * TSO_HEADER_SIZE, 2720 &txq->tso_hdrs_dma, 2721 GFP_KERNEL); 2722 if (!txq->tso_hdrs) { 2723 ret = -ENOMEM; 2724 goto alloc_failed; 2725 } 2726 } 2727 2728 for (i = 0; i < fep->num_rx_queues; i++) { 2729 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 2730 GFP_KERNEL); 2731 if (!fep->rx_queue[i]) { 2732 ret = -ENOMEM; 2733 goto alloc_failed; 2734 } 2735 2736 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 2737 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 2738 } 2739 return ret; 2740 2741 alloc_failed: 2742 fec_enet_free_queue(ndev); 2743 return ret; 2744 } 2745 2746 static int 2747 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 2748 { 2749 struct fec_enet_private *fep = netdev_priv(ndev); 2750 unsigned int i; 2751 struct sk_buff *skb; 2752 struct bufdesc *bdp; 2753 struct fec_enet_priv_rx_q *rxq; 2754 2755 rxq = fep->rx_queue[queue]; 2756 bdp = rxq->bd.base; 2757 for (i = 0; i < rxq->bd.ring_size; i++) { 2758 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2759 if (!skb) 2760 goto err_alloc; 2761 2762 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 2763 dev_kfree_skb(skb); 2764 goto err_alloc; 2765 } 2766 2767 rxq->rx_skbuff[i] = skb; 2768 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 2769 2770 if (fep->bufdesc_ex) { 2771 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2772 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 2773 } 2774 2775 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2776 } 2777 2778 /* Set the last buffer to wrap. */ 2779 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 2780 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2781 return 0; 2782 2783 err_alloc: 2784 fec_enet_free_buffers(ndev); 2785 return -ENOMEM; 2786 } 2787 2788 static int 2789 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 2790 { 2791 struct fec_enet_private *fep = netdev_priv(ndev); 2792 unsigned int i; 2793 struct bufdesc *bdp; 2794 struct fec_enet_priv_tx_q *txq; 2795 2796 txq = fep->tx_queue[queue]; 2797 bdp = txq->bd.base; 2798 for (i = 0; i < txq->bd.ring_size; i++) { 2799 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2800 if (!txq->tx_bounce[i]) 2801 goto err_alloc; 2802 2803 bdp->cbd_sc = cpu_to_fec16(0); 2804 bdp->cbd_bufaddr = cpu_to_fec32(0); 2805 2806 if (fep->bufdesc_ex) { 2807 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2808 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 2809 } 2810 2811 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 2812 } 2813 2814 /* Set the last buffer to wrap. */ 2815 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 2816 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2817 2818 return 0; 2819 2820 err_alloc: 2821 fec_enet_free_buffers(ndev); 2822 return -ENOMEM; 2823 } 2824 2825 static int fec_enet_alloc_buffers(struct net_device *ndev) 2826 { 2827 struct fec_enet_private *fep = netdev_priv(ndev); 2828 unsigned int i; 2829 2830 for (i = 0; i < fep->num_rx_queues; i++) 2831 if (fec_enet_alloc_rxq_buffers(ndev, i)) 2832 return -ENOMEM; 2833 2834 for (i = 0; i < fep->num_tx_queues; i++) 2835 if (fec_enet_alloc_txq_buffers(ndev, i)) 2836 return -ENOMEM; 2837 return 0; 2838 } 2839 2840 static int 2841 fec_enet_open(struct net_device *ndev) 2842 { 2843 struct fec_enet_private *fep = netdev_priv(ndev); 2844 int ret; 2845 bool reset_again; 2846 2847 ret = pm_runtime_get_sync(&fep->pdev->dev); 2848 if (ret < 0) 2849 return ret; 2850 2851 pinctrl_pm_select_default_state(&fep->pdev->dev); 2852 ret = fec_enet_clk_enable(ndev, true); 2853 if (ret) 2854 goto clk_enable; 2855 2856 /* During the first fec_enet_open call the PHY isn't probed at this 2857 * point. Therefore the phy_reset_after_clk_enable() call within 2858 * fec_enet_clk_enable() fails. As we need this reset in order to be 2859 * sure the PHY is working correctly we check if we need to reset again 2860 * later when the PHY is probed 2861 */ 2862 if (ndev->phydev && ndev->phydev->drv) 2863 reset_again = false; 2864 else 2865 reset_again = true; 2866 2867 /* I should reset the ring buffers here, but I don't yet know 2868 * a simple way to do that. 2869 */ 2870 2871 ret = fec_enet_alloc_buffers(ndev); 2872 if (ret) 2873 goto err_enet_alloc; 2874 2875 /* Init MAC prior to mii bus probe */ 2876 fec_restart(ndev); 2877 2878 /* Probe and connect to PHY when open the interface */ 2879 ret = fec_enet_mii_probe(ndev); 2880 if (ret) 2881 goto err_enet_mii_probe; 2882 2883 /* Call phy_reset_after_clk_enable() again if it failed during 2884 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 2885 */ 2886 if (reset_again) 2887 phy_reset_after_clk_enable(ndev->phydev); 2888 2889 if (fep->quirks & FEC_QUIRK_ERR006687) 2890 imx6q_cpuidle_fec_irqs_used(); 2891 2892 napi_enable(&fep->napi); 2893 phy_start(ndev->phydev); 2894 netif_tx_start_all_queues(ndev); 2895 2896 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 2897 FEC_WOL_FLAG_ENABLE); 2898 2899 return 0; 2900 2901 err_enet_mii_probe: 2902 fec_enet_free_buffers(ndev); 2903 err_enet_alloc: 2904 fec_enet_clk_enable(ndev, false); 2905 clk_enable: 2906 pm_runtime_mark_last_busy(&fep->pdev->dev); 2907 pm_runtime_put_autosuspend(&fep->pdev->dev); 2908 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2909 return ret; 2910 } 2911 2912 static int 2913 fec_enet_close(struct net_device *ndev) 2914 { 2915 struct fec_enet_private *fep = netdev_priv(ndev); 2916 2917 phy_stop(ndev->phydev); 2918 2919 if (netif_device_present(ndev)) { 2920 napi_disable(&fep->napi); 2921 netif_tx_disable(ndev); 2922 fec_stop(ndev); 2923 } 2924 2925 phy_disconnect(ndev->phydev); 2926 2927 if (fep->quirks & FEC_QUIRK_ERR006687) 2928 imx6q_cpuidle_fec_irqs_unused(); 2929 2930 fec_enet_update_ethtool_stats(ndev); 2931 2932 fec_enet_clk_enable(ndev, false); 2933 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2934 pm_runtime_mark_last_busy(&fep->pdev->dev); 2935 pm_runtime_put_autosuspend(&fep->pdev->dev); 2936 2937 fec_enet_free_buffers(ndev); 2938 2939 return 0; 2940 } 2941 2942 /* Set or clear the multicast filter for this adaptor. 2943 * Skeleton taken from sunlance driver. 2944 * The CPM Ethernet implementation allows Multicast as well as individual 2945 * MAC address filtering. Some of the drivers check to make sure it is 2946 * a group multicast address, and discard those that are not. I guess I 2947 * will do the same for now, but just remove the test if you want 2948 * individual filtering as well (do the upper net layers want or support 2949 * this kind of feature?). 2950 */ 2951 2952 #define FEC_HASH_BITS 6 /* #bits in hash */ 2953 #define CRC32_POLY 0xEDB88320 2954 2955 static void set_multicast_list(struct net_device *ndev) 2956 { 2957 struct fec_enet_private *fep = netdev_priv(ndev); 2958 struct netdev_hw_addr *ha; 2959 unsigned int i, bit, data, crc, tmp; 2960 unsigned char hash; 2961 unsigned int hash_high = 0, hash_low = 0; 2962 2963 if (ndev->flags & IFF_PROMISC) { 2964 tmp = readl(fep->hwp + FEC_R_CNTRL); 2965 tmp |= 0x8; 2966 writel(tmp, fep->hwp + FEC_R_CNTRL); 2967 return; 2968 } 2969 2970 tmp = readl(fep->hwp + FEC_R_CNTRL); 2971 tmp &= ~0x8; 2972 writel(tmp, fep->hwp + FEC_R_CNTRL); 2973 2974 if (ndev->flags & IFF_ALLMULTI) { 2975 /* Catch all multicast addresses, so set the 2976 * filter to all 1's 2977 */ 2978 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2979 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2980 2981 return; 2982 } 2983 2984 /* Add the addresses in hash register */ 2985 netdev_for_each_mc_addr(ha, ndev) { 2986 /* calculate crc32 value of mac address */ 2987 crc = 0xffffffff; 2988 2989 for (i = 0; i < ndev->addr_len; i++) { 2990 data = ha->addr[i]; 2991 for (bit = 0; bit < 8; bit++, data >>= 1) { 2992 crc = (crc >> 1) ^ 2993 (((crc ^ data) & 1) ? CRC32_POLY : 0); 2994 } 2995 } 2996 2997 /* only upper 6 bits (FEC_HASH_BITS) are used 2998 * which point to specific bit in the hash registers 2999 */ 3000 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3001 3002 if (hash > 31) 3003 hash_high |= 1 << (hash - 32); 3004 else 3005 hash_low |= 1 << hash; 3006 } 3007 3008 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3009 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3010 } 3011 3012 /* Set a MAC change in hardware. */ 3013 static int 3014 fec_set_mac_address(struct net_device *ndev, void *p) 3015 { 3016 struct fec_enet_private *fep = netdev_priv(ndev); 3017 struct sockaddr *addr = p; 3018 3019 if (addr) { 3020 if (!is_valid_ether_addr(addr->sa_data)) 3021 return -EADDRNOTAVAIL; 3022 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 3023 } 3024 3025 /* Add netif status check here to avoid system hang in below case: 3026 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3027 * After ethx down, fec all clocks are gated off and then register 3028 * access causes system hang. 3029 */ 3030 if (!netif_running(ndev)) 3031 return 0; 3032 3033 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3034 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3035 fep->hwp + FEC_ADDR_LOW); 3036 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3037 fep->hwp + FEC_ADDR_HIGH); 3038 return 0; 3039 } 3040 3041 #ifdef CONFIG_NET_POLL_CONTROLLER 3042 /** 3043 * fec_poll_controller - FEC Poll controller function 3044 * @dev: The FEC network adapter 3045 * 3046 * Polled functionality used by netconsole and others in non interrupt mode 3047 * 3048 */ 3049 static void fec_poll_controller(struct net_device *dev) 3050 { 3051 int i; 3052 struct fec_enet_private *fep = netdev_priv(dev); 3053 3054 for (i = 0; i < FEC_IRQ_NUM; i++) { 3055 if (fep->irq[i] > 0) { 3056 disable_irq(fep->irq[i]); 3057 fec_enet_interrupt(fep->irq[i], dev); 3058 enable_irq(fep->irq[i]); 3059 } 3060 } 3061 } 3062 #endif 3063 3064 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3065 netdev_features_t features) 3066 { 3067 struct fec_enet_private *fep = netdev_priv(netdev); 3068 netdev_features_t changed = features ^ netdev->features; 3069 3070 netdev->features = features; 3071 3072 /* Receive checksum has been changed */ 3073 if (changed & NETIF_F_RXCSUM) { 3074 if (features & NETIF_F_RXCSUM) 3075 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3076 else 3077 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3078 } 3079 } 3080 3081 static int fec_set_features(struct net_device *netdev, 3082 netdev_features_t features) 3083 { 3084 struct fec_enet_private *fep = netdev_priv(netdev); 3085 netdev_features_t changed = features ^ netdev->features; 3086 3087 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3088 napi_disable(&fep->napi); 3089 netif_tx_lock_bh(netdev); 3090 fec_stop(netdev); 3091 fec_enet_set_netdev_features(netdev, features); 3092 fec_restart(netdev); 3093 netif_tx_wake_all_queues(netdev); 3094 netif_tx_unlock_bh(netdev); 3095 napi_enable(&fep->napi); 3096 } else { 3097 fec_enet_set_netdev_features(netdev, features); 3098 } 3099 3100 return 0; 3101 } 3102 3103 static const struct net_device_ops fec_netdev_ops = { 3104 .ndo_open = fec_enet_open, 3105 .ndo_stop = fec_enet_close, 3106 .ndo_start_xmit = fec_enet_start_xmit, 3107 .ndo_set_rx_mode = set_multicast_list, 3108 .ndo_validate_addr = eth_validate_addr, 3109 .ndo_tx_timeout = fec_timeout, 3110 .ndo_set_mac_address = fec_set_mac_address, 3111 .ndo_do_ioctl = fec_enet_ioctl, 3112 #ifdef CONFIG_NET_POLL_CONTROLLER 3113 .ndo_poll_controller = fec_poll_controller, 3114 #endif 3115 .ndo_set_features = fec_set_features, 3116 }; 3117 3118 static const unsigned short offset_des_active_rxq[] = { 3119 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3120 }; 3121 3122 static const unsigned short offset_des_active_txq[] = { 3123 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3124 }; 3125 3126 /* 3127 * XXX: We need to clean up on failure exits here. 3128 * 3129 */ 3130 static int fec_enet_init(struct net_device *ndev) 3131 { 3132 struct fec_enet_private *fep = netdev_priv(ndev); 3133 struct bufdesc *cbd_base; 3134 dma_addr_t bd_dma; 3135 int bd_size; 3136 unsigned int i; 3137 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3138 sizeof(struct bufdesc); 3139 unsigned dsize_log2 = __fls(dsize); 3140 3141 WARN_ON(dsize != (1 << dsize_log2)); 3142 #if defined(CONFIG_ARM) 3143 fep->rx_align = 0xf; 3144 fep->tx_align = 0xf; 3145 #else 3146 fep->rx_align = 0x3; 3147 fep->tx_align = 0x3; 3148 #endif 3149 3150 fec_enet_alloc_queue(ndev); 3151 3152 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3153 3154 /* Allocate memory for buffer descriptors. */ 3155 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3156 GFP_KERNEL); 3157 if (!cbd_base) { 3158 return -ENOMEM; 3159 } 3160 3161 memset(cbd_base, 0, bd_size); 3162 3163 /* Get the Ethernet address */ 3164 fec_get_mac(ndev); 3165 /* make sure MAC we just acquired is programmed into the hw */ 3166 fec_set_mac_address(ndev, NULL); 3167 3168 /* Set receive and transmit descriptor base. */ 3169 for (i = 0; i < fep->num_rx_queues; i++) { 3170 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3171 unsigned size = dsize * rxq->bd.ring_size; 3172 3173 rxq->bd.qid = i; 3174 rxq->bd.base = cbd_base; 3175 rxq->bd.cur = cbd_base; 3176 rxq->bd.dma = bd_dma; 3177 rxq->bd.dsize = dsize; 3178 rxq->bd.dsize_log2 = dsize_log2; 3179 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3180 bd_dma += size; 3181 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3182 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3183 } 3184 3185 for (i = 0; i < fep->num_tx_queues; i++) { 3186 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3187 unsigned size = dsize * txq->bd.ring_size; 3188 3189 txq->bd.qid = i; 3190 txq->bd.base = cbd_base; 3191 txq->bd.cur = cbd_base; 3192 txq->bd.dma = bd_dma; 3193 txq->bd.dsize = dsize; 3194 txq->bd.dsize_log2 = dsize_log2; 3195 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3196 bd_dma += size; 3197 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3198 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3199 } 3200 3201 3202 /* The FEC Ethernet specific entries in the device structure */ 3203 ndev->watchdog_timeo = TX_TIMEOUT; 3204 ndev->netdev_ops = &fec_netdev_ops; 3205 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3206 3207 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3208 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3209 3210 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3211 /* enable hw VLAN support */ 3212 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3213 3214 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3215 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3216 3217 /* enable hw accelerator */ 3218 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3219 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3220 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3221 } 3222 3223 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 3224 fep->tx_align = 0; 3225 fep->rx_align = 0x3f; 3226 } 3227 3228 ndev->hw_features = ndev->features; 3229 3230 fec_restart(ndev); 3231 3232 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 3233 fec_enet_clear_ethtool_stats(ndev); 3234 else 3235 fec_enet_update_ethtool_stats(ndev); 3236 3237 return 0; 3238 } 3239 3240 #ifdef CONFIG_OF 3241 static int fec_reset_phy(struct platform_device *pdev) 3242 { 3243 int err, phy_reset; 3244 bool active_high = false; 3245 int msec = 1, phy_post_delay = 0; 3246 struct device_node *np = pdev->dev.of_node; 3247 3248 if (!np) 3249 return 0; 3250 3251 err = of_property_read_u32(np, "phy-reset-duration", &msec); 3252 /* A sane reset duration should not be longer than 1s */ 3253 if (!err && msec > 1000) 3254 msec = 1; 3255 3256 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3257 if (phy_reset == -EPROBE_DEFER) 3258 return phy_reset; 3259 else if (!gpio_is_valid(phy_reset)) 3260 return 0; 3261 3262 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 3263 /* valid reset duration should be less than 1s */ 3264 if (!err && phy_post_delay > 1000) 3265 return -EINVAL; 3266 3267 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3268 3269 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3270 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3271 "phy-reset"); 3272 if (err) { 3273 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3274 return err; 3275 } 3276 3277 if (msec > 20) 3278 msleep(msec); 3279 else 3280 usleep_range(msec * 1000, msec * 1000 + 1000); 3281 3282 gpio_set_value_cansleep(phy_reset, !active_high); 3283 3284 if (!phy_post_delay) 3285 return 0; 3286 3287 if (phy_post_delay > 20) 3288 msleep(phy_post_delay); 3289 else 3290 usleep_range(phy_post_delay * 1000, 3291 phy_post_delay * 1000 + 1000); 3292 3293 return 0; 3294 } 3295 #else /* CONFIG_OF */ 3296 static int fec_reset_phy(struct platform_device *pdev) 3297 { 3298 /* 3299 * In case of platform probe, the reset has been done 3300 * by machine code. 3301 */ 3302 return 0; 3303 } 3304 #endif /* CONFIG_OF */ 3305 3306 static void 3307 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3308 { 3309 struct device_node *np = pdev->dev.of_node; 3310 3311 *num_tx = *num_rx = 1; 3312 3313 if (!np || !of_device_is_available(np)) 3314 return; 3315 3316 /* parse the num of tx and rx queues */ 3317 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3318 3319 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3320 3321 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3322 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3323 *num_tx); 3324 *num_tx = 1; 3325 return; 3326 } 3327 3328 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3329 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3330 *num_rx); 3331 *num_rx = 1; 3332 return; 3333 } 3334 3335 } 3336 3337 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 3338 { 3339 int irq_cnt = platform_irq_count(pdev); 3340 3341 if (irq_cnt > FEC_IRQ_NUM) 3342 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 3343 else if (irq_cnt == 2) 3344 irq_cnt = 1; /* last for pps */ 3345 else if (irq_cnt <= 0) 3346 irq_cnt = 1; /* At least 1 irq is needed */ 3347 return irq_cnt; 3348 } 3349 3350 static int 3351 fec_probe(struct platform_device *pdev) 3352 { 3353 struct fec_enet_private *fep; 3354 struct fec_platform_data *pdata; 3355 struct net_device *ndev; 3356 int i, irq, ret = 0; 3357 struct resource *r; 3358 const struct of_device_id *of_id; 3359 static int dev_id; 3360 struct device_node *np = pdev->dev.of_node, *phy_node; 3361 int num_tx_qs; 3362 int num_rx_qs; 3363 char irq_name[8]; 3364 int irq_cnt; 3365 3366 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3367 3368 /* Init network device */ 3369 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 3370 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 3371 if (!ndev) 3372 return -ENOMEM; 3373 3374 SET_NETDEV_DEV(ndev, &pdev->dev); 3375 3376 /* setup board info structure */ 3377 fep = netdev_priv(ndev); 3378 3379 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3380 if (of_id) 3381 pdev->id_entry = of_id->data; 3382 fep->quirks = pdev->id_entry->driver_data; 3383 3384 fep->netdev = ndev; 3385 fep->num_rx_queues = num_rx_qs; 3386 fep->num_tx_queues = num_tx_qs; 3387 3388 #if !defined(CONFIG_M5272) 3389 /* default enable pause frame auto negotiation */ 3390 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3391 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3392 #endif 3393 3394 /* Select default pin state */ 3395 pinctrl_pm_select_default_state(&pdev->dev); 3396 3397 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3398 fep->hwp = devm_ioremap_resource(&pdev->dev, r); 3399 if (IS_ERR(fep->hwp)) { 3400 ret = PTR_ERR(fep->hwp); 3401 goto failed_ioremap; 3402 } 3403 3404 fep->pdev = pdev; 3405 fep->dev_id = dev_id++; 3406 3407 platform_set_drvdata(pdev, ndev); 3408 3409 if ((of_machine_is_compatible("fsl,imx6q") || 3410 of_machine_is_compatible("fsl,imx6dl")) && 3411 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3412 fep->quirks |= FEC_QUIRK_ERR006687; 3413 3414 if (of_get_property(np, "fsl,magic-packet", NULL)) 3415 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3416 3417 phy_node = of_parse_phandle(np, "phy-handle", 0); 3418 if (!phy_node && of_phy_is_fixed_link(np)) { 3419 ret = of_phy_register_fixed_link(np); 3420 if (ret < 0) { 3421 dev_err(&pdev->dev, 3422 "broken fixed-link specification\n"); 3423 goto failed_phy; 3424 } 3425 phy_node = of_node_get(np); 3426 } 3427 fep->phy_node = phy_node; 3428 3429 ret = of_get_phy_mode(pdev->dev.of_node); 3430 if (ret < 0) { 3431 pdata = dev_get_platdata(&pdev->dev); 3432 if (pdata) 3433 fep->phy_interface = pdata->phy; 3434 else 3435 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3436 } else { 3437 fep->phy_interface = ret; 3438 } 3439 3440 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3441 if (IS_ERR(fep->clk_ipg)) { 3442 ret = PTR_ERR(fep->clk_ipg); 3443 goto failed_clk; 3444 } 3445 3446 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3447 if (IS_ERR(fep->clk_ahb)) { 3448 ret = PTR_ERR(fep->clk_ahb); 3449 goto failed_clk; 3450 } 3451 3452 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3453 3454 /* enet_out is optional, depends on board */ 3455 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3456 if (IS_ERR(fep->clk_enet_out)) 3457 fep->clk_enet_out = NULL; 3458 3459 fep->ptp_clk_on = false; 3460 mutex_init(&fep->ptp_clk_mutex); 3461 3462 /* clk_ref is optional, depends on board */ 3463 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3464 if (IS_ERR(fep->clk_ref)) 3465 fep->clk_ref = NULL; 3466 3467 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3468 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3469 if (IS_ERR(fep->clk_ptp)) { 3470 fep->clk_ptp = NULL; 3471 fep->bufdesc_ex = false; 3472 } 3473 3474 ret = fec_enet_clk_enable(ndev, true); 3475 if (ret) 3476 goto failed_clk; 3477 3478 ret = clk_prepare_enable(fep->clk_ipg); 3479 if (ret) 3480 goto failed_clk_ipg; 3481 3482 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); 3483 if (!IS_ERR(fep->reg_phy)) { 3484 ret = regulator_enable(fep->reg_phy); 3485 if (ret) { 3486 dev_err(&pdev->dev, 3487 "Failed to enable phy regulator: %d\n", ret); 3488 clk_disable_unprepare(fep->clk_ipg); 3489 goto failed_regulator; 3490 } 3491 } else { 3492 fep->reg_phy = NULL; 3493 } 3494 3495 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3496 pm_runtime_use_autosuspend(&pdev->dev); 3497 pm_runtime_get_noresume(&pdev->dev); 3498 pm_runtime_set_active(&pdev->dev); 3499 pm_runtime_enable(&pdev->dev); 3500 3501 ret = fec_reset_phy(pdev); 3502 if (ret) 3503 goto failed_reset; 3504 3505 irq_cnt = fec_enet_get_irq_cnt(pdev); 3506 if (fep->bufdesc_ex) 3507 fec_ptp_init(pdev, irq_cnt); 3508 3509 ret = fec_enet_init(ndev); 3510 if (ret) 3511 goto failed_init; 3512 3513 for (i = 0; i < irq_cnt; i++) { 3514 sprintf(irq_name, "int%d", i); 3515 irq = platform_get_irq_byname(pdev, irq_name); 3516 if (irq < 0) 3517 irq = platform_get_irq(pdev, i); 3518 if (irq < 0) { 3519 ret = irq; 3520 goto failed_irq; 3521 } 3522 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3523 0, pdev->name, ndev); 3524 if (ret) 3525 goto failed_irq; 3526 3527 fep->irq[i] = irq; 3528 } 3529 3530 init_completion(&fep->mdio_done); 3531 ret = fec_enet_mii_init(pdev); 3532 if (ret) 3533 goto failed_mii_init; 3534 3535 /* Carrier starts down, phylib will bring it up */ 3536 netif_carrier_off(ndev); 3537 fec_enet_clk_enable(ndev, false); 3538 pinctrl_pm_select_sleep_state(&pdev->dev); 3539 3540 ret = register_netdev(ndev); 3541 if (ret) 3542 goto failed_register; 3543 3544 device_init_wakeup(&ndev->dev, fep->wol_flag & 3545 FEC_WOL_HAS_MAGIC_PACKET); 3546 3547 if (fep->bufdesc_ex && fep->ptp_clock) 3548 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3549 3550 fep->rx_copybreak = COPYBREAK_DEFAULT; 3551 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3552 3553 pm_runtime_mark_last_busy(&pdev->dev); 3554 pm_runtime_put_autosuspend(&pdev->dev); 3555 3556 return 0; 3557 3558 failed_register: 3559 fec_enet_mii_remove(fep); 3560 failed_mii_init: 3561 failed_irq: 3562 failed_init: 3563 fec_ptp_stop(pdev); 3564 if (fep->reg_phy) 3565 regulator_disable(fep->reg_phy); 3566 failed_reset: 3567 pm_runtime_put(&pdev->dev); 3568 pm_runtime_disable(&pdev->dev); 3569 failed_regulator: 3570 failed_clk_ipg: 3571 fec_enet_clk_enable(ndev, false); 3572 failed_clk: 3573 if (of_phy_is_fixed_link(np)) 3574 of_phy_deregister_fixed_link(np); 3575 failed_phy: 3576 of_node_put(phy_node); 3577 failed_ioremap: 3578 free_netdev(ndev); 3579 3580 return ret; 3581 } 3582 3583 static int 3584 fec_drv_remove(struct platform_device *pdev) 3585 { 3586 struct net_device *ndev = platform_get_drvdata(pdev); 3587 struct fec_enet_private *fep = netdev_priv(ndev); 3588 struct device_node *np = pdev->dev.of_node; 3589 3590 cancel_work_sync(&fep->tx_timeout_work); 3591 fec_ptp_stop(pdev); 3592 unregister_netdev(ndev); 3593 fec_enet_mii_remove(fep); 3594 if (fep->reg_phy) 3595 regulator_disable(fep->reg_phy); 3596 if (of_phy_is_fixed_link(np)) 3597 of_phy_deregister_fixed_link(np); 3598 of_node_put(fep->phy_node); 3599 free_netdev(ndev); 3600 3601 return 0; 3602 } 3603 3604 static int __maybe_unused fec_suspend(struct device *dev) 3605 { 3606 struct net_device *ndev = dev_get_drvdata(dev); 3607 struct fec_enet_private *fep = netdev_priv(ndev); 3608 3609 rtnl_lock(); 3610 if (netif_running(ndev)) { 3611 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 3612 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 3613 phy_stop(ndev->phydev); 3614 napi_disable(&fep->napi); 3615 netif_tx_lock_bh(ndev); 3616 netif_device_detach(ndev); 3617 netif_tx_unlock_bh(ndev); 3618 fec_stop(ndev); 3619 fec_enet_clk_enable(ndev, false); 3620 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3621 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3622 } 3623 rtnl_unlock(); 3624 3625 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3626 regulator_disable(fep->reg_phy); 3627 3628 /* SOC supply clock to phy, when clock is disabled, phy link down 3629 * SOC control phy regulator, when regulator is disabled, phy link down 3630 */ 3631 if (fep->clk_enet_out || fep->reg_phy) 3632 fep->link = 0; 3633 3634 return 0; 3635 } 3636 3637 static int __maybe_unused fec_resume(struct device *dev) 3638 { 3639 struct net_device *ndev = dev_get_drvdata(dev); 3640 struct fec_enet_private *fep = netdev_priv(ndev); 3641 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 3642 int ret; 3643 int val; 3644 3645 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 3646 ret = regulator_enable(fep->reg_phy); 3647 if (ret) 3648 return ret; 3649 } 3650 3651 rtnl_lock(); 3652 if (netif_running(ndev)) { 3653 ret = fec_enet_clk_enable(ndev, true); 3654 if (ret) { 3655 rtnl_unlock(); 3656 goto failed_clk; 3657 } 3658 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 3659 if (pdata && pdata->sleep_mode_enable) 3660 pdata->sleep_mode_enable(false); 3661 val = readl(fep->hwp + FEC_ECNTRL); 3662 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 3663 writel(val, fep->hwp + FEC_ECNTRL); 3664 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 3665 } else { 3666 pinctrl_pm_select_default_state(&fep->pdev->dev); 3667 } 3668 fec_restart(ndev); 3669 netif_tx_lock_bh(ndev); 3670 netif_device_attach(ndev); 3671 netif_tx_unlock_bh(ndev); 3672 napi_enable(&fep->napi); 3673 phy_start(ndev->phydev); 3674 } 3675 rtnl_unlock(); 3676 3677 return 0; 3678 3679 failed_clk: 3680 if (fep->reg_phy) 3681 regulator_disable(fep->reg_phy); 3682 return ret; 3683 } 3684 3685 static int __maybe_unused fec_runtime_suspend(struct device *dev) 3686 { 3687 struct net_device *ndev = dev_get_drvdata(dev); 3688 struct fec_enet_private *fep = netdev_priv(ndev); 3689 3690 clk_disable_unprepare(fep->clk_ipg); 3691 3692 return 0; 3693 } 3694 3695 static int __maybe_unused fec_runtime_resume(struct device *dev) 3696 { 3697 struct net_device *ndev = dev_get_drvdata(dev); 3698 struct fec_enet_private *fep = netdev_priv(ndev); 3699 3700 return clk_prepare_enable(fep->clk_ipg); 3701 } 3702 3703 static const struct dev_pm_ops fec_pm_ops = { 3704 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 3705 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 3706 }; 3707 3708 static struct platform_driver fec_driver = { 3709 .driver = { 3710 .name = DRIVER_NAME, 3711 .pm = &fec_pm_ops, 3712 .of_match_table = fec_dt_ids, 3713 }, 3714 .id_table = fec_devtype, 3715 .probe = fec_probe, 3716 .remove = fec_drv_remove, 3717 }; 3718 3719 module_platform_driver(fec_driver); 3720 3721 MODULE_ALIAS("platform:"DRIVER_NAME); 3722 MODULE_LICENSE("GPL"); 3723