1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/tso.h> 42 #include <linux/tcp.h> 43 #include <linux/udp.h> 44 #include <linux/icmp.h> 45 #include <linux/spinlock.h> 46 #include <linux/workqueue.h> 47 #include <linux/bitops.h> 48 #include <linux/io.h> 49 #include <linux/irq.h> 50 #include <linux/clk.h> 51 #include <linux/crc32.h> 52 #include <linux/platform_device.h> 53 #include <linux/mdio.h> 54 #include <linux/phy.h> 55 #include <linux/fec.h> 56 #include <linux/of.h> 57 #include <linux/of_device.h> 58 #include <linux/of_gpio.h> 59 #include <linux/of_mdio.h> 60 #include <linux/of_net.h> 61 #include <linux/regulator/consumer.h> 62 #include <linux/if_vlan.h> 63 #include <linux/pinctrl/consumer.h> 64 #include <linux/prefetch.h> 65 #include <linux/mfd/syscon.h> 66 #include <linux/regmap.h> 67 #include <soc/imx/cpuidle.h> 68 69 #include <asm/cacheflush.h> 70 71 #include "fec.h" 72 73 static void set_multicast_list(struct net_device *ndev); 74 static void fec_enet_itr_coal_init(struct net_device *ndev); 75 76 #define DRIVER_NAME "fec" 77 78 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0)) 79 80 /* Pause frame feild and FIFO threshold */ 81 #define FEC_ENET_FCE (1 << 5) 82 #define FEC_ENET_RSEM_V 0x84 83 #define FEC_ENET_RSFL_V 16 84 #define FEC_ENET_RAEM_V 0x8 85 #define FEC_ENET_RAFL_V 0x8 86 #define FEC_ENET_OPD_V 0xFFF0 87 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 88 89 struct fec_devinfo { 90 u32 quirks; 91 u8 stop_gpr_reg; 92 u8 stop_gpr_bit; 93 }; 94 95 static const struct fec_devinfo fec_imx25_info = { 96 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 97 FEC_QUIRK_HAS_FRREG, 98 }; 99 100 static const struct fec_devinfo fec_imx27_info = { 101 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG, 102 }; 103 104 static const struct fec_devinfo fec_imx28_info = { 105 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 106 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 107 FEC_QUIRK_HAS_FRREG, 108 }; 109 110 static const struct fec_devinfo fec_imx6q_info = { 111 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 112 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 113 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 114 FEC_QUIRK_HAS_RACC, 115 .stop_gpr_reg = 0x34, 116 .stop_gpr_bit = 27, 117 }; 118 119 static const struct fec_devinfo fec_mvf600_info = { 120 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 121 }; 122 123 static const struct fec_devinfo fec_imx6x_info = { 124 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 125 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 126 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 127 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 128 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE, 129 }; 130 131 static const struct fec_devinfo fec_imx6ul_info = { 132 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 133 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 134 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 135 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 136 FEC_QUIRK_HAS_COALESCE, 137 }; 138 139 static struct platform_device_id fec_devtype[] = { 140 { 141 /* keep it for coldfire */ 142 .name = DRIVER_NAME, 143 .driver_data = 0, 144 }, { 145 .name = "imx25-fec", 146 .driver_data = (kernel_ulong_t)&fec_imx25_info, 147 }, { 148 .name = "imx27-fec", 149 .driver_data = (kernel_ulong_t)&fec_imx27_info, 150 }, { 151 .name = "imx28-fec", 152 .driver_data = (kernel_ulong_t)&fec_imx28_info, 153 }, { 154 .name = "imx6q-fec", 155 .driver_data = (kernel_ulong_t)&fec_imx6q_info, 156 }, { 157 .name = "mvf600-fec", 158 .driver_data = (kernel_ulong_t)&fec_mvf600_info, 159 }, { 160 .name = "imx6sx-fec", 161 .driver_data = (kernel_ulong_t)&fec_imx6x_info, 162 }, { 163 .name = "imx6ul-fec", 164 .driver_data = (kernel_ulong_t)&fec_imx6ul_info, 165 }, { 166 /* sentinel */ 167 } 168 }; 169 MODULE_DEVICE_TABLE(platform, fec_devtype); 170 171 enum imx_fec_type { 172 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 173 IMX27_FEC, /* runs on i.mx27/35/51 */ 174 IMX28_FEC, 175 IMX6Q_FEC, 176 MVF600_FEC, 177 IMX6SX_FEC, 178 IMX6UL_FEC, 179 }; 180 181 static const struct of_device_id fec_dt_ids[] = { 182 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 183 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 184 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 185 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 186 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 187 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 188 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 189 { /* sentinel */ } 190 }; 191 MODULE_DEVICE_TABLE(of, fec_dt_ids); 192 193 static unsigned char macaddr[ETH_ALEN]; 194 module_param_array(macaddr, byte, NULL, 0); 195 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 196 197 #if defined(CONFIG_M5272) 198 /* 199 * Some hardware gets it MAC address out of local flash memory. 200 * if this is non-zero then assume it is the address to get MAC from. 201 */ 202 #if defined(CONFIG_NETtel) 203 #define FEC_FLASHMAC 0xf0006006 204 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 205 #define FEC_FLASHMAC 0xf0006000 206 #elif defined(CONFIG_CANCam) 207 #define FEC_FLASHMAC 0xf0020000 208 #elif defined (CONFIG_M5272C3) 209 #define FEC_FLASHMAC (0xffe04000 + 4) 210 #elif defined(CONFIG_MOD5272) 211 #define FEC_FLASHMAC 0xffc0406b 212 #else 213 #define FEC_FLASHMAC 0 214 #endif 215 #endif /* CONFIG_M5272 */ 216 217 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 218 * 219 * 2048 byte skbufs are allocated. However, alignment requirements 220 * varies between FEC variants. Worst case is 64, so round down by 64. 221 */ 222 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 223 #define PKT_MINBUF_SIZE 64 224 225 /* FEC receive acceleration */ 226 #define FEC_RACC_IPDIS (1 << 1) 227 #define FEC_RACC_PRODIS (1 << 2) 228 #define FEC_RACC_SHIFT16 BIT(7) 229 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 230 231 /* MIB Control Register */ 232 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 233 234 /* 235 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 236 * size bits. Other FEC hardware does not, so we need to take that into 237 * account when setting it. 238 */ 239 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 240 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 241 defined(CONFIG_ARM64) 242 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 243 #else 244 #define OPT_FRAME_SIZE 0 245 #endif 246 247 /* FEC MII MMFR bits definition */ 248 #define FEC_MMFR_ST (1 << 30) 249 #define FEC_MMFR_ST_C45 (0) 250 #define FEC_MMFR_OP_READ (2 << 28) 251 #define FEC_MMFR_OP_READ_C45 (3 << 28) 252 #define FEC_MMFR_OP_WRITE (1 << 28) 253 #define FEC_MMFR_OP_ADDR_WRITE (0) 254 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 255 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 256 #define FEC_MMFR_TA (2 << 16) 257 #define FEC_MMFR_DATA(v) (v & 0xffff) 258 /* FEC ECR bits definition */ 259 #define FEC_ECR_MAGICEN (1 << 2) 260 #define FEC_ECR_SLEEP (1 << 3) 261 262 #define FEC_MII_TIMEOUT 30000 /* us */ 263 264 /* Transmitter timeout */ 265 #define TX_TIMEOUT (2 * HZ) 266 267 #define FEC_PAUSE_FLAG_AUTONEG 0x1 268 #define FEC_PAUSE_FLAG_ENABLE 0x2 269 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 270 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 271 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 272 273 #define COPYBREAK_DEFAULT 256 274 275 /* Max number of allowed TCP segments for software TSO */ 276 #define FEC_MAX_TSO_SEGS 100 277 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 278 279 #define IS_TSO_HEADER(txq, addr) \ 280 ((addr >= txq->tso_hdrs_dma) && \ 281 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 282 283 static int mii_cnt; 284 285 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 286 struct bufdesc_prop *bd) 287 { 288 return (bdp >= bd->last) ? bd->base 289 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 290 } 291 292 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 293 struct bufdesc_prop *bd) 294 { 295 return (bdp <= bd->base) ? bd->last 296 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 297 } 298 299 static int fec_enet_get_bd_index(struct bufdesc *bdp, 300 struct bufdesc_prop *bd) 301 { 302 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 303 } 304 305 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 306 { 307 int entries; 308 309 entries = (((const char *)txq->dirty_tx - 310 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 311 312 return entries >= 0 ? entries : entries + txq->bd.ring_size; 313 } 314 315 static void swap_buffer(void *bufaddr, int len) 316 { 317 int i; 318 unsigned int *buf = bufaddr; 319 320 for (i = 0; i < len; i += 4, buf++) 321 swab32s(buf); 322 } 323 324 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 325 { 326 int i; 327 unsigned int *src = src_buf; 328 unsigned int *dst = dst_buf; 329 330 for (i = 0; i < len; i += 4, src++, dst++) 331 *dst = swab32p(src); 332 } 333 334 static void fec_dump(struct net_device *ndev) 335 { 336 struct fec_enet_private *fep = netdev_priv(ndev); 337 struct bufdesc *bdp; 338 struct fec_enet_priv_tx_q *txq; 339 int index = 0; 340 341 netdev_info(ndev, "TX ring dump\n"); 342 pr_info("Nr SC addr len SKB\n"); 343 344 txq = fep->tx_queue[0]; 345 bdp = txq->bd.base; 346 347 do { 348 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 349 index, 350 bdp == txq->bd.cur ? 'S' : ' ', 351 bdp == txq->dirty_tx ? 'H' : ' ', 352 fec16_to_cpu(bdp->cbd_sc), 353 fec32_to_cpu(bdp->cbd_bufaddr), 354 fec16_to_cpu(bdp->cbd_datlen), 355 txq->tx_skbuff[index]); 356 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 357 index++; 358 } while (bdp != txq->bd.base); 359 } 360 361 static inline bool is_ipv4_pkt(struct sk_buff *skb) 362 { 363 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 364 } 365 366 static int 367 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 368 { 369 /* Only run for packets requiring a checksum. */ 370 if (skb->ip_summed != CHECKSUM_PARTIAL) 371 return 0; 372 373 if (unlikely(skb_cow_head(skb, 0))) 374 return -1; 375 376 if (is_ipv4_pkt(skb)) 377 ip_hdr(skb)->check = 0; 378 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 379 380 return 0; 381 } 382 383 static struct bufdesc * 384 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 385 struct sk_buff *skb, 386 struct net_device *ndev) 387 { 388 struct fec_enet_private *fep = netdev_priv(ndev); 389 struct bufdesc *bdp = txq->bd.cur; 390 struct bufdesc_ex *ebdp; 391 int nr_frags = skb_shinfo(skb)->nr_frags; 392 int frag, frag_len; 393 unsigned short status; 394 unsigned int estatus = 0; 395 skb_frag_t *this_frag; 396 unsigned int index; 397 void *bufaddr; 398 dma_addr_t addr; 399 int i; 400 401 for (frag = 0; frag < nr_frags; frag++) { 402 this_frag = &skb_shinfo(skb)->frags[frag]; 403 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 404 ebdp = (struct bufdesc_ex *)bdp; 405 406 status = fec16_to_cpu(bdp->cbd_sc); 407 status &= ~BD_ENET_TX_STATS; 408 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 409 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 410 411 /* Handle the last BD specially */ 412 if (frag == nr_frags - 1) { 413 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 414 if (fep->bufdesc_ex) { 415 estatus |= BD_ENET_TX_INT; 416 if (unlikely(skb_shinfo(skb)->tx_flags & 417 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 418 estatus |= BD_ENET_TX_TS; 419 } 420 } 421 422 if (fep->bufdesc_ex) { 423 if (fep->quirks & FEC_QUIRK_HAS_AVB) 424 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 425 if (skb->ip_summed == CHECKSUM_PARTIAL) 426 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 427 ebdp->cbd_bdu = 0; 428 ebdp->cbd_esc = cpu_to_fec32(estatus); 429 } 430 431 bufaddr = skb_frag_address(this_frag); 432 433 index = fec_enet_get_bd_index(bdp, &txq->bd); 434 if (((unsigned long) bufaddr) & fep->tx_align || 435 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 436 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 437 bufaddr = txq->tx_bounce[index]; 438 439 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 440 swap_buffer(bufaddr, frag_len); 441 } 442 443 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 444 DMA_TO_DEVICE); 445 if (dma_mapping_error(&fep->pdev->dev, addr)) { 446 if (net_ratelimit()) 447 netdev_err(ndev, "Tx DMA memory map failed\n"); 448 goto dma_mapping_error; 449 } 450 451 bdp->cbd_bufaddr = cpu_to_fec32(addr); 452 bdp->cbd_datlen = cpu_to_fec16(frag_len); 453 /* Make sure the updates to rest of the descriptor are 454 * performed before transferring ownership. 455 */ 456 wmb(); 457 bdp->cbd_sc = cpu_to_fec16(status); 458 } 459 460 return bdp; 461 dma_mapping_error: 462 bdp = txq->bd.cur; 463 for (i = 0; i < frag; i++) { 464 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 465 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 466 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 467 } 468 return ERR_PTR(-ENOMEM); 469 } 470 471 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 472 struct sk_buff *skb, struct net_device *ndev) 473 { 474 struct fec_enet_private *fep = netdev_priv(ndev); 475 int nr_frags = skb_shinfo(skb)->nr_frags; 476 struct bufdesc *bdp, *last_bdp; 477 void *bufaddr; 478 dma_addr_t addr; 479 unsigned short status; 480 unsigned short buflen; 481 unsigned int estatus = 0; 482 unsigned int index; 483 int entries_free; 484 485 entries_free = fec_enet_get_free_txdesc_num(txq); 486 if (entries_free < MAX_SKB_FRAGS + 1) { 487 dev_kfree_skb_any(skb); 488 if (net_ratelimit()) 489 netdev_err(ndev, "NOT enough BD for SG!\n"); 490 return NETDEV_TX_OK; 491 } 492 493 /* Protocol checksum off-load for TCP and UDP. */ 494 if (fec_enet_clear_csum(skb, ndev)) { 495 dev_kfree_skb_any(skb); 496 return NETDEV_TX_OK; 497 } 498 499 /* Fill in a Tx ring entry */ 500 bdp = txq->bd.cur; 501 last_bdp = bdp; 502 status = fec16_to_cpu(bdp->cbd_sc); 503 status &= ~BD_ENET_TX_STATS; 504 505 /* Set buffer length and buffer pointer */ 506 bufaddr = skb->data; 507 buflen = skb_headlen(skb); 508 509 index = fec_enet_get_bd_index(bdp, &txq->bd); 510 if (((unsigned long) bufaddr) & fep->tx_align || 511 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 512 memcpy(txq->tx_bounce[index], skb->data, buflen); 513 bufaddr = txq->tx_bounce[index]; 514 515 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 516 swap_buffer(bufaddr, buflen); 517 } 518 519 /* Push the data cache so the CPM does not get stale memory data. */ 520 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 521 if (dma_mapping_error(&fep->pdev->dev, addr)) { 522 dev_kfree_skb_any(skb); 523 if (net_ratelimit()) 524 netdev_err(ndev, "Tx DMA memory map failed\n"); 525 return NETDEV_TX_OK; 526 } 527 528 if (nr_frags) { 529 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 530 if (IS_ERR(last_bdp)) { 531 dma_unmap_single(&fep->pdev->dev, addr, 532 buflen, DMA_TO_DEVICE); 533 dev_kfree_skb_any(skb); 534 return NETDEV_TX_OK; 535 } 536 } else { 537 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 538 if (fep->bufdesc_ex) { 539 estatus = BD_ENET_TX_INT; 540 if (unlikely(skb_shinfo(skb)->tx_flags & 541 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 542 estatus |= BD_ENET_TX_TS; 543 } 544 } 545 bdp->cbd_bufaddr = cpu_to_fec32(addr); 546 bdp->cbd_datlen = cpu_to_fec16(buflen); 547 548 if (fep->bufdesc_ex) { 549 550 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 551 552 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 553 fep->hwts_tx_en)) 554 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 555 556 if (fep->quirks & FEC_QUIRK_HAS_AVB) 557 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 558 559 if (skb->ip_summed == CHECKSUM_PARTIAL) 560 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 561 562 ebdp->cbd_bdu = 0; 563 ebdp->cbd_esc = cpu_to_fec32(estatus); 564 } 565 566 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 567 /* Save skb pointer */ 568 txq->tx_skbuff[index] = skb; 569 570 /* Make sure the updates to rest of the descriptor are performed before 571 * transferring ownership. 572 */ 573 wmb(); 574 575 /* Send it on its way. Tell FEC it's ready, interrupt when done, 576 * it's the last BD of the frame, and to put the CRC on the end. 577 */ 578 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 579 bdp->cbd_sc = cpu_to_fec16(status); 580 581 /* If this was the last BD in the ring, start at the beginning again. */ 582 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 583 584 skb_tx_timestamp(skb); 585 586 /* Make sure the update to bdp and tx_skbuff are performed before 587 * txq->bd.cur. 588 */ 589 wmb(); 590 txq->bd.cur = bdp; 591 592 /* Trigger transmission start */ 593 writel(0, txq->bd.reg_desc_active); 594 595 return 0; 596 } 597 598 static int 599 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 600 struct net_device *ndev, 601 struct bufdesc *bdp, int index, char *data, 602 int size, bool last_tcp, bool is_last) 603 { 604 struct fec_enet_private *fep = netdev_priv(ndev); 605 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 606 unsigned short status; 607 unsigned int estatus = 0; 608 dma_addr_t addr; 609 610 status = fec16_to_cpu(bdp->cbd_sc); 611 status &= ~BD_ENET_TX_STATS; 612 613 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 614 615 if (((unsigned long) data) & fep->tx_align || 616 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 617 memcpy(txq->tx_bounce[index], data, size); 618 data = txq->tx_bounce[index]; 619 620 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 621 swap_buffer(data, size); 622 } 623 624 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 625 if (dma_mapping_error(&fep->pdev->dev, addr)) { 626 dev_kfree_skb_any(skb); 627 if (net_ratelimit()) 628 netdev_err(ndev, "Tx DMA memory map failed\n"); 629 return NETDEV_TX_BUSY; 630 } 631 632 bdp->cbd_datlen = cpu_to_fec16(size); 633 bdp->cbd_bufaddr = cpu_to_fec32(addr); 634 635 if (fep->bufdesc_ex) { 636 if (fep->quirks & FEC_QUIRK_HAS_AVB) 637 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 638 if (skb->ip_summed == CHECKSUM_PARTIAL) 639 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 640 ebdp->cbd_bdu = 0; 641 ebdp->cbd_esc = cpu_to_fec32(estatus); 642 } 643 644 /* Handle the last BD specially */ 645 if (last_tcp) 646 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 647 if (is_last) { 648 status |= BD_ENET_TX_INTR; 649 if (fep->bufdesc_ex) 650 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 651 } 652 653 bdp->cbd_sc = cpu_to_fec16(status); 654 655 return 0; 656 } 657 658 static int 659 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 660 struct sk_buff *skb, struct net_device *ndev, 661 struct bufdesc *bdp, int index) 662 { 663 struct fec_enet_private *fep = netdev_priv(ndev); 664 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 665 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 666 void *bufaddr; 667 unsigned long dmabuf; 668 unsigned short status; 669 unsigned int estatus = 0; 670 671 status = fec16_to_cpu(bdp->cbd_sc); 672 status &= ~BD_ENET_TX_STATS; 673 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 674 675 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 676 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 677 if (((unsigned long)bufaddr) & fep->tx_align || 678 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 679 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 680 bufaddr = txq->tx_bounce[index]; 681 682 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 683 swap_buffer(bufaddr, hdr_len); 684 685 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 686 hdr_len, DMA_TO_DEVICE); 687 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 688 dev_kfree_skb_any(skb); 689 if (net_ratelimit()) 690 netdev_err(ndev, "Tx DMA memory map failed\n"); 691 return NETDEV_TX_BUSY; 692 } 693 } 694 695 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 696 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 697 698 if (fep->bufdesc_ex) { 699 if (fep->quirks & FEC_QUIRK_HAS_AVB) 700 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 701 if (skb->ip_summed == CHECKSUM_PARTIAL) 702 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 703 ebdp->cbd_bdu = 0; 704 ebdp->cbd_esc = cpu_to_fec32(estatus); 705 } 706 707 bdp->cbd_sc = cpu_to_fec16(status); 708 709 return 0; 710 } 711 712 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 713 struct sk_buff *skb, 714 struct net_device *ndev) 715 { 716 struct fec_enet_private *fep = netdev_priv(ndev); 717 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 718 int total_len, data_left; 719 struct bufdesc *bdp = txq->bd.cur; 720 struct tso_t tso; 721 unsigned int index = 0; 722 int ret; 723 724 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 725 dev_kfree_skb_any(skb); 726 if (net_ratelimit()) 727 netdev_err(ndev, "NOT enough BD for TSO!\n"); 728 return NETDEV_TX_OK; 729 } 730 731 /* Protocol checksum off-load for TCP and UDP. */ 732 if (fec_enet_clear_csum(skb, ndev)) { 733 dev_kfree_skb_any(skb); 734 return NETDEV_TX_OK; 735 } 736 737 /* Initialize the TSO handler, and prepare the first payload */ 738 tso_start(skb, &tso); 739 740 total_len = skb->len - hdr_len; 741 while (total_len > 0) { 742 char *hdr; 743 744 index = fec_enet_get_bd_index(bdp, &txq->bd); 745 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 746 total_len -= data_left; 747 748 /* prepare packet headers: MAC + IP + TCP */ 749 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 750 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 751 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 752 if (ret) 753 goto err_release; 754 755 while (data_left > 0) { 756 int size; 757 758 size = min_t(int, tso.size, data_left); 759 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 760 index = fec_enet_get_bd_index(bdp, &txq->bd); 761 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 762 bdp, index, 763 tso.data, size, 764 size == data_left, 765 total_len == 0); 766 if (ret) 767 goto err_release; 768 769 data_left -= size; 770 tso_build_data(skb, &tso, size); 771 } 772 773 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 774 } 775 776 /* Save skb pointer */ 777 txq->tx_skbuff[index] = skb; 778 779 skb_tx_timestamp(skb); 780 txq->bd.cur = bdp; 781 782 /* Trigger transmission start */ 783 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 784 !readl(txq->bd.reg_desc_active) || 785 !readl(txq->bd.reg_desc_active) || 786 !readl(txq->bd.reg_desc_active) || 787 !readl(txq->bd.reg_desc_active)) 788 writel(0, txq->bd.reg_desc_active); 789 790 return 0; 791 792 err_release: 793 /* TODO: Release all used data descriptors for TSO */ 794 return ret; 795 } 796 797 static netdev_tx_t 798 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 799 { 800 struct fec_enet_private *fep = netdev_priv(ndev); 801 int entries_free; 802 unsigned short queue; 803 struct fec_enet_priv_tx_q *txq; 804 struct netdev_queue *nq; 805 int ret; 806 807 queue = skb_get_queue_mapping(skb); 808 txq = fep->tx_queue[queue]; 809 nq = netdev_get_tx_queue(ndev, queue); 810 811 if (skb_is_gso(skb)) 812 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 813 else 814 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 815 if (ret) 816 return ret; 817 818 entries_free = fec_enet_get_free_txdesc_num(txq); 819 if (entries_free <= txq->tx_stop_threshold) 820 netif_tx_stop_queue(nq); 821 822 return NETDEV_TX_OK; 823 } 824 825 /* Init RX & TX buffer descriptors 826 */ 827 static void fec_enet_bd_init(struct net_device *dev) 828 { 829 struct fec_enet_private *fep = netdev_priv(dev); 830 struct fec_enet_priv_tx_q *txq; 831 struct fec_enet_priv_rx_q *rxq; 832 struct bufdesc *bdp; 833 unsigned int i; 834 unsigned int q; 835 836 for (q = 0; q < fep->num_rx_queues; q++) { 837 /* Initialize the receive buffer descriptors. */ 838 rxq = fep->rx_queue[q]; 839 bdp = rxq->bd.base; 840 841 for (i = 0; i < rxq->bd.ring_size; i++) { 842 843 /* Initialize the BD for every fragment in the page. */ 844 if (bdp->cbd_bufaddr) 845 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 846 else 847 bdp->cbd_sc = cpu_to_fec16(0); 848 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 849 } 850 851 /* Set the last buffer to wrap */ 852 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 853 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 854 855 rxq->bd.cur = rxq->bd.base; 856 } 857 858 for (q = 0; q < fep->num_tx_queues; q++) { 859 /* ...and the same for transmit */ 860 txq = fep->tx_queue[q]; 861 bdp = txq->bd.base; 862 txq->bd.cur = bdp; 863 864 for (i = 0; i < txq->bd.ring_size; i++) { 865 /* Initialize the BD for every fragment in the page. */ 866 bdp->cbd_sc = cpu_to_fec16(0); 867 if (bdp->cbd_bufaddr && 868 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 869 dma_unmap_single(&fep->pdev->dev, 870 fec32_to_cpu(bdp->cbd_bufaddr), 871 fec16_to_cpu(bdp->cbd_datlen), 872 DMA_TO_DEVICE); 873 if (txq->tx_skbuff[i]) { 874 dev_kfree_skb_any(txq->tx_skbuff[i]); 875 txq->tx_skbuff[i] = NULL; 876 } 877 bdp->cbd_bufaddr = cpu_to_fec32(0); 878 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 879 } 880 881 /* Set the last buffer to wrap */ 882 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 883 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 884 txq->dirty_tx = bdp; 885 } 886 } 887 888 static void fec_enet_active_rxring(struct net_device *ndev) 889 { 890 struct fec_enet_private *fep = netdev_priv(ndev); 891 int i; 892 893 for (i = 0; i < fep->num_rx_queues; i++) 894 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 895 } 896 897 static void fec_enet_enable_ring(struct net_device *ndev) 898 { 899 struct fec_enet_private *fep = netdev_priv(ndev); 900 struct fec_enet_priv_tx_q *txq; 901 struct fec_enet_priv_rx_q *rxq; 902 int i; 903 904 for (i = 0; i < fep->num_rx_queues; i++) { 905 rxq = fep->rx_queue[i]; 906 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 907 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 908 909 /* enable DMA1/2 */ 910 if (i) 911 writel(RCMR_MATCHEN | RCMR_CMP(i), 912 fep->hwp + FEC_RCMR(i)); 913 } 914 915 for (i = 0; i < fep->num_tx_queues; i++) { 916 txq = fep->tx_queue[i]; 917 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 918 919 /* enable DMA1/2 */ 920 if (i) 921 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 922 fep->hwp + FEC_DMA_CFG(i)); 923 } 924 } 925 926 static void fec_enet_reset_skb(struct net_device *ndev) 927 { 928 struct fec_enet_private *fep = netdev_priv(ndev); 929 struct fec_enet_priv_tx_q *txq; 930 int i, j; 931 932 for (i = 0; i < fep->num_tx_queues; i++) { 933 txq = fep->tx_queue[i]; 934 935 for (j = 0; j < txq->bd.ring_size; j++) { 936 if (txq->tx_skbuff[j]) { 937 dev_kfree_skb_any(txq->tx_skbuff[j]); 938 txq->tx_skbuff[j] = NULL; 939 } 940 } 941 } 942 } 943 944 /* 945 * This function is called to start or restart the FEC during a link 946 * change, transmit timeout, or to reconfigure the FEC. The network 947 * packet processing for this device must be stopped before this call. 948 */ 949 static void 950 fec_restart(struct net_device *ndev) 951 { 952 struct fec_enet_private *fep = netdev_priv(ndev); 953 u32 val; 954 u32 temp_mac[2]; 955 u32 rcntl = OPT_FRAME_SIZE | 0x04; 956 u32 ecntl = 0x2; /* ETHEREN */ 957 958 /* Whack a reset. We should wait for this. 959 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 960 * instead of reset MAC itself. 961 */ 962 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 963 writel(0, fep->hwp + FEC_ECNTRL); 964 } else { 965 writel(1, fep->hwp + FEC_ECNTRL); 966 udelay(10); 967 } 968 969 /* 970 * enet-mac reset will reset mac address registers too, 971 * so need to reconfigure it. 972 */ 973 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 974 writel((__force u32)cpu_to_be32(temp_mac[0]), 975 fep->hwp + FEC_ADDR_LOW); 976 writel((__force u32)cpu_to_be32(temp_mac[1]), 977 fep->hwp + FEC_ADDR_HIGH); 978 979 /* Clear any outstanding interrupt. */ 980 writel(0xffffffff, fep->hwp + FEC_IEVENT); 981 982 fec_enet_bd_init(ndev); 983 984 fec_enet_enable_ring(ndev); 985 986 /* Reset tx SKB buffers. */ 987 fec_enet_reset_skb(ndev); 988 989 /* Enable MII mode */ 990 if (fep->full_duplex == DUPLEX_FULL) { 991 /* FD enable */ 992 writel(0x04, fep->hwp + FEC_X_CNTRL); 993 } else { 994 /* No Rcv on Xmit */ 995 rcntl |= 0x02; 996 writel(0x0, fep->hwp + FEC_X_CNTRL); 997 } 998 999 /* Set MII speed */ 1000 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1001 1002 #if !defined(CONFIG_M5272) 1003 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1004 val = readl(fep->hwp + FEC_RACC); 1005 /* align IP header */ 1006 val |= FEC_RACC_SHIFT16; 1007 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1008 /* set RX checksum */ 1009 val |= FEC_RACC_OPTIONS; 1010 else 1011 val &= ~FEC_RACC_OPTIONS; 1012 writel(val, fep->hwp + FEC_RACC); 1013 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1014 } 1015 #endif 1016 1017 /* 1018 * The phy interface and speed need to get configured 1019 * differently on enet-mac. 1020 */ 1021 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1022 /* Enable flow control and length check */ 1023 rcntl |= 0x40000000 | 0x00000020; 1024 1025 /* RGMII, RMII or MII */ 1026 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1027 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1028 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1029 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1030 rcntl |= (1 << 6); 1031 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1032 rcntl |= (1 << 8); 1033 else 1034 rcntl &= ~(1 << 8); 1035 1036 /* 1G, 100M or 10M */ 1037 if (ndev->phydev) { 1038 if (ndev->phydev->speed == SPEED_1000) 1039 ecntl |= (1 << 5); 1040 else if (ndev->phydev->speed == SPEED_100) 1041 rcntl &= ~(1 << 9); 1042 else 1043 rcntl |= (1 << 9); 1044 } 1045 } else { 1046 #ifdef FEC_MIIGSK_ENR 1047 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1048 u32 cfgr; 1049 /* disable the gasket and wait */ 1050 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1051 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1052 udelay(1); 1053 1054 /* 1055 * configure the gasket: 1056 * RMII, 50 MHz, no loopback, no echo 1057 * MII, 25 MHz, no loopback, no echo 1058 */ 1059 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1060 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1061 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1062 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1063 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1064 1065 /* re-enable the gasket */ 1066 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1067 } 1068 #endif 1069 } 1070 1071 #if !defined(CONFIG_M5272) 1072 /* enable pause frame*/ 1073 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1074 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1075 ndev->phydev && ndev->phydev->pause)) { 1076 rcntl |= FEC_ENET_FCE; 1077 1078 /* set FIFO threshold parameter to reduce overrun */ 1079 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1080 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1081 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1082 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1083 1084 /* OPD */ 1085 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1086 } else { 1087 rcntl &= ~FEC_ENET_FCE; 1088 } 1089 #endif /* !defined(CONFIG_M5272) */ 1090 1091 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1092 1093 /* Setup multicast filter. */ 1094 set_multicast_list(ndev); 1095 #ifndef CONFIG_M5272 1096 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1097 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1098 #endif 1099 1100 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1101 /* enable ENET endian swap */ 1102 ecntl |= (1 << 8); 1103 /* enable ENET store and forward mode */ 1104 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1105 } 1106 1107 if (fep->bufdesc_ex) 1108 ecntl |= (1 << 4); 1109 1110 #ifndef CONFIG_M5272 1111 /* Enable the MIB statistic event counters */ 1112 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1113 #endif 1114 1115 /* And last, enable the transmit and receive processing */ 1116 writel(ecntl, fep->hwp + FEC_ECNTRL); 1117 fec_enet_active_rxring(ndev); 1118 1119 if (fep->bufdesc_ex) 1120 fec_ptp_start_cyclecounter(ndev); 1121 1122 /* Enable interrupts we wish to service */ 1123 if (fep->link) 1124 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1125 else 1126 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); 1127 1128 /* Init the interrupt coalescing */ 1129 fec_enet_itr_coal_init(ndev); 1130 1131 } 1132 1133 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1134 { 1135 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1136 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1137 1138 if (stop_gpr->gpr) { 1139 if (enabled) 1140 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1141 BIT(stop_gpr->bit), 1142 BIT(stop_gpr->bit)); 1143 else 1144 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1145 BIT(stop_gpr->bit), 0); 1146 } else if (pdata && pdata->sleep_mode_enable) { 1147 pdata->sleep_mode_enable(enabled); 1148 } 1149 } 1150 1151 static void 1152 fec_stop(struct net_device *ndev) 1153 { 1154 struct fec_enet_private *fep = netdev_priv(ndev); 1155 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1156 u32 val; 1157 1158 /* We cannot expect a graceful transmit stop without link !!! */ 1159 if (fep->link) { 1160 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1161 udelay(10); 1162 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1163 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1164 } 1165 1166 /* Whack a reset. We should wait for this. 1167 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1168 * instead of reset MAC itself. 1169 */ 1170 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1171 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 1172 writel(0, fep->hwp + FEC_ECNTRL); 1173 } else { 1174 writel(1, fep->hwp + FEC_ECNTRL); 1175 udelay(10); 1176 } 1177 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1178 } else { 1179 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1180 val = readl(fep->hwp + FEC_ECNTRL); 1181 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1182 writel(val, fep->hwp + FEC_ECNTRL); 1183 fec_enet_stop_mode(fep, true); 1184 } 1185 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1186 1187 /* We have to keep ENET enabled to have MII interrupt stay working */ 1188 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1189 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1190 writel(2, fep->hwp + FEC_ECNTRL); 1191 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1192 } 1193 } 1194 1195 1196 static void 1197 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1198 { 1199 struct fec_enet_private *fep = netdev_priv(ndev); 1200 1201 fec_dump(ndev); 1202 1203 ndev->stats.tx_errors++; 1204 1205 schedule_work(&fep->tx_timeout_work); 1206 } 1207 1208 static void fec_enet_timeout_work(struct work_struct *work) 1209 { 1210 struct fec_enet_private *fep = 1211 container_of(work, struct fec_enet_private, tx_timeout_work); 1212 struct net_device *ndev = fep->netdev; 1213 1214 rtnl_lock(); 1215 if (netif_device_present(ndev) || netif_running(ndev)) { 1216 napi_disable(&fep->napi); 1217 netif_tx_lock_bh(ndev); 1218 fec_restart(ndev); 1219 netif_tx_wake_all_queues(ndev); 1220 netif_tx_unlock_bh(ndev); 1221 napi_enable(&fep->napi); 1222 } 1223 rtnl_unlock(); 1224 } 1225 1226 static void 1227 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1228 struct skb_shared_hwtstamps *hwtstamps) 1229 { 1230 unsigned long flags; 1231 u64 ns; 1232 1233 spin_lock_irqsave(&fep->tmreg_lock, flags); 1234 ns = timecounter_cyc2time(&fep->tc, ts); 1235 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1236 1237 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1238 hwtstamps->hwtstamp = ns_to_ktime(ns); 1239 } 1240 1241 static void 1242 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1243 { 1244 struct fec_enet_private *fep; 1245 struct bufdesc *bdp; 1246 unsigned short status; 1247 struct sk_buff *skb; 1248 struct fec_enet_priv_tx_q *txq; 1249 struct netdev_queue *nq; 1250 int index = 0; 1251 int entries_free; 1252 1253 fep = netdev_priv(ndev); 1254 1255 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1256 1257 txq = fep->tx_queue[queue_id]; 1258 /* get next bdp of dirty_tx */ 1259 nq = netdev_get_tx_queue(ndev, queue_id); 1260 bdp = txq->dirty_tx; 1261 1262 /* get next bdp of dirty_tx */ 1263 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1264 1265 while (bdp != READ_ONCE(txq->bd.cur)) { 1266 /* Order the load of bd.cur and cbd_sc */ 1267 rmb(); 1268 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1269 if (status & BD_ENET_TX_READY) 1270 break; 1271 1272 index = fec_enet_get_bd_index(bdp, &txq->bd); 1273 1274 skb = txq->tx_skbuff[index]; 1275 txq->tx_skbuff[index] = NULL; 1276 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1277 dma_unmap_single(&fep->pdev->dev, 1278 fec32_to_cpu(bdp->cbd_bufaddr), 1279 fec16_to_cpu(bdp->cbd_datlen), 1280 DMA_TO_DEVICE); 1281 bdp->cbd_bufaddr = cpu_to_fec32(0); 1282 if (!skb) 1283 goto skb_done; 1284 1285 /* Check for errors. */ 1286 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1287 BD_ENET_TX_RL | BD_ENET_TX_UN | 1288 BD_ENET_TX_CSL)) { 1289 ndev->stats.tx_errors++; 1290 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1291 ndev->stats.tx_heartbeat_errors++; 1292 if (status & BD_ENET_TX_LC) /* Late collision */ 1293 ndev->stats.tx_window_errors++; 1294 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1295 ndev->stats.tx_aborted_errors++; 1296 if (status & BD_ENET_TX_UN) /* Underrun */ 1297 ndev->stats.tx_fifo_errors++; 1298 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1299 ndev->stats.tx_carrier_errors++; 1300 } else { 1301 ndev->stats.tx_packets++; 1302 ndev->stats.tx_bytes += skb->len; 1303 } 1304 1305 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 1306 fep->bufdesc_ex) { 1307 struct skb_shared_hwtstamps shhwtstamps; 1308 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1309 1310 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1311 skb_tstamp_tx(skb, &shhwtstamps); 1312 } 1313 1314 /* Deferred means some collisions occurred during transmit, 1315 * but we eventually sent the packet OK. 1316 */ 1317 if (status & BD_ENET_TX_DEF) 1318 ndev->stats.collisions++; 1319 1320 /* Free the sk buffer associated with this last transmit */ 1321 dev_kfree_skb_any(skb); 1322 skb_done: 1323 /* Make sure the update to bdp and tx_skbuff are performed 1324 * before dirty_tx 1325 */ 1326 wmb(); 1327 txq->dirty_tx = bdp; 1328 1329 /* Update pointer to next buffer descriptor to be transmitted */ 1330 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1331 1332 /* Since we have freed up a buffer, the ring is no longer full 1333 */ 1334 if (netif_tx_queue_stopped(nq)) { 1335 entries_free = fec_enet_get_free_txdesc_num(txq); 1336 if (entries_free >= txq->tx_wake_threshold) 1337 netif_tx_wake_queue(nq); 1338 } 1339 } 1340 1341 /* ERR006358: Keep the transmitter going */ 1342 if (bdp != txq->bd.cur && 1343 readl(txq->bd.reg_desc_active) == 0) 1344 writel(0, txq->bd.reg_desc_active); 1345 } 1346 1347 static void 1348 fec_enet_tx(struct net_device *ndev) 1349 { 1350 struct fec_enet_private *fep = netdev_priv(ndev); 1351 u16 queue_id; 1352 /* First process class A queue, then Class B and Best Effort queue */ 1353 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) { 1354 clear_bit(queue_id, &fep->work_tx); 1355 fec_enet_tx_queue(ndev, queue_id); 1356 } 1357 return; 1358 } 1359 1360 static int 1361 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1362 { 1363 struct fec_enet_private *fep = netdev_priv(ndev); 1364 int off; 1365 1366 off = ((unsigned long)skb->data) & fep->rx_align; 1367 if (off) 1368 skb_reserve(skb, fep->rx_align + 1 - off); 1369 1370 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1371 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1372 if (net_ratelimit()) 1373 netdev_err(ndev, "Rx DMA memory map failed\n"); 1374 return -ENOMEM; 1375 } 1376 1377 return 0; 1378 } 1379 1380 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1381 struct bufdesc *bdp, u32 length, bool swap) 1382 { 1383 struct fec_enet_private *fep = netdev_priv(ndev); 1384 struct sk_buff *new_skb; 1385 1386 if (length > fep->rx_copybreak) 1387 return false; 1388 1389 new_skb = netdev_alloc_skb(ndev, length); 1390 if (!new_skb) 1391 return false; 1392 1393 dma_sync_single_for_cpu(&fep->pdev->dev, 1394 fec32_to_cpu(bdp->cbd_bufaddr), 1395 FEC_ENET_RX_FRSIZE - fep->rx_align, 1396 DMA_FROM_DEVICE); 1397 if (!swap) 1398 memcpy(new_skb->data, (*skb)->data, length); 1399 else 1400 swap_buffer2(new_skb->data, (*skb)->data, length); 1401 *skb = new_skb; 1402 1403 return true; 1404 } 1405 1406 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1407 * When we update through the ring, if the next incoming buffer has 1408 * not been given to the system, we just set the empty indicator, 1409 * effectively tossing the packet. 1410 */ 1411 static int 1412 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1413 { 1414 struct fec_enet_private *fep = netdev_priv(ndev); 1415 struct fec_enet_priv_rx_q *rxq; 1416 struct bufdesc *bdp; 1417 unsigned short status; 1418 struct sk_buff *skb_new = NULL; 1419 struct sk_buff *skb; 1420 ushort pkt_len; 1421 __u8 *data; 1422 int pkt_received = 0; 1423 struct bufdesc_ex *ebdp = NULL; 1424 bool vlan_packet_rcvd = false; 1425 u16 vlan_tag; 1426 int index = 0; 1427 bool is_copybreak; 1428 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1429 1430 #ifdef CONFIG_M532x 1431 flush_cache_all(); 1432 #endif 1433 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1434 rxq = fep->rx_queue[queue_id]; 1435 1436 /* First, grab all of the stats for the incoming packet. 1437 * These get messed up if we get called due to a busy condition. 1438 */ 1439 bdp = rxq->bd.cur; 1440 1441 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1442 1443 if (pkt_received >= budget) 1444 break; 1445 pkt_received++; 1446 1447 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); 1448 1449 /* Check for errors. */ 1450 status ^= BD_ENET_RX_LAST; 1451 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1452 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1453 BD_ENET_RX_CL)) { 1454 ndev->stats.rx_errors++; 1455 if (status & BD_ENET_RX_OV) { 1456 /* FIFO overrun */ 1457 ndev->stats.rx_fifo_errors++; 1458 goto rx_processing_done; 1459 } 1460 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1461 | BD_ENET_RX_LAST)) { 1462 /* Frame too long or too short. */ 1463 ndev->stats.rx_length_errors++; 1464 if (status & BD_ENET_RX_LAST) 1465 netdev_err(ndev, "rcv is not +last\n"); 1466 } 1467 if (status & BD_ENET_RX_CR) /* CRC Error */ 1468 ndev->stats.rx_crc_errors++; 1469 /* Report late collisions as a frame error. */ 1470 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1471 ndev->stats.rx_frame_errors++; 1472 goto rx_processing_done; 1473 } 1474 1475 /* Process the incoming frame. */ 1476 ndev->stats.rx_packets++; 1477 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1478 ndev->stats.rx_bytes += pkt_len; 1479 1480 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1481 skb = rxq->rx_skbuff[index]; 1482 1483 /* The packet length includes FCS, but we don't want to 1484 * include that when passing upstream as it messes up 1485 * bridging applications. 1486 */ 1487 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1488 need_swap); 1489 if (!is_copybreak) { 1490 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1491 if (unlikely(!skb_new)) { 1492 ndev->stats.rx_dropped++; 1493 goto rx_processing_done; 1494 } 1495 dma_unmap_single(&fep->pdev->dev, 1496 fec32_to_cpu(bdp->cbd_bufaddr), 1497 FEC_ENET_RX_FRSIZE - fep->rx_align, 1498 DMA_FROM_DEVICE); 1499 } 1500 1501 prefetch(skb->data - NET_IP_ALIGN); 1502 skb_put(skb, pkt_len - 4); 1503 data = skb->data; 1504 1505 if (!is_copybreak && need_swap) 1506 swap_buffer(data, pkt_len); 1507 1508 #if !defined(CONFIG_M5272) 1509 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1510 data = skb_pull_inline(skb, 2); 1511 #endif 1512 1513 /* Extract the enhanced buffer descriptor */ 1514 ebdp = NULL; 1515 if (fep->bufdesc_ex) 1516 ebdp = (struct bufdesc_ex *)bdp; 1517 1518 /* If this is a VLAN packet remove the VLAN Tag */ 1519 vlan_packet_rcvd = false; 1520 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1521 fep->bufdesc_ex && 1522 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1523 /* Push and remove the vlan tag */ 1524 struct vlan_hdr *vlan_header = 1525 (struct vlan_hdr *) (data + ETH_HLEN); 1526 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1527 1528 vlan_packet_rcvd = true; 1529 1530 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1531 skb_pull(skb, VLAN_HLEN); 1532 } 1533 1534 skb->protocol = eth_type_trans(skb, ndev); 1535 1536 /* Get receive timestamp from the skb */ 1537 if (fep->hwts_rx_en && fep->bufdesc_ex) 1538 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1539 skb_hwtstamps(skb)); 1540 1541 if (fep->bufdesc_ex && 1542 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1543 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1544 /* don't check it */ 1545 skb->ip_summed = CHECKSUM_UNNECESSARY; 1546 } else { 1547 skb_checksum_none_assert(skb); 1548 } 1549 } 1550 1551 /* Handle received VLAN packets */ 1552 if (vlan_packet_rcvd) 1553 __vlan_hwaccel_put_tag(skb, 1554 htons(ETH_P_8021Q), 1555 vlan_tag); 1556 1557 napi_gro_receive(&fep->napi, skb); 1558 1559 if (is_copybreak) { 1560 dma_sync_single_for_device(&fep->pdev->dev, 1561 fec32_to_cpu(bdp->cbd_bufaddr), 1562 FEC_ENET_RX_FRSIZE - fep->rx_align, 1563 DMA_FROM_DEVICE); 1564 } else { 1565 rxq->rx_skbuff[index] = skb_new; 1566 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1567 } 1568 1569 rx_processing_done: 1570 /* Clear the status flags for this buffer */ 1571 status &= ~BD_ENET_RX_STATS; 1572 1573 /* Mark the buffer empty */ 1574 status |= BD_ENET_RX_EMPTY; 1575 1576 if (fep->bufdesc_ex) { 1577 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1578 1579 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1580 ebdp->cbd_prot = 0; 1581 ebdp->cbd_bdu = 0; 1582 } 1583 /* Make sure the updates to rest of the descriptor are 1584 * performed before transferring ownership. 1585 */ 1586 wmb(); 1587 bdp->cbd_sc = cpu_to_fec16(status); 1588 1589 /* Update BD pointer to next entry */ 1590 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1591 1592 /* Doing this here will keep the FEC running while we process 1593 * incoming frames. On a heavily loaded network, we should be 1594 * able to keep up at the expense of system resources. 1595 */ 1596 writel(0, rxq->bd.reg_desc_active); 1597 } 1598 rxq->bd.cur = bdp; 1599 return pkt_received; 1600 } 1601 1602 static int 1603 fec_enet_rx(struct net_device *ndev, int budget) 1604 { 1605 int pkt_received = 0; 1606 u16 queue_id; 1607 struct fec_enet_private *fep = netdev_priv(ndev); 1608 1609 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) { 1610 int ret; 1611 1612 ret = fec_enet_rx_queue(ndev, 1613 budget - pkt_received, queue_id); 1614 1615 if (ret < budget - pkt_received) 1616 clear_bit(queue_id, &fep->work_rx); 1617 1618 pkt_received += ret; 1619 } 1620 return pkt_received; 1621 } 1622 1623 static bool 1624 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events) 1625 { 1626 if (int_events == 0) 1627 return false; 1628 1629 if (int_events & FEC_ENET_RXF_0) 1630 fep->work_rx |= (1 << 2); 1631 if (int_events & FEC_ENET_RXF_1) 1632 fep->work_rx |= (1 << 0); 1633 if (int_events & FEC_ENET_RXF_2) 1634 fep->work_rx |= (1 << 1); 1635 1636 if (int_events & FEC_ENET_TXF_0) 1637 fep->work_tx |= (1 << 2); 1638 if (int_events & FEC_ENET_TXF_1) 1639 fep->work_tx |= (1 << 0); 1640 if (int_events & FEC_ENET_TXF_2) 1641 fep->work_tx |= (1 << 1); 1642 1643 return true; 1644 } 1645 1646 static irqreturn_t 1647 fec_enet_interrupt(int irq, void *dev_id) 1648 { 1649 struct net_device *ndev = dev_id; 1650 struct fec_enet_private *fep = netdev_priv(ndev); 1651 uint int_events; 1652 irqreturn_t ret = IRQ_NONE; 1653 1654 int_events = readl(fep->hwp + FEC_IEVENT); 1655 writel(int_events, fep->hwp + FEC_IEVENT); 1656 fec_enet_collect_events(fep, int_events); 1657 1658 if ((fep->work_tx || fep->work_rx) && fep->link) { 1659 ret = IRQ_HANDLED; 1660 1661 if (napi_schedule_prep(&fep->napi)) { 1662 /* Disable the NAPI interrupts */ 1663 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK); 1664 __napi_schedule(&fep->napi); 1665 } 1666 } 1667 1668 if (int_events & FEC_ENET_MII) { 1669 ret = IRQ_HANDLED; 1670 complete(&fep->mdio_done); 1671 } 1672 return ret; 1673 } 1674 1675 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1676 { 1677 struct net_device *ndev = napi->dev; 1678 struct fec_enet_private *fep = netdev_priv(ndev); 1679 int pkts; 1680 1681 pkts = fec_enet_rx(ndev, budget); 1682 1683 fec_enet_tx(ndev); 1684 1685 if (pkts < budget) { 1686 napi_complete_done(napi, pkts); 1687 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1688 } 1689 return pkts; 1690 } 1691 1692 /* ------------------------------------------------------------------------- */ 1693 static void fec_get_mac(struct net_device *ndev) 1694 { 1695 struct fec_enet_private *fep = netdev_priv(ndev); 1696 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1697 unsigned char *iap, tmpaddr[ETH_ALEN]; 1698 1699 /* 1700 * try to get mac address in following order: 1701 * 1702 * 1) module parameter via kernel command line in form 1703 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1704 */ 1705 iap = macaddr; 1706 1707 /* 1708 * 2) from device tree data 1709 */ 1710 if (!is_valid_ether_addr(iap)) { 1711 struct device_node *np = fep->pdev->dev.of_node; 1712 if (np) { 1713 const char *mac = of_get_mac_address(np); 1714 if (!IS_ERR(mac)) 1715 iap = (unsigned char *) mac; 1716 } 1717 } 1718 1719 /* 1720 * 3) from flash or fuse (via platform data) 1721 */ 1722 if (!is_valid_ether_addr(iap)) { 1723 #ifdef CONFIG_M5272 1724 if (FEC_FLASHMAC) 1725 iap = (unsigned char *)FEC_FLASHMAC; 1726 #else 1727 if (pdata) 1728 iap = (unsigned char *)&pdata->mac; 1729 #endif 1730 } 1731 1732 /* 1733 * 4) FEC mac registers set by bootloader 1734 */ 1735 if (!is_valid_ether_addr(iap)) { 1736 *((__be32 *) &tmpaddr[0]) = 1737 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1738 *((__be16 *) &tmpaddr[4]) = 1739 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1740 iap = &tmpaddr[0]; 1741 } 1742 1743 /* 1744 * 5) random mac address 1745 */ 1746 if (!is_valid_ether_addr(iap)) { 1747 /* Report it and use a random ethernet address instead */ 1748 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1749 eth_hw_addr_random(ndev); 1750 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1751 ndev->dev_addr); 1752 return; 1753 } 1754 1755 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1756 1757 /* Adjust MAC if using macaddr */ 1758 if (iap == macaddr) 1759 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1760 } 1761 1762 /* ------------------------------------------------------------------------- */ 1763 1764 /* 1765 * Phy section 1766 */ 1767 static void fec_enet_adjust_link(struct net_device *ndev) 1768 { 1769 struct fec_enet_private *fep = netdev_priv(ndev); 1770 struct phy_device *phy_dev = ndev->phydev; 1771 int status_change = 0; 1772 1773 /* 1774 * If the netdev is down, or is going down, we're not interested 1775 * in link state events, so just mark our idea of the link as down 1776 * and ignore the event. 1777 */ 1778 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1779 fep->link = 0; 1780 } else if (phy_dev->link) { 1781 if (!fep->link) { 1782 fep->link = phy_dev->link; 1783 status_change = 1; 1784 } 1785 1786 if (fep->full_duplex != phy_dev->duplex) { 1787 fep->full_duplex = phy_dev->duplex; 1788 status_change = 1; 1789 } 1790 1791 if (phy_dev->speed != fep->speed) { 1792 fep->speed = phy_dev->speed; 1793 status_change = 1; 1794 } 1795 1796 /* if any of the above changed restart the FEC */ 1797 if (status_change) { 1798 napi_disable(&fep->napi); 1799 netif_tx_lock_bh(ndev); 1800 fec_restart(ndev); 1801 netif_tx_wake_all_queues(ndev); 1802 netif_tx_unlock_bh(ndev); 1803 napi_enable(&fep->napi); 1804 } 1805 } else { 1806 if (fep->link) { 1807 napi_disable(&fep->napi); 1808 netif_tx_lock_bh(ndev); 1809 fec_stop(ndev); 1810 netif_tx_unlock_bh(ndev); 1811 napi_enable(&fep->napi); 1812 fep->link = phy_dev->link; 1813 status_change = 1; 1814 } 1815 } 1816 1817 if (status_change) 1818 phy_print_status(phy_dev); 1819 } 1820 1821 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1822 { 1823 struct fec_enet_private *fep = bus->priv; 1824 struct device *dev = &fep->pdev->dev; 1825 unsigned long time_left; 1826 int ret = 0, frame_start, frame_addr, frame_op; 1827 bool is_c45 = !!(regnum & MII_ADDR_C45); 1828 1829 ret = pm_runtime_get_sync(dev); 1830 if (ret < 0) 1831 return ret; 1832 1833 reinit_completion(&fep->mdio_done); 1834 1835 if (is_c45) { 1836 frame_start = FEC_MMFR_ST_C45; 1837 1838 /* write address */ 1839 frame_addr = (regnum >> 16); 1840 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1841 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1842 FEC_MMFR_TA | (regnum & 0xFFFF), 1843 fep->hwp + FEC_MII_DATA); 1844 1845 /* wait for end of transfer */ 1846 time_left = wait_for_completion_timeout(&fep->mdio_done, 1847 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1848 if (time_left == 0) { 1849 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1850 ret = -ETIMEDOUT; 1851 goto out; 1852 } 1853 1854 frame_op = FEC_MMFR_OP_READ_C45; 1855 1856 } else { 1857 /* C22 read */ 1858 frame_op = FEC_MMFR_OP_READ; 1859 frame_start = FEC_MMFR_ST; 1860 frame_addr = regnum; 1861 } 1862 1863 /* start a read op */ 1864 writel(frame_start | frame_op | 1865 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1866 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1867 1868 /* wait for end of transfer */ 1869 time_left = wait_for_completion_timeout(&fep->mdio_done, 1870 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1871 if (time_left == 0) { 1872 netdev_err(fep->netdev, "MDIO read timeout\n"); 1873 ret = -ETIMEDOUT; 1874 goto out; 1875 } 1876 1877 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1878 1879 out: 1880 pm_runtime_mark_last_busy(dev); 1881 pm_runtime_put_autosuspend(dev); 1882 1883 return ret; 1884 } 1885 1886 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1887 u16 value) 1888 { 1889 struct fec_enet_private *fep = bus->priv; 1890 struct device *dev = &fep->pdev->dev; 1891 unsigned long time_left; 1892 int ret, frame_start, frame_addr; 1893 bool is_c45 = !!(regnum & MII_ADDR_C45); 1894 1895 ret = pm_runtime_get_sync(dev); 1896 if (ret < 0) 1897 return ret; 1898 else 1899 ret = 0; 1900 1901 reinit_completion(&fep->mdio_done); 1902 1903 if (is_c45) { 1904 frame_start = FEC_MMFR_ST_C45; 1905 1906 /* write address */ 1907 frame_addr = (regnum >> 16); 1908 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1909 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1910 FEC_MMFR_TA | (regnum & 0xFFFF), 1911 fep->hwp + FEC_MII_DATA); 1912 1913 /* wait for end of transfer */ 1914 time_left = wait_for_completion_timeout(&fep->mdio_done, 1915 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1916 if (time_left == 0) { 1917 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1918 ret = -ETIMEDOUT; 1919 goto out; 1920 } 1921 } else { 1922 /* C22 write */ 1923 frame_start = FEC_MMFR_ST; 1924 frame_addr = regnum; 1925 } 1926 1927 /* start a write op */ 1928 writel(frame_start | FEC_MMFR_OP_WRITE | 1929 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1930 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1931 fep->hwp + FEC_MII_DATA); 1932 1933 /* wait for end of transfer */ 1934 time_left = wait_for_completion_timeout(&fep->mdio_done, 1935 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1936 if (time_left == 0) { 1937 netdev_err(fep->netdev, "MDIO write timeout\n"); 1938 ret = -ETIMEDOUT; 1939 } 1940 1941 out: 1942 pm_runtime_mark_last_busy(dev); 1943 pm_runtime_put_autosuspend(dev); 1944 1945 return ret; 1946 } 1947 1948 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1949 { 1950 struct fec_enet_private *fep = netdev_priv(ndev); 1951 int ret; 1952 1953 if (enable) { 1954 ret = clk_prepare_enable(fep->clk_enet_out); 1955 if (ret) 1956 return ret; 1957 1958 if (fep->clk_ptp) { 1959 mutex_lock(&fep->ptp_clk_mutex); 1960 ret = clk_prepare_enable(fep->clk_ptp); 1961 if (ret) { 1962 mutex_unlock(&fep->ptp_clk_mutex); 1963 goto failed_clk_ptp; 1964 } else { 1965 fep->ptp_clk_on = true; 1966 } 1967 mutex_unlock(&fep->ptp_clk_mutex); 1968 } 1969 1970 ret = clk_prepare_enable(fep->clk_ref); 1971 if (ret) 1972 goto failed_clk_ref; 1973 1974 phy_reset_after_clk_enable(ndev->phydev); 1975 } else { 1976 clk_disable_unprepare(fep->clk_enet_out); 1977 if (fep->clk_ptp) { 1978 mutex_lock(&fep->ptp_clk_mutex); 1979 clk_disable_unprepare(fep->clk_ptp); 1980 fep->ptp_clk_on = false; 1981 mutex_unlock(&fep->ptp_clk_mutex); 1982 } 1983 clk_disable_unprepare(fep->clk_ref); 1984 } 1985 1986 return 0; 1987 1988 failed_clk_ref: 1989 if (fep->clk_ref) 1990 clk_disable_unprepare(fep->clk_ref); 1991 failed_clk_ptp: 1992 if (fep->clk_enet_out) 1993 clk_disable_unprepare(fep->clk_enet_out); 1994 1995 return ret; 1996 } 1997 1998 static int fec_enet_mii_probe(struct net_device *ndev) 1999 { 2000 struct fec_enet_private *fep = netdev_priv(ndev); 2001 struct phy_device *phy_dev = NULL; 2002 char mdio_bus_id[MII_BUS_ID_SIZE]; 2003 char phy_name[MII_BUS_ID_SIZE + 3]; 2004 int phy_id; 2005 int dev_id = fep->dev_id; 2006 2007 if (fep->phy_node) { 2008 phy_dev = of_phy_connect(ndev, fep->phy_node, 2009 &fec_enet_adjust_link, 0, 2010 fep->phy_interface); 2011 if (!phy_dev) { 2012 netdev_err(ndev, "Unable to connect to phy\n"); 2013 return -ENODEV; 2014 } 2015 } else { 2016 /* check for attached phy */ 2017 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2018 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2019 continue; 2020 if (dev_id--) 2021 continue; 2022 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2023 break; 2024 } 2025 2026 if (phy_id >= PHY_MAX_ADDR) { 2027 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2028 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2029 phy_id = 0; 2030 } 2031 2032 snprintf(phy_name, sizeof(phy_name), 2033 PHY_ID_FMT, mdio_bus_id, phy_id); 2034 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2035 fep->phy_interface); 2036 } 2037 2038 if (IS_ERR(phy_dev)) { 2039 netdev_err(ndev, "could not attach to PHY\n"); 2040 return PTR_ERR(phy_dev); 2041 } 2042 2043 /* mask with MAC supported features */ 2044 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2045 phy_set_max_speed(phy_dev, 1000); 2046 phy_remove_link_mode(phy_dev, 2047 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2048 #if !defined(CONFIG_M5272) 2049 phy_support_sym_pause(phy_dev); 2050 #endif 2051 } 2052 else 2053 phy_set_max_speed(phy_dev, 100); 2054 2055 fep->link = 0; 2056 fep->full_duplex = 0; 2057 2058 phy_attached_info(phy_dev); 2059 2060 return 0; 2061 } 2062 2063 static int fec_enet_mii_init(struct platform_device *pdev) 2064 { 2065 static struct mii_bus *fec0_mii_bus; 2066 struct net_device *ndev = platform_get_drvdata(pdev); 2067 struct fec_enet_private *fep = netdev_priv(ndev); 2068 struct device_node *node; 2069 int err = -ENXIO; 2070 u32 mii_speed, holdtime; 2071 2072 /* 2073 * The i.MX28 dual fec interfaces are not equal. 2074 * Here are the differences: 2075 * 2076 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2077 * - fec0 acts as the 1588 time master while fec1 is slave 2078 * - external phys can only be configured by fec0 2079 * 2080 * That is to say fec1 can not work independently. It only works 2081 * when fec0 is working. The reason behind this design is that the 2082 * second interface is added primarily for Switch mode. 2083 * 2084 * Because of the last point above, both phys are attached on fec0 2085 * mdio interface in board design, and need to be configured by 2086 * fec0 mii_bus. 2087 */ 2088 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2089 /* fec1 uses fec0 mii_bus */ 2090 if (mii_cnt && fec0_mii_bus) { 2091 fep->mii_bus = fec0_mii_bus; 2092 mii_cnt++; 2093 return 0; 2094 } 2095 return -ENOENT; 2096 } 2097 2098 /* 2099 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 2100 * 2101 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2102 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2103 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2104 * document. 2105 */ 2106 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000); 2107 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2108 mii_speed--; 2109 if (mii_speed > 63) { 2110 dev_err(&pdev->dev, 2111 "fec clock (%lu) too fast to get right mii speed\n", 2112 clk_get_rate(fep->clk_ipg)); 2113 err = -EINVAL; 2114 goto err_out; 2115 } 2116 2117 /* 2118 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2119 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2120 * versions are RAZ there, so just ignore the difference and write the 2121 * register always. 2122 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2123 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2124 * output. 2125 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2126 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2127 * holdtime cannot result in a value greater than 3. 2128 */ 2129 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2130 2131 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2132 2133 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2134 2135 fep->mii_bus = mdiobus_alloc(); 2136 if (fep->mii_bus == NULL) { 2137 err = -ENOMEM; 2138 goto err_out; 2139 } 2140 2141 fep->mii_bus->name = "fec_enet_mii_bus"; 2142 fep->mii_bus->read = fec_enet_mdio_read; 2143 fep->mii_bus->write = fec_enet_mdio_write; 2144 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2145 pdev->name, fep->dev_id + 1); 2146 fep->mii_bus->priv = fep; 2147 fep->mii_bus->parent = &pdev->dev; 2148 2149 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2150 err = of_mdiobus_register(fep->mii_bus, node); 2151 of_node_put(node); 2152 if (err) 2153 goto err_out_free_mdiobus; 2154 2155 mii_cnt++; 2156 2157 /* save fec0 mii_bus */ 2158 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2159 fec0_mii_bus = fep->mii_bus; 2160 2161 return 0; 2162 2163 err_out_free_mdiobus: 2164 mdiobus_free(fep->mii_bus); 2165 err_out: 2166 return err; 2167 } 2168 2169 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2170 { 2171 if (--mii_cnt == 0) { 2172 mdiobus_unregister(fep->mii_bus); 2173 mdiobus_free(fep->mii_bus); 2174 } 2175 } 2176 2177 static void fec_enet_get_drvinfo(struct net_device *ndev, 2178 struct ethtool_drvinfo *info) 2179 { 2180 struct fec_enet_private *fep = netdev_priv(ndev); 2181 2182 strlcpy(info->driver, fep->pdev->dev.driver->name, 2183 sizeof(info->driver)); 2184 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2185 } 2186 2187 static int fec_enet_get_regs_len(struct net_device *ndev) 2188 { 2189 struct fec_enet_private *fep = netdev_priv(ndev); 2190 struct resource *r; 2191 int s = 0; 2192 2193 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2194 if (r) 2195 s = resource_size(r); 2196 2197 return s; 2198 } 2199 2200 /* List of registers that can be safety be read to dump them with ethtool */ 2201 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2202 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2203 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2204 static __u32 fec_enet_register_version = 2; 2205 static u32 fec_enet_register_offset[] = { 2206 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2207 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2208 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2209 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2210 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2211 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2212 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2213 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2214 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2215 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2216 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2217 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2218 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2219 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2220 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2221 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2222 RMON_T_P_GTE2048, RMON_T_OCTETS, 2223 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2224 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2225 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2226 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2227 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2228 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2229 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2230 RMON_R_P_GTE2048, RMON_R_OCTETS, 2231 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2232 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2233 }; 2234 #else 2235 static __u32 fec_enet_register_version = 1; 2236 static u32 fec_enet_register_offset[] = { 2237 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2238 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2239 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2240 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2241 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2242 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2243 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2244 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2245 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2246 }; 2247 #endif 2248 2249 static void fec_enet_get_regs(struct net_device *ndev, 2250 struct ethtool_regs *regs, void *regbuf) 2251 { 2252 struct fec_enet_private *fep = netdev_priv(ndev); 2253 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2254 struct device *dev = &fep->pdev->dev; 2255 u32 *buf = (u32 *)regbuf; 2256 u32 i, off; 2257 int ret; 2258 2259 ret = pm_runtime_get_sync(dev); 2260 if (ret < 0) 2261 return; 2262 2263 regs->version = fec_enet_register_version; 2264 2265 memset(buf, 0, regs->len); 2266 2267 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2268 off = fec_enet_register_offset[i]; 2269 2270 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2271 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2272 continue; 2273 2274 off >>= 2; 2275 buf[off] = readl(&theregs[off]); 2276 } 2277 2278 pm_runtime_mark_last_busy(dev); 2279 pm_runtime_put_autosuspend(dev); 2280 } 2281 2282 static int fec_enet_get_ts_info(struct net_device *ndev, 2283 struct ethtool_ts_info *info) 2284 { 2285 struct fec_enet_private *fep = netdev_priv(ndev); 2286 2287 if (fep->bufdesc_ex) { 2288 2289 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2290 SOF_TIMESTAMPING_RX_SOFTWARE | 2291 SOF_TIMESTAMPING_SOFTWARE | 2292 SOF_TIMESTAMPING_TX_HARDWARE | 2293 SOF_TIMESTAMPING_RX_HARDWARE | 2294 SOF_TIMESTAMPING_RAW_HARDWARE; 2295 if (fep->ptp_clock) 2296 info->phc_index = ptp_clock_index(fep->ptp_clock); 2297 else 2298 info->phc_index = -1; 2299 2300 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2301 (1 << HWTSTAMP_TX_ON); 2302 2303 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2304 (1 << HWTSTAMP_FILTER_ALL); 2305 return 0; 2306 } else { 2307 return ethtool_op_get_ts_info(ndev, info); 2308 } 2309 } 2310 2311 #if !defined(CONFIG_M5272) 2312 2313 static void fec_enet_get_pauseparam(struct net_device *ndev, 2314 struct ethtool_pauseparam *pause) 2315 { 2316 struct fec_enet_private *fep = netdev_priv(ndev); 2317 2318 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2319 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2320 pause->rx_pause = pause->tx_pause; 2321 } 2322 2323 static int fec_enet_set_pauseparam(struct net_device *ndev, 2324 struct ethtool_pauseparam *pause) 2325 { 2326 struct fec_enet_private *fep = netdev_priv(ndev); 2327 2328 if (!ndev->phydev) 2329 return -ENODEV; 2330 2331 if (pause->tx_pause != pause->rx_pause) { 2332 netdev_info(ndev, 2333 "hardware only support enable/disable both tx and rx"); 2334 return -EINVAL; 2335 } 2336 2337 fep->pause_flag = 0; 2338 2339 /* tx pause must be same as rx pause */ 2340 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2341 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2342 2343 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2344 pause->autoneg); 2345 2346 if (pause->autoneg) { 2347 if (netif_running(ndev)) 2348 fec_stop(ndev); 2349 phy_start_aneg(ndev->phydev); 2350 } 2351 if (netif_running(ndev)) { 2352 napi_disable(&fep->napi); 2353 netif_tx_lock_bh(ndev); 2354 fec_restart(ndev); 2355 netif_tx_wake_all_queues(ndev); 2356 netif_tx_unlock_bh(ndev); 2357 napi_enable(&fep->napi); 2358 } 2359 2360 return 0; 2361 } 2362 2363 static const struct fec_stat { 2364 char name[ETH_GSTRING_LEN]; 2365 u16 offset; 2366 } fec_stats[] = { 2367 /* RMON TX */ 2368 { "tx_dropped", RMON_T_DROP }, 2369 { "tx_packets", RMON_T_PACKETS }, 2370 { "tx_broadcast", RMON_T_BC_PKT }, 2371 { "tx_multicast", RMON_T_MC_PKT }, 2372 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2373 { "tx_undersize", RMON_T_UNDERSIZE }, 2374 { "tx_oversize", RMON_T_OVERSIZE }, 2375 { "tx_fragment", RMON_T_FRAG }, 2376 { "tx_jabber", RMON_T_JAB }, 2377 { "tx_collision", RMON_T_COL }, 2378 { "tx_64byte", RMON_T_P64 }, 2379 { "tx_65to127byte", RMON_T_P65TO127 }, 2380 { "tx_128to255byte", RMON_T_P128TO255 }, 2381 { "tx_256to511byte", RMON_T_P256TO511 }, 2382 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2383 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2384 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2385 { "tx_octets", RMON_T_OCTETS }, 2386 2387 /* IEEE TX */ 2388 { "IEEE_tx_drop", IEEE_T_DROP }, 2389 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2390 { "IEEE_tx_1col", IEEE_T_1COL }, 2391 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2392 { "IEEE_tx_def", IEEE_T_DEF }, 2393 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2394 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2395 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2396 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2397 { "IEEE_tx_sqe", IEEE_T_SQE }, 2398 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2399 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2400 2401 /* RMON RX */ 2402 { "rx_packets", RMON_R_PACKETS }, 2403 { "rx_broadcast", RMON_R_BC_PKT }, 2404 { "rx_multicast", RMON_R_MC_PKT }, 2405 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2406 { "rx_undersize", RMON_R_UNDERSIZE }, 2407 { "rx_oversize", RMON_R_OVERSIZE }, 2408 { "rx_fragment", RMON_R_FRAG }, 2409 { "rx_jabber", RMON_R_JAB }, 2410 { "rx_64byte", RMON_R_P64 }, 2411 { "rx_65to127byte", RMON_R_P65TO127 }, 2412 { "rx_128to255byte", RMON_R_P128TO255 }, 2413 { "rx_256to511byte", RMON_R_P256TO511 }, 2414 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2415 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2416 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2417 { "rx_octets", RMON_R_OCTETS }, 2418 2419 /* IEEE RX */ 2420 { "IEEE_rx_drop", IEEE_R_DROP }, 2421 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2422 { "IEEE_rx_crc", IEEE_R_CRC }, 2423 { "IEEE_rx_align", IEEE_R_ALIGN }, 2424 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2425 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2426 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2427 }; 2428 2429 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2430 2431 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2432 { 2433 struct fec_enet_private *fep = netdev_priv(dev); 2434 int i; 2435 2436 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2437 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2438 } 2439 2440 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2441 struct ethtool_stats *stats, u64 *data) 2442 { 2443 struct fec_enet_private *fep = netdev_priv(dev); 2444 2445 if (netif_running(dev)) 2446 fec_enet_update_ethtool_stats(dev); 2447 2448 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2449 } 2450 2451 static void fec_enet_get_strings(struct net_device *netdev, 2452 u32 stringset, u8 *data) 2453 { 2454 int i; 2455 switch (stringset) { 2456 case ETH_SS_STATS: 2457 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2458 memcpy(data + i * ETH_GSTRING_LEN, 2459 fec_stats[i].name, ETH_GSTRING_LEN); 2460 break; 2461 } 2462 } 2463 2464 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2465 { 2466 switch (sset) { 2467 case ETH_SS_STATS: 2468 return ARRAY_SIZE(fec_stats); 2469 default: 2470 return -EOPNOTSUPP; 2471 } 2472 } 2473 2474 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2475 { 2476 struct fec_enet_private *fep = netdev_priv(dev); 2477 int i; 2478 2479 /* Disable MIB statistics counters */ 2480 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2481 2482 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2483 writel(0, fep->hwp + fec_stats[i].offset); 2484 2485 /* Don't disable MIB statistics counters */ 2486 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2487 } 2488 2489 #else /* !defined(CONFIG_M5272) */ 2490 #define FEC_STATS_SIZE 0 2491 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2492 { 2493 } 2494 2495 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2496 { 2497 } 2498 #endif /* !defined(CONFIG_M5272) */ 2499 2500 /* ITR clock source is enet system clock (clk_ahb). 2501 * TCTT unit is cycle_ns * 64 cycle 2502 * So, the ICTT value = X us / (cycle_ns * 64) 2503 */ 2504 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2505 { 2506 struct fec_enet_private *fep = netdev_priv(ndev); 2507 2508 return us * (fep->itr_clk_rate / 64000) / 1000; 2509 } 2510 2511 /* Set threshold for interrupt coalescing */ 2512 static void fec_enet_itr_coal_set(struct net_device *ndev) 2513 { 2514 struct fec_enet_private *fep = netdev_priv(ndev); 2515 int rx_itr, tx_itr; 2516 2517 /* Must be greater than zero to avoid unpredictable behavior */ 2518 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2519 !fep->tx_time_itr || !fep->tx_pkts_itr) 2520 return; 2521 2522 /* Select enet system clock as Interrupt Coalescing 2523 * timer Clock Source 2524 */ 2525 rx_itr = FEC_ITR_CLK_SEL; 2526 tx_itr = FEC_ITR_CLK_SEL; 2527 2528 /* set ICFT and ICTT */ 2529 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2530 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2531 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2532 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2533 2534 rx_itr |= FEC_ITR_EN; 2535 tx_itr |= FEC_ITR_EN; 2536 2537 writel(tx_itr, fep->hwp + FEC_TXIC0); 2538 writel(rx_itr, fep->hwp + FEC_RXIC0); 2539 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 2540 writel(tx_itr, fep->hwp + FEC_TXIC1); 2541 writel(rx_itr, fep->hwp + FEC_RXIC1); 2542 writel(tx_itr, fep->hwp + FEC_TXIC2); 2543 writel(rx_itr, fep->hwp + FEC_RXIC2); 2544 } 2545 } 2546 2547 static int 2548 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2549 { 2550 struct fec_enet_private *fep = netdev_priv(ndev); 2551 2552 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2553 return -EOPNOTSUPP; 2554 2555 ec->rx_coalesce_usecs = fep->rx_time_itr; 2556 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2557 2558 ec->tx_coalesce_usecs = fep->tx_time_itr; 2559 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2560 2561 return 0; 2562 } 2563 2564 static int 2565 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2566 { 2567 struct fec_enet_private *fep = netdev_priv(ndev); 2568 struct device *dev = &fep->pdev->dev; 2569 unsigned int cycle; 2570 2571 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2572 return -EOPNOTSUPP; 2573 2574 if (ec->rx_max_coalesced_frames > 255) { 2575 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 2576 return -EINVAL; 2577 } 2578 2579 if (ec->tx_max_coalesced_frames > 255) { 2580 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 2581 return -EINVAL; 2582 } 2583 2584 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 2585 if (cycle > 0xFFFF) { 2586 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 2587 return -EINVAL; 2588 } 2589 2590 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 2591 if (cycle > 0xFFFF) { 2592 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 2593 return -EINVAL; 2594 } 2595 2596 fep->rx_time_itr = ec->rx_coalesce_usecs; 2597 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2598 2599 fep->tx_time_itr = ec->tx_coalesce_usecs; 2600 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2601 2602 fec_enet_itr_coal_set(ndev); 2603 2604 return 0; 2605 } 2606 2607 static void fec_enet_itr_coal_init(struct net_device *ndev) 2608 { 2609 struct ethtool_coalesce ec; 2610 2611 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2612 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2613 2614 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2615 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2616 2617 fec_enet_set_coalesce(ndev, &ec); 2618 } 2619 2620 static int fec_enet_get_tunable(struct net_device *netdev, 2621 const struct ethtool_tunable *tuna, 2622 void *data) 2623 { 2624 struct fec_enet_private *fep = netdev_priv(netdev); 2625 int ret = 0; 2626 2627 switch (tuna->id) { 2628 case ETHTOOL_RX_COPYBREAK: 2629 *(u32 *)data = fep->rx_copybreak; 2630 break; 2631 default: 2632 ret = -EINVAL; 2633 break; 2634 } 2635 2636 return ret; 2637 } 2638 2639 static int fec_enet_set_tunable(struct net_device *netdev, 2640 const struct ethtool_tunable *tuna, 2641 const void *data) 2642 { 2643 struct fec_enet_private *fep = netdev_priv(netdev); 2644 int ret = 0; 2645 2646 switch (tuna->id) { 2647 case ETHTOOL_RX_COPYBREAK: 2648 fep->rx_copybreak = *(u32 *)data; 2649 break; 2650 default: 2651 ret = -EINVAL; 2652 break; 2653 } 2654 2655 return ret; 2656 } 2657 2658 static void 2659 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2660 { 2661 struct fec_enet_private *fep = netdev_priv(ndev); 2662 2663 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2664 wol->supported = WAKE_MAGIC; 2665 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2666 } else { 2667 wol->supported = wol->wolopts = 0; 2668 } 2669 } 2670 2671 static int 2672 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2673 { 2674 struct fec_enet_private *fep = netdev_priv(ndev); 2675 2676 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2677 return -EINVAL; 2678 2679 if (wol->wolopts & ~WAKE_MAGIC) 2680 return -EINVAL; 2681 2682 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2683 if (device_may_wakeup(&ndev->dev)) { 2684 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2685 if (fep->irq[0] > 0) 2686 enable_irq_wake(fep->irq[0]); 2687 } else { 2688 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2689 if (fep->irq[0] > 0) 2690 disable_irq_wake(fep->irq[0]); 2691 } 2692 2693 return 0; 2694 } 2695 2696 static const struct ethtool_ops fec_enet_ethtool_ops = { 2697 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2698 ETHTOOL_COALESCE_MAX_FRAMES, 2699 .get_drvinfo = fec_enet_get_drvinfo, 2700 .get_regs_len = fec_enet_get_regs_len, 2701 .get_regs = fec_enet_get_regs, 2702 .nway_reset = phy_ethtool_nway_reset, 2703 .get_link = ethtool_op_get_link, 2704 .get_coalesce = fec_enet_get_coalesce, 2705 .set_coalesce = fec_enet_set_coalesce, 2706 #ifndef CONFIG_M5272 2707 .get_pauseparam = fec_enet_get_pauseparam, 2708 .set_pauseparam = fec_enet_set_pauseparam, 2709 .get_strings = fec_enet_get_strings, 2710 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2711 .get_sset_count = fec_enet_get_sset_count, 2712 #endif 2713 .get_ts_info = fec_enet_get_ts_info, 2714 .get_tunable = fec_enet_get_tunable, 2715 .set_tunable = fec_enet_set_tunable, 2716 .get_wol = fec_enet_get_wol, 2717 .set_wol = fec_enet_set_wol, 2718 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2719 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2720 }; 2721 2722 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2723 { 2724 struct fec_enet_private *fep = netdev_priv(ndev); 2725 struct phy_device *phydev = ndev->phydev; 2726 2727 if (!netif_running(ndev)) 2728 return -EINVAL; 2729 2730 if (!phydev) 2731 return -ENODEV; 2732 2733 if (fep->bufdesc_ex) { 2734 if (cmd == SIOCSHWTSTAMP) 2735 return fec_ptp_set(ndev, rq); 2736 if (cmd == SIOCGHWTSTAMP) 2737 return fec_ptp_get(ndev, rq); 2738 } 2739 2740 return phy_mii_ioctl(phydev, rq, cmd); 2741 } 2742 2743 static void fec_enet_free_buffers(struct net_device *ndev) 2744 { 2745 struct fec_enet_private *fep = netdev_priv(ndev); 2746 unsigned int i; 2747 struct sk_buff *skb; 2748 struct bufdesc *bdp; 2749 struct fec_enet_priv_tx_q *txq; 2750 struct fec_enet_priv_rx_q *rxq; 2751 unsigned int q; 2752 2753 for (q = 0; q < fep->num_rx_queues; q++) { 2754 rxq = fep->rx_queue[q]; 2755 bdp = rxq->bd.base; 2756 for (i = 0; i < rxq->bd.ring_size; i++) { 2757 skb = rxq->rx_skbuff[i]; 2758 rxq->rx_skbuff[i] = NULL; 2759 if (skb) { 2760 dma_unmap_single(&fep->pdev->dev, 2761 fec32_to_cpu(bdp->cbd_bufaddr), 2762 FEC_ENET_RX_FRSIZE - fep->rx_align, 2763 DMA_FROM_DEVICE); 2764 dev_kfree_skb(skb); 2765 } 2766 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2767 } 2768 } 2769 2770 for (q = 0; q < fep->num_tx_queues; q++) { 2771 txq = fep->tx_queue[q]; 2772 for (i = 0; i < txq->bd.ring_size; i++) { 2773 kfree(txq->tx_bounce[i]); 2774 txq->tx_bounce[i] = NULL; 2775 skb = txq->tx_skbuff[i]; 2776 txq->tx_skbuff[i] = NULL; 2777 dev_kfree_skb(skb); 2778 } 2779 } 2780 } 2781 2782 static void fec_enet_free_queue(struct net_device *ndev) 2783 { 2784 struct fec_enet_private *fep = netdev_priv(ndev); 2785 int i; 2786 struct fec_enet_priv_tx_q *txq; 2787 2788 for (i = 0; i < fep->num_tx_queues; i++) 2789 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2790 txq = fep->tx_queue[i]; 2791 dma_free_coherent(&fep->pdev->dev, 2792 txq->bd.ring_size * TSO_HEADER_SIZE, 2793 txq->tso_hdrs, 2794 txq->tso_hdrs_dma); 2795 } 2796 2797 for (i = 0; i < fep->num_rx_queues; i++) 2798 kfree(fep->rx_queue[i]); 2799 for (i = 0; i < fep->num_tx_queues; i++) 2800 kfree(fep->tx_queue[i]); 2801 } 2802 2803 static int fec_enet_alloc_queue(struct net_device *ndev) 2804 { 2805 struct fec_enet_private *fep = netdev_priv(ndev); 2806 int i; 2807 int ret = 0; 2808 struct fec_enet_priv_tx_q *txq; 2809 2810 for (i = 0; i < fep->num_tx_queues; i++) { 2811 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 2812 if (!txq) { 2813 ret = -ENOMEM; 2814 goto alloc_failed; 2815 } 2816 2817 fep->tx_queue[i] = txq; 2818 txq->bd.ring_size = TX_RING_SIZE; 2819 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 2820 2821 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2822 txq->tx_wake_threshold = 2823 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 2824 2825 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 2826 txq->bd.ring_size * TSO_HEADER_SIZE, 2827 &txq->tso_hdrs_dma, 2828 GFP_KERNEL); 2829 if (!txq->tso_hdrs) { 2830 ret = -ENOMEM; 2831 goto alloc_failed; 2832 } 2833 } 2834 2835 for (i = 0; i < fep->num_rx_queues; i++) { 2836 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 2837 GFP_KERNEL); 2838 if (!fep->rx_queue[i]) { 2839 ret = -ENOMEM; 2840 goto alloc_failed; 2841 } 2842 2843 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 2844 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 2845 } 2846 return ret; 2847 2848 alloc_failed: 2849 fec_enet_free_queue(ndev); 2850 return ret; 2851 } 2852 2853 static int 2854 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 2855 { 2856 struct fec_enet_private *fep = netdev_priv(ndev); 2857 unsigned int i; 2858 struct sk_buff *skb; 2859 struct bufdesc *bdp; 2860 struct fec_enet_priv_rx_q *rxq; 2861 2862 rxq = fep->rx_queue[queue]; 2863 bdp = rxq->bd.base; 2864 for (i = 0; i < rxq->bd.ring_size; i++) { 2865 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2866 if (!skb) 2867 goto err_alloc; 2868 2869 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 2870 dev_kfree_skb(skb); 2871 goto err_alloc; 2872 } 2873 2874 rxq->rx_skbuff[i] = skb; 2875 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 2876 2877 if (fep->bufdesc_ex) { 2878 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2879 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 2880 } 2881 2882 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2883 } 2884 2885 /* Set the last buffer to wrap. */ 2886 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 2887 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2888 return 0; 2889 2890 err_alloc: 2891 fec_enet_free_buffers(ndev); 2892 return -ENOMEM; 2893 } 2894 2895 static int 2896 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 2897 { 2898 struct fec_enet_private *fep = netdev_priv(ndev); 2899 unsigned int i; 2900 struct bufdesc *bdp; 2901 struct fec_enet_priv_tx_q *txq; 2902 2903 txq = fep->tx_queue[queue]; 2904 bdp = txq->bd.base; 2905 for (i = 0; i < txq->bd.ring_size; i++) { 2906 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2907 if (!txq->tx_bounce[i]) 2908 goto err_alloc; 2909 2910 bdp->cbd_sc = cpu_to_fec16(0); 2911 bdp->cbd_bufaddr = cpu_to_fec32(0); 2912 2913 if (fep->bufdesc_ex) { 2914 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2915 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 2916 } 2917 2918 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 2919 } 2920 2921 /* Set the last buffer to wrap. */ 2922 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 2923 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2924 2925 return 0; 2926 2927 err_alloc: 2928 fec_enet_free_buffers(ndev); 2929 return -ENOMEM; 2930 } 2931 2932 static int fec_enet_alloc_buffers(struct net_device *ndev) 2933 { 2934 struct fec_enet_private *fep = netdev_priv(ndev); 2935 unsigned int i; 2936 2937 for (i = 0; i < fep->num_rx_queues; i++) 2938 if (fec_enet_alloc_rxq_buffers(ndev, i)) 2939 return -ENOMEM; 2940 2941 for (i = 0; i < fep->num_tx_queues; i++) 2942 if (fec_enet_alloc_txq_buffers(ndev, i)) 2943 return -ENOMEM; 2944 return 0; 2945 } 2946 2947 static int 2948 fec_enet_open(struct net_device *ndev) 2949 { 2950 struct fec_enet_private *fep = netdev_priv(ndev); 2951 int ret; 2952 bool reset_again; 2953 2954 ret = pm_runtime_get_sync(&fep->pdev->dev); 2955 if (ret < 0) 2956 return ret; 2957 2958 pinctrl_pm_select_default_state(&fep->pdev->dev); 2959 ret = fec_enet_clk_enable(ndev, true); 2960 if (ret) 2961 goto clk_enable; 2962 2963 /* During the first fec_enet_open call the PHY isn't probed at this 2964 * point. Therefore the phy_reset_after_clk_enable() call within 2965 * fec_enet_clk_enable() fails. As we need this reset in order to be 2966 * sure the PHY is working correctly we check if we need to reset again 2967 * later when the PHY is probed 2968 */ 2969 if (ndev->phydev && ndev->phydev->drv) 2970 reset_again = false; 2971 else 2972 reset_again = true; 2973 2974 /* I should reset the ring buffers here, but I don't yet know 2975 * a simple way to do that. 2976 */ 2977 2978 ret = fec_enet_alloc_buffers(ndev); 2979 if (ret) 2980 goto err_enet_alloc; 2981 2982 /* Init MAC prior to mii bus probe */ 2983 fec_restart(ndev); 2984 2985 /* Probe and connect to PHY when open the interface */ 2986 ret = fec_enet_mii_probe(ndev); 2987 if (ret) 2988 goto err_enet_mii_probe; 2989 2990 /* Call phy_reset_after_clk_enable() again if it failed during 2991 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 2992 */ 2993 if (reset_again) 2994 phy_reset_after_clk_enable(ndev->phydev); 2995 2996 if (fep->quirks & FEC_QUIRK_ERR006687) 2997 imx6q_cpuidle_fec_irqs_used(); 2998 2999 napi_enable(&fep->napi); 3000 phy_start(ndev->phydev); 3001 netif_tx_start_all_queues(ndev); 3002 3003 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3004 FEC_WOL_FLAG_ENABLE); 3005 3006 return 0; 3007 3008 err_enet_mii_probe: 3009 fec_enet_free_buffers(ndev); 3010 err_enet_alloc: 3011 fec_enet_clk_enable(ndev, false); 3012 clk_enable: 3013 pm_runtime_mark_last_busy(&fep->pdev->dev); 3014 pm_runtime_put_autosuspend(&fep->pdev->dev); 3015 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3016 return ret; 3017 } 3018 3019 static int 3020 fec_enet_close(struct net_device *ndev) 3021 { 3022 struct fec_enet_private *fep = netdev_priv(ndev); 3023 3024 phy_stop(ndev->phydev); 3025 3026 if (netif_device_present(ndev)) { 3027 napi_disable(&fep->napi); 3028 netif_tx_disable(ndev); 3029 fec_stop(ndev); 3030 } 3031 3032 phy_disconnect(ndev->phydev); 3033 3034 if (fep->quirks & FEC_QUIRK_ERR006687) 3035 imx6q_cpuidle_fec_irqs_unused(); 3036 3037 fec_enet_update_ethtool_stats(ndev); 3038 3039 fec_enet_clk_enable(ndev, false); 3040 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3041 pm_runtime_mark_last_busy(&fep->pdev->dev); 3042 pm_runtime_put_autosuspend(&fep->pdev->dev); 3043 3044 fec_enet_free_buffers(ndev); 3045 3046 return 0; 3047 } 3048 3049 /* Set or clear the multicast filter for this adaptor. 3050 * Skeleton taken from sunlance driver. 3051 * The CPM Ethernet implementation allows Multicast as well as individual 3052 * MAC address filtering. Some of the drivers check to make sure it is 3053 * a group multicast address, and discard those that are not. I guess I 3054 * will do the same for now, but just remove the test if you want 3055 * individual filtering as well (do the upper net layers want or support 3056 * this kind of feature?). 3057 */ 3058 3059 #define FEC_HASH_BITS 6 /* #bits in hash */ 3060 3061 static void set_multicast_list(struct net_device *ndev) 3062 { 3063 struct fec_enet_private *fep = netdev_priv(ndev); 3064 struct netdev_hw_addr *ha; 3065 unsigned int crc, tmp; 3066 unsigned char hash; 3067 unsigned int hash_high = 0, hash_low = 0; 3068 3069 if (ndev->flags & IFF_PROMISC) { 3070 tmp = readl(fep->hwp + FEC_R_CNTRL); 3071 tmp |= 0x8; 3072 writel(tmp, fep->hwp + FEC_R_CNTRL); 3073 return; 3074 } 3075 3076 tmp = readl(fep->hwp + FEC_R_CNTRL); 3077 tmp &= ~0x8; 3078 writel(tmp, fep->hwp + FEC_R_CNTRL); 3079 3080 if (ndev->flags & IFF_ALLMULTI) { 3081 /* Catch all multicast addresses, so set the 3082 * filter to all 1's 3083 */ 3084 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3085 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3086 3087 return; 3088 } 3089 3090 /* Add the addresses in hash register */ 3091 netdev_for_each_mc_addr(ha, ndev) { 3092 /* calculate crc32 value of mac address */ 3093 crc = ether_crc_le(ndev->addr_len, ha->addr); 3094 3095 /* only upper 6 bits (FEC_HASH_BITS) are used 3096 * which point to specific bit in the hash registers 3097 */ 3098 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3099 3100 if (hash > 31) 3101 hash_high |= 1 << (hash - 32); 3102 else 3103 hash_low |= 1 << hash; 3104 } 3105 3106 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3107 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3108 } 3109 3110 /* Set a MAC change in hardware. */ 3111 static int 3112 fec_set_mac_address(struct net_device *ndev, void *p) 3113 { 3114 struct fec_enet_private *fep = netdev_priv(ndev); 3115 struct sockaddr *addr = p; 3116 3117 if (addr) { 3118 if (!is_valid_ether_addr(addr->sa_data)) 3119 return -EADDRNOTAVAIL; 3120 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 3121 } 3122 3123 /* Add netif status check here to avoid system hang in below case: 3124 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3125 * After ethx down, fec all clocks are gated off and then register 3126 * access causes system hang. 3127 */ 3128 if (!netif_running(ndev)) 3129 return 0; 3130 3131 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3132 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3133 fep->hwp + FEC_ADDR_LOW); 3134 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3135 fep->hwp + FEC_ADDR_HIGH); 3136 return 0; 3137 } 3138 3139 #ifdef CONFIG_NET_POLL_CONTROLLER 3140 /** 3141 * fec_poll_controller - FEC Poll controller function 3142 * @dev: The FEC network adapter 3143 * 3144 * Polled functionality used by netconsole and others in non interrupt mode 3145 * 3146 */ 3147 static void fec_poll_controller(struct net_device *dev) 3148 { 3149 int i; 3150 struct fec_enet_private *fep = netdev_priv(dev); 3151 3152 for (i = 0; i < FEC_IRQ_NUM; i++) { 3153 if (fep->irq[i] > 0) { 3154 disable_irq(fep->irq[i]); 3155 fec_enet_interrupt(fep->irq[i], dev); 3156 enable_irq(fep->irq[i]); 3157 } 3158 } 3159 } 3160 #endif 3161 3162 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3163 netdev_features_t features) 3164 { 3165 struct fec_enet_private *fep = netdev_priv(netdev); 3166 netdev_features_t changed = features ^ netdev->features; 3167 3168 netdev->features = features; 3169 3170 /* Receive checksum has been changed */ 3171 if (changed & NETIF_F_RXCSUM) { 3172 if (features & NETIF_F_RXCSUM) 3173 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3174 else 3175 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3176 } 3177 } 3178 3179 static int fec_set_features(struct net_device *netdev, 3180 netdev_features_t features) 3181 { 3182 struct fec_enet_private *fep = netdev_priv(netdev); 3183 netdev_features_t changed = features ^ netdev->features; 3184 3185 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3186 napi_disable(&fep->napi); 3187 netif_tx_lock_bh(netdev); 3188 fec_stop(netdev); 3189 fec_enet_set_netdev_features(netdev, features); 3190 fec_restart(netdev); 3191 netif_tx_wake_all_queues(netdev); 3192 netif_tx_unlock_bh(netdev); 3193 napi_enable(&fep->napi); 3194 } else { 3195 fec_enet_set_netdev_features(netdev, features); 3196 } 3197 3198 return 0; 3199 } 3200 3201 static const struct net_device_ops fec_netdev_ops = { 3202 .ndo_open = fec_enet_open, 3203 .ndo_stop = fec_enet_close, 3204 .ndo_start_xmit = fec_enet_start_xmit, 3205 .ndo_set_rx_mode = set_multicast_list, 3206 .ndo_validate_addr = eth_validate_addr, 3207 .ndo_tx_timeout = fec_timeout, 3208 .ndo_set_mac_address = fec_set_mac_address, 3209 .ndo_do_ioctl = fec_enet_ioctl, 3210 #ifdef CONFIG_NET_POLL_CONTROLLER 3211 .ndo_poll_controller = fec_poll_controller, 3212 #endif 3213 .ndo_set_features = fec_set_features, 3214 }; 3215 3216 static const unsigned short offset_des_active_rxq[] = { 3217 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3218 }; 3219 3220 static const unsigned short offset_des_active_txq[] = { 3221 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3222 }; 3223 3224 /* 3225 * XXX: We need to clean up on failure exits here. 3226 * 3227 */ 3228 static int fec_enet_init(struct net_device *ndev) 3229 { 3230 struct fec_enet_private *fep = netdev_priv(ndev); 3231 struct bufdesc *cbd_base; 3232 dma_addr_t bd_dma; 3233 int bd_size; 3234 unsigned int i; 3235 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3236 sizeof(struct bufdesc); 3237 unsigned dsize_log2 = __fls(dsize); 3238 int ret; 3239 3240 WARN_ON(dsize != (1 << dsize_log2)); 3241 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 3242 fep->rx_align = 0xf; 3243 fep->tx_align = 0xf; 3244 #else 3245 fep->rx_align = 0x3; 3246 fep->tx_align = 0x3; 3247 #endif 3248 3249 /* Check mask of the streaming and coherent API */ 3250 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 3251 if (ret < 0) { 3252 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 3253 return ret; 3254 } 3255 3256 fec_enet_alloc_queue(ndev); 3257 3258 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3259 3260 /* Allocate memory for buffer descriptors. */ 3261 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3262 GFP_KERNEL); 3263 if (!cbd_base) { 3264 return -ENOMEM; 3265 } 3266 3267 /* Get the Ethernet address */ 3268 fec_get_mac(ndev); 3269 /* make sure MAC we just acquired is programmed into the hw */ 3270 fec_set_mac_address(ndev, NULL); 3271 3272 /* Set receive and transmit descriptor base. */ 3273 for (i = 0; i < fep->num_rx_queues; i++) { 3274 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3275 unsigned size = dsize * rxq->bd.ring_size; 3276 3277 rxq->bd.qid = i; 3278 rxq->bd.base = cbd_base; 3279 rxq->bd.cur = cbd_base; 3280 rxq->bd.dma = bd_dma; 3281 rxq->bd.dsize = dsize; 3282 rxq->bd.dsize_log2 = dsize_log2; 3283 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3284 bd_dma += size; 3285 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3286 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3287 } 3288 3289 for (i = 0; i < fep->num_tx_queues; i++) { 3290 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3291 unsigned size = dsize * txq->bd.ring_size; 3292 3293 txq->bd.qid = i; 3294 txq->bd.base = cbd_base; 3295 txq->bd.cur = cbd_base; 3296 txq->bd.dma = bd_dma; 3297 txq->bd.dsize = dsize; 3298 txq->bd.dsize_log2 = dsize_log2; 3299 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3300 bd_dma += size; 3301 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3302 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3303 } 3304 3305 3306 /* The FEC Ethernet specific entries in the device structure */ 3307 ndev->watchdog_timeo = TX_TIMEOUT; 3308 ndev->netdev_ops = &fec_netdev_ops; 3309 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3310 3311 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3312 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3313 3314 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3315 /* enable hw VLAN support */ 3316 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3317 3318 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3319 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3320 3321 /* enable hw accelerator */ 3322 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3323 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3324 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3325 } 3326 3327 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 3328 fep->tx_align = 0; 3329 fep->rx_align = 0x3f; 3330 } 3331 3332 ndev->hw_features = ndev->features; 3333 3334 fec_restart(ndev); 3335 3336 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 3337 fec_enet_clear_ethtool_stats(ndev); 3338 else 3339 fec_enet_update_ethtool_stats(ndev); 3340 3341 return 0; 3342 } 3343 3344 #ifdef CONFIG_OF 3345 static int fec_reset_phy(struct platform_device *pdev) 3346 { 3347 int err, phy_reset; 3348 bool active_high = false; 3349 int msec = 1, phy_post_delay = 0; 3350 struct device_node *np = pdev->dev.of_node; 3351 3352 if (!np) 3353 return 0; 3354 3355 err = of_property_read_u32(np, "phy-reset-duration", &msec); 3356 /* A sane reset duration should not be longer than 1s */ 3357 if (!err && msec > 1000) 3358 msec = 1; 3359 3360 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3361 if (phy_reset == -EPROBE_DEFER) 3362 return phy_reset; 3363 else if (!gpio_is_valid(phy_reset)) 3364 return 0; 3365 3366 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 3367 /* valid reset duration should be less than 1s */ 3368 if (!err && phy_post_delay > 1000) 3369 return -EINVAL; 3370 3371 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3372 3373 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3374 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3375 "phy-reset"); 3376 if (err) { 3377 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3378 return err; 3379 } 3380 3381 if (msec > 20) 3382 msleep(msec); 3383 else 3384 usleep_range(msec * 1000, msec * 1000 + 1000); 3385 3386 gpio_set_value_cansleep(phy_reset, !active_high); 3387 3388 if (!phy_post_delay) 3389 return 0; 3390 3391 if (phy_post_delay > 20) 3392 msleep(phy_post_delay); 3393 else 3394 usleep_range(phy_post_delay * 1000, 3395 phy_post_delay * 1000 + 1000); 3396 3397 return 0; 3398 } 3399 #else /* CONFIG_OF */ 3400 static int fec_reset_phy(struct platform_device *pdev) 3401 { 3402 /* 3403 * In case of platform probe, the reset has been done 3404 * by machine code. 3405 */ 3406 return 0; 3407 } 3408 #endif /* CONFIG_OF */ 3409 3410 static void 3411 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3412 { 3413 struct device_node *np = pdev->dev.of_node; 3414 3415 *num_tx = *num_rx = 1; 3416 3417 if (!np || !of_device_is_available(np)) 3418 return; 3419 3420 /* parse the num of tx and rx queues */ 3421 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3422 3423 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3424 3425 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3426 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3427 *num_tx); 3428 *num_tx = 1; 3429 return; 3430 } 3431 3432 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3433 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3434 *num_rx); 3435 *num_rx = 1; 3436 return; 3437 } 3438 3439 } 3440 3441 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 3442 { 3443 int irq_cnt = platform_irq_count(pdev); 3444 3445 if (irq_cnt > FEC_IRQ_NUM) 3446 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 3447 else if (irq_cnt == 2) 3448 irq_cnt = 1; /* last for pps */ 3449 else if (irq_cnt <= 0) 3450 irq_cnt = 1; /* At least 1 irq is needed */ 3451 return irq_cnt; 3452 } 3453 3454 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 3455 struct fec_devinfo *dev_info, 3456 struct device_node *np) 3457 { 3458 struct device_node *gpr_np; 3459 int ret = 0; 3460 3461 if (!dev_info) 3462 return 0; 3463 3464 gpr_np = of_parse_phandle(np, "gpr", 0); 3465 if (!gpr_np) 3466 return 0; 3467 3468 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 3469 if (IS_ERR(fep->stop_gpr.gpr)) { 3470 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 3471 ret = PTR_ERR(fep->stop_gpr.gpr); 3472 fep->stop_gpr.gpr = NULL; 3473 goto out; 3474 } 3475 3476 fep->stop_gpr.reg = dev_info->stop_gpr_reg; 3477 fep->stop_gpr.bit = dev_info->stop_gpr_bit; 3478 3479 out: 3480 of_node_put(gpr_np); 3481 3482 return ret; 3483 } 3484 3485 static int 3486 fec_probe(struct platform_device *pdev) 3487 { 3488 struct fec_enet_private *fep; 3489 struct fec_platform_data *pdata; 3490 phy_interface_t interface; 3491 struct net_device *ndev; 3492 int i, irq, ret = 0; 3493 const struct of_device_id *of_id; 3494 static int dev_id; 3495 struct device_node *np = pdev->dev.of_node, *phy_node; 3496 int num_tx_qs; 3497 int num_rx_qs; 3498 char irq_name[8]; 3499 int irq_cnt; 3500 struct fec_devinfo *dev_info; 3501 3502 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3503 3504 /* Init network device */ 3505 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 3506 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 3507 if (!ndev) 3508 return -ENOMEM; 3509 3510 SET_NETDEV_DEV(ndev, &pdev->dev); 3511 3512 /* setup board info structure */ 3513 fep = netdev_priv(ndev); 3514 3515 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3516 if (of_id) 3517 pdev->id_entry = of_id->data; 3518 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; 3519 if (dev_info) 3520 fep->quirks = dev_info->quirks; 3521 3522 fep->netdev = ndev; 3523 fep->num_rx_queues = num_rx_qs; 3524 fep->num_tx_queues = num_tx_qs; 3525 3526 #if !defined(CONFIG_M5272) 3527 /* default enable pause frame auto negotiation */ 3528 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3529 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3530 #endif 3531 3532 /* Select default pin state */ 3533 pinctrl_pm_select_default_state(&pdev->dev); 3534 3535 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 3536 if (IS_ERR(fep->hwp)) { 3537 ret = PTR_ERR(fep->hwp); 3538 goto failed_ioremap; 3539 } 3540 3541 fep->pdev = pdev; 3542 fep->dev_id = dev_id++; 3543 3544 platform_set_drvdata(pdev, ndev); 3545 3546 if ((of_machine_is_compatible("fsl,imx6q") || 3547 of_machine_is_compatible("fsl,imx6dl")) && 3548 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3549 fep->quirks |= FEC_QUIRK_ERR006687; 3550 3551 if (of_get_property(np, "fsl,magic-packet", NULL)) 3552 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3553 3554 ret = fec_enet_init_stop_mode(fep, dev_info, np); 3555 if (ret) 3556 goto failed_stop_mode; 3557 3558 phy_node = of_parse_phandle(np, "phy-handle", 0); 3559 if (!phy_node && of_phy_is_fixed_link(np)) { 3560 ret = of_phy_register_fixed_link(np); 3561 if (ret < 0) { 3562 dev_err(&pdev->dev, 3563 "broken fixed-link specification\n"); 3564 goto failed_phy; 3565 } 3566 phy_node = of_node_get(np); 3567 } 3568 fep->phy_node = phy_node; 3569 3570 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 3571 if (ret) { 3572 pdata = dev_get_platdata(&pdev->dev); 3573 if (pdata) 3574 fep->phy_interface = pdata->phy; 3575 else 3576 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3577 } else { 3578 fep->phy_interface = interface; 3579 } 3580 3581 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3582 if (IS_ERR(fep->clk_ipg)) { 3583 ret = PTR_ERR(fep->clk_ipg); 3584 goto failed_clk; 3585 } 3586 3587 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3588 if (IS_ERR(fep->clk_ahb)) { 3589 ret = PTR_ERR(fep->clk_ahb); 3590 goto failed_clk; 3591 } 3592 3593 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3594 3595 /* enet_out is optional, depends on board */ 3596 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3597 if (IS_ERR(fep->clk_enet_out)) 3598 fep->clk_enet_out = NULL; 3599 3600 fep->ptp_clk_on = false; 3601 mutex_init(&fep->ptp_clk_mutex); 3602 3603 /* clk_ref is optional, depends on board */ 3604 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3605 if (IS_ERR(fep->clk_ref)) 3606 fep->clk_ref = NULL; 3607 3608 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3609 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3610 if (IS_ERR(fep->clk_ptp)) { 3611 fep->clk_ptp = NULL; 3612 fep->bufdesc_ex = false; 3613 } 3614 3615 ret = fec_enet_clk_enable(ndev, true); 3616 if (ret) 3617 goto failed_clk; 3618 3619 ret = clk_prepare_enable(fep->clk_ipg); 3620 if (ret) 3621 goto failed_clk_ipg; 3622 ret = clk_prepare_enable(fep->clk_ahb); 3623 if (ret) 3624 goto failed_clk_ahb; 3625 3626 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 3627 if (!IS_ERR(fep->reg_phy)) { 3628 ret = regulator_enable(fep->reg_phy); 3629 if (ret) { 3630 dev_err(&pdev->dev, 3631 "Failed to enable phy regulator: %d\n", ret); 3632 goto failed_regulator; 3633 } 3634 } else { 3635 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 3636 ret = -EPROBE_DEFER; 3637 goto failed_regulator; 3638 } 3639 fep->reg_phy = NULL; 3640 } 3641 3642 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3643 pm_runtime_use_autosuspend(&pdev->dev); 3644 pm_runtime_get_noresume(&pdev->dev); 3645 pm_runtime_set_active(&pdev->dev); 3646 pm_runtime_enable(&pdev->dev); 3647 3648 ret = fec_reset_phy(pdev); 3649 if (ret) 3650 goto failed_reset; 3651 3652 irq_cnt = fec_enet_get_irq_cnt(pdev); 3653 if (fep->bufdesc_ex) 3654 fec_ptp_init(pdev, irq_cnt); 3655 3656 ret = fec_enet_init(ndev); 3657 if (ret) 3658 goto failed_init; 3659 3660 for (i = 0; i < irq_cnt; i++) { 3661 snprintf(irq_name, sizeof(irq_name), "int%d", i); 3662 irq = platform_get_irq_byname_optional(pdev, irq_name); 3663 if (irq < 0) 3664 irq = platform_get_irq(pdev, i); 3665 if (irq < 0) { 3666 ret = irq; 3667 goto failed_irq; 3668 } 3669 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3670 0, pdev->name, ndev); 3671 if (ret) 3672 goto failed_irq; 3673 3674 fep->irq[i] = irq; 3675 } 3676 3677 init_completion(&fep->mdio_done); 3678 ret = fec_enet_mii_init(pdev); 3679 if (ret) 3680 goto failed_mii_init; 3681 3682 /* Carrier starts down, phylib will bring it up */ 3683 netif_carrier_off(ndev); 3684 fec_enet_clk_enable(ndev, false); 3685 pinctrl_pm_select_sleep_state(&pdev->dev); 3686 3687 ret = register_netdev(ndev); 3688 if (ret) 3689 goto failed_register; 3690 3691 device_init_wakeup(&ndev->dev, fep->wol_flag & 3692 FEC_WOL_HAS_MAGIC_PACKET); 3693 3694 if (fep->bufdesc_ex && fep->ptp_clock) 3695 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3696 3697 fep->rx_copybreak = COPYBREAK_DEFAULT; 3698 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3699 3700 pm_runtime_mark_last_busy(&pdev->dev); 3701 pm_runtime_put_autosuspend(&pdev->dev); 3702 3703 return 0; 3704 3705 failed_register: 3706 fec_enet_mii_remove(fep); 3707 failed_mii_init: 3708 failed_irq: 3709 failed_init: 3710 fec_ptp_stop(pdev); 3711 if (fep->reg_phy) 3712 regulator_disable(fep->reg_phy); 3713 failed_reset: 3714 pm_runtime_put_noidle(&pdev->dev); 3715 pm_runtime_disable(&pdev->dev); 3716 failed_regulator: 3717 clk_disable_unprepare(fep->clk_ahb); 3718 failed_clk_ahb: 3719 clk_disable_unprepare(fep->clk_ipg); 3720 failed_clk_ipg: 3721 fec_enet_clk_enable(ndev, false); 3722 failed_clk: 3723 if (of_phy_is_fixed_link(np)) 3724 of_phy_deregister_fixed_link(np); 3725 of_node_put(phy_node); 3726 failed_stop_mode: 3727 failed_phy: 3728 dev_id--; 3729 failed_ioremap: 3730 free_netdev(ndev); 3731 3732 return ret; 3733 } 3734 3735 static int 3736 fec_drv_remove(struct platform_device *pdev) 3737 { 3738 struct net_device *ndev = platform_get_drvdata(pdev); 3739 struct fec_enet_private *fep = netdev_priv(ndev); 3740 struct device_node *np = pdev->dev.of_node; 3741 int ret; 3742 3743 ret = pm_runtime_get_sync(&pdev->dev); 3744 if (ret < 0) 3745 return ret; 3746 3747 cancel_work_sync(&fep->tx_timeout_work); 3748 fec_ptp_stop(pdev); 3749 unregister_netdev(ndev); 3750 fec_enet_mii_remove(fep); 3751 if (fep->reg_phy) 3752 regulator_disable(fep->reg_phy); 3753 3754 if (of_phy_is_fixed_link(np)) 3755 of_phy_deregister_fixed_link(np); 3756 of_node_put(fep->phy_node); 3757 free_netdev(ndev); 3758 3759 clk_disable_unprepare(fep->clk_ahb); 3760 clk_disable_unprepare(fep->clk_ipg); 3761 pm_runtime_put_noidle(&pdev->dev); 3762 pm_runtime_disable(&pdev->dev); 3763 3764 return 0; 3765 } 3766 3767 static int __maybe_unused fec_suspend(struct device *dev) 3768 { 3769 struct net_device *ndev = dev_get_drvdata(dev); 3770 struct fec_enet_private *fep = netdev_priv(ndev); 3771 3772 rtnl_lock(); 3773 if (netif_running(ndev)) { 3774 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 3775 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 3776 phy_stop(ndev->phydev); 3777 napi_disable(&fep->napi); 3778 netif_tx_lock_bh(ndev); 3779 netif_device_detach(ndev); 3780 netif_tx_unlock_bh(ndev); 3781 fec_stop(ndev); 3782 fec_enet_clk_enable(ndev, false); 3783 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3784 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3785 } 3786 rtnl_unlock(); 3787 3788 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3789 regulator_disable(fep->reg_phy); 3790 3791 /* SOC supply clock to phy, when clock is disabled, phy link down 3792 * SOC control phy regulator, when regulator is disabled, phy link down 3793 */ 3794 if (fep->clk_enet_out || fep->reg_phy) 3795 fep->link = 0; 3796 3797 return 0; 3798 } 3799 3800 static int __maybe_unused fec_resume(struct device *dev) 3801 { 3802 struct net_device *ndev = dev_get_drvdata(dev); 3803 struct fec_enet_private *fep = netdev_priv(ndev); 3804 int ret; 3805 int val; 3806 3807 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 3808 ret = regulator_enable(fep->reg_phy); 3809 if (ret) 3810 return ret; 3811 } 3812 3813 rtnl_lock(); 3814 if (netif_running(ndev)) { 3815 ret = fec_enet_clk_enable(ndev, true); 3816 if (ret) { 3817 rtnl_unlock(); 3818 goto failed_clk; 3819 } 3820 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 3821 fec_enet_stop_mode(fep, false); 3822 3823 val = readl(fep->hwp + FEC_ECNTRL); 3824 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 3825 writel(val, fep->hwp + FEC_ECNTRL); 3826 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 3827 } else { 3828 pinctrl_pm_select_default_state(&fep->pdev->dev); 3829 } 3830 fec_restart(ndev); 3831 netif_tx_lock_bh(ndev); 3832 netif_device_attach(ndev); 3833 netif_tx_unlock_bh(ndev); 3834 napi_enable(&fep->napi); 3835 phy_start(ndev->phydev); 3836 } 3837 rtnl_unlock(); 3838 3839 return 0; 3840 3841 failed_clk: 3842 if (fep->reg_phy) 3843 regulator_disable(fep->reg_phy); 3844 return ret; 3845 } 3846 3847 static int __maybe_unused fec_runtime_suspend(struct device *dev) 3848 { 3849 struct net_device *ndev = dev_get_drvdata(dev); 3850 struct fec_enet_private *fep = netdev_priv(ndev); 3851 3852 clk_disable_unprepare(fep->clk_ahb); 3853 clk_disable_unprepare(fep->clk_ipg); 3854 3855 return 0; 3856 } 3857 3858 static int __maybe_unused fec_runtime_resume(struct device *dev) 3859 { 3860 struct net_device *ndev = dev_get_drvdata(dev); 3861 struct fec_enet_private *fep = netdev_priv(ndev); 3862 int ret; 3863 3864 ret = clk_prepare_enable(fep->clk_ahb); 3865 if (ret) 3866 return ret; 3867 ret = clk_prepare_enable(fep->clk_ipg); 3868 if (ret) 3869 goto failed_clk_ipg; 3870 3871 return 0; 3872 3873 failed_clk_ipg: 3874 clk_disable_unprepare(fep->clk_ahb); 3875 return ret; 3876 } 3877 3878 static const struct dev_pm_ops fec_pm_ops = { 3879 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 3880 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 3881 }; 3882 3883 static struct platform_driver fec_driver = { 3884 .driver = { 3885 .name = DRIVER_NAME, 3886 .pm = &fec_pm_ops, 3887 .of_match_table = fec_dt_ids, 3888 .suppress_bind_attrs = true, 3889 }, 3890 .id_table = fec_devtype, 3891 .probe = fec_probe, 3892 .remove = fec_drv_remove, 3893 }; 3894 3895 module_platform_driver(fec_driver); 3896 3897 MODULE_ALIAS("platform:"DRIVER_NAME); 3898 MODULE_LICENSE("GPL"); 3899