1 /* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 * 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/string.h> 27 #include <linux/ptrace.h> 28 #include <linux/errno.h> 29 #include <linux/ioport.h> 30 #include <linux/slab.h> 31 #include <linux/interrupt.h> 32 #include <linux/delay.h> 33 #include <linux/netdevice.h> 34 #include <linux/etherdevice.h> 35 #include <linux/skbuff.h> 36 #include <linux/in.h> 37 #include <linux/ip.h> 38 #include <net/ip.h> 39 #include <net/tso.h> 40 #include <linux/tcp.h> 41 #include <linux/udp.h> 42 #include <linux/icmp.h> 43 #include <linux/spinlock.h> 44 #include <linux/workqueue.h> 45 #include <linux/bitops.h> 46 #include <linux/io.h> 47 #include <linux/irq.h> 48 #include <linux/clk.h> 49 #include <linux/platform_device.h> 50 #include <linux/phy.h> 51 #include <linux/fec.h> 52 #include <linux/of.h> 53 #include <linux/of_device.h> 54 #include <linux/of_gpio.h> 55 #include <linux/of_mdio.h> 56 #include <linux/of_net.h> 57 #include <linux/regulator/consumer.h> 58 #include <linux/if_vlan.h> 59 #include <linux/pinctrl/consumer.h> 60 #include <linux/prefetch.h> 61 62 #include <asm/cacheflush.h> 63 64 #include "fec.h" 65 66 static void set_multicast_list(struct net_device *ndev); 67 static void fec_enet_itr_coal_init(struct net_device *ndev); 68 69 #define DRIVER_NAME "fec" 70 71 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0)) 72 73 /* Pause frame feild and FIFO threshold */ 74 #define FEC_ENET_FCE (1 << 5) 75 #define FEC_ENET_RSEM_V 0x84 76 #define FEC_ENET_RSFL_V 16 77 #define FEC_ENET_RAEM_V 0x8 78 #define FEC_ENET_RAFL_V 0x8 79 #define FEC_ENET_OPD_V 0xFFF0 80 81 static struct platform_device_id fec_devtype[] = { 82 { 83 /* keep it for coldfire */ 84 .name = DRIVER_NAME, 85 .driver_data = 0, 86 }, { 87 .name = "imx25-fec", 88 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_HAS_RACC, 89 }, { 90 .name = "imx27-fec", 91 .driver_data = FEC_QUIRK_HAS_RACC, 92 }, { 93 .name = "imx28-fec", 94 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 95 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC, 96 }, { 97 .name = "imx6q-fec", 98 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 99 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 100 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 101 FEC_QUIRK_HAS_RACC, 102 }, { 103 .name = "mvf600-fec", 104 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 105 }, { 106 .name = "imx6sx-fec", 107 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 108 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 109 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 110 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 111 FEC_QUIRK_HAS_RACC, 112 }, { 113 /* sentinel */ 114 } 115 }; 116 MODULE_DEVICE_TABLE(platform, fec_devtype); 117 118 enum imx_fec_type { 119 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 120 IMX27_FEC, /* runs on i.mx27/35/51 */ 121 IMX28_FEC, 122 IMX6Q_FEC, 123 MVF600_FEC, 124 IMX6SX_FEC, 125 }; 126 127 static const struct of_device_id fec_dt_ids[] = { 128 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 129 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 130 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 131 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 132 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 133 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 134 { /* sentinel */ } 135 }; 136 MODULE_DEVICE_TABLE(of, fec_dt_ids); 137 138 static unsigned char macaddr[ETH_ALEN]; 139 module_param_array(macaddr, byte, NULL, 0); 140 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 141 142 #if defined(CONFIG_M5272) 143 /* 144 * Some hardware gets it MAC address out of local flash memory. 145 * if this is non-zero then assume it is the address to get MAC from. 146 */ 147 #if defined(CONFIG_NETtel) 148 #define FEC_FLASHMAC 0xf0006006 149 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 150 #define FEC_FLASHMAC 0xf0006000 151 #elif defined(CONFIG_CANCam) 152 #define FEC_FLASHMAC 0xf0020000 153 #elif defined (CONFIG_M5272C3) 154 #define FEC_FLASHMAC (0xffe04000 + 4) 155 #elif defined(CONFIG_MOD5272) 156 #define FEC_FLASHMAC 0xffc0406b 157 #else 158 #define FEC_FLASHMAC 0 159 #endif 160 #endif /* CONFIG_M5272 */ 161 162 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 163 */ 164 #define PKT_MAXBUF_SIZE 1522 165 #define PKT_MINBUF_SIZE 64 166 #define PKT_MAXBLR_SIZE 1536 167 168 /* FEC receive acceleration */ 169 #define FEC_RACC_IPDIS (1 << 1) 170 #define FEC_RACC_PRODIS (1 << 2) 171 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 172 173 /* 174 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 175 * size bits. Other FEC hardware does not, so we need to take that into 176 * account when setting it. 177 */ 178 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 179 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 180 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 181 #else 182 #define OPT_FRAME_SIZE 0 183 #endif 184 185 /* FEC MII MMFR bits definition */ 186 #define FEC_MMFR_ST (1 << 30) 187 #define FEC_MMFR_OP_READ (2 << 28) 188 #define FEC_MMFR_OP_WRITE (1 << 28) 189 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 190 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 191 #define FEC_MMFR_TA (2 << 16) 192 #define FEC_MMFR_DATA(v) (v & 0xffff) 193 /* FEC ECR bits definition */ 194 #define FEC_ECR_MAGICEN (1 << 2) 195 #define FEC_ECR_SLEEP (1 << 3) 196 197 #define FEC_MII_TIMEOUT 30000 /* us */ 198 199 /* Transmitter timeout */ 200 #define TX_TIMEOUT (2 * HZ) 201 202 #define FEC_PAUSE_FLAG_AUTONEG 0x1 203 #define FEC_PAUSE_FLAG_ENABLE 0x2 204 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 205 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 206 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 207 208 #define COPYBREAK_DEFAULT 256 209 210 #define TSO_HEADER_SIZE 128 211 /* Max number of allowed TCP segments for software TSO */ 212 #define FEC_MAX_TSO_SEGS 100 213 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 214 215 #define IS_TSO_HEADER(txq, addr) \ 216 ((addr >= txq->tso_hdrs_dma) && \ 217 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE)) 218 219 static int mii_cnt; 220 221 static inline 222 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 223 struct fec_enet_private *fep, 224 int queue_id) 225 { 226 struct bufdesc *new_bd = bdp + 1; 227 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1; 228 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id]; 229 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id]; 230 struct bufdesc_ex *ex_base; 231 struct bufdesc *base; 232 int ring_size; 233 234 if (bdp >= txq->tx_bd_base) { 235 base = txq->tx_bd_base; 236 ring_size = txq->tx_ring_size; 237 ex_base = (struct bufdesc_ex *)txq->tx_bd_base; 238 } else { 239 base = rxq->rx_bd_base; 240 ring_size = rxq->rx_ring_size; 241 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base; 242 } 243 244 if (fep->bufdesc_ex) 245 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ? 246 ex_base : ex_new_bd); 247 else 248 return (new_bd >= (base + ring_size)) ? 249 base : new_bd; 250 } 251 252 static inline 253 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 254 struct fec_enet_private *fep, 255 int queue_id) 256 { 257 struct bufdesc *new_bd = bdp - 1; 258 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1; 259 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id]; 260 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id]; 261 struct bufdesc_ex *ex_base; 262 struct bufdesc *base; 263 int ring_size; 264 265 if (bdp >= txq->tx_bd_base) { 266 base = txq->tx_bd_base; 267 ring_size = txq->tx_ring_size; 268 ex_base = (struct bufdesc_ex *)txq->tx_bd_base; 269 } else { 270 base = rxq->rx_bd_base; 271 ring_size = rxq->rx_ring_size; 272 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base; 273 } 274 275 if (fep->bufdesc_ex) 276 return (struct bufdesc *)((ex_new_bd < ex_base) ? 277 (ex_new_bd + ring_size) : ex_new_bd); 278 else 279 return (new_bd < base) ? (new_bd + ring_size) : new_bd; 280 } 281 282 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp, 283 struct fec_enet_private *fep) 284 { 285 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size; 286 } 287 288 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep, 289 struct fec_enet_priv_tx_q *txq) 290 { 291 int entries; 292 293 entries = ((const char *)txq->dirty_tx - 294 (const char *)txq->cur_tx) / fep->bufdesc_size - 1; 295 296 return entries > 0 ? entries : entries + txq->tx_ring_size; 297 } 298 299 static void swap_buffer(void *bufaddr, int len) 300 { 301 int i; 302 unsigned int *buf = bufaddr; 303 304 for (i = 0; i < len; i += 4, buf++) 305 swab32s(buf); 306 } 307 308 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 309 { 310 int i; 311 unsigned int *src = src_buf; 312 unsigned int *dst = dst_buf; 313 314 for (i = 0; i < len; i += 4, src++, dst++) 315 *dst = swab32p(src); 316 } 317 318 static void fec_dump(struct net_device *ndev) 319 { 320 struct fec_enet_private *fep = netdev_priv(ndev); 321 struct bufdesc *bdp; 322 struct fec_enet_priv_tx_q *txq; 323 int index = 0; 324 325 netdev_info(ndev, "TX ring dump\n"); 326 pr_info("Nr SC addr len SKB\n"); 327 328 txq = fep->tx_queue[0]; 329 bdp = txq->tx_bd_base; 330 331 do { 332 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n", 333 index, 334 bdp == txq->cur_tx ? 'S' : ' ', 335 bdp == txq->dirty_tx ? 'H' : ' ', 336 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen, 337 txq->tx_skbuff[index]); 338 bdp = fec_enet_get_nextdesc(bdp, fep, 0); 339 index++; 340 } while (bdp != txq->tx_bd_base); 341 } 342 343 static inline bool is_ipv4_pkt(struct sk_buff *skb) 344 { 345 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 346 } 347 348 static int 349 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 350 { 351 /* Only run for packets requiring a checksum. */ 352 if (skb->ip_summed != CHECKSUM_PARTIAL) 353 return 0; 354 355 if (unlikely(skb_cow_head(skb, 0))) 356 return -1; 357 358 if (is_ipv4_pkt(skb)) 359 ip_hdr(skb)->check = 0; 360 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 361 362 return 0; 363 } 364 365 static int 366 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 367 struct sk_buff *skb, 368 struct net_device *ndev) 369 { 370 struct fec_enet_private *fep = netdev_priv(ndev); 371 struct bufdesc *bdp = txq->cur_tx; 372 struct bufdesc_ex *ebdp; 373 int nr_frags = skb_shinfo(skb)->nr_frags; 374 unsigned short queue = skb_get_queue_mapping(skb); 375 int frag, frag_len; 376 unsigned short status; 377 unsigned int estatus = 0; 378 skb_frag_t *this_frag; 379 unsigned int index; 380 void *bufaddr; 381 dma_addr_t addr; 382 int i; 383 384 for (frag = 0; frag < nr_frags; frag++) { 385 this_frag = &skb_shinfo(skb)->frags[frag]; 386 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 387 ebdp = (struct bufdesc_ex *)bdp; 388 389 status = bdp->cbd_sc; 390 status &= ~BD_ENET_TX_STATS; 391 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 392 frag_len = skb_shinfo(skb)->frags[frag].size; 393 394 /* Handle the last BD specially */ 395 if (frag == nr_frags - 1) { 396 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 397 if (fep->bufdesc_ex) { 398 estatus |= BD_ENET_TX_INT; 399 if (unlikely(skb_shinfo(skb)->tx_flags & 400 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 401 estatus |= BD_ENET_TX_TS; 402 } 403 } 404 405 if (fep->bufdesc_ex) { 406 if (fep->quirks & FEC_QUIRK_HAS_AVB) 407 estatus |= FEC_TX_BD_FTYPE(queue); 408 if (skb->ip_summed == CHECKSUM_PARTIAL) 409 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 410 ebdp->cbd_bdu = 0; 411 ebdp->cbd_esc = estatus; 412 } 413 414 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset; 415 416 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep); 417 if (((unsigned long) bufaddr) & fep->tx_align || 418 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 419 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 420 bufaddr = txq->tx_bounce[index]; 421 422 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 423 swap_buffer(bufaddr, frag_len); 424 } 425 426 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 427 DMA_TO_DEVICE); 428 if (dma_mapping_error(&fep->pdev->dev, addr)) { 429 dev_kfree_skb_any(skb); 430 if (net_ratelimit()) 431 netdev_err(ndev, "Tx DMA memory map failed\n"); 432 goto dma_mapping_error; 433 } 434 435 bdp->cbd_bufaddr = addr; 436 bdp->cbd_datlen = frag_len; 437 bdp->cbd_sc = status; 438 } 439 440 txq->cur_tx = bdp; 441 442 return 0; 443 444 dma_mapping_error: 445 bdp = txq->cur_tx; 446 for (i = 0; i < frag; i++) { 447 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 448 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 449 bdp->cbd_datlen, DMA_TO_DEVICE); 450 } 451 return NETDEV_TX_OK; 452 } 453 454 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 455 struct sk_buff *skb, struct net_device *ndev) 456 { 457 struct fec_enet_private *fep = netdev_priv(ndev); 458 int nr_frags = skb_shinfo(skb)->nr_frags; 459 struct bufdesc *bdp, *last_bdp; 460 void *bufaddr; 461 dma_addr_t addr; 462 unsigned short status; 463 unsigned short buflen; 464 unsigned short queue; 465 unsigned int estatus = 0; 466 unsigned int index; 467 int entries_free; 468 int ret; 469 470 entries_free = fec_enet_get_free_txdesc_num(fep, txq); 471 if (entries_free < MAX_SKB_FRAGS + 1) { 472 dev_kfree_skb_any(skb); 473 if (net_ratelimit()) 474 netdev_err(ndev, "NOT enough BD for SG!\n"); 475 return NETDEV_TX_OK; 476 } 477 478 /* Protocol checksum off-load for TCP and UDP. */ 479 if (fec_enet_clear_csum(skb, ndev)) { 480 dev_kfree_skb_any(skb); 481 return NETDEV_TX_OK; 482 } 483 484 /* Fill in a Tx ring entry */ 485 bdp = txq->cur_tx; 486 status = bdp->cbd_sc; 487 status &= ~BD_ENET_TX_STATS; 488 489 /* Set buffer length and buffer pointer */ 490 bufaddr = skb->data; 491 buflen = skb_headlen(skb); 492 493 queue = skb_get_queue_mapping(skb); 494 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep); 495 if (((unsigned long) bufaddr) & fep->tx_align || 496 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 497 memcpy(txq->tx_bounce[index], skb->data, buflen); 498 bufaddr = txq->tx_bounce[index]; 499 500 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 501 swap_buffer(bufaddr, buflen); 502 } 503 504 /* Push the data cache so the CPM does not get stale memory data. */ 505 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 506 if (dma_mapping_error(&fep->pdev->dev, addr)) { 507 dev_kfree_skb_any(skb); 508 if (net_ratelimit()) 509 netdev_err(ndev, "Tx DMA memory map failed\n"); 510 return NETDEV_TX_OK; 511 } 512 513 if (nr_frags) { 514 ret = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 515 if (ret) 516 return ret; 517 } else { 518 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 519 if (fep->bufdesc_ex) { 520 estatus = BD_ENET_TX_INT; 521 if (unlikely(skb_shinfo(skb)->tx_flags & 522 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 523 estatus |= BD_ENET_TX_TS; 524 } 525 } 526 527 if (fep->bufdesc_ex) { 528 529 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 530 531 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 532 fep->hwts_tx_en)) 533 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 534 535 if (fep->quirks & FEC_QUIRK_HAS_AVB) 536 estatus |= FEC_TX_BD_FTYPE(queue); 537 538 if (skb->ip_summed == CHECKSUM_PARTIAL) 539 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 540 541 ebdp->cbd_bdu = 0; 542 ebdp->cbd_esc = estatus; 543 } 544 545 last_bdp = txq->cur_tx; 546 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep); 547 /* Save skb pointer */ 548 txq->tx_skbuff[index] = skb; 549 550 bdp->cbd_datlen = buflen; 551 bdp->cbd_bufaddr = addr; 552 553 /* Send it on its way. Tell FEC it's ready, interrupt when done, 554 * it's the last BD of the frame, and to put the CRC on the end. 555 */ 556 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 557 bdp->cbd_sc = status; 558 559 /* If this was the last BD in the ring, start at the beginning again. */ 560 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue); 561 562 skb_tx_timestamp(skb); 563 564 txq->cur_tx = bdp; 565 566 /* Trigger transmission start */ 567 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue)); 568 569 return 0; 570 } 571 572 static int 573 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 574 struct net_device *ndev, 575 struct bufdesc *bdp, int index, char *data, 576 int size, bool last_tcp, bool is_last) 577 { 578 struct fec_enet_private *fep = netdev_priv(ndev); 579 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 580 unsigned short queue = skb_get_queue_mapping(skb); 581 unsigned short status; 582 unsigned int estatus = 0; 583 dma_addr_t addr; 584 585 status = bdp->cbd_sc; 586 status &= ~BD_ENET_TX_STATS; 587 588 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 589 590 if (((unsigned long) data) & fep->tx_align || 591 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 592 memcpy(txq->tx_bounce[index], data, size); 593 data = txq->tx_bounce[index]; 594 595 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 596 swap_buffer(data, size); 597 } 598 599 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 600 if (dma_mapping_error(&fep->pdev->dev, addr)) { 601 dev_kfree_skb_any(skb); 602 if (net_ratelimit()) 603 netdev_err(ndev, "Tx DMA memory map failed\n"); 604 return NETDEV_TX_BUSY; 605 } 606 607 bdp->cbd_datlen = size; 608 bdp->cbd_bufaddr = addr; 609 610 if (fep->bufdesc_ex) { 611 if (fep->quirks & FEC_QUIRK_HAS_AVB) 612 estatus |= FEC_TX_BD_FTYPE(queue); 613 if (skb->ip_summed == CHECKSUM_PARTIAL) 614 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 615 ebdp->cbd_bdu = 0; 616 ebdp->cbd_esc = estatus; 617 } 618 619 /* Handle the last BD specially */ 620 if (last_tcp) 621 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 622 if (is_last) { 623 status |= BD_ENET_TX_INTR; 624 if (fep->bufdesc_ex) 625 ebdp->cbd_esc |= BD_ENET_TX_INT; 626 } 627 628 bdp->cbd_sc = status; 629 630 return 0; 631 } 632 633 static int 634 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 635 struct sk_buff *skb, struct net_device *ndev, 636 struct bufdesc *bdp, int index) 637 { 638 struct fec_enet_private *fep = netdev_priv(ndev); 639 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 640 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 641 unsigned short queue = skb_get_queue_mapping(skb); 642 void *bufaddr; 643 unsigned long dmabuf; 644 unsigned short status; 645 unsigned int estatus = 0; 646 647 status = bdp->cbd_sc; 648 status &= ~BD_ENET_TX_STATS; 649 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 650 651 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 652 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 653 if (((unsigned long)bufaddr) & fep->tx_align || 654 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 655 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 656 bufaddr = txq->tx_bounce[index]; 657 658 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 659 swap_buffer(bufaddr, hdr_len); 660 661 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 662 hdr_len, DMA_TO_DEVICE); 663 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 664 dev_kfree_skb_any(skb); 665 if (net_ratelimit()) 666 netdev_err(ndev, "Tx DMA memory map failed\n"); 667 return NETDEV_TX_BUSY; 668 } 669 } 670 671 bdp->cbd_bufaddr = dmabuf; 672 bdp->cbd_datlen = hdr_len; 673 674 if (fep->bufdesc_ex) { 675 if (fep->quirks & FEC_QUIRK_HAS_AVB) 676 estatus |= FEC_TX_BD_FTYPE(queue); 677 if (skb->ip_summed == CHECKSUM_PARTIAL) 678 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 679 ebdp->cbd_bdu = 0; 680 ebdp->cbd_esc = estatus; 681 } 682 683 bdp->cbd_sc = status; 684 685 return 0; 686 } 687 688 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 689 struct sk_buff *skb, 690 struct net_device *ndev) 691 { 692 struct fec_enet_private *fep = netdev_priv(ndev); 693 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 694 int total_len, data_left; 695 struct bufdesc *bdp = txq->cur_tx; 696 unsigned short queue = skb_get_queue_mapping(skb); 697 struct tso_t tso; 698 unsigned int index = 0; 699 int ret; 700 701 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) { 702 dev_kfree_skb_any(skb); 703 if (net_ratelimit()) 704 netdev_err(ndev, "NOT enough BD for TSO!\n"); 705 return NETDEV_TX_OK; 706 } 707 708 /* Protocol checksum off-load for TCP and UDP. */ 709 if (fec_enet_clear_csum(skb, ndev)) { 710 dev_kfree_skb_any(skb); 711 return NETDEV_TX_OK; 712 } 713 714 /* Initialize the TSO handler, and prepare the first payload */ 715 tso_start(skb, &tso); 716 717 total_len = skb->len - hdr_len; 718 while (total_len > 0) { 719 char *hdr; 720 721 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep); 722 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 723 total_len -= data_left; 724 725 /* prepare packet headers: MAC + IP + TCP */ 726 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 727 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 728 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 729 if (ret) 730 goto err_release; 731 732 while (data_left > 0) { 733 int size; 734 735 size = min_t(int, tso.size, data_left); 736 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 737 index = fec_enet_get_bd_index(txq->tx_bd_base, 738 bdp, fep); 739 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 740 bdp, index, 741 tso.data, size, 742 size == data_left, 743 total_len == 0); 744 if (ret) 745 goto err_release; 746 747 data_left -= size; 748 tso_build_data(skb, &tso, size); 749 } 750 751 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 752 } 753 754 /* Save skb pointer */ 755 txq->tx_skbuff[index] = skb; 756 757 skb_tx_timestamp(skb); 758 txq->cur_tx = bdp; 759 760 /* Trigger transmission start */ 761 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 762 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) || 763 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) || 764 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) || 765 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue))) 766 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue)); 767 768 return 0; 769 770 err_release: 771 /* TODO: Release all used data descriptors for TSO */ 772 return ret; 773 } 774 775 static netdev_tx_t 776 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 777 { 778 struct fec_enet_private *fep = netdev_priv(ndev); 779 int entries_free; 780 unsigned short queue; 781 struct fec_enet_priv_tx_q *txq; 782 struct netdev_queue *nq; 783 int ret; 784 785 queue = skb_get_queue_mapping(skb); 786 txq = fep->tx_queue[queue]; 787 nq = netdev_get_tx_queue(ndev, queue); 788 789 if (skb_is_gso(skb)) 790 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 791 else 792 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 793 if (ret) 794 return ret; 795 796 entries_free = fec_enet_get_free_txdesc_num(fep, txq); 797 if (entries_free <= txq->tx_stop_threshold) 798 netif_tx_stop_queue(nq); 799 800 return NETDEV_TX_OK; 801 } 802 803 /* Init RX & TX buffer descriptors 804 */ 805 static void fec_enet_bd_init(struct net_device *dev) 806 { 807 struct fec_enet_private *fep = netdev_priv(dev); 808 struct fec_enet_priv_tx_q *txq; 809 struct fec_enet_priv_rx_q *rxq; 810 struct bufdesc *bdp; 811 unsigned int i; 812 unsigned int q; 813 814 for (q = 0; q < fep->num_rx_queues; q++) { 815 /* Initialize the receive buffer descriptors. */ 816 rxq = fep->rx_queue[q]; 817 bdp = rxq->rx_bd_base; 818 819 for (i = 0; i < rxq->rx_ring_size; i++) { 820 821 /* Initialize the BD for every fragment in the page. */ 822 if (bdp->cbd_bufaddr) 823 bdp->cbd_sc = BD_ENET_RX_EMPTY; 824 else 825 bdp->cbd_sc = 0; 826 bdp = fec_enet_get_nextdesc(bdp, fep, q); 827 } 828 829 /* Set the last buffer to wrap */ 830 bdp = fec_enet_get_prevdesc(bdp, fep, q); 831 bdp->cbd_sc |= BD_SC_WRAP; 832 833 rxq->cur_rx = rxq->rx_bd_base; 834 } 835 836 for (q = 0; q < fep->num_tx_queues; q++) { 837 /* ...and the same for transmit */ 838 txq = fep->tx_queue[q]; 839 bdp = txq->tx_bd_base; 840 txq->cur_tx = bdp; 841 842 for (i = 0; i < txq->tx_ring_size; i++) { 843 /* Initialize the BD for every fragment in the page. */ 844 bdp->cbd_sc = 0; 845 if (txq->tx_skbuff[i]) { 846 dev_kfree_skb_any(txq->tx_skbuff[i]); 847 txq->tx_skbuff[i] = NULL; 848 } 849 bdp->cbd_bufaddr = 0; 850 bdp = fec_enet_get_nextdesc(bdp, fep, q); 851 } 852 853 /* Set the last buffer to wrap */ 854 bdp = fec_enet_get_prevdesc(bdp, fep, q); 855 bdp->cbd_sc |= BD_SC_WRAP; 856 txq->dirty_tx = bdp; 857 } 858 } 859 860 static void fec_enet_active_rxring(struct net_device *ndev) 861 { 862 struct fec_enet_private *fep = netdev_priv(ndev); 863 int i; 864 865 for (i = 0; i < fep->num_rx_queues; i++) 866 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i)); 867 } 868 869 static void fec_enet_enable_ring(struct net_device *ndev) 870 { 871 struct fec_enet_private *fep = netdev_priv(ndev); 872 struct fec_enet_priv_tx_q *txq; 873 struct fec_enet_priv_rx_q *rxq; 874 int i; 875 876 for (i = 0; i < fep->num_rx_queues; i++) { 877 rxq = fep->rx_queue[i]; 878 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i)); 879 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 880 881 /* enable DMA1/2 */ 882 if (i) 883 writel(RCMR_MATCHEN | RCMR_CMP(i), 884 fep->hwp + FEC_RCMR(i)); 885 } 886 887 for (i = 0; i < fep->num_tx_queues; i++) { 888 txq = fep->tx_queue[i]; 889 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i)); 890 891 /* enable DMA1/2 */ 892 if (i) 893 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 894 fep->hwp + FEC_DMA_CFG(i)); 895 } 896 } 897 898 static void fec_enet_reset_skb(struct net_device *ndev) 899 { 900 struct fec_enet_private *fep = netdev_priv(ndev); 901 struct fec_enet_priv_tx_q *txq; 902 int i, j; 903 904 for (i = 0; i < fep->num_tx_queues; i++) { 905 txq = fep->tx_queue[i]; 906 907 for (j = 0; j < txq->tx_ring_size; j++) { 908 if (txq->tx_skbuff[j]) { 909 dev_kfree_skb_any(txq->tx_skbuff[j]); 910 txq->tx_skbuff[j] = NULL; 911 } 912 } 913 } 914 } 915 916 /* 917 * This function is called to start or restart the FEC during a link 918 * change, transmit timeout, or to reconfigure the FEC. The network 919 * packet processing for this device must be stopped before this call. 920 */ 921 static void 922 fec_restart(struct net_device *ndev) 923 { 924 struct fec_enet_private *fep = netdev_priv(ndev); 925 u32 val; 926 u32 temp_mac[2]; 927 u32 rcntl = OPT_FRAME_SIZE | 0x04; 928 u32 ecntl = 0x2; /* ETHEREN */ 929 930 /* Whack a reset. We should wait for this. 931 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 932 * instead of reset MAC itself. 933 */ 934 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 935 writel(0, fep->hwp + FEC_ECNTRL); 936 } else { 937 writel(1, fep->hwp + FEC_ECNTRL); 938 udelay(10); 939 } 940 941 /* 942 * enet-mac reset will reset mac address registers too, 943 * so need to reconfigure it. 944 */ 945 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 946 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 947 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); 948 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); 949 } 950 951 /* Clear any outstanding interrupt. */ 952 writel(0xffffffff, fep->hwp + FEC_IEVENT); 953 954 fec_enet_bd_init(ndev); 955 956 fec_enet_enable_ring(ndev); 957 958 /* Reset tx SKB buffers. */ 959 fec_enet_reset_skb(ndev); 960 961 /* Enable MII mode */ 962 if (fep->full_duplex == DUPLEX_FULL) { 963 /* FD enable */ 964 writel(0x04, fep->hwp + FEC_X_CNTRL); 965 } else { 966 /* No Rcv on Xmit */ 967 rcntl |= 0x02; 968 writel(0x0, fep->hwp + FEC_X_CNTRL); 969 } 970 971 /* Set MII speed */ 972 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 973 974 #if !defined(CONFIG_M5272) 975 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 976 /* set RX checksum */ 977 val = readl(fep->hwp + FEC_RACC); 978 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 979 val |= FEC_RACC_OPTIONS; 980 else 981 val &= ~FEC_RACC_OPTIONS; 982 writel(val, fep->hwp + FEC_RACC); 983 } 984 #endif 985 986 /* 987 * The phy interface and speed need to get configured 988 * differently on enet-mac. 989 */ 990 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 991 /* Enable flow control and length check */ 992 rcntl |= 0x40000000 | 0x00000020; 993 994 /* RGMII, RMII or MII */ 995 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 996 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 997 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 998 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 999 rcntl |= (1 << 6); 1000 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1001 rcntl |= (1 << 8); 1002 else 1003 rcntl &= ~(1 << 8); 1004 1005 /* 1G, 100M or 10M */ 1006 if (fep->phy_dev) { 1007 if (fep->phy_dev->speed == SPEED_1000) 1008 ecntl |= (1 << 5); 1009 else if (fep->phy_dev->speed == SPEED_100) 1010 rcntl &= ~(1 << 9); 1011 else 1012 rcntl |= (1 << 9); 1013 } 1014 } else { 1015 #ifdef FEC_MIIGSK_ENR 1016 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1017 u32 cfgr; 1018 /* disable the gasket and wait */ 1019 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1020 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1021 udelay(1); 1022 1023 /* 1024 * configure the gasket: 1025 * RMII, 50 MHz, no loopback, no echo 1026 * MII, 25 MHz, no loopback, no echo 1027 */ 1028 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1029 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1030 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) 1031 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1032 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1033 1034 /* re-enable the gasket */ 1035 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1036 } 1037 #endif 1038 } 1039 1040 #if !defined(CONFIG_M5272) 1041 /* enable pause frame*/ 1042 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1043 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1044 fep->phy_dev && fep->phy_dev->pause)) { 1045 rcntl |= FEC_ENET_FCE; 1046 1047 /* set FIFO threshold parameter to reduce overrun */ 1048 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1049 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1050 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1051 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1052 1053 /* OPD */ 1054 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1055 } else { 1056 rcntl &= ~FEC_ENET_FCE; 1057 } 1058 #endif /* !defined(CONFIG_M5272) */ 1059 1060 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1061 1062 /* Setup multicast filter. */ 1063 set_multicast_list(ndev); 1064 #ifndef CONFIG_M5272 1065 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1066 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1067 #endif 1068 1069 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1070 /* enable ENET endian swap */ 1071 ecntl |= (1 << 8); 1072 /* enable ENET store and forward mode */ 1073 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1074 } 1075 1076 if (fep->bufdesc_ex) 1077 ecntl |= (1 << 4); 1078 1079 #ifndef CONFIG_M5272 1080 /* Enable the MIB statistic event counters */ 1081 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1082 #endif 1083 1084 /* And last, enable the transmit and receive processing */ 1085 writel(ecntl, fep->hwp + FEC_ECNTRL); 1086 fec_enet_active_rxring(ndev); 1087 1088 if (fep->bufdesc_ex) 1089 fec_ptp_start_cyclecounter(ndev); 1090 1091 /* Enable interrupts we wish to service */ 1092 if (fep->link) 1093 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1094 else 1095 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); 1096 1097 /* Init the interrupt coalescing */ 1098 fec_enet_itr_coal_init(ndev); 1099 1100 } 1101 1102 static void 1103 fec_stop(struct net_device *ndev) 1104 { 1105 struct fec_enet_private *fep = netdev_priv(ndev); 1106 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1107 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1108 u32 val; 1109 1110 /* We cannot expect a graceful transmit stop without link !!! */ 1111 if (fep->link) { 1112 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1113 udelay(10); 1114 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1115 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1116 } 1117 1118 /* Whack a reset. We should wait for this. 1119 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1120 * instead of reset MAC itself. 1121 */ 1122 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1123 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 1124 writel(0, fep->hwp + FEC_ECNTRL); 1125 } else { 1126 writel(1, fep->hwp + FEC_ECNTRL); 1127 udelay(10); 1128 } 1129 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1130 } else { 1131 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1132 val = readl(fep->hwp + FEC_ECNTRL); 1133 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1134 writel(val, fep->hwp + FEC_ECNTRL); 1135 1136 if (pdata && pdata->sleep_mode_enable) 1137 pdata->sleep_mode_enable(true); 1138 } 1139 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1140 1141 /* We have to keep ENET enabled to have MII interrupt stay working */ 1142 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1143 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1144 writel(2, fep->hwp + FEC_ECNTRL); 1145 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1146 } 1147 } 1148 1149 1150 static void 1151 fec_timeout(struct net_device *ndev) 1152 { 1153 struct fec_enet_private *fep = netdev_priv(ndev); 1154 1155 fec_dump(ndev); 1156 1157 ndev->stats.tx_errors++; 1158 1159 schedule_work(&fep->tx_timeout_work); 1160 } 1161 1162 static void fec_enet_timeout_work(struct work_struct *work) 1163 { 1164 struct fec_enet_private *fep = 1165 container_of(work, struct fec_enet_private, tx_timeout_work); 1166 struct net_device *ndev = fep->netdev; 1167 1168 rtnl_lock(); 1169 if (netif_device_present(ndev) || netif_running(ndev)) { 1170 napi_disable(&fep->napi); 1171 netif_tx_lock_bh(ndev); 1172 fec_restart(ndev); 1173 netif_wake_queue(ndev); 1174 netif_tx_unlock_bh(ndev); 1175 napi_enable(&fep->napi); 1176 } 1177 rtnl_unlock(); 1178 } 1179 1180 static void 1181 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1182 struct skb_shared_hwtstamps *hwtstamps) 1183 { 1184 unsigned long flags; 1185 u64 ns; 1186 1187 spin_lock_irqsave(&fep->tmreg_lock, flags); 1188 ns = timecounter_cyc2time(&fep->tc, ts); 1189 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1190 1191 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1192 hwtstamps->hwtstamp = ns_to_ktime(ns); 1193 } 1194 1195 static void 1196 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1197 { 1198 struct fec_enet_private *fep; 1199 struct bufdesc *bdp; 1200 unsigned short status; 1201 struct sk_buff *skb; 1202 struct fec_enet_priv_tx_q *txq; 1203 struct netdev_queue *nq; 1204 int index = 0; 1205 int entries_free; 1206 1207 fep = netdev_priv(ndev); 1208 1209 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1210 1211 txq = fep->tx_queue[queue_id]; 1212 /* get next bdp of dirty_tx */ 1213 nq = netdev_get_tx_queue(ndev, queue_id); 1214 bdp = txq->dirty_tx; 1215 1216 /* get next bdp of dirty_tx */ 1217 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id); 1218 1219 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { 1220 1221 /* current queue is empty */ 1222 if (bdp == txq->cur_tx) 1223 break; 1224 1225 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep); 1226 1227 skb = txq->tx_skbuff[index]; 1228 txq->tx_skbuff[index] = NULL; 1229 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr)) 1230 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 1231 bdp->cbd_datlen, DMA_TO_DEVICE); 1232 bdp->cbd_bufaddr = 0; 1233 if (!skb) { 1234 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id); 1235 continue; 1236 } 1237 1238 /* Check for errors. */ 1239 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1240 BD_ENET_TX_RL | BD_ENET_TX_UN | 1241 BD_ENET_TX_CSL)) { 1242 ndev->stats.tx_errors++; 1243 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1244 ndev->stats.tx_heartbeat_errors++; 1245 if (status & BD_ENET_TX_LC) /* Late collision */ 1246 ndev->stats.tx_window_errors++; 1247 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1248 ndev->stats.tx_aborted_errors++; 1249 if (status & BD_ENET_TX_UN) /* Underrun */ 1250 ndev->stats.tx_fifo_errors++; 1251 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1252 ndev->stats.tx_carrier_errors++; 1253 } else { 1254 ndev->stats.tx_packets++; 1255 ndev->stats.tx_bytes += skb->len; 1256 } 1257 1258 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 1259 fep->bufdesc_ex) { 1260 struct skb_shared_hwtstamps shhwtstamps; 1261 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1262 1263 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps); 1264 skb_tstamp_tx(skb, &shhwtstamps); 1265 } 1266 1267 /* Deferred means some collisions occurred during transmit, 1268 * but we eventually sent the packet OK. 1269 */ 1270 if (status & BD_ENET_TX_DEF) 1271 ndev->stats.collisions++; 1272 1273 /* Free the sk buffer associated with this last transmit */ 1274 dev_kfree_skb_any(skb); 1275 1276 txq->dirty_tx = bdp; 1277 1278 /* Update pointer to next buffer descriptor to be transmitted */ 1279 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id); 1280 1281 /* Since we have freed up a buffer, the ring is no longer full 1282 */ 1283 if (netif_queue_stopped(ndev)) { 1284 entries_free = fec_enet_get_free_txdesc_num(fep, txq); 1285 if (entries_free >= txq->tx_wake_threshold) 1286 netif_tx_wake_queue(nq); 1287 } 1288 } 1289 1290 /* ERR006538: Keep the transmitter going */ 1291 if (bdp != txq->cur_tx && 1292 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0) 1293 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id)); 1294 } 1295 1296 static void 1297 fec_enet_tx(struct net_device *ndev) 1298 { 1299 struct fec_enet_private *fep = netdev_priv(ndev); 1300 u16 queue_id; 1301 /* First process class A queue, then Class B and Best Effort queue */ 1302 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) { 1303 clear_bit(queue_id, &fep->work_tx); 1304 fec_enet_tx_queue(ndev, queue_id); 1305 } 1306 return; 1307 } 1308 1309 static int 1310 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1311 { 1312 struct fec_enet_private *fep = netdev_priv(ndev); 1313 int off; 1314 1315 off = ((unsigned long)skb->data) & fep->rx_align; 1316 if (off) 1317 skb_reserve(skb, fep->rx_align + 1 - off); 1318 1319 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, 1320 FEC_ENET_RX_FRSIZE - fep->rx_align, 1321 DMA_FROM_DEVICE); 1322 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) { 1323 if (net_ratelimit()) 1324 netdev_err(ndev, "Rx DMA memory map failed\n"); 1325 return -ENOMEM; 1326 } 1327 1328 return 0; 1329 } 1330 1331 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1332 struct bufdesc *bdp, u32 length, bool swap) 1333 { 1334 struct fec_enet_private *fep = netdev_priv(ndev); 1335 struct sk_buff *new_skb; 1336 1337 if (length > fep->rx_copybreak) 1338 return false; 1339 1340 new_skb = netdev_alloc_skb(ndev, length); 1341 if (!new_skb) 1342 return false; 1343 1344 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr, 1345 FEC_ENET_RX_FRSIZE - fep->rx_align, 1346 DMA_FROM_DEVICE); 1347 if (!swap) 1348 memcpy(new_skb->data, (*skb)->data, length); 1349 else 1350 swap_buffer2(new_skb->data, (*skb)->data, length); 1351 *skb = new_skb; 1352 1353 return true; 1354 } 1355 1356 /* During a receive, the cur_rx points to the current incoming buffer. 1357 * When we update through the ring, if the next incoming buffer has 1358 * not been given to the system, we just set the empty indicator, 1359 * effectively tossing the packet. 1360 */ 1361 static int 1362 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1363 { 1364 struct fec_enet_private *fep = netdev_priv(ndev); 1365 struct fec_enet_priv_rx_q *rxq; 1366 struct bufdesc *bdp; 1367 unsigned short status; 1368 struct sk_buff *skb_new = NULL; 1369 struct sk_buff *skb; 1370 ushort pkt_len; 1371 __u8 *data; 1372 int pkt_received = 0; 1373 struct bufdesc_ex *ebdp = NULL; 1374 bool vlan_packet_rcvd = false; 1375 u16 vlan_tag; 1376 int index = 0; 1377 bool is_copybreak; 1378 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1379 1380 #ifdef CONFIG_M532x 1381 flush_cache_all(); 1382 #endif 1383 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1384 rxq = fep->rx_queue[queue_id]; 1385 1386 /* First, grab all of the stats for the incoming packet. 1387 * These get messed up if we get called due to a busy condition. 1388 */ 1389 bdp = rxq->cur_rx; 1390 1391 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { 1392 1393 if (pkt_received >= budget) 1394 break; 1395 pkt_received++; 1396 1397 /* Since we have allocated space to hold a complete frame, 1398 * the last indicator should be set. 1399 */ 1400 if ((status & BD_ENET_RX_LAST) == 0) 1401 netdev_err(ndev, "rcv is not +last\n"); 1402 1403 1404 /* Check for errors. */ 1405 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1406 BD_ENET_RX_CR | BD_ENET_RX_OV)) { 1407 ndev->stats.rx_errors++; 1408 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { 1409 /* Frame too long or too short. */ 1410 ndev->stats.rx_length_errors++; 1411 } 1412 if (status & BD_ENET_RX_NO) /* Frame alignment */ 1413 ndev->stats.rx_frame_errors++; 1414 if (status & BD_ENET_RX_CR) /* CRC Error */ 1415 ndev->stats.rx_crc_errors++; 1416 if (status & BD_ENET_RX_OV) /* FIFO overrun */ 1417 ndev->stats.rx_fifo_errors++; 1418 } 1419 1420 /* Report late collisions as a frame error. 1421 * On this error, the BD is closed, but we don't know what we 1422 * have in the buffer. So, just drop this frame on the floor. 1423 */ 1424 if (status & BD_ENET_RX_CL) { 1425 ndev->stats.rx_errors++; 1426 ndev->stats.rx_frame_errors++; 1427 goto rx_processing_done; 1428 } 1429 1430 /* Process the incoming frame. */ 1431 ndev->stats.rx_packets++; 1432 pkt_len = bdp->cbd_datlen; 1433 ndev->stats.rx_bytes += pkt_len; 1434 1435 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep); 1436 skb = rxq->rx_skbuff[index]; 1437 1438 /* The packet length includes FCS, but we don't want to 1439 * include that when passing upstream as it messes up 1440 * bridging applications. 1441 */ 1442 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1443 need_swap); 1444 if (!is_copybreak) { 1445 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1446 if (unlikely(!skb_new)) { 1447 ndev->stats.rx_dropped++; 1448 goto rx_processing_done; 1449 } 1450 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 1451 FEC_ENET_RX_FRSIZE - fep->rx_align, 1452 DMA_FROM_DEVICE); 1453 } 1454 1455 prefetch(skb->data - NET_IP_ALIGN); 1456 skb_put(skb, pkt_len - 4); 1457 data = skb->data; 1458 if (!is_copybreak && need_swap) 1459 swap_buffer(data, pkt_len); 1460 1461 /* Extract the enhanced buffer descriptor */ 1462 ebdp = NULL; 1463 if (fep->bufdesc_ex) 1464 ebdp = (struct bufdesc_ex *)bdp; 1465 1466 /* If this is a VLAN packet remove the VLAN Tag */ 1467 vlan_packet_rcvd = false; 1468 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1469 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) { 1470 /* Push and remove the vlan tag */ 1471 struct vlan_hdr *vlan_header = 1472 (struct vlan_hdr *) (data + ETH_HLEN); 1473 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1474 1475 vlan_packet_rcvd = true; 1476 1477 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1478 skb_pull(skb, VLAN_HLEN); 1479 } 1480 1481 skb->protocol = eth_type_trans(skb, ndev); 1482 1483 /* Get receive timestamp from the skb */ 1484 if (fep->hwts_rx_en && fep->bufdesc_ex) 1485 fec_enet_hwtstamp(fep, ebdp->ts, 1486 skb_hwtstamps(skb)); 1487 1488 if (fep->bufdesc_ex && 1489 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1490 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) { 1491 /* don't check it */ 1492 skb->ip_summed = CHECKSUM_UNNECESSARY; 1493 } else { 1494 skb_checksum_none_assert(skb); 1495 } 1496 } 1497 1498 /* Handle received VLAN packets */ 1499 if (vlan_packet_rcvd) 1500 __vlan_hwaccel_put_tag(skb, 1501 htons(ETH_P_8021Q), 1502 vlan_tag); 1503 1504 napi_gro_receive(&fep->napi, skb); 1505 1506 if (is_copybreak) { 1507 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr, 1508 FEC_ENET_RX_FRSIZE - fep->rx_align, 1509 DMA_FROM_DEVICE); 1510 } else { 1511 rxq->rx_skbuff[index] = skb_new; 1512 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1513 } 1514 1515 rx_processing_done: 1516 /* Clear the status flags for this buffer */ 1517 status &= ~BD_ENET_RX_STATS; 1518 1519 /* Mark the buffer empty */ 1520 status |= BD_ENET_RX_EMPTY; 1521 bdp->cbd_sc = status; 1522 1523 if (fep->bufdesc_ex) { 1524 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1525 1526 ebdp->cbd_esc = BD_ENET_RX_INT; 1527 ebdp->cbd_prot = 0; 1528 ebdp->cbd_bdu = 0; 1529 } 1530 1531 /* Update BD pointer to next entry */ 1532 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id); 1533 1534 /* Doing this here will keep the FEC running while we process 1535 * incoming frames. On a heavily loaded network, we should be 1536 * able to keep up at the expense of system resources. 1537 */ 1538 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id)); 1539 } 1540 rxq->cur_rx = bdp; 1541 return pkt_received; 1542 } 1543 1544 static int 1545 fec_enet_rx(struct net_device *ndev, int budget) 1546 { 1547 int pkt_received = 0; 1548 u16 queue_id; 1549 struct fec_enet_private *fep = netdev_priv(ndev); 1550 1551 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) { 1552 clear_bit(queue_id, &fep->work_rx); 1553 pkt_received += fec_enet_rx_queue(ndev, 1554 budget - pkt_received, queue_id); 1555 } 1556 return pkt_received; 1557 } 1558 1559 static bool 1560 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events) 1561 { 1562 if (int_events == 0) 1563 return false; 1564 1565 if (int_events & FEC_ENET_RXF) 1566 fep->work_rx |= (1 << 2); 1567 if (int_events & FEC_ENET_RXF_1) 1568 fep->work_rx |= (1 << 0); 1569 if (int_events & FEC_ENET_RXF_2) 1570 fep->work_rx |= (1 << 1); 1571 1572 if (int_events & FEC_ENET_TXF) 1573 fep->work_tx |= (1 << 2); 1574 if (int_events & FEC_ENET_TXF_1) 1575 fep->work_tx |= (1 << 0); 1576 if (int_events & FEC_ENET_TXF_2) 1577 fep->work_tx |= (1 << 1); 1578 1579 return true; 1580 } 1581 1582 static irqreturn_t 1583 fec_enet_interrupt(int irq, void *dev_id) 1584 { 1585 struct net_device *ndev = dev_id; 1586 struct fec_enet_private *fep = netdev_priv(ndev); 1587 uint int_events; 1588 irqreturn_t ret = IRQ_NONE; 1589 1590 int_events = readl(fep->hwp + FEC_IEVENT); 1591 writel(int_events, fep->hwp + FEC_IEVENT); 1592 fec_enet_collect_events(fep, int_events); 1593 1594 if ((fep->work_tx || fep->work_rx) && fep->link) { 1595 ret = IRQ_HANDLED; 1596 1597 if (napi_schedule_prep(&fep->napi)) { 1598 /* Disable the NAPI interrupts */ 1599 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); 1600 __napi_schedule(&fep->napi); 1601 } 1602 } 1603 1604 if (int_events & FEC_ENET_MII) { 1605 ret = IRQ_HANDLED; 1606 complete(&fep->mdio_done); 1607 } 1608 1609 if (fep->ptp_clock) 1610 fec_ptp_check_pps_event(fep); 1611 1612 return ret; 1613 } 1614 1615 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1616 { 1617 struct net_device *ndev = napi->dev; 1618 struct fec_enet_private *fep = netdev_priv(ndev); 1619 int pkts; 1620 1621 pkts = fec_enet_rx(ndev, budget); 1622 1623 fec_enet_tx(ndev); 1624 1625 if (pkts < budget) { 1626 napi_complete(napi); 1627 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1628 } 1629 return pkts; 1630 } 1631 1632 /* ------------------------------------------------------------------------- */ 1633 static void fec_get_mac(struct net_device *ndev) 1634 { 1635 struct fec_enet_private *fep = netdev_priv(ndev); 1636 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1637 unsigned char *iap, tmpaddr[ETH_ALEN]; 1638 1639 /* 1640 * try to get mac address in following order: 1641 * 1642 * 1) module parameter via kernel command line in form 1643 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1644 */ 1645 iap = macaddr; 1646 1647 /* 1648 * 2) from device tree data 1649 */ 1650 if (!is_valid_ether_addr(iap)) { 1651 struct device_node *np = fep->pdev->dev.of_node; 1652 if (np) { 1653 const char *mac = of_get_mac_address(np); 1654 if (mac) 1655 iap = (unsigned char *) mac; 1656 } 1657 } 1658 1659 /* 1660 * 3) from flash or fuse (via platform data) 1661 */ 1662 if (!is_valid_ether_addr(iap)) { 1663 #ifdef CONFIG_M5272 1664 if (FEC_FLASHMAC) 1665 iap = (unsigned char *)FEC_FLASHMAC; 1666 #else 1667 if (pdata) 1668 iap = (unsigned char *)&pdata->mac; 1669 #endif 1670 } 1671 1672 /* 1673 * 4) FEC mac registers set by bootloader 1674 */ 1675 if (!is_valid_ether_addr(iap)) { 1676 *((__be32 *) &tmpaddr[0]) = 1677 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1678 *((__be16 *) &tmpaddr[4]) = 1679 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1680 iap = &tmpaddr[0]; 1681 } 1682 1683 /* 1684 * 5) random mac address 1685 */ 1686 if (!is_valid_ether_addr(iap)) { 1687 /* Report it and use a random ethernet address instead */ 1688 netdev_err(ndev, "Invalid MAC address: %pM\n", iap); 1689 eth_hw_addr_random(ndev); 1690 netdev_info(ndev, "Using random MAC address: %pM\n", 1691 ndev->dev_addr); 1692 return; 1693 } 1694 1695 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1696 1697 /* Adjust MAC if using macaddr */ 1698 if (iap == macaddr) 1699 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1700 } 1701 1702 /* ------------------------------------------------------------------------- */ 1703 1704 /* 1705 * Phy section 1706 */ 1707 static void fec_enet_adjust_link(struct net_device *ndev) 1708 { 1709 struct fec_enet_private *fep = netdev_priv(ndev); 1710 struct phy_device *phy_dev = fep->phy_dev; 1711 int status_change = 0; 1712 1713 /* Prevent a state halted on mii error */ 1714 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 1715 phy_dev->state = PHY_RESUMING; 1716 return; 1717 } 1718 1719 /* 1720 * If the netdev is down, or is going down, we're not interested 1721 * in link state events, so just mark our idea of the link as down 1722 * and ignore the event. 1723 */ 1724 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1725 fep->link = 0; 1726 } else if (phy_dev->link) { 1727 if (!fep->link) { 1728 fep->link = phy_dev->link; 1729 status_change = 1; 1730 } 1731 1732 if (fep->full_duplex != phy_dev->duplex) { 1733 fep->full_duplex = phy_dev->duplex; 1734 status_change = 1; 1735 } 1736 1737 if (phy_dev->speed != fep->speed) { 1738 fep->speed = phy_dev->speed; 1739 status_change = 1; 1740 } 1741 1742 /* if any of the above changed restart the FEC */ 1743 if (status_change) { 1744 napi_disable(&fep->napi); 1745 netif_tx_lock_bh(ndev); 1746 fec_restart(ndev); 1747 netif_wake_queue(ndev); 1748 netif_tx_unlock_bh(ndev); 1749 napi_enable(&fep->napi); 1750 } 1751 } else { 1752 if (fep->link) { 1753 napi_disable(&fep->napi); 1754 netif_tx_lock_bh(ndev); 1755 fec_stop(ndev); 1756 netif_tx_unlock_bh(ndev); 1757 napi_enable(&fep->napi); 1758 fep->link = phy_dev->link; 1759 status_change = 1; 1760 } 1761 } 1762 1763 if (status_change) 1764 phy_print_status(phy_dev); 1765 } 1766 1767 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1768 { 1769 struct fec_enet_private *fep = bus->priv; 1770 unsigned long time_left; 1771 1772 fep->mii_timeout = 0; 1773 init_completion(&fep->mdio_done); 1774 1775 /* start a read op */ 1776 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 1777 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1778 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1779 1780 /* wait for end of transfer */ 1781 time_left = wait_for_completion_timeout(&fep->mdio_done, 1782 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1783 if (time_left == 0) { 1784 fep->mii_timeout = 1; 1785 netdev_err(fep->netdev, "MDIO read timeout\n"); 1786 return -ETIMEDOUT; 1787 } 1788 1789 /* return value */ 1790 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1791 } 1792 1793 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1794 u16 value) 1795 { 1796 struct fec_enet_private *fep = bus->priv; 1797 unsigned long time_left; 1798 1799 fep->mii_timeout = 0; 1800 init_completion(&fep->mdio_done); 1801 1802 /* start a write op */ 1803 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 1804 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1805 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1806 fep->hwp + FEC_MII_DATA); 1807 1808 /* wait for end of transfer */ 1809 time_left = wait_for_completion_timeout(&fep->mdio_done, 1810 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1811 if (time_left == 0) { 1812 fep->mii_timeout = 1; 1813 netdev_err(fep->netdev, "MDIO write timeout\n"); 1814 return -ETIMEDOUT; 1815 } 1816 1817 return 0; 1818 } 1819 1820 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1821 { 1822 struct fec_enet_private *fep = netdev_priv(ndev); 1823 int ret; 1824 1825 if (enable) { 1826 ret = clk_prepare_enable(fep->clk_ahb); 1827 if (ret) 1828 return ret; 1829 ret = clk_prepare_enable(fep->clk_ipg); 1830 if (ret) 1831 goto failed_clk_ipg; 1832 if (fep->clk_enet_out) { 1833 ret = clk_prepare_enable(fep->clk_enet_out); 1834 if (ret) 1835 goto failed_clk_enet_out; 1836 } 1837 if (fep->clk_ptp) { 1838 mutex_lock(&fep->ptp_clk_mutex); 1839 ret = clk_prepare_enable(fep->clk_ptp); 1840 if (ret) { 1841 mutex_unlock(&fep->ptp_clk_mutex); 1842 goto failed_clk_ptp; 1843 } else { 1844 fep->ptp_clk_on = true; 1845 } 1846 mutex_unlock(&fep->ptp_clk_mutex); 1847 } 1848 if (fep->clk_ref) { 1849 ret = clk_prepare_enable(fep->clk_ref); 1850 if (ret) 1851 goto failed_clk_ref; 1852 } 1853 } else { 1854 clk_disable_unprepare(fep->clk_ahb); 1855 clk_disable_unprepare(fep->clk_ipg); 1856 if (fep->clk_enet_out) 1857 clk_disable_unprepare(fep->clk_enet_out); 1858 if (fep->clk_ptp) { 1859 mutex_lock(&fep->ptp_clk_mutex); 1860 clk_disable_unprepare(fep->clk_ptp); 1861 fep->ptp_clk_on = false; 1862 mutex_unlock(&fep->ptp_clk_mutex); 1863 } 1864 if (fep->clk_ref) 1865 clk_disable_unprepare(fep->clk_ref); 1866 } 1867 1868 return 0; 1869 1870 failed_clk_ref: 1871 if (fep->clk_ref) 1872 clk_disable_unprepare(fep->clk_ref); 1873 failed_clk_ptp: 1874 if (fep->clk_enet_out) 1875 clk_disable_unprepare(fep->clk_enet_out); 1876 failed_clk_enet_out: 1877 clk_disable_unprepare(fep->clk_ipg); 1878 failed_clk_ipg: 1879 clk_disable_unprepare(fep->clk_ahb); 1880 1881 return ret; 1882 } 1883 1884 static int fec_enet_mii_probe(struct net_device *ndev) 1885 { 1886 struct fec_enet_private *fep = netdev_priv(ndev); 1887 struct phy_device *phy_dev = NULL; 1888 char mdio_bus_id[MII_BUS_ID_SIZE]; 1889 char phy_name[MII_BUS_ID_SIZE + 3]; 1890 int phy_id; 1891 int dev_id = fep->dev_id; 1892 1893 fep->phy_dev = NULL; 1894 1895 if (fep->phy_node) { 1896 phy_dev = of_phy_connect(ndev, fep->phy_node, 1897 &fec_enet_adjust_link, 0, 1898 fep->phy_interface); 1899 if (!phy_dev) 1900 return -ENODEV; 1901 } else { 1902 /* check for attached phy */ 1903 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1904 if ((fep->mii_bus->phy_mask & (1 << phy_id))) 1905 continue; 1906 if (fep->mii_bus->phy_map[phy_id] == NULL) 1907 continue; 1908 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) 1909 continue; 1910 if (dev_id--) 1911 continue; 1912 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1913 break; 1914 } 1915 1916 if (phy_id >= PHY_MAX_ADDR) { 1917 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1918 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 1919 phy_id = 0; 1920 } 1921 1922 snprintf(phy_name, sizeof(phy_name), 1923 PHY_ID_FMT, mdio_bus_id, phy_id); 1924 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 1925 fep->phy_interface); 1926 } 1927 1928 if (IS_ERR(phy_dev)) { 1929 netdev_err(ndev, "could not attach to PHY\n"); 1930 return PTR_ERR(phy_dev); 1931 } 1932 1933 /* mask with MAC supported features */ 1934 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 1935 phy_dev->supported &= PHY_GBIT_FEATURES; 1936 phy_dev->supported &= ~SUPPORTED_1000baseT_Half; 1937 #if !defined(CONFIG_M5272) 1938 phy_dev->supported |= SUPPORTED_Pause; 1939 #endif 1940 } 1941 else 1942 phy_dev->supported &= PHY_BASIC_FEATURES; 1943 1944 phy_dev->advertising = phy_dev->supported; 1945 1946 fep->phy_dev = phy_dev; 1947 fep->link = 0; 1948 fep->full_duplex = 0; 1949 1950 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 1951 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), 1952 fep->phy_dev->irq); 1953 1954 return 0; 1955 } 1956 1957 static int fec_enet_mii_init(struct platform_device *pdev) 1958 { 1959 static struct mii_bus *fec0_mii_bus; 1960 struct net_device *ndev = platform_get_drvdata(pdev); 1961 struct fec_enet_private *fep = netdev_priv(ndev); 1962 struct device_node *node; 1963 int err = -ENXIO, i; 1964 u32 mii_speed, holdtime; 1965 1966 /* 1967 * The i.MX28 dual fec interfaces are not equal. 1968 * Here are the differences: 1969 * 1970 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1971 * - fec0 acts as the 1588 time master while fec1 is slave 1972 * - external phys can only be configured by fec0 1973 * 1974 * That is to say fec1 can not work independently. It only works 1975 * when fec0 is working. The reason behind this design is that the 1976 * second interface is added primarily for Switch mode. 1977 * 1978 * Because of the last point above, both phys are attached on fec0 1979 * mdio interface in board design, and need to be configured by 1980 * fec0 mii_bus. 1981 */ 1982 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 1983 /* fec1 uses fec0 mii_bus */ 1984 if (mii_cnt && fec0_mii_bus) { 1985 fep->mii_bus = fec0_mii_bus; 1986 mii_cnt++; 1987 return 0; 1988 } 1989 return -ENOENT; 1990 } 1991 1992 fep->mii_timeout = 0; 1993 1994 /* 1995 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 1996 * 1997 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 1998 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 1999 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2000 * document. 2001 */ 2002 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000); 2003 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2004 mii_speed--; 2005 if (mii_speed > 63) { 2006 dev_err(&pdev->dev, 2007 "fec clock (%lu) to fast to get right mii speed\n", 2008 clk_get_rate(fep->clk_ipg)); 2009 err = -EINVAL; 2010 goto err_out; 2011 } 2012 2013 /* 2014 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2015 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2016 * versions are RAZ there, so just ignore the difference and write the 2017 * register always. 2018 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2019 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2020 * output. 2021 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2022 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2023 * holdtime cannot result in a value greater than 3. 2024 */ 2025 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2026 2027 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2028 2029 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2030 2031 fep->mii_bus = mdiobus_alloc(); 2032 if (fep->mii_bus == NULL) { 2033 err = -ENOMEM; 2034 goto err_out; 2035 } 2036 2037 fep->mii_bus->name = "fec_enet_mii_bus"; 2038 fep->mii_bus->read = fec_enet_mdio_read; 2039 fep->mii_bus->write = fec_enet_mdio_write; 2040 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2041 pdev->name, fep->dev_id + 1); 2042 fep->mii_bus->priv = fep; 2043 fep->mii_bus->parent = &pdev->dev; 2044 2045 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 2046 if (!fep->mii_bus->irq) { 2047 err = -ENOMEM; 2048 goto err_out_free_mdiobus; 2049 } 2050 2051 for (i = 0; i < PHY_MAX_ADDR; i++) 2052 fep->mii_bus->irq[i] = PHY_POLL; 2053 2054 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2055 if (node) { 2056 err = of_mdiobus_register(fep->mii_bus, node); 2057 of_node_put(node); 2058 } else { 2059 err = mdiobus_register(fep->mii_bus); 2060 } 2061 2062 if (err) 2063 goto err_out_free_mdio_irq; 2064 2065 mii_cnt++; 2066 2067 /* save fec0 mii_bus */ 2068 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2069 fec0_mii_bus = fep->mii_bus; 2070 2071 return 0; 2072 2073 err_out_free_mdio_irq: 2074 kfree(fep->mii_bus->irq); 2075 err_out_free_mdiobus: 2076 mdiobus_free(fep->mii_bus); 2077 err_out: 2078 return err; 2079 } 2080 2081 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2082 { 2083 if (--mii_cnt == 0) { 2084 mdiobus_unregister(fep->mii_bus); 2085 kfree(fep->mii_bus->irq); 2086 mdiobus_free(fep->mii_bus); 2087 } 2088 } 2089 2090 static int fec_enet_get_settings(struct net_device *ndev, 2091 struct ethtool_cmd *cmd) 2092 { 2093 struct fec_enet_private *fep = netdev_priv(ndev); 2094 struct phy_device *phydev = fep->phy_dev; 2095 2096 if (!phydev) 2097 return -ENODEV; 2098 2099 return phy_ethtool_gset(phydev, cmd); 2100 } 2101 2102 static int fec_enet_set_settings(struct net_device *ndev, 2103 struct ethtool_cmd *cmd) 2104 { 2105 struct fec_enet_private *fep = netdev_priv(ndev); 2106 struct phy_device *phydev = fep->phy_dev; 2107 2108 if (!phydev) 2109 return -ENODEV; 2110 2111 return phy_ethtool_sset(phydev, cmd); 2112 } 2113 2114 static void fec_enet_get_drvinfo(struct net_device *ndev, 2115 struct ethtool_drvinfo *info) 2116 { 2117 struct fec_enet_private *fep = netdev_priv(ndev); 2118 2119 strlcpy(info->driver, fep->pdev->dev.driver->name, 2120 sizeof(info->driver)); 2121 strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); 2122 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2123 } 2124 2125 static int fec_enet_get_regs_len(struct net_device *ndev) 2126 { 2127 struct fec_enet_private *fep = netdev_priv(ndev); 2128 struct resource *r; 2129 int s = 0; 2130 2131 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2132 if (r) 2133 s = resource_size(r); 2134 2135 return s; 2136 } 2137 2138 /* List of registers that can be safety be read to dump them with ethtool */ 2139 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2140 defined(CONFIG_M520x) || defined(CONFIG_M532x) || \ 2141 defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) 2142 static u32 fec_enet_register_offset[] = { 2143 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2144 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2145 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2146 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2147 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2148 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2149 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2150 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2151 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2152 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2153 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2154 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2155 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2156 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2157 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2158 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2159 RMON_T_P_GTE2048, RMON_T_OCTETS, 2160 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2161 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2162 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2163 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2164 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2165 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2166 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2167 RMON_R_P_GTE2048, RMON_R_OCTETS, 2168 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2169 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2170 }; 2171 #else 2172 static u32 fec_enet_register_offset[] = { 2173 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2174 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2175 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2176 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2177 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2178 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2179 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2180 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2181 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2182 }; 2183 #endif 2184 2185 static void fec_enet_get_regs(struct net_device *ndev, 2186 struct ethtool_regs *regs, void *regbuf) 2187 { 2188 struct fec_enet_private *fep = netdev_priv(ndev); 2189 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2190 u32 *buf = (u32 *)regbuf; 2191 u32 i, off; 2192 2193 memset(buf, 0, regs->len); 2194 2195 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2196 off = fec_enet_register_offset[i] / 4; 2197 buf[off] = readl(&theregs[off]); 2198 } 2199 } 2200 2201 static int fec_enet_get_ts_info(struct net_device *ndev, 2202 struct ethtool_ts_info *info) 2203 { 2204 struct fec_enet_private *fep = netdev_priv(ndev); 2205 2206 if (fep->bufdesc_ex) { 2207 2208 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2209 SOF_TIMESTAMPING_RX_SOFTWARE | 2210 SOF_TIMESTAMPING_SOFTWARE | 2211 SOF_TIMESTAMPING_TX_HARDWARE | 2212 SOF_TIMESTAMPING_RX_HARDWARE | 2213 SOF_TIMESTAMPING_RAW_HARDWARE; 2214 if (fep->ptp_clock) 2215 info->phc_index = ptp_clock_index(fep->ptp_clock); 2216 else 2217 info->phc_index = -1; 2218 2219 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2220 (1 << HWTSTAMP_TX_ON); 2221 2222 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2223 (1 << HWTSTAMP_FILTER_ALL); 2224 return 0; 2225 } else { 2226 return ethtool_op_get_ts_info(ndev, info); 2227 } 2228 } 2229 2230 #if !defined(CONFIG_M5272) 2231 2232 static void fec_enet_get_pauseparam(struct net_device *ndev, 2233 struct ethtool_pauseparam *pause) 2234 { 2235 struct fec_enet_private *fep = netdev_priv(ndev); 2236 2237 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2238 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2239 pause->rx_pause = pause->tx_pause; 2240 } 2241 2242 static int fec_enet_set_pauseparam(struct net_device *ndev, 2243 struct ethtool_pauseparam *pause) 2244 { 2245 struct fec_enet_private *fep = netdev_priv(ndev); 2246 2247 if (!fep->phy_dev) 2248 return -ENODEV; 2249 2250 if (pause->tx_pause != pause->rx_pause) { 2251 netdev_info(ndev, 2252 "hardware only support enable/disable both tx and rx"); 2253 return -EINVAL; 2254 } 2255 2256 fep->pause_flag = 0; 2257 2258 /* tx pause must be same as rx pause */ 2259 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2260 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2261 2262 if (pause->rx_pause || pause->autoneg) { 2263 fep->phy_dev->supported |= ADVERTISED_Pause; 2264 fep->phy_dev->advertising |= ADVERTISED_Pause; 2265 } else { 2266 fep->phy_dev->supported &= ~ADVERTISED_Pause; 2267 fep->phy_dev->advertising &= ~ADVERTISED_Pause; 2268 } 2269 2270 if (pause->autoneg) { 2271 if (netif_running(ndev)) 2272 fec_stop(ndev); 2273 phy_start_aneg(fep->phy_dev); 2274 } 2275 if (netif_running(ndev)) { 2276 napi_disable(&fep->napi); 2277 netif_tx_lock_bh(ndev); 2278 fec_restart(ndev); 2279 netif_wake_queue(ndev); 2280 netif_tx_unlock_bh(ndev); 2281 napi_enable(&fep->napi); 2282 } 2283 2284 return 0; 2285 } 2286 2287 static const struct fec_stat { 2288 char name[ETH_GSTRING_LEN]; 2289 u16 offset; 2290 } fec_stats[] = { 2291 /* RMON TX */ 2292 { "tx_dropped", RMON_T_DROP }, 2293 { "tx_packets", RMON_T_PACKETS }, 2294 { "tx_broadcast", RMON_T_BC_PKT }, 2295 { "tx_multicast", RMON_T_MC_PKT }, 2296 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2297 { "tx_undersize", RMON_T_UNDERSIZE }, 2298 { "tx_oversize", RMON_T_OVERSIZE }, 2299 { "tx_fragment", RMON_T_FRAG }, 2300 { "tx_jabber", RMON_T_JAB }, 2301 { "tx_collision", RMON_T_COL }, 2302 { "tx_64byte", RMON_T_P64 }, 2303 { "tx_65to127byte", RMON_T_P65TO127 }, 2304 { "tx_128to255byte", RMON_T_P128TO255 }, 2305 { "tx_256to511byte", RMON_T_P256TO511 }, 2306 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2307 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2308 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2309 { "tx_octets", RMON_T_OCTETS }, 2310 2311 /* IEEE TX */ 2312 { "IEEE_tx_drop", IEEE_T_DROP }, 2313 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2314 { "IEEE_tx_1col", IEEE_T_1COL }, 2315 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2316 { "IEEE_tx_def", IEEE_T_DEF }, 2317 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2318 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2319 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2320 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2321 { "IEEE_tx_sqe", IEEE_T_SQE }, 2322 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2323 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2324 2325 /* RMON RX */ 2326 { "rx_packets", RMON_R_PACKETS }, 2327 { "rx_broadcast", RMON_R_BC_PKT }, 2328 { "rx_multicast", RMON_R_MC_PKT }, 2329 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2330 { "rx_undersize", RMON_R_UNDERSIZE }, 2331 { "rx_oversize", RMON_R_OVERSIZE }, 2332 { "rx_fragment", RMON_R_FRAG }, 2333 { "rx_jabber", RMON_R_JAB }, 2334 { "rx_64byte", RMON_R_P64 }, 2335 { "rx_65to127byte", RMON_R_P65TO127 }, 2336 { "rx_128to255byte", RMON_R_P128TO255 }, 2337 { "rx_256to511byte", RMON_R_P256TO511 }, 2338 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2339 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2340 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2341 { "rx_octets", RMON_R_OCTETS }, 2342 2343 /* IEEE RX */ 2344 { "IEEE_rx_drop", IEEE_R_DROP }, 2345 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2346 { "IEEE_rx_crc", IEEE_R_CRC }, 2347 { "IEEE_rx_align", IEEE_R_ALIGN }, 2348 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2349 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2350 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2351 }; 2352 2353 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2354 struct ethtool_stats *stats, u64 *data) 2355 { 2356 struct fec_enet_private *fep = netdev_priv(dev); 2357 int i; 2358 2359 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2360 data[i] = readl(fep->hwp + fec_stats[i].offset); 2361 } 2362 2363 static void fec_enet_get_strings(struct net_device *netdev, 2364 u32 stringset, u8 *data) 2365 { 2366 int i; 2367 switch (stringset) { 2368 case ETH_SS_STATS: 2369 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2370 memcpy(data + i * ETH_GSTRING_LEN, 2371 fec_stats[i].name, ETH_GSTRING_LEN); 2372 break; 2373 } 2374 } 2375 2376 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2377 { 2378 switch (sset) { 2379 case ETH_SS_STATS: 2380 return ARRAY_SIZE(fec_stats); 2381 default: 2382 return -EOPNOTSUPP; 2383 } 2384 } 2385 #endif /* !defined(CONFIG_M5272) */ 2386 2387 static int fec_enet_nway_reset(struct net_device *dev) 2388 { 2389 struct fec_enet_private *fep = netdev_priv(dev); 2390 struct phy_device *phydev = fep->phy_dev; 2391 2392 if (!phydev) 2393 return -ENODEV; 2394 2395 return genphy_restart_aneg(phydev); 2396 } 2397 2398 /* ITR clock source is enet system clock (clk_ahb). 2399 * TCTT unit is cycle_ns * 64 cycle 2400 * So, the ICTT value = X us / (cycle_ns * 64) 2401 */ 2402 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2403 { 2404 struct fec_enet_private *fep = netdev_priv(ndev); 2405 2406 return us * (fep->itr_clk_rate / 64000) / 1000; 2407 } 2408 2409 /* Set threshold for interrupt coalescing */ 2410 static void fec_enet_itr_coal_set(struct net_device *ndev) 2411 { 2412 struct fec_enet_private *fep = netdev_priv(ndev); 2413 int rx_itr, tx_itr; 2414 2415 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 2416 return; 2417 2418 /* Must be greater than zero to avoid unpredictable behavior */ 2419 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2420 !fep->tx_time_itr || !fep->tx_pkts_itr) 2421 return; 2422 2423 /* Select enet system clock as Interrupt Coalescing 2424 * timer Clock Source 2425 */ 2426 rx_itr = FEC_ITR_CLK_SEL; 2427 tx_itr = FEC_ITR_CLK_SEL; 2428 2429 /* set ICFT and ICTT */ 2430 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2431 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2432 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2433 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2434 2435 rx_itr |= FEC_ITR_EN; 2436 tx_itr |= FEC_ITR_EN; 2437 2438 writel(tx_itr, fep->hwp + FEC_TXIC0); 2439 writel(rx_itr, fep->hwp + FEC_RXIC0); 2440 writel(tx_itr, fep->hwp + FEC_TXIC1); 2441 writel(rx_itr, fep->hwp + FEC_RXIC1); 2442 writel(tx_itr, fep->hwp + FEC_TXIC2); 2443 writel(rx_itr, fep->hwp + FEC_RXIC2); 2444 } 2445 2446 static int 2447 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2448 { 2449 struct fec_enet_private *fep = netdev_priv(ndev); 2450 2451 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 2452 return -EOPNOTSUPP; 2453 2454 ec->rx_coalesce_usecs = fep->rx_time_itr; 2455 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2456 2457 ec->tx_coalesce_usecs = fep->tx_time_itr; 2458 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2459 2460 return 0; 2461 } 2462 2463 static int 2464 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2465 { 2466 struct fec_enet_private *fep = netdev_priv(ndev); 2467 unsigned int cycle; 2468 2469 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 2470 return -EOPNOTSUPP; 2471 2472 if (ec->rx_max_coalesced_frames > 255) { 2473 pr_err("Rx coalesced frames exceed hardware limiation"); 2474 return -EINVAL; 2475 } 2476 2477 if (ec->tx_max_coalesced_frames > 255) { 2478 pr_err("Tx coalesced frame exceed hardware limiation"); 2479 return -EINVAL; 2480 } 2481 2482 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); 2483 if (cycle > 0xFFFF) { 2484 pr_err("Rx coalesed usec exceeed hardware limiation"); 2485 return -EINVAL; 2486 } 2487 2488 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); 2489 if (cycle > 0xFFFF) { 2490 pr_err("Rx coalesed usec exceeed hardware limiation"); 2491 return -EINVAL; 2492 } 2493 2494 fep->rx_time_itr = ec->rx_coalesce_usecs; 2495 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2496 2497 fep->tx_time_itr = ec->tx_coalesce_usecs; 2498 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2499 2500 fec_enet_itr_coal_set(ndev); 2501 2502 return 0; 2503 } 2504 2505 static void fec_enet_itr_coal_init(struct net_device *ndev) 2506 { 2507 struct ethtool_coalesce ec; 2508 2509 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2510 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2511 2512 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2513 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2514 2515 fec_enet_set_coalesce(ndev, &ec); 2516 } 2517 2518 static int fec_enet_get_tunable(struct net_device *netdev, 2519 const struct ethtool_tunable *tuna, 2520 void *data) 2521 { 2522 struct fec_enet_private *fep = netdev_priv(netdev); 2523 int ret = 0; 2524 2525 switch (tuna->id) { 2526 case ETHTOOL_RX_COPYBREAK: 2527 *(u32 *)data = fep->rx_copybreak; 2528 break; 2529 default: 2530 ret = -EINVAL; 2531 break; 2532 } 2533 2534 return ret; 2535 } 2536 2537 static int fec_enet_set_tunable(struct net_device *netdev, 2538 const struct ethtool_tunable *tuna, 2539 const void *data) 2540 { 2541 struct fec_enet_private *fep = netdev_priv(netdev); 2542 int ret = 0; 2543 2544 switch (tuna->id) { 2545 case ETHTOOL_RX_COPYBREAK: 2546 fep->rx_copybreak = *(u32 *)data; 2547 break; 2548 default: 2549 ret = -EINVAL; 2550 break; 2551 } 2552 2553 return ret; 2554 } 2555 2556 static void 2557 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2558 { 2559 struct fec_enet_private *fep = netdev_priv(ndev); 2560 2561 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2562 wol->supported = WAKE_MAGIC; 2563 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2564 } else { 2565 wol->supported = wol->wolopts = 0; 2566 } 2567 } 2568 2569 static int 2570 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2571 { 2572 struct fec_enet_private *fep = netdev_priv(ndev); 2573 2574 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2575 return -EINVAL; 2576 2577 if (wol->wolopts & ~WAKE_MAGIC) 2578 return -EINVAL; 2579 2580 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2581 if (device_may_wakeup(&ndev->dev)) { 2582 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2583 if (fep->irq[0] > 0) 2584 enable_irq_wake(fep->irq[0]); 2585 } else { 2586 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2587 if (fep->irq[0] > 0) 2588 disable_irq_wake(fep->irq[0]); 2589 } 2590 2591 return 0; 2592 } 2593 2594 static const struct ethtool_ops fec_enet_ethtool_ops = { 2595 .get_settings = fec_enet_get_settings, 2596 .set_settings = fec_enet_set_settings, 2597 .get_drvinfo = fec_enet_get_drvinfo, 2598 .get_regs_len = fec_enet_get_regs_len, 2599 .get_regs = fec_enet_get_regs, 2600 .nway_reset = fec_enet_nway_reset, 2601 .get_link = ethtool_op_get_link, 2602 .get_coalesce = fec_enet_get_coalesce, 2603 .set_coalesce = fec_enet_set_coalesce, 2604 #ifndef CONFIG_M5272 2605 .get_pauseparam = fec_enet_get_pauseparam, 2606 .set_pauseparam = fec_enet_set_pauseparam, 2607 .get_strings = fec_enet_get_strings, 2608 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2609 .get_sset_count = fec_enet_get_sset_count, 2610 #endif 2611 .get_ts_info = fec_enet_get_ts_info, 2612 .get_tunable = fec_enet_get_tunable, 2613 .set_tunable = fec_enet_set_tunable, 2614 .get_wol = fec_enet_get_wol, 2615 .set_wol = fec_enet_set_wol, 2616 }; 2617 2618 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2619 { 2620 struct fec_enet_private *fep = netdev_priv(ndev); 2621 struct phy_device *phydev = fep->phy_dev; 2622 2623 if (!netif_running(ndev)) 2624 return -EINVAL; 2625 2626 if (!phydev) 2627 return -ENODEV; 2628 2629 if (fep->bufdesc_ex) { 2630 if (cmd == SIOCSHWTSTAMP) 2631 return fec_ptp_set(ndev, rq); 2632 if (cmd == SIOCGHWTSTAMP) 2633 return fec_ptp_get(ndev, rq); 2634 } 2635 2636 return phy_mii_ioctl(phydev, rq, cmd); 2637 } 2638 2639 static void fec_enet_free_buffers(struct net_device *ndev) 2640 { 2641 struct fec_enet_private *fep = netdev_priv(ndev); 2642 unsigned int i; 2643 struct sk_buff *skb; 2644 struct bufdesc *bdp; 2645 struct fec_enet_priv_tx_q *txq; 2646 struct fec_enet_priv_rx_q *rxq; 2647 unsigned int q; 2648 2649 for (q = 0; q < fep->num_rx_queues; q++) { 2650 rxq = fep->rx_queue[q]; 2651 bdp = rxq->rx_bd_base; 2652 for (i = 0; i < rxq->rx_ring_size; i++) { 2653 skb = rxq->rx_skbuff[i]; 2654 rxq->rx_skbuff[i] = NULL; 2655 if (skb) { 2656 dma_unmap_single(&fep->pdev->dev, 2657 bdp->cbd_bufaddr, 2658 FEC_ENET_RX_FRSIZE - fep->rx_align, 2659 DMA_FROM_DEVICE); 2660 dev_kfree_skb(skb); 2661 } 2662 bdp = fec_enet_get_nextdesc(bdp, fep, q); 2663 } 2664 } 2665 2666 for (q = 0; q < fep->num_tx_queues; q++) { 2667 txq = fep->tx_queue[q]; 2668 bdp = txq->tx_bd_base; 2669 for (i = 0; i < txq->tx_ring_size; i++) { 2670 kfree(txq->tx_bounce[i]); 2671 txq->tx_bounce[i] = NULL; 2672 skb = txq->tx_skbuff[i]; 2673 txq->tx_skbuff[i] = NULL; 2674 dev_kfree_skb(skb); 2675 } 2676 } 2677 } 2678 2679 static void fec_enet_free_queue(struct net_device *ndev) 2680 { 2681 struct fec_enet_private *fep = netdev_priv(ndev); 2682 int i; 2683 struct fec_enet_priv_tx_q *txq; 2684 2685 for (i = 0; i < fep->num_tx_queues; i++) 2686 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2687 txq = fep->tx_queue[i]; 2688 dma_free_coherent(NULL, 2689 txq->tx_ring_size * TSO_HEADER_SIZE, 2690 txq->tso_hdrs, 2691 txq->tso_hdrs_dma); 2692 } 2693 2694 for (i = 0; i < fep->num_rx_queues; i++) 2695 kfree(fep->rx_queue[i]); 2696 for (i = 0; i < fep->num_tx_queues; i++) 2697 kfree(fep->tx_queue[i]); 2698 } 2699 2700 static int fec_enet_alloc_queue(struct net_device *ndev) 2701 { 2702 struct fec_enet_private *fep = netdev_priv(ndev); 2703 int i; 2704 int ret = 0; 2705 struct fec_enet_priv_tx_q *txq; 2706 2707 for (i = 0; i < fep->num_tx_queues; i++) { 2708 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 2709 if (!txq) { 2710 ret = -ENOMEM; 2711 goto alloc_failed; 2712 } 2713 2714 fep->tx_queue[i] = txq; 2715 txq->tx_ring_size = TX_RING_SIZE; 2716 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size; 2717 2718 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2719 txq->tx_wake_threshold = 2720 (txq->tx_ring_size - txq->tx_stop_threshold) / 2; 2721 2722 txq->tso_hdrs = dma_alloc_coherent(NULL, 2723 txq->tx_ring_size * TSO_HEADER_SIZE, 2724 &txq->tso_hdrs_dma, 2725 GFP_KERNEL); 2726 if (!txq->tso_hdrs) { 2727 ret = -ENOMEM; 2728 goto alloc_failed; 2729 } 2730 } 2731 2732 for (i = 0; i < fep->num_rx_queues; i++) { 2733 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 2734 GFP_KERNEL); 2735 if (!fep->rx_queue[i]) { 2736 ret = -ENOMEM; 2737 goto alloc_failed; 2738 } 2739 2740 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE; 2741 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size; 2742 } 2743 return ret; 2744 2745 alloc_failed: 2746 fec_enet_free_queue(ndev); 2747 return ret; 2748 } 2749 2750 static int 2751 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 2752 { 2753 struct fec_enet_private *fep = netdev_priv(ndev); 2754 unsigned int i; 2755 struct sk_buff *skb; 2756 struct bufdesc *bdp; 2757 struct fec_enet_priv_rx_q *rxq; 2758 2759 rxq = fep->rx_queue[queue]; 2760 bdp = rxq->rx_bd_base; 2761 for (i = 0; i < rxq->rx_ring_size; i++) { 2762 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2763 if (!skb) 2764 goto err_alloc; 2765 2766 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 2767 dev_kfree_skb(skb); 2768 goto err_alloc; 2769 } 2770 2771 rxq->rx_skbuff[i] = skb; 2772 bdp->cbd_sc = BD_ENET_RX_EMPTY; 2773 2774 if (fep->bufdesc_ex) { 2775 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2776 ebdp->cbd_esc = BD_ENET_RX_INT; 2777 } 2778 2779 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 2780 } 2781 2782 /* Set the last buffer to wrap. */ 2783 bdp = fec_enet_get_prevdesc(bdp, fep, queue); 2784 bdp->cbd_sc |= BD_SC_WRAP; 2785 return 0; 2786 2787 err_alloc: 2788 fec_enet_free_buffers(ndev); 2789 return -ENOMEM; 2790 } 2791 2792 static int 2793 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 2794 { 2795 struct fec_enet_private *fep = netdev_priv(ndev); 2796 unsigned int i; 2797 struct bufdesc *bdp; 2798 struct fec_enet_priv_tx_q *txq; 2799 2800 txq = fep->tx_queue[queue]; 2801 bdp = txq->tx_bd_base; 2802 for (i = 0; i < txq->tx_ring_size; i++) { 2803 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2804 if (!txq->tx_bounce[i]) 2805 goto err_alloc; 2806 2807 bdp->cbd_sc = 0; 2808 bdp->cbd_bufaddr = 0; 2809 2810 if (fep->bufdesc_ex) { 2811 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2812 ebdp->cbd_esc = BD_ENET_TX_INT; 2813 } 2814 2815 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 2816 } 2817 2818 /* Set the last buffer to wrap. */ 2819 bdp = fec_enet_get_prevdesc(bdp, fep, queue); 2820 bdp->cbd_sc |= BD_SC_WRAP; 2821 2822 return 0; 2823 2824 err_alloc: 2825 fec_enet_free_buffers(ndev); 2826 return -ENOMEM; 2827 } 2828 2829 static int fec_enet_alloc_buffers(struct net_device *ndev) 2830 { 2831 struct fec_enet_private *fep = netdev_priv(ndev); 2832 unsigned int i; 2833 2834 for (i = 0; i < fep->num_rx_queues; i++) 2835 if (fec_enet_alloc_rxq_buffers(ndev, i)) 2836 return -ENOMEM; 2837 2838 for (i = 0; i < fep->num_tx_queues; i++) 2839 if (fec_enet_alloc_txq_buffers(ndev, i)) 2840 return -ENOMEM; 2841 return 0; 2842 } 2843 2844 static int 2845 fec_enet_open(struct net_device *ndev) 2846 { 2847 struct fec_enet_private *fep = netdev_priv(ndev); 2848 int ret; 2849 2850 pinctrl_pm_select_default_state(&fep->pdev->dev); 2851 ret = fec_enet_clk_enable(ndev, true); 2852 if (ret) 2853 return ret; 2854 2855 /* I should reset the ring buffers here, but I don't yet know 2856 * a simple way to do that. 2857 */ 2858 2859 ret = fec_enet_alloc_buffers(ndev); 2860 if (ret) 2861 goto err_enet_alloc; 2862 2863 /* Init MAC prior to mii bus probe */ 2864 fec_restart(ndev); 2865 2866 /* Probe and connect to PHY when open the interface */ 2867 ret = fec_enet_mii_probe(ndev); 2868 if (ret) 2869 goto err_enet_mii_probe; 2870 2871 napi_enable(&fep->napi); 2872 phy_start(fep->phy_dev); 2873 netif_tx_start_all_queues(ndev); 2874 2875 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 2876 FEC_WOL_FLAG_ENABLE); 2877 2878 return 0; 2879 2880 err_enet_mii_probe: 2881 fec_enet_free_buffers(ndev); 2882 err_enet_alloc: 2883 fec_enet_clk_enable(ndev, false); 2884 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2885 return ret; 2886 } 2887 2888 static int 2889 fec_enet_close(struct net_device *ndev) 2890 { 2891 struct fec_enet_private *fep = netdev_priv(ndev); 2892 2893 phy_stop(fep->phy_dev); 2894 2895 if (netif_device_present(ndev)) { 2896 napi_disable(&fep->napi); 2897 netif_tx_disable(ndev); 2898 fec_stop(ndev); 2899 } 2900 2901 phy_disconnect(fep->phy_dev); 2902 fep->phy_dev = NULL; 2903 2904 fec_enet_clk_enable(ndev, false); 2905 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2906 fec_enet_free_buffers(ndev); 2907 2908 return 0; 2909 } 2910 2911 /* Set or clear the multicast filter for this adaptor. 2912 * Skeleton taken from sunlance driver. 2913 * The CPM Ethernet implementation allows Multicast as well as individual 2914 * MAC address filtering. Some of the drivers check to make sure it is 2915 * a group multicast address, and discard those that are not. I guess I 2916 * will do the same for now, but just remove the test if you want 2917 * individual filtering as well (do the upper net layers want or support 2918 * this kind of feature?). 2919 */ 2920 2921 #define HASH_BITS 6 /* #bits in hash */ 2922 #define CRC32_POLY 0xEDB88320 2923 2924 static void set_multicast_list(struct net_device *ndev) 2925 { 2926 struct fec_enet_private *fep = netdev_priv(ndev); 2927 struct netdev_hw_addr *ha; 2928 unsigned int i, bit, data, crc, tmp; 2929 unsigned char hash; 2930 2931 if (ndev->flags & IFF_PROMISC) { 2932 tmp = readl(fep->hwp + FEC_R_CNTRL); 2933 tmp |= 0x8; 2934 writel(tmp, fep->hwp + FEC_R_CNTRL); 2935 return; 2936 } 2937 2938 tmp = readl(fep->hwp + FEC_R_CNTRL); 2939 tmp &= ~0x8; 2940 writel(tmp, fep->hwp + FEC_R_CNTRL); 2941 2942 if (ndev->flags & IFF_ALLMULTI) { 2943 /* Catch all multicast addresses, so set the 2944 * filter to all 1's 2945 */ 2946 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2947 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2948 2949 return; 2950 } 2951 2952 /* Clear filter and add the addresses in hash register 2953 */ 2954 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2955 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2956 2957 netdev_for_each_mc_addr(ha, ndev) { 2958 /* calculate crc32 value of mac address */ 2959 crc = 0xffffffff; 2960 2961 for (i = 0; i < ndev->addr_len; i++) { 2962 data = ha->addr[i]; 2963 for (bit = 0; bit < 8; bit++, data >>= 1) { 2964 crc = (crc >> 1) ^ 2965 (((crc ^ data) & 1) ? CRC32_POLY : 0); 2966 } 2967 } 2968 2969 /* only upper 6 bits (HASH_BITS) are used 2970 * which point to specific bit in he hash registers 2971 */ 2972 hash = (crc >> (32 - HASH_BITS)) & 0x3f; 2973 2974 if (hash > 31) { 2975 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2976 tmp |= 1 << (hash - 32); 2977 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2978 } else { 2979 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2980 tmp |= 1 << hash; 2981 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2982 } 2983 } 2984 } 2985 2986 /* Set a MAC change in hardware. */ 2987 static int 2988 fec_set_mac_address(struct net_device *ndev, void *p) 2989 { 2990 struct fec_enet_private *fep = netdev_priv(ndev); 2991 struct sockaddr *addr = p; 2992 2993 if (addr) { 2994 if (!is_valid_ether_addr(addr->sa_data)) 2995 return -EADDRNOTAVAIL; 2996 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 2997 } 2998 2999 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3000 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3001 fep->hwp + FEC_ADDR_LOW); 3002 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3003 fep->hwp + FEC_ADDR_HIGH); 3004 return 0; 3005 } 3006 3007 #ifdef CONFIG_NET_POLL_CONTROLLER 3008 /** 3009 * fec_poll_controller - FEC Poll controller function 3010 * @dev: The FEC network adapter 3011 * 3012 * Polled functionality used by netconsole and others in non interrupt mode 3013 * 3014 */ 3015 static void fec_poll_controller(struct net_device *dev) 3016 { 3017 int i; 3018 struct fec_enet_private *fep = netdev_priv(dev); 3019 3020 for (i = 0; i < FEC_IRQ_NUM; i++) { 3021 if (fep->irq[i] > 0) { 3022 disable_irq(fep->irq[i]); 3023 fec_enet_interrupt(fep->irq[i], dev); 3024 enable_irq(fep->irq[i]); 3025 } 3026 } 3027 } 3028 #endif 3029 3030 #define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM 3031 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3032 netdev_features_t features) 3033 { 3034 struct fec_enet_private *fep = netdev_priv(netdev); 3035 netdev_features_t changed = features ^ netdev->features; 3036 3037 netdev->features = features; 3038 3039 /* Receive checksum has been changed */ 3040 if (changed & NETIF_F_RXCSUM) { 3041 if (features & NETIF_F_RXCSUM) 3042 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3043 else 3044 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3045 } 3046 } 3047 3048 static int fec_set_features(struct net_device *netdev, 3049 netdev_features_t features) 3050 { 3051 struct fec_enet_private *fep = netdev_priv(netdev); 3052 netdev_features_t changed = features ^ netdev->features; 3053 3054 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) { 3055 napi_disable(&fep->napi); 3056 netif_tx_lock_bh(netdev); 3057 fec_stop(netdev); 3058 fec_enet_set_netdev_features(netdev, features); 3059 fec_restart(netdev); 3060 netif_tx_wake_all_queues(netdev); 3061 netif_tx_unlock_bh(netdev); 3062 napi_enable(&fep->napi); 3063 } else { 3064 fec_enet_set_netdev_features(netdev, features); 3065 } 3066 3067 return 0; 3068 } 3069 3070 static const struct net_device_ops fec_netdev_ops = { 3071 .ndo_open = fec_enet_open, 3072 .ndo_stop = fec_enet_close, 3073 .ndo_start_xmit = fec_enet_start_xmit, 3074 .ndo_set_rx_mode = set_multicast_list, 3075 .ndo_change_mtu = eth_change_mtu, 3076 .ndo_validate_addr = eth_validate_addr, 3077 .ndo_tx_timeout = fec_timeout, 3078 .ndo_set_mac_address = fec_set_mac_address, 3079 .ndo_do_ioctl = fec_enet_ioctl, 3080 #ifdef CONFIG_NET_POLL_CONTROLLER 3081 .ndo_poll_controller = fec_poll_controller, 3082 #endif 3083 .ndo_set_features = fec_set_features, 3084 }; 3085 3086 /* 3087 * XXX: We need to clean up on failure exits here. 3088 * 3089 */ 3090 static int fec_enet_init(struct net_device *ndev) 3091 { 3092 struct fec_enet_private *fep = netdev_priv(ndev); 3093 struct fec_enet_priv_tx_q *txq; 3094 struct fec_enet_priv_rx_q *rxq; 3095 struct bufdesc *cbd_base; 3096 dma_addr_t bd_dma; 3097 int bd_size; 3098 unsigned int i; 3099 3100 #if defined(CONFIG_ARM) 3101 fep->rx_align = 0xf; 3102 fep->tx_align = 0xf; 3103 #else 3104 fep->rx_align = 0x3; 3105 fep->tx_align = 0x3; 3106 #endif 3107 3108 fec_enet_alloc_queue(ndev); 3109 3110 if (fep->bufdesc_ex) 3111 fep->bufdesc_size = sizeof(struct bufdesc_ex); 3112 else 3113 fep->bufdesc_size = sizeof(struct bufdesc); 3114 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * 3115 fep->bufdesc_size; 3116 3117 /* Allocate memory for buffer descriptors. */ 3118 cbd_base = dma_alloc_coherent(NULL, bd_size, &bd_dma, 3119 GFP_KERNEL); 3120 if (!cbd_base) { 3121 return -ENOMEM; 3122 } 3123 3124 memset(cbd_base, 0, bd_size); 3125 3126 /* Get the Ethernet address */ 3127 fec_get_mac(ndev); 3128 /* make sure MAC we just acquired is programmed into the hw */ 3129 fec_set_mac_address(ndev, NULL); 3130 3131 /* Set receive and transmit descriptor base. */ 3132 for (i = 0; i < fep->num_rx_queues; i++) { 3133 rxq = fep->rx_queue[i]; 3134 rxq->index = i; 3135 rxq->rx_bd_base = (struct bufdesc *)cbd_base; 3136 rxq->bd_dma = bd_dma; 3137 if (fep->bufdesc_ex) { 3138 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size; 3139 cbd_base = (struct bufdesc *) 3140 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size); 3141 } else { 3142 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size; 3143 cbd_base += rxq->rx_ring_size; 3144 } 3145 } 3146 3147 for (i = 0; i < fep->num_tx_queues; i++) { 3148 txq = fep->tx_queue[i]; 3149 txq->index = i; 3150 txq->tx_bd_base = (struct bufdesc *)cbd_base; 3151 txq->bd_dma = bd_dma; 3152 if (fep->bufdesc_ex) { 3153 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size; 3154 cbd_base = (struct bufdesc *) 3155 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size); 3156 } else { 3157 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size; 3158 cbd_base += txq->tx_ring_size; 3159 } 3160 } 3161 3162 3163 /* The FEC Ethernet specific entries in the device structure */ 3164 ndev->watchdog_timeo = TX_TIMEOUT; 3165 ndev->netdev_ops = &fec_netdev_ops; 3166 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3167 3168 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3169 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3170 3171 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3172 /* enable hw VLAN support */ 3173 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3174 3175 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3176 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3177 3178 /* enable hw accelerator */ 3179 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3180 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3181 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3182 } 3183 3184 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 3185 fep->tx_align = 0; 3186 fep->rx_align = 0x3f; 3187 } 3188 3189 ndev->hw_features = ndev->features; 3190 3191 fec_restart(ndev); 3192 3193 return 0; 3194 } 3195 3196 #ifdef CONFIG_OF 3197 static void fec_reset_phy(struct platform_device *pdev) 3198 { 3199 int err, phy_reset; 3200 int msec = 1; 3201 struct device_node *np = pdev->dev.of_node; 3202 3203 if (!np) 3204 return; 3205 3206 of_property_read_u32(np, "phy-reset-duration", &msec); 3207 /* A sane reset duration should not be longer than 1s */ 3208 if (msec > 1000) 3209 msec = 1; 3210 3211 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3212 if (!gpio_is_valid(phy_reset)) 3213 return; 3214 3215 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3216 GPIOF_OUT_INIT_LOW, "phy-reset"); 3217 if (err) { 3218 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3219 return; 3220 } 3221 msleep(msec); 3222 gpio_set_value(phy_reset, 1); 3223 } 3224 #else /* CONFIG_OF */ 3225 static void fec_reset_phy(struct platform_device *pdev) 3226 { 3227 /* 3228 * In case of platform probe, the reset has been done 3229 * by machine code. 3230 */ 3231 } 3232 #endif /* CONFIG_OF */ 3233 3234 static void 3235 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3236 { 3237 struct device_node *np = pdev->dev.of_node; 3238 int err; 3239 3240 *num_tx = *num_rx = 1; 3241 3242 if (!np || !of_device_is_available(np)) 3243 return; 3244 3245 /* parse the num of tx and rx queues */ 3246 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3247 if (err) 3248 *num_tx = 1; 3249 3250 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3251 if (err) 3252 *num_rx = 1; 3253 3254 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3255 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3256 *num_tx); 3257 *num_tx = 1; 3258 return; 3259 } 3260 3261 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3262 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3263 *num_rx); 3264 *num_rx = 1; 3265 return; 3266 } 3267 3268 } 3269 3270 static int 3271 fec_probe(struct platform_device *pdev) 3272 { 3273 struct fec_enet_private *fep; 3274 struct fec_platform_data *pdata; 3275 struct net_device *ndev; 3276 int i, irq, ret = 0; 3277 struct resource *r; 3278 const struct of_device_id *of_id; 3279 static int dev_id; 3280 struct device_node *np = pdev->dev.of_node, *phy_node; 3281 int num_tx_qs; 3282 int num_rx_qs; 3283 3284 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3285 3286 /* Init network device */ 3287 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private), 3288 num_tx_qs, num_rx_qs); 3289 if (!ndev) 3290 return -ENOMEM; 3291 3292 SET_NETDEV_DEV(ndev, &pdev->dev); 3293 3294 /* setup board info structure */ 3295 fep = netdev_priv(ndev); 3296 3297 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3298 if (of_id) 3299 pdev->id_entry = of_id->data; 3300 fep->quirks = pdev->id_entry->driver_data; 3301 3302 fep->netdev = ndev; 3303 fep->num_rx_queues = num_rx_qs; 3304 fep->num_tx_queues = num_tx_qs; 3305 3306 #if !defined(CONFIG_M5272) 3307 /* default enable pause frame auto negotiation */ 3308 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3309 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3310 #endif 3311 3312 /* Select default pin state */ 3313 pinctrl_pm_select_default_state(&pdev->dev); 3314 3315 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3316 fep->hwp = devm_ioremap_resource(&pdev->dev, r); 3317 if (IS_ERR(fep->hwp)) { 3318 ret = PTR_ERR(fep->hwp); 3319 goto failed_ioremap; 3320 } 3321 3322 fep->pdev = pdev; 3323 fep->dev_id = dev_id++; 3324 3325 platform_set_drvdata(pdev, ndev); 3326 3327 if (of_get_property(np, "fsl,magic-packet", NULL)) 3328 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3329 3330 phy_node = of_parse_phandle(np, "phy-handle", 0); 3331 if (!phy_node && of_phy_is_fixed_link(np)) { 3332 ret = of_phy_register_fixed_link(np); 3333 if (ret < 0) { 3334 dev_err(&pdev->dev, 3335 "broken fixed-link specification\n"); 3336 goto failed_phy; 3337 } 3338 phy_node = of_node_get(np); 3339 } 3340 fep->phy_node = phy_node; 3341 3342 ret = of_get_phy_mode(pdev->dev.of_node); 3343 if (ret < 0) { 3344 pdata = dev_get_platdata(&pdev->dev); 3345 if (pdata) 3346 fep->phy_interface = pdata->phy; 3347 else 3348 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3349 } else { 3350 fep->phy_interface = ret; 3351 } 3352 3353 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3354 if (IS_ERR(fep->clk_ipg)) { 3355 ret = PTR_ERR(fep->clk_ipg); 3356 goto failed_clk; 3357 } 3358 3359 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3360 if (IS_ERR(fep->clk_ahb)) { 3361 ret = PTR_ERR(fep->clk_ahb); 3362 goto failed_clk; 3363 } 3364 3365 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3366 3367 /* enet_out is optional, depends on board */ 3368 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3369 if (IS_ERR(fep->clk_enet_out)) 3370 fep->clk_enet_out = NULL; 3371 3372 fep->ptp_clk_on = false; 3373 mutex_init(&fep->ptp_clk_mutex); 3374 3375 /* clk_ref is optional, depends on board */ 3376 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3377 if (IS_ERR(fep->clk_ref)) 3378 fep->clk_ref = NULL; 3379 3380 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3381 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3382 if (IS_ERR(fep->clk_ptp)) { 3383 fep->clk_ptp = NULL; 3384 fep->bufdesc_ex = false; 3385 } 3386 3387 ret = fec_enet_clk_enable(ndev, true); 3388 if (ret) 3389 goto failed_clk; 3390 3391 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); 3392 if (!IS_ERR(fep->reg_phy)) { 3393 ret = regulator_enable(fep->reg_phy); 3394 if (ret) { 3395 dev_err(&pdev->dev, 3396 "Failed to enable phy regulator: %d\n", ret); 3397 goto failed_regulator; 3398 } 3399 } else { 3400 fep->reg_phy = NULL; 3401 } 3402 3403 fec_reset_phy(pdev); 3404 3405 if (fep->bufdesc_ex) 3406 fec_ptp_init(pdev); 3407 3408 ret = fec_enet_init(ndev); 3409 if (ret) 3410 goto failed_init; 3411 3412 for (i = 0; i < FEC_IRQ_NUM; i++) { 3413 irq = platform_get_irq(pdev, i); 3414 if (irq < 0) { 3415 if (i) 3416 break; 3417 ret = irq; 3418 goto failed_irq; 3419 } 3420 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3421 0, pdev->name, ndev); 3422 if (ret) 3423 goto failed_irq; 3424 3425 fep->irq[i] = irq; 3426 } 3427 3428 init_completion(&fep->mdio_done); 3429 ret = fec_enet_mii_init(pdev); 3430 if (ret) 3431 goto failed_mii_init; 3432 3433 /* Carrier starts down, phylib will bring it up */ 3434 netif_carrier_off(ndev); 3435 fec_enet_clk_enable(ndev, false); 3436 pinctrl_pm_select_sleep_state(&pdev->dev); 3437 3438 ret = register_netdev(ndev); 3439 if (ret) 3440 goto failed_register; 3441 3442 device_init_wakeup(&ndev->dev, fep->wol_flag & 3443 FEC_WOL_HAS_MAGIC_PACKET); 3444 3445 if (fep->bufdesc_ex && fep->ptp_clock) 3446 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3447 3448 fep->rx_copybreak = COPYBREAK_DEFAULT; 3449 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3450 return 0; 3451 3452 failed_register: 3453 fec_enet_mii_remove(fep); 3454 failed_mii_init: 3455 failed_irq: 3456 failed_init: 3457 if (fep->reg_phy) 3458 regulator_disable(fep->reg_phy); 3459 failed_regulator: 3460 fec_enet_clk_enable(ndev, false); 3461 failed_clk: 3462 failed_phy: 3463 of_node_put(phy_node); 3464 failed_ioremap: 3465 free_netdev(ndev); 3466 3467 return ret; 3468 } 3469 3470 static int 3471 fec_drv_remove(struct platform_device *pdev) 3472 { 3473 struct net_device *ndev = platform_get_drvdata(pdev); 3474 struct fec_enet_private *fep = netdev_priv(ndev); 3475 3476 cancel_delayed_work_sync(&fep->time_keep); 3477 cancel_work_sync(&fep->tx_timeout_work); 3478 unregister_netdev(ndev); 3479 fec_enet_mii_remove(fep); 3480 if (fep->reg_phy) 3481 regulator_disable(fep->reg_phy); 3482 if (fep->ptp_clock) 3483 ptp_clock_unregister(fep->ptp_clock); 3484 of_node_put(fep->phy_node); 3485 free_netdev(ndev); 3486 3487 return 0; 3488 } 3489 3490 static int __maybe_unused fec_suspend(struct device *dev) 3491 { 3492 struct net_device *ndev = dev_get_drvdata(dev); 3493 struct fec_enet_private *fep = netdev_priv(ndev); 3494 3495 rtnl_lock(); 3496 if (netif_running(ndev)) { 3497 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 3498 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 3499 phy_stop(fep->phy_dev); 3500 napi_disable(&fep->napi); 3501 netif_tx_lock_bh(ndev); 3502 netif_device_detach(ndev); 3503 netif_tx_unlock_bh(ndev); 3504 fec_stop(ndev); 3505 fec_enet_clk_enable(ndev, false); 3506 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3507 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3508 } 3509 rtnl_unlock(); 3510 3511 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3512 regulator_disable(fep->reg_phy); 3513 3514 /* SOC supply clock to phy, when clock is disabled, phy link down 3515 * SOC control phy regulator, when regulator is disabled, phy link down 3516 */ 3517 if (fep->clk_enet_out || fep->reg_phy) 3518 fep->link = 0; 3519 3520 return 0; 3521 } 3522 3523 static int __maybe_unused fec_resume(struct device *dev) 3524 { 3525 struct net_device *ndev = dev_get_drvdata(dev); 3526 struct fec_enet_private *fep = netdev_priv(ndev); 3527 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 3528 int ret; 3529 int val; 3530 3531 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 3532 ret = regulator_enable(fep->reg_phy); 3533 if (ret) 3534 return ret; 3535 } 3536 3537 rtnl_lock(); 3538 if (netif_running(ndev)) { 3539 ret = fec_enet_clk_enable(ndev, true); 3540 if (ret) { 3541 rtnl_unlock(); 3542 goto failed_clk; 3543 } 3544 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 3545 if (pdata && pdata->sleep_mode_enable) 3546 pdata->sleep_mode_enable(false); 3547 val = readl(fep->hwp + FEC_ECNTRL); 3548 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 3549 writel(val, fep->hwp + FEC_ECNTRL); 3550 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 3551 } else { 3552 pinctrl_pm_select_default_state(&fep->pdev->dev); 3553 } 3554 fec_restart(ndev); 3555 netif_tx_lock_bh(ndev); 3556 netif_device_attach(ndev); 3557 netif_tx_unlock_bh(ndev); 3558 napi_enable(&fep->napi); 3559 phy_start(fep->phy_dev); 3560 } 3561 rtnl_unlock(); 3562 3563 return 0; 3564 3565 failed_clk: 3566 if (fep->reg_phy) 3567 regulator_disable(fep->reg_phy); 3568 return ret; 3569 } 3570 3571 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume); 3572 3573 static struct platform_driver fec_driver = { 3574 .driver = { 3575 .name = DRIVER_NAME, 3576 .pm = &fec_pm_ops, 3577 .of_match_table = fec_dt_ids, 3578 }, 3579 .id_table = fec_devtype, 3580 .probe = fec_probe, 3581 .remove = fec_drv_remove, 3582 }; 3583 3584 module_platform_driver(fec_driver); 3585 3586 MODULE_ALIAS("platform:"DRIVER_NAME); 3587 MODULE_LICENSE("GPL"); 3588