1 /* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 * 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/string.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/ptrace.h> 29 #include <linux/errno.h> 30 #include <linux/ioport.h> 31 #include <linux/slab.h> 32 #include <linux/interrupt.h> 33 #include <linux/delay.h> 34 #include <linux/netdevice.h> 35 #include <linux/etherdevice.h> 36 #include <linux/skbuff.h> 37 #include <linux/in.h> 38 #include <linux/ip.h> 39 #include <net/ip.h> 40 #include <net/tso.h> 41 #include <linux/tcp.h> 42 #include <linux/udp.h> 43 #include <linux/icmp.h> 44 #include <linux/spinlock.h> 45 #include <linux/workqueue.h> 46 #include <linux/bitops.h> 47 #include <linux/io.h> 48 #include <linux/irq.h> 49 #include <linux/clk.h> 50 #include <linux/platform_device.h> 51 #include <linux/phy.h> 52 #include <linux/fec.h> 53 #include <linux/of.h> 54 #include <linux/of_device.h> 55 #include <linux/of_gpio.h> 56 #include <linux/of_mdio.h> 57 #include <linux/of_net.h> 58 #include <linux/regulator/consumer.h> 59 #include <linux/if_vlan.h> 60 #include <linux/pinctrl/consumer.h> 61 #include <linux/prefetch.h> 62 63 #include <asm/cacheflush.h> 64 65 #include "fec.h" 66 67 static void set_multicast_list(struct net_device *ndev); 68 static void fec_enet_itr_coal_init(struct net_device *ndev); 69 70 #define DRIVER_NAME "fec" 71 72 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0)) 73 74 /* Pause frame feild and FIFO threshold */ 75 #define FEC_ENET_FCE (1 << 5) 76 #define FEC_ENET_RSEM_V 0x84 77 #define FEC_ENET_RSFL_V 16 78 #define FEC_ENET_RAEM_V 0x8 79 #define FEC_ENET_RAFL_V 0x8 80 #define FEC_ENET_OPD_V 0xFFF0 81 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 82 83 static struct platform_device_id fec_devtype[] = { 84 { 85 /* keep it for coldfire */ 86 .name = DRIVER_NAME, 87 .driver_data = 0, 88 }, { 89 .name = "imx25-fec", 90 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_HAS_RACC, 91 }, { 92 .name = "imx27-fec", 93 .driver_data = FEC_QUIRK_HAS_RACC, 94 }, { 95 .name = "imx28-fec", 96 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 97 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC, 98 }, { 99 .name = "imx6q-fec", 100 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 101 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 102 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 103 FEC_QUIRK_HAS_RACC, 104 }, { 105 .name = "mvf600-fec", 106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 107 }, { 108 .name = "imx6sx-fec", 109 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 110 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 111 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 112 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 113 FEC_QUIRK_HAS_RACC, 114 }, { 115 /* sentinel */ 116 } 117 }; 118 MODULE_DEVICE_TABLE(platform, fec_devtype); 119 120 enum imx_fec_type { 121 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 122 IMX27_FEC, /* runs on i.mx27/35/51 */ 123 IMX28_FEC, 124 IMX6Q_FEC, 125 MVF600_FEC, 126 IMX6SX_FEC, 127 }; 128 129 static const struct of_device_id fec_dt_ids[] = { 130 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 131 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 132 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 133 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 134 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 135 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 136 { /* sentinel */ } 137 }; 138 MODULE_DEVICE_TABLE(of, fec_dt_ids); 139 140 static unsigned char macaddr[ETH_ALEN]; 141 module_param_array(macaddr, byte, NULL, 0); 142 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 143 144 #if defined(CONFIG_M5272) 145 /* 146 * Some hardware gets it MAC address out of local flash memory. 147 * if this is non-zero then assume it is the address to get MAC from. 148 */ 149 #if defined(CONFIG_NETtel) 150 #define FEC_FLASHMAC 0xf0006006 151 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 152 #define FEC_FLASHMAC 0xf0006000 153 #elif defined(CONFIG_CANCam) 154 #define FEC_FLASHMAC 0xf0020000 155 #elif defined (CONFIG_M5272C3) 156 #define FEC_FLASHMAC (0xffe04000 + 4) 157 #elif defined(CONFIG_MOD5272) 158 #define FEC_FLASHMAC 0xffc0406b 159 #else 160 #define FEC_FLASHMAC 0 161 #endif 162 #endif /* CONFIG_M5272 */ 163 164 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 165 */ 166 #define PKT_MAXBUF_SIZE 1522 167 #define PKT_MINBUF_SIZE 64 168 #define PKT_MAXBLR_SIZE 1536 169 170 /* FEC receive acceleration */ 171 #define FEC_RACC_IPDIS (1 << 1) 172 #define FEC_RACC_PRODIS (1 << 2) 173 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 174 175 /* 176 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 177 * size bits. Other FEC hardware does not, so we need to take that into 178 * account when setting it. 179 */ 180 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 181 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 182 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 183 #else 184 #define OPT_FRAME_SIZE 0 185 #endif 186 187 /* FEC MII MMFR bits definition */ 188 #define FEC_MMFR_ST (1 << 30) 189 #define FEC_MMFR_OP_READ (2 << 28) 190 #define FEC_MMFR_OP_WRITE (1 << 28) 191 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 192 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 193 #define FEC_MMFR_TA (2 << 16) 194 #define FEC_MMFR_DATA(v) (v & 0xffff) 195 /* FEC ECR bits definition */ 196 #define FEC_ECR_MAGICEN (1 << 2) 197 #define FEC_ECR_SLEEP (1 << 3) 198 199 #define FEC_MII_TIMEOUT 30000 /* us */ 200 201 /* Transmitter timeout */ 202 #define TX_TIMEOUT (2 * HZ) 203 204 #define FEC_PAUSE_FLAG_AUTONEG 0x1 205 #define FEC_PAUSE_FLAG_ENABLE 0x2 206 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 207 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 208 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 209 210 #define COPYBREAK_DEFAULT 256 211 212 #define TSO_HEADER_SIZE 128 213 /* Max number of allowed TCP segments for software TSO */ 214 #define FEC_MAX_TSO_SEGS 100 215 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 216 217 #define IS_TSO_HEADER(txq, addr) \ 218 ((addr >= txq->tso_hdrs_dma) && \ 219 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE)) 220 221 static int mii_cnt; 222 223 static inline 224 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 225 struct fec_enet_private *fep, 226 int queue_id) 227 { 228 struct bufdesc *new_bd = bdp + 1; 229 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1; 230 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id]; 231 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id]; 232 struct bufdesc_ex *ex_base; 233 struct bufdesc *base; 234 int ring_size; 235 236 if (bdp >= txq->tx_bd_base) { 237 base = txq->tx_bd_base; 238 ring_size = txq->tx_ring_size; 239 ex_base = (struct bufdesc_ex *)txq->tx_bd_base; 240 } else { 241 base = rxq->rx_bd_base; 242 ring_size = rxq->rx_ring_size; 243 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base; 244 } 245 246 if (fep->bufdesc_ex) 247 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ? 248 ex_base : ex_new_bd); 249 else 250 return (new_bd >= (base + ring_size)) ? 251 base : new_bd; 252 } 253 254 static inline 255 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 256 struct fec_enet_private *fep, 257 int queue_id) 258 { 259 struct bufdesc *new_bd = bdp - 1; 260 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1; 261 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id]; 262 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id]; 263 struct bufdesc_ex *ex_base; 264 struct bufdesc *base; 265 int ring_size; 266 267 if (bdp >= txq->tx_bd_base) { 268 base = txq->tx_bd_base; 269 ring_size = txq->tx_ring_size; 270 ex_base = (struct bufdesc_ex *)txq->tx_bd_base; 271 } else { 272 base = rxq->rx_bd_base; 273 ring_size = rxq->rx_ring_size; 274 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base; 275 } 276 277 if (fep->bufdesc_ex) 278 return (struct bufdesc *)((ex_new_bd < ex_base) ? 279 (ex_new_bd + ring_size) : ex_new_bd); 280 else 281 return (new_bd < base) ? (new_bd + ring_size) : new_bd; 282 } 283 284 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp, 285 struct fec_enet_private *fep) 286 { 287 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size; 288 } 289 290 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep, 291 struct fec_enet_priv_tx_q *txq) 292 { 293 int entries; 294 295 entries = ((const char *)txq->dirty_tx - 296 (const char *)txq->cur_tx) / fep->bufdesc_size - 1; 297 298 return entries > 0 ? entries : entries + txq->tx_ring_size; 299 } 300 301 static void swap_buffer(void *bufaddr, int len) 302 { 303 int i; 304 unsigned int *buf = bufaddr; 305 306 for (i = 0; i < len; i += 4, buf++) 307 swab32s(buf); 308 } 309 310 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 311 { 312 int i; 313 unsigned int *src = src_buf; 314 unsigned int *dst = dst_buf; 315 316 for (i = 0; i < len; i += 4, src++, dst++) 317 *dst = swab32p(src); 318 } 319 320 static void fec_dump(struct net_device *ndev) 321 { 322 struct fec_enet_private *fep = netdev_priv(ndev); 323 struct bufdesc *bdp; 324 struct fec_enet_priv_tx_q *txq; 325 int index = 0; 326 327 netdev_info(ndev, "TX ring dump\n"); 328 pr_info("Nr SC addr len SKB\n"); 329 330 txq = fep->tx_queue[0]; 331 bdp = txq->tx_bd_base; 332 333 do { 334 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n", 335 index, 336 bdp == txq->cur_tx ? 'S' : ' ', 337 bdp == txq->dirty_tx ? 'H' : ' ', 338 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen, 339 txq->tx_skbuff[index]); 340 bdp = fec_enet_get_nextdesc(bdp, fep, 0); 341 index++; 342 } while (bdp != txq->tx_bd_base); 343 } 344 345 static inline bool is_ipv4_pkt(struct sk_buff *skb) 346 { 347 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 348 } 349 350 static int 351 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 352 { 353 /* Only run for packets requiring a checksum. */ 354 if (skb->ip_summed != CHECKSUM_PARTIAL) 355 return 0; 356 357 if (unlikely(skb_cow_head(skb, 0))) 358 return -1; 359 360 if (is_ipv4_pkt(skb)) 361 ip_hdr(skb)->check = 0; 362 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 363 364 return 0; 365 } 366 367 static struct bufdesc * 368 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 369 struct sk_buff *skb, 370 struct net_device *ndev) 371 { 372 struct fec_enet_private *fep = netdev_priv(ndev); 373 struct bufdesc *bdp = txq->cur_tx; 374 struct bufdesc_ex *ebdp; 375 int nr_frags = skb_shinfo(skb)->nr_frags; 376 unsigned short queue = skb_get_queue_mapping(skb); 377 int frag, frag_len; 378 unsigned short status; 379 unsigned int estatus = 0; 380 skb_frag_t *this_frag; 381 unsigned int index; 382 void *bufaddr; 383 dma_addr_t addr; 384 int i; 385 386 for (frag = 0; frag < nr_frags; frag++) { 387 this_frag = &skb_shinfo(skb)->frags[frag]; 388 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 389 ebdp = (struct bufdesc_ex *)bdp; 390 391 status = bdp->cbd_sc; 392 status &= ~BD_ENET_TX_STATS; 393 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 394 frag_len = skb_shinfo(skb)->frags[frag].size; 395 396 /* Handle the last BD specially */ 397 if (frag == nr_frags - 1) { 398 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 399 if (fep->bufdesc_ex) { 400 estatus |= BD_ENET_TX_INT; 401 if (unlikely(skb_shinfo(skb)->tx_flags & 402 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 403 estatus |= BD_ENET_TX_TS; 404 } 405 } 406 407 if (fep->bufdesc_ex) { 408 if (fep->quirks & FEC_QUIRK_HAS_AVB) 409 estatus |= FEC_TX_BD_FTYPE(queue); 410 if (skb->ip_summed == CHECKSUM_PARTIAL) 411 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 412 ebdp->cbd_bdu = 0; 413 ebdp->cbd_esc = estatus; 414 } 415 416 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset; 417 418 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep); 419 if (((unsigned long) bufaddr) & fep->tx_align || 420 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 421 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 422 bufaddr = txq->tx_bounce[index]; 423 424 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 425 swap_buffer(bufaddr, frag_len); 426 } 427 428 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 429 DMA_TO_DEVICE); 430 if (dma_mapping_error(&fep->pdev->dev, addr)) { 431 dev_kfree_skb_any(skb); 432 if (net_ratelimit()) 433 netdev_err(ndev, "Tx DMA memory map failed\n"); 434 goto dma_mapping_error; 435 } 436 437 bdp->cbd_bufaddr = addr; 438 bdp->cbd_datlen = frag_len; 439 bdp->cbd_sc = status; 440 } 441 442 return bdp; 443 dma_mapping_error: 444 bdp = txq->cur_tx; 445 for (i = 0; i < frag; i++) { 446 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 447 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 448 bdp->cbd_datlen, DMA_TO_DEVICE); 449 } 450 return ERR_PTR(-ENOMEM); 451 } 452 453 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 454 struct sk_buff *skb, struct net_device *ndev) 455 { 456 struct fec_enet_private *fep = netdev_priv(ndev); 457 int nr_frags = skb_shinfo(skb)->nr_frags; 458 struct bufdesc *bdp, *last_bdp; 459 void *bufaddr; 460 dma_addr_t addr; 461 unsigned short status; 462 unsigned short buflen; 463 unsigned short queue; 464 unsigned int estatus = 0; 465 unsigned int index; 466 int entries_free; 467 468 entries_free = fec_enet_get_free_txdesc_num(fep, txq); 469 if (entries_free < MAX_SKB_FRAGS + 1) { 470 dev_kfree_skb_any(skb); 471 if (net_ratelimit()) 472 netdev_err(ndev, "NOT enough BD for SG!\n"); 473 return NETDEV_TX_OK; 474 } 475 476 /* Protocol checksum off-load for TCP and UDP. */ 477 if (fec_enet_clear_csum(skb, ndev)) { 478 dev_kfree_skb_any(skb); 479 return NETDEV_TX_OK; 480 } 481 482 /* Fill in a Tx ring entry */ 483 bdp = txq->cur_tx; 484 last_bdp = bdp; 485 status = bdp->cbd_sc; 486 status &= ~BD_ENET_TX_STATS; 487 488 /* Set buffer length and buffer pointer */ 489 bufaddr = skb->data; 490 buflen = skb_headlen(skb); 491 492 queue = skb_get_queue_mapping(skb); 493 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep); 494 if (((unsigned long) bufaddr) & fep->tx_align || 495 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 496 memcpy(txq->tx_bounce[index], skb->data, buflen); 497 bufaddr = txq->tx_bounce[index]; 498 499 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 500 swap_buffer(bufaddr, buflen); 501 } 502 503 /* Push the data cache so the CPM does not get stale memory data. */ 504 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 505 if (dma_mapping_error(&fep->pdev->dev, addr)) { 506 dev_kfree_skb_any(skb); 507 if (net_ratelimit()) 508 netdev_err(ndev, "Tx DMA memory map failed\n"); 509 return NETDEV_TX_OK; 510 } 511 512 if (nr_frags) { 513 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 514 if (IS_ERR(last_bdp)) 515 return NETDEV_TX_OK; 516 } else { 517 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 518 if (fep->bufdesc_ex) { 519 estatus = BD_ENET_TX_INT; 520 if (unlikely(skb_shinfo(skb)->tx_flags & 521 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 522 estatus |= BD_ENET_TX_TS; 523 } 524 } 525 526 if (fep->bufdesc_ex) { 527 528 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 529 530 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 531 fep->hwts_tx_en)) 532 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 533 534 if (fep->quirks & FEC_QUIRK_HAS_AVB) 535 estatus |= FEC_TX_BD_FTYPE(queue); 536 537 if (skb->ip_summed == CHECKSUM_PARTIAL) 538 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 539 540 ebdp->cbd_bdu = 0; 541 ebdp->cbd_esc = estatus; 542 } 543 544 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep); 545 /* Save skb pointer */ 546 txq->tx_skbuff[index] = skb; 547 548 bdp->cbd_datlen = buflen; 549 bdp->cbd_bufaddr = addr; 550 551 /* Send it on its way. Tell FEC it's ready, interrupt when done, 552 * it's the last BD of the frame, and to put the CRC on the end. 553 */ 554 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 555 bdp->cbd_sc = status; 556 557 /* If this was the last BD in the ring, start at the beginning again. */ 558 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue); 559 560 skb_tx_timestamp(skb); 561 562 /* Make sure the update to bdp and tx_skbuff are performed before 563 * cur_tx. 564 */ 565 wmb(); 566 txq->cur_tx = bdp; 567 568 /* Trigger transmission start */ 569 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue)); 570 571 return 0; 572 } 573 574 static int 575 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 576 struct net_device *ndev, 577 struct bufdesc *bdp, int index, char *data, 578 int size, bool last_tcp, bool is_last) 579 { 580 struct fec_enet_private *fep = netdev_priv(ndev); 581 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 582 unsigned short queue = skb_get_queue_mapping(skb); 583 unsigned short status; 584 unsigned int estatus = 0; 585 dma_addr_t addr; 586 587 status = bdp->cbd_sc; 588 status &= ~BD_ENET_TX_STATS; 589 590 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 591 592 if (((unsigned long) data) & fep->tx_align || 593 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 594 memcpy(txq->tx_bounce[index], data, size); 595 data = txq->tx_bounce[index]; 596 597 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 598 swap_buffer(data, size); 599 } 600 601 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 602 if (dma_mapping_error(&fep->pdev->dev, addr)) { 603 dev_kfree_skb_any(skb); 604 if (net_ratelimit()) 605 netdev_err(ndev, "Tx DMA memory map failed\n"); 606 return NETDEV_TX_BUSY; 607 } 608 609 bdp->cbd_datlen = size; 610 bdp->cbd_bufaddr = addr; 611 612 if (fep->bufdesc_ex) { 613 if (fep->quirks & FEC_QUIRK_HAS_AVB) 614 estatus |= FEC_TX_BD_FTYPE(queue); 615 if (skb->ip_summed == CHECKSUM_PARTIAL) 616 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 617 ebdp->cbd_bdu = 0; 618 ebdp->cbd_esc = estatus; 619 } 620 621 /* Handle the last BD specially */ 622 if (last_tcp) 623 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 624 if (is_last) { 625 status |= BD_ENET_TX_INTR; 626 if (fep->bufdesc_ex) 627 ebdp->cbd_esc |= BD_ENET_TX_INT; 628 } 629 630 bdp->cbd_sc = status; 631 632 return 0; 633 } 634 635 static int 636 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 637 struct sk_buff *skb, struct net_device *ndev, 638 struct bufdesc *bdp, int index) 639 { 640 struct fec_enet_private *fep = netdev_priv(ndev); 641 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 642 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 643 unsigned short queue = skb_get_queue_mapping(skb); 644 void *bufaddr; 645 unsigned long dmabuf; 646 unsigned short status; 647 unsigned int estatus = 0; 648 649 status = bdp->cbd_sc; 650 status &= ~BD_ENET_TX_STATS; 651 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 652 653 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 654 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 655 if (((unsigned long)bufaddr) & fep->tx_align || 656 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 657 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 658 bufaddr = txq->tx_bounce[index]; 659 660 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 661 swap_buffer(bufaddr, hdr_len); 662 663 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 664 hdr_len, DMA_TO_DEVICE); 665 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 666 dev_kfree_skb_any(skb); 667 if (net_ratelimit()) 668 netdev_err(ndev, "Tx DMA memory map failed\n"); 669 return NETDEV_TX_BUSY; 670 } 671 } 672 673 bdp->cbd_bufaddr = dmabuf; 674 bdp->cbd_datlen = hdr_len; 675 676 if (fep->bufdesc_ex) { 677 if (fep->quirks & FEC_QUIRK_HAS_AVB) 678 estatus |= FEC_TX_BD_FTYPE(queue); 679 if (skb->ip_summed == CHECKSUM_PARTIAL) 680 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 681 ebdp->cbd_bdu = 0; 682 ebdp->cbd_esc = estatus; 683 } 684 685 bdp->cbd_sc = status; 686 687 return 0; 688 } 689 690 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 691 struct sk_buff *skb, 692 struct net_device *ndev) 693 { 694 struct fec_enet_private *fep = netdev_priv(ndev); 695 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 696 int total_len, data_left; 697 struct bufdesc *bdp = txq->cur_tx; 698 unsigned short queue = skb_get_queue_mapping(skb); 699 struct tso_t tso; 700 unsigned int index = 0; 701 int ret; 702 703 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) { 704 dev_kfree_skb_any(skb); 705 if (net_ratelimit()) 706 netdev_err(ndev, "NOT enough BD for TSO!\n"); 707 return NETDEV_TX_OK; 708 } 709 710 /* Protocol checksum off-load for TCP and UDP. */ 711 if (fec_enet_clear_csum(skb, ndev)) { 712 dev_kfree_skb_any(skb); 713 return NETDEV_TX_OK; 714 } 715 716 /* Initialize the TSO handler, and prepare the first payload */ 717 tso_start(skb, &tso); 718 719 total_len = skb->len - hdr_len; 720 while (total_len > 0) { 721 char *hdr; 722 723 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep); 724 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 725 total_len -= data_left; 726 727 /* prepare packet headers: MAC + IP + TCP */ 728 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 729 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 730 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 731 if (ret) 732 goto err_release; 733 734 while (data_left > 0) { 735 int size; 736 737 size = min_t(int, tso.size, data_left); 738 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 739 index = fec_enet_get_bd_index(txq->tx_bd_base, 740 bdp, fep); 741 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 742 bdp, index, 743 tso.data, size, 744 size == data_left, 745 total_len == 0); 746 if (ret) 747 goto err_release; 748 749 data_left -= size; 750 tso_build_data(skb, &tso, size); 751 } 752 753 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 754 } 755 756 /* Save skb pointer */ 757 txq->tx_skbuff[index] = skb; 758 759 skb_tx_timestamp(skb); 760 txq->cur_tx = bdp; 761 762 /* Trigger transmission start */ 763 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 764 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) || 765 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) || 766 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) || 767 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue))) 768 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue)); 769 770 return 0; 771 772 err_release: 773 /* TODO: Release all used data descriptors for TSO */ 774 return ret; 775 } 776 777 static netdev_tx_t 778 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 779 { 780 struct fec_enet_private *fep = netdev_priv(ndev); 781 int entries_free; 782 unsigned short queue; 783 struct fec_enet_priv_tx_q *txq; 784 struct netdev_queue *nq; 785 int ret; 786 787 queue = skb_get_queue_mapping(skb); 788 txq = fep->tx_queue[queue]; 789 nq = netdev_get_tx_queue(ndev, queue); 790 791 if (skb_is_gso(skb)) 792 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 793 else 794 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 795 if (ret) 796 return ret; 797 798 entries_free = fec_enet_get_free_txdesc_num(fep, txq); 799 if (entries_free <= txq->tx_stop_threshold) 800 netif_tx_stop_queue(nq); 801 802 return NETDEV_TX_OK; 803 } 804 805 /* Init RX & TX buffer descriptors 806 */ 807 static void fec_enet_bd_init(struct net_device *dev) 808 { 809 struct fec_enet_private *fep = netdev_priv(dev); 810 struct fec_enet_priv_tx_q *txq; 811 struct fec_enet_priv_rx_q *rxq; 812 struct bufdesc *bdp; 813 unsigned int i; 814 unsigned int q; 815 816 for (q = 0; q < fep->num_rx_queues; q++) { 817 /* Initialize the receive buffer descriptors. */ 818 rxq = fep->rx_queue[q]; 819 bdp = rxq->rx_bd_base; 820 821 for (i = 0; i < rxq->rx_ring_size; i++) { 822 823 /* Initialize the BD for every fragment in the page. */ 824 if (bdp->cbd_bufaddr) 825 bdp->cbd_sc = BD_ENET_RX_EMPTY; 826 else 827 bdp->cbd_sc = 0; 828 bdp = fec_enet_get_nextdesc(bdp, fep, q); 829 } 830 831 /* Set the last buffer to wrap */ 832 bdp = fec_enet_get_prevdesc(bdp, fep, q); 833 bdp->cbd_sc |= BD_SC_WRAP; 834 835 rxq->cur_rx = rxq->rx_bd_base; 836 } 837 838 for (q = 0; q < fep->num_tx_queues; q++) { 839 /* ...and the same for transmit */ 840 txq = fep->tx_queue[q]; 841 bdp = txq->tx_bd_base; 842 txq->cur_tx = bdp; 843 844 for (i = 0; i < txq->tx_ring_size; i++) { 845 /* Initialize the BD for every fragment in the page. */ 846 bdp->cbd_sc = 0; 847 if (txq->tx_skbuff[i]) { 848 dev_kfree_skb_any(txq->tx_skbuff[i]); 849 txq->tx_skbuff[i] = NULL; 850 } 851 bdp->cbd_bufaddr = 0; 852 bdp = fec_enet_get_nextdesc(bdp, fep, q); 853 } 854 855 /* Set the last buffer to wrap */ 856 bdp = fec_enet_get_prevdesc(bdp, fep, q); 857 bdp->cbd_sc |= BD_SC_WRAP; 858 txq->dirty_tx = bdp; 859 } 860 } 861 862 static void fec_enet_active_rxring(struct net_device *ndev) 863 { 864 struct fec_enet_private *fep = netdev_priv(ndev); 865 int i; 866 867 for (i = 0; i < fep->num_rx_queues; i++) 868 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i)); 869 } 870 871 static void fec_enet_enable_ring(struct net_device *ndev) 872 { 873 struct fec_enet_private *fep = netdev_priv(ndev); 874 struct fec_enet_priv_tx_q *txq; 875 struct fec_enet_priv_rx_q *rxq; 876 int i; 877 878 for (i = 0; i < fep->num_rx_queues; i++) { 879 rxq = fep->rx_queue[i]; 880 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i)); 881 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 882 883 /* enable DMA1/2 */ 884 if (i) 885 writel(RCMR_MATCHEN | RCMR_CMP(i), 886 fep->hwp + FEC_RCMR(i)); 887 } 888 889 for (i = 0; i < fep->num_tx_queues; i++) { 890 txq = fep->tx_queue[i]; 891 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i)); 892 893 /* enable DMA1/2 */ 894 if (i) 895 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 896 fep->hwp + FEC_DMA_CFG(i)); 897 } 898 } 899 900 static void fec_enet_reset_skb(struct net_device *ndev) 901 { 902 struct fec_enet_private *fep = netdev_priv(ndev); 903 struct fec_enet_priv_tx_q *txq; 904 int i, j; 905 906 for (i = 0; i < fep->num_tx_queues; i++) { 907 txq = fep->tx_queue[i]; 908 909 for (j = 0; j < txq->tx_ring_size; j++) { 910 if (txq->tx_skbuff[j]) { 911 dev_kfree_skb_any(txq->tx_skbuff[j]); 912 txq->tx_skbuff[j] = NULL; 913 } 914 } 915 } 916 } 917 918 /* 919 * This function is called to start or restart the FEC during a link 920 * change, transmit timeout, or to reconfigure the FEC. The network 921 * packet processing for this device must be stopped before this call. 922 */ 923 static void 924 fec_restart(struct net_device *ndev) 925 { 926 struct fec_enet_private *fep = netdev_priv(ndev); 927 u32 val; 928 u32 temp_mac[2]; 929 u32 rcntl = OPT_FRAME_SIZE | 0x04; 930 u32 ecntl = 0x2; /* ETHEREN */ 931 932 /* Whack a reset. We should wait for this. 933 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 934 * instead of reset MAC itself. 935 */ 936 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 937 writel(0, fep->hwp + FEC_ECNTRL); 938 } else { 939 writel(1, fep->hwp + FEC_ECNTRL); 940 udelay(10); 941 } 942 943 /* 944 * enet-mac reset will reset mac address registers too, 945 * so need to reconfigure it. 946 */ 947 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 948 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 949 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); 950 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); 951 } 952 953 /* Clear any outstanding interrupt. */ 954 writel(0xffffffff, fep->hwp + FEC_IEVENT); 955 956 fec_enet_bd_init(ndev); 957 958 fec_enet_enable_ring(ndev); 959 960 /* Reset tx SKB buffers. */ 961 fec_enet_reset_skb(ndev); 962 963 /* Enable MII mode */ 964 if (fep->full_duplex == DUPLEX_FULL) { 965 /* FD enable */ 966 writel(0x04, fep->hwp + FEC_X_CNTRL); 967 } else { 968 /* No Rcv on Xmit */ 969 rcntl |= 0x02; 970 writel(0x0, fep->hwp + FEC_X_CNTRL); 971 } 972 973 /* Set MII speed */ 974 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 975 976 #if !defined(CONFIG_M5272) 977 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 978 /* set RX checksum */ 979 val = readl(fep->hwp + FEC_RACC); 980 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 981 val |= FEC_RACC_OPTIONS; 982 else 983 val &= ~FEC_RACC_OPTIONS; 984 writel(val, fep->hwp + FEC_RACC); 985 } 986 #endif 987 988 /* 989 * The phy interface and speed need to get configured 990 * differently on enet-mac. 991 */ 992 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 993 /* Enable flow control and length check */ 994 rcntl |= 0x40000000 | 0x00000020; 995 996 /* RGMII, RMII or MII */ 997 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 998 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 999 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1000 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1001 rcntl |= (1 << 6); 1002 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1003 rcntl |= (1 << 8); 1004 else 1005 rcntl &= ~(1 << 8); 1006 1007 /* 1G, 100M or 10M */ 1008 if (fep->phy_dev) { 1009 if (fep->phy_dev->speed == SPEED_1000) 1010 ecntl |= (1 << 5); 1011 else if (fep->phy_dev->speed == SPEED_100) 1012 rcntl &= ~(1 << 9); 1013 else 1014 rcntl |= (1 << 9); 1015 } 1016 } else { 1017 #ifdef FEC_MIIGSK_ENR 1018 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1019 u32 cfgr; 1020 /* disable the gasket and wait */ 1021 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1022 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1023 udelay(1); 1024 1025 /* 1026 * configure the gasket: 1027 * RMII, 50 MHz, no loopback, no echo 1028 * MII, 25 MHz, no loopback, no echo 1029 */ 1030 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1031 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1032 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) 1033 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1034 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1035 1036 /* re-enable the gasket */ 1037 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1038 } 1039 #endif 1040 } 1041 1042 #if !defined(CONFIG_M5272) 1043 /* enable pause frame*/ 1044 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1045 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1046 fep->phy_dev && fep->phy_dev->pause)) { 1047 rcntl |= FEC_ENET_FCE; 1048 1049 /* set FIFO threshold parameter to reduce overrun */ 1050 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1051 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1052 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1053 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1054 1055 /* OPD */ 1056 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1057 } else { 1058 rcntl &= ~FEC_ENET_FCE; 1059 } 1060 #endif /* !defined(CONFIG_M5272) */ 1061 1062 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1063 1064 /* Setup multicast filter. */ 1065 set_multicast_list(ndev); 1066 #ifndef CONFIG_M5272 1067 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1068 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1069 #endif 1070 1071 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1072 /* enable ENET endian swap */ 1073 ecntl |= (1 << 8); 1074 /* enable ENET store and forward mode */ 1075 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1076 } 1077 1078 if (fep->bufdesc_ex) 1079 ecntl |= (1 << 4); 1080 1081 #ifndef CONFIG_M5272 1082 /* Enable the MIB statistic event counters */ 1083 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1084 #endif 1085 1086 /* And last, enable the transmit and receive processing */ 1087 writel(ecntl, fep->hwp + FEC_ECNTRL); 1088 fec_enet_active_rxring(ndev); 1089 1090 if (fep->bufdesc_ex) 1091 fec_ptp_start_cyclecounter(ndev); 1092 1093 /* Enable interrupts we wish to service */ 1094 if (fep->link) 1095 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1096 else 1097 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); 1098 1099 /* Init the interrupt coalescing */ 1100 fec_enet_itr_coal_init(ndev); 1101 1102 } 1103 1104 static void 1105 fec_stop(struct net_device *ndev) 1106 { 1107 struct fec_enet_private *fep = netdev_priv(ndev); 1108 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1109 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1110 u32 val; 1111 1112 /* We cannot expect a graceful transmit stop without link !!! */ 1113 if (fep->link) { 1114 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1115 udelay(10); 1116 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1117 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1118 } 1119 1120 /* Whack a reset. We should wait for this. 1121 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1122 * instead of reset MAC itself. 1123 */ 1124 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1125 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 1126 writel(0, fep->hwp + FEC_ECNTRL); 1127 } else { 1128 writel(1, fep->hwp + FEC_ECNTRL); 1129 udelay(10); 1130 } 1131 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1132 } else { 1133 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1134 val = readl(fep->hwp + FEC_ECNTRL); 1135 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1136 writel(val, fep->hwp + FEC_ECNTRL); 1137 1138 if (pdata && pdata->sleep_mode_enable) 1139 pdata->sleep_mode_enable(true); 1140 } 1141 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1142 1143 /* We have to keep ENET enabled to have MII interrupt stay working */ 1144 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1145 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1146 writel(2, fep->hwp + FEC_ECNTRL); 1147 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1148 } 1149 } 1150 1151 1152 static void 1153 fec_timeout(struct net_device *ndev) 1154 { 1155 struct fec_enet_private *fep = netdev_priv(ndev); 1156 1157 fec_dump(ndev); 1158 1159 ndev->stats.tx_errors++; 1160 1161 schedule_work(&fep->tx_timeout_work); 1162 } 1163 1164 static void fec_enet_timeout_work(struct work_struct *work) 1165 { 1166 struct fec_enet_private *fep = 1167 container_of(work, struct fec_enet_private, tx_timeout_work); 1168 struct net_device *ndev = fep->netdev; 1169 1170 rtnl_lock(); 1171 if (netif_device_present(ndev) || netif_running(ndev)) { 1172 napi_disable(&fep->napi); 1173 netif_tx_lock_bh(ndev); 1174 fec_restart(ndev); 1175 netif_wake_queue(ndev); 1176 netif_tx_unlock_bh(ndev); 1177 napi_enable(&fep->napi); 1178 } 1179 rtnl_unlock(); 1180 } 1181 1182 static void 1183 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1184 struct skb_shared_hwtstamps *hwtstamps) 1185 { 1186 unsigned long flags; 1187 u64 ns; 1188 1189 spin_lock_irqsave(&fep->tmreg_lock, flags); 1190 ns = timecounter_cyc2time(&fep->tc, ts); 1191 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1192 1193 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1194 hwtstamps->hwtstamp = ns_to_ktime(ns); 1195 } 1196 1197 static void 1198 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1199 { 1200 struct fec_enet_private *fep; 1201 struct bufdesc *bdp; 1202 unsigned short status; 1203 struct sk_buff *skb; 1204 struct fec_enet_priv_tx_q *txq; 1205 struct netdev_queue *nq; 1206 int index = 0; 1207 int entries_free; 1208 1209 fep = netdev_priv(ndev); 1210 1211 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1212 1213 txq = fep->tx_queue[queue_id]; 1214 /* get next bdp of dirty_tx */ 1215 nq = netdev_get_tx_queue(ndev, queue_id); 1216 bdp = txq->dirty_tx; 1217 1218 /* get next bdp of dirty_tx */ 1219 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id); 1220 1221 while (bdp != READ_ONCE(txq->cur_tx)) { 1222 /* Order the load of cur_tx and cbd_sc */ 1223 rmb(); 1224 status = READ_ONCE(bdp->cbd_sc); 1225 if (status & BD_ENET_TX_READY) 1226 break; 1227 1228 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep); 1229 1230 skb = txq->tx_skbuff[index]; 1231 txq->tx_skbuff[index] = NULL; 1232 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr)) 1233 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 1234 bdp->cbd_datlen, DMA_TO_DEVICE); 1235 bdp->cbd_bufaddr = 0; 1236 if (!skb) { 1237 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id); 1238 continue; 1239 } 1240 1241 /* Check for errors. */ 1242 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1243 BD_ENET_TX_RL | BD_ENET_TX_UN | 1244 BD_ENET_TX_CSL)) { 1245 ndev->stats.tx_errors++; 1246 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1247 ndev->stats.tx_heartbeat_errors++; 1248 if (status & BD_ENET_TX_LC) /* Late collision */ 1249 ndev->stats.tx_window_errors++; 1250 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1251 ndev->stats.tx_aborted_errors++; 1252 if (status & BD_ENET_TX_UN) /* Underrun */ 1253 ndev->stats.tx_fifo_errors++; 1254 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1255 ndev->stats.tx_carrier_errors++; 1256 } else { 1257 ndev->stats.tx_packets++; 1258 ndev->stats.tx_bytes += skb->len; 1259 } 1260 1261 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 1262 fep->bufdesc_ex) { 1263 struct skb_shared_hwtstamps shhwtstamps; 1264 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1265 1266 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps); 1267 skb_tstamp_tx(skb, &shhwtstamps); 1268 } 1269 1270 /* Deferred means some collisions occurred during transmit, 1271 * but we eventually sent the packet OK. 1272 */ 1273 if (status & BD_ENET_TX_DEF) 1274 ndev->stats.collisions++; 1275 1276 /* Free the sk buffer associated with this last transmit */ 1277 dev_kfree_skb_any(skb); 1278 1279 /* Make sure the update to bdp and tx_skbuff are performed 1280 * before dirty_tx 1281 */ 1282 wmb(); 1283 txq->dirty_tx = bdp; 1284 1285 /* Update pointer to next buffer descriptor to be transmitted */ 1286 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id); 1287 1288 /* Since we have freed up a buffer, the ring is no longer full 1289 */ 1290 if (netif_queue_stopped(ndev)) { 1291 entries_free = fec_enet_get_free_txdesc_num(fep, txq); 1292 if (entries_free >= txq->tx_wake_threshold) 1293 netif_tx_wake_queue(nq); 1294 } 1295 } 1296 1297 /* ERR006538: Keep the transmitter going */ 1298 if (bdp != txq->cur_tx && 1299 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0) 1300 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id)); 1301 } 1302 1303 static void 1304 fec_enet_tx(struct net_device *ndev) 1305 { 1306 struct fec_enet_private *fep = netdev_priv(ndev); 1307 u16 queue_id; 1308 /* First process class A queue, then Class B and Best Effort queue */ 1309 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) { 1310 clear_bit(queue_id, &fep->work_tx); 1311 fec_enet_tx_queue(ndev, queue_id); 1312 } 1313 return; 1314 } 1315 1316 static int 1317 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1318 { 1319 struct fec_enet_private *fep = netdev_priv(ndev); 1320 int off; 1321 1322 off = ((unsigned long)skb->data) & fep->rx_align; 1323 if (off) 1324 skb_reserve(skb, fep->rx_align + 1 - off); 1325 1326 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, 1327 FEC_ENET_RX_FRSIZE - fep->rx_align, 1328 DMA_FROM_DEVICE); 1329 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) { 1330 if (net_ratelimit()) 1331 netdev_err(ndev, "Rx DMA memory map failed\n"); 1332 return -ENOMEM; 1333 } 1334 1335 return 0; 1336 } 1337 1338 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1339 struct bufdesc *bdp, u32 length, bool swap) 1340 { 1341 struct fec_enet_private *fep = netdev_priv(ndev); 1342 struct sk_buff *new_skb; 1343 1344 if (length > fep->rx_copybreak) 1345 return false; 1346 1347 new_skb = netdev_alloc_skb(ndev, length); 1348 if (!new_skb) 1349 return false; 1350 1351 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr, 1352 FEC_ENET_RX_FRSIZE - fep->rx_align, 1353 DMA_FROM_DEVICE); 1354 if (!swap) 1355 memcpy(new_skb->data, (*skb)->data, length); 1356 else 1357 swap_buffer2(new_skb->data, (*skb)->data, length); 1358 *skb = new_skb; 1359 1360 return true; 1361 } 1362 1363 /* During a receive, the cur_rx points to the current incoming buffer. 1364 * When we update through the ring, if the next incoming buffer has 1365 * not been given to the system, we just set the empty indicator, 1366 * effectively tossing the packet. 1367 */ 1368 static int 1369 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1370 { 1371 struct fec_enet_private *fep = netdev_priv(ndev); 1372 struct fec_enet_priv_rx_q *rxq; 1373 struct bufdesc *bdp; 1374 unsigned short status; 1375 struct sk_buff *skb_new = NULL; 1376 struct sk_buff *skb; 1377 ushort pkt_len; 1378 __u8 *data; 1379 int pkt_received = 0; 1380 struct bufdesc_ex *ebdp = NULL; 1381 bool vlan_packet_rcvd = false; 1382 u16 vlan_tag; 1383 int index = 0; 1384 bool is_copybreak; 1385 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1386 1387 #ifdef CONFIG_M532x 1388 flush_cache_all(); 1389 #endif 1390 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1391 rxq = fep->rx_queue[queue_id]; 1392 1393 /* First, grab all of the stats for the incoming packet. 1394 * These get messed up if we get called due to a busy condition. 1395 */ 1396 bdp = rxq->cur_rx; 1397 1398 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { 1399 1400 if (pkt_received >= budget) 1401 break; 1402 pkt_received++; 1403 1404 /* Since we have allocated space to hold a complete frame, 1405 * the last indicator should be set. 1406 */ 1407 if ((status & BD_ENET_RX_LAST) == 0) 1408 netdev_err(ndev, "rcv is not +last\n"); 1409 1410 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); 1411 1412 /* Check for errors. */ 1413 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1414 BD_ENET_RX_CR | BD_ENET_RX_OV)) { 1415 ndev->stats.rx_errors++; 1416 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { 1417 /* Frame too long or too short. */ 1418 ndev->stats.rx_length_errors++; 1419 } 1420 if (status & BD_ENET_RX_NO) /* Frame alignment */ 1421 ndev->stats.rx_frame_errors++; 1422 if (status & BD_ENET_RX_CR) /* CRC Error */ 1423 ndev->stats.rx_crc_errors++; 1424 if (status & BD_ENET_RX_OV) /* FIFO overrun */ 1425 ndev->stats.rx_fifo_errors++; 1426 } 1427 1428 /* Report late collisions as a frame error. 1429 * On this error, the BD is closed, but we don't know what we 1430 * have in the buffer. So, just drop this frame on the floor. 1431 */ 1432 if (status & BD_ENET_RX_CL) { 1433 ndev->stats.rx_errors++; 1434 ndev->stats.rx_frame_errors++; 1435 goto rx_processing_done; 1436 } 1437 1438 /* Process the incoming frame. */ 1439 ndev->stats.rx_packets++; 1440 pkt_len = bdp->cbd_datlen; 1441 ndev->stats.rx_bytes += pkt_len; 1442 1443 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep); 1444 skb = rxq->rx_skbuff[index]; 1445 1446 /* The packet length includes FCS, but we don't want to 1447 * include that when passing upstream as it messes up 1448 * bridging applications. 1449 */ 1450 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1451 need_swap); 1452 if (!is_copybreak) { 1453 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1454 if (unlikely(!skb_new)) { 1455 ndev->stats.rx_dropped++; 1456 goto rx_processing_done; 1457 } 1458 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 1459 FEC_ENET_RX_FRSIZE - fep->rx_align, 1460 DMA_FROM_DEVICE); 1461 } 1462 1463 prefetch(skb->data - NET_IP_ALIGN); 1464 skb_put(skb, pkt_len - 4); 1465 data = skb->data; 1466 if (!is_copybreak && need_swap) 1467 swap_buffer(data, pkt_len); 1468 1469 /* Extract the enhanced buffer descriptor */ 1470 ebdp = NULL; 1471 if (fep->bufdesc_ex) 1472 ebdp = (struct bufdesc_ex *)bdp; 1473 1474 /* If this is a VLAN packet remove the VLAN Tag */ 1475 vlan_packet_rcvd = false; 1476 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1477 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) { 1478 /* Push and remove the vlan tag */ 1479 struct vlan_hdr *vlan_header = 1480 (struct vlan_hdr *) (data + ETH_HLEN); 1481 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1482 1483 vlan_packet_rcvd = true; 1484 1485 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1486 skb_pull(skb, VLAN_HLEN); 1487 } 1488 1489 skb->protocol = eth_type_trans(skb, ndev); 1490 1491 /* Get receive timestamp from the skb */ 1492 if (fep->hwts_rx_en && fep->bufdesc_ex) 1493 fec_enet_hwtstamp(fep, ebdp->ts, 1494 skb_hwtstamps(skb)); 1495 1496 if (fep->bufdesc_ex && 1497 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1498 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) { 1499 /* don't check it */ 1500 skb->ip_summed = CHECKSUM_UNNECESSARY; 1501 } else { 1502 skb_checksum_none_assert(skb); 1503 } 1504 } 1505 1506 /* Handle received VLAN packets */ 1507 if (vlan_packet_rcvd) 1508 __vlan_hwaccel_put_tag(skb, 1509 htons(ETH_P_8021Q), 1510 vlan_tag); 1511 1512 napi_gro_receive(&fep->napi, skb); 1513 1514 if (is_copybreak) { 1515 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr, 1516 FEC_ENET_RX_FRSIZE - fep->rx_align, 1517 DMA_FROM_DEVICE); 1518 } else { 1519 rxq->rx_skbuff[index] = skb_new; 1520 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1521 } 1522 1523 rx_processing_done: 1524 /* Clear the status flags for this buffer */ 1525 status &= ~BD_ENET_RX_STATS; 1526 1527 /* Mark the buffer empty */ 1528 status |= BD_ENET_RX_EMPTY; 1529 bdp->cbd_sc = status; 1530 1531 if (fep->bufdesc_ex) { 1532 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1533 1534 ebdp->cbd_esc = BD_ENET_RX_INT; 1535 ebdp->cbd_prot = 0; 1536 ebdp->cbd_bdu = 0; 1537 } 1538 1539 /* Update BD pointer to next entry */ 1540 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id); 1541 1542 /* Doing this here will keep the FEC running while we process 1543 * incoming frames. On a heavily loaded network, we should be 1544 * able to keep up at the expense of system resources. 1545 */ 1546 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id)); 1547 } 1548 rxq->cur_rx = bdp; 1549 return pkt_received; 1550 } 1551 1552 static int 1553 fec_enet_rx(struct net_device *ndev, int budget) 1554 { 1555 int pkt_received = 0; 1556 u16 queue_id; 1557 struct fec_enet_private *fep = netdev_priv(ndev); 1558 1559 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) { 1560 clear_bit(queue_id, &fep->work_rx); 1561 pkt_received += fec_enet_rx_queue(ndev, 1562 budget - pkt_received, queue_id); 1563 } 1564 return pkt_received; 1565 } 1566 1567 static bool 1568 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events) 1569 { 1570 if (int_events == 0) 1571 return false; 1572 1573 if (int_events & FEC_ENET_RXF) 1574 fep->work_rx |= (1 << 2); 1575 if (int_events & FEC_ENET_RXF_1) 1576 fep->work_rx |= (1 << 0); 1577 if (int_events & FEC_ENET_RXF_2) 1578 fep->work_rx |= (1 << 1); 1579 1580 if (int_events & FEC_ENET_TXF) 1581 fep->work_tx |= (1 << 2); 1582 if (int_events & FEC_ENET_TXF_1) 1583 fep->work_tx |= (1 << 0); 1584 if (int_events & FEC_ENET_TXF_2) 1585 fep->work_tx |= (1 << 1); 1586 1587 return true; 1588 } 1589 1590 static irqreturn_t 1591 fec_enet_interrupt(int irq, void *dev_id) 1592 { 1593 struct net_device *ndev = dev_id; 1594 struct fec_enet_private *fep = netdev_priv(ndev); 1595 uint int_events; 1596 irqreturn_t ret = IRQ_NONE; 1597 1598 int_events = readl(fep->hwp + FEC_IEVENT); 1599 writel(int_events, fep->hwp + FEC_IEVENT); 1600 fec_enet_collect_events(fep, int_events); 1601 1602 if ((fep->work_tx || fep->work_rx) && fep->link) { 1603 ret = IRQ_HANDLED; 1604 1605 if (napi_schedule_prep(&fep->napi)) { 1606 /* Disable the NAPI interrupts */ 1607 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); 1608 __napi_schedule(&fep->napi); 1609 } 1610 } 1611 1612 if (int_events & FEC_ENET_MII) { 1613 ret = IRQ_HANDLED; 1614 complete(&fep->mdio_done); 1615 } 1616 1617 if (fep->ptp_clock) 1618 fec_ptp_check_pps_event(fep); 1619 1620 return ret; 1621 } 1622 1623 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1624 { 1625 struct net_device *ndev = napi->dev; 1626 struct fec_enet_private *fep = netdev_priv(ndev); 1627 int pkts; 1628 1629 pkts = fec_enet_rx(ndev, budget); 1630 1631 fec_enet_tx(ndev); 1632 1633 if (pkts < budget) { 1634 napi_complete(napi); 1635 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1636 } 1637 return pkts; 1638 } 1639 1640 /* ------------------------------------------------------------------------- */ 1641 static void fec_get_mac(struct net_device *ndev) 1642 { 1643 struct fec_enet_private *fep = netdev_priv(ndev); 1644 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1645 unsigned char *iap, tmpaddr[ETH_ALEN]; 1646 1647 /* 1648 * try to get mac address in following order: 1649 * 1650 * 1) module parameter via kernel command line in form 1651 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1652 */ 1653 iap = macaddr; 1654 1655 /* 1656 * 2) from device tree data 1657 */ 1658 if (!is_valid_ether_addr(iap)) { 1659 struct device_node *np = fep->pdev->dev.of_node; 1660 if (np) { 1661 const char *mac = of_get_mac_address(np); 1662 if (mac) 1663 iap = (unsigned char *) mac; 1664 } 1665 } 1666 1667 /* 1668 * 3) from flash or fuse (via platform data) 1669 */ 1670 if (!is_valid_ether_addr(iap)) { 1671 #ifdef CONFIG_M5272 1672 if (FEC_FLASHMAC) 1673 iap = (unsigned char *)FEC_FLASHMAC; 1674 #else 1675 if (pdata) 1676 iap = (unsigned char *)&pdata->mac; 1677 #endif 1678 } 1679 1680 /* 1681 * 4) FEC mac registers set by bootloader 1682 */ 1683 if (!is_valid_ether_addr(iap)) { 1684 *((__be32 *) &tmpaddr[0]) = 1685 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1686 *((__be16 *) &tmpaddr[4]) = 1687 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1688 iap = &tmpaddr[0]; 1689 } 1690 1691 /* 1692 * 5) random mac address 1693 */ 1694 if (!is_valid_ether_addr(iap)) { 1695 /* Report it and use a random ethernet address instead */ 1696 netdev_err(ndev, "Invalid MAC address: %pM\n", iap); 1697 eth_hw_addr_random(ndev); 1698 netdev_info(ndev, "Using random MAC address: %pM\n", 1699 ndev->dev_addr); 1700 return; 1701 } 1702 1703 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1704 1705 /* Adjust MAC if using macaddr */ 1706 if (iap == macaddr) 1707 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1708 } 1709 1710 /* ------------------------------------------------------------------------- */ 1711 1712 /* 1713 * Phy section 1714 */ 1715 static void fec_enet_adjust_link(struct net_device *ndev) 1716 { 1717 struct fec_enet_private *fep = netdev_priv(ndev); 1718 struct phy_device *phy_dev = fep->phy_dev; 1719 int status_change = 0; 1720 1721 /* Prevent a state halted on mii error */ 1722 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 1723 phy_dev->state = PHY_RESUMING; 1724 return; 1725 } 1726 1727 /* 1728 * If the netdev is down, or is going down, we're not interested 1729 * in link state events, so just mark our idea of the link as down 1730 * and ignore the event. 1731 */ 1732 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1733 fep->link = 0; 1734 } else if (phy_dev->link) { 1735 if (!fep->link) { 1736 fep->link = phy_dev->link; 1737 status_change = 1; 1738 } 1739 1740 if (fep->full_duplex != phy_dev->duplex) { 1741 fep->full_duplex = phy_dev->duplex; 1742 status_change = 1; 1743 } 1744 1745 if (phy_dev->speed != fep->speed) { 1746 fep->speed = phy_dev->speed; 1747 status_change = 1; 1748 } 1749 1750 /* if any of the above changed restart the FEC */ 1751 if (status_change) { 1752 napi_disable(&fep->napi); 1753 netif_tx_lock_bh(ndev); 1754 fec_restart(ndev); 1755 netif_wake_queue(ndev); 1756 netif_tx_unlock_bh(ndev); 1757 napi_enable(&fep->napi); 1758 } 1759 } else { 1760 if (fep->link) { 1761 napi_disable(&fep->napi); 1762 netif_tx_lock_bh(ndev); 1763 fec_stop(ndev); 1764 netif_tx_unlock_bh(ndev); 1765 napi_enable(&fep->napi); 1766 fep->link = phy_dev->link; 1767 status_change = 1; 1768 } 1769 } 1770 1771 if (status_change) 1772 phy_print_status(phy_dev); 1773 } 1774 1775 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1776 { 1777 struct fec_enet_private *fep = bus->priv; 1778 struct device *dev = &fep->pdev->dev; 1779 unsigned long time_left; 1780 int ret = 0; 1781 1782 ret = pm_runtime_get_sync(dev); 1783 if (ret < 0) 1784 return ret; 1785 1786 fep->mii_timeout = 0; 1787 reinit_completion(&fep->mdio_done); 1788 1789 /* start a read op */ 1790 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 1791 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1792 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1793 1794 /* wait for end of transfer */ 1795 time_left = wait_for_completion_timeout(&fep->mdio_done, 1796 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1797 if (time_left == 0) { 1798 fep->mii_timeout = 1; 1799 netdev_err(fep->netdev, "MDIO read timeout\n"); 1800 ret = -ETIMEDOUT; 1801 goto out; 1802 } 1803 1804 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1805 1806 out: 1807 pm_runtime_mark_last_busy(dev); 1808 pm_runtime_put_autosuspend(dev); 1809 1810 return ret; 1811 } 1812 1813 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1814 u16 value) 1815 { 1816 struct fec_enet_private *fep = bus->priv; 1817 struct device *dev = &fep->pdev->dev; 1818 unsigned long time_left; 1819 int ret = 0; 1820 1821 ret = pm_runtime_get_sync(dev); 1822 if (ret < 0) 1823 return ret; 1824 1825 fep->mii_timeout = 0; 1826 reinit_completion(&fep->mdio_done); 1827 1828 /* start a write op */ 1829 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 1830 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1831 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1832 fep->hwp + FEC_MII_DATA); 1833 1834 /* wait for end of transfer */ 1835 time_left = wait_for_completion_timeout(&fep->mdio_done, 1836 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1837 if (time_left == 0) { 1838 fep->mii_timeout = 1; 1839 netdev_err(fep->netdev, "MDIO write timeout\n"); 1840 ret = -ETIMEDOUT; 1841 } 1842 1843 pm_runtime_mark_last_busy(dev); 1844 pm_runtime_put_autosuspend(dev); 1845 1846 return ret; 1847 } 1848 1849 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1850 { 1851 struct fec_enet_private *fep = netdev_priv(ndev); 1852 int ret; 1853 1854 if (enable) { 1855 ret = clk_prepare_enable(fep->clk_ahb); 1856 if (ret) 1857 return ret; 1858 if (fep->clk_enet_out) { 1859 ret = clk_prepare_enable(fep->clk_enet_out); 1860 if (ret) 1861 goto failed_clk_enet_out; 1862 } 1863 if (fep->clk_ptp) { 1864 mutex_lock(&fep->ptp_clk_mutex); 1865 ret = clk_prepare_enable(fep->clk_ptp); 1866 if (ret) { 1867 mutex_unlock(&fep->ptp_clk_mutex); 1868 goto failed_clk_ptp; 1869 } else { 1870 fep->ptp_clk_on = true; 1871 } 1872 mutex_unlock(&fep->ptp_clk_mutex); 1873 } 1874 if (fep->clk_ref) { 1875 ret = clk_prepare_enable(fep->clk_ref); 1876 if (ret) 1877 goto failed_clk_ref; 1878 } 1879 } else { 1880 clk_disable_unprepare(fep->clk_ahb); 1881 if (fep->clk_enet_out) 1882 clk_disable_unprepare(fep->clk_enet_out); 1883 if (fep->clk_ptp) { 1884 mutex_lock(&fep->ptp_clk_mutex); 1885 clk_disable_unprepare(fep->clk_ptp); 1886 fep->ptp_clk_on = false; 1887 mutex_unlock(&fep->ptp_clk_mutex); 1888 } 1889 if (fep->clk_ref) 1890 clk_disable_unprepare(fep->clk_ref); 1891 } 1892 1893 return 0; 1894 1895 failed_clk_ref: 1896 if (fep->clk_ref) 1897 clk_disable_unprepare(fep->clk_ref); 1898 failed_clk_ptp: 1899 if (fep->clk_enet_out) 1900 clk_disable_unprepare(fep->clk_enet_out); 1901 failed_clk_enet_out: 1902 clk_disable_unprepare(fep->clk_ahb); 1903 1904 return ret; 1905 } 1906 1907 static int fec_enet_mii_probe(struct net_device *ndev) 1908 { 1909 struct fec_enet_private *fep = netdev_priv(ndev); 1910 struct phy_device *phy_dev = NULL; 1911 char mdio_bus_id[MII_BUS_ID_SIZE]; 1912 char phy_name[MII_BUS_ID_SIZE + 3]; 1913 int phy_id; 1914 int dev_id = fep->dev_id; 1915 1916 fep->phy_dev = NULL; 1917 1918 if (fep->phy_node) { 1919 phy_dev = of_phy_connect(ndev, fep->phy_node, 1920 &fec_enet_adjust_link, 0, 1921 fep->phy_interface); 1922 if (!phy_dev) 1923 return -ENODEV; 1924 } else { 1925 /* check for attached phy */ 1926 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1927 if ((fep->mii_bus->phy_mask & (1 << phy_id))) 1928 continue; 1929 if (fep->mii_bus->phy_map[phy_id] == NULL) 1930 continue; 1931 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) 1932 continue; 1933 if (dev_id--) 1934 continue; 1935 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1936 break; 1937 } 1938 1939 if (phy_id >= PHY_MAX_ADDR) { 1940 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1941 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 1942 phy_id = 0; 1943 } 1944 1945 snprintf(phy_name, sizeof(phy_name), 1946 PHY_ID_FMT, mdio_bus_id, phy_id); 1947 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 1948 fep->phy_interface); 1949 } 1950 1951 if (IS_ERR(phy_dev)) { 1952 netdev_err(ndev, "could not attach to PHY\n"); 1953 return PTR_ERR(phy_dev); 1954 } 1955 1956 /* mask with MAC supported features */ 1957 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 1958 phy_dev->supported &= PHY_GBIT_FEATURES; 1959 phy_dev->supported &= ~SUPPORTED_1000baseT_Half; 1960 #if !defined(CONFIG_M5272) 1961 phy_dev->supported |= SUPPORTED_Pause; 1962 #endif 1963 } 1964 else 1965 phy_dev->supported &= PHY_BASIC_FEATURES; 1966 1967 phy_dev->advertising = phy_dev->supported; 1968 1969 fep->phy_dev = phy_dev; 1970 fep->link = 0; 1971 fep->full_duplex = 0; 1972 1973 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 1974 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), 1975 fep->phy_dev->irq); 1976 1977 return 0; 1978 } 1979 1980 static int fec_enet_mii_init(struct platform_device *pdev) 1981 { 1982 static struct mii_bus *fec0_mii_bus; 1983 struct net_device *ndev = platform_get_drvdata(pdev); 1984 struct fec_enet_private *fep = netdev_priv(ndev); 1985 struct device_node *node; 1986 int err = -ENXIO, i; 1987 u32 mii_speed, holdtime; 1988 1989 /* 1990 * The i.MX28 dual fec interfaces are not equal. 1991 * Here are the differences: 1992 * 1993 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1994 * - fec0 acts as the 1588 time master while fec1 is slave 1995 * - external phys can only be configured by fec0 1996 * 1997 * That is to say fec1 can not work independently. It only works 1998 * when fec0 is working. The reason behind this design is that the 1999 * second interface is added primarily for Switch mode. 2000 * 2001 * Because of the last point above, both phys are attached on fec0 2002 * mdio interface in board design, and need to be configured by 2003 * fec0 mii_bus. 2004 */ 2005 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2006 /* fec1 uses fec0 mii_bus */ 2007 if (mii_cnt && fec0_mii_bus) { 2008 fep->mii_bus = fec0_mii_bus; 2009 mii_cnt++; 2010 return 0; 2011 } 2012 return -ENOENT; 2013 } 2014 2015 fep->mii_timeout = 0; 2016 2017 /* 2018 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 2019 * 2020 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2021 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2022 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2023 * document. 2024 */ 2025 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000); 2026 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2027 mii_speed--; 2028 if (mii_speed > 63) { 2029 dev_err(&pdev->dev, 2030 "fec clock (%lu) to fast to get right mii speed\n", 2031 clk_get_rate(fep->clk_ipg)); 2032 err = -EINVAL; 2033 goto err_out; 2034 } 2035 2036 /* 2037 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2038 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2039 * versions are RAZ there, so just ignore the difference and write the 2040 * register always. 2041 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2042 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2043 * output. 2044 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2045 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2046 * holdtime cannot result in a value greater than 3. 2047 */ 2048 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2049 2050 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2051 2052 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2053 2054 fep->mii_bus = mdiobus_alloc(); 2055 if (fep->mii_bus == NULL) { 2056 err = -ENOMEM; 2057 goto err_out; 2058 } 2059 2060 fep->mii_bus->name = "fec_enet_mii_bus"; 2061 fep->mii_bus->read = fec_enet_mdio_read; 2062 fep->mii_bus->write = fec_enet_mdio_write; 2063 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2064 pdev->name, fep->dev_id + 1); 2065 fep->mii_bus->priv = fep; 2066 fep->mii_bus->parent = &pdev->dev; 2067 2068 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 2069 if (!fep->mii_bus->irq) { 2070 err = -ENOMEM; 2071 goto err_out_free_mdiobus; 2072 } 2073 2074 for (i = 0; i < PHY_MAX_ADDR; i++) 2075 fep->mii_bus->irq[i] = PHY_POLL; 2076 2077 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2078 if (node) { 2079 err = of_mdiobus_register(fep->mii_bus, node); 2080 of_node_put(node); 2081 } else { 2082 err = mdiobus_register(fep->mii_bus); 2083 } 2084 2085 if (err) 2086 goto err_out_free_mdio_irq; 2087 2088 mii_cnt++; 2089 2090 /* save fec0 mii_bus */ 2091 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2092 fec0_mii_bus = fep->mii_bus; 2093 2094 return 0; 2095 2096 err_out_free_mdio_irq: 2097 kfree(fep->mii_bus->irq); 2098 err_out_free_mdiobus: 2099 mdiobus_free(fep->mii_bus); 2100 err_out: 2101 return err; 2102 } 2103 2104 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2105 { 2106 if (--mii_cnt == 0) { 2107 mdiobus_unregister(fep->mii_bus); 2108 kfree(fep->mii_bus->irq); 2109 mdiobus_free(fep->mii_bus); 2110 } 2111 } 2112 2113 static int fec_enet_get_settings(struct net_device *ndev, 2114 struct ethtool_cmd *cmd) 2115 { 2116 struct fec_enet_private *fep = netdev_priv(ndev); 2117 struct phy_device *phydev = fep->phy_dev; 2118 2119 if (!phydev) 2120 return -ENODEV; 2121 2122 return phy_ethtool_gset(phydev, cmd); 2123 } 2124 2125 static int fec_enet_set_settings(struct net_device *ndev, 2126 struct ethtool_cmd *cmd) 2127 { 2128 struct fec_enet_private *fep = netdev_priv(ndev); 2129 struct phy_device *phydev = fep->phy_dev; 2130 2131 if (!phydev) 2132 return -ENODEV; 2133 2134 return phy_ethtool_sset(phydev, cmd); 2135 } 2136 2137 static void fec_enet_get_drvinfo(struct net_device *ndev, 2138 struct ethtool_drvinfo *info) 2139 { 2140 struct fec_enet_private *fep = netdev_priv(ndev); 2141 2142 strlcpy(info->driver, fep->pdev->dev.driver->name, 2143 sizeof(info->driver)); 2144 strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); 2145 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2146 } 2147 2148 static int fec_enet_get_regs_len(struct net_device *ndev) 2149 { 2150 struct fec_enet_private *fep = netdev_priv(ndev); 2151 struct resource *r; 2152 int s = 0; 2153 2154 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2155 if (r) 2156 s = resource_size(r); 2157 2158 return s; 2159 } 2160 2161 /* List of registers that can be safety be read to dump them with ethtool */ 2162 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2163 defined(CONFIG_M520x) || defined(CONFIG_M532x) || \ 2164 defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) 2165 static u32 fec_enet_register_offset[] = { 2166 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2167 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2168 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2169 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2170 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2171 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2172 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2173 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2174 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2175 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2176 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2177 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2178 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2179 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2180 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2181 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2182 RMON_T_P_GTE2048, RMON_T_OCTETS, 2183 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2184 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2185 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2186 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2187 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2188 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2189 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2190 RMON_R_P_GTE2048, RMON_R_OCTETS, 2191 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2192 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2193 }; 2194 #else 2195 static u32 fec_enet_register_offset[] = { 2196 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2197 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2198 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2199 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2200 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2201 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2202 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2203 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2204 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2205 }; 2206 #endif 2207 2208 static void fec_enet_get_regs(struct net_device *ndev, 2209 struct ethtool_regs *regs, void *regbuf) 2210 { 2211 struct fec_enet_private *fep = netdev_priv(ndev); 2212 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2213 u32 *buf = (u32 *)regbuf; 2214 u32 i, off; 2215 2216 memset(buf, 0, regs->len); 2217 2218 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2219 off = fec_enet_register_offset[i] / 4; 2220 buf[off] = readl(&theregs[off]); 2221 } 2222 } 2223 2224 static int fec_enet_get_ts_info(struct net_device *ndev, 2225 struct ethtool_ts_info *info) 2226 { 2227 struct fec_enet_private *fep = netdev_priv(ndev); 2228 2229 if (fep->bufdesc_ex) { 2230 2231 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2232 SOF_TIMESTAMPING_RX_SOFTWARE | 2233 SOF_TIMESTAMPING_SOFTWARE | 2234 SOF_TIMESTAMPING_TX_HARDWARE | 2235 SOF_TIMESTAMPING_RX_HARDWARE | 2236 SOF_TIMESTAMPING_RAW_HARDWARE; 2237 if (fep->ptp_clock) 2238 info->phc_index = ptp_clock_index(fep->ptp_clock); 2239 else 2240 info->phc_index = -1; 2241 2242 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2243 (1 << HWTSTAMP_TX_ON); 2244 2245 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2246 (1 << HWTSTAMP_FILTER_ALL); 2247 return 0; 2248 } else { 2249 return ethtool_op_get_ts_info(ndev, info); 2250 } 2251 } 2252 2253 #if !defined(CONFIG_M5272) 2254 2255 static void fec_enet_get_pauseparam(struct net_device *ndev, 2256 struct ethtool_pauseparam *pause) 2257 { 2258 struct fec_enet_private *fep = netdev_priv(ndev); 2259 2260 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2261 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2262 pause->rx_pause = pause->tx_pause; 2263 } 2264 2265 static int fec_enet_set_pauseparam(struct net_device *ndev, 2266 struct ethtool_pauseparam *pause) 2267 { 2268 struct fec_enet_private *fep = netdev_priv(ndev); 2269 2270 if (!fep->phy_dev) 2271 return -ENODEV; 2272 2273 if (pause->tx_pause != pause->rx_pause) { 2274 netdev_info(ndev, 2275 "hardware only support enable/disable both tx and rx"); 2276 return -EINVAL; 2277 } 2278 2279 fep->pause_flag = 0; 2280 2281 /* tx pause must be same as rx pause */ 2282 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2283 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2284 2285 if (pause->rx_pause || pause->autoneg) { 2286 fep->phy_dev->supported |= ADVERTISED_Pause; 2287 fep->phy_dev->advertising |= ADVERTISED_Pause; 2288 } else { 2289 fep->phy_dev->supported &= ~ADVERTISED_Pause; 2290 fep->phy_dev->advertising &= ~ADVERTISED_Pause; 2291 } 2292 2293 if (pause->autoneg) { 2294 if (netif_running(ndev)) 2295 fec_stop(ndev); 2296 phy_start_aneg(fep->phy_dev); 2297 } 2298 if (netif_running(ndev)) { 2299 napi_disable(&fep->napi); 2300 netif_tx_lock_bh(ndev); 2301 fec_restart(ndev); 2302 netif_wake_queue(ndev); 2303 netif_tx_unlock_bh(ndev); 2304 napi_enable(&fep->napi); 2305 } 2306 2307 return 0; 2308 } 2309 2310 static const struct fec_stat { 2311 char name[ETH_GSTRING_LEN]; 2312 u16 offset; 2313 } fec_stats[] = { 2314 /* RMON TX */ 2315 { "tx_dropped", RMON_T_DROP }, 2316 { "tx_packets", RMON_T_PACKETS }, 2317 { "tx_broadcast", RMON_T_BC_PKT }, 2318 { "tx_multicast", RMON_T_MC_PKT }, 2319 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2320 { "tx_undersize", RMON_T_UNDERSIZE }, 2321 { "tx_oversize", RMON_T_OVERSIZE }, 2322 { "tx_fragment", RMON_T_FRAG }, 2323 { "tx_jabber", RMON_T_JAB }, 2324 { "tx_collision", RMON_T_COL }, 2325 { "tx_64byte", RMON_T_P64 }, 2326 { "tx_65to127byte", RMON_T_P65TO127 }, 2327 { "tx_128to255byte", RMON_T_P128TO255 }, 2328 { "tx_256to511byte", RMON_T_P256TO511 }, 2329 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2330 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2331 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2332 { "tx_octets", RMON_T_OCTETS }, 2333 2334 /* IEEE TX */ 2335 { "IEEE_tx_drop", IEEE_T_DROP }, 2336 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2337 { "IEEE_tx_1col", IEEE_T_1COL }, 2338 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2339 { "IEEE_tx_def", IEEE_T_DEF }, 2340 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2341 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2342 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2343 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2344 { "IEEE_tx_sqe", IEEE_T_SQE }, 2345 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2346 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2347 2348 /* RMON RX */ 2349 { "rx_packets", RMON_R_PACKETS }, 2350 { "rx_broadcast", RMON_R_BC_PKT }, 2351 { "rx_multicast", RMON_R_MC_PKT }, 2352 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2353 { "rx_undersize", RMON_R_UNDERSIZE }, 2354 { "rx_oversize", RMON_R_OVERSIZE }, 2355 { "rx_fragment", RMON_R_FRAG }, 2356 { "rx_jabber", RMON_R_JAB }, 2357 { "rx_64byte", RMON_R_P64 }, 2358 { "rx_65to127byte", RMON_R_P65TO127 }, 2359 { "rx_128to255byte", RMON_R_P128TO255 }, 2360 { "rx_256to511byte", RMON_R_P256TO511 }, 2361 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2362 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2363 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2364 { "rx_octets", RMON_R_OCTETS }, 2365 2366 /* IEEE RX */ 2367 { "IEEE_rx_drop", IEEE_R_DROP }, 2368 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2369 { "IEEE_rx_crc", IEEE_R_CRC }, 2370 { "IEEE_rx_align", IEEE_R_ALIGN }, 2371 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2372 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2373 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2374 }; 2375 2376 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2377 struct ethtool_stats *stats, u64 *data) 2378 { 2379 struct fec_enet_private *fep = netdev_priv(dev); 2380 int i; 2381 2382 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2383 data[i] = readl(fep->hwp + fec_stats[i].offset); 2384 } 2385 2386 static void fec_enet_get_strings(struct net_device *netdev, 2387 u32 stringset, u8 *data) 2388 { 2389 int i; 2390 switch (stringset) { 2391 case ETH_SS_STATS: 2392 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2393 memcpy(data + i * ETH_GSTRING_LEN, 2394 fec_stats[i].name, ETH_GSTRING_LEN); 2395 break; 2396 } 2397 } 2398 2399 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2400 { 2401 switch (sset) { 2402 case ETH_SS_STATS: 2403 return ARRAY_SIZE(fec_stats); 2404 default: 2405 return -EOPNOTSUPP; 2406 } 2407 } 2408 #endif /* !defined(CONFIG_M5272) */ 2409 2410 static int fec_enet_nway_reset(struct net_device *dev) 2411 { 2412 struct fec_enet_private *fep = netdev_priv(dev); 2413 struct phy_device *phydev = fep->phy_dev; 2414 2415 if (!phydev) 2416 return -ENODEV; 2417 2418 return genphy_restart_aneg(phydev); 2419 } 2420 2421 /* ITR clock source is enet system clock (clk_ahb). 2422 * TCTT unit is cycle_ns * 64 cycle 2423 * So, the ICTT value = X us / (cycle_ns * 64) 2424 */ 2425 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2426 { 2427 struct fec_enet_private *fep = netdev_priv(ndev); 2428 2429 return us * (fep->itr_clk_rate / 64000) / 1000; 2430 } 2431 2432 /* Set threshold for interrupt coalescing */ 2433 static void fec_enet_itr_coal_set(struct net_device *ndev) 2434 { 2435 struct fec_enet_private *fep = netdev_priv(ndev); 2436 int rx_itr, tx_itr; 2437 2438 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 2439 return; 2440 2441 /* Must be greater than zero to avoid unpredictable behavior */ 2442 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2443 !fep->tx_time_itr || !fep->tx_pkts_itr) 2444 return; 2445 2446 /* Select enet system clock as Interrupt Coalescing 2447 * timer Clock Source 2448 */ 2449 rx_itr = FEC_ITR_CLK_SEL; 2450 tx_itr = FEC_ITR_CLK_SEL; 2451 2452 /* set ICFT and ICTT */ 2453 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2454 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2455 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2456 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2457 2458 rx_itr |= FEC_ITR_EN; 2459 tx_itr |= FEC_ITR_EN; 2460 2461 writel(tx_itr, fep->hwp + FEC_TXIC0); 2462 writel(rx_itr, fep->hwp + FEC_RXIC0); 2463 writel(tx_itr, fep->hwp + FEC_TXIC1); 2464 writel(rx_itr, fep->hwp + FEC_RXIC1); 2465 writel(tx_itr, fep->hwp + FEC_TXIC2); 2466 writel(rx_itr, fep->hwp + FEC_RXIC2); 2467 } 2468 2469 static int 2470 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2471 { 2472 struct fec_enet_private *fep = netdev_priv(ndev); 2473 2474 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 2475 return -EOPNOTSUPP; 2476 2477 ec->rx_coalesce_usecs = fep->rx_time_itr; 2478 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2479 2480 ec->tx_coalesce_usecs = fep->tx_time_itr; 2481 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2482 2483 return 0; 2484 } 2485 2486 static int 2487 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2488 { 2489 struct fec_enet_private *fep = netdev_priv(ndev); 2490 unsigned int cycle; 2491 2492 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 2493 return -EOPNOTSUPP; 2494 2495 if (ec->rx_max_coalesced_frames > 255) { 2496 pr_err("Rx coalesced frames exceed hardware limiation"); 2497 return -EINVAL; 2498 } 2499 2500 if (ec->tx_max_coalesced_frames > 255) { 2501 pr_err("Tx coalesced frame exceed hardware limiation"); 2502 return -EINVAL; 2503 } 2504 2505 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); 2506 if (cycle > 0xFFFF) { 2507 pr_err("Rx coalesed usec exceeed hardware limiation"); 2508 return -EINVAL; 2509 } 2510 2511 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); 2512 if (cycle > 0xFFFF) { 2513 pr_err("Rx coalesed usec exceeed hardware limiation"); 2514 return -EINVAL; 2515 } 2516 2517 fep->rx_time_itr = ec->rx_coalesce_usecs; 2518 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2519 2520 fep->tx_time_itr = ec->tx_coalesce_usecs; 2521 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2522 2523 fec_enet_itr_coal_set(ndev); 2524 2525 return 0; 2526 } 2527 2528 static void fec_enet_itr_coal_init(struct net_device *ndev) 2529 { 2530 struct ethtool_coalesce ec; 2531 2532 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2533 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2534 2535 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2536 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2537 2538 fec_enet_set_coalesce(ndev, &ec); 2539 } 2540 2541 static int fec_enet_get_tunable(struct net_device *netdev, 2542 const struct ethtool_tunable *tuna, 2543 void *data) 2544 { 2545 struct fec_enet_private *fep = netdev_priv(netdev); 2546 int ret = 0; 2547 2548 switch (tuna->id) { 2549 case ETHTOOL_RX_COPYBREAK: 2550 *(u32 *)data = fep->rx_copybreak; 2551 break; 2552 default: 2553 ret = -EINVAL; 2554 break; 2555 } 2556 2557 return ret; 2558 } 2559 2560 static int fec_enet_set_tunable(struct net_device *netdev, 2561 const struct ethtool_tunable *tuna, 2562 const void *data) 2563 { 2564 struct fec_enet_private *fep = netdev_priv(netdev); 2565 int ret = 0; 2566 2567 switch (tuna->id) { 2568 case ETHTOOL_RX_COPYBREAK: 2569 fep->rx_copybreak = *(u32 *)data; 2570 break; 2571 default: 2572 ret = -EINVAL; 2573 break; 2574 } 2575 2576 return ret; 2577 } 2578 2579 static void 2580 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2581 { 2582 struct fec_enet_private *fep = netdev_priv(ndev); 2583 2584 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2585 wol->supported = WAKE_MAGIC; 2586 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2587 } else { 2588 wol->supported = wol->wolopts = 0; 2589 } 2590 } 2591 2592 static int 2593 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2594 { 2595 struct fec_enet_private *fep = netdev_priv(ndev); 2596 2597 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2598 return -EINVAL; 2599 2600 if (wol->wolopts & ~WAKE_MAGIC) 2601 return -EINVAL; 2602 2603 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2604 if (device_may_wakeup(&ndev->dev)) { 2605 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2606 if (fep->irq[0] > 0) 2607 enable_irq_wake(fep->irq[0]); 2608 } else { 2609 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2610 if (fep->irq[0] > 0) 2611 disable_irq_wake(fep->irq[0]); 2612 } 2613 2614 return 0; 2615 } 2616 2617 static const struct ethtool_ops fec_enet_ethtool_ops = { 2618 .get_settings = fec_enet_get_settings, 2619 .set_settings = fec_enet_set_settings, 2620 .get_drvinfo = fec_enet_get_drvinfo, 2621 .get_regs_len = fec_enet_get_regs_len, 2622 .get_regs = fec_enet_get_regs, 2623 .nway_reset = fec_enet_nway_reset, 2624 .get_link = ethtool_op_get_link, 2625 .get_coalesce = fec_enet_get_coalesce, 2626 .set_coalesce = fec_enet_set_coalesce, 2627 #ifndef CONFIG_M5272 2628 .get_pauseparam = fec_enet_get_pauseparam, 2629 .set_pauseparam = fec_enet_set_pauseparam, 2630 .get_strings = fec_enet_get_strings, 2631 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2632 .get_sset_count = fec_enet_get_sset_count, 2633 #endif 2634 .get_ts_info = fec_enet_get_ts_info, 2635 .get_tunable = fec_enet_get_tunable, 2636 .set_tunable = fec_enet_set_tunable, 2637 .get_wol = fec_enet_get_wol, 2638 .set_wol = fec_enet_set_wol, 2639 }; 2640 2641 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2642 { 2643 struct fec_enet_private *fep = netdev_priv(ndev); 2644 struct phy_device *phydev = fep->phy_dev; 2645 2646 if (!netif_running(ndev)) 2647 return -EINVAL; 2648 2649 if (!phydev) 2650 return -ENODEV; 2651 2652 if (fep->bufdesc_ex) { 2653 if (cmd == SIOCSHWTSTAMP) 2654 return fec_ptp_set(ndev, rq); 2655 if (cmd == SIOCGHWTSTAMP) 2656 return fec_ptp_get(ndev, rq); 2657 } 2658 2659 return phy_mii_ioctl(phydev, rq, cmd); 2660 } 2661 2662 static void fec_enet_free_buffers(struct net_device *ndev) 2663 { 2664 struct fec_enet_private *fep = netdev_priv(ndev); 2665 unsigned int i; 2666 struct sk_buff *skb; 2667 struct bufdesc *bdp; 2668 struct fec_enet_priv_tx_q *txq; 2669 struct fec_enet_priv_rx_q *rxq; 2670 unsigned int q; 2671 2672 for (q = 0; q < fep->num_rx_queues; q++) { 2673 rxq = fep->rx_queue[q]; 2674 bdp = rxq->rx_bd_base; 2675 for (i = 0; i < rxq->rx_ring_size; i++) { 2676 skb = rxq->rx_skbuff[i]; 2677 rxq->rx_skbuff[i] = NULL; 2678 if (skb) { 2679 dma_unmap_single(&fep->pdev->dev, 2680 bdp->cbd_bufaddr, 2681 FEC_ENET_RX_FRSIZE - fep->rx_align, 2682 DMA_FROM_DEVICE); 2683 dev_kfree_skb(skb); 2684 } 2685 bdp = fec_enet_get_nextdesc(bdp, fep, q); 2686 } 2687 } 2688 2689 for (q = 0; q < fep->num_tx_queues; q++) { 2690 txq = fep->tx_queue[q]; 2691 bdp = txq->tx_bd_base; 2692 for (i = 0; i < txq->tx_ring_size; i++) { 2693 kfree(txq->tx_bounce[i]); 2694 txq->tx_bounce[i] = NULL; 2695 skb = txq->tx_skbuff[i]; 2696 txq->tx_skbuff[i] = NULL; 2697 dev_kfree_skb(skb); 2698 } 2699 } 2700 } 2701 2702 static void fec_enet_free_queue(struct net_device *ndev) 2703 { 2704 struct fec_enet_private *fep = netdev_priv(ndev); 2705 int i; 2706 struct fec_enet_priv_tx_q *txq; 2707 2708 for (i = 0; i < fep->num_tx_queues; i++) 2709 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2710 txq = fep->tx_queue[i]; 2711 dma_free_coherent(NULL, 2712 txq->tx_ring_size * TSO_HEADER_SIZE, 2713 txq->tso_hdrs, 2714 txq->tso_hdrs_dma); 2715 } 2716 2717 for (i = 0; i < fep->num_rx_queues; i++) 2718 kfree(fep->rx_queue[i]); 2719 for (i = 0; i < fep->num_tx_queues; i++) 2720 kfree(fep->tx_queue[i]); 2721 } 2722 2723 static int fec_enet_alloc_queue(struct net_device *ndev) 2724 { 2725 struct fec_enet_private *fep = netdev_priv(ndev); 2726 int i; 2727 int ret = 0; 2728 struct fec_enet_priv_tx_q *txq; 2729 2730 for (i = 0; i < fep->num_tx_queues; i++) { 2731 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 2732 if (!txq) { 2733 ret = -ENOMEM; 2734 goto alloc_failed; 2735 } 2736 2737 fep->tx_queue[i] = txq; 2738 txq->tx_ring_size = TX_RING_SIZE; 2739 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size; 2740 2741 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2742 txq->tx_wake_threshold = 2743 (txq->tx_ring_size - txq->tx_stop_threshold) / 2; 2744 2745 txq->tso_hdrs = dma_alloc_coherent(NULL, 2746 txq->tx_ring_size * TSO_HEADER_SIZE, 2747 &txq->tso_hdrs_dma, 2748 GFP_KERNEL); 2749 if (!txq->tso_hdrs) { 2750 ret = -ENOMEM; 2751 goto alloc_failed; 2752 } 2753 } 2754 2755 for (i = 0; i < fep->num_rx_queues; i++) { 2756 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 2757 GFP_KERNEL); 2758 if (!fep->rx_queue[i]) { 2759 ret = -ENOMEM; 2760 goto alloc_failed; 2761 } 2762 2763 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE; 2764 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size; 2765 } 2766 return ret; 2767 2768 alloc_failed: 2769 fec_enet_free_queue(ndev); 2770 return ret; 2771 } 2772 2773 static int 2774 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 2775 { 2776 struct fec_enet_private *fep = netdev_priv(ndev); 2777 unsigned int i; 2778 struct sk_buff *skb; 2779 struct bufdesc *bdp; 2780 struct fec_enet_priv_rx_q *rxq; 2781 2782 rxq = fep->rx_queue[queue]; 2783 bdp = rxq->rx_bd_base; 2784 for (i = 0; i < rxq->rx_ring_size; i++) { 2785 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2786 if (!skb) 2787 goto err_alloc; 2788 2789 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 2790 dev_kfree_skb(skb); 2791 goto err_alloc; 2792 } 2793 2794 rxq->rx_skbuff[i] = skb; 2795 bdp->cbd_sc = BD_ENET_RX_EMPTY; 2796 2797 if (fep->bufdesc_ex) { 2798 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2799 ebdp->cbd_esc = BD_ENET_RX_INT; 2800 } 2801 2802 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 2803 } 2804 2805 /* Set the last buffer to wrap. */ 2806 bdp = fec_enet_get_prevdesc(bdp, fep, queue); 2807 bdp->cbd_sc |= BD_SC_WRAP; 2808 return 0; 2809 2810 err_alloc: 2811 fec_enet_free_buffers(ndev); 2812 return -ENOMEM; 2813 } 2814 2815 static int 2816 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 2817 { 2818 struct fec_enet_private *fep = netdev_priv(ndev); 2819 unsigned int i; 2820 struct bufdesc *bdp; 2821 struct fec_enet_priv_tx_q *txq; 2822 2823 txq = fep->tx_queue[queue]; 2824 bdp = txq->tx_bd_base; 2825 for (i = 0; i < txq->tx_ring_size; i++) { 2826 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2827 if (!txq->tx_bounce[i]) 2828 goto err_alloc; 2829 2830 bdp->cbd_sc = 0; 2831 bdp->cbd_bufaddr = 0; 2832 2833 if (fep->bufdesc_ex) { 2834 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2835 ebdp->cbd_esc = BD_ENET_TX_INT; 2836 } 2837 2838 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 2839 } 2840 2841 /* Set the last buffer to wrap. */ 2842 bdp = fec_enet_get_prevdesc(bdp, fep, queue); 2843 bdp->cbd_sc |= BD_SC_WRAP; 2844 2845 return 0; 2846 2847 err_alloc: 2848 fec_enet_free_buffers(ndev); 2849 return -ENOMEM; 2850 } 2851 2852 static int fec_enet_alloc_buffers(struct net_device *ndev) 2853 { 2854 struct fec_enet_private *fep = netdev_priv(ndev); 2855 unsigned int i; 2856 2857 for (i = 0; i < fep->num_rx_queues; i++) 2858 if (fec_enet_alloc_rxq_buffers(ndev, i)) 2859 return -ENOMEM; 2860 2861 for (i = 0; i < fep->num_tx_queues; i++) 2862 if (fec_enet_alloc_txq_buffers(ndev, i)) 2863 return -ENOMEM; 2864 return 0; 2865 } 2866 2867 static int 2868 fec_enet_open(struct net_device *ndev) 2869 { 2870 struct fec_enet_private *fep = netdev_priv(ndev); 2871 int ret; 2872 2873 ret = pm_runtime_get_sync(&fep->pdev->dev); 2874 if (ret < 0) 2875 return ret; 2876 2877 pinctrl_pm_select_default_state(&fep->pdev->dev); 2878 ret = fec_enet_clk_enable(ndev, true); 2879 if (ret) 2880 goto clk_enable; 2881 2882 /* I should reset the ring buffers here, but I don't yet know 2883 * a simple way to do that. 2884 */ 2885 2886 ret = fec_enet_alloc_buffers(ndev); 2887 if (ret) 2888 goto err_enet_alloc; 2889 2890 /* Init MAC prior to mii bus probe */ 2891 fec_restart(ndev); 2892 2893 /* Probe and connect to PHY when open the interface */ 2894 ret = fec_enet_mii_probe(ndev); 2895 if (ret) 2896 goto err_enet_mii_probe; 2897 2898 napi_enable(&fep->napi); 2899 phy_start(fep->phy_dev); 2900 netif_tx_start_all_queues(ndev); 2901 2902 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 2903 FEC_WOL_FLAG_ENABLE); 2904 2905 return 0; 2906 2907 err_enet_mii_probe: 2908 fec_enet_free_buffers(ndev); 2909 err_enet_alloc: 2910 fec_enet_clk_enable(ndev, false); 2911 clk_enable: 2912 pm_runtime_mark_last_busy(&fep->pdev->dev); 2913 pm_runtime_put_autosuspend(&fep->pdev->dev); 2914 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2915 return ret; 2916 } 2917 2918 static int 2919 fec_enet_close(struct net_device *ndev) 2920 { 2921 struct fec_enet_private *fep = netdev_priv(ndev); 2922 2923 phy_stop(fep->phy_dev); 2924 2925 if (netif_device_present(ndev)) { 2926 napi_disable(&fep->napi); 2927 netif_tx_disable(ndev); 2928 fec_stop(ndev); 2929 } 2930 2931 phy_disconnect(fep->phy_dev); 2932 fep->phy_dev = NULL; 2933 2934 fec_enet_clk_enable(ndev, false); 2935 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2936 pm_runtime_mark_last_busy(&fep->pdev->dev); 2937 pm_runtime_put_autosuspend(&fep->pdev->dev); 2938 2939 fec_enet_free_buffers(ndev); 2940 2941 return 0; 2942 } 2943 2944 /* Set or clear the multicast filter for this adaptor. 2945 * Skeleton taken from sunlance driver. 2946 * The CPM Ethernet implementation allows Multicast as well as individual 2947 * MAC address filtering. Some of the drivers check to make sure it is 2948 * a group multicast address, and discard those that are not. I guess I 2949 * will do the same for now, but just remove the test if you want 2950 * individual filtering as well (do the upper net layers want or support 2951 * this kind of feature?). 2952 */ 2953 2954 #define HASH_BITS 6 /* #bits in hash */ 2955 #define CRC32_POLY 0xEDB88320 2956 2957 static void set_multicast_list(struct net_device *ndev) 2958 { 2959 struct fec_enet_private *fep = netdev_priv(ndev); 2960 struct netdev_hw_addr *ha; 2961 unsigned int i, bit, data, crc, tmp; 2962 unsigned char hash; 2963 2964 if (ndev->flags & IFF_PROMISC) { 2965 tmp = readl(fep->hwp + FEC_R_CNTRL); 2966 tmp |= 0x8; 2967 writel(tmp, fep->hwp + FEC_R_CNTRL); 2968 return; 2969 } 2970 2971 tmp = readl(fep->hwp + FEC_R_CNTRL); 2972 tmp &= ~0x8; 2973 writel(tmp, fep->hwp + FEC_R_CNTRL); 2974 2975 if (ndev->flags & IFF_ALLMULTI) { 2976 /* Catch all multicast addresses, so set the 2977 * filter to all 1's 2978 */ 2979 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2980 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2981 2982 return; 2983 } 2984 2985 /* Clear filter and add the addresses in hash register 2986 */ 2987 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2988 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2989 2990 netdev_for_each_mc_addr(ha, ndev) { 2991 /* calculate crc32 value of mac address */ 2992 crc = 0xffffffff; 2993 2994 for (i = 0; i < ndev->addr_len; i++) { 2995 data = ha->addr[i]; 2996 for (bit = 0; bit < 8; bit++, data >>= 1) { 2997 crc = (crc >> 1) ^ 2998 (((crc ^ data) & 1) ? CRC32_POLY : 0); 2999 } 3000 } 3001 3002 /* only upper 6 bits (HASH_BITS) are used 3003 * which point to specific bit in he hash registers 3004 */ 3005 hash = (crc >> (32 - HASH_BITS)) & 0x3f; 3006 3007 if (hash > 31) { 3008 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3009 tmp |= 1 << (hash - 32); 3010 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3011 } else { 3012 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3013 tmp |= 1 << hash; 3014 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3015 } 3016 } 3017 } 3018 3019 /* Set a MAC change in hardware. */ 3020 static int 3021 fec_set_mac_address(struct net_device *ndev, void *p) 3022 { 3023 struct fec_enet_private *fep = netdev_priv(ndev); 3024 struct sockaddr *addr = p; 3025 3026 if (addr) { 3027 if (!is_valid_ether_addr(addr->sa_data)) 3028 return -EADDRNOTAVAIL; 3029 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 3030 } 3031 3032 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3033 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3034 fep->hwp + FEC_ADDR_LOW); 3035 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3036 fep->hwp + FEC_ADDR_HIGH); 3037 return 0; 3038 } 3039 3040 #ifdef CONFIG_NET_POLL_CONTROLLER 3041 /** 3042 * fec_poll_controller - FEC Poll controller function 3043 * @dev: The FEC network adapter 3044 * 3045 * Polled functionality used by netconsole and others in non interrupt mode 3046 * 3047 */ 3048 static void fec_poll_controller(struct net_device *dev) 3049 { 3050 int i; 3051 struct fec_enet_private *fep = netdev_priv(dev); 3052 3053 for (i = 0; i < FEC_IRQ_NUM; i++) { 3054 if (fep->irq[i] > 0) { 3055 disable_irq(fep->irq[i]); 3056 fec_enet_interrupt(fep->irq[i], dev); 3057 enable_irq(fep->irq[i]); 3058 } 3059 } 3060 } 3061 #endif 3062 3063 #define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM 3064 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3065 netdev_features_t features) 3066 { 3067 struct fec_enet_private *fep = netdev_priv(netdev); 3068 netdev_features_t changed = features ^ netdev->features; 3069 3070 netdev->features = features; 3071 3072 /* Receive checksum has been changed */ 3073 if (changed & NETIF_F_RXCSUM) { 3074 if (features & NETIF_F_RXCSUM) 3075 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3076 else 3077 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3078 } 3079 } 3080 3081 static int fec_set_features(struct net_device *netdev, 3082 netdev_features_t features) 3083 { 3084 struct fec_enet_private *fep = netdev_priv(netdev); 3085 netdev_features_t changed = features ^ netdev->features; 3086 3087 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) { 3088 napi_disable(&fep->napi); 3089 netif_tx_lock_bh(netdev); 3090 fec_stop(netdev); 3091 fec_enet_set_netdev_features(netdev, features); 3092 fec_restart(netdev); 3093 netif_tx_wake_all_queues(netdev); 3094 netif_tx_unlock_bh(netdev); 3095 napi_enable(&fep->napi); 3096 } else { 3097 fec_enet_set_netdev_features(netdev, features); 3098 } 3099 3100 return 0; 3101 } 3102 3103 static const struct net_device_ops fec_netdev_ops = { 3104 .ndo_open = fec_enet_open, 3105 .ndo_stop = fec_enet_close, 3106 .ndo_start_xmit = fec_enet_start_xmit, 3107 .ndo_set_rx_mode = set_multicast_list, 3108 .ndo_change_mtu = eth_change_mtu, 3109 .ndo_validate_addr = eth_validate_addr, 3110 .ndo_tx_timeout = fec_timeout, 3111 .ndo_set_mac_address = fec_set_mac_address, 3112 .ndo_do_ioctl = fec_enet_ioctl, 3113 #ifdef CONFIG_NET_POLL_CONTROLLER 3114 .ndo_poll_controller = fec_poll_controller, 3115 #endif 3116 .ndo_set_features = fec_set_features, 3117 }; 3118 3119 /* 3120 * XXX: We need to clean up on failure exits here. 3121 * 3122 */ 3123 static int fec_enet_init(struct net_device *ndev) 3124 { 3125 struct fec_enet_private *fep = netdev_priv(ndev); 3126 struct fec_enet_priv_tx_q *txq; 3127 struct fec_enet_priv_rx_q *rxq; 3128 struct bufdesc *cbd_base; 3129 dma_addr_t bd_dma; 3130 int bd_size; 3131 unsigned int i; 3132 3133 #if defined(CONFIG_ARM) 3134 fep->rx_align = 0xf; 3135 fep->tx_align = 0xf; 3136 #else 3137 fep->rx_align = 0x3; 3138 fep->tx_align = 0x3; 3139 #endif 3140 3141 fec_enet_alloc_queue(ndev); 3142 3143 if (fep->bufdesc_ex) 3144 fep->bufdesc_size = sizeof(struct bufdesc_ex); 3145 else 3146 fep->bufdesc_size = sizeof(struct bufdesc); 3147 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * 3148 fep->bufdesc_size; 3149 3150 /* Allocate memory for buffer descriptors. */ 3151 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3152 GFP_KERNEL); 3153 if (!cbd_base) { 3154 return -ENOMEM; 3155 } 3156 3157 memset(cbd_base, 0, bd_size); 3158 3159 /* Get the Ethernet address */ 3160 fec_get_mac(ndev); 3161 /* make sure MAC we just acquired is programmed into the hw */ 3162 fec_set_mac_address(ndev, NULL); 3163 3164 /* Set receive and transmit descriptor base. */ 3165 for (i = 0; i < fep->num_rx_queues; i++) { 3166 rxq = fep->rx_queue[i]; 3167 rxq->index = i; 3168 rxq->rx_bd_base = (struct bufdesc *)cbd_base; 3169 rxq->bd_dma = bd_dma; 3170 if (fep->bufdesc_ex) { 3171 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size; 3172 cbd_base = (struct bufdesc *) 3173 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size); 3174 } else { 3175 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size; 3176 cbd_base += rxq->rx_ring_size; 3177 } 3178 } 3179 3180 for (i = 0; i < fep->num_tx_queues; i++) { 3181 txq = fep->tx_queue[i]; 3182 txq->index = i; 3183 txq->tx_bd_base = (struct bufdesc *)cbd_base; 3184 txq->bd_dma = bd_dma; 3185 if (fep->bufdesc_ex) { 3186 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size; 3187 cbd_base = (struct bufdesc *) 3188 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size); 3189 } else { 3190 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size; 3191 cbd_base += txq->tx_ring_size; 3192 } 3193 } 3194 3195 3196 /* The FEC Ethernet specific entries in the device structure */ 3197 ndev->watchdog_timeo = TX_TIMEOUT; 3198 ndev->netdev_ops = &fec_netdev_ops; 3199 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3200 3201 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3202 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3203 3204 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3205 /* enable hw VLAN support */ 3206 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3207 3208 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3209 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3210 3211 /* enable hw accelerator */ 3212 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3213 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3214 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3215 } 3216 3217 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 3218 fep->tx_align = 0; 3219 fep->rx_align = 0x3f; 3220 } 3221 3222 ndev->hw_features = ndev->features; 3223 3224 fec_restart(ndev); 3225 3226 return 0; 3227 } 3228 3229 #ifdef CONFIG_OF 3230 static void fec_reset_phy(struct platform_device *pdev) 3231 { 3232 int err, phy_reset; 3233 int msec = 1; 3234 struct device_node *np = pdev->dev.of_node; 3235 3236 if (!np) 3237 return; 3238 3239 of_property_read_u32(np, "phy-reset-duration", &msec); 3240 /* A sane reset duration should not be longer than 1s */ 3241 if (msec > 1000) 3242 msec = 1; 3243 3244 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3245 if (!gpio_is_valid(phy_reset)) 3246 return; 3247 3248 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3249 GPIOF_OUT_INIT_LOW, "phy-reset"); 3250 if (err) { 3251 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3252 return; 3253 } 3254 msleep(msec); 3255 gpio_set_value(phy_reset, 1); 3256 } 3257 #else /* CONFIG_OF */ 3258 static void fec_reset_phy(struct platform_device *pdev) 3259 { 3260 /* 3261 * In case of platform probe, the reset has been done 3262 * by machine code. 3263 */ 3264 } 3265 #endif /* CONFIG_OF */ 3266 3267 static void 3268 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3269 { 3270 struct device_node *np = pdev->dev.of_node; 3271 int err; 3272 3273 *num_tx = *num_rx = 1; 3274 3275 if (!np || !of_device_is_available(np)) 3276 return; 3277 3278 /* parse the num of tx and rx queues */ 3279 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3280 if (err) 3281 *num_tx = 1; 3282 3283 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3284 if (err) 3285 *num_rx = 1; 3286 3287 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3288 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3289 *num_tx); 3290 *num_tx = 1; 3291 return; 3292 } 3293 3294 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3295 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3296 *num_rx); 3297 *num_rx = 1; 3298 return; 3299 } 3300 3301 } 3302 3303 static int 3304 fec_probe(struct platform_device *pdev) 3305 { 3306 struct fec_enet_private *fep; 3307 struct fec_platform_data *pdata; 3308 struct net_device *ndev; 3309 int i, irq, ret = 0; 3310 struct resource *r; 3311 const struct of_device_id *of_id; 3312 static int dev_id; 3313 struct device_node *np = pdev->dev.of_node, *phy_node; 3314 int num_tx_qs; 3315 int num_rx_qs; 3316 3317 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3318 3319 /* Init network device */ 3320 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private), 3321 num_tx_qs, num_rx_qs); 3322 if (!ndev) 3323 return -ENOMEM; 3324 3325 SET_NETDEV_DEV(ndev, &pdev->dev); 3326 3327 /* setup board info structure */ 3328 fep = netdev_priv(ndev); 3329 3330 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3331 if (of_id) 3332 pdev->id_entry = of_id->data; 3333 fep->quirks = pdev->id_entry->driver_data; 3334 3335 fep->netdev = ndev; 3336 fep->num_rx_queues = num_rx_qs; 3337 fep->num_tx_queues = num_tx_qs; 3338 3339 #if !defined(CONFIG_M5272) 3340 /* default enable pause frame auto negotiation */ 3341 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3342 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3343 #endif 3344 3345 /* Select default pin state */ 3346 pinctrl_pm_select_default_state(&pdev->dev); 3347 3348 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3349 fep->hwp = devm_ioremap_resource(&pdev->dev, r); 3350 if (IS_ERR(fep->hwp)) { 3351 ret = PTR_ERR(fep->hwp); 3352 goto failed_ioremap; 3353 } 3354 3355 fep->pdev = pdev; 3356 fep->dev_id = dev_id++; 3357 3358 platform_set_drvdata(pdev, ndev); 3359 3360 if (of_get_property(np, "fsl,magic-packet", NULL)) 3361 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3362 3363 phy_node = of_parse_phandle(np, "phy-handle", 0); 3364 if (!phy_node && of_phy_is_fixed_link(np)) { 3365 ret = of_phy_register_fixed_link(np); 3366 if (ret < 0) { 3367 dev_err(&pdev->dev, 3368 "broken fixed-link specification\n"); 3369 goto failed_phy; 3370 } 3371 phy_node = of_node_get(np); 3372 } 3373 fep->phy_node = phy_node; 3374 3375 ret = of_get_phy_mode(pdev->dev.of_node); 3376 if (ret < 0) { 3377 pdata = dev_get_platdata(&pdev->dev); 3378 if (pdata) 3379 fep->phy_interface = pdata->phy; 3380 else 3381 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3382 } else { 3383 fep->phy_interface = ret; 3384 } 3385 3386 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3387 if (IS_ERR(fep->clk_ipg)) { 3388 ret = PTR_ERR(fep->clk_ipg); 3389 goto failed_clk; 3390 } 3391 3392 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3393 if (IS_ERR(fep->clk_ahb)) { 3394 ret = PTR_ERR(fep->clk_ahb); 3395 goto failed_clk; 3396 } 3397 3398 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3399 3400 /* enet_out is optional, depends on board */ 3401 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3402 if (IS_ERR(fep->clk_enet_out)) 3403 fep->clk_enet_out = NULL; 3404 3405 fep->ptp_clk_on = false; 3406 mutex_init(&fep->ptp_clk_mutex); 3407 3408 /* clk_ref is optional, depends on board */ 3409 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3410 if (IS_ERR(fep->clk_ref)) 3411 fep->clk_ref = NULL; 3412 3413 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3414 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3415 if (IS_ERR(fep->clk_ptp)) { 3416 fep->clk_ptp = NULL; 3417 fep->bufdesc_ex = false; 3418 } 3419 3420 ret = fec_enet_clk_enable(ndev, true); 3421 if (ret) 3422 goto failed_clk; 3423 3424 ret = clk_prepare_enable(fep->clk_ipg); 3425 if (ret) 3426 goto failed_clk_ipg; 3427 3428 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); 3429 if (!IS_ERR(fep->reg_phy)) { 3430 ret = regulator_enable(fep->reg_phy); 3431 if (ret) { 3432 dev_err(&pdev->dev, 3433 "Failed to enable phy regulator: %d\n", ret); 3434 goto failed_regulator; 3435 } 3436 } else { 3437 fep->reg_phy = NULL; 3438 } 3439 3440 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3441 pm_runtime_use_autosuspend(&pdev->dev); 3442 pm_runtime_get_noresume(&pdev->dev); 3443 pm_runtime_set_active(&pdev->dev); 3444 pm_runtime_enable(&pdev->dev); 3445 3446 fec_reset_phy(pdev); 3447 3448 if (fep->bufdesc_ex) 3449 fec_ptp_init(pdev); 3450 3451 ret = fec_enet_init(ndev); 3452 if (ret) 3453 goto failed_init; 3454 3455 for (i = 0; i < FEC_IRQ_NUM; i++) { 3456 irq = platform_get_irq(pdev, i); 3457 if (irq < 0) { 3458 if (i) 3459 break; 3460 ret = irq; 3461 goto failed_irq; 3462 } 3463 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3464 0, pdev->name, ndev); 3465 if (ret) 3466 goto failed_irq; 3467 3468 fep->irq[i] = irq; 3469 } 3470 3471 init_completion(&fep->mdio_done); 3472 ret = fec_enet_mii_init(pdev); 3473 if (ret) 3474 goto failed_mii_init; 3475 3476 /* Carrier starts down, phylib will bring it up */ 3477 netif_carrier_off(ndev); 3478 fec_enet_clk_enable(ndev, false); 3479 pinctrl_pm_select_sleep_state(&pdev->dev); 3480 3481 ret = register_netdev(ndev); 3482 if (ret) 3483 goto failed_register; 3484 3485 device_init_wakeup(&ndev->dev, fep->wol_flag & 3486 FEC_WOL_HAS_MAGIC_PACKET); 3487 3488 if (fep->bufdesc_ex && fep->ptp_clock) 3489 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3490 3491 fep->rx_copybreak = COPYBREAK_DEFAULT; 3492 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3493 3494 pm_runtime_mark_last_busy(&pdev->dev); 3495 pm_runtime_put_autosuspend(&pdev->dev); 3496 3497 return 0; 3498 3499 failed_register: 3500 fec_enet_mii_remove(fep); 3501 failed_mii_init: 3502 failed_irq: 3503 failed_init: 3504 fec_ptp_stop(pdev); 3505 if (fep->reg_phy) 3506 regulator_disable(fep->reg_phy); 3507 failed_regulator: 3508 clk_disable_unprepare(fep->clk_ipg); 3509 failed_clk_ipg: 3510 fec_enet_clk_enable(ndev, false); 3511 failed_clk: 3512 failed_phy: 3513 of_node_put(phy_node); 3514 failed_ioremap: 3515 free_netdev(ndev); 3516 3517 return ret; 3518 } 3519 3520 static int 3521 fec_drv_remove(struct platform_device *pdev) 3522 { 3523 struct net_device *ndev = platform_get_drvdata(pdev); 3524 struct fec_enet_private *fep = netdev_priv(ndev); 3525 3526 cancel_work_sync(&fep->tx_timeout_work); 3527 fec_ptp_stop(pdev); 3528 unregister_netdev(ndev); 3529 fec_enet_mii_remove(fep); 3530 if (fep->reg_phy) 3531 regulator_disable(fep->reg_phy); 3532 of_node_put(fep->phy_node); 3533 free_netdev(ndev); 3534 3535 return 0; 3536 } 3537 3538 static int __maybe_unused fec_suspend(struct device *dev) 3539 { 3540 struct net_device *ndev = dev_get_drvdata(dev); 3541 struct fec_enet_private *fep = netdev_priv(ndev); 3542 3543 rtnl_lock(); 3544 if (netif_running(ndev)) { 3545 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 3546 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 3547 phy_stop(fep->phy_dev); 3548 napi_disable(&fep->napi); 3549 netif_tx_lock_bh(ndev); 3550 netif_device_detach(ndev); 3551 netif_tx_unlock_bh(ndev); 3552 fec_stop(ndev); 3553 fec_enet_clk_enable(ndev, false); 3554 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3555 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3556 } 3557 rtnl_unlock(); 3558 3559 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3560 regulator_disable(fep->reg_phy); 3561 3562 /* SOC supply clock to phy, when clock is disabled, phy link down 3563 * SOC control phy regulator, when regulator is disabled, phy link down 3564 */ 3565 if (fep->clk_enet_out || fep->reg_phy) 3566 fep->link = 0; 3567 3568 return 0; 3569 } 3570 3571 static int __maybe_unused fec_resume(struct device *dev) 3572 { 3573 struct net_device *ndev = dev_get_drvdata(dev); 3574 struct fec_enet_private *fep = netdev_priv(ndev); 3575 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 3576 int ret; 3577 int val; 3578 3579 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 3580 ret = regulator_enable(fep->reg_phy); 3581 if (ret) 3582 return ret; 3583 } 3584 3585 rtnl_lock(); 3586 if (netif_running(ndev)) { 3587 ret = fec_enet_clk_enable(ndev, true); 3588 if (ret) { 3589 rtnl_unlock(); 3590 goto failed_clk; 3591 } 3592 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 3593 if (pdata && pdata->sleep_mode_enable) 3594 pdata->sleep_mode_enable(false); 3595 val = readl(fep->hwp + FEC_ECNTRL); 3596 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 3597 writel(val, fep->hwp + FEC_ECNTRL); 3598 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 3599 } else { 3600 pinctrl_pm_select_default_state(&fep->pdev->dev); 3601 } 3602 fec_restart(ndev); 3603 netif_tx_lock_bh(ndev); 3604 netif_device_attach(ndev); 3605 netif_tx_unlock_bh(ndev); 3606 napi_enable(&fep->napi); 3607 phy_start(fep->phy_dev); 3608 } 3609 rtnl_unlock(); 3610 3611 return 0; 3612 3613 failed_clk: 3614 if (fep->reg_phy) 3615 regulator_disable(fep->reg_phy); 3616 return ret; 3617 } 3618 3619 static int __maybe_unused fec_runtime_suspend(struct device *dev) 3620 { 3621 struct net_device *ndev = dev_get_drvdata(dev); 3622 struct fec_enet_private *fep = netdev_priv(ndev); 3623 3624 clk_disable_unprepare(fep->clk_ipg); 3625 3626 return 0; 3627 } 3628 3629 static int __maybe_unused fec_runtime_resume(struct device *dev) 3630 { 3631 struct net_device *ndev = dev_get_drvdata(dev); 3632 struct fec_enet_private *fep = netdev_priv(ndev); 3633 3634 return clk_prepare_enable(fep->clk_ipg); 3635 } 3636 3637 static const struct dev_pm_ops fec_pm_ops = { 3638 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 3639 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 3640 }; 3641 3642 static struct platform_driver fec_driver = { 3643 .driver = { 3644 .name = DRIVER_NAME, 3645 .pm = &fec_pm_ops, 3646 .of_match_table = fec_dt_ids, 3647 }, 3648 .id_table = fec_devtype, 3649 .probe = fec_probe, 3650 .remove = fec_drv_remove, 3651 }; 3652 3653 module_platform_driver(fec_driver); 3654 3655 MODULE_ALIAS("platform:"DRIVER_NAME); 3656 MODULE_LICENSE("GPL"); 3657