1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/page_pool/helpers.h> 42 #include <net/selftests.h> 43 #include <net/tso.h> 44 #include <linux/tcp.h> 45 #include <linux/udp.h> 46 #include <linux/icmp.h> 47 #include <linux/spinlock.h> 48 #include <linux/workqueue.h> 49 #include <linux/bitops.h> 50 #include <linux/io.h> 51 #include <linux/irq.h> 52 #include <linux/clk.h> 53 #include <linux/crc32.h> 54 #include <linux/platform_device.h> 55 #include <linux/mdio.h> 56 #include <linux/phy.h> 57 #include <linux/fec.h> 58 #include <linux/of.h> 59 #include <linux/of_device.h> 60 #include <linux/of_mdio.h> 61 #include <linux/of_net.h> 62 #include <linux/regulator/consumer.h> 63 #include <linux/if_vlan.h> 64 #include <linux/pinctrl/consumer.h> 65 #include <linux/gpio/consumer.h> 66 #include <linux/prefetch.h> 67 #include <linux/mfd/syscon.h> 68 #include <linux/regmap.h> 69 #include <soc/imx/cpuidle.h> 70 #include <linux/filter.h> 71 #include <linux/bpf.h> 72 #include <linux/bpf_trace.h> 73 74 #include <asm/cacheflush.h> 75 76 #include "fec.h" 77 78 static void set_multicast_list(struct net_device *ndev); 79 static void fec_enet_itr_coal_set(struct net_device *ndev); 80 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 81 int cpu, struct xdp_buff *xdp, 82 u32 dma_sync_len); 83 84 #define DRIVER_NAME "fec" 85 86 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 87 88 /* Pause frame feild and FIFO threshold */ 89 #define FEC_ENET_FCE (1 << 5) 90 #define FEC_ENET_RSEM_V 0x84 91 #define FEC_ENET_RSFL_V 16 92 #define FEC_ENET_RAEM_V 0x8 93 #define FEC_ENET_RAFL_V 0x8 94 #define FEC_ENET_OPD_V 0xFFF0 95 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 96 97 #define FEC_ENET_XDP_PASS 0 98 #define FEC_ENET_XDP_CONSUMED BIT(0) 99 #define FEC_ENET_XDP_TX BIT(1) 100 #define FEC_ENET_XDP_REDIR BIT(2) 101 102 struct fec_devinfo { 103 u32 quirks; 104 }; 105 106 static const struct fec_devinfo fec_imx25_info = { 107 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 108 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45, 109 }; 110 111 static const struct fec_devinfo fec_imx27_info = { 112 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG | 113 FEC_QUIRK_HAS_MDIO_C45, 114 }; 115 116 static const struct fec_devinfo fec_imx28_info = { 117 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 118 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 119 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 120 FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45, 121 }; 122 123 static const struct fec_devinfo fec_imx6q_info = { 124 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 125 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 126 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 127 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII | 128 FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45, 129 }; 130 131 static const struct fec_devinfo fec_mvf600_info = { 132 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC | 133 FEC_QUIRK_HAS_MDIO_C45, 134 }; 135 136 static const struct fec_devinfo fec_imx6x_info = { 137 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 138 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 139 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 140 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 141 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 142 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 143 FEC_QUIRK_HAS_MDIO_C45, 144 }; 145 146 static const struct fec_devinfo fec_imx6ul_info = { 147 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 148 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 149 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 150 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 151 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII | 152 FEC_QUIRK_HAS_MDIO_C45, 153 }; 154 155 static const struct fec_devinfo fec_imx8mq_info = { 156 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 157 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 158 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 159 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 160 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 161 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 162 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 | 163 FEC_QUIRK_HAS_MDIO_C45, 164 }; 165 166 static const struct fec_devinfo fec_imx8qm_info = { 167 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 168 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 169 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 170 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 171 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 172 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 173 FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45, 174 }; 175 176 static const struct fec_devinfo fec_s32v234_info = { 177 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 178 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 179 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 180 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 181 FEC_QUIRK_HAS_MDIO_C45, 182 }; 183 184 static struct platform_device_id fec_devtype[] = { 185 { 186 /* keep it for coldfire */ 187 .name = DRIVER_NAME, 188 .driver_data = 0, 189 }, { 190 .name = "imx25-fec", 191 .driver_data = (kernel_ulong_t)&fec_imx25_info, 192 }, { 193 .name = "imx27-fec", 194 .driver_data = (kernel_ulong_t)&fec_imx27_info, 195 }, { 196 .name = "imx28-fec", 197 .driver_data = (kernel_ulong_t)&fec_imx28_info, 198 }, { 199 .name = "imx6q-fec", 200 .driver_data = (kernel_ulong_t)&fec_imx6q_info, 201 }, { 202 .name = "mvf600-fec", 203 .driver_data = (kernel_ulong_t)&fec_mvf600_info, 204 }, { 205 .name = "imx6sx-fec", 206 .driver_data = (kernel_ulong_t)&fec_imx6x_info, 207 }, { 208 .name = "imx6ul-fec", 209 .driver_data = (kernel_ulong_t)&fec_imx6ul_info, 210 }, { 211 .name = "imx8mq-fec", 212 .driver_data = (kernel_ulong_t)&fec_imx8mq_info, 213 }, { 214 .name = "imx8qm-fec", 215 .driver_data = (kernel_ulong_t)&fec_imx8qm_info, 216 }, { 217 .name = "s32v234-fec", 218 .driver_data = (kernel_ulong_t)&fec_s32v234_info, 219 }, { 220 /* sentinel */ 221 } 222 }; 223 MODULE_DEVICE_TABLE(platform, fec_devtype); 224 225 enum imx_fec_type { 226 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 227 IMX27_FEC, /* runs on i.mx27/35/51 */ 228 IMX28_FEC, 229 IMX6Q_FEC, 230 MVF600_FEC, 231 IMX6SX_FEC, 232 IMX6UL_FEC, 233 IMX8MQ_FEC, 234 IMX8QM_FEC, 235 S32V234_FEC, 236 }; 237 238 static const struct of_device_id fec_dt_ids[] = { 239 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 240 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 241 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 242 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 243 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 244 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 245 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 246 { .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], }, 247 { .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], }, 248 { .compatible = "fsl,s32v234-fec", .data = &fec_devtype[S32V234_FEC], }, 249 { /* sentinel */ } 250 }; 251 MODULE_DEVICE_TABLE(of, fec_dt_ids); 252 253 static unsigned char macaddr[ETH_ALEN]; 254 module_param_array(macaddr, byte, NULL, 0); 255 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 256 257 #if defined(CONFIG_M5272) 258 /* 259 * Some hardware gets it MAC address out of local flash memory. 260 * if this is non-zero then assume it is the address to get MAC from. 261 */ 262 #if defined(CONFIG_NETtel) 263 #define FEC_FLASHMAC 0xf0006006 264 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 265 #define FEC_FLASHMAC 0xf0006000 266 #elif defined(CONFIG_CANCam) 267 #define FEC_FLASHMAC 0xf0020000 268 #elif defined (CONFIG_M5272C3) 269 #define FEC_FLASHMAC (0xffe04000 + 4) 270 #elif defined(CONFIG_MOD5272) 271 #define FEC_FLASHMAC 0xffc0406b 272 #else 273 #define FEC_FLASHMAC 0 274 #endif 275 #endif /* CONFIG_M5272 */ 276 277 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 278 * 279 * 2048 byte skbufs are allocated. However, alignment requirements 280 * varies between FEC variants. Worst case is 64, so round down by 64. 281 */ 282 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 283 #define PKT_MINBUF_SIZE 64 284 285 /* FEC receive acceleration */ 286 #define FEC_RACC_IPDIS (1 << 1) 287 #define FEC_RACC_PRODIS (1 << 2) 288 #define FEC_RACC_SHIFT16 BIT(7) 289 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 290 291 /* MIB Control Register */ 292 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 293 294 /* 295 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 296 * size bits. Other FEC hardware does not, so we need to take that into 297 * account when setting it. 298 */ 299 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 300 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 301 defined(CONFIG_ARM64) 302 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 303 #else 304 #define OPT_FRAME_SIZE 0 305 #endif 306 307 /* FEC MII MMFR bits definition */ 308 #define FEC_MMFR_ST (1 << 30) 309 #define FEC_MMFR_ST_C45 (0) 310 #define FEC_MMFR_OP_READ (2 << 28) 311 #define FEC_MMFR_OP_READ_C45 (3 << 28) 312 #define FEC_MMFR_OP_WRITE (1 << 28) 313 #define FEC_MMFR_OP_ADDR_WRITE (0) 314 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 315 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 316 #define FEC_MMFR_TA (2 << 16) 317 #define FEC_MMFR_DATA(v) (v & 0xffff) 318 /* FEC ECR bits definition */ 319 #define FEC_ECR_MAGICEN (1 << 2) 320 #define FEC_ECR_SLEEP (1 << 3) 321 322 #define FEC_MII_TIMEOUT 30000 /* us */ 323 324 /* Transmitter timeout */ 325 #define TX_TIMEOUT (2 * HZ) 326 327 #define FEC_PAUSE_FLAG_AUTONEG 0x1 328 #define FEC_PAUSE_FLAG_ENABLE 0x2 329 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 330 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 331 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 332 333 /* Max number of allowed TCP segments for software TSO */ 334 #define FEC_MAX_TSO_SEGS 100 335 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 336 337 #define IS_TSO_HEADER(txq, addr) \ 338 ((addr >= txq->tso_hdrs_dma) && \ 339 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 340 341 static int mii_cnt; 342 343 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 344 struct bufdesc_prop *bd) 345 { 346 return (bdp >= bd->last) ? bd->base 347 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 348 } 349 350 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 351 struct bufdesc_prop *bd) 352 { 353 return (bdp <= bd->base) ? bd->last 354 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 355 } 356 357 static int fec_enet_get_bd_index(struct bufdesc *bdp, 358 struct bufdesc_prop *bd) 359 { 360 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 361 } 362 363 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 364 { 365 int entries; 366 367 entries = (((const char *)txq->dirty_tx - 368 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 369 370 return entries >= 0 ? entries : entries + txq->bd.ring_size; 371 } 372 373 static void swap_buffer(void *bufaddr, int len) 374 { 375 int i; 376 unsigned int *buf = bufaddr; 377 378 for (i = 0; i < len; i += 4, buf++) 379 swab32s(buf); 380 } 381 382 static void fec_dump(struct net_device *ndev) 383 { 384 struct fec_enet_private *fep = netdev_priv(ndev); 385 struct bufdesc *bdp; 386 struct fec_enet_priv_tx_q *txq; 387 int index = 0; 388 389 netdev_info(ndev, "TX ring dump\n"); 390 pr_info("Nr SC addr len SKB\n"); 391 392 txq = fep->tx_queue[0]; 393 bdp = txq->bd.base; 394 395 do { 396 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 397 index, 398 bdp == txq->bd.cur ? 'S' : ' ', 399 bdp == txq->dirty_tx ? 'H' : ' ', 400 fec16_to_cpu(bdp->cbd_sc), 401 fec32_to_cpu(bdp->cbd_bufaddr), 402 fec16_to_cpu(bdp->cbd_datlen), 403 txq->tx_buf[index].buf_p); 404 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 405 index++; 406 } while (bdp != txq->bd.base); 407 } 408 409 static inline bool is_ipv4_pkt(struct sk_buff *skb) 410 { 411 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 412 } 413 414 static int 415 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 416 { 417 /* Only run for packets requiring a checksum. */ 418 if (skb->ip_summed != CHECKSUM_PARTIAL) 419 return 0; 420 421 if (unlikely(skb_cow_head(skb, 0))) 422 return -1; 423 424 if (is_ipv4_pkt(skb)) 425 ip_hdr(skb)->check = 0; 426 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 427 428 return 0; 429 } 430 431 static int 432 fec_enet_create_page_pool(struct fec_enet_private *fep, 433 struct fec_enet_priv_rx_q *rxq, int size) 434 { 435 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 436 struct page_pool_params pp_params = { 437 .order = 0, 438 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 439 .pool_size = size, 440 .nid = dev_to_node(&fep->pdev->dev), 441 .dev = &fep->pdev->dev, 442 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 443 .offset = FEC_ENET_XDP_HEADROOM, 444 .max_len = FEC_ENET_RX_FRSIZE, 445 }; 446 int err; 447 448 rxq->page_pool = page_pool_create(&pp_params); 449 if (IS_ERR(rxq->page_pool)) { 450 err = PTR_ERR(rxq->page_pool); 451 rxq->page_pool = NULL; 452 return err; 453 } 454 455 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0); 456 if (err < 0) 457 goto err_free_pp; 458 459 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 460 rxq->page_pool); 461 if (err) 462 goto err_unregister_rxq; 463 464 return 0; 465 466 err_unregister_rxq: 467 xdp_rxq_info_unreg(&rxq->xdp_rxq); 468 err_free_pp: 469 page_pool_destroy(rxq->page_pool); 470 rxq->page_pool = NULL; 471 return err; 472 } 473 474 static struct bufdesc * 475 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 476 struct sk_buff *skb, 477 struct net_device *ndev) 478 { 479 struct fec_enet_private *fep = netdev_priv(ndev); 480 struct bufdesc *bdp = txq->bd.cur; 481 struct bufdesc_ex *ebdp; 482 int nr_frags = skb_shinfo(skb)->nr_frags; 483 int frag, frag_len; 484 unsigned short status; 485 unsigned int estatus = 0; 486 skb_frag_t *this_frag; 487 unsigned int index; 488 void *bufaddr; 489 dma_addr_t addr; 490 int i; 491 492 for (frag = 0; frag < nr_frags; frag++) { 493 this_frag = &skb_shinfo(skb)->frags[frag]; 494 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 495 ebdp = (struct bufdesc_ex *)bdp; 496 497 status = fec16_to_cpu(bdp->cbd_sc); 498 status &= ~BD_ENET_TX_STATS; 499 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 500 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 501 502 /* Handle the last BD specially */ 503 if (frag == nr_frags - 1) { 504 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 505 if (fep->bufdesc_ex) { 506 estatus |= BD_ENET_TX_INT; 507 if (unlikely(skb_shinfo(skb)->tx_flags & 508 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 509 estatus |= BD_ENET_TX_TS; 510 } 511 } 512 513 if (fep->bufdesc_ex) { 514 if (fep->quirks & FEC_QUIRK_HAS_AVB) 515 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 516 if (skb->ip_summed == CHECKSUM_PARTIAL) 517 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 518 519 ebdp->cbd_bdu = 0; 520 ebdp->cbd_esc = cpu_to_fec32(estatus); 521 } 522 523 bufaddr = skb_frag_address(this_frag); 524 525 index = fec_enet_get_bd_index(bdp, &txq->bd); 526 if (((unsigned long) bufaddr) & fep->tx_align || 527 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 528 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 529 bufaddr = txq->tx_bounce[index]; 530 531 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 532 swap_buffer(bufaddr, frag_len); 533 } 534 535 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 536 DMA_TO_DEVICE); 537 if (dma_mapping_error(&fep->pdev->dev, addr)) { 538 if (net_ratelimit()) 539 netdev_err(ndev, "Tx DMA memory map failed\n"); 540 goto dma_mapping_error; 541 } 542 543 bdp->cbd_bufaddr = cpu_to_fec32(addr); 544 bdp->cbd_datlen = cpu_to_fec16(frag_len); 545 /* Make sure the updates to rest of the descriptor are 546 * performed before transferring ownership. 547 */ 548 wmb(); 549 bdp->cbd_sc = cpu_to_fec16(status); 550 } 551 552 return bdp; 553 dma_mapping_error: 554 bdp = txq->bd.cur; 555 for (i = 0; i < frag; i++) { 556 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 557 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 558 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 559 } 560 return ERR_PTR(-ENOMEM); 561 } 562 563 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 564 struct sk_buff *skb, struct net_device *ndev) 565 { 566 struct fec_enet_private *fep = netdev_priv(ndev); 567 int nr_frags = skb_shinfo(skb)->nr_frags; 568 struct bufdesc *bdp, *last_bdp; 569 void *bufaddr; 570 dma_addr_t addr; 571 unsigned short status; 572 unsigned short buflen; 573 unsigned int estatus = 0; 574 unsigned int index; 575 int entries_free; 576 577 entries_free = fec_enet_get_free_txdesc_num(txq); 578 if (entries_free < MAX_SKB_FRAGS + 1) { 579 dev_kfree_skb_any(skb); 580 if (net_ratelimit()) 581 netdev_err(ndev, "NOT enough BD for SG!\n"); 582 return NETDEV_TX_OK; 583 } 584 585 /* Protocol checksum off-load for TCP and UDP. */ 586 if (fec_enet_clear_csum(skb, ndev)) { 587 dev_kfree_skb_any(skb); 588 return NETDEV_TX_OK; 589 } 590 591 /* Fill in a Tx ring entry */ 592 bdp = txq->bd.cur; 593 last_bdp = bdp; 594 status = fec16_to_cpu(bdp->cbd_sc); 595 status &= ~BD_ENET_TX_STATS; 596 597 /* Set buffer length and buffer pointer */ 598 bufaddr = skb->data; 599 buflen = skb_headlen(skb); 600 601 index = fec_enet_get_bd_index(bdp, &txq->bd); 602 if (((unsigned long) bufaddr) & fep->tx_align || 603 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 604 memcpy(txq->tx_bounce[index], skb->data, buflen); 605 bufaddr = txq->tx_bounce[index]; 606 607 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 608 swap_buffer(bufaddr, buflen); 609 } 610 611 /* Push the data cache so the CPM does not get stale memory data. */ 612 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 613 if (dma_mapping_error(&fep->pdev->dev, addr)) { 614 dev_kfree_skb_any(skb); 615 if (net_ratelimit()) 616 netdev_err(ndev, "Tx DMA memory map failed\n"); 617 return NETDEV_TX_OK; 618 } 619 620 if (nr_frags) { 621 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 622 if (IS_ERR(last_bdp)) { 623 dma_unmap_single(&fep->pdev->dev, addr, 624 buflen, DMA_TO_DEVICE); 625 dev_kfree_skb_any(skb); 626 return NETDEV_TX_OK; 627 } 628 } else { 629 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 630 if (fep->bufdesc_ex) { 631 estatus = BD_ENET_TX_INT; 632 if (unlikely(skb_shinfo(skb)->tx_flags & 633 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 634 estatus |= BD_ENET_TX_TS; 635 } 636 } 637 bdp->cbd_bufaddr = cpu_to_fec32(addr); 638 bdp->cbd_datlen = cpu_to_fec16(buflen); 639 640 if (fep->bufdesc_ex) { 641 642 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 643 644 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 645 fep->hwts_tx_en)) 646 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 647 648 if (fep->quirks & FEC_QUIRK_HAS_AVB) 649 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 650 651 if (skb->ip_summed == CHECKSUM_PARTIAL) 652 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 653 654 ebdp->cbd_bdu = 0; 655 ebdp->cbd_esc = cpu_to_fec32(estatus); 656 } 657 658 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 659 /* Save skb pointer */ 660 txq->tx_buf[index].buf_p = skb; 661 662 /* Make sure the updates to rest of the descriptor are performed before 663 * transferring ownership. 664 */ 665 wmb(); 666 667 /* Send it on its way. Tell FEC it's ready, interrupt when done, 668 * it's the last BD of the frame, and to put the CRC on the end. 669 */ 670 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 671 bdp->cbd_sc = cpu_to_fec16(status); 672 673 /* If this was the last BD in the ring, start at the beginning again. */ 674 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 675 676 skb_tx_timestamp(skb); 677 678 /* Make sure the update to bdp is performed before txq->bd.cur. */ 679 wmb(); 680 txq->bd.cur = bdp; 681 682 /* Trigger transmission start */ 683 writel(0, txq->bd.reg_desc_active); 684 685 return 0; 686 } 687 688 static int 689 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 690 struct net_device *ndev, 691 struct bufdesc *bdp, int index, char *data, 692 int size, bool last_tcp, bool is_last) 693 { 694 struct fec_enet_private *fep = netdev_priv(ndev); 695 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 696 unsigned short status; 697 unsigned int estatus = 0; 698 dma_addr_t addr; 699 700 status = fec16_to_cpu(bdp->cbd_sc); 701 status &= ~BD_ENET_TX_STATS; 702 703 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 704 705 if (((unsigned long) data) & fep->tx_align || 706 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 707 memcpy(txq->tx_bounce[index], data, size); 708 data = txq->tx_bounce[index]; 709 710 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 711 swap_buffer(data, size); 712 } 713 714 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 715 if (dma_mapping_error(&fep->pdev->dev, addr)) { 716 dev_kfree_skb_any(skb); 717 if (net_ratelimit()) 718 netdev_err(ndev, "Tx DMA memory map failed\n"); 719 return NETDEV_TX_OK; 720 } 721 722 bdp->cbd_datlen = cpu_to_fec16(size); 723 bdp->cbd_bufaddr = cpu_to_fec32(addr); 724 725 if (fep->bufdesc_ex) { 726 if (fep->quirks & FEC_QUIRK_HAS_AVB) 727 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 728 if (skb->ip_summed == CHECKSUM_PARTIAL) 729 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 730 ebdp->cbd_bdu = 0; 731 ebdp->cbd_esc = cpu_to_fec32(estatus); 732 } 733 734 /* Handle the last BD specially */ 735 if (last_tcp) 736 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 737 if (is_last) { 738 status |= BD_ENET_TX_INTR; 739 if (fep->bufdesc_ex) 740 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 741 } 742 743 bdp->cbd_sc = cpu_to_fec16(status); 744 745 return 0; 746 } 747 748 static int 749 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 750 struct sk_buff *skb, struct net_device *ndev, 751 struct bufdesc *bdp, int index) 752 { 753 struct fec_enet_private *fep = netdev_priv(ndev); 754 int hdr_len = skb_tcp_all_headers(skb); 755 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 756 void *bufaddr; 757 unsigned long dmabuf; 758 unsigned short status; 759 unsigned int estatus = 0; 760 761 status = fec16_to_cpu(bdp->cbd_sc); 762 status &= ~BD_ENET_TX_STATS; 763 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 764 765 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 766 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 767 if (((unsigned long)bufaddr) & fep->tx_align || 768 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 769 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 770 bufaddr = txq->tx_bounce[index]; 771 772 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 773 swap_buffer(bufaddr, hdr_len); 774 775 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 776 hdr_len, DMA_TO_DEVICE); 777 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 778 dev_kfree_skb_any(skb); 779 if (net_ratelimit()) 780 netdev_err(ndev, "Tx DMA memory map failed\n"); 781 return NETDEV_TX_OK; 782 } 783 } 784 785 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 786 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 787 788 if (fep->bufdesc_ex) { 789 if (fep->quirks & FEC_QUIRK_HAS_AVB) 790 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 791 if (skb->ip_summed == CHECKSUM_PARTIAL) 792 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 793 ebdp->cbd_bdu = 0; 794 ebdp->cbd_esc = cpu_to_fec32(estatus); 795 } 796 797 bdp->cbd_sc = cpu_to_fec16(status); 798 799 return 0; 800 } 801 802 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 803 struct sk_buff *skb, 804 struct net_device *ndev) 805 { 806 struct fec_enet_private *fep = netdev_priv(ndev); 807 int hdr_len, total_len, data_left; 808 struct bufdesc *bdp = txq->bd.cur; 809 struct tso_t tso; 810 unsigned int index = 0; 811 int ret; 812 813 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 814 dev_kfree_skb_any(skb); 815 if (net_ratelimit()) 816 netdev_err(ndev, "NOT enough BD for TSO!\n"); 817 return NETDEV_TX_OK; 818 } 819 820 /* Protocol checksum off-load for TCP and UDP. */ 821 if (fec_enet_clear_csum(skb, ndev)) { 822 dev_kfree_skb_any(skb); 823 return NETDEV_TX_OK; 824 } 825 826 /* Initialize the TSO handler, and prepare the first payload */ 827 hdr_len = tso_start(skb, &tso); 828 829 total_len = skb->len - hdr_len; 830 while (total_len > 0) { 831 char *hdr; 832 833 index = fec_enet_get_bd_index(bdp, &txq->bd); 834 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 835 total_len -= data_left; 836 837 /* prepare packet headers: MAC + IP + TCP */ 838 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 839 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 840 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 841 if (ret) 842 goto err_release; 843 844 while (data_left > 0) { 845 int size; 846 847 size = min_t(int, tso.size, data_left); 848 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 849 index = fec_enet_get_bd_index(bdp, &txq->bd); 850 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 851 bdp, index, 852 tso.data, size, 853 size == data_left, 854 total_len == 0); 855 if (ret) 856 goto err_release; 857 858 data_left -= size; 859 tso_build_data(skb, &tso, size); 860 } 861 862 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 863 } 864 865 /* Save skb pointer */ 866 txq->tx_buf[index].buf_p = skb; 867 868 skb_tx_timestamp(skb); 869 txq->bd.cur = bdp; 870 871 /* Trigger transmission start */ 872 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 873 !readl(txq->bd.reg_desc_active) || 874 !readl(txq->bd.reg_desc_active) || 875 !readl(txq->bd.reg_desc_active) || 876 !readl(txq->bd.reg_desc_active)) 877 writel(0, txq->bd.reg_desc_active); 878 879 return 0; 880 881 err_release: 882 /* TODO: Release all used data descriptors for TSO */ 883 return ret; 884 } 885 886 static netdev_tx_t 887 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 888 { 889 struct fec_enet_private *fep = netdev_priv(ndev); 890 int entries_free; 891 unsigned short queue; 892 struct fec_enet_priv_tx_q *txq; 893 struct netdev_queue *nq; 894 int ret; 895 896 queue = skb_get_queue_mapping(skb); 897 txq = fep->tx_queue[queue]; 898 nq = netdev_get_tx_queue(ndev, queue); 899 900 if (skb_is_gso(skb)) 901 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 902 else 903 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 904 if (ret) 905 return ret; 906 907 entries_free = fec_enet_get_free_txdesc_num(txq); 908 if (entries_free <= txq->tx_stop_threshold) 909 netif_tx_stop_queue(nq); 910 911 return NETDEV_TX_OK; 912 } 913 914 /* Init RX & TX buffer descriptors 915 */ 916 static void fec_enet_bd_init(struct net_device *dev) 917 { 918 struct fec_enet_private *fep = netdev_priv(dev); 919 struct fec_enet_priv_tx_q *txq; 920 struct fec_enet_priv_rx_q *rxq; 921 struct bufdesc *bdp; 922 unsigned int i; 923 unsigned int q; 924 925 for (q = 0; q < fep->num_rx_queues; q++) { 926 /* Initialize the receive buffer descriptors. */ 927 rxq = fep->rx_queue[q]; 928 bdp = rxq->bd.base; 929 930 for (i = 0; i < rxq->bd.ring_size; i++) { 931 932 /* Initialize the BD for every fragment in the page. */ 933 if (bdp->cbd_bufaddr) 934 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 935 else 936 bdp->cbd_sc = cpu_to_fec16(0); 937 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 938 } 939 940 /* Set the last buffer to wrap */ 941 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 942 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 943 944 rxq->bd.cur = rxq->bd.base; 945 } 946 947 for (q = 0; q < fep->num_tx_queues; q++) { 948 /* ...and the same for transmit */ 949 txq = fep->tx_queue[q]; 950 bdp = txq->bd.base; 951 txq->bd.cur = bdp; 952 953 for (i = 0; i < txq->bd.ring_size; i++) { 954 /* Initialize the BD for every fragment in the page. */ 955 bdp->cbd_sc = cpu_to_fec16(0); 956 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 957 if (bdp->cbd_bufaddr && 958 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 959 dma_unmap_single(&fep->pdev->dev, 960 fec32_to_cpu(bdp->cbd_bufaddr), 961 fec16_to_cpu(bdp->cbd_datlen), 962 DMA_TO_DEVICE); 963 if (txq->tx_buf[i].buf_p) 964 dev_kfree_skb_any(txq->tx_buf[i].buf_p); 965 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 966 if (bdp->cbd_bufaddr) 967 dma_unmap_single(&fep->pdev->dev, 968 fec32_to_cpu(bdp->cbd_bufaddr), 969 fec16_to_cpu(bdp->cbd_datlen), 970 DMA_TO_DEVICE); 971 972 if (txq->tx_buf[i].buf_p) 973 xdp_return_frame(txq->tx_buf[i].buf_p); 974 } else { 975 struct page *page = txq->tx_buf[i].buf_p; 976 977 if (page) 978 page_pool_put_page(page->pp, page, 0, false); 979 } 980 981 txq->tx_buf[i].buf_p = NULL; 982 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 983 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 984 bdp->cbd_bufaddr = cpu_to_fec32(0); 985 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 986 } 987 988 /* Set the last buffer to wrap */ 989 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 990 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 991 txq->dirty_tx = bdp; 992 } 993 } 994 995 static void fec_enet_active_rxring(struct net_device *ndev) 996 { 997 struct fec_enet_private *fep = netdev_priv(ndev); 998 int i; 999 1000 for (i = 0; i < fep->num_rx_queues; i++) 1001 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 1002 } 1003 1004 static void fec_enet_enable_ring(struct net_device *ndev) 1005 { 1006 struct fec_enet_private *fep = netdev_priv(ndev); 1007 struct fec_enet_priv_tx_q *txq; 1008 struct fec_enet_priv_rx_q *rxq; 1009 int i; 1010 1011 for (i = 0; i < fep->num_rx_queues; i++) { 1012 rxq = fep->rx_queue[i]; 1013 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 1014 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 1015 1016 /* enable DMA1/2 */ 1017 if (i) 1018 writel(RCMR_MATCHEN | RCMR_CMP(i), 1019 fep->hwp + FEC_RCMR(i)); 1020 } 1021 1022 for (i = 0; i < fep->num_tx_queues; i++) { 1023 txq = fep->tx_queue[i]; 1024 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 1025 1026 /* enable DMA1/2 */ 1027 if (i) 1028 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 1029 fep->hwp + FEC_DMA_CFG(i)); 1030 } 1031 } 1032 1033 /* 1034 * This function is called to start or restart the FEC during a link 1035 * change, transmit timeout, or to reconfigure the FEC. The network 1036 * packet processing for this device must be stopped before this call. 1037 */ 1038 static void 1039 fec_restart(struct net_device *ndev) 1040 { 1041 struct fec_enet_private *fep = netdev_priv(ndev); 1042 u32 temp_mac[2]; 1043 u32 rcntl = OPT_FRAME_SIZE | 0x04; 1044 u32 ecntl = 0x2; /* ETHEREN */ 1045 1046 /* Whack a reset. We should wait for this. 1047 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1048 * instead of reset MAC itself. 1049 */ 1050 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 1051 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 1052 writel(0, fep->hwp + FEC_ECNTRL); 1053 } else { 1054 writel(1, fep->hwp + FEC_ECNTRL); 1055 udelay(10); 1056 } 1057 1058 /* 1059 * enet-mac reset will reset mac address registers too, 1060 * so need to reconfigure it. 1061 */ 1062 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 1063 writel((__force u32)cpu_to_be32(temp_mac[0]), 1064 fep->hwp + FEC_ADDR_LOW); 1065 writel((__force u32)cpu_to_be32(temp_mac[1]), 1066 fep->hwp + FEC_ADDR_HIGH); 1067 1068 /* Clear any outstanding interrupt, except MDIO. */ 1069 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1070 1071 fec_enet_bd_init(ndev); 1072 1073 fec_enet_enable_ring(ndev); 1074 1075 /* Enable MII mode */ 1076 if (fep->full_duplex == DUPLEX_FULL) { 1077 /* FD enable */ 1078 writel(0x04, fep->hwp + FEC_X_CNTRL); 1079 } else { 1080 /* No Rcv on Xmit */ 1081 rcntl |= 0x02; 1082 writel(0x0, fep->hwp + FEC_X_CNTRL); 1083 } 1084 1085 /* Set MII speed */ 1086 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1087 1088 #if !defined(CONFIG_M5272) 1089 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1090 u32 val = readl(fep->hwp + FEC_RACC); 1091 1092 /* align IP header */ 1093 val |= FEC_RACC_SHIFT16; 1094 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1095 /* set RX checksum */ 1096 val |= FEC_RACC_OPTIONS; 1097 else 1098 val &= ~FEC_RACC_OPTIONS; 1099 writel(val, fep->hwp + FEC_RACC); 1100 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1101 } 1102 #endif 1103 1104 /* 1105 * The phy interface and speed need to get configured 1106 * differently on enet-mac. 1107 */ 1108 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1109 /* Enable flow control and length check */ 1110 rcntl |= 0x40000000 | 0x00000020; 1111 1112 /* RGMII, RMII or MII */ 1113 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1114 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1115 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1116 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1117 rcntl |= (1 << 6); 1118 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1119 rcntl |= (1 << 8); 1120 else 1121 rcntl &= ~(1 << 8); 1122 1123 /* 1G, 100M or 10M */ 1124 if (ndev->phydev) { 1125 if (ndev->phydev->speed == SPEED_1000) 1126 ecntl |= (1 << 5); 1127 else if (ndev->phydev->speed == SPEED_100) 1128 rcntl &= ~(1 << 9); 1129 else 1130 rcntl |= (1 << 9); 1131 } 1132 } else { 1133 #ifdef FEC_MIIGSK_ENR 1134 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1135 u32 cfgr; 1136 /* disable the gasket and wait */ 1137 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1138 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1139 udelay(1); 1140 1141 /* 1142 * configure the gasket: 1143 * RMII, 50 MHz, no loopback, no echo 1144 * MII, 25 MHz, no loopback, no echo 1145 */ 1146 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1147 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1148 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1149 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1150 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1151 1152 /* re-enable the gasket */ 1153 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1154 } 1155 #endif 1156 } 1157 1158 #if !defined(CONFIG_M5272) 1159 /* enable pause frame*/ 1160 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1161 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1162 ndev->phydev && ndev->phydev->pause)) { 1163 rcntl |= FEC_ENET_FCE; 1164 1165 /* set FIFO threshold parameter to reduce overrun */ 1166 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1167 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1168 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1169 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1170 1171 /* OPD */ 1172 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1173 } else { 1174 rcntl &= ~FEC_ENET_FCE; 1175 } 1176 #endif /* !defined(CONFIG_M5272) */ 1177 1178 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1179 1180 /* Setup multicast filter. */ 1181 set_multicast_list(ndev); 1182 #ifndef CONFIG_M5272 1183 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1184 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1185 #endif 1186 1187 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1188 /* enable ENET endian swap */ 1189 ecntl |= (1 << 8); 1190 /* enable ENET store and forward mode */ 1191 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1192 } 1193 1194 if (fep->bufdesc_ex) 1195 ecntl |= (1 << 4); 1196 1197 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1198 fep->rgmii_txc_dly) 1199 ecntl |= FEC_ENET_TXC_DLY; 1200 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1201 fep->rgmii_rxc_dly) 1202 ecntl |= FEC_ENET_RXC_DLY; 1203 1204 #ifndef CONFIG_M5272 1205 /* Enable the MIB statistic event counters */ 1206 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1207 #endif 1208 1209 /* And last, enable the transmit and receive processing */ 1210 writel(ecntl, fep->hwp + FEC_ECNTRL); 1211 fec_enet_active_rxring(ndev); 1212 1213 if (fep->bufdesc_ex) 1214 fec_ptp_start_cyclecounter(ndev); 1215 1216 /* Enable interrupts we wish to service */ 1217 if (fep->link) 1218 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1219 else 1220 writel(0, fep->hwp + FEC_IMASK); 1221 1222 /* Init the interrupt coalescing */ 1223 if (fep->quirks & FEC_QUIRK_HAS_COALESCE) 1224 fec_enet_itr_coal_set(ndev); 1225 } 1226 1227 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep) 1228 { 1229 if (!(of_machine_is_compatible("fsl,imx8qm") || 1230 of_machine_is_compatible("fsl,imx8qxp") || 1231 of_machine_is_compatible("fsl,imx8dxl"))) 1232 return 0; 1233 1234 return imx_scu_get_handle(&fep->ipc_handle); 1235 } 1236 1237 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled) 1238 { 1239 struct device_node *np = fep->pdev->dev.of_node; 1240 u32 rsrc_id, val; 1241 int idx; 1242 1243 if (!np || !fep->ipc_handle) 1244 return; 1245 1246 idx = of_alias_get_id(np, "ethernet"); 1247 if (idx < 0) 1248 idx = 0; 1249 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0; 1250 1251 val = enabled ? 1 : 0; 1252 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val); 1253 } 1254 1255 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1256 { 1257 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1258 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1259 1260 if (stop_gpr->gpr) { 1261 if (enabled) 1262 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1263 BIT(stop_gpr->bit), 1264 BIT(stop_gpr->bit)); 1265 else 1266 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1267 BIT(stop_gpr->bit), 0); 1268 } else if (pdata && pdata->sleep_mode_enable) { 1269 pdata->sleep_mode_enable(enabled); 1270 } else { 1271 fec_enet_ipg_stop_set(fep, enabled); 1272 } 1273 } 1274 1275 static void fec_irqs_disable(struct net_device *ndev) 1276 { 1277 struct fec_enet_private *fep = netdev_priv(ndev); 1278 1279 writel(0, fep->hwp + FEC_IMASK); 1280 } 1281 1282 static void fec_irqs_disable_except_wakeup(struct net_device *ndev) 1283 { 1284 struct fec_enet_private *fep = netdev_priv(ndev); 1285 1286 writel(0, fep->hwp + FEC_IMASK); 1287 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1288 } 1289 1290 static void 1291 fec_stop(struct net_device *ndev) 1292 { 1293 struct fec_enet_private *fep = netdev_priv(ndev); 1294 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1295 u32 val; 1296 1297 /* We cannot expect a graceful transmit stop without link !!! */ 1298 if (fep->link) { 1299 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1300 udelay(10); 1301 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1302 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1303 } 1304 1305 /* Whack a reset. We should wait for this. 1306 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1307 * instead of reset MAC itself. 1308 */ 1309 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1310 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 1311 writel(0, fep->hwp + FEC_ECNTRL); 1312 } else { 1313 writel(1, fep->hwp + FEC_ECNTRL); 1314 udelay(10); 1315 } 1316 } else { 1317 val = readl(fep->hwp + FEC_ECNTRL); 1318 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1319 writel(val, fep->hwp + FEC_ECNTRL); 1320 } 1321 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1322 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1323 1324 /* We have to keep ENET enabled to have MII interrupt stay working */ 1325 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1326 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1327 writel(2, fep->hwp + FEC_ECNTRL); 1328 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1329 } 1330 } 1331 1332 1333 static void 1334 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1335 { 1336 struct fec_enet_private *fep = netdev_priv(ndev); 1337 1338 fec_dump(ndev); 1339 1340 ndev->stats.tx_errors++; 1341 1342 schedule_work(&fep->tx_timeout_work); 1343 } 1344 1345 static void fec_enet_timeout_work(struct work_struct *work) 1346 { 1347 struct fec_enet_private *fep = 1348 container_of(work, struct fec_enet_private, tx_timeout_work); 1349 struct net_device *ndev = fep->netdev; 1350 1351 rtnl_lock(); 1352 if (netif_device_present(ndev) || netif_running(ndev)) { 1353 napi_disable(&fep->napi); 1354 netif_tx_lock_bh(ndev); 1355 fec_restart(ndev); 1356 netif_tx_wake_all_queues(ndev); 1357 netif_tx_unlock_bh(ndev); 1358 napi_enable(&fep->napi); 1359 } 1360 rtnl_unlock(); 1361 } 1362 1363 static void 1364 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1365 struct skb_shared_hwtstamps *hwtstamps) 1366 { 1367 unsigned long flags; 1368 u64 ns; 1369 1370 spin_lock_irqsave(&fep->tmreg_lock, flags); 1371 ns = timecounter_cyc2time(&fep->tc, ts); 1372 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1373 1374 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1375 hwtstamps->hwtstamp = ns_to_ktime(ns); 1376 } 1377 1378 static void 1379 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget) 1380 { 1381 struct fec_enet_private *fep; 1382 struct xdp_frame *xdpf; 1383 struct bufdesc *bdp; 1384 unsigned short status; 1385 struct sk_buff *skb; 1386 struct fec_enet_priv_tx_q *txq; 1387 struct netdev_queue *nq; 1388 int index = 0; 1389 int entries_free; 1390 struct page *page; 1391 int frame_len; 1392 1393 fep = netdev_priv(ndev); 1394 1395 txq = fep->tx_queue[queue_id]; 1396 /* get next bdp of dirty_tx */ 1397 nq = netdev_get_tx_queue(ndev, queue_id); 1398 bdp = txq->dirty_tx; 1399 1400 /* get next bdp of dirty_tx */ 1401 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1402 1403 while (bdp != READ_ONCE(txq->bd.cur)) { 1404 /* Order the load of bd.cur and cbd_sc */ 1405 rmb(); 1406 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1407 if (status & BD_ENET_TX_READY) 1408 break; 1409 1410 index = fec_enet_get_bd_index(bdp, &txq->bd); 1411 1412 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1413 skb = txq->tx_buf[index].buf_p; 1414 if (bdp->cbd_bufaddr && 1415 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1416 dma_unmap_single(&fep->pdev->dev, 1417 fec32_to_cpu(bdp->cbd_bufaddr), 1418 fec16_to_cpu(bdp->cbd_datlen), 1419 DMA_TO_DEVICE); 1420 bdp->cbd_bufaddr = cpu_to_fec32(0); 1421 if (!skb) 1422 goto tx_buf_done; 1423 } else { 1424 /* Tx processing cannot call any XDP (or page pool) APIs if 1425 * the "budget" is 0. Because NAPI is called with budget of 1426 * 0 (such as netpoll) indicates we may be in an IRQ context, 1427 * however, we can't use the page pool from IRQ context. 1428 */ 1429 if (unlikely(!budget)) 1430 break; 1431 1432 if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1433 xdpf = txq->tx_buf[index].buf_p; 1434 if (bdp->cbd_bufaddr) 1435 dma_unmap_single(&fep->pdev->dev, 1436 fec32_to_cpu(bdp->cbd_bufaddr), 1437 fec16_to_cpu(bdp->cbd_datlen), 1438 DMA_TO_DEVICE); 1439 } else { 1440 page = txq->tx_buf[index].buf_p; 1441 } 1442 1443 bdp->cbd_bufaddr = cpu_to_fec32(0); 1444 if (unlikely(!txq->tx_buf[index].buf_p)) { 1445 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1446 goto tx_buf_done; 1447 } 1448 1449 frame_len = fec16_to_cpu(bdp->cbd_datlen); 1450 } 1451 1452 /* Check for errors. */ 1453 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1454 BD_ENET_TX_RL | BD_ENET_TX_UN | 1455 BD_ENET_TX_CSL)) { 1456 ndev->stats.tx_errors++; 1457 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1458 ndev->stats.tx_heartbeat_errors++; 1459 if (status & BD_ENET_TX_LC) /* Late collision */ 1460 ndev->stats.tx_window_errors++; 1461 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1462 ndev->stats.tx_aborted_errors++; 1463 if (status & BD_ENET_TX_UN) /* Underrun */ 1464 ndev->stats.tx_fifo_errors++; 1465 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1466 ndev->stats.tx_carrier_errors++; 1467 } else { 1468 ndev->stats.tx_packets++; 1469 1470 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) 1471 ndev->stats.tx_bytes += skb->len; 1472 else 1473 ndev->stats.tx_bytes += frame_len; 1474 } 1475 1476 /* Deferred means some collisions occurred during transmit, 1477 * but we eventually sent the packet OK. 1478 */ 1479 if (status & BD_ENET_TX_DEF) 1480 ndev->stats.collisions++; 1481 1482 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1483 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1484 * are to time stamp the packet, so we still need to check time 1485 * stamping enabled flag. 1486 */ 1487 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1488 fep->hwts_tx_en) && fep->bufdesc_ex) { 1489 struct skb_shared_hwtstamps shhwtstamps; 1490 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1491 1492 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1493 skb_tstamp_tx(skb, &shhwtstamps); 1494 } 1495 1496 /* Free the sk buffer associated with this last transmit */ 1497 napi_consume_skb(skb, budget); 1498 } else if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1499 xdp_return_frame_rx_napi(xdpf); 1500 } else { /* recycle pages of XDP_TX frames */ 1501 /* The dma_sync_size = 0 as XDP_TX has already synced DMA for_device */ 1502 page_pool_put_page(page->pp, page, 0, true); 1503 } 1504 1505 txq->tx_buf[index].buf_p = NULL; 1506 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1507 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1508 1509 tx_buf_done: 1510 /* Make sure the update to bdp and tx_buf are performed 1511 * before dirty_tx 1512 */ 1513 wmb(); 1514 txq->dirty_tx = bdp; 1515 1516 /* Update pointer to next buffer descriptor to be transmitted */ 1517 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1518 1519 /* Since we have freed up a buffer, the ring is no longer full 1520 */ 1521 if (netif_tx_queue_stopped(nq)) { 1522 entries_free = fec_enet_get_free_txdesc_num(txq); 1523 if (entries_free >= txq->tx_wake_threshold) 1524 netif_tx_wake_queue(nq); 1525 } 1526 } 1527 1528 /* ERR006358: Keep the transmitter going */ 1529 if (bdp != txq->bd.cur && 1530 readl(txq->bd.reg_desc_active) == 0) 1531 writel(0, txq->bd.reg_desc_active); 1532 } 1533 1534 static void fec_enet_tx(struct net_device *ndev, int budget) 1535 { 1536 struct fec_enet_private *fep = netdev_priv(ndev); 1537 int i; 1538 1539 /* Make sure that AVB queues are processed first. */ 1540 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1541 fec_enet_tx_queue(ndev, i, budget); 1542 } 1543 1544 static void fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq, 1545 struct bufdesc *bdp, int index) 1546 { 1547 struct page *new_page; 1548 dma_addr_t phys_addr; 1549 1550 new_page = page_pool_dev_alloc_pages(rxq->page_pool); 1551 WARN_ON(!new_page); 1552 rxq->rx_skb_info[index].page = new_page; 1553 1554 rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM; 1555 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM; 1556 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 1557 } 1558 1559 static u32 1560 fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog, 1561 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int cpu) 1562 { 1563 unsigned int sync, len = xdp->data_end - xdp->data; 1564 u32 ret = FEC_ENET_XDP_PASS; 1565 struct page *page; 1566 int err; 1567 u32 act; 1568 1569 act = bpf_prog_run_xdp(prog, xdp); 1570 1571 /* Due xdp_adjust_tail and xdp_adjust_head: DMA sync for_device cover 1572 * max len CPU touch 1573 */ 1574 sync = xdp->data_end - xdp->data; 1575 sync = max(sync, len); 1576 1577 switch (act) { 1578 case XDP_PASS: 1579 rxq->stats[RX_XDP_PASS]++; 1580 ret = FEC_ENET_XDP_PASS; 1581 break; 1582 1583 case XDP_REDIRECT: 1584 rxq->stats[RX_XDP_REDIRECT]++; 1585 err = xdp_do_redirect(fep->netdev, xdp, prog); 1586 if (unlikely(err)) 1587 goto xdp_err; 1588 1589 ret = FEC_ENET_XDP_REDIR; 1590 break; 1591 1592 case XDP_TX: 1593 rxq->stats[RX_XDP_TX]++; 1594 err = fec_enet_xdp_tx_xmit(fep, cpu, xdp, sync); 1595 if (unlikely(err)) { 1596 rxq->stats[RX_XDP_TX_ERRORS]++; 1597 goto xdp_err; 1598 } 1599 1600 ret = FEC_ENET_XDP_TX; 1601 break; 1602 1603 default: 1604 bpf_warn_invalid_xdp_action(fep->netdev, prog, act); 1605 fallthrough; 1606 1607 case XDP_ABORTED: 1608 fallthrough; /* handle aborts by dropping packet */ 1609 1610 case XDP_DROP: 1611 rxq->stats[RX_XDP_DROP]++; 1612 xdp_err: 1613 ret = FEC_ENET_XDP_CONSUMED; 1614 page = virt_to_head_page(xdp->data); 1615 page_pool_put_page(rxq->page_pool, page, sync, true); 1616 if (act != XDP_DROP) 1617 trace_xdp_exception(fep->netdev, prog, act); 1618 break; 1619 } 1620 1621 return ret; 1622 } 1623 1624 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1625 * When we update through the ring, if the next incoming buffer has 1626 * not been given to the system, we just set the empty indicator, 1627 * effectively tossing the packet. 1628 */ 1629 static int 1630 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1631 { 1632 struct fec_enet_private *fep = netdev_priv(ndev); 1633 struct fec_enet_priv_rx_q *rxq; 1634 struct bufdesc *bdp; 1635 unsigned short status; 1636 struct sk_buff *skb; 1637 ushort pkt_len; 1638 __u8 *data; 1639 int pkt_received = 0; 1640 struct bufdesc_ex *ebdp = NULL; 1641 bool vlan_packet_rcvd = false; 1642 u16 vlan_tag; 1643 int index = 0; 1644 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1645 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 1646 u32 ret, xdp_result = FEC_ENET_XDP_PASS; 1647 u32 data_start = FEC_ENET_XDP_HEADROOM; 1648 int cpu = smp_processor_id(); 1649 struct xdp_buff xdp; 1650 struct page *page; 1651 u32 sub_len = 4; 1652 1653 #if !defined(CONFIG_M5272) 1654 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of 1655 * FEC_RACC_SHIFT16 is set by default in the probe function. 1656 */ 1657 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1658 data_start += 2; 1659 sub_len += 2; 1660 } 1661 #endif 1662 1663 #ifdef CONFIG_M532x 1664 flush_cache_all(); 1665 #endif 1666 rxq = fep->rx_queue[queue_id]; 1667 1668 /* First, grab all of the stats for the incoming packet. 1669 * These get messed up if we get called due to a busy condition. 1670 */ 1671 bdp = rxq->bd.cur; 1672 xdp_init_buff(&xdp, PAGE_SIZE, &rxq->xdp_rxq); 1673 1674 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1675 1676 if (pkt_received >= budget) 1677 break; 1678 pkt_received++; 1679 1680 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); 1681 1682 /* Check for errors. */ 1683 status ^= BD_ENET_RX_LAST; 1684 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1685 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1686 BD_ENET_RX_CL)) { 1687 ndev->stats.rx_errors++; 1688 if (status & BD_ENET_RX_OV) { 1689 /* FIFO overrun */ 1690 ndev->stats.rx_fifo_errors++; 1691 goto rx_processing_done; 1692 } 1693 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1694 | BD_ENET_RX_LAST)) { 1695 /* Frame too long or too short. */ 1696 ndev->stats.rx_length_errors++; 1697 if (status & BD_ENET_RX_LAST) 1698 netdev_err(ndev, "rcv is not +last\n"); 1699 } 1700 if (status & BD_ENET_RX_CR) /* CRC Error */ 1701 ndev->stats.rx_crc_errors++; 1702 /* Report late collisions as a frame error. */ 1703 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1704 ndev->stats.rx_frame_errors++; 1705 goto rx_processing_done; 1706 } 1707 1708 /* Process the incoming frame. */ 1709 ndev->stats.rx_packets++; 1710 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1711 ndev->stats.rx_bytes += pkt_len; 1712 1713 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1714 page = rxq->rx_skb_info[index].page; 1715 dma_sync_single_for_cpu(&fep->pdev->dev, 1716 fec32_to_cpu(bdp->cbd_bufaddr), 1717 pkt_len, 1718 DMA_FROM_DEVICE); 1719 prefetch(page_address(page)); 1720 fec_enet_update_cbd(rxq, bdp, index); 1721 1722 if (xdp_prog) { 1723 xdp_buff_clear_frags_flag(&xdp); 1724 /* subtract 16bit shift and FCS */ 1725 xdp_prepare_buff(&xdp, page_address(page), 1726 data_start, pkt_len - sub_len, false); 1727 ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, cpu); 1728 xdp_result |= ret; 1729 if (ret != FEC_ENET_XDP_PASS) 1730 goto rx_processing_done; 1731 } 1732 1733 /* The packet length includes FCS, but we don't want to 1734 * include that when passing upstream as it messes up 1735 * bridging applications. 1736 */ 1737 skb = build_skb(page_address(page), PAGE_SIZE); 1738 if (unlikely(!skb)) { 1739 page_pool_recycle_direct(rxq->page_pool, page); 1740 ndev->stats.rx_dropped++; 1741 1742 netdev_err_once(ndev, "build_skb failed!\n"); 1743 goto rx_processing_done; 1744 } 1745 1746 skb_reserve(skb, data_start); 1747 skb_put(skb, pkt_len - sub_len); 1748 skb_mark_for_recycle(skb); 1749 1750 if (unlikely(need_swap)) { 1751 data = page_address(page) + FEC_ENET_XDP_HEADROOM; 1752 swap_buffer(data, pkt_len); 1753 } 1754 data = skb->data; 1755 1756 /* Extract the enhanced buffer descriptor */ 1757 ebdp = NULL; 1758 if (fep->bufdesc_ex) 1759 ebdp = (struct bufdesc_ex *)bdp; 1760 1761 /* If this is a VLAN packet remove the VLAN Tag */ 1762 vlan_packet_rcvd = false; 1763 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1764 fep->bufdesc_ex && 1765 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1766 /* Push and remove the vlan tag */ 1767 struct vlan_hdr *vlan_header = 1768 (struct vlan_hdr *) (data + ETH_HLEN); 1769 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1770 1771 vlan_packet_rcvd = true; 1772 1773 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1774 skb_pull(skb, VLAN_HLEN); 1775 } 1776 1777 skb->protocol = eth_type_trans(skb, ndev); 1778 1779 /* Get receive timestamp from the skb */ 1780 if (fep->hwts_rx_en && fep->bufdesc_ex) 1781 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1782 skb_hwtstamps(skb)); 1783 1784 if (fep->bufdesc_ex && 1785 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1786 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1787 /* don't check it */ 1788 skb->ip_summed = CHECKSUM_UNNECESSARY; 1789 } else { 1790 skb_checksum_none_assert(skb); 1791 } 1792 } 1793 1794 /* Handle received VLAN packets */ 1795 if (vlan_packet_rcvd) 1796 __vlan_hwaccel_put_tag(skb, 1797 htons(ETH_P_8021Q), 1798 vlan_tag); 1799 1800 skb_record_rx_queue(skb, queue_id); 1801 napi_gro_receive(&fep->napi, skb); 1802 1803 rx_processing_done: 1804 /* Clear the status flags for this buffer */ 1805 status &= ~BD_ENET_RX_STATS; 1806 1807 /* Mark the buffer empty */ 1808 status |= BD_ENET_RX_EMPTY; 1809 1810 if (fep->bufdesc_ex) { 1811 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1812 1813 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1814 ebdp->cbd_prot = 0; 1815 ebdp->cbd_bdu = 0; 1816 } 1817 /* Make sure the updates to rest of the descriptor are 1818 * performed before transferring ownership. 1819 */ 1820 wmb(); 1821 bdp->cbd_sc = cpu_to_fec16(status); 1822 1823 /* Update BD pointer to next entry */ 1824 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1825 1826 /* Doing this here will keep the FEC running while we process 1827 * incoming frames. On a heavily loaded network, we should be 1828 * able to keep up at the expense of system resources. 1829 */ 1830 writel(0, rxq->bd.reg_desc_active); 1831 } 1832 rxq->bd.cur = bdp; 1833 1834 if (xdp_result & FEC_ENET_XDP_REDIR) 1835 xdp_do_flush_map(); 1836 1837 return pkt_received; 1838 } 1839 1840 static int fec_enet_rx(struct net_device *ndev, int budget) 1841 { 1842 struct fec_enet_private *fep = netdev_priv(ndev); 1843 int i, done = 0; 1844 1845 /* Make sure that AVB queues are processed first. */ 1846 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1847 done += fec_enet_rx_queue(ndev, budget - done, i); 1848 1849 return done; 1850 } 1851 1852 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1853 { 1854 uint int_events; 1855 1856 int_events = readl(fep->hwp + FEC_IEVENT); 1857 1858 /* Don't clear MDIO events, we poll for those */ 1859 int_events &= ~FEC_ENET_MII; 1860 1861 writel(int_events, fep->hwp + FEC_IEVENT); 1862 1863 return int_events != 0; 1864 } 1865 1866 static irqreturn_t 1867 fec_enet_interrupt(int irq, void *dev_id) 1868 { 1869 struct net_device *ndev = dev_id; 1870 struct fec_enet_private *fep = netdev_priv(ndev); 1871 irqreturn_t ret = IRQ_NONE; 1872 1873 if (fec_enet_collect_events(fep) && fep->link) { 1874 ret = IRQ_HANDLED; 1875 1876 if (napi_schedule_prep(&fep->napi)) { 1877 /* Disable interrupts */ 1878 writel(0, fep->hwp + FEC_IMASK); 1879 __napi_schedule(&fep->napi); 1880 } 1881 } 1882 1883 return ret; 1884 } 1885 1886 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1887 { 1888 struct net_device *ndev = napi->dev; 1889 struct fec_enet_private *fep = netdev_priv(ndev); 1890 int done = 0; 1891 1892 do { 1893 done += fec_enet_rx(ndev, budget - done); 1894 fec_enet_tx(ndev, budget); 1895 } while ((done < budget) && fec_enet_collect_events(fep)); 1896 1897 if (done < budget) { 1898 napi_complete_done(napi, done); 1899 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1900 } 1901 1902 return done; 1903 } 1904 1905 /* ------------------------------------------------------------------------- */ 1906 static int fec_get_mac(struct net_device *ndev) 1907 { 1908 struct fec_enet_private *fep = netdev_priv(ndev); 1909 unsigned char *iap, tmpaddr[ETH_ALEN]; 1910 int ret; 1911 1912 /* 1913 * try to get mac address in following order: 1914 * 1915 * 1) module parameter via kernel command line in form 1916 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1917 */ 1918 iap = macaddr; 1919 1920 /* 1921 * 2) from device tree data 1922 */ 1923 if (!is_valid_ether_addr(iap)) { 1924 struct device_node *np = fep->pdev->dev.of_node; 1925 if (np) { 1926 ret = of_get_mac_address(np, tmpaddr); 1927 if (!ret) 1928 iap = tmpaddr; 1929 else if (ret == -EPROBE_DEFER) 1930 return ret; 1931 } 1932 } 1933 1934 /* 1935 * 3) from flash or fuse (via platform data) 1936 */ 1937 if (!is_valid_ether_addr(iap)) { 1938 #ifdef CONFIG_M5272 1939 if (FEC_FLASHMAC) 1940 iap = (unsigned char *)FEC_FLASHMAC; 1941 #else 1942 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1943 1944 if (pdata) 1945 iap = (unsigned char *)&pdata->mac; 1946 #endif 1947 } 1948 1949 /* 1950 * 4) FEC mac registers set by bootloader 1951 */ 1952 if (!is_valid_ether_addr(iap)) { 1953 *((__be32 *) &tmpaddr[0]) = 1954 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1955 *((__be16 *) &tmpaddr[4]) = 1956 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1957 iap = &tmpaddr[0]; 1958 } 1959 1960 /* 1961 * 5) random mac address 1962 */ 1963 if (!is_valid_ether_addr(iap)) { 1964 /* Report it and use a random ethernet address instead */ 1965 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1966 eth_hw_addr_random(ndev); 1967 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1968 ndev->dev_addr); 1969 return 0; 1970 } 1971 1972 /* Adjust MAC if using macaddr */ 1973 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); 1974 1975 return 0; 1976 } 1977 1978 /* ------------------------------------------------------------------------- */ 1979 1980 /* 1981 * Phy section 1982 */ 1983 static void fec_enet_adjust_link(struct net_device *ndev) 1984 { 1985 struct fec_enet_private *fep = netdev_priv(ndev); 1986 struct phy_device *phy_dev = ndev->phydev; 1987 int status_change = 0; 1988 1989 /* 1990 * If the netdev is down, or is going down, we're not interested 1991 * in link state events, so just mark our idea of the link as down 1992 * and ignore the event. 1993 */ 1994 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1995 fep->link = 0; 1996 } else if (phy_dev->link) { 1997 if (!fep->link) { 1998 fep->link = phy_dev->link; 1999 status_change = 1; 2000 } 2001 2002 if (fep->full_duplex != phy_dev->duplex) { 2003 fep->full_duplex = phy_dev->duplex; 2004 status_change = 1; 2005 } 2006 2007 if (phy_dev->speed != fep->speed) { 2008 fep->speed = phy_dev->speed; 2009 status_change = 1; 2010 } 2011 2012 /* if any of the above changed restart the FEC */ 2013 if (status_change) { 2014 napi_disable(&fep->napi); 2015 netif_tx_lock_bh(ndev); 2016 fec_restart(ndev); 2017 netif_tx_wake_all_queues(ndev); 2018 netif_tx_unlock_bh(ndev); 2019 napi_enable(&fep->napi); 2020 } 2021 } else { 2022 if (fep->link) { 2023 napi_disable(&fep->napi); 2024 netif_tx_lock_bh(ndev); 2025 fec_stop(ndev); 2026 netif_tx_unlock_bh(ndev); 2027 napi_enable(&fep->napi); 2028 fep->link = phy_dev->link; 2029 status_change = 1; 2030 } 2031 } 2032 2033 if (status_change) 2034 phy_print_status(phy_dev); 2035 } 2036 2037 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 2038 { 2039 uint ievent; 2040 int ret; 2041 2042 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 2043 ievent & FEC_ENET_MII, 2, 30000); 2044 2045 if (!ret) 2046 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2047 2048 return ret; 2049 } 2050 2051 static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) 2052 { 2053 struct fec_enet_private *fep = bus->priv; 2054 struct device *dev = &fep->pdev->dev; 2055 int ret = 0, frame_start, frame_addr, frame_op; 2056 2057 ret = pm_runtime_resume_and_get(dev); 2058 if (ret < 0) 2059 return ret; 2060 2061 /* C22 read */ 2062 frame_op = FEC_MMFR_OP_READ; 2063 frame_start = FEC_MMFR_ST; 2064 frame_addr = regnum; 2065 2066 /* start a read op */ 2067 writel(frame_start | frame_op | 2068 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2069 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2070 2071 /* wait for end of transfer */ 2072 ret = fec_enet_mdio_wait(fep); 2073 if (ret) { 2074 netdev_err(fep->netdev, "MDIO read timeout\n"); 2075 goto out; 2076 } 2077 2078 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2079 2080 out: 2081 pm_runtime_mark_last_busy(dev); 2082 pm_runtime_put_autosuspend(dev); 2083 2084 return ret; 2085 } 2086 2087 static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id, 2088 int devad, int regnum) 2089 { 2090 struct fec_enet_private *fep = bus->priv; 2091 struct device *dev = &fep->pdev->dev; 2092 int ret = 0, frame_start, frame_op; 2093 2094 ret = pm_runtime_resume_and_get(dev); 2095 if (ret < 0) 2096 return ret; 2097 2098 frame_start = FEC_MMFR_ST_C45; 2099 2100 /* write address */ 2101 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2102 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2103 FEC_MMFR_TA | (regnum & 0xFFFF), 2104 fep->hwp + FEC_MII_DATA); 2105 2106 /* wait for end of transfer */ 2107 ret = fec_enet_mdio_wait(fep); 2108 if (ret) { 2109 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2110 goto out; 2111 } 2112 2113 frame_op = FEC_MMFR_OP_READ_C45; 2114 2115 /* start a read op */ 2116 writel(frame_start | frame_op | 2117 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2118 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2119 2120 /* wait for end of transfer */ 2121 ret = fec_enet_mdio_wait(fep); 2122 if (ret) { 2123 netdev_err(fep->netdev, "MDIO read timeout\n"); 2124 goto out; 2125 } 2126 2127 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2128 2129 out: 2130 pm_runtime_mark_last_busy(dev); 2131 pm_runtime_put_autosuspend(dev); 2132 2133 return ret; 2134 } 2135 2136 static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, 2137 u16 value) 2138 { 2139 struct fec_enet_private *fep = bus->priv; 2140 struct device *dev = &fep->pdev->dev; 2141 int ret, frame_start, frame_addr; 2142 2143 ret = pm_runtime_resume_and_get(dev); 2144 if (ret < 0) 2145 return ret; 2146 2147 /* C22 write */ 2148 frame_start = FEC_MMFR_ST; 2149 frame_addr = regnum; 2150 2151 /* start a write op */ 2152 writel(frame_start | FEC_MMFR_OP_WRITE | 2153 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2154 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2155 fep->hwp + FEC_MII_DATA); 2156 2157 /* wait for end of transfer */ 2158 ret = fec_enet_mdio_wait(fep); 2159 if (ret) 2160 netdev_err(fep->netdev, "MDIO write timeout\n"); 2161 2162 pm_runtime_mark_last_busy(dev); 2163 pm_runtime_put_autosuspend(dev); 2164 2165 return ret; 2166 } 2167 2168 static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id, 2169 int devad, int regnum, u16 value) 2170 { 2171 struct fec_enet_private *fep = bus->priv; 2172 struct device *dev = &fep->pdev->dev; 2173 int ret, frame_start; 2174 2175 ret = pm_runtime_resume_and_get(dev); 2176 if (ret < 0) 2177 return ret; 2178 2179 frame_start = FEC_MMFR_ST_C45; 2180 2181 /* write address */ 2182 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2183 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2184 FEC_MMFR_TA | (regnum & 0xFFFF), 2185 fep->hwp + FEC_MII_DATA); 2186 2187 /* wait for end of transfer */ 2188 ret = fec_enet_mdio_wait(fep); 2189 if (ret) { 2190 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2191 goto out; 2192 } 2193 2194 /* start a write op */ 2195 writel(frame_start | FEC_MMFR_OP_WRITE | 2196 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2197 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2198 fep->hwp + FEC_MII_DATA); 2199 2200 /* wait for end of transfer */ 2201 ret = fec_enet_mdio_wait(fep); 2202 if (ret) 2203 netdev_err(fep->netdev, "MDIO write timeout\n"); 2204 2205 out: 2206 pm_runtime_mark_last_busy(dev); 2207 pm_runtime_put_autosuspend(dev); 2208 2209 return ret; 2210 } 2211 2212 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 2213 { 2214 struct fec_enet_private *fep = netdev_priv(ndev); 2215 struct phy_device *phy_dev = ndev->phydev; 2216 2217 if (phy_dev) { 2218 phy_reset_after_clk_enable(phy_dev); 2219 } else if (fep->phy_node) { 2220 /* 2221 * If the PHY still is not bound to the MAC, but there is 2222 * OF PHY node and a matching PHY device instance already, 2223 * use the OF PHY node to obtain the PHY device instance, 2224 * and then use that PHY device instance when triggering 2225 * the PHY reset. 2226 */ 2227 phy_dev = of_phy_find_device(fep->phy_node); 2228 phy_reset_after_clk_enable(phy_dev); 2229 put_device(&phy_dev->mdio.dev); 2230 } 2231 } 2232 2233 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 2234 { 2235 struct fec_enet_private *fep = netdev_priv(ndev); 2236 int ret; 2237 2238 if (enable) { 2239 ret = clk_prepare_enable(fep->clk_enet_out); 2240 if (ret) 2241 return ret; 2242 2243 if (fep->clk_ptp) { 2244 mutex_lock(&fep->ptp_clk_mutex); 2245 ret = clk_prepare_enable(fep->clk_ptp); 2246 if (ret) { 2247 mutex_unlock(&fep->ptp_clk_mutex); 2248 goto failed_clk_ptp; 2249 } else { 2250 fep->ptp_clk_on = true; 2251 } 2252 mutex_unlock(&fep->ptp_clk_mutex); 2253 } 2254 2255 ret = clk_prepare_enable(fep->clk_ref); 2256 if (ret) 2257 goto failed_clk_ref; 2258 2259 ret = clk_prepare_enable(fep->clk_2x_txclk); 2260 if (ret) 2261 goto failed_clk_2x_txclk; 2262 2263 fec_enet_phy_reset_after_clk_enable(ndev); 2264 } else { 2265 clk_disable_unprepare(fep->clk_enet_out); 2266 if (fep->clk_ptp) { 2267 mutex_lock(&fep->ptp_clk_mutex); 2268 clk_disable_unprepare(fep->clk_ptp); 2269 fep->ptp_clk_on = false; 2270 mutex_unlock(&fep->ptp_clk_mutex); 2271 } 2272 clk_disable_unprepare(fep->clk_ref); 2273 clk_disable_unprepare(fep->clk_2x_txclk); 2274 } 2275 2276 return 0; 2277 2278 failed_clk_2x_txclk: 2279 if (fep->clk_ref) 2280 clk_disable_unprepare(fep->clk_ref); 2281 failed_clk_ref: 2282 if (fep->clk_ptp) { 2283 mutex_lock(&fep->ptp_clk_mutex); 2284 clk_disable_unprepare(fep->clk_ptp); 2285 fep->ptp_clk_on = false; 2286 mutex_unlock(&fep->ptp_clk_mutex); 2287 } 2288 failed_clk_ptp: 2289 clk_disable_unprepare(fep->clk_enet_out); 2290 2291 return ret; 2292 } 2293 2294 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2295 struct device_node *np) 2296 { 2297 u32 rgmii_tx_delay, rgmii_rx_delay; 2298 2299 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2300 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2301 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2302 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2303 return -EINVAL; 2304 } else if (rgmii_tx_delay == 2000) { 2305 fep->rgmii_txc_dly = true; 2306 } 2307 } 2308 2309 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2310 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2311 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2312 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2313 return -EINVAL; 2314 } else if (rgmii_rx_delay == 2000) { 2315 fep->rgmii_rxc_dly = true; 2316 } 2317 } 2318 2319 return 0; 2320 } 2321 2322 static int fec_enet_mii_probe(struct net_device *ndev) 2323 { 2324 struct fec_enet_private *fep = netdev_priv(ndev); 2325 struct phy_device *phy_dev = NULL; 2326 char mdio_bus_id[MII_BUS_ID_SIZE]; 2327 char phy_name[MII_BUS_ID_SIZE + 3]; 2328 int phy_id; 2329 int dev_id = fep->dev_id; 2330 2331 if (fep->phy_node) { 2332 phy_dev = of_phy_connect(ndev, fep->phy_node, 2333 &fec_enet_adjust_link, 0, 2334 fep->phy_interface); 2335 if (!phy_dev) { 2336 netdev_err(ndev, "Unable to connect to phy\n"); 2337 return -ENODEV; 2338 } 2339 } else { 2340 /* check for attached phy */ 2341 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2342 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2343 continue; 2344 if (dev_id--) 2345 continue; 2346 strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2347 break; 2348 } 2349 2350 if (phy_id >= PHY_MAX_ADDR) { 2351 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2352 strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2353 phy_id = 0; 2354 } 2355 2356 snprintf(phy_name, sizeof(phy_name), 2357 PHY_ID_FMT, mdio_bus_id, phy_id); 2358 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2359 fep->phy_interface); 2360 } 2361 2362 if (IS_ERR(phy_dev)) { 2363 netdev_err(ndev, "could not attach to PHY\n"); 2364 return PTR_ERR(phy_dev); 2365 } 2366 2367 /* mask with MAC supported features */ 2368 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2369 phy_set_max_speed(phy_dev, 1000); 2370 phy_remove_link_mode(phy_dev, 2371 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2372 #if !defined(CONFIG_M5272) 2373 phy_support_sym_pause(phy_dev); 2374 #endif 2375 } 2376 else 2377 phy_set_max_speed(phy_dev, 100); 2378 2379 fep->link = 0; 2380 fep->full_duplex = 0; 2381 2382 phy_dev->mac_managed_pm = true; 2383 2384 phy_attached_info(phy_dev); 2385 2386 return 0; 2387 } 2388 2389 static int fec_enet_mii_init(struct platform_device *pdev) 2390 { 2391 static struct mii_bus *fec0_mii_bus; 2392 struct net_device *ndev = platform_get_drvdata(pdev); 2393 struct fec_enet_private *fep = netdev_priv(ndev); 2394 bool suppress_preamble = false; 2395 struct device_node *node; 2396 int err = -ENXIO; 2397 u32 mii_speed, holdtime; 2398 u32 bus_freq; 2399 2400 /* 2401 * The i.MX28 dual fec interfaces are not equal. 2402 * Here are the differences: 2403 * 2404 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2405 * - fec0 acts as the 1588 time master while fec1 is slave 2406 * - external phys can only be configured by fec0 2407 * 2408 * That is to say fec1 can not work independently. It only works 2409 * when fec0 is working. The reason behind this design is that the 2410 * second interface is added primarily for Switch mode. 2411 * 2412 * Because of the last point above, both phys are attached on fec0 2413 * mdio interface in board design, and need to be configured by 2414 * fec0 mii_bus. 2415 */ 2416 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2417 /* fec1 uses fec0 mii_bus */ 2418 if (mii_cnt && fec0_mii_bus) { 2419 fep->mii_bus = fec0_mii_bus; 2420 mii_cnt++; 2421 return 0; 2422 } 2423 return -ENOENT; 2424 } 2425 2426 bus_freq = 2500000; /* 2.5MHz by default */ 2427 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2428 if (node) { 2429 of_property_read_u32(node, "clock-frequency", &bus_freq); 2430 suppress_preamble = of_property_read_bool(node, 2431 "suppress-preamble"); 2432 } 2433 2434 /* 2435 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2436 * 2437 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2438 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2439 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2440 * document. 2441 */ 2442 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2443 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2444 mii_speed--; 2445 if (mii_speed > 63) { 2446 dev_err(&pdev->dev, 2447 "fec clock (%lu) too fast to get right mii speed\n", 2448 clk_get_rate(fep->clk_ipg)); 2449 err = -EINVAL; 2450 goto err_out; 2451 } 2452 2453 /* 2454 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2455 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2456 * versions are RAZ there, so just ignore the difference and write the 2457 * register always. 2458 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2459 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2460 * output. 2461 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2462 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2463 * holdtime cannot result in a value greater than 3. 2464 */ 2465 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2466 2467 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2468 2469 if (suppress_preamble) 2470 fep->phy_speed |= BIT(7); 2471 2472 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2473 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2474 * MII event generation condition: 2475 * - writing MSCR: 2476 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2477 * mscr_reg_data_in[7:0] != 0 2478 * - writing MMFR: 2479 * - mscr[7:0]_not_zero 2480 */ 2481 writel(0, fep->hwp + FEC_MII_DATA); 2482 } 2483 2484 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2485 2486 /* Clear any pending transaction complete indication */ 2487 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2488 2489 fep->mii_bus = mdiobus_alloc(); 2490 if (fep->mii_bus == NULL) { 2491 err = -ENOMEM; 2492 goto err_out; 2493 } 2494 2495 fep->mii_bus->name = "fec_enet_mii_bus"; 2496 fep->mii_bus->read = fec_enet_mdio_read_c22; 2497 fep->mii_bus->write = fec_enet_mdio_write_c22; 2498 if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) { 2499 fep->mii_bus->read_c45 = fec_enet_mdio_read_c45; 2500 fep->mii_bus->write_c45 = fec_enet_mdio_write_c45; 2501 } 2502 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2503 pdev->name, fep->dev_id + 1); 2504 fep->mii_bus->priv = fep; 2505 fep->mii_bus->parent = &pdev->dev; 2506 2507 err = of_mdiobus_register(fep->mii_bus, node); 2508 if (err) 2509 goto err_out_free_mdiobus; 2510 of_node_put(node); 2511 2512 mii_cnt++; 2513 2514 /* save fec0 mii_bus */ 2515 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2516 fec0_mii_bus = fep->mii_bus; 2517 2518 return 0; 2519 2520 err_out_free_mdiobus: 2521 mdiobus_free(fep->mii_bus); 2522 err_out: 2523 of_node_put(node); 2524 return err; 2525 } 2526 2527 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2528 { 2529 if (--mii_cnt == 0) { 2530 mdiobus_unregister(fep->mii_bus); 2531 mdiobus_free(fep->mii_bus); 2532 } 2533 } 2534 2535 static void fec_enet_get_drvinfo(struct net_device *ndev, 2536 struct ethtool_drvinfo *info) 2537 { 2538 struct fec_enet_private *fep = netdev_priv(ndev); 2539 2540 strscpy(info->driver, fep->pdev->dev.driver->name, 2541 sizeof(info->driver)); 2542 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2543 } 2544 2545 static int fec_enet_get_regs_len(struct net_device *ndev) 2546 { 2547 struct fec_enet_private *fep = netdev_priv(ndev); 2548 struct resource *r; 2549 int s = 0; 2550 2551 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2552 if (r) 2553 s = resource_size(r); 2554 2555 return s; 2556 } 2557 2558 /* List of registers that can be safety be read to dump them with ethtool */ 2559 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2560 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2561 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2562 static __u32 fec_enet_register_version = 2; 2563 static u32 fec_enet_register_offset[] = { 2564 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2565 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2566 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2567 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2568 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2569 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2570 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2571 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2572 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2573 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2574 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2575 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2576 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2577 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2578 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2579 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2580 RMON_T_P_GTE2048, RMON_T_OCTETS, 2581 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2582 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2583 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2584 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2585 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2586 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2587 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2588 RMON_R_P_GTE2048, RMON_R_OCTETS, 2589 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2590 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2591 }; 2592 /* for i.MX6ul */ 2593 static u32 fec_enet_register_offset_6ul[] = { 2594 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2595 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2596 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0, 2597 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, 2598 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0, 2599 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2600 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, 2601 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2602 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2603 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2604 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2605 RMON_T_P_GTE2048, RMON_T_OCTETS, 2606 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2607 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2608 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2609 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2610 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2611 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2612 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2613 RMON_R_P_GTE2048, RMON_R_OCTETS, 2614 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2615 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2616 }; 2617 #else 2618 static __u32 fec_enet_register_version = 1; 2619 static u32 fec_enet_register_offset[] = { 2620 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2621 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2622 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2623 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2624 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2625 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2626 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2627 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2628 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2629 }; 2630 #endif 2631 2632 static void fec_enet_get_regs(struct net_device *ndev, 2633 struct ethtool_regs *regs, void *regbuf) 2634 { 2635 struct fec_enet_private *fep = netdev_priv(ndev); 2636 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2637 struct device *dev = &fep->pdev->dev; 2638 u32 *buf = (u32 *)regbuf; 2639 u32 i, off; 2640 int ret; 2641 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2642 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2643 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2644 u32 *reg_list; 2645 u32 reg_cnt; 2646 2647 if (!of_machine_is_compatible("fsl,imx6ul")) { 2648 reg_list = fec_enet_register_offset; 2649 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2650 } else { 2651 reg_list = fec_enet_register_offset_6ul; 2652 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul); 2653 } 2654 #else 2655 /* coldfire */ 2656 static u32 *reg_list = fec_enet_register_offset; 2657 static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2658 #endif 2659 ret = pm_runtime_resume_and_get(dev); 2660 if (ret < 0) 2661 return; 2662 2663 regs->version = fec_enet_register_version; 2664 2665 memset(buf, 0, regs->len); 2666 2667 for (i = 0; i < reg_cnt; i++) { 2668 off = reg_list[i]; 2669 2670 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2671 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2672 continue; 2673 2674 off >>= 2; 2675 buf[off] = readl(&theregs[off]); 2676 } 2677 2678 pm_runtime_mark_last_busy(dev); 2679 pm_runtime_put_autosuspend(dev); 2680 } 2681 2682 static int fec_enet_get_ts_info(struct net_device *ndev, 2683 struct ethtool_ts_info *info) 2684 { 2685 struct fec_enet_private *fep = netdev_priv(ndev); 2686 2687 if (fep->bufdesc_ex) { 2688 2689 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2690 SOF_TIMESTAMPING_RX_SOFTWARE | 2691 SOF_TIMESTAMPING_SOFTWARE | 2692 SOF_TIMESTAMPING_TX_HARDWARE | 2693 SOF_TIMESTAMPING_RX_HARDWARE | 2694 SOF_TIMESTAMPING_RAW_HARDWARE; 2695 if (fep->ptp_clock) 2696 info->phc_index = ptp_clock_index(fep->ptp_clock); 2697 else 2698 info->phc_index = -1; 2699 2700 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2701 (1 << HWTSTAMP_TX_ON); 2702 2703 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2704 (1 << HWTSTAMP_FILTER_ALL); 2705 return 0; 2706 } else { 2707 return ethtool_op_get_ts_info(ndev, info); 2708 } 2709 } 2710 2711 #if !defined(CONFIG_M5272) 2712 2713 static void fec_enet_get_pauseparam(struct net_device *ndev, 2714 struct ethtool_pauseparam *pause) 2715 { 2716 struct fec_enet_private *fep = netdev_priv(ndev); 2717 2718 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2719 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2720 pause->rx_pause = pause->tx_pause; 2721 } 2722 2723 static int fec_enet_set_pauseparam(struct net_device *ndev, 2724 struct ethtool_pauseparam *pause) 2725 { 2726 struct fec_enet_private *fep = netdev_priv(ndev); 2727 2728 if (!ndev->phydev) 2729 return -ENODEV; 2730 2731 if (pause->tx_pause != pause->rx_pause) { 2732 netdev_info(ndev, 2733 "hardware only support enable/disable both tx and rx"); 2734 return -EINVAL; 2735 } 2736 2737 fep->pause_flag = 0; 2738 2739 /* tx pause must be same as rx pause */ 2740 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2741 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2742 2743 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2744 pause->autoneg); 2745 2746 if (pause->autoneg) { 2747 if (netif_running(ndev)) 2748 fec_stop(ndev); 2749 phy_start_aneg(ndev->phydev); 2750 } 2751 if (netif_running(ndev)) { 2752 napi_disable(&fep->napi); 2753 netif_tx_lock_bh(ndev); 2754 fec_restart(ndev); 2755 netif_tx_wake_all_queues(ndev); 2756 netif_tx_unlock_bh(ndev); 2757 napi_enable(&fep->napi); 2758 } 2759 2760 return 0; 2761 } 2762 2763 static const struct fec_stat { 2764 char name[ETH_GSTRING_LEN]; 2765 u16 offset; 2766 } fec_stats[] = { 2767 /* RMON TX */ 2768 { "tx_dropped", RMON_T_DROP }, 2769 { "tx_packets", RMON_T_PACKETS }, 2770 { "tx_broadcast", RMON_T_BC_PKT }, 2771 { "tx_multicast", RMON_T_MC_PKT }, 2772 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2773 { "tx_undersize", RMON_T_UNDERSIZE }, 2774 { "tx_oversize", RMON_T_OVERSIZE }, 2775 { "tx_fragment", RMON_T_FRAG }, 2776 { "tx_jabber", RMON_T_JAB }, 2777 { "tx_collision", RMON_T_COL }, 2778 { "tx_64byte", RMON_T_P64 }, 2779 { "tx_65to127byte", RMON_T_P65TO127 }, 2780 { "tx_128to255byte", RMON_T_P128TO255 }, 2781 { "tx_256to511byte", RMON_T_P256TO511 }, 2782 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2783 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2784 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2785 { "tx_octets", RMON_T_OCTETS }, 2786 2787 /* IEEE TX */ 2788 { "IEEE_tx_drop", IEEE_T_DROP }, 2789 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2790 { "IEEE_tx_1col", IEEE_T_1COL }, 2791 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2792 { "IEEE_tx_def", IEEE_T_DEF }, 2793 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2794 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2795 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2796 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2797 { "IEEE_tx_sqe", IEEE_T_SQE }, 2798 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2799 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2800 2801 /* RMON RX */ 2802 { "rx_packets", RMON_R_PACKETS }, 2803 { "rx_broadcast", RMON_R_BC_PKT }, 2804 { "rx_multicast", RMON_R_MC_PKT }, 2805 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2806 { "rx_undersize", RMON_R_UNDERSIZE }, 2807 { "rx_oversize", RMON_R_OVERSIZE }, 2808 { "rx_fragment", RMON_R_FRAG }, 2809 { "rx_jabber", RMON_R_JAB }, 2810 { "rx_64byte", RMON_R_P64 }, 2811 { "rx_65to127byte", RMON_R_P65TO127 }, 2812 { "rx_128to255byte", RMON_R_P128TO255 }, 2813 { "rx_256to511byte", RMON_R_P256TO511 }, 2814 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2815 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2816 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2817 { "rx_octets", RMON_R_OCTETS }, 2818 2819 /* IEEE RX */ 2820 { "IEEE_rx_drop", IEEE_R_DROP }, 2821 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2822 { "IEEE_rx_crc", IEEE_R_CRC }, 2823 { "IEEE_rx_align", IEEE_R_ALIGN }, 2824 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2825 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2826 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2827 }; 2828 2829 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2830 2831 static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = { 2832 "rx_xdp_redirect", /* RX_XDP_REDIRECT = 0, */ 2833 "rx_xdp_pass", /* RX_XDP_PASS, */ 2834 "rx_xdp_drop", /* RX_XDP_DROP, */ 2835 "rx_xdp_tx", /* RX_XDP_TX, */ 2836 "rx_xdp_tx_errors", /* RX_XDP_TX_ERRORS, */ 2837 "tx_xdp_xmit", /* TX_XDP_XMIT, */ 2838 "tx_xdp_xmit_errors", /* TX_XDP_XMIT_ERRORS, */ 2839 }; 2840 2841 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2842 { 2843 struct fec_enet_private *fep = netdev_priv(dev); 2844 int i; 2845 2846 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2847 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2848 } 2849 2850 static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data) 2851 { 2852 u64 xdp_stats[XDP_STATS_TOTAL] = { 0 }; 2853 struct fec_enet_priv_rx_q *rxq; 2854 int i, j; 2855 2856 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2857 rxq = fep->rx_queue[i]; 2858 2859 for (j = 0; j < XDP_STATS_TOTAL; j++) 2860 xdp_stats[j] += rxq->stats[j]; 2861 } 2862 2863 memcpy(data, xdp_stats, sizeof(xdp_stats)); 2864 } 2865 2866 static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data) 2867 { 2868 #ifdef CONFIG_PAGE_POOL_STATS 2869 struct page_pool_stats stats = {}; 2870 struct fec_enet_priv_rx_q *rxq; 2871 int i; 2872 2873 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2874 rxq = fep->rx_queue[i]; 2875 2876 if (!rxq->page_pool) 2877 continue; 2878 2879 page_pool_get_stats(rxq->page_pool, &stats); 2880 } 2881 2882 page_pool_ethtool_stats_get(data, &stats); 2883 #endif 2884 } 2885 2886 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2887 struct ethtool_stats *stats, u64 *data) 2888 { 2889 struct fec_enet_private *fep = netdev_priv(dev); 2890 2891 if (netif_running(dev)) 2892 fec_enet_update_ethtool_stats(dev); 2893 2894 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2895 data += FEC_STATS_SIZE / sizeof(u64); 2896 2897 fec_enet_get_xdp_stats(fep, data); 2898 data += XDP_STATS_TOTAL; 2899 2900 fec_enet_page_pool_stats(fep, data); 2901 } 2902 2903 static void fec_enet_get_strings(struct net_device *netdev, 2904 u32 stringset, u8 *data) 2905 { 2906 int i; 2907 switch (stringset) { 2908 case ETH_SS_STATS: 2909 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) { 2910 memcpy(data, fec_stats[i].name, ETH_GSTRING_LEN); 2911 data += ETH_GSTRING_LEN; 2912 } 2913 for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) { 2914 strncpy(data, fec_xdp_stat_strs[i], ETH_GSTRING_LEN); 2915 data += ETH_GSTRING_LEN; 2916 } 2917 page_pool_ethtool_stats_get_strings(data); 2918 2919 break; 2920 case ETH_SS_TEST: 2921 net_selftest_get_strings(data); 2922 break; 2923 } 2924 } 2925 2926 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2927 { 2928 int count; 2929 2930 switch (sset) { 2931 case ETH_SS_STATS: 2932 count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL; 2933 count += page_pool_ethtool_stats_get_count(); 2934 return count; 2935 2936 case ETH_SS_TEST: 2937 return net_selftest_get_count(); 2938 default: 2939 return -EOPNOTSUPP; 2940 } 2941 } 2942 2943 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2944 { 2945 struct fec_enet_private *fep = netdev_priv(dev); 2946 struct fec_enet_priv_rx_q *rxq; 2947 int i, j; 2948 2949 /* Disable MIB statistics counters */ 2950 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2951 2952 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2953 writel(0, fep->hwp + fec_stats[i].offset); 2954 2955 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2956 rxq = fep->rx_queue[i]; 2957 for (j = 0; j < XDP_STATS_TOTAL; j++) 2958 rxq->stats[j] = 0; 2959 } 2960 2961 /* Don't disable MIB statistics counters */ 2962 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2963 } 2964 2965 #else /* !defined(CONFIG_M5272) */ 2966 #define FEC_STATS_SIZE 0 2967 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2968 { 2969 } 2970 2971 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2972 { 2973 } 2974 #endif /* !defined(CONFIG_M5272) */ 2975 2976 /* ITR clock source is enet system clock (clk_ahb). 2977 * TCTT unit is cycle_ns * 64 cycle 2978 * So, the ICTT value = X us / (cycle_ns * 64) 2979 */ 2980 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2981 { 2982 struct fec_enet_private *fep = netdev_priv(ndev); 2983 2984 return us * (fep->itr_clk_rate / 64000) / 1000; 2985 } 2986 2987 /* Set threshold for interrupt coalescing */ 2988 static void fec_enet_itr_coal_set(struct net_device *ndev) 2989 { 2990 struct fec_enet_private *fep = netdev_priv(ndev); 2991 int rx_itr, tx_itr; 2992 2993 /* Must be greater than zero to avoid unpredictable behavior */ 2994 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2995 !fep->tx_time_itr || !fep->tx_pkts_itr) 2996 return; 2997 2998 /* Select enet system clock as Interrupt Coalescing 2999 * timer Clock Source 3000 */ 3001 rx_itr = FEC_ITR_CLK_SEL; 3002 tx_itr = FEC_ITR_CLK_SEL; 3003 3004 /* set ICFT and ICTT */ 3005 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 3006 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 3007 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 3008 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 3009 3010 rx_itr |= FEC_ITR_EN; 3011 tx_itr |= FEC_ITR_EN; 3012 3013 writel(tx_itr, fep->hwp + FEC_TXIC0); 3014 writel(rx_itr, fep->hwp + FEC_RXIC0); 3015 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 3016 writel(tx_itr, fep->hwp + FEC_TXIC1); 3017 writel(rx_itr, fep->hwp + FEC_RXIC1); 3018 writel(tx_itr, fep->hwp + FEC_TXIC2); 3019 writel(rx_itr, fep->hwp + FEC_RXIC2); 3020 } 3021 } 3022 3023 static int fec_enet_get_coalesce(struct net_device *ndev, 3024 struct ethtool_coalesce *ec, 3025 struct kernel_ethtool_coalesce *kernel_coal, 3026 struct netlink_ext_ack *extack) 3027 { 3028 struct fec_enet_private *fep = netdev_priv(ndev); 3029 3030 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3031 return -EOPNOTSUPP; 3032 3033 ec->rx_coalesce_usecs = fep->rx_time_itr; 3034 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 3035 3036 ec->tx_coalesce_usecs = fep->tx_time_itr; 3037 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 3038 3039 return 0; 3040 } 3041 3042 static int fec_enet_set_coalesce(struct net_device *ndev, 3043 struct ethtool_coalesce *ec, 3044 struct kernel_ethtool_coalesce *kernel_coal, 3045 struct netlink_ext_ack *extack) 3046 { 3047 struct fec_enet_private *fep = netdev_priv(ndev); 3048 struct device *dev = &fep->pdev->dev; 3049 unsigned int cycle; 3050 3051 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3052 return -EOPNOTSUPP; 3053 3054 if (ec->rx_max_coalesced_frames > 255) { 3055 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 3056 return -EINVAL; 3057 } 3058 3059 if (ec->tx_max_coalesced_frames > 255) { 3060 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 3061 return -EINVAL; 3062 } 3063 3064 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 3065 if (cycle > 0xFFFF) { 3066 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 3067 return -EINVAL; 3068 } 3069 3070 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 3071 if (cycle > 0xFFFF) { 3072 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 3073 return -EINVAL; 3074 } 3075 3076 fep->rx_time_itr = ec->rx_coalesce_usecs; 3077 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 3078 3079 fep->tx_time_itr = ec->tx_coalesce_usecs; 3080 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 3081 3082 fec_enet_itr_coal_set(ndev); 3083 3084 return 0; 3085 } 3086 3087 /* LPI Sleep Ts count base on tx clk (clk_ref). 3088 * The lpi sleep cnt value = X us / (cycle_ns). 3089 */ 3090 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 3091 { 3092 struct fec_enet_private *fep = netdev_priv(ndev); 3093 3094 return us * (fep->clk_ref_rate / 1000) / 1000; 3095 } 3096 3097 static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable) 3098 { 3099 struct fec_enet_private *fep = netdev_priv(ndev); 3100 struct ethtool_eee *p = &fep->eee; 3101 unsigned int sleep_cycle, wake_cycle; 3102 int ret = 0; 3103 3104 if (enable) { 3105 ret = phy_init_eee(ndev->phydev, false); 3106 if (ret) 3107 return ret; 3108 3109 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer); 3110 wake_cycle = sleep_cycle; 3111 } else { 3112 sleep_cycle = 0; 3113 wake_cycle = 0; 3114 } 3115 3116 p->tx_lpi_enabled = enable; 3117 p->eee_enabled = enable; 3118 p->eee_active = enable; 3119 3120 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 3121 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 3122 3123 return 0; 3124 } 3125 3126 static int 3127 fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata) 3128 { 3129 struct fec_enet_private *fep = netdev_priv(ndev); 3130 struct ethtool_eee *p = &fep->eee; 3131 3132 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3133 return -EOPNOTSUPP; 3134 3135 if (!netif_running(ndev)) 3136 return -ENETDOWN; 3137 3138 edata->eee_enabled = p->eee_enabled; 3139 edata->eee_active = p->eee_active; 3140 edata->tx_lpi_timer = p->tx_lpi_timer; 3141 edata->tx_lpi_enabled = p->tx_lpi_enabled; 3142 3143 return phy_ethtool_get_eee(ndev->phydev, edata); 3144 } 3145 3146 static int 3147 fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata) 3148 { 3149 struct fec_enet_private *fep = netdev_priv(ndev); 3150 struct ethtool_eee *p = &fep->eee; 3151 int ret = 0; 3152 3153 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3154 return -EOPNOTSUPP; 3155 3156 if (!netif_running(ndev)) 3157 return -ENETDOWN; 3158 3159 p->tx_lpi_timer = edata->tx_lpi_timer; 3160 3161 if (!edata->eee_enabled || !edata->tx_lpi_enabled || 3162 !edata->tx_lpi_timer) 3163 ret = fec_enet_eee_mode_set(ndev, false); 3164 else 3165 ret = fec_enet_eee_mode_set(ndev, true); 3166 3167 if (ret) 3168 return ret; 3169 3170 return phy_ethtool_set_eee(ndev->phydev, edata); 3171 } 3172 3173 static void 3174 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3175 { 3176 struct fec_enet_private *fep = netdev_priv(ndev); 3177 3178 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 3179 wol->supported = WAKE_MAGIC; 3180 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 3181 } else { 3182 wol->supported = wol->wolopts = 0; 3183 } 3184 } 3185 3186 static int 3187 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3188 { 3189 struct fec_enet_private *fep = netdev_priv(ndev); 3190 3191 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 3192 return -EINVAL; 3193 3194 if (wol->wolopts & ~WAKE_MAGIC) 3195 return -EINVAL; 3196 3197 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 3198 if (device_may_wakeup(&ndev->dev)) 3199 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 3200 else 3201 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 3202 3203 return 0; 3204 } 3205 3206 static const struct ethtool_ops fec_enet_ethtool_ops = { 3207 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3208 ETHTOOL_COALESCE_MAX_FRAMES, 3209 .get_drvinfo = fec_enet_get_drvinfo, 3210 .get_regs_len = fec_enet_get_regs_len, 3211 .get_regs = fec_enet_get_regs, 3212 .nway_reset = phy_ethtool_nway_reset, 3213 .get_link = ethtool_op_get_link, 3214 .get_coalesce = fec_enet_get_coalesce, 3215 .set_coalesce = fec_enet_set_coalesce, 3216 #ifndef CONFIG_M5272 3217 .get_pauseparam = fec_enet_get_pauseparam, 3218 .set_pauseparam = fec_enet_set_pauseparam, 3219 .get_strings = fec_enet_get_strings, 3220 .get_ethtool_stats = fec_enet_get_ethtool_stats, 3221 .get_sset_count = fec_enet_get_sset_count, 3222 #endif 3223 .get_ts_info = fec_enet_get_ts_info, 3224 .get_wol = fec_enet_get_wol, 3225 .set_wol = fec_enet_set_wol, 3226 .get_eee = fec_enet_get_eee, 3227 .set_eee = fec_enet_set_eee, 3228 .get_link_ksettings = phy_ethtool_get_link_ksettings, 3229 .set_link_ksettings = phy_ethtool_set_link_ksettings, 3230 .self_test = net_selftest, 3231 }; 3232 3233 static void fec_enet_free_buffers(struct net_device *ndev) 3234 { 3235 struct fec_enet_private *fep = netdev_priv(ndev); 3236 unsigned int i; 3237 struct fec_enet_priv_tx_q *txq; 3238 struct fec_enet_priv_rx_q *rxq; 3239 unsigned int q; 3240 3241 for (q = 0; q < fep->num_rx_queues; q++) { 3242 rxq = fep->rx_queue[q]; 3243 for (i = 0; i < rxq->bd.ring_size; i++) 3244 page_pool_put_full_page(rxq->page_pool, rxq->rx_skb_info[i].page, false); 3245 3246 for (i = 0; i < XDP_STATS_TOTAL; i++) 3247 rxq->stats[i] = 0; 3248 3249 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 3250 xdp_rxq_info_unreg(&rxq->xdp_rxq); 3251 page_pool_destroy(rxq->page_pool); 3252 rxq->page_pool = NULL; 3253 } 3254 3255 for (q = 0; q < fep->num_tx_queues; q++) { 3256 txq = fep->tx_queue[q]; 3257 for (i = 0; i < txq->bd.ring_size; i++) { 3258 kfree(txq->tx_bounce[i]); 3259 txq->tx_bounce[i] = NULL; 3260 3261 if (!txq->tx_buf[i].buf_p) { 3262 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3263 continue; 3264 } 3265 3266 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 3267 dev_kfree_skb(txq->tx_buf[i].buf_p); 3268 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 3269 xdp_return_frame(txq->tx_buf[i].buf_p); 3270 } else { 3271 struct page *page = txq->tx_buf[i].buf_p; 3272 3273 page_pool_put_page(page->pp, page, 0, false); 3274 } 3275 3276 txq->tx_buf[i].buf_p = NULL; 3277 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3278 } 3279 } 3280 } 3281 3282 static void fec_enet_free_queue(struct net_device *ndev) 3283 { 3284 struct fec_enet_private *fep = netdev_priv(ndev); 3285 int i; 3286 struct fec_enet_priv_tx_q *txq; 3287 3288 for (i = 0; i < fep->num_tx_queues; i++) 3289 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 3290 txq = fep->tx_queue[i]; 3291 dma_free_coherent(&fep->pdev->dev, 3292 txq->bd.ring_size * TSO_HEADER_SIZE, 3293 txq->tso_hdrs, 3294 txq->tso_hdrs_dma); 3295 } 3296 3297 for (i = 0; i < fep->num_rx_queues; i++) 3298 kfree(fep->rx_queue[i]); 3299 for (i = 0; i < fep->num_tx_queues; i++) 3300 kfree(fep->tx_queue[i]); 3301 } 3302 3303 static int fec_enet_alloc_queue(struct net_device *ndev) 3304 { 3305 struct fec_enet_private *fep = netdev_priv(ndev); 3306 int i; 3307 int ret = 0; 3308 struct fec_enet_priv_tx_q *txq; 3309 3310 for (i = 0; i < fep->num_tx_queues; i++) { 3311 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3312 if (!txq) { 3313 ret = -ENOMEM; 3314 goto alloc_failed; 3315 } 3316 3317 fep->tx_queue[i] = txq; 3318 txq->bd.ring_size = TX_RING_SIZE; 3319 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3320 3321 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3322 txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS; 3323 3324 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 3325 txq->bd.ring_size * TSO_HEADER_SIZE, 3326 &txq->tso_hdrs_dma, 3327 GFP_KERNEL); 3328 if (!txq->tso_hdrs) { 3329 ret = -ENOMEM; 3330 goto alloc_failed; 3331 } 3332 } 3333 3334 for (i = 0; i < fep->num_rx_queues; i++) { 3335 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3336 GFP_KERNEL); 3337 if (!fep->rx_queue[i]) { 3338 ret = -ENOMEM; 3339 goto alloc_failed; 3340 } 3341 3342 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3343 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3344 } 3345 return ret; 3346 3347 alloc_failed: 3348 fec_enet_free_queue(ndev); 3349 return ret; 3350 } 3351 3352 static int 3353 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3354 { 3355 struct fec_enet_private *fep = netdev_priv(ndev); 3356 struct fec_enet_priv_rx_q *rxq; 3357 dma_addr_t phys_addr; 3358 struct bufdesc *bdp; 3359 struct page *page; 3360 int i, err; 3361 3362 rxq = fep->rx_queue[queue]; 3363 bdp = rxq->bd.base; 3364 3365 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size); 3366 if (err < 0) { 3367 netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err); 3368 return err; 3369 } 3370 3371 for (i = 0; i < rxq->bd.ring_size; i++) { 3372 page = page_pool_dev_alloc_pages(rxq->page_pool); 3373 if (!page) 3374 goto err_alloc; 3375 3376 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM; 3377 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 3378 3379 rxq->rx_skb_info[i].page = page; 3380 rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM; 3381 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3382 3383 if (fep->bufdesc_ex) { 3384 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3385 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3386 } 3387 3388 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3389 } 3390 3391 /* Set the last buffer to wrap. */ 3392 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3393 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3394 return 0; 3395 3396 err_alloc: 3397 fec_enet_free_buffers(ndev); 3398 return -ENOMEM; 3399 } 3400 3401 static int 3402 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3403 { 3404 struct fec_enet_private *fep = netdev_priv(ndev); 3405 unsigned int i; 3406 struct bufdesc *bdp; 3407 struct fec_enet_priv_tx_q *txq; 3408 3409 txq = fep->tx_queue[queue]; 3410 bdp = txq->bd.base; 3411 for (i = 0; i < txq->bd.ring_size; i++) { 3412 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3413 if (!txq->tx_bounce[i]) 3414 goto err_alloc; 3415 3416 bdp->cbd_sc = cpu_to_fec16(0); 3417 bdp->cbd_bufaddr = cpu_to_fec32(0); 3418 3419 if (fep->bufdesc_ex) { 3420 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3421 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3422 } 3423 3424 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3425 } 3426 3427 /* Set the last buffer to wrap. */ 3428 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3429 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3430 3431 return 0; 3432 3433 err_alloc: 3434 fec_enet_free_buffers(ndev); 3435 return -ENOMEM; 3436 } 3437 3438 static int fec_enet_alloc_buffers(struct net_device *ndev) 3439 { 3440 struct fec_enet_private *fep = netdev_priv(ndev); 3441 unsigned int i; 3442 3443 for (i = 0; i < fep->num_rx_queues; i++) 3444 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3445 return -ENOMEM; 3446 3447 for (i = 0; i < fep->num_tx_queues; i++) 3448 if (fec_enet_alloc_txq_buffers(ndev, i)) 3449 return -ENOMEM; 3450 return 0; 3451 } 3452 3453 static int 3454 fec_enet_open(struct net_device *ndev) 3455 { 3456 struct fec_enet_private *fep = netdev_priv(ndev); 3457 int ret; 3458 bool reset_again; 3459 3460 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3461 if (ret < 0) 3462 return ret; 3463 3464 pinctrl_pm_select_default_state(&fep->pdev->dev); 3465 ret = fec_enet_clk_enable(ndev, true); 3466 if (ret) 3467 goto clk_enable; 3468 3469 /* During the first fec_enet_open call the PHY isn't probed at this 3470 * point. Therefore the phy_reset_after_clk_enable() call within 3471 * fec_enet_clk_enable() fails. As we need this reset in order to be 3472 * sure the PHY is working correctly we check if we need to reset again 3473 * later when the PHY is probed 3474 */ 3475 if (ndev->phydev && ndev->phydev->drv) 3476 reset_again = false; 3477 else 3478 reset_again = true; 3479 3480 /* I should reset the ring buffers here, but I don't yet know 3481 * a simple way to do that. 3482 */ 3483 3484 ret = fec_enet_alloc_buffers(ndev); 3485 if (ret) 3486 goto err_enet_alloc; 3487 3488 /* Init MAC prior to mii bus probe */ 3489 fec_restart(ndev); 3490 3491 /* Call phy_reset_after_clk_enable() again if it failed during 3492 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3493 */ 3494 if (reset_again) 3495 fec_enet_phy_reset_after_clk_enable(ndev); 3496 3497 /* Probe and connect to PHY when open the interface */ 3498 ret = fec_enet_mii_probe(ndev); 3499 if (ret) 3500 goto err_enet_mii_probe; 3501 3502 if (fep->quirks & FEC_QUIRK_ERR006687) 3503 imx6q_cpuidle_fec_irqs_used(); 3504 3505 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3506 cpu_latency_qos_add_request(&fep->pm_qos_req, 0); 3507 3508 napi_enable(&fep->napi); 3509 phy_start(ndev->phydev); 3510 netif_tx_start_all_queues(ndev); 3511 3512 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3513 FEC_WOL_FLAG_ENABLE); 3514 3515 return 0; 3516 3517 err_enet_mii_probe: 3518 fec_enet_free_buffers(ndev); 3519 err_enet_alloc: 3520 fec_enet_clk_enable(ndev, false); 3521 clk_enable: 3522 pm_runtime_mark_last_busy(&fep->pdev->dev); 3523 pm_runtime_put_autosuspend(&fep->pdev->dev); 3524 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3525 return ret; 3526 } 3527 3528 static int 3529 fec_enet_close(struct net_device *ndev) 3530 { 3531 struct fec_enet_private *fep = netdev_priv(ndev); 3532 3533 phy_stop(ndev->phydev); 3534 3535 if (netif_device_present(ndev)) { 3536 napi_disable(&fep->napi); 3537 netif_tx_disable(ndev); 3538 fec_stop(ndev); 3539 } 3540 3541 phy_disconnect(ndev->phydev); 3542 3543 if (fep->quirks & FEC_QUIRK_ERR006687) 3544 imx6q_cpuidle_fec_irqs_unused(); 3545 3546 fec_enet_update_ethtool_stats(ndev); 3547 3548 fec_enet_clk_enable(ndev, false); 3549 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3550 cpu_latency_qos_remove_request(&fep->pm_qos_req); 3551 3552 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3553 pm_runtime_mark_last_busy(&fep->pdev->dev); 3554 pm_runtime_put_autosuspend(&fep->pdev->dev); 3555 3556 fec_enet_free_buffers(ndev); 3557 3558 return 0; 3559 } 3560 3561 /* Set or clear the multicast filter for this adaptor. 3562 * Skeleton taken from sunlance driver. 3563 * The CPM Ethernet implementation allows Multicast as well as individual 3564 * MAC address filtering. Some of the drivers check to make sure it is 3565 * a group multicast address, and discard those that are not. I guess I 3566 * will do the same for now, but just remove the test if you want 3567 * individual filtering as well (do the upper net layers want or support 3568 * this kind of feature?). 3569 */ 3570 3571 #define FEC_HASH_BITS 6 /* #bits in hash */ 3572 3573 static void set_multicast_list(struct net_device *ndev) 3574 { 3575 struct fec_enet_private *fep = netdev_priv(ndev); 3576 struct netdev_hw_addr *ha; 3577 unsigned int crc, tmp; 3578 unsigned char hash; 3579 unsigned int hash_high = 0, hash_low = 0; 3580 3581 if (ndev->flags & IFF_PROMISC) { 3582 tmp = readl(fep->hwp + FEC_R_CNTRL); 3583 tmp |= 0x8; 3584 writel(tmp, fep->hwp + FEC_R_CNTRL); 3585 return; 3586 } 3587 3588 tmp = readl(fep->hwp + FEC_R_CNTRL); 3589 tmp &= ~0x8; 3590 writel(tmp, fep->hwp + FEC_R_CNTRL); 3591 3592 if (ndev->flags & IFF_ALLMULTI) { 3593 /* Catch all multicast addresses, so set the 3594 * filter to all 1's 3595 */ 3596 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3597 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3598 3599 return; 3600 } 3601 3602 /* Add the addresses in hash register */ 3603 netdev_for_each_mc_addr(ha, ndev) { 3604 /* calculate crc32 value of mac address */ 3605 crc = ether_crc_le(ndev->addr_len, ha->addr); 3606 3607 /* only upper 6 bits (FEC_HASH_BITS) are used 3608 * which point to specific bit in the hash registers 3609 */ 3610 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3611 3612 if (hash > 31) 3613 hash_high |= 1 << (hash - 32); 3614 else 3615 hash_low |= 1 << hash; 3616 } 3617 3618 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3619 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3620 } 3621 3622 /* Set a MAC change in hardware. */ 3623 static int 3624 fec_set_mac_address(struct net_device *ndev, void *p) 3625 { 3626 struct fec_enet_private *fep = netdev_priv(ndev); 3627 struct sockaddr *addr = p; 3628 3629 if (addr) { 3630 if (!is_valid_ether_addr(addr->sa_data)) 3631 return -EADDRNOTAVAIL; 3632 eth_hw_addr_set(ndev, addr->sa_data); 3633 } 3634 3635 /* Add netif status check here to avoid system hang in below case: 3636 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3637 * After ethx down, fec all clocks are gated off and then register 3638 * access causes system hang. 3639 */ 3640 if (!netif_running(ndev)) 3641 return 0; 3642 3643 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3644 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3645 fep->hwp + FEC_ADDR_LOW); 3646 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3647 fep->hwp + FEC_ADDR_HIGH); 3648 return 0; 3649 } 3650 3651 #ifdef CONFIG_NET_POLL_CONTROLLER 3652 /** 3653 * fec_poll_controller - FEC Poll controller function 3654 * @dev: The FEC network adapter 3655 * 3656 * Polled functionality used by netconsole and others in non interrupt mode 3657 * 3658 */ 3659 static void fec_poll_controller(struct net_device *dev) 3660 { 3661 int i; 3662 struct fec_enet_private *fep = netdev_priv(dev); 3663 3664 for (i = 0; i < FEC_IRQ_NUM; i++) { 3665 if (fep->irq[i] > 0) { 3666 disable_irq(fep->irq[i]); 3667 fec_enet_interrupt(fep->irq[i], dev); 3668 enable_irq(fep->irq[i]); 3669 } 3670 } 3671 } 3672 #endif 3673 3674 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3675 netdev_features_t features) 3676 { 3677 struct fec_enet_private *fep = netdev_priv(netdev); 3678 netdev_features_t changed = features ^ netdev->features; 3679 3680 netdev->features = features; 3681 3682 /* Receive checksum has been changed */ 3683 if (changed & NETIF_F_RXCSUM) { 3684 if (features & NETIF_F_RXCSUM) 3685 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3686 else 3687 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3688 } 3689 } 3690 3691 static int fec_set_features(struct net_device *netdev, 3692 netdev_features_t features) 3693 { 3694 struct fec_enet_private *fep = netdev_priv(netdev); 3695 netdev_features_t changed = features ^ netdev->features; 3696 3697 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3698 napi_disable(&fep->napi); 3699 netif_tx_lock_bh(netdev); 3700 fec_stop(netdev); 3701 fec_enet_set_netdev_features(netdev, features); 3702 fec_restart(netdev); 3703 netif_tx_wake_all_queues(netdev); 3704 netif_tx_unlock_bh(netdev); 3705 napi_enable(&fep->napi); 3706 } else { 3707 fec_enet_set_netdev_features(netdev, features); 3708 } 3709 3710 return 0; 3711 } 3712 3713 static u16 fec_enet_get_raw_vlan_tci(struct sk_buff *skb) 3714 { 3715 struct vlan_ethhdr *vhdr; 3716 unsigned short vlan_TCI = 0; 3717 3718 if (skb->protocol == htons(ETH_P_ALL)) { 3719 vhdr = (struct vlan_ethhdr *)(skb->data); 3720 vlan_TCI = ntohs(vhdr->h_vlan_TCI); 3721 } 3722 3723 return vlan_TCI; 3724 } 3725 3726 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3727 struct net_device *sb_dev) 3728 { 3729 struct fec_enet_private *fep = netdev_priv(ndev); 3730 u16 vlan_tag; 3731 3732 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3733 return netdev_pick_tx(ndev, skb, NULL); 3734 3735 vlan_tag = fec_enet_get_raw_vlan_tci(skb); 3736 if (!vlan_tag) 3737 return vlan_tag; 3738 3739 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3740 } 3741 3742 static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf) 3743 { 3744 struct fec_enet_private *fep = netdev_priv(dev); 3745 bool is_run = netif_running(dev); 3746 struct bpf_prog *old_prog; 3747 3748 switch (bpf->command) { 3749 case XDP_SETUP_PROG: 3750 /* No need to support the SoCs that require to 3751 * do the frame swap because the performance wouldn't be 3752 * better than the skb mode. 3753 */ 3754 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 3755 return -EOPNOTSUPP; 3756 3757 if (!bpf->prog) 3758 xdp_features_clear_redirect_target(dev); 3759 3760 if (is_run) { 3761 napi_disable(&fep->napi); 3762 netif_tx_disable(dev); 3763 } 3764 3765 old_prog = xchg(&fep->xdp_prog, bpf->prog); 3766 if (old_prog) 3767 bpf_prog_put(old_prog); 3768 3769 fec_restart(dev); 3770 3771 if (is_run) { 3772 napi_enable(&fep->napi); 3773 netif_tx_start_all_queues(dev); 3774 } 3775 3776 if (bpf->prog) 3777 xdp_features_set_redirect_target(dev, false); 3778 3779 return 0; 3780 3781 case XDP_SETUP_XSK_POOL: 3782 return -EOPNOTSUPP; 3783 3784 default: 3785 return -EOPNOTSUPP; 3786 } 3787 } 3788 3789 static int 3790 fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index) 3791 { 3792 if (unlikely(index < 0)) 3793 return 0; 3794 3795 return (index % fep->num_tx_queues); 3796 } 3797 3798 static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep, 3799 struct fec_enet_priv_tx_q *txq, 3800 void *frame, u32 dma_sync_len, 3801 bool ndo_xmit) 3802 { 3803 unsigned int index, status, estatus; 3804 struct bufdesc *bdp; 3805 dma_addr_t dma_addr; 3806 int entries_free; 3807 u16 frame_len; 3808 3809 entries_free = fec_enet_get_free_txdesc_num(txq); 3810 if (entries_free < MAX_SKB_FRAGS + 1) { 3811 netdev_err_once(fep->netdev, "NOT enough BD for SG!\n"); 3812 return -EBUSY; 3813 } 3814 3815 /* Fill in a Tx ring entry */ 3816 bdp = txq->bd.cur; 3817 status = fec16_to_cpu(bdp->cbd_sc); 3818 status &= ~BD_ENET_TX_STATS; 3819 3820 index = fec_enet_get_bd_index(bdp, &txq->bd); 3821 3822 if (ndo_xmit) { 3823 struct xdp_frame *xdpf = frame; 3824 3825 dma_addr = dma_map_single(&fep->pdev->dev, xdpf->data, 3826 xdpf->len, DMA_TO_DEVICE); 3827 if (dma_mapping_error(&fep->pdev->dev, dma_addr)) 3828 return -ENOMEM; 3829 3830 frame_len = xdpf->len; 3831 txq->tx_buf[index].buf_p = xdpf; 3832 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO; 3833 } else { 3834 struct xdp_buff *xdpb = frame; 3835 struct page *page; 3836 3837 page = virt_to_page(xdpb->data); 3838 dma_addr = page_pool_get_dma_addr(page) + 3839 (xdpb->data - xdpb->data_hard_start); 3840 dma_sync_single_for_device(&fep->pdev->dev, dma_addr, 3841 dma_sync_len, DMA_BIDIRECTIONAL); 3842 frame_len = xdpb->data_end - xdpb->data; 3843 txq->tx_buf[index].buf_p = page; 3844 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_TX; 3845 } 3846 3847 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 3848 if (fep->bufdesc_ex) 3849 estatus = BD_ENET_TX_INT; 3850 3851 bdp->cbd_bufaddr = cpu_to_fec32(dma_addr); 3852 bdp->cbd_datlen = cpu_to_fec16(frame_len); 3853 3854 if (fep->bufdesc_ex) { 3855 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3856 3857 if (fep->quirks & FEC_QUIRK_HAS_AVB) 3858 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 3859 3860 ebdp->cbd_bdu = 0; 3861 ebdp->cbd_esc = cpu_to_fec32(estatus); 3862 } 3863 3864 /* Make sure the updates to rest of the descriptor are performed before 3865 * transferring ownership. 3866 */ 3867 dma_wmb(); 3868 3869 /* Send it on its way. Tell FEC it's ready, interrupt when done, 3870 * it's the last BD of the frame, and to put the CRC on the end. 3871 */ 3872 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 3873 bdp->cbd_sc = cpu_to_fec16(status); 3874 3875 /* If this was the last BD in the ring, start at the beginning again. */ 3876 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3877 3878 /* Make sure the update to bdp are performed before txq->bd.cur. */ 3879 dma_wmb(); 3880 3881 txq->bd.cur = bdp; 3882 3883 /* Trigger transmission start */ 3884 writel(0, txq->bd.reg_desc_active); 3885 3886 return 0; 3887 } 3888 3889 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 3890 int cpu, struct xdp_buff *xdp, 3891 u32 dma_sync_len) 3892 { 3893 struct fec_enet_priv_tx_q *txq; 3894 struct netdev_queue *nq; 3895 int queue, ret; 3896 3897 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3898 txq = fep->tx_queue[queue]; 3899 nq = netdev_get_tx_queue(fep->netdev, queue); 3900 3901 __netif_tx_lock(nq, cpu); 3902 3903 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3904 txq_trans_cond_update(nq); 3905 ret = fec_enet_txq_xmit_frame(fep, txq, xdp, dma_sync_len, false); 3906 3907 __netif_tx_unlock(nq); 3908 3909 return ret; 3910 } 3911 3912 static int fec_enet_xdp_xmit(struct net_device *dev, 3913 int num_frames, 3914 struct xdp_frame **frames, 3915 u32 flags) 3916 { 3917 struct fec_enet_private *fep = netdev_priv(dev); 3918 struct fec_enet_priv_tx_q *txq; 3919 int cpu = smp_processor_id(); 3920 unsigned int sent_frames = 0; 3921 struct netdev_queue *nq; 3922 unsigned int queue; 3923 int i; 3924 3925 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3926 txq = fep->tx_queue[queue]; 3927 nq = netdev_get_tx_queue(fep->netdev, queue); 3928 3929 __netif_tx_lock(nq, cpu); 3930 3931 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3932 txq_trans_cond_update(nq); 3933 for (i = 0; i < num_frames; i++) { 3934 if (fec_enet_txq_xmit_frame(fep, txq, frames[i], 0, true) < 0) 3935 break; 3936 sent_frames++; 3937 } 3938 3939 __netif_tx_unlock(nq); 3940 3941 return sent_frames; 3942 } 3943 3944 static int fec_hwtstamp_get(struct net_device *ndev, 3945 struct kernel_hwtstamp_config *config) 3946 { 3947 struct fec_enet_private *fep = netdev_priv(ndev); 3948 3949 if (!netif_running(ndev)) 3950 return -EINVAL; 3951 3952 if (!fep->bufdesc_ex) 3953 return -EOPNOTSUPP; 3954 3955 fec_ptp_get(ndev, config); 3956 3957 return 0; 3958 } 3959 3960 static int fec_hwtstamp_set(struct net_device *ndev, 3961 struct kernel_hwtstamp_config *config, 3962 struct netlink_ext_ack *extack) 3963 { 3964 struct fec_enet_private *fep = netdev_priv(ndev); 3965 3966 if (!netif_running(ndev)) 3967 return -EINVAL; 3968 3969 if (!fep->bufdesc_ex) 3970 return -EOPNOTSUPP; 3971 3972 return fec_ptp_set(ndev, config, extack); 3973 } 3974 3975 static const struct net_device_ops fec_netdev_ops = { 3976 .ndo_open = fec_enet_open, 3977 .ndo_stop = fec_enet_close, 3978 .ndo_start_xmit = fec_enet_start_xmit, 3979 .ndo_select_queue = fec_enet_select_queue, 3980 .ndo_set_rx_mode = set_multicast_list, 3981 .ndo_validate_addr = eth_validate_addr, 3982 .ndo_tx_timeout = fec_timeout, 3983 .ndo_set_mac_address = fec_set_mac_address, 3984 .ndo_eth_ioctl = phy_do_ioctl_running, 3985 #ifdef CONFIG_NET_POLL_CONTROLLER 3986 .ndo_poll_controller = fec_poll_controller, 3987 #endif 3988 .ndo_set_features = fec_set_features, 3989 .ndo_bpf = fec_enet_bpf, 3990 .ndo_xdp_xmit = fec_enet_xdp_xmit, 3991 .ndo_hwtstamp_get = fec_hwtstamp_get, 3992 .ndo_hwtstamp_set = fec_hwtstamp_set, 3993 }; 3994 3995 static const unsigned short offset_des_active_rxq[] = { 3996 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3997 }; 3998 3999 static const unsigned short offset_des_active_txq[] = { 4000 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 4001 }; 4002 4003 /* 4004 * XXX: We need to clean up on failure exits here. 4005 * 4006 */ 4007 static int fec_enet_init(struct net_device *ndev) 4008 { 4009 struct fec_enet_private *fep = netdev_priv(ndev); 4010 struct bufdesc *cbd_base; 4011 dma_addr_t bd_dma; 4012 int bd_size; 4013 unsigned int i; 4014 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 4015 sizeof(struct bufdesc); 4016 unsigned dsize_log2 = __fls(dsize); 4017 int ret; 4018 4019 WARN_ON(dsize != (1 << dsize_log2)); 4020 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 4021 fep->rx_align = 0xf; 4022 fep->tx_align = 0xf; 4023 #else 4024 fep->rx_align = 0x3; 4025 fep->tx_align = 0x3; 4026 #endif 4027 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4028 fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4029 fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT; 4030 fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT; 4031 4032 /* Check mask of the streaming and coherent API */ 4033 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 4034 if (ret < 0) { 4035 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 4036 return ret; 4037 } 4038 4039 ret = fec_enet_alloc_queue(ndev); 4040 if (ret) 4041 return ret; 4042 4043 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 4044 4045 /* Allocate memory for buffer descriptors. */ 4046 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 4047 GFP_KERNEL); 4048 if (!cbd_base) { 4049 ret = -ENOMEM; 4050 goto free_queue_mem; 4051 } 4052 4053 /* Get the Ethernet address */ 4054 ret = fec_get_mac(ndev); 4055 if (ret) 4056 goto free_queue_mem; 4057 4058 /* Set receive and transmit descriptor base. */ 4059 for (i = 0; i < fep->num_rx_queues; i++) { 4060 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 4061 unsigned size = dsize * rxq->bd.ring_size; 4062 4063 rxq->bd.qid = i; 4064 rxq->bd.base = cbd_base; 4065 rxq->bd.cur = cbd_base; 4066 rxq->bd.dma = bd_dma; 4067 rxq->bd.dsize = dsize; 4068 rxq->bd.dsize_log2 = dsize_log2; 4069 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 4070 bd_dma += size; 4071 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4072 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4073 } 4074 4075 for (i = 0; i < fep->num_tx_queues; i++) { 4076 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 4077 unsigned size = dsize * txq->bd.ring_size; 4078 4079 txq->bd.qid = i; 4080 txq->bd.base = cbd_base; 4081 txq->bd.cur = cbd_base; 4082 txq->bd.dma = bd_dma; 4083 txq->bd.dsize = dsize; 4084 txq->bd.dsize_log2 = dsize_log2; 4085 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 4086 bd_dma += size; 4087 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4088 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4089 } 4090 4091 4092 /* The FEC Ethernet specific entries in the device structure */ 4093 ndev->watchdog_timeo = TX_TIMEOUT; 4094 ndev->netdev_ops = &fec_netdev_ops; 4095 ndev->ethtool_ops = &fec_enet_ethtool_ops; 4096 4097 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 4098 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi); 4099 4100 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 4101 /* enable hw VLAN support */ 4102 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 4103 4104 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 4105 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS); 4106 4107 /* enable hw accelerator */ 4108 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 4109 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 4110 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 4111 } 4112 4113 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 4114 fep->tx_align = 0; 4115 fep->rx_align = 0x3f; 4116 } 4117 4118 ndev->hw_features = ndev->features; 4119 4120 if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME)) 4121 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 4122 NETDEV_XDP_ACT_REDIRECT; 4123 4124 fec_restart(ndev); 4125 4126 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 4127 fec_enet_clear_ethtool_stats(ndev); 4128 else 4129 fec_enet_update_ethtool_stats(ndev); 4130 4131 return 0; 4132 4133 free_queue_mem: 4134 fec_enet_free_queue(ndev); 4135 return ret; 4136 } 4137 4138 #ifdef CONFIG_OF 4139 static int fec_reset_phy(struct platform_device *pdev) 4140 { 4141 struct gpio_desc *phy_reset; 4142 int msec = 1, phy_post_delay = 0; 4143 struct device_node *np = pdev->dev.of_node; 4144 int err; 4145 4146 if (!np) 4147 return 0; 4148 4149 err = of_property_read_u32(np, "phy-reset-duration", &msec); 4150 /* A sane reset duration should not be longer than 1s */ 4151 if (!err && msec > 1000) 4152 msec = 1; 4153 4154 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 4155 /* valid reset duration should be less than 1s */ 4156 if (!err && phy_post_delay > 1000) 4157 return -EINVAL; 4158 4159 phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset", 4160 GPIOD_OUT_HIGH); 4161 if (IS_ERR(phy_reset)) 4162 return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset), 4163 "failed to get phy-reset-gpios\n"); 4164 4165 if (!phy_reset) 4166 return 0; 4167 4168 if (msec > 20) 4169 msleep(msec); 4170 else 4171 usleep_range(msec * 1000, msec * 1000 + 1000); 4172 4173 gpiod_set_value_cansleep(phy_reset, 0); 4174 4175 if (!phy_post_delay) 4176 return 0; 4177 4178 if (phy_post_delay > 20) 4179 msleep(phy_post_delay); 4180 else 4181 usleep_range(phy_post_delay * 1000, 4182 phy_post_delay * 1000 + 1000); 4183 4184 return 0; 4185 } 4186 #else /* CONFIG_OF */ 4187 static int fec_reset_phy(struct platform_device *pdev) 4188 { 4189 /* 4190 * In case of platform probe, the reset has been done 4191 * by machine code. 4192 */ 4193 return 0; 4194 } 4195 #endif /* CONFIG_OF */ 4196 4197 static void 4198 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 4199 { 4200 struct device_node *np = pdev->dev.of_node; 4201 4202 *num_tx = *num_rx = 1; 4203 4204 if (!np || !of_device_is_available(np)) 4205 return; 4206 4207 /* parse the num of tx and rx queues */ 4208 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 4209 4210 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 4211 4212 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 4213 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 4214 *num_tx); 4215 *num_tx = 1; 4216 return; 4217 } 4218 4219 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 4220 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 4221 *num_rx); 4222 *num_rx = 1; 4223 return; 4224 } 4225 4226 } 4227 4228 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 4229 { 4230 int irq_cnt = platform_irq_count(pdev); 4231 4232 if (irq_cnt > FEC_IRQ_NUM) 4233 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 4234 else if (irq_cnt == 2) 4235 irq_cnt = 1; /* last for pps */ 4236 else if (irq_cnt <= 0) 4237 irq_cnt = 1; /* At least 1 irq is needed */ 4238 return irq_cnt; 4239 } 4240 4241 static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 4242 { 4243 struct net_device *ndev = platform_get_drvdata(pdev); 4244 struct fec_enet_private *fep = netdev_priv(ndev); 4245 4246 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 4247 fep->wake_irq = fep->irq[2]; 4248 else 4249 fep->wake_irq = fep->irq[0]; 4250 } 4251 4252 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 4253 struct device_node *np) 4254 { 4255 struct device_node *gpr_np; 4256 u32 out_val[3]; 4257 int ret = 0; 4258 4259 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 4260 if (!gpr_np) 4261 return 0; 4262 4263 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 4264 ARRAY_SIZE(out_val)); 4265 if (ret) { 4266 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 4267 goto out; 4268 } 4269 4270 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 4271 if (IS_ERR(fep->stop_gpr.gpr)) { 4272 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 4273 ret = PTR_ERR(fep->stop_gpr.gpr); 4274 fep->stop_gpr.gpr = NULL; 4275 goto out; 4276 } 4277 4278 fep->stop_gpr.reg = out_val[1]; 4279 fep->stop_gpr.bit = out_val[2]; 4280 4281 out: 4282 of_node_put(gpr_np); 4283 4284 return ret; 4285 } 4286 4287 static int 4288 fec_probe(struct platform_device *pdev) 4289 { 4290 struct fec_enet_private *fep; 4291 struct fec_platform_data *pdata; 4292 phy_interface_t interface; 4293 struct net_device *ndev; 4294 int i, irq, ret = 0; 4295 const struct of_device_id *of_id; 4296 static int dev_id; 4297 struct device_node *np = pdev->dev.of_node, *phy_node; 4298 int num_tx_qs; 4299 int num_rx_qs; 4300 char irq_name[8]; 4301 int irq_cnt; 4302 struct fec_devinfo *dev_info; 4303 4304 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 4305 4306 /* Init network device */ 4307 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 4308 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 4309 if (!ndev) 4310 return -ENOMEM; 4311 4312 SET_NETDEV_DEV(ndev, &pdev->dev); 4313 4314 /* setup board info structure */ 4315 fep = netdev_priv(ndev); 4316 4317 of_id = of_match_device(fec_dt_ids, &pdev->dev); 4318 if (of_id) 4319 pdev->id_entry = of_id->data; 4320 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; 4321 if (dev_info) 4322 fep->quirks = dev_info->quirks; 4323 4324 fep->netdev = ndev; 4325 fep->num_rx_queues = num_rx_qs; 4326 fep->num_tx_queues = num_tx_qs; 4327 4328 #if !defined(CONFIG_M5272) 4329 /* default enable pause frame auto negotiation */ 4330 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 4331 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 4332 #endif 4333 4334 /* Select default pin state */ 4335 pinctrl_pm_select_default_state(&pdev->dev); 4336 4337 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 4338 if (IS_ERR(fep->hwp)) { 4339 ret = PTR_ERR(fep->hwp); 4340 goto failed_ioremap; 4341 } 4342 4343 fep->pdev = pdev; 4344 fep->dev_id = dev_id++; 4345 4346 platform_set_drvdata(pdev, ndev); 4347 4348 if ((of_machine_is_compatible("fsl,imx6q") || 4349 of_machine_is_compatible("fsl,imx6dl")) && 4350 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 4351 fep->quirks |= FEC_QUIRK_ERR006687; 4352 4353 ret = fec_enet_ipc_handle_init(fep); 4354 if (ret) 4355 goto failed_ipc_init; 4356 4357 if (of_property_read_bool(np, "fsl,magic-packet")) 4358 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 4359 4360 ret = fec_enet_init_stop_mode(fep, np); 4361 if (ret) 4362 goto failed_stop_mode; 4363 4364 phy_node = of_parse_phandle(np, "phy-handle", 0); 4365 if (!phy_node && of_phy_is_fixed_link(np)) { 4366 ret = of_phy_register_fixed_link(np); 4367 if (ret < 0) { 4368 dev_err(&pdev->dev, 4369 "broken fixed-link specification\n"); 4370 goto failed_phy; 4371 } 4372 phy_node = of_node_get(np); 4373 } 4374 fep->phy_node = phy_node; 4375 4376 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 4377 if (ret) { 4378 pdata = dev_get_platdata(&pdev->dev); 4379 if (pdata) 4380 fep->phy_interface = pdata->phy; 4381 else 4382 fep->phy_interface = PHY_INTERFACE_MODE_MII; 4383 } else { 4384 fep->phy_interface = interface; 4385 } 4386 4387 ret = fec_enet_parse_rgmii_delay(fep, np); 4388 if (ret) 4389 goto failed_rgmii_delay; 4390 4391 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 4392 if (IS_ERR(fep->clk_ipg)) { 4393 ret = PTR_ERR(fep->clk_ipg); 4394 goto failed_clk; 4395 } 4396 4397 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 4398 if (IS_ERR(fep->clk_ahb)) { 4399 ret = PTR_ERR(fep->clk_ahb); 4400 goto failed_clk; 4401 } 4402 4403 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 4404 4405 /* enet_out is optional, depends on board */ 4406 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out"); 4407 if (IS_ERR(fep->clk_enet_out)) { 4408 ret = PTR_ERR(fep->clk_enet_out); 4409 goto failed_clk; 4410 } 4411 4412 fep->ptp_clk_on = false; 4413 mutex_init(&fep->ptp_clk_mutex); 4414 4415 /* clk_ref is optional, depends on board */ 4416 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref"); 4417 if (IS_ERR(fep->clk_ref)) { 4418 ret = PTR_ERR(fep->clk_ref); 4419 goto failed_clk; 4420 } 4421 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 4422 4423 /* clk_2x_txclk is optional, depends on board */ 4424 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 4425 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 4426 if (IS_ERR(fep->clk_2x_txclk)) 4427 fep->clk_2x_txclk = NULL; 4428 } 4429 4430 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 4431 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 4432 if (IS_ERR(fep->clk_ptp)) { 4433 fep->clk_ptp = NULL; 4434 fep->bufdesc_ex = false; 4435 } 4436 4437 ret = fec_enet_clk_enable(ndev, true); 4438 if (ret) 4439 goto failed_clk; 4440 4441 ret = clk_prepare_enable(fep->clk_ipg); 4442 if (ret) 4443 goto failed_clk_ipg; 4444 ret = clk_prepare_enable(fep->clk_ahb); 4445 if (ret) 4446 goto failed_clk_ahb; 4447 4448 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 4449 if (!IS_ERR(fep->reg_phy)) { 4450 ret = regulator_enable(fep->reg_phy); 4451 if (ret) { 4452 dev_err(&pdev->dev, 4453 "Failed to enable phy regulator: %d\n", ret); 4454 goto failed_regulator; 4455 } 4456 } else { 4457 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 4458 ret = -EPROBE_DEFER; 4459 goto failed_regulator; 4460 } 4461 fep->reg_phy = NULL; 4462 } 4463 4464 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 4465 pm_runtime_use_autosuspend(&pdev->dev); 4466 pm_runtime_get_noresume(&pdev->dev); 4467 pm_runtime_set_active(&pdev->dev); 4468 pm_runtime_enable(&pdev->dev); 4469 4470 ret = fec_reset_phy(pdev); 4471 if (ret) 4472 goto failed_reset; 4473 4474 irq_cnt = fec_enet_get_irq_cnt(pdev); 4475 if (fep->bufdesc_ex) 4476 fec_ptp_init(pdev, irq_cnt); 4477 4478 ret = fec_enet_init(ndev); 4479 if (ret) 4480 goto failed_init; 4481 4482 for (i = 0; i < irq_cnt; i++) { 4483 snprintf(irq_name, sizeof(irq_name), "int%d", i); 4484 irq = platform_get_irq_byname_optional(pdev, irq_name); 4485 if (irq < 0) 4486 irq = platform_get_irq(pdev, i); 4487 if (irq < 0) { 4488 ret = irq; 4489 goto failed_irq; 4490 } 4491 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 4492 0, pdev->name, ndev); 4493 if (ret) 4494 goto failed_irq; 4495 4496 fep->irq[i] = irq; 4497 } 4498 4499 /* Decide which interrupt line is wakeup capable */ 4500 fec_enet_get_wakeup_irq(pdev); 4501 4502 ret = fec_enet_mii_init(pdev); 4503 if (ret) 4504 goto failed_mii_init; 4505 4506 /* Carrier starts down, phylib will bring it up */ 4507 netif_carrier_off(ndev); 4508 fec_enet_clk_enable(ndev, false); 4509 pinctrl_pm_select_sleep_state(&pdev->dev); 4510 4511 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN; 4512 4513 ret = register_netdev(ndev); 4514 if (ret) 4515 goto failed_register; 4516 4517 device_init_wakeup(&ndev->dev, fep->wol_flag & 4518 FEC_WOL_HAS_MAGIC_PACKET); 4519 4520 if (fep->bufdesc_ex && fep->ptp_clock) 4521 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 4522 4523 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 4524 4525 pm_runtime_mark_last_busy(&pdev->dev); 4526 pm_runtime_put_autosuspend(&pdev->dev); 4527 4528 return 0; 4529 4530 failed_register: 4531 fec_enet_mii_remove(fep); 4532 failed_mii_init: 4533 failed_irq: 4534 failed_init: 4535 fec_ptp_stop(pdev); 4536 failed_reset: 4537 pm_runtime_put_noidle(&pdev->dev); 4538 pm_runtime_disable(&pdev->dev); 4539 if (fep->reg_phy) 4540 regulator_disable(fep->reg_phy); 4541 failed_regulator: 4542 clk_disable_unprepare(fep->clk_ahb); 4543 failed_clk_ahb: 4544 clk_disable_unprepare(fep->clk_ipg); 4545 failed_clk_ipg: 4546 fec_enet_clk_enable(ndev, false); 4547 failed_clk: 4548 failed_rgmii_delay: 4549 if (of_phy_is_fixed_link(np)) 4550 of_phy_deregister_fixed_link(np); 4551 of_node_put(phy_node); 4552 failed_stop_mode: 4553 failed_ipc_init: 4554 failed_phy: 4555 dev_id--; 4556 failed_ioremap: 4557 free_netdev(ndev); 4558 4559 return ret; 4560 } 4561 4562 static void 4563 fec_drv_remove(struct platform_device *pdev) 4564 { 4565 struct net_device *ndev = platform_get_drvdata(pdev); 4566 struct fec_enet_private *fep = netdev_priv(ndev); 4567 struct device_node *np = pdev->dev.of_node; 4568 int ret; 4569 4570 ret = pm_runtime_get_sync(&pdev->dev); 4571 if (ret < 0) 4572 dev_err(&pdev->dev, 4573 "Failed to resume device in remove callback (%pe)\n", 4574 ERR_PTR(ret)); 4575 4576 cancel_work_sync(&fep->tx_timeout_work); 4577 fec_ptp_stop(pdev); 4578 unregister_netdev(ndev); 4579 fec_enet_mii_remove(fep); 4580 if (fep->reg_phy) 4581 regulator_disable(fep->reg_phy); 4582 4583 if (of_phy_is_fixed_link(np)) 4584 of_phy_deregister_fixed_link(np); 4585 of_node_put(fep->phy_node); 4586 4587 /* After pm_runtime_get_sync() failed, the clks are still off, so skip 4588 * disabling them again. 4589 */ 4590 if (ret >= 0) { 4591 clk_disable_unprepare(fep->clk_ahb); 4592 clk_disable_unprepare(fep->clk_ipg); 4593 } 4594 pm_runtime_put_noidle(&pdev->dev); 4595 pm_runtime_disable(&pdev->dev); 4596 4597 free_netdev(ndev); 4598 } 4599 4600 static int __maybe_unused fec_suspend(struct device *dev) 4601 { 4602 struct net_device *ndev = dev_get_drvdata(dev); 4603 struct fec_enet_private *fep = netdev_priv(ndev); 4604 int ret; 4605 4606 rtnl_lock(); 4607 if (netif_running(ndev)) { 4608 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4609 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4610 phy_stop(ndev->phydev); 4611 napi_disable(&fep->napi); 4612 netif_tx_lock_bh(ndev); 4613 netif_device_detach(ndev); 4614 netif_tx_unlock_bh(ndev); 4615 fec_stop(ndev); 4616 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4617 fec_irqs_disable(ndev); 4618 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4619 } else { 4620 fec_irqs_disable_except_wakeup(ndev); 4621 if (fep->wake_irq > 0) { 4622 disable_irq(fep->wake_irq); 4623 enable_irq_wake(fep->wake_irq); 4624 } 4625 fec_enet_stop_mode(fep, true); 4626 } 4627 /* It's safe to disable clocks since interrupts are masked */ 4628 fec_enet_clk_enable(ndev, false); 4629 4630 fep->rpm_active = !pm_runtime_status_suspended(dev); 4631 if (fep->rpm_active) { 4632 ret = pm_runtime_force_suspend(dev); 4633 if (ret < 0) { 4634 rtnl_unlock(); 4635 return ret; 4636 } 4637 } 4638 } 4639 rtnl_unlock(); 4640 4641 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4642 regulator_disable(fep->reg_phy); 4643 4644 /* SOC supply clock to phy, when clock is disabled, phy link down 4645 * SOC control phy regulator, when regulator is disabled, phy link down 4646 */ 4647 if (fep->clk_enet_out || fep->reg_phy) 4648 fep->link = 0; 4649 4650 return 0; 4651 } 4652 4653 static int __maybe_unused fec_resume(struct device *dev) 4654 { 4655 struct net_device *ndev = dev_get_drvdata(dev); 4656 struct fec_enet_private *fep = netdev_priv(ndev); 4657 int ret; 4658 int val; 4659 4660 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4661 ret = regulator_enable(fep->reg_phy); 4662 if (ret) 4663 return ret; 4664 } 4665 4666 rtnl_lock(); 4667 if (netif_running(ndev)) { 4668 if (fep->rpm_active) 4669 pm_runtime_force_resume(dev); 4670 4671 ret = fec_enet_clk_enable(ndev, true); 4672 if (ret) { 4673 rtnl_unlock(); 4674 goto failed_clk; 4675 } 4676 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4677 fec_enet_stop_mode(fep, false); 4678 if (fep->wake_irq) { 4679 disable_irq_wake(fep->wake_irq); 4680 enable_irq(fep->wake_irq); 4681 } 4682 4683 val = readl(fep->hwp + FEC_ECNTRL); 4684 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4685 writel(val, fep->hwp + FEC_ECNTRL); 4686 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4687 } else { 4688 pinctrl_pm_select_default_state(&fep->pdev->dev); 4689 } 4690 fec_restart(ndev); 4691 netif_tx_lock_bh(ndev); 4692 netif_device_attach(ndev); 4693 netif_tx_unlock_bh(ndev); 4694 napi_enable(&fep->napi); 4695 phy_init_hw(ndev->phydev); 4696 phy_start(ndev->phydev); 4697 } 4698 rtnl_unlock(); 4699 4700 return 0; 4701 4702 failed_clk: 4703 if (fep->reg_phy) 4704 regulator_disable(fep->reg_phy); 4705 return ret; 4706 } 4707 4708 static int __maybe_unused fec_runtime_suspend(struct device *dev) 4709 { 4710 struct net_device *ndev = dev_get_drvdata(dev); 4711 struct fec_enet_private *fep = netdev_priv(ndev); 4712 4713 clk_disable_unprepare(fep->clk_ahb); 4714 clk_disable_unprepare(fep->clk_ipg); 4715 4716 return 0; 4717 } 4718 4719 static int __maybe_unused fec_runtime_resume(struct device *dev) 4720 { 4721 struct net_device *ndev = dev_get_drvdata(dev); 4722 struct fec_enet_private *fep = netdev_priv(ndev); 4723 int ret; 4724 4725 ret = clk_prepare_enable(fep->clk_ahb); 4726 if (ret) 4727 return ret; 4728 ret = clk_prepare_enable(fep->clk_ipg); 4729 if (ret) 4730 goto failed_clk_ipg; 4731 4732 return 0; 4733 4734 failed_clk_ipg: 4735 clk_disable_unprepare(fep->clk_ahb); 4736 return ret; 4737 } 4738 4739 static const struct dev_pm_ops fec_pm_ops = { 4740 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4741 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4742 }; 4743 4744 static struct platform_driver fec_driver = { 4745 .driver = { 4746 .name = DRIVER_NAME, 4747 .pm = &fec_pm_ops, 4748 .of_match_table = fec_dt_ids, 4749 .suppress_bind_attrs = true, 4750 }, 4751 .id_table = fec_devtype, 4752 .probe = fec_probe, 4753 .remove_new = fec_drv_remove, 4754 }; 4755 4756 module_platform_driver(fec_driver); 4757 4758 MODULE_LICENSE("GPL"); 4759