1 /* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 * 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/string.h> 27 #include <linux/ptrace.h> 28 #include <linux/errno.h> 29 #include <linux/ioport.h> 30 #include <linux/slab.h> 31 #include <linux/interrupt.h> 32 #include <linux/init.h> 33 #include <linux/delay.h> 34 #include <linux/netdevice.h> 35 #include <linux/etherdevice.h> 36 #include <linux/skbuff.h> 37 #include <linux/in.h> 38 #include <linux/ip.h> 39 #include <net/ip.h> 40 #include <linux/tcp.h> 41 #include <linux/udp.h> 42 #include <linux/icmp.h> 43 #include <linux/spinlock.h> 44 #include <linux/workqueue.h> 45 #include <linux/bitops.h> 46 #include <linux/io.h> 47 #include <linux/irq.h> 48 #include <linux/clk.h> 49 #include <linux/platform_device.h> 50 #include <linux/phy.h> 51 #include <linux/fec.h> 52 #include <linux/of.h> 53 #include <linux/of_device.h> 54 #include <linux/of_gpio.h> 55 #include <linux/of_net.h> 56 #include <linux/regulator/consumer.h> 57 #include <linux/if_vlan.h> 58 59 #include <asm/cacheflush.h> 60 61 #include "fec.h" 62 63 static void set_multicast_list(struct net_device *ndev); 64 65 #if defined(CONFIG_ARM) 66 #define FEC_ALIGNMENT 0xf 67 #else 68 #define FEC_ALIGNMENT 0x3 69 #endif 70 71 #define DRIVER_NAME "fec" 72 #define FEC_NAPI_WEIGHT 64 73 74 /* Pause frame feild and FIFO threshold */ 75 #define FEC_ENET_FCE (1 << 5) 76 #define FEC_ENET_RSEM_V 0x84 77 #define FEC_ENET_RSFL_V 16 78 #define FEC_ENET_RAEM_V 0x8 79 #define FEC_ENET_RAFL_V 0x8 80 #define FEC_ENET_OPD_V 0xFFF0 81 82 /* Controller is ENET-MAC */ 83 #define FEC_QUIRK_ENET_MAC (1 << 0) 84 /* Controller needs driver to swap frame */ 85 #define FEC_QUIRK_SWAP_FRAME (1 << 1) 86 /* Controller uses gasket */ 87 #define FEC_QUIRK_USE_GASKET (1 << 2) 88 /* Controller has GBIT support */ 89 #define FEC_QUIRK_HAS_GBIT (1 << 3) 90 /* Controller has extend desc buffer */ 91 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) 92 /* Controller has hardware checksum support */ 93 #define FEC_QUIRK_HAS_CSUM (1 << 5) 94 /* Controller has hardware vlan support */ 95 #define FEC_QUIRK_HAS_VLAN (1 << 6) 96 /* ENET IP errata ERR006358 97 * 98 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously 99 * detected as not set during a prior frame transmission, then the 100 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs 101 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in 102 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously 103 * detected as not set during a prior frame transmission, then the 104 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs 105 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in 106 * frames not being transmitted until there is a 0-to-1 transition on 107 * ENET_TDAR[TDAR]. 108 */ 109 #define FEC_QUIRK_ERR006358 (1 << 7) 110 111 static struct platform_device_id fec_devtype[] = { 112 { 113 /* keep it for coldfire */ 114 .name = DRIVER_NAME, 115 .driver_data = 0, 116 }, { 117 .name = "imx25-fec", 118 .driver_data = FEC_QUIRK_USE_GASKET, 119 }, { 120 .name = "imx27-fec", 121 .driver_data = 0, 122 }, { 123 .name = "imx28-fec", 124 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, 125 }, { 126 .name = "imx6q-fec", 127 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 128 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 129 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358, 130 }, { 131 .name = "mvf600-fec", 132 .driver_data = FEC_QUIRK_ENET_MAC, 133 }, { 134 /* sentinel */ 135 } 136 }; 137 MODULE_DEVICE_TABLE(platform, fec_devtype); 138 139 enum imx_fec_type { 140 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 141 IMX27_FEC, /* runs on i.mx27/35/51 */ 142 IMX28_FEC, 143 IMX6Q_FEC, 144 MVF600_FEC, 145 }; 146 147 static const struct of_device_id fec_dt_ids[] = { 148 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 149 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 150 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 151 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 152 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 153 { /* sentinel */ } 154 }; 155 MODULE_DEVICE_TABLE(of, fec_dt_ids); 156 157 static unsigned char macaddr[ETH_ALEN]; 158 module_param_array(macaddr, byte, NULL, 0); 159 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 160 161 #if defined(CONFIG_M5272) 162 /* 163 * Some hardware gets it MAC address out of local flash memory. 164 * if this is non-zero then assume it is the address to get MAC from. 165 */ 166 #if defined(CONFIG_NETtel) 167 #define FEC_FLASHMAC 0xf0006006 168 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 169 #define FEC_FLASHMAC 0xf0006000 170 #elif defined(CONFIG_CANCam) 171 #define FEC_FLASHMAC 0xf0020000 172 #elif defined (CONFIG_M5272C3) 173 #define FEC_FLASHMAC (0xffe04000 + 4) 174 #elif defined(CONFIG_MOD5272) 175 #define FEC_FLASHMAC 0xffc0406b 176 #else 177 #define FEC_FLASHMAC 0 178 #endif 179 #endif /* CONFIG_M5272 */ 180 181 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE) 182 #error "FEC: descriptor ring size constants too large" 183 #endif 184 185 /* Interrupt events/masks. */ 186 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ 187 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ 188 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ 189 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ 190 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ 191 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ 192 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ 193 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ 194 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ 195 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ 196 197 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) 198 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) 199 200 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 201 */ 202 #define PKT_MAXBUF_SIZE 1522 203 #define PKT_MINBUF_SIZE 64 204 #define PKT_MAXBLR_SIZE 1536 205 206 /* FEC receive acceleration */ 207 #define FEC_RACC_IPDIS (1 << 1) 208 #define FEC_RACC_PRODIS (1 << 2) 209 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 210 211 /* 212 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 213 * size bits. Other FEC hardware does not, so we need to take that into 214 * account when setting it. 215 */ 216 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 217 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 218 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 219 #else 220 #define OPT_FRAME_SIZE 0 221 #endif 222 223 /* FEC MII MMFR bits definition */ 224 #define FEC_MMFR_ST (1 << 30) 225 #define FEC_MMFR_OP_READ (2 << 28) 226 #define FEC_MMFR_OP_WRITE (1 << 28) 227 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 228 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 229 #define FEC_MMFR_TA (2 << 16) 230 #define FEC_MMFR_DATA(v) (v & 0xffff) 231 232 #define FEC_MII_TIMEOUT 30000 /* us */ 233 234 /* Transmitter timeout */ 235 #define TX_TIMEOUT (2 * HZ) 236 237 #define FEC_PAUSE_FLAG_AUTONEG 0x1 238 #define FEC_PAUSE_FLAG_ENABLE 0x2 239 240 static int mii_cnt; 241 242 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex) 243 { 244 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; 245 if (is_ex) 246 return (struct bufdesc *)(ex + 1); 247 else 248 return bdp + 1; 249 } 250 251 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex) 252 { 253 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; 254 if (is_ex) 255 return (struct bufdesc *)(ex - 1); 256 else 257 return bdp - 1; 258 } 259 260 static void *swap_buffer(void *bufaddr, int len) 261 { 262 int i; 263 unsigned int *buf = bufaddr; 264 265 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++) 266 *buf = cpu_to_be32(*buf); 267 268 return bufaddr; 269 } 270 271 static int 272 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 273 { 274 /* Only run for packets requiring a checksum. */ 275 if (skb->ip_summed != CHECKSUM_PARTIAL) 276 return 0; 277 278 if (unlikely(skb_cow_head(skb, 0))) 279 return -1; 280 281 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 282 283 return 0; 284 } 285 286 static netdev_tx_t 287 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 288 { 289 struct fec_enet_private *fep = netdev_priv(ndev); 290 const struct platform_device_id *id_entry = 291 platform_get_device_id(fep->pdev); 292 struct bufdesc *bdp, *bdp_pre; 293 void *bufaddr; 294 unsigned short status; 295 unsigned int index; 296 297 /* Fill in a Tx ring entry */ 298 bdp = fep->cur_tx; 299 300 status = bdp->cbd_sc; 301 302 if (status & BD_ENET_TX_READY) { 303 /* Ooops. All transmit buffers are full. Bail out. 304 * This should not happen, since ndev->tbusy should be set. 305 */ 306 netdev_err(ndev, "tx queue full!\n"); 307 return NETDEV_TX_BUSY; 308 } 309 310 /* Protocol checksum off-load for TCP and UDP. */ 311 if (fec_enet_clear_csum(skb, ndev)) { 312 kfree_skb(skb); 313 return NETDEV_TX_OK; 314 } 315 316 /* Clear all of the status flags */ 317 status &= ~BD_ENET_TX_STATS; 318 319 /* Set buffer length and buffer pointer */ 320 bufaddr = skb->data; 321 bdp->cbd_datlen = skb->len; 322 323 /* 324 * On some FEC implementations data must be aligned on 325 * 4-byte boundaries. Use bounce buffers to copy data 326 * and get it aligned. Ugh. 327 */ 328 if (fep->bufdesc_ex) 329 index = (struct bufdesc_ex *)bdp - 330 (struct bufdesc_ex *)fep->tx_bd_base; 331 else 332 index = bdp - fep->tx_bd_base; 333 334 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { 335 memcpy(fep->tx_bounce[index], skb->data, skb->len); 336 bufaddr = fep->tx_bounce[index]; 337 } 338 339 /* 340 * Some design made an incorrect assumption on endian mode of 341 * the system that it's running on. As the result, driver has to 342 * swap every frame going to and coming from the controller. 343 */ 344 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 345 swap_buffer(bufaddr, skb->len); 346 347 /* Save skb pointer */ 348 fep->tx_skbuff[index] = skb; 349 350 /* Push the data cache so the CPM does not get stale memory 351 * data. 352 */ 353 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, 354 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); 355 356 /* Send it on its way. Tell FEC it's ready, interrupt when done, 357 * it's the last BD of the frame, and to put the CRC on the end. 358 */ 359 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR 360 | BD_ENET_TX_LAST | BD_ENET_TX_TC); 361 bdp->cbd_sc = status; 362 363 if (fep->bufdesc_ex) { 364 365 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 366 ebdp->cbd_bdu = 0; 367 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 368 fep->hwts_tx_en)) { 369 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT); 370 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 371 } else { 372 ebdp->cbd_esc = BD_ENET_TX_INT; 373 374 /* Enable protocol checksum flags 375 * We do not bother with the IP Checksum bits as they 376 * are done by the kernel 377 */ 378 if (skb->ip_summed == CHECKSUM_PARTIAL) 379 ebdp->cbd_esc |= BD_ENET_TX_PINS; 380 } 381 } 382 383 bdp_pre = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); 384 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) && 385 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) { 386 fep->delay_work.trig_tx = true; 387 schedule_delayed_work(&(fep->delay_work.delay_work), 388 msecs_to_jiffies(1)); 389 } 390 391 /* If this was the last BD in the ring, start at the beginning again. */ 392 if (status & BD_ENET_TX_WRAP) 393 bdp = fep->tx_bd_base; 394 else 395 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 396 397 fep->cur_tx = bdp; 398 399 if (fep->cur_tx == fep->dirty_tx) 400 netif_stop_queue(ndev); 401 402 /* Trigger transmission start */ 403 writel(0, fep->hwp + FEC_X_DES_ACTIVE); 404 405 skb_tx_timestamp(skb); 406 407 return NETDEV_TX_OK; 408 } 409 410 /* Init RX & TX buffer descriptors 411 */ 412 static void fec_enet_bd_init(struct net_device *dev) 413 { 414 struct fec_enet_private *fep = netdev_priv(dev); 415 struct bufdesc *bdp; 416 unsigned int i; 417 418 /* Initialize the receive buffer descriptors. */ 419 bdp = fep->rx_bd_base; 420 for (i = 0; i < RX_RING_SIZE; i++) { 421 422 /* Initialize the BD for every fragment in the page. */ 423 if (bdp->cbd_bufaddr) 424 bdp->cbd_sc = BD_ENET_RX_EMPTY; 425 else 426 bdp->cbd_sc = 0; 427 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 428 } 429 430 /* Set the last buffer to wrap */ 431 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); 432 bdp->cbd_sc |= BD_SC_WRAP; 433 434 fep->cur_rx = fep->rx_bd_base; 435 436 /* ...and the same for transmit */ 437 bdp = fep->tx_bd_base; 438 fep->cur_tx = bdp; 439 for (i = 0; i < TX_RING_SIZE; i++) { 440 441 /* Initialize the BD for every fragment in the page. */ 442 bdp->cbd_sc = 0; 443 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) { 444 dev_kfree_skb_any(fep->tx_skbuff[i]); 445 fep->tx_skbuff[i] = NULL; 446 } 447 bdp->cbd_bufaddr = 0; 448 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 449 } 450 451 /* Set the last buffer to wrap */ 452 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); 453 bdp->cbd_sc |= BD_SC_WRAP; 454 fep->dirty_tx = bdp; 455 } 456 457 /* This function is called to start or restart the FEC during a link 458 * change. This only happens when switching between half and full 459 * duplex. 460 */ 461 static void 462 fec_restart(struct net_device *ndev, int duplex) 463 { 464 struct fec_enet_private *fep = netdev_priv(ndev); 465 const struct platform_device_id *id_entry = 466 platform_get_device_id(fep->pdev); 467 int i; 468 u32 val; 469 u32 temp_mac[2]; 470 u32 rcntl = OPT_FRAME_SIZE | 0x04; 471 u32 ecntl = 0x2; /* ETHEREN */ 472 473 if (netif_running(ndev)) { 474 netif_device_detach(ndev); 475 napi_disable(&fep->napi); 476 netif_stop_queue(ndev); 477 netif_tx_lock_bh(ndev); 478 } 479 480 /* Whack a reset. We should wait for this. */ 481 writel(1, fep->hwp + FEC_ECNTRL); 482 udelay(10); 483 484 /* 485 * enet-mac reset will reset mac address registers too, 486 * so need to reconfigure it. 487 */ 488 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 489 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 490 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); 491 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); 492 } 493 494 /* Clear any outstanding interrupt. */ 495 writel(0xffc00000, fep->hwp + FEC_IEVENT); 496 497 /* Setup multicast filter. */ 498 set_multicast_list(ndev); 499 #ifndef CONFIG_M5272 500 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 501 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 502 #endif 503 504 /* Set maximum receive buffer size. */ 505 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); 506 507 fec_enet_bd_init(ndev); 508 509 /* Set receive and transmit descriptor base. */ 510 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); 511 if (fep->bufdesc_ex) 512 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex) 513 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); 514 else 515 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) 516 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); 517 518 519 for (i = 0; i <= TX_RING_MOD_MASK; i++) { 520 if (fep->tx_skbuff[i]) { 521 dev_kfree_skb_any(fep->tx_skbuff[i]); 522 fep->tx_skbuff[i] = NULL; 523 } 524 } 525 526 /* Enable MII mode */ 527 if (duplex) { 528 /* FD enable */ 529 writel(0x04, fep->hwp + FEC_X_CNTRL); 530 } else { 531 /* No Rcv on Xmit */ 532 rcntl |= 0x02; 533 writel(0x0, fep->hwp + FEC_X_CNTRL); 534 } 535 536 fep->full_duplex = duplex; 537 538 /* Set MII speed */ 539 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 540 541 #if !defined(CONFIG_M5272) 542 /* set RX checksum */ 543 val = readl(fep->hwp + FEC_RACC); 544 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 545 val |= FEC_RACC_OPTIONS; 546 else 547 val &= ~FEC_RACC_OPTIONS; 548 writel(val, fep->hwp + FEC_RACC); 549 #endif 550 551 /* 552 * The phy interface and speed need to get configured 553 * differently on enet-mac. 554 */ 555 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 556 /* Enable flow control and length check */ 557 rcntl |= 0x40000000 | 0x00000020; 558 559 /* RGMII, RMII or MII */ 560 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) 561 rcntl |= (1 << 6); 562 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 563 rcntl |= (1 << 8); 564 else 565 rcntl &= ~(1 << 8); 566 567 /* 1G, 100M or 10M */ 568 if (fep->phy_dev) { 569 if (fep->phy_dev->speed == SPEED_1000) 570 ecntl |= (1 << 5); 571 else if (fep->phy_dev->speed == SPEED_100) 572 rcntl &= ~(1 << 9); 573 else 574 rcntl |= (1 << 9); 575 } 576 } else { 577 #ifdef FEC_MIIGSK_ENR 578 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { 579 u32 cfgr; 580 /* disable the gasket and wait */ 581 writel(0, fep->hwp + FEC_MIIGSK_ENR); 582 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 583 udelay(1); 584 585 /* 586 * configure the gasket: 587 * RMII, 50 MHz, no loopback, no echo 588 * MII, 25 MHz, no loopback, no echo 589 */ 590 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 591 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 592 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) 593 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 594 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 595 596 /* re-enable the gasket */ 597 writel(2, fep->hwp + FEC_MIIGSK_ENR); 598 } 599 #endif 600 } 601 602 #if !defined(CONFIG_M5272) 603 /* enable pause frame*/ 604 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 605 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 606 fep->phy_dev && fep->phy_dev->pause)) { 607 rcntl |= FEC_ENET_FCE; 608 609 /* set FIFO threshold parameter to reduce overrun */ 610 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 611 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 612 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 613 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 614 615 /* OPD */ 616 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 617 } else { 618 rcntl &= ~FEC_ENET_FCE; 619 } 620 #endif /* !defined(CONFIG_M5272) */ 621 622 writel(rcntl, fep->hwp + FEC_R_CNTRL); 623 624 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 625 /* enable ENET endian swap */ 626 ecntl |= (1 << 8); 627 /* enable ENET store and forward mode */ 628 writel(1 << 8, fep->hwp + FEC_X_WMRK); 629 } 630 631 if (fep->bufdesc_ex) 632 ecntl |= (1 << 4); 633 634 #ifndef CONFIG_M5272 635 /* Enable the MIB statistic event counters */ 636 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 637 #endif 638 639 /* And last, enable the transmit and receive processing */ 640 writel(ecntl, fep->hwp + FEC_ECNTRL); 641 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 642 643 if (fep->bufdesc_ex) 644 fec_ptp_start_cyclecounter(ndev); 645 646 /* Enable interrupts we wish to service */ 647 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 648 649 if (netif_running(ndev)) { 650 netif_tx_unlock_bh(ndev); 651 netif_wake_queue(ndev); 652 napi_enable(&fep->napi); 653 netif_device_attach(ndev); 654 } 655 } 656 657 static void 658 fec_stop(struct net_device *ndev) 659 { 660 struct fec_enet_private *fep = netdev_priv(ndev); 661 const struct platform_device_id *id_entry = 662 platform_get_device_id(fep->pdev); 663 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 664 665 /* We cannot expect a graceful transmit stop without link !!! */ 666 if (fep->link) { 667 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 668 udelay(10); 669 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 670 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 671 } 672 673 /* Whack a reset. We should wait for this. */ 674 writel(1, fep->hwp + FEC_ECNTRL); 675 udelay(10); 676 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 677 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 678 679 /* We have to keep ENET enabled to have MII interrupt stay working */ 680 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 681 writel(2, fep->hwp + FEC_ECNTRL); 682 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 683 } 684 } 685 686 687 static void 688 fec_timeout(struct net_device *ndev) 689 { 690 struct fec_enet_private *fep = netdev_priv(ndev); 691 692 ndev->stats.tx_errors++; 693 694 fep->delay_work.timeout = true; 695 schedule_delayed_work(&(fep->delay_work.delay_work), 0); 696 } 697 698 static void fec_enet_work(struct work_struct *work) 699 { 700 struct fec_enet_private *fep = 701 container_of(work, 702 struct fec_enet_private, 703 delay_work.delay_work.work); 704 705 if (fep->delay_work.timeout) { 706 fep->delay_work.timeout = false; 707 fec_restart(fep->netdev, fep->full_duplex); 708 netif_wake_queue(fep->netdev); 709 } 710 711 if (fep->delay_work.trig_tx) { 712 fep->delay_work.trig_tx = false; 713 writel(0, fep->hwp + FEC_X_DES_ACTIVE); 714 } 715 } 716 717 static void 718 fec_enet_tx(struct net_device *ndev) 719 { 720 struct fec_enet_private *fep; 721 struct bufdesc *bdp; 722 unsigned short status; 723 struct sk_buff *skb; 724 int index = 0; 725 726 fep = netdev_priv(ndev); 727 bdp = fep->dirty_tx; 728 729 /* get next bdp of dirty_tx */ 730 if (bdp->cbd_sc & BD_ENET_TX_WRAP) 731 bdp = fep->tx_bd_base; 732 else 733 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 734 735 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { 736 737 /* current queue is empty */ 738 if (bdp == fep->cur_tx) 739 break; 740 741 if (fep->bufdesc_ex) 742 index = (struct bufdesc_ex *)bdp - 743 (struct bufdesc_ex *)fep->tx_bd_base; 744 else 745 index = bdp - fep->tx_bd_base; 746 747 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 748 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); 749 bdp->cbd_bufaddr = 0; 750 751 skb = fep->tx_skbuff[index]; 752 753 /* Check for errors. */ 754 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 755 BD_ENET_TX_RL | BD_ENET_TX_UN | 756 BD_ENET_TX_CSL)) { 757 ndev->stats.tx_errors++; 758 if (status & BD_ENET_TX_HB) /* No heartbeat */ 759 ndev->stats.tx_heartbeat_errors++; 760 if (status & BD_ENET_TX_LC) /* Late collision */ 761 ndev->stats.tx_window_errors++; 762 if (status & BD_ENET_TX_RL) /* Retrans limit */ 763 ndev->stats.tx_aborted_errors++; 764 if (status & BD_ENET_TX_UN) /* Underrun */ 765 ndev->stats.tx_fifo_errors++; 766 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 767 ndev->stats.tx_carrier_errors++; 768 } else { 769 ndev->stats.tx_packets++; 770 ndev->stats.tx_bytes += bdp->cbd_datlen; 771 } 772 773 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 774 fep->bufdesc_ex) { 775 struct skb_shared_hwtstamps shhwtstamps; 776 unsigned long flags; 777 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 778 779 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 780 spin_lock_irqsave(&fep->tmreg_lock, flags); 781 shhwtstamps.hwtstamp = ns_to_ktime( 782 timecounter_cyc2time(&fep->tc, ebdp->ts)); 783 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 784 skb_tstamp_tx(skb, &shhwtstamps); 785 } 786 787 if (status & BD_ENET_TX_READY) 788 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n"); 789 790 /* Deferred means some collisions occurred during transmit, 791 * but we eventually sent the packet OK. 792 */ 793 if (status & BD_ENET_TX_DEF) 794 ndev->stats.collisions++; 795 796 /* Free the sk buffer associated with this last transmit */ 797 dev_kfree_skb_any(skb); 798 fep->tx_skbuff[index] = NULL; 799 800 fep->dirty_tx = bdp; 801 802 /* Update pointer to next buffer descriptor to be transmitted */ 803 if (status & BD_ENET_TX_WRAP) 804 bdp = fep->tx_bd_base; 805 else 806 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 807 808 /* Since we have freed up a buffer, the ring is no longer full 809 */ 810 if (fep->dirty_tx != fep->cur_tx) { 811 if (netif_queue_stopped(ndev)) 812 netif_wake_queue(ndev); 813 } 814 } 815 return; 816 } 817 818 819 /* During a receive, the cur_rx points to the current incoming buffer. 820 * When we update through the ring, if the next incoming buffer has 821 * not been given to the system, we just set the empty indicator, 822 * effectively tossing the packet. 823 */ 824 static int 825 fec_enet_rx(struct net_device *ndev, int budget) 826 { 827 struct fec_enet_private *fep = netdev_priv(ndev); 828 const struct platform_device_id *id_entry = 829 platform_get_device_id(fep->pdev); 830 struct bufdesc *bdp; 831 unsigned short status; 832 struct sk_buff *skb; 833 ushort pkt_len; 834 __u8 *data; 835 int pkt_received = 0; 836 struct bufdesc_ex *ebdp = NULL; 837 bool vlan_packet_rcvd = false; 838 u16 vlan_tag; 839 840 #ifdef CONFIG_M532x 841 flush_cache_all(); 842 #endif 843 844 /* First, grab all of the stats for the incoming packet. 845 * These get messed up if we get called due to a busy condition. 846 */ 847 bdp = fep->cur_rx; 848 849 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { 850 851 if (pkt_received >= budget) 852 break; 853 pkt_received++; 854 855 /* Since we have allocated space to hold a complete frame, 856 * the last indicator should be set. 857 */ 858 if ((status & BD_ENET_RX_LAST) == 0) 859 netdev_err(ndev, "rcv is not +last\n"); 860 861 if (!fep->opened) 862 goto rx_processing_done; 863 864 /* Check for errors. */ 865 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 866 BD_ENET_RX_CR | BD_ENET_RX_OV)) { 867 ndev->stats.rx_errors++; 868 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { 869 /* Frame too long or too short. */ 870 ndev->stats.rx_length_errors++; 871 } 872 if (status & BD_ENET_RX_NO) /* Frame alignment */ 873 ndev->stats.rx_frame_errors++; 874 if (status & BD_ENET_RX_CR) /* CRC Error */ 875 ndev->stats.rx_crc_errors++; 876 if (status & BD_ENET_RX_OV) /* FIFO overrun */ 877 ndev->stats.rx_fifo_errors++; 878 } 879 880 /* Report late collisions as a frame error. 881 * On this error, the BD is closed, but we don't know what we 882 * have in the buffer. So, just drop this frame on the floor. 883 */ 884 if (status & BD_ENET_RX_CL) { 885 ndev->stats.rx_errors++; 886 ndev->stats.rx_frame_errors++; 887 goto rx_processing_done; 888 } 889 890 /* Process the incoming frame. */ 891 ndev->stats.rx_packets++; 892 pkt_len = bdp->cbd_datlen; 893 ndev->stats.rx_bytes += pkt_len; 894 data = (__u8*)__va(bdp->cbd_bufaddr); 895 896 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 897 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); 898 899 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 900 swap_buffer(data, pkt_len); 901 902 /* Extract the enhanced buffer descriptor */ 903 ebdp = NULL; 904 if (fep->bufdesc_ex) 905 ebdp = (struct bufdesc_ex *)bdp; 906 907 /* If this is a VLAN packet remove the VLAN Tag */ 908 vlan_packet_rcvd = false; 909 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 910 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) { 911 /* Push and remove the vlan tag */ 912 struct vlan_hdr *vlan_header = 913 (struct vlan_hdr *) (data + ETH_HLEN); 914 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 915 pkt_len -= VLAN_HLEN; 916 917 vlan_packet_rcvd = true; 918 } 919 920 /* This does 16 byte alignment, exactly what we need. 921 * The packet length includes FCS, but we don't want to 922 * include that when passing upstream as it messes up 923 * bridging applications. 924 */ 925 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); 926 927 if (unlikely(!skb)) { 928 ndev->stats.rx_dropped++; 929 } else { 930 int payload_offset = (2 * ETH_ALEN); 931 skb_reserve(skb, NET_IP_ALIGN); 932 skb_put(skb, pkt_len - 4); /* Make room */ 933 934 /* Extract the frame data without the VLAN header. */ 935 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN)); 936 if (vlan_packet_rcvd) 937 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN; 938 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN), 939 data + payload_offset, 940 pkt_len - 4 - (2 * ETH_ALEN)); 941 942 skb->protocol = eth_type_trans(skb, ndev); 943 944 /* Get receive timestamp from the skb */ 945 if (fep->hwts_rx_en && fep->bufdesc_ex) { 946 struct skb_shared_hwtstamps *shhwtstamps = 947 skb_hwtstamps(skb); 948 unsigned long flags; 949 950 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 951 952 spin_lock_irqsave(&fep->tmreg_lock, flags); 953 shhwtstamps->hwtstamp = ns_to_ktime( 954 timecounter_cyc2time(&fep->tc, ebdp->ts)); 955 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 956 } 957 958 if (fep->bufdesc_ex && 959 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 960 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) { 961 /* don't check it */ 962 skb->ip_summed = CHECKSUM_UNNECESSARY; 963 } else { 964 skb_checksum_none_assert(skb); 965 } 966 } 967 968 /* Handle received VLAN packets */ 969 if (vlan_packet_rcvd) 970 __vlan_hwaccel_put_tag(skb, 971 htons(ETH_P_8021Q), 972 vlan_tag); 973 974 if (!skb_defer_rx_timestamp(skb)) 975 napi_gro_receive(&fep->napi, skb); 976 } 977 978 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data, 979 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); 980 rx_processing_done: 981 /* Clear the status flags for this buffer */ 982 status &= ~BD_ENET_RX_STATS; 983 984 /* Mark the buffer empty */ 985 status |= BD_ENET_RX_EMPTY; 986 bdp->cbd_sc = status; 987 988 if (fep->bufdesc_ex) { 989 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 990 991 ebdp->cbd_esc = BD_ENET_RX_INT; 992 ebdp->cbd_prot = 0; 993 ebdp->cbd_bdu = 0; 994 } 995 996 /* Update BD pointer to next entry */ 997 if (status & BD_ENET_RX_WRAP) 998 bdp = fep->rx_bd_base; 999 else 1000 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 1001 /* Doing this here will keep the FEC running while we process 1002 * incoming frames. On a heavily loaded network, we should be 1003 * able to keep up at the expense of system resources. 1004 */ 1005 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 1006 } 1007 fep->cur_rx = bdp; 1008 1009 return pkt_received; 1010 } 1011 1012 static irqreturn_t 1013 fec_enet_interrupt(int irq, void *dev_id) 1014 { 1015 struct net_device *ndev = dev_id; 1016 struct fec_enet_private *fep = netdev_priv(ndev); 1017 uint int_events; 1018 irqreturn_t ret = IRQ_NONE; 1019 1020 do { 1021 int_events = readl(fep->hwp + FEC_IEVENT); 1022 writel(int_events, fep->hwp + FEC_IEVENT); 1023 1024 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) { 1025 ret = IRQ_HANDLED; 1026 1027 /* Disable the RX interrupt */ 1028 if (napi_schedule_prep(&fep->napi)) { 1029 writel(FEC_RX_DISABLED_IMASK, 1030 fep->hwp + FEC_IMASK); 1031 __napi_schedule(&fep->napi); 1032 } 1033 } 1034 1035 if (int_events & FEC_ENET_MII) { 1036 ret = IRQ_HANDLED; 1037 complete(&fep->mdio_done); 1038 } 1039 } while (int_events); 1040 1041 return ret; 1042 } 1043 1044 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1045 { 1046 struct net_device *ndev = napi->dev; 1047 int pkts = fec_enet_rx(ndev, budget); 1048 struct fec_enet_private *fep = netdev_priv(ndev); 1049 1050 fec_enet_tx(ndev); 1051 1052 if (pkts < budget) { 1053 napi_complete(napi); 1054 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1055 } 1056 return pkts; 1057 } 1058 1059 /* ------------------------------------------------------------------------- */ 1060 static void fec_get_mac(struct net_device *ndev) 1061 { 1062 struct fec_enet_private *fep = netdev_priv(ndev); 1063 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1064 unsigned char *iap, tmpaddr[ETH_ALEN]; 1065 1066 /* 1067 * try to get mac address in following order: 1068 * 1069 * 1) module parameter via kernel command line in form 1070 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1071 */ 1072 iap = macaddr; 1073 1074 /* 1075 * 2) from device tree data 1076 */ 1077 if (!is_valid_ether_addr(iap)) { 1078 struct device_node *np = fep->pdev->dev.of_node; 1079 if (np) { 1080 const char *mac = of_get_mac_address(np); 1081 if (mac) 1082 iap = (unsigned char *) mac; 1083 } 1084 } 1085 1086 /* 1087 * 3) from flash or fuse (via platform data) 1088 */ 1089 if (!is_valid_ether_addr(iap)) { 1090 #ifdef CONFIG_M5272 1091 if (FEC_FLASHMAC) 1092 iap = (unsigned char *)FEC_FLASHMAC; 1093 #else 1094 if (pdata) 1095 iap = (unsigned char *)&pdata->mac; 1096 #endif 1097 } 1098 1099 /* 1100 * 4) FEC mac registers set by bootloader 1101 */ 1102 if (!is_valid_ether_addr(iap)) { 1103 *((unsigned long *) &tmpaddr[0]) = 1104 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); 1105 *((unsigned short *) &tmpaddr[4]) = 1106 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1107 iap = &tmpaddr[0]; 1108 } 1109 1110 /* 1111 * 5) random mac address 1112 */ 1113 if (!is_valid_ether_addr(iap)) { 1114 /* Report it and use a random ethernet address instead */ 1115 netdev_err(ndev, "Invalid MAC address: %pM\n", iap); 1116 eth_hw_addr_random(ndev); 1117 netdev_info(ndev, "Using random MAC address: %pM\n", 1118 ndev->dev_addr); 1119 return; 1120 } 1121 1122 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1123 1124 /* Adjust MAC if using macaddr */ 1125 if (iap == macaddr) 1126 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1127 } 1128 1129 /* ------------------------------------------------------------------------- */ 1130 1131 /* 1132 * Phy section 1133 */ 1134 static void fec_enet_adjust_link(struct net_device *ndev) 1135 { 1136 struct fec_enet_private *fep = netdev_priv(ndev); 1137 struct phy_device *phy_dev = fep->phy_dev; 1138 int status_change = 0; 1139 1140 /* Prevent a state halted on mii error */ 1141 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 1142 phy_dev->state = PHY_RESUMING; 1143 return; 1144 } 1145 1146 if (phy_dev->link) { 1147 if (!fep->link) { 1148 fep->link = phy_dev->link; 1149 status_change = 1; 1150 } 1151 1152 if (fep->full_duplex != phy_dev->duplex) 1153 status_change = 1; 1154 1155 if (phy_dev->speed != fep->speed) { 1156 fep->speed = phy_dev->speed; 1157 status_change = 1; 1158 } 1159 1160 /* if any of the above changed restart the FEC */ 1161 if (status_change) 1162 fec_restart(ndev, phy_dev->duplex); 1163 } else { 1164 if (fep->link) { 1165 fec_stop(ndev); 1166 fep->link = phy_dev->link; 1167 status_change = 1; 1168 } 1169 } 1170 1171 if (status_change) 1172 phy_print_status(phy_dev); 1173 } 1174 1175 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1176 { 1177 struct fec_enet_private *fep = bus->priv; 1178 unsigned long time_left; 1179 1180 fep->mii_timeout = 0; 1181 init_completion(&fep->mdio_done); 1182 1183 /* start a read op */ 1184 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 1185 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1186 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1187 1188 /* wait for end of transfer */ 1189 time_left = wait_for_completion_timeout(&fep->mdio_done, 1190 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1191 if (time_left == 0) { 1192 fep->mii_timeout = 1; 1193 netdev_err(fep->netdev, "MDIO read timeout\n"); 1194 return -ETIMEDOUT; 1195 } 1196 1197 /* return value */ 1198 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1199 } 1200 1201 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1202 u16 value) 1203 { 1204 struct fec_enet_private *fep = bus->priv; 1205 unsigned long time_left; 1206 1207 fep->mii_timeout = 0; 1208 init_completion(&fep->mdio_done); 1209 1210 /* start a write op */ 1211 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 1212 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1213 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1214 fep->hwp + FEC_MII_DATA); 1215 1216 /* wait for end of transfer */ 1217 time_left = wait_for_completion_timeout(&fep->mdio_done, 1218 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1219 if (time_left == 0) { 1220 fep->mii_timeout = 1; 1221 netdev_err(fep->netdev, "MDIO write timeout\n"); 1222 return -ETIMEDOUT; 1223 } 1224 1225 return 0; 1226 } 1227 1228 static int fec_enet_mdio_reset(struct mii_bus *bus) 1229 { 1230 return 0; 1231 } 1232 1233 static int fec_enet_mii_probe(struct net_device *ndev) 1234 { 1235 struct fec_enet_private *fep = netdev_priv(ndev); 1236 const struct platform_device_id *id_entry = 1237 platform_get_device_id(fep->pdev); 1238 struct phy_device *phy_dev = NULL; 1239 char mdio_bus_id[MII_BUS_ID_SIZE]; 1240 char phy_name[MII_BUS_ID_SIZE + 3]; 1241 int phy_id; 1242 int dev_id = fep->dev_id; 1243 1244 fep->phy_dev = NULL; 1245 1246 /* check for attached phy */ 1247 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1248 if ((fep->mii_bus->phy_mask & (1 << phy_id))) 1249 continue; 1250 if (fep->mii_bus->phy_map[phy_id] == NULL) 1251 continue; 1252 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) 1253 continue; 1254 if (dev_id--) 1255 continue; 1256 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1257 break; 1258 } 1259 1260 if (phy_id >= PHY_MAX_ADDR) { 1261 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1262 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 1263 phy_id = 0; 1264 } 1265 1266 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); 1267 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 1268 fep->phy_interface); 1269 if (IS_ERR(phy_dev)) { 1270 netdev_err(ndev, "could not attach to PHY\n"); 1271 return PTR_ERR(phy_dev); 1272 } 1273 1274 /* mask with MAC supported features */ 1275 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) { 1276 phy_dev->supported &= PHY_GBIT_FEATURES; 1277 #if !defined(CONFIG_M5272) 1278 phy_dev->supported |= SUPPORTED_Pause; 1279 #endif 1280 } 1281 else 1282 phy_dev->supported &= PHY_BASIC_FEATURES; 1283 1284 phy_dev->advertising = phy_dev->supported; 1285 1286 fep->phy_dev = phy_dev; 1287 fep->link = 0; 1288 fep->full_duplex = 0; 1289 1290 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 1291 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), 1292 fep->phy_dev->irq); 1293 1294 return 0; 1295 } 1296 1297 static int fec_enet_mii_init(struct platform_device *pdev) 1298 { 1299 static struct mii_bus *fec0_mii_bus; 1300 struct net_device *ndev = platform_get_drvdata(pdev); 1301 struct fec_enet_private *fep = netdev_priv(ndev); 1302 const struct platform_device_id *id_entry = 1303 platform_get_device_id(fep->pdev); 1304 int err = -ENXIO, i; 1305 1306 /* 1307 * The dual fec interfaces are not equivalent with enet-mac. 1308 * Here are the differences: 1309 * 1310 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1311 * - fec0 acts as the 1588 time master while fec1 is slave 1312 * - external phys can only be configured by fec0 1313 * 1314 * That is to say fec1 can not work independently. It only works 1315 * when fec0 is working. The reason behind this design is that the 1316 * second interface is added primarily for Switch mode. 1317 * 1318 * Because of the last point above, both phys are attached on fec0 1319 * mdio interface in board design, and need to be configured by 1320 * fec0 mii_bus. 1321 */ 1322 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { 1323 /* fec1 uses fec0 mii_bus */ 1324 if (mii_cnt && fec0_mii_bus) { 1325 fep->mii_bus = fec0_mii_bus; 1326 mii_cnt++; 1327 return 0; 1328 } 1329 return -ENOENT; 1330 } 1331 1332 fep->mii_timeout = 0; 1333 1334 /* 1335 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 1336 * 1337 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 1338 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 1339 * Reference Manual has an error on this, and gets fixed on i.MX6Q 1340 * document. 1341 */ 1342 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000); 1343 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1344 fep->phy_speed--; 1345 fep->phy_speed <<= 1; 1346 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1347 1348 fep->mii_bus = mdiobus_alloc(); 1349 if (fep->mii_bus == NULL) { 1350 err = -ENOMEM; 1351 goto err_out; 1352 } 1353 1354 fep->mii_bus->name = "fec_enet_mii_bus"; 1355 fep->mii_bus->read = fec_enet_mdio_read; 1356 fep->mii_bus->write = fec_enet_mdio_write; 1357 fep->mii_bus->reset = fec_enet_mdio_reset; 1358 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1359 pdev->name, fep->dev_id + 1); 1360 fep->mii_bus->priv = fep; 1361 fep->mii_bus->parent = &pdev->dev; 1362 1363 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 1364 if (!fep->mii_bus->irq) { 1365 err = -ENOMEM; 1366 goto err_out_free_mdiobus; 1367 } 1368 1369 for (i = 0; i < PHY_MAX_ADDR; i++) 1370 fep->mii_bus->irq[i] = PHY_POLL; 1371 1372 if (mdiobus_register(fep->mii_bus)) 1373 goto err_out_free_mdio_irq; 1374 1375 mii_cnt++; 1376 1377 /* save fec0 mii_bus */ 1378 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1379 fec0_mii_bus = fep->mii_bus; 1380 1381 return 0; 1382 1383 err_out_free_mdio_irq: 1384 kfree(fep->mii_bus->irq); 1385 err_out_free_mdiobus: 1386 mdiobus_free(fep->mii_bus); 1387 err_out: 1388 return err; 1389 } 1390 1391 static void fec_enet_mii_remove(struct fec_enet_private *fep) 1392 { 1393 if (--mii_cnt == 0) { 1394 mdiobus_unregister(fep->mii_bus); 1395 kfree(fep->mii_bus->irq); 1396 mdiobus_free(fep->mii_bus); 1397 } 1398 } 1399 1400 static int fec_enet_get_settings(struct net_device *ndev, 1401 struct ethtool_cmd *cmd) 1402 { 1403 struct fec_enet_private *fep = netdev_priv(ndev); 1404 struct phy_device *phydev = fep->phy_dev; 1405 1406 if (!phydev) 1407 return -ENODEV; 1408 1409 return phy_ethtool_gset(phydev, cmd); 1410 } 1411 1412 static int fec_enet_set_settings(struct net_device *ndev, 1413 struct ethtool_cmd *cmd) 1414 { 1415 struct fec_enet_private *fep = netdev_priv(ndev); 1416 struct phy_device *phydev = fep->phy_dev; 1417 1418 if (!phydev) 1419 return -ENODEV; 1420 1421 return phy_ethtool_sset(phydev, cmd); 1422 } 1423 1424 static void fec_enet_get_drvinfo(struct net_device *ndev, 1425 struct ethtool_drvinfo *info) 1426 { 1427 struct fec_enet_private *fep = netdev_priv(ndev); 1428 1429 strlcpy(info->driver, fep->pdev->dev.driver->name, 1430 sizeof(info->driver)); 1431 strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); 1432 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 1433 } 1434 1435 static int fec_enet_get_ts_info(struct net_device *ndev, 1436 struct ethtool_ts_info *info) 1437 { 1438 struct fec_enet_private *fep = netdev_priv(ndev); 1439 1440 if (fep->bufdesc_ex) { 1441 1442 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1443 SOF_TIMESTAMPING_RX_SOFTWARE | 1444 SOF_TIMESTAMPING_SOFTWARE | 1445 SOF_TIMESTAMPING_TX_HARDWARE | 1446 SOF_TIMESTAMPING_RX_HARDWARE | 1447 SOF_TIMESTAMPING_RAW_HARDWARE; 1448 if (fep->ptp_clock) 1449 info->phc_index = ptp_clock_index(fep->ptp_clock); 1450 else 1451 info->phc_index = -1; 1452 1453 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 1454 (1 << HWTSTAMP_TX_ON); 1455 1456 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 1457 (1 << HWTSTAMP_FILTER_ALL); 1458 return 0; 1459 } else { 1460 return ethtool_op_get_ts_info(ndev, info); 1461 } 1462 } 1463 1464 #if !defined(CONFIG_M5272) 1465 1466 static void fec_enet_get_pauseparam(struct net_device *ndev, 1467 struct ethtool_pauseparam *pause) 1468 { 1469 struct fec_enet_private *fep = netdev_priv(ndev); 1470 1471 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 1472 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 1473 pause->rx_pause = pause->tx_pause; 1474 } 1475 1476 static int fec_enet_set_pauseparam(struct net_device *ndev, 1477 struct ethtool_pauseparam *pause) 1478 { 1479 struct fec_enet_private *fep = netdev_priv(ndev); 1480 1481 if (pause->tx_pause != pause->rx_pause) { 1482 netdev_info(ndev, 1483 "hardware only support enable/disable both tx and rx"); 1484 return -EINVAL; 1485 } 1486 1487 fep->pause_flag = 0; 1488 1489 /* tx pause must be same as rx pause */ 1490 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 1491 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 1492 1493 if (pause->rx_pause || pause->autoneg) { 1494 fep->phy_dev->supported |= ADVERTISED_Pause; 1495 fep->phy_dev->advertising |= ADVERTISED_Pause; 1496 } else { 1497 fep->phy_dev->supported &= ~ADVERTISED_Pause; 1498 fep->phy_dev->advertising &= ~ADVERTISED_Pause; 1499 } 1500 1501 if (pause->autoneg) { 1502 if (netif_running(ndev)) 1503 fec_stop(ndev); 1504 phy_start_aneg(fep->phy_dev); 1505 } 1506 if (netif_running(ndev)) 1507 fec_restart(ndev, 0); 1508 1509 return 0; 1510 } 1511 1512 static const struct fec_stat { 1513 char name[ETH_GSTRING_LEN]; 1514 u16 offset; 1515 } fec_stats[] = { 1516 /* RMON TX */ 1517 { "tx_dropped", RMON_T_DROP }, 1518 { "tx_packets", RMON_T_PACKETS }, 1519 { "tx_broadcast", RMON_T_BC_PKT }, 1520 { "tx_multicast", RMON_T_MC_PKT }, 1521 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 1522 { "tx_undersize", RMON_T_UNDERSIZE }, 1523 { "tx_oversize", RMON_T_OVERSIZE }, 1524 { "tx_fragment", RMON_T_FRAG }, 1525 { "tx_jabber", RMON_T_JAB }, 1526 { "tx_collision", RMON_T_COL }, 1527 { "tx_64byte", RMON_T_P64 }, 1528 { "tx_65to127byte", RMON_T_P65TO127 }, 1529 { "tx_128to255byte", RMON_T_P128TO255 }, 1530 { "tx_256to511byte", RMON_T_P256TO511 }, 1531 { "tx_512to1023byte", RMON_T_P512TO1023 }, 1532 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 1533 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 1534 { "tx_octets", RMON_T_OCTETS }, 1535 1536 /* IEEE TX */ 1537 { "IEEE_tx_drop", IEEE_T_DROP }, 1538 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 1539 { "IEEE_tx_1col", IEEE_T_1COL }, 1540 { "IEEE_tx_mcol", IEEE_T_MCOL }, 1541 { "IEEE_tx_def", IEEE_T_DEF }, 1542 { "IEEE_tx_lcol", IEEE_T_LCOL }, 1543 { "IEEE_tx_excol", IEEE_T_EXCOL }, 1544 { "IEEE_tx_macerr", IEEE_T_MACERR }, 1545 { "IEEE_tx_cserr", IEEE_T_CSERR }, 1546 { "IEEE_tx_sqe", IEEE_T_SQE }, 1547 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 1548 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 1549 1550 /* RMON RX */ 1551 { "rx_packets", RMON_R_PACKETS }, 1552 { "rx_broadcast", RMON_R_BC_PKT }, 1553 { "rx_multicast", RMON_R_MC_PKT }, 1554 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 1555 { "rx_undersize", RMON_R_UNDERSIZE }, 1556 { "rx_oversize", RMON_R_OVERSIZE }, 1557 { "rx_fragment", RMON_R_FRAG }, 1558 { "rx_jabber", RMON_R_JAB }, 1559 { "rx_64byte", RMON_R_P64 }, 1560 { "rx_65to127byte", RMON_R_P65TO127 }, 1561 { "rx_128to255byte", RMON_R_P128TO255 }, 1562 { "rx_256to511byte", RMON_R_P256TO511 }, 1563 { "rx_512to1023byte", RMON_R_P512TO1023 }, 1564 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 1565 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 1566 { "rx_octets", RMON_R_OCTETS }, 1567 1568 /* IEEE RX */ 1569 { "IEEE_rx_drop", IEEE_R_DROP }, 1570 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 1571 { "IEEE_rx_crc", IEEE_R_CRC }, 1572 { "IEEE_rx_align", IEEE_R_ALIGN }, 1573 { "IEEE_rx_macerr", IEEE_R_MACERR }, 1574 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 1575 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 1576 }; 1577 1578 static void fec_enet_get_ethtool_stats(struct net_device *dev, 1579 struct ethtool_stats *stats, u64 *data) 1580 { 1581 struct fec_enet_private *fep = netdev_priv(dev); 1582 int i; 1583 1584 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 1585 data[i] = readl(fep->hwp + fec_stats[i].offset); 1586 } 1587 1588 static void fec_enet_get_strings(struct net_device *netdev, 1589 u32 stringset, u8 *data) 1590 { 1591 int i; 1592 switch (stringset) { 1593 case ETH_SS_STATS: 1594 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 1595 memcpy(data + i * ETH_GSTRING_LEN, 1596 fec_stats[i].name, ETH_GSTRING_LEN); 1597 break; 1598 } 1599 } 1600 1601 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 1602 { 1603 switch (sset) { 1604 case ETH_SS_STATS: 1605 return ARRAY_SIZE(fec_stats); 1606 default: 1607 return -EOPNOTSUPP; 1608 } 1609 } 1610 #endif /* !defined(CONFIG_M5272) */ 1611 1612 static int fec_enet_nway_reset(struct net_device *dev) 1613 { 1614 struct fec_enet_private *fep = netdev_priv(dev); 1615 struct phy_device *phydev = fep->phy_dev; 1616 1617 if (!phydev) 1618 return -ENODEV; 1619 1620 return genphy_restart_aneg(phydev); 1621 } 1622 1623 static const struct ethtool_ops fec_enet_ethtool_ops = { 1624 #if !defined(CONFIG_M5272) 1625 .get_pauseparam = fec_enet_get_pauseparam, 1626 .set_pauseparam = fec_enet_set_pauseparam, 1627 #endif 1628 .get_settings = fec_enet_get_settings, 1629 .set_settings = fec_enet_set_settings, 1630 .get_drvinfo = fec_enet_get_drvinfo, 1631 .get_link = ethtool_op_get_link, 1632 .get_ts_info = fec_enet_get_ts_info, 1633 .nway_reset = fec_enet_nway_reset, 1634 #ifndef CONFIG_M5272 1635 .get_ethtool_stats = fec_enet_get_ethtool_stats, 1636 .get_strings = fec_enet_get_strings, 1637 .get_sset_count = fec_enet_get_sset_count, 1638 #endif 1639 }; 1640 1641 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 1642 { 1643 struct fec_enet_private *fep = netdev_priv(ndev); 1644 struct phy_device *phydev = fep->phy_dev; 1645 1646 if (!netif_running(ndev)) 1647 return -EINVAL; 1648 1649 if (!phydev) 1650 return -ENODEV; 1651 1652 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex) 1653 return fec_ptp_ioctl(ndev, rq, cmd); 1654 1655 return phy_mii_ioctl(phydev, rq, cmd); 1656 } 1657 1658 static void fec_enet_free_buffers(struct net_device *ndev) 1659 { 1660 struct fec_enet_private *fep = netdev_priv(ndev); 1661 unsigned int i; 1662 struct sk_buff *skb; 1663 struct bufdesc *bdp; 1664 1665 bdp = fep->rx_bd_base; 1666 for (i = 0; i < RX_RING_SIZE; i++) { 1667 skb = fep->rx_skbuff[i]; 1668 1669 if (bdp->cbd_bufaddr) 1670 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 1671 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1672 if (skb) 1673 dev_kfree_skb(skb); 1674 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 1675 } 1676 1677 bdp = fep->tx_bd_base; 1678 for (i = 0; i < TX_RING_SIZE; i++) 1679 kfree(fep->tx_bounce[i]); 1680 } 1681 1682 static int fec_enet_alloc_buffers(struct net_device *ndev) 1683 { 1684 struct fec_enet_private *fep = netdev_priv(ndev); 1685 unsigned int i; 1686 struct sk_buff *skb; 1687 struct bufdesc *bdp; 1688 1689 bdp = fep->rx_bd_base; 1690 for (i = 0; i < RX_RING_SIZE; i++) { 1691 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1692 if (!skb) { 1693 fec_enet_free_buffers(ndev); 1694 return -ENOMEM; 1695 } 1696 fep->rx_skbuff[i] = skb; 1697 1698 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, 1699 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1700 bdp->cbd_sc = BD_ENET_RX_EMPTY; 1701 1702 if (fep->bufdesc_ex) { 1703 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1704 ebdp->cbd_esc = BD_ENET_RX_INT; 1705 } 1706 1707 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 1708 } 1709 1710 /* Set the last buffer to wrap. */ 1711 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); 1712 bdp->cbd_sc |= BD_SC_WRAP; 1713 1714 bdp = fep->tx_bd_base; 1715 for (i = 0; i < TX_RING_SIZE; i++) { 1716 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 1717 1718 bdp->cbd_sc = 0; 1719 bdp->cbd_bufaddr = 0; 1720 1721 if (fep->bufdesc_ex) { 1722 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1723 ebdp->cbd_esc = BD_ENET_TX_INT; 1724 } 1725 1726 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 1727 } 1728 1729 /* Set the last buffer to wrap. */ 1730 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); 1731 bdp->cbd_sc |= BD_SC_WRAP; 1732 1733 return 0; 1734 } 1735 1736 static int 1737 fec_enet_open(struct net_device *ndev) 1738 { 1739 struct fec_enet_private *fep = netdev_priv(ndev); 1740 int ret; 1741 1742 napi_enable(&fep->napi); 1743 1744 /* I should reset the ring buffers here, but I don't yet know 1745 * a simple way to do that. 1746 */ 1747 1748 ret = fec_enet_alloc_buffers(ndev); 1749 if (ret) 1750 return ret; 1751 1752 /* Probe and connect to PHY when open the interface */ 1753 ret = fec_enet_mii_probe(ndev); 1754 if (ret) { 1755 fec_enet_free_buffers(ndev); 1756 return ret; 1757 } 1758 phy_start(fep->phy_dev); 1759 netif_start_queue(ndev); 1760 fep->opened = 1; 1761 return 0; 1762 } 1763 1764 static int 1765 fec_enet_close(struct net_device *ndev) 1766 { 1767 struct fec_enet_private *fep = netdev_priv(ndev); 1768 1769 /* Don't know what to do yet. */ 1770 napi_disable(&fep->napi); 1771 fep->opened = 0; 1772 netif_stop_queue(ndev); 1773 fec_stop(ndev); 1774 1775 if (fep->phy_dev) { 1776 phy_stop(fep->phy_dev); 1777 phy_disconnect(fep->phy_dev); 1778 } 1779 1780 fec_enet_free_buffers(ndev); 1781 1782 return 0; 1783 } 1784 1785 /* Set or clear the multicast filter for this adaptor. 1786 * Skeleton taken from sunlance driver. 1787 * The CPM Ethernet implementation allows Multicast as well as individual 1788 * MAC address filtering. Some of the drivers check to make sure it is 1789 * a group multicast address, and discard those that are not. I guess I 1790 * will do the same for now, but just remove the test if you want 1791 * individual filtering as well (do the upper net layers want or support 1792 * this kind of feature?). 1793 */ 1794 1795 #define HASH_BITS 6 /* #bits in hash */ 1796 #define CRC32_POLY 0xEDB88320 1797 1798 static void set_multicast_list(struct net_device *ndev) 1799 { 1800 struct fec_enet_private *fep = netdev_priv(ndev); 1801 struct netdev_hw_addr *ha; 1802 unsigned int i, bit, data, crc, tmp; 1803 unsigned char hash; 1804 1805 if (ndev->flags & IFF_PROMISC) { 1806 tmp = readl(fep->hwp + FEC_R_CNTRL); 1807 tmp |= 0x8; 1808 writel(tmp, fep->hwp + FEC_R_CNTRL); 1809 return; 1810 } 1811 1812 tmp = readl(fep->hwp + FEC_R_CNTRL); 1813 tmp &= ~0x8; 1814 writel(tmp, fep->hwp + FEC_R_CNTRL); 1815 1816 if (ndev->flags & IFF_ALLMULTI) { 1817 /* Catch all multicast addresses, so set the 1818 * filter to all 1's 1819 */ 1820 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1821 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1822 1823 return; 1824 } 1825 1826 /* Clear filter and add the addresses in hash register 1827 */ 1828 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1829 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1830 1831 netdev_for_each_mc_addr(ha, ndev) { 1832 /* calculate crc32 value of mac address */ 1833 crc = 0xffffffff; 1834 1835 for (i = 0; i < ndev->addr_len; i++) { 1836 data = ha->addr[i]; 1837 for (bit = 0; bit < 8; bit++, data >>= 1) { 1838 crc = (crc >> 1) ^ 1839 (((crc ^ data) & 1) ? CRC32_POLY : 0); 1840 } 1841 } 1842 1843 /* only upper 6 bits (HASH_BITS) are used 1844 * which point to specific bit in he hash registers 1845 */ 1846 hash = (crc >> (32 - HASH_BITS)) & 0x3f; 1847 1848 if (hash > 31) { 1849 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1850 tmp |= 1 << (hash - 32); 1851 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1852 } else { 1853 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1854 tmp |= 1 << hash; 1855 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1856 } 1857 } 1858 } 1859 1860 /* Set a MAC change in hardware. */ 1861 static int 1862 fec_set_mac_address(struct net_device *ndev, void *p) 1863 { 1864 struct fec_enet_private *fep = netdev_priv(ndev); 1865 struct sockaddr *addr = p; 1866 1867 if (!is_valid_ether_addr(addr->sa_data)) 1868 return -EADDRNOTAVAIL; 1869 1870 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 1871 1872 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 1873 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 1874 fep->hwp + FEC_ADDR_LOW); 1875 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 1876 fep->hwp + FEC_ADDR_HIGH); 1877 return 0; 1878 } 1879 1880 #ifdef CONFIG_NET_POLL_CONTROLLER 1881 /** 1882 * fec_poll_controller - FEC Poll controller function 1883 * @dev: The FEC network adapter 1884 * 1885 * Polled functionality used by netconsole and others in non interrupt mode 1886 * 1887 */ 1888 static void fec_poll_controller(struct net_device *dev) 1889 { 1890 int i; 1891 struct fec_enet_private *fep = netdev_priv(dev); 1892 1893 for (i = 0; i < FEC_IRQ_NUM; i++) { 1894 if (fep->irq[i] > 0) { 1895 disable_irq(fep->irq[i]); 1896 fec_enet_interrupt(fep->irq[i], dev); 1897 enable_irq(fep->irq[i]); 1898 } 1899 } 1900 } 1901 #endif 1902 1903 static int fec_set_features(struct net_device *netdev, 1904 netdev_features_t features) 1905 { 1906 struct fec_enet_private *fep = netdev_priv(netdev); 1907 netdev_features_t changed = features ^ netdev->features; 1908 1909 netdev->features = features; 1910 1911 /* Receive checksum has been changed */ 1912 if (changed & NETIF_F_RXCSUM) { 1913 if (features & NETIF_F_RXCSUM) 1914 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 1915 else 1916 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 1917 1918 if (netif_running(netdev)) { 1919 fec_stop(netdev); 1920 fec_restart(netdev, fep->phy_dev->duplex); 1921 netif_wake_queue(netdev); 1922 } else { 1923 fec_restart(netdev, fep->phy_dev->duplex); 1924 } 1925 } 1926 1927 return 0; 1928 } 1929 1930 static const struct net_device_ops fec_netdev_ops = { 1931 .ndo_open = fec_enet_open, 1932 .ndo_stop = fec_enet_close, 1933 .ndo_start_xmit = fec_enet_start_xmit, 1934 .ndo_set_rx_mode = set_multicast_list, 1935 .ndo_change_mtu = eth_change_mtu, 1936 .ndo_validate_addr = eth_validate_addr, 1937 .ndo_tx_timeout = fec_timeout, 1938 .ndo_set_mac_address = fec_set_mac_address, 1939 .ndo_do_ioctl = fec_enet_ioctl, 1940 #ifdef CONFIG_NET_POLL_CONTROLLER 1941 .ndo_poll_controller = fec_poll_controller, 1942 #endif 1943 .ndo_set_features = fec_set_features, 1944 }; 1945 1946 /* 1947 * XXX: We need to clean up on failure exits here. 1948 * 1949 */ 1950 static int fec_enet_init(struct net_device *ndev) 1951 { 1952 struct fec_enet_private *fep = netdev_priv(ndev); 1953 const struct platform_device_id *id_entry = 1954 platform_get_device_id(fep->pdev); 1955 struct bufdesc *cbd_base; 1956 1957 /* Allocate memory for buffer descriptors. */ 1958 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, 1959 GFP_KERNEL); 1960 if (!cbd_base) 1961 return -ENOMEM; 1962 1963 memset(cbd_base, 0, PAGE_SIZE); 1964 1965 fep->netdev = ndev; 1966 1967 /* Get the Ethernet address */ 1968 fec_get_mac(ndev); 1969 1970 /* Set receive and transmit descriptor base. */ 1971 fep->rx_bd_base = cbd_base; 1972 if (fep->bufdesc_ex) 1973 fep->tx_bd_base = (struct bufdesc *) 1974 (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE); 1975 else 1976 fep->tx_bd_base = cbd_base + RX_RING_SIZE; 1977 1978 /* The FEC Ethernet specific entries in the device structure */ 1979 ndev->watchdog_timeo = TX_TIMEOUT; 1980 ndev->netdev_ops = &fec_netdev_ops; 1981 ndev->ethtool_ops = &fec_enet_ethtool_ops; 1982 1983 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 1984 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT); 1985 1986 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) { 1987 /* enable hw VLAN support */ 1988 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 1989 ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 1990 } 1991 1992 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) { 1993 /* enable hw accelerator */ 1994 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 1995 | NETIF_F_RXCSUM); 1996 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 1997 | NETIF_F_RXCSUM); 1998 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 1999 } 2000 2001 fec_restart(ndev, 0); 2002 2003 return 0; 2004 } 2005 2006 #ifdef CONFIG_OF 2007 static void fec_reset_phy(struct platform_device *pdev) 2008 { 2009 int err, phy_reset; 2010 int msec = 1; 2011 struct device_node *np = pdev->dev.of_node; 2012 2013 if (!np) 2014 return; 2015 2016 of_property_read_u32(np, "phy-reset-duration", &msec); 2017 /* A sane reset duration should not be longer than 1s */ 2018 if (msec > 1000) 2019 msec = 1; 2020 2021 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 2022 if (!gpio_is_valid(phy_reset)) 2023 return; 2024 2025 err = devm_gpio_request_one(&pdev->dev, phy_reset, 2026 GPIOF_OUT_INIT_LOW, "phy-reset"); 2027 if (err) { 2028 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 2029 return; 2030 } 2031 msleep(msec); 2032 gpio_set_value(phy_reset, 1); 2033 } 2034 #else /* CONFIG_OF */ 2035 static void fec_reset_phy(struct platform_device *pdev) 2036 { 2037 /* 2038 * In case of platform probe, the reset has been done 2039 * by machine code. 2040 */ 2041 } 2042 #endif /* CONFIG_OF */ 2043 2044 static int 2045 fec_probe(struct platform_device *pdev) 2046 { 2047 struct fec_enet_private *fep; 2048 struct fec_platform_data *pdata; 2049 struct net_device *ndev; 2050 int i, irq, ret = 0; 2051 struct resource *r; 2052 const struct of_device_id *of_id; 2053 static int dev_id; 2054 2055 of_id = of_match_device(fec_dt_ids, &pdev->dev); 2056 if (of_id) 2057 pdev->id_entry = of_id->data; 2058 2059 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2060 if (!r) 2061 return -ENXIO; 2062 2063 /* Init network device */ 2064 ndev = alloc_etherdev(sizeof(struct fec_enet_private)); 2065 if (!ndev) 2066 return -ENOMEM; 2067 2068 SET_NETDEV_DEV(ndev, &pdev->dev); 2069 2070 /* setup board info structure */ 2071 fep = netdev_priv(ndev); 2072 2073 #if !defined(CONFIG_M5272) 2074 /* default enable pause frame auto negotiation */ 2075 if (pdev->id_entry && 2076 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT)) 2077 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 2078 #endif 2079 2080 fep->hwp = devm_ioremap_resource(&pdev->dev, r); 2081 if (IS_ERR(fep->hwp)) { 2082 ret = PTR_ERR(fep->hwp); 2083 goto failed_ioremap; 2084 } 2085 2086 fep->pdev = pdev; 2087 fep->dev_id = dev_id++; 2088 2089 fep->bufdesc_ex = 0; 2090 2091 platform_set_drvdata(pdev, ndev); 2092 2093 ret = of_get_phy_mode(pdev->dev.of_node); 2094 if (ret < 0) { 2095 pdata = pdev->dev.platform_data; 2096 if (pdata) 2097 fep->phy_interface = pdata->phy; 2098 else 2099 fep->phy_interface = PHY_INTERFACE_MODE_MII; 2100 } else { 2101 fep->phy_interface = ret; 2102 } 2103 2104 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2105 if (IS_ERR(fep->clk_ipg)) { 2106 ret = PTR_ERR(fep->clk_ipg); 2107 goto failed_clk; 2108 } 2109 2110 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 2111 if (IS_ERR(fep->clk_ahb)) { 2112 ret = PTR_ERR(fep->clk_ahb); 2113 goto failed_clk; 2114 } 2115 2116 /* enet_out is optional, depends on board */ 2117 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 2118 if (IS_ERR(fep->clk_enet_out)) 2119 fep->clk_enet_out = NULL; 2120 2121 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 2122 fep->bufdesc_ex = 2123 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX; 2124 if (IS_ERR(fep->clk_ptp)) { 2125 fep->clk_ptp = NULL; 2126 fep->bufdesc_ex = 0; 2127 } 2128 2129 clk_prepare_enable(fep->clk_ahb); 2130 clk_prepare_enable(fep->clk_ipg); 2131 clk_prepare_enable(fep->clk_enet_out); 2132 clk_prepare_enable(fep->clk_ptp); 2133 2134 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); 2135 if (!IS_ERR(fep->reg_phy)) { 2136 ret = regulator_enable(fep->reg_phy); 2137 if (ret) { 2138 dev_err(&pdev->dev, 2139 "Failed to enable phy regulator: %d\n", ret); 2140 goto failed_regulator; 2141 } 2142 } else { 2143 fep->reg_phy = NULL; 2144 } 2145 2146 fec_reset_phy(pdev); 2147 2148 if (fep->bufdesc_ex) 2149 fec_ptp_init(pdev); 2150 2151 ret = fec_enet_init(ndev); 2152 if (ret) 2153 goto failed_init; 2154 2155 for (i = 0; i < FEC_IRQ_NUM; i++) { 2156 irq = platform_get_irq(pdev, i); 2157 if (irq < 0) { 2158 if (i) 2159 break; 2160 ret = irq; 2161 goto failed_irq; 2162 } 2163 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); 2164 if (ret) { 2165 while (--i >= 0) { 2166 irq = platform_get_irq(pdev, i); 2167 free_irq(irq, ndev); 2168 } 2169 goto failed_irq; 2170 } 2171 } 2172 2173 ret = fec_enet_mii_init(pdev); 2174 if (ret) 2175 goto failed_mii_init; 2176 2177 /* Carrier starts down, phylib will bring it up */ 2178 netif_carrier_off(ndev); 2179 2180 ret = register_netdev(ndev); 2181 if (ret) 2182 goto failed_register; 2183 2184 if (fep->bufdesc_ex && fep->ptp_clock) 2185 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 2186 2187 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work); 2188 return 0; 2189 2190 failed_register: 2191 fec_enet_mii_remove(fep); 2192 failed_mii_init: 2193 failed_irq: 2194 for (i = 0; i < FEC_IRQ_NUM; i++) { 2195 irq = platform_get_irq(pdev, i); 2196 if (irq > 0) 2197 free_irq(irq, ndev); 2198 } 2199 failed_init: 2200 if (fep->reg_phy) 2201 regulator_disable(fep->reg_phy); 2202 failed_regulator: 2203 clk_disable_unprepare(fep->clk_ahb); 2204 clk_disable_unprepare(fep->clk_ipg); 2205 clk_disable_unprepare(fep->clk_enet_out); 2206 clk_disable_unprepare(fep->clk_ptp); 2207 failed_clk: 2208 failed_ioremap: 2209 free_netdev(ndev); 2210 2211 return ret; 2212 } 2213 2214 static int 2215 fec_drv_remove(struct platform_device *pdev) 2216 { 2217 struct net_device *ndev = platform_get_drvdata(pdev); 2218 struct fec_enet_private *fep = netdev_priv(ndev); 2219 int i; 2220 2221 cancel_delayed_work_sync(&(fep->delay_work.delay_work)); 2222 unregister_netdev(ndev); 2223 fec_enet_mii_remove(fep); 2224 del_timer_sync(&fep->time_keep); 2225 for (i = 0; i < FEC_IRQ_NUM; i++) { 2226 int irq = platform_get_irq(pdev, i); 2227 if (irq > 0) 2228 free_irq(irq, ndev); 2229 } 2230 if (fep->reg_phy) 2231 regulator_disable(fep->reg_phy); 2232 clk_disable_unprepare(fep->clk_ptp); 2233 if (fep->ptp_clock) 2234 ptp_clock_unregister(fep->ptp_clock); 2235 clk_disable_unprepare(fep->clk_enet_out); 2236 clk_disable_unprepare(fep->clk_ahb); 2237 clk_disable_unprepare(fep->clk_ipg); 2238 free_netdev(ndev); 2239 2240 return 0; 2241 } 2242 2243 #ifdef CONFIG_PM_SLEEP 2244 static int 2245 fec_suspend(struct device *dev) 2246 { 2247 struct net_device *ndev = dev_get_drvdata(dev); 2248 struct fec_enet_private *fep = netdev_priv(ndev); 2249 2250 if (netif_running(ndev)) { 2251 fec_stop(ndev); 2252 netif_device_detach(ndev); 2253 } 2254 clk_disable_unprepare(fep->clk_enet_out); 2255 clk_disable_unprepare(fep->clk_ahb); 2256 clk_disable_unprepare(fep->clk_ipg); 2257 2258 if (fep->reg_phy) 2259 regulator_disable(fep->reg_phy); 2260 2261 return 0; 2262 } 2263 2264 static int 2265 fec_resume(struct device *dev) 2266 { 2267 struct net_device *ndev = dev_get_drvdata(dev); 2268 struct fec_enet_private *fep = netdev_priv(ndev); 2269 int ret; 2270 2271 if (fep->reg_phy) { 2272 ret = regulator_enable(fep->reg_phy); 2273 if (ret) 2274 return ret; 2275 } 2276 2277 clk_prepare_enable(fep->clk_enet_out); 2278 clk_prepare_enable(fep->clk_ahb); 2279 clk_prepare_enable(fep->clk_ipg); 2280 if (netif_running(ndev)) { 2281 fec_restart(ndev, fep->full_duplex); 2282 netif_device_attach(ndev); 2283 } 2284 2285 return 0; 2286 } 2287 #endif /* CONFIG_PM_SLEEP */ 2288 2289 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume); 2290 2291 static struct platform_driver fec_driver = { 2292 .driver = { 2293 .name = DRIVER_NAME, 2294 .owner = THIS_MODULE, 2295 .pm = &fec_pm_ops, 2296 .of_match_table = fec_dt_ids, 2297 }, 2298 .id_table = fec_devtype, 2299 .probe = fec_probe, 2300 .remove = fec_drv_remove, 2301 }; 2302 2303 module_platform_driver(fec_driver); 2304 2305 MODULE_ALIAS("platform:"DRIVER_NAME); 2306 MODULE_LICENSE("GPL"); 2307