1 /* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 * 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/string.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/ptrace.h> 29 #include <linux/errno.h> 30 #include <linux/ioport.h> 31 #include <linux/slab.h> 32 #include <linux/interrupt.h> 33 #include <linux/delay.h> 34 #include <linux/netdevice.h> 35 #include <linux/etherdevice.h> 36 #include <linux/skbuff.h> 37 #include <linux/in.h> 38 #include <linux/ip.h> 39 #include <net/ip.h> 40 #include <net/tso.h> 41 #include <linux/tcp.h> 42 #include <linux/udp.h> 43 #include <linux/icmp.h> 44 #include <linux/spinlock.h> 45 #include <linux/workqueue.h> 46 #include <linux/bitops.h> 47 #include <linux/io.h> 48 #include <linux/irq.h> 49 #include <linux/clk.h> 50 #include <linux/platform_device.h> 51 #include <linux/mdio.h> 52 #include <linux/phy.h> 53 #include <linux/fec.h> 54 #include <linux/of.h> 55 #include <linux/of_device.h> 56 #include <linux/of_gpio.h> 57 #include <linux/of_mdio.h> 58 #include <linux/of_net.h> 59 #include <linux/regulator/consumer.h> 60 #include <linux/if_vlan.h> 61 #include <linux/pinctrl/consumer.h> 62 #include <linux/prefetch.h> 63 #include <soc/imx/cpuidle.h> 64 65 #include <asm/cacheflush.h> 66 67 #include "fec.h" 68 69 static void set_multicast_list(struct net_device *ndev); 70 static void fec_enet_itr_coal_init(struct net_device *ndev); 71 72 #define DRIVER_NAME "fec" 73 74 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0)) 75 76 /* Pause frame feild and FIFO threshold */ 77 #define FEC_ENET_FCE (1 << 5) 78 #define FEC_ENET_RSEM_V 0x84 79 #define FEC_ENET_RSFL_V 16 80 #define FEC_ENET_RAEM_V 0x8 81 #define FEC_ENET_RAFL_V 0x8 82 #define FEC_ENET_OPD_V 0xFFF0 83 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 84 85 static struct platform_device_id fec_devtype[] = { 86 { 87 /* keep it for coldfire */ 88 .name = DRIVER_NAME, 89 .driver_data = 0, 90 }, { 91 .name = "imx25-fec", 92 .driver_data = FEC_QUIRK_USE_GASKET, 93 }, { 94 .name = "imx27-fec", 95 .driver_data = 0, 96 }, { 97 .name = "imx28-fec", 98 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 99 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC, 100 }, { 101 .name = "imx6q-fec", 102 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 103 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 104 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 105 FEC_QUIRK_HAS_RACC, 106 }, { 107 .name = "mvf600-fec", 108 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 109 }, { 110 .name = "imx6sx-fec", 111 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 112 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 113 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 114 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 115 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE, 116 }, { 117 .name = "imx6ul-fec", 118 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 119 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 120 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_BUG_CAPTURE | 121 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE, 122 }, { 123 /* sentinel */ 124 } 125 }; 126 MODULE_DEVICE_TABLE(platform, fec_devtype); 127 128 enum imx_fec_type { 129 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 130 IMX27_FEC, /* runs on i.mx27/35/51 */ 131 IMX28_FEC, 132 IMX6Q_FEC, 133 MVF600_FEC, 134 IMX6SX_FEC, 135 IMX6UL_FEC, 136 }; 137 138 static const struct of_device_id fec_dt_ids[] = { 139 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 140 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 141 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 142 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 143 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 144 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 145 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 146 { /* sentinel */ } 147 }; 148 MODULE_DEVICE_TABLE(of, fec_dt_ids); 149 150 static unsigned char macaddr[ETH_ALEN]; 151 module_param_array(macaddr, byte, NULL, 0); 152 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 153 154 #if defined(CONFIG_M5272) 155 /* 156 * Some hardware gets it MAC address out of local flash memory. 157 * if this is non-zero then assume it is the address to get MAC from. 158 */ 159 #if defined(CONFIG_NETtel) 160 #define FEC_FLASHMAC 0xf0006006 161 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 162 #define FEC_FLASHMAC 0xf0006000 163 #elif defined(CONFIG_CANCam) 164 #define FEC_FLASHMAC 0xf0020000 165 #elif defined (CONFIG_M5272C3) 166 #define FEC_FLASHMAC (0xffe04000 + 4) 167 #elif defined(CONFIG_MOD5272) 168 #define FEC_FLASHMAC 0xffc0406b 169 #else 170 #define FEC_FLASHMAC 0 171 #endif 172 #endif /* CONFIG_M5272 */ 173 174 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 175 */ 176 #define PKT_MAXBUF_SIZE 1522 177 #define PKT_MINBUF_SIZE 64 178 #define PKT_MAXBLR_SIZE 1536 179 180 /* FEC receive acceleration */ 181 #define FEC_RACC_IPDIS (1 << 1) 182 #define FEC_RACC_PRODIS (1 << 2) 183 #define FEC_RACC_SHIFT16 BIT(7) 184 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 185 186 /* 187 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 188 * size bits. Other FEC hardware does not, so we need to take that into 189 * account when setting it. 190 */ 191 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 192 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 193 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 194 #else 195 #define OPT_FRAME_SIZE 0 196 #endif 197 198 /* FEC MII MMFR bits definition */ 199 #define FEC_MMFR_ST (1 << 30) 200 #define FEC_MMFR_OP_READ (2 << 28) 201 #define FEC_MMFR_OP_WRITE (1 << 28) 202 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 203 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 204 #define FEC_MMFR_TA (2 << 16) 205 #define FEC_MMFR_DATA(v) (v & 0xffff) 206 /* FEC ECR bits definition */ 207 #define FEC_ECR_MAGICEN (1 << 2) 208 #define FEC_ECR_SLEEP (1 << 3) 209 210 #define FEC_MII_TIMEOUT 30000 /* us */ 211 212 /* Transmitter timeout */ 213 #define TX_TIMEOUT (2 * HZ) 214 215 #define FEC_PAUSE_FLAG_AUTONEG 0x1 216 #define FEC_PAUSE_FLAG_ENABLE 0x2 217 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 218 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 219 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 220 221 #define COPYBREAK_DEFAULT 256 222 223 #define TSO_HEADER_SIZE 128 224 /* Max number of allowed TCP segments for software TSO */ 225 #define FEC_MAX_TSO_SEGS 100 226 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 227 228 #define IS_TSO_HEADER(txq, addr) \ 229 ((addr >= txq->tso_hdrs_dma) && \ 230 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 231 232 static int mii_cnt; 233 234 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 235 struct bufdesc_prop *bd) 236 { 237 return (bdp >= bd->last) ? bd->base 238 : (struct bufdesc *)(((unsigned)bdp) + bd->dsize); 239 } 240 241 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 242 struct bufdesc_prop *bd) 243 { 244 return (bdp <= bd->base) ? bd->last 245 : (struct bufdesc *)(((unsigned)bdp) - bd->dsize); 246 } 247 248 static int fec_enet_get_bd_index(struct bufdesc *bdp, 249 struct bufdesc_prop *bd) 250 { 251 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 252 } 253 254 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 255 { 256 int entries; 257 258 entries = (((const char *)txq->dirty_tx - 259 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 260 261 return entries >= 0 ? entries : entries + txq->bd.ring_size; 262 } 263 264 static void swap_buffer(void *bufaddr, int len) 265 { 266 int i; 267 unsigned int *buf = bufaddr; 268 269 for (i = 0; i < len; i += 4, buf++) 270 swab32s(buf); 271 } 272 273 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 274 { 275 int i; 276 unsigned int *src = src_buf; 277 unsigned int *dst = dst_buf; 278 279 for (i = 0; i < len; i += 4, src++, dst++) 280 *dst = swab32p(src); 281 } 282 283 static void fec_dump(struct net_device *ndev) 284 { 285 struct fec_enet_private *fep = netdev_priv(ndev); 286 struct bufdesc *bdp; 287 struct fec_enet_priv_tx_q *txq; 288 int index = 0; 289 290 netdev_info(ndev, "TX ring dump\n"); 291 pr_info("Nr SC addr len SKB\n"); 292 293 txq = fep->tx_queue[0]; 294 bdp = txq->bd.base; 295 296 do { 297 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 298 index, 299 bdp == txq->bd.cur ? 'S' : ' ', 300 bdp == txq->dirty_tx ? 'H' : ' ', 301 fec16_to_cpu(bdp->cbd_sc), 302 fec32_to_cpu(bdp->cbd_bufaddr), 303 fec16_to_cpu(bdp->cbd_datlen), 304 txq->tx_skbuff[index]); 305 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 306 index++; 307 } while (bdp != txq->bd.base); 308 } 309 310 static inline bool is_ipv4_pkt(struct sk_buff *skb) 311 { 312 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 313 } 314 315 static int 316 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 317 { 318 /* Only run for packets requiring a checksum. */ 319 if (skb->ip_summed != CHECKSUM_PARTIAL) 320 return 0; 321 322 if (unlikely(skb_cow_head(skb, 0))) 323 return -1; 324 325 if (is_ipv4_pkt(skb)) 326 ip_hdr(skb)->check = 0; 327 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 328 329 return 0; 330 } 331 332 static struct bufdesc * 333 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 334 struct sk_buff *skb, 335 struct net_device *ndev) 336 { 337 struct fec_enet_private *fep = netdev_priv(ndev); 338 struct bufdesc *bdp = txq->bd.cur; 339 struct bufdesc_ex *ebdp; 340 int nr_frags = skb_shinfo(skb)->nr_frags; 341 int frag, frag_len; 342 unsigned short status; 343 unsigned int estatus = 0; 344 skb_frag_t *this_frag; 345 unsigned int index; 346 void *bufaddr; 347 dma_addr_t addr; 348 int i; 349 350 for (frag = 0; frag < nr_frags; frag++) { 351 this_frag = &skb_shinfo(skb)->frags[frag]; 352 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 353 ebdp = (struct bufdesc_ex *)bdp; 354 355 status = fec16_to_cpu(bdp->cbd_sc); 356 status &= ~BD_ENET_TX_STATS; 357 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 358 frag_len = skb_shinfo(skb)->frags[frag].size; 359 360 /* Handle the last BD specially */ 361 if (frag == nr_frags - 1) { 362 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 363 if (fep->bufdesc_ex) { 364 estatus |= BD_ENET_TX_INT; 365 if (unlikely(skb_shinfo(skb)->tx_flags & 366 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 367 estatus |= BD_ENET_TX_TS; 368 } 369 } 370 371 if (fep->bufdesc_ex) { 372 if (fep->quirks & FEC_QUIRK_HAS_AVB) 373 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 374 if (skb->ip_summed == CHECKSUM_PARTIAL) 375 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 376 ebdp->cbd_bdu = 0; 377 ebdp->cbd_esc = cpu_to_fec32(estatus); 378 } 379 380 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset; 381 382 index = fec_enet_get_bd_index(bdp, &txq->bd); 383 if (((unsigned long) bufaddr) & fep->tx_align || 384 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 385 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 386 bufaddr = txq->tx_bounce[index]; 387 388 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 389 swap_buffer(bufaddr, frag_len); 390 } 391 392 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 393 DMA_TO_DEVICE); 394 if (dma_mapping_error(&fep->pdev->dev, addr)) { 395 if (net_ratelimit()) 396 netdev_err(ndev, "Tx DMA memory map failed\n"); 397 goto dma_mapping_error; 398 } 399 400 bdp->cbd_bufaddr = cpu_to_fec32(addr); 401 bdp->cbd_datlen = cpu_to_fec16(frag_len); 402 /* Make sure the updates to rest of the descriptor are 403 * performed before transferring ownership. 404 */ 405 wmb(); 406 bdp->cbd_sc = cpu_to_fec16(status); 407 } 408 409 return bdp; 410 dma_mapping_error: 411 bdp = txq->bd.cur; 412 for (i = 0; i < frag; i++) { 413 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 414 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 415 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 416 } 417 return ERR_PTR(-ENOMEM); 418 } 419 420 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 421 struct sk_buff *skb, struct net_device *ndev) 422 { 423 struct fec_enet_private *fep = netdev_priv(ndev); 424 int nr_frags = skb_shinfo(skb)->nr_frags; 425 struct bufdesc *bdp, *last_bdp; 426 void *bufaddr; 427 dma_addr_t addr; 428 unsigned short status; 429 unsigned short buflen; 430 unsigned int estatus = 0; 431 unsigned int index; 432 int entries_free; 433 434 entries_free = fec_enet_get_free_txdesc_num(txq); 435 if (entries_free < MAX_SKB_FRAGS + 1) { 436 dev_kfree_skb_any(skb); 437 if (net_ratelimit()) 438 netdev_err(ndev, "NOT enough BD for SG!\n"); 439 return NETDEV_TX_OK; 440 } 441 442 /* Protocol checksum off-load for TCP and UDP. */ 443 if (fec_enet_clear_csum(skb, ndev)) { 444 dev_kfree_skb_any(skb); 445 return NETDEV_TX_OK; 446 } 447 448 /* Fill in a Tx ring entry */ 449 bdp = txq->bd.cur; 450 last_bdp = bdp; 451 status = fec16_to_cpu(bdp->cbd_sc); 452 status &= ~BD_ENET_TX_STATS; 453 454 /* Set buffer length and buffer pointer */ 455 bufaddr = skb->data; 456 buflen = skb_headlen(skb); 457 458 index = fec_enet_get_bd_index(bdp, &txq->bd); 459 if (((unsigned long) bufaddr) & fep->tx_align || 460 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 461 memcpy(txq->tx_bounce[index], skb->data, buflen); 462 bufaddr = txq->tx_bounce[index]; 463 464 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 465 swap_buffer(bufaddr, buflen); 466 } 467 468 /* Push the data cache so the CPM does not get stale memory data. */ 469 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 470 if (dma_mapping_error(&fep->pdev->dev, addr)) { 471 dev_kfree_skb_any(skb); 472 if (net_ratelimit()) 473 netdev_err(ndev, "Tx DMA memory map failed\n"); 474 return NETDEV_TX_OK; 475 } 476 477 if (nr_frags) { 478 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 479 if (IS_ERR(last_bdp)) { 480 dma_unmap_single(&fep->pdev->dev, addr, 481 buflen, DMA_TO_DEVICE); 482 dev_kfree_skb_any(skb); 483 return NETDEV_TX_OK; 484 } 485 } else { 486 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 487 if (fep->bufdesc_ex) { 488 estatus = BD_ENET_TX_INT; 489 if (unlikely(skb_shinfo(skb)->tx_flags & 490 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 491 estatus |= BD_ENET_TX_TS; 492 } 493 } 494 bdp->cbd_bufaddr = cpu_to_fec32(addr); 495 bdp->cbd_datlen = cpu_to_fec16(buflen); 496 497 if (fep->bufdesc_ex) { 498 499 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 500 501 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 502 fep->hwts_tx_en)) 503 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 504 505 if (fep->quirks & FEC_QUIRK_HAS_AVB) 506 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 507 508 if (skb->ip_summed == CHECKSUM_PARTIAL) 509 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 510 511 ebdp->cbd_bdu = 0; 512 ebdp->cbd_esc = cpu_to_fec32(estatus); 513 } 514 515 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 516 /* Save skb pointer */ 517 txq->tx_skbuff[index] = skb; 518 519 /* Make sure the updates to rest of the descriptor are performed before 520 * transferring ownership. 521 */ 522 wmb(); 523 524 /* Send it on its way. Tell FEC it's ready, interrupt when done, 525 * it's the last BD of the frame, and to put the CRC on the end. 526 */ 527 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 528 bdp->cbd_sc = cpu_to_fec16(status); 529 530 /* If this was the last BD in the ring, start at the beginning again. */ 531 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 532 533 skb_tx_timestamp(skb); 534 535 /* Make sure the update to bdp and tx_skbuff are performed before 536 * txq->bd.cur. 537 */ 538 wmb(); 539 txq->bd.cur = bdp; 540 541 /* Trigger transmission start */ 542 writel(0, txq->bd.reg_desc_active); 543 544 return 0; 545 } 546 547 static int 548 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 549 struct net_device *ndev, 550 struct bufdesc *bdp, int index, char *data, 551 int size, bool last_tcp, bool is_last) 552 { 553 struct fec_enet_private *fep = netdev_priv(ndev); 554 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 555 unsigned short status; 556 unsigned int estatus = 0; 557 dma_addr_t addr; 558 559 status = fec16_to_cpu(bdp->cbd_sc); 560 status &= ~BD_ENET_TX_STATS; 561 562 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 563 564 if (((unsigned long) data) & fep->tx_align || 565 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 566 memcpy(txq->tx_bounce[index], data, size); 567 data = txq->tx_bounce[index]; 568 569 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 570 swap_buffer(data, size); 571 } 572 573 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 574 if (dma_mapping_error(&fep->pdev->dev, addr)) { 575 dev_kfree_skb_any(skb); 576 if (net_ratelimit()) 577 netdev_err(ndev, "Tx DMA memory map failed\n"); 578 return NETDEV_TX_BUSY; 579 } 580 581 bdp->cbd_datlen = cpu_to_fec16(size); 582 bdp->cbd_bufaddr = cpu_to_fec32(addr); 583 584 if (fep->bufdesc_ex) { 585 if (fep->quirks & FEC_QUIRK_HAS_AVB) 586 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 587 if (skb->ip_summed == CHECKSUM_PARTIAL) 588 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 589 ebdp->cbd_bdu = 0; 590 ebdp->cbd_esc = cpu_to_fec32(estatus); 591 } 592 593 /* Handle the last BD specially */ 594 if (last_tcp) 595 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 596 if (is_last) { 597 status |= BD_ENET_TX_INTR; 598 if (fep->bufdesc_ex) 599 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 600 } 601 602 bdp->cbd_sc = cpu_to_fec16(status); 603 604 return 0; 605 } 606 607 static int 608 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 609 struct sk_buff *skb, struct net_device *ndev, 610 struct bufdesc *bdp, int index) 611 { 612 struct fec_enet_private *fep = netdev_priv(ndev); 613 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 614 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 615 void *bufaddr; 616 unsigned long dmabuf; 617 unsigned short status; 618 unsigned int estatus = 0; 619 620 status = fec16_to_cpu(bdp->cbd_sc); 621 status &= ~BD_ENET_TX_STATS; 622 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 623 624 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 625 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 626 if (((unsigned long)bufaddr) & fep->tx_align || 627 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 628 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 629 bufaddr = txq->tx_bounce[index]; 630 631 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 632 swap_buffer(bufaddr, hdr_len); 633 634 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 635 hdr_len, DMA_TO_DEVICE); 636 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 637 dev_kfree_skb_any(skb); 638 if (net_ratelimit()) 639 netdev_err(ndev, "Tx DMA memory map failed\n"); 640 return NETDEV_TX_BUSY; 641 } 642 } 643 644 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 645 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 646 647 if (fep->bufdesc_ex) { 648 if (fep->quirks & FEC_QUIRK_HAS_AVB) 649 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 650 if (skb->ip_summed == CHECKSUM_PARTIAL) 651 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 652 ebdp->cbd_bdu = 0; 653 ebdp->cbd_esc = cpu_to_fec32(estatus); 654 } 655 656 bdp->cbd_sc = cpu_to_fec16(status); 657 658 return 0; 659 } 660 661 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 662 struct sk_buff *skb, 663 struct net_device *ndev) 664 { 665 struct fec_enet_private *fep = netdev_priv(ndev); 666 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 667 int total_len, data_left; 668 struct bufdesc *bdp = txq->bd.cur; 669 struct tso_t tso; 670 unsigned int index = 0; 671 int ret; 672 673 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 674 dev_kfree_skb_any(skb); 675 if (net_ratelimit()) 676 netdev_err(ndev, "NOT enough BD for TSO!\n"); 677 return NETDEV_TX_OK; 678 } 679 680 /* Protocol checksum off-load for TCP and UDP. */ 681 if (fec_enet_clear_csum(skb, ndev)) { 682 dev_kfree_skb_any(skb); 683 return NETDEV_TX_OK; 684 } 685 686 /* Initialize the TSO handler, and prepare the first payload */ 687 tso_start(skb, &tso); 688 689 total_len = skb->len - hdr_len; 690 while (total_len > 0) { 691 char *hdr; 692 693 index = fec_enet_get_bd_index(bdp, &txq->bd); 694 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 695 total_len -= data_left; 696 697 /* prepare packet headers: MAC + IP + TCP */ 698 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 699 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 700 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 701 if (ret) 702 goto err_release; 703 704 while (data_left > 0) { 705 int size; 706 707 size = min_t(int, tso.size, data_left); 708 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 709 index = fec_enet_get_bd_index(bdp, &txq->bd); 710 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 711 bdp, index, 712 tso.data, size, 713 size == data_left, 714 total_len == 0); 715 if (ret) 716 goto err_release; 717 718 data_left -= size; 719 tso_build_data(skb, &tso, size); 720 } 721 722 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 723 } 724 725 /* Save skb pointer */ 726 txq->tx_skbuff[index] = skb; 727 728 skb_tx_timestamp(skb); 729 txq->bd.cur = bdp; 730 731 /* Trigger transmission start */ 732 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 733 !readl(txq->bd.reg_desc_active) || 734 !readl(txq->bd.reg_desc_active) || 735 !readl(txq->bd.reg_desc_active) || 736 !readl(txq->bd.reg_desc_active)) 737 writel(0, txq->bd.reg_desc_active); 738 739 return 0; 740 741 err_release: 742 /* TODO: Release all used data descriptors for TSO */ 743 return ret; 744 } 745 746 static netdev_tx_t 747 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 748 { 749 struct fec_enet_private *fep = netdev_priv(ndev); 750 int entries_free; 751 unsigned short queue; 752 struct fec_enet_priv_tx_q *txq; 753 struct netdev_queue *nq; 754 int ret; 755 756 queue = skb_get_queue_mapping(skb); 757 txq = fep->tx_queue[queue]; 758 nq = netdev_get_tx_queue(ndev, queue); 759 760 if (skb_is_gso(skb)) 761 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 762 else 763 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 764 if (ret) 765 return ret; 766 767 entries_free = fec_enet_get_free_txdesc_num(txq); 768 if (entries_free <= txq->tx_stop_threshold) 769 netif_tx_stop_queue(nq); 770 771 return NETDEV_TX_OK; 772 } 773 774 /* Init RX & TX buffer descriptors 775 */ 776 static void fec_enet_bd_init(struct net_device *dev) 777 { 778 struct fec_enet_private *fep = netdev_priv(dev); 779 struct fec_enet_priv_tx_q *txq; 780 struct fec_enet_priv_rx_q *rxq; 781 struct bufdesc *bdp; 782 unsigned int i; 783 unsigned int q; 784 785 for (q = 0; q < fep->num_rx_queues; q++) { 786 /* Initialize the receive buffer descriptors. */ 787 rxq = fep->rx_queue[q]; 788 bdp = rxq->bd.base; 789 790 for (i = 0; i < rxq->bd.ring_size; i++) { 791 792 /* Initialize the BD for every fragment in the page. */ 793 if (bdp->cbd_bufaddr) 794 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 795 else 796 bdp->cbd_sc = cpu_to_fec16(0); 797 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 798 } 799 800 /* Set the last buffer to wrap */ 801 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 802 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 803 804 rxq->bd.cur = rxq->bd.base; 805 } 806 807 for (q = 0; q < fep->num_tx_queues; q++) { 808 /* ...and the same for transmit */ 809 txq = fep->tx_queue[q]; 810 bdp = txq->bd.base; 811 txq->bd.cur = bdp; 812 813 for (i = 0; i < txq->bd.ring_size; i++) { 814 /* Initialize the BD for every fragment in the page. */ 815 bdp->cbd_sc = cpu_to_fec16(0); 816 if (txq->tx_skbuff[i]) { 817 dev_kfree_skb_any(txq->tx_skbuff[i]); 818 txq->tx_skbuff[i] = NULL; 819 } 820 bdp->cbd_bufaddr = cpu_to_fec32(0); 821 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 822 } 823 824 /* Set the last buffer to wrap */ 825 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 826 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 827 txq->dirty_tx = bdp; 828 } 829 } 830 831 static void fec_enet_active_rxring(struct net_device *ndev) 832 { 833 struct fec_enet_private *fep = netdev_priv(ndev); 834 int i; 835 836 for (i = 0; i < fep->num_rx_queues; i++) 837 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 838 } 839 840 static void fec_enet_enable_ring(struct net_device *ndev) 841 { 842 struct fec_enet_private *fep = netdev_priv(ndev); 843 struct fec_enet_priv_tx_q *txq; 844 struct fec_enet_priv_rx_q *rxq; 845 int i; 846 847 for (i = 0; i < fep->num_rx_queues; i++) { 848 rxq = fep->rx_queue[i]; 849 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 850 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 851 852 /* enable DMA1/2 */ 853 if (i) 854 writel(RCMR_MATCHEN | RCMR_CMP(i), 855 fep->hwp + FEC_RCMR(i)); 856 } 857 858 for (i = 0; i < fep->num_tx_queues; i++) { 859 txq = fep->tx_queue[i]; 860 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 861 862 /* enable DMA1/2 */ 863 if (i) 864 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 865 fep->hwp + FEC_DMA_CFG(i)); 866 } 867 } 868 869 static void fec_enet_reset_skb(struct net_device *ndev) 870 { 871 struct fec_enet_private *fep = netdev_priv(ndev); 872 struct fec_enet_priv_tx_q *txq; 873 int i, j; 874 875 for (i = 0; i < fep->num_tx_queues; i++) { 876 txq = fep->tx_queue[i]; 877 878 for (j = 0; j < txq->bd.ring_size; j++) { 879 if (txq->tx_skbuff[j]) { 880 dev_kfree_skb_any(txq->tx_skbuff[j]); 881 txq->tx_skbuff[j] = NULL; 882 } 883 } 884 } 885 } 886 887 /* 888 * This function is called to start or restart the FEC during a link 889 * change, transmit timeout, or to reconfigure the FEC. The network 890 * packet processing for this device must be stopped before this call. 891 */ 892 static void 893 fec_restart(struct net_device *ndev) 894 { 895 struct fec_enet_private *fep = netdev_priv(ndev); 896 u32 val; 897 u32 temp_mac[2]; 898 u32 rcntl = OPT_FRAME_SIZE | 0x04; 899 u32 ecntl = 0x2; /* ETHEREN */ 900 901 /* Whack a reset. We should wait for this. 902 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 903 * instead of reset MAC itself. 904 */ 905 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 906 writel(0, fep->hwp + FEC_ECNTRL); 907 } else { 908 writel(1, fep->hwp + FEC_ECNTRL); 909 udelay(10); 910 } 911 912 /* 913 * enet-mac reset will reset mac address registers too, 914 * so need to reconfigure it. 915 */ 916 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 917 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 918 writel((__force u32)cpu_to_be32(temp_mac[0]), 919 fep->hwp + FEC_ADDR_LOW); 920 writel((__force u32)cpu_to_be32(temp_mac[1]), 921 fep->hwp + FEC_ADDR_HIGH); 922 } 923 924 /* Clear any outstanding interrupt. */ 925 writel(0xffffffff, fep->hwp + FEC_IEVENT); 926 927 fec_enet_bd_init(ndev); 928 929 fec_enet_enable_ring(ndev); 930 931 /* Reset tx SKB buffers. */ 932 fec_enet_reset_skb(ndev); 933 934 /* Enable MII mode */ 935 if (fep->full_duplex == DUPLEX_FULL) { 936 /* FD enable */ 937 writel(0x04, fep->hwp + FEC_X_CNTRL); 938 } else { 939 /* No Rcv on Xmit */ 940 rcntl |= 0x02; 941 writel(0x0, fep->hwp + FEC_X_CNTRL); 942 } 943 944 /* Set MII speed */ 945 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 946 947 #if !defined(CONFIG_M5272) 948 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 949 val = readl(fep->hwp + FEC_RACC); 950 /* align IP header */ 951 val |= FEC_RACC_SHIFT16; 952 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 953 /* set RX checksum */ 954 val |= FEC_RACC_OPTIONS; 955 else 956 val &= ~FEC_RACC_OPTIONS; 957 writel(val, fep->hwp + FEC_RACC); 958 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 959 } 960 #endif 961 962 /* 963 * The phy interface and speed need to get configured 964 * differently on enet-mac. 965 */ 966 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 967 /* Enable flow control and length check */ 968 rcntl |= 0x40000000 | 0x00000020; 969 970 /* RGMII, RMII or MII */ 971 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 972 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 973 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 974 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 975 rcntl |= (1 << 6); 976 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 977 rcntl |= (1 << 8); 978 else 979 rcntl &= ~(1 << 8); 980 981 /* 1G, 100M or 10M */ 982 if (ndev->phydev) { 983 if (ndev->phydev->speed == SPEED_1000) 984 ecntl |= (1 << 5); 985 else if (ndev->phydev->speed == SPEED_100) 986 rcntl &= ~(1 << 9); 987 else 988 rcntl |= (1 << 9); 989 } 990 } else { 991 #ifdef FEC_MIIGSK_ENR 992 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 993 u32 cfgr; 994 /* disable the gasket and wait */ 995 writel(0, fep->hwp + FEC_MIIGSK_ENR); 996 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 997 udelay(1); 998 999 /* 1000 * configure the gasket: 1001 * RMII, 50 MHz, no loopback, no echo 1002 * MII, 25 MHz, no loopback, no echo 1003 */ 1004 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1005 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1006 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1007 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1008 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1009 1010 /* re-enable the gasket */ 1011 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1012 } 1013 #endif 1014 } 1015 1016 #if !defined(CONFIG_M5272) 1017 /* enable pause frame*/ 1018 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1019 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1020 ndev->phydev && ndev->phydev->pause)) { 1021 rcntl |= FEC_ENET_FCE; 1022 1023 /* set FIFO threshold parameter to reduce overrun */ 1024 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1025 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1026 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1027 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1028 1029 /* OPD */ 1030 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1031 } else { 1032 rcntl &= ~FEC_ENET_FCE; 1033 } 1034 #endif /* !defined(CONFIG_M5272) */ 1035 1036 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1037 1038 /* Setup multicast filter. */ 1039 set_multicast_list(ndev); 1040 #ifndef CONFIG_M5272 1041 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1042 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1043 #endif 1044 1045 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1046 /* enable ENET endian swap */ 1047 ecntl |= (1 << 8); 1048 /* enable ENET store and forward mode */ 1049 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1050 } 1051 1052 if (fep->bufdesc_ex) 1053 ecntl |= (1 << 4); 1054 1055 #ifndef CONFIG_M5272 1056 /* Enable the MIB statistic event counters */ 1057 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1058 #endif 1059 1060 /* And last, enable the transmit and receive processing */ 1061 writel(ecntl, fep->hwp + FEC_ECNTRL); 1062 fec_enet_active_rxring(ndev); 1063 1064 if (fep->bufdesc_ex) 1065 fec_ptp_start_cyclecounter(ndev); 1066 1067 /* Enable interrupts we wish to service */ 1068 if (fep->link) 1069 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1070 else 1071 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); 1072 1073 /* Init the interrupt coalescing */ 1074 fec_enet_itr_coal_init(ndev); 1075 1076 } 1077 1078 static void 1079 fec_stop(struct net_device *ndev) 1080 { 1081 struct fec_enet_private *fep = netdev_priv(ndev); 1082 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1083 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1084 u32 val; 1085 1086 /* We cannot expect a graceful transmit stop without link !!! */ 1087 if (fep->link) { 1088 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1089 udelay(10); 1090 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1091 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1092 } 1093 1094 /* Whack a reset. We should wait for this. 1095 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1096 * instead of reset MAC itself. 1097 */ 1098 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1099 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 1100 writel(0, fep->hwp + FEC_ECNTRL); 1101 } else { 1102 writel(1, fep->hwp + FEC_ECNTRL); 1103 udelay(10); 1104 } 1105 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1106 } else { 1107 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1108 val = readl(fep->hwp + FEC_ECNTRL); 1109 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1110 writel(val, fep->hwp + FEC_ECNTRL); 1111 1112 if (pdata && pdata->sleep_mode_enable) 1113 pdata->sleep_mode_enable(true); 1114 } 1115 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1116 1117 /* We have to keep ENET enabled to have MII interrupt stay working */ 1118 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1119 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1120 writel(2, fep->hwp + FEC_ECNTRL); 1121 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1122 } 1123 } 1124 1125 1126 static void 1127 fec_timeout(struct net_device *ndev) 1128 { 1129 struct fec_enet_private *fep = netdev_priv(ndev); 1130 1131 fec_dump(ndev); 1132 1133 ndev->stats.tx_errors++; 1134 1135 schedule_work(&fep->tx_timeout_work); 1136 } 1137 1138 static void fec_enet_timeout_work(struct work_struct *work) 1139 { 1140 struct fec_enet_private *fep = 1141 container_of(work, struct fec_enet_private, tx_timeout_work); 1142 struct net_device *ndev = fep->netdev; 1143 1144 rtnl_lock(); 1145 if (netif_device_present(ndev) || netif_running(ndev)) { 1146 napi_disable(&fep->napi); 1147 netif_tx_lock_bh(ndev); 1148 fec_restart(ndev); 1149 netif_wake_queue(ndev); 1150 netif_tx_unlock_bh(ndev); 1151 napi_enable(&fep->napi); 1152 } 1153 rtnl_unlock(); 1154 } 1155 1156 static void 1157 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1158 struct skb_shared_hwtstamps *hwtstamps) 1159 { 1160 unsigned long flags; 1161 u64 ns; 1162 1163 spin_lock_irqsave(&fep->tmreg_lock, flags); 1164 ns = timecounter_cyc2time(&fep->tc, ts); 1165 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1166 1167 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1168 hwtstamps->hwtstamp = ns_to_ktime(ns); 1169 } 1170 1171 static void 1172 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1173 { 1174 struct fec_enet_private *fep; 1175 struct bufdesc *bdp; 1176 unsigned short status; 1177 struct sk_buff *skb; 1178 struct fec_enet_priv_tx_q *txq; 1179 struct netdev_queue *nq; 1180 int index = 0; 1181 int entries_free; 1182 1183 fep = netdev_priv(ndev); 1184 1185 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1186 1187 txq = fep->tx_queue[queue_id]; 1188 /* get next bdp of dirty_tx */ 1189 nq = netdev_get_tx_queue(ndev, queue_id); 1190 bdp = txq->dirty_tx; 1191 1192 /* get next bdp of dirty_tx */ 1193 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1194 1195 while (bdp != READ_ONCE(txq->bd.cur)) { 1196 /* Order the load of bd.cur and cbd_sc */ 1197 rmb(); 1198 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1199 if (status & BD_ENET_TX_READY) 1200 break; 1201 1202 index = fec_enet_get_bd_index(bdp, &txq->bd); 1203 1204 skb = txq->tx_skbuff[index]; 1205 txq->tx_skbuff[index] = NULL; 1206 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1207 dma_unmap_single(&fep->pdev->dev, 1208 fec32_to_cpu(bdp->cbd_bufaddr), 1209 fec16_to_cpu(bdp->cbd_datlen), 1210 DMA_TO_DEVICE); 1211 bdp->cbd_bufaddr = cpu_to_fec32(0); 1212 if (!skb) 1213 goto skb_done; 1214 1215 /* Check for errors. */ 1216 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1217 BD_ENET_TX_RL | BD_ENET_TX_UN | 1218 BD_ENET_TX_CSL)) { 1219 ndev->stats.tx_errors++; 1220 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1221 ndev->stats.tx_heartbeat_errors++; 1222 if (status & BD_ENET_TX_LC) /* Late collision */ 1223 ndev->stats.tx_window_errors++; 1224 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1225 ndev->stats.tx_aborted_errors++; 1226 if (status & BD_ENET_TX_UN) /* Underrun */ 1227 ndev->stats.tx_fifo_errors++; 1228 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1229 ndev->stats.tx_carrier_errors++; 1230 } else { 1231 ndev->stats.tx_packets++; 1232 ndev->stats.tx_bytes += skb->len; 1233 } 1234 1235 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 1236 fep->bufdesc_ex) { 1237 struct skb_shared_hwtstamps shhwtstamps; 1238 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1239 1240 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1241 skb_tstamp_tx(skb, &shhwtstamps); 1242 } 1243 1244 /* Deferred means some collisions occurred during transmit, 1245 * but we eventually sent the packet OK. 1246 */ 1247 if (status & BD_ENET_TX_DEF) 1248 ndev->stats.collisions++; 1249 1250 /* Free the sk buffer associated with this last transmit */ 1251 dev_kfree_skb_any(skb); 1252 skb_done: 1253 /* Make sure the update to bdp and tx_skbuff are performed 1254 * before dirty_tx 1255 */ 1256 wmb(); 1257 txq->dirty_tx = bdp; 1258 1259 /* Update pointer to next buffer descriptor to be transmitted */ 1260 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1261 1262 /* Since we have freed up a buffer, the ring is no longer full 1263 */ 1264 if (netif_queue_stopped(ndev)) { 1265 entries_free = fec_enet_get_free_txdesc_num(txq); 1266 if (entries_free >= txq->tx_wake_threshold) 1267 netif_tx_wake_queue(nq); 1268 } 1269 } 1270 1271 /* ERR006538: Keep the transmitter going */ 1272 if (bdp != txq->bd.cur && 1273 readl(txq->bd.reg_desc_active) == 0) 1274 writel(0, txq->bd.reg_desc_active); 1275 } 1276 1277 static void 1278 fec_enet_tx(struct net_device *ndev) 1279 { 1280 struct fec_enet_private *fep = netdev_priv(ndev); 1281 u16 queue_id; 1282 /* First process class A queue, then Class B and Best Effort queue */ 1283 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) { 1284 clear_bit(queue_id, &fep->work_tx); 1285 fec_enet_tx_queue(ndev, queue_id); 1286 } 1287 return; 1288 } 1289 1290 static int 1291 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1292 { 1293 struct fec_enet_private *fep = netdev_priv(ndev); 1294 int off; 1295 1296 off = ((unsigned long)skb->data) & fep->rx_align; 1297 if (off) 1298 skb_reserve(skb, fep->rx_align + 1 - off); 1299 1300 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1301 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1302 if (net_ratelimit()) 1303 netdev_err(ndev, "Rx DMA memory map failed\n"); 1304 return -ENOMEM; 1305 } 1306 1307 return 0; 1308 } 1309 1310 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1311 struct bufdesc *bdp, u32 length, bool swap) 1312 { 1313 struct fec_enet_private *fep = netdev_priv(ndev); 1314 struct sk_buff *new_skb; 1315 1316 if (length > fep->rx_copybreak) 1317 return false; 1318 1319 new_skb = netdev_alloc_skb(ndev, length); 1320 if (!new_skb) 1321 return false; 1322 1323 dma_sync_single_for_cpu(&fep->pdev->dev, 1324 fec32_to_cpu(bdp->cbd_bufaddr), 1325 FEC_ENET_RX_FRSIZE - fep->rx_align, 1326 DMA_FROM_DEVICE); 1327 if (!swap) 1328 memcpy(new_skb->data, (*skb)->data, length); 1329 else 1330 swap_buffer2(new_skb->data, (*skb)->data, length); 1331 *skb = new_skb; 1332 1333 return true; 1334 } 1335 1336 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1337 * When we update through the ring, if the next incoming buffer has 1338 * not been given to the system, we just set the empty indicator, 1339 * effectively tossing the packet. 1340 */ 1341 static int 1342 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1343 { 1344 struct fec_enet_private *fep = netdev_priv(ndev); 1345 struct fec_enet_priv_rx_q *rxq; 1346 struct bufdesc *bdp; 1347 unsigned short status; 1348 struct sk_buff *skb_new = NULL; 1349 struct sk_buff *skb; 1350 ushort pkt_len; 1351 __u8 *data; 1352 int pkt_received = 0; 1353 struct bufdesc_ex *ebdp = NULL; 1354 bool vlan_packet_rcvd = false; 1355 u16 vlan_tag; 1356 int index = 0; 1357 bool is_copybreak; 1358 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1359 1360 #ifdef CONFIG_M532x 1361 flush_cache_all(); 1362 #endif 1363 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1364 rxq = fep->rx_queue[queue_id]; 1365 1366 /* First, grab all of the stats for the incoming packet. 1367 * These get messed up if we get called due to a busy condition. 1368 */ 1369 bdp = rxq->bd.cur; 1370 1371 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1372 1373 if (pkt_received >= budget) 1374 break; 1375 pkt_received++; 1376 1377 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); 1378 1379 /* Check for errors. */ 1380 status ^= BD_ENET_RX_LAST; 1381 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1382 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1383 BD_ENET_RX_CL)) { 1384 ndev->stats.rx_errors++; 1385 if (status & BD_ENET_RX_OV) { 1386 /* FIFO overrun */ 1387 ndev->stats.rx_fifo_errors++; 1388 goto rx_processing_done; 1389 } 1390 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1391 | BD_ENET_RX_LAST)) { 1392 /* Frame too long or too short. */ 1393 ndev->stats.rx_length_errors++; 1394 if (status & BD_ENET_RX_LAST) 1395 netdev_err(ndev, "rcv is not +last\n"); 1396 } 1397 if (status & BD_ENET_RX_CR) /* CRC Error */ 1398 ndev->stats.rx_crc_errors++; 1399 /* Report late collisions as a frame error. */ 1400 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1401 ndev->stats.rx_frame_errors++; 1402 goto rx_processing_done; 1403 } 1404 1405 /* Process the incoming frame. */ 1406 ndev->stats.rx_packets++; 1407 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1408 ndev->stats.rx_bytes += pkt_len; 1409 1410 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1411 skb = rxq->rx_skbuff[index]; 1412 1413 /* The packet length includes FCS, but we don't want to 1414 * include that when passing upstream as it messes up 1415 * bridging applications. 1416 */ 1417 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1418 need_swap); 1419 if (!is_copybreak) { 1420 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1421 if (unlikely(!skb_new)) { 1422 ndev->stats.rx_dropped++; 1423 goto rx_processing_done; 1424 } 1425 dma_unmap_single(&fep->pdev->dev, 1426 fec32_to_cpu(bdp->cbd_bufaddr), 1427 FEC_ENET_RX_FRSIZE - fep->rx_align, 1428 DMA_FROM_DEVICE); 1429 } 1430 1431 prefetch(skb->data - NET_IP_ALIGN); 1432 skb_put(skb, pkt_len - 4); 1433 data = skb->data; 1434 1435 #if !defined(CONFIG_M5272) 1436 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1437 data = skb_pull_inline(skb, 2); 1438 #endif 1439 1440 if (!is_copybreak && need_swap) 1441 swap_buffer(data, pkt_len); 1442 1443 /* Extract the enhanced buffer descriptor */ 1444 ebdp = NULL; 1445 if (fep->bufdesc_ex) 1446 ebdp = (struct bufdesc_ex *)bdp; 1447 1448 /* If this is a VLAN packet remove the VLAN Tag */ 1449 vlan_packet_rcvd = false; 1450 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1451 fep->bufdesc_ex && 1452 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1453 /* Push and remove the vlan tag */ 1454 struct vlan_hdr *vlan_header = 1455 (struct vlan_hdr *) (data + ETH_HLEN); 1456 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1457 1458 vlan_packet_rcvd = true; 1459 1460 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1461 skb_pull(skb, VLAN_HLEN); 1462 } 1463 1464 skb->protocol = eth_type_trans(skb, ndev); 1465 1466 /* Get receive timestamp from the skb */ 1467 if (fep->hwts_rx_en && fep->bufdesc_ex) 1468 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1469 skb_hwtstamps(skb)); 1470 1471 if (fep->bufdesc_ex && 1472 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1473 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1474 /* don't check it */ 1475 skb->ip_summed = CHECKSUM_UNNECESSARY; 1476 } else { 1477 skb_checksum_none_assert(skb); 1478 } 1479 } 1480 1481 /* Handle received VLAN packets */ 1482 if (vlan_packet_rcvd) 1483 __vlan_hwaccel_put_tag(skb, 1484 htons(ETH_P_8021Q), 1485 vlan_tag); 1486 1487 napi_gro_receive(&fep->napi, skb); 1488 1489 if (is_copybreak) { 1490 dma_sync_single_for_device(&fep->pdev->dev, 1491 fec32_to_cpu(bdp->cbd_bufaddr), 1492 FEC_ENET_RX_FRSIZE - fep->rx_align, 1493 DMA_FROM_DEVICE); 1494 } else { 1495 rxq->rx_skbuff[index] = skb_new; 1496 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1497 } 1498 1499 rx_processing_done: 1500 /* Clear the status flags for this buffer */ 1501 status &= ~BD_ENET_RX_STATS; 1502 1503 /* Mark the buffer empty */ 1504 status |= BD_ENET_RX_EMPTY; 1505 1506 if (fep->bufdesc_ex) { 1507 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1508 1509 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1510 ebdp->cbd_prot = 0; 1511 ebdp->cbd_bdu = 0; 1512 } 1513 /* Make sure the updates to rest of the descriptor are 1514 * performed before transferring ownership. 1515 */ 1516 wmb(); 1517 bdp->cbd_sc = cpu_to_fec16(status); 1518 1519 /* Update BD pointer to next entry */ 1520 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1521 1522 /* Doing this here will keep the FEC running while we process 1523 * incoming frames. On a heavily loaded network, we should be 1524 * able to keep up at the expense of system resources. 1525 */ 1526 writel(0, rxq->bd.reg_desc_active); 1527 } 1528 rxq->bd.cur = bdp; 1529 return pkt_received; 1530 } 1531 1532 static int 1533 fec_enet_rx(struct net_device *ndev, int budget) 1534 { 1535 int pkt_received = 0; 1536 u16 queue_id; 1537 struct fec_enet_private *fep = netdev_priv(ndev); 1538 1539 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) { 1540 int ret; 1541 1542 ret = fec_enet_rx_queue(ndev, 1543 budget - pkt_received, queue_id); 1544 1545 if (ret < budget - pkt_received) 1546 clear_bit(queue_id, &fep->work_rx); 1547 1548 pkt_received += ret; 1549 } 1550 return pkt_received; 1551 } 1552 1553 static bool 1554 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events) 1555 { 1556 if (int_events == 0) 1557 return false; 1558 1559 if (int_events & FEC_ENET_RXF) 1560 fep->work_rx |= (1 << 2); 1561 if (int_events & FEC_ENET_RXF_1) 1562 fep->work_rx |= (1 << 0); 1563 if (int_events & FEC_ENET_RXF_2) 1564 fep->work_rx |= (1 << 1); 1565 1566 if (int_events & FEC_ENET_TXF) 1567 fep->work_tx |= (1 << 2); 1568 if (int_events & FEC_ENET_TXF_1) 1569 fep->work_tx |= (1 << 0); 1570 if (int_events & FEC_ENET_TXF_2) 1571 fep->work_tx |= (1 << 1); 1572 1573 return true; 1574 } 1575 1576 static irqreturn_t 1577 fec_enet_interrupt(int irq, void *dev_id) 1578 { 1579 struct net_device *ndev = dev_id; 1580 struct fec_enet_private *fep = netdev_priv(ndev); 1581 uint int_events; 1582 irqreturn_t ret = IRQ_NONE; 1583 1584 int_events = readl(fep->hwp + FEC_IEVENT); 1585 writel(int_events, fep->hwp + FEC_IEVENT); 1586 fec_enet_collect_events(fep, int_events); 1587 1588 if ((fep->work_tx || fep->work_rx) && fep->link) { 1589 ret = IRQ_HANDLED; 1590 1591 if (napi_schedule_prep(&fep->napi)) { 1592 /* Disable the NAPI interrupts */ 1593 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK); 1594 __napi_schedule(&fep->napi); 1595 } 1596 } 1597 1598 if (int_events & FEC_ENET_MII) { 1599 ret = IRQ_HANDLED; 1600 complete(&fep->mdio_done); 1601 } 1602 1603 if (fep->ptp_clock) 1604 fec_ptp_check_pps_event(fep); 1605 1606 return ret; 1607 } 1608 1609 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1610 { 1611 struct net_device *ndev = napi->dev; 1612 struct fec_enet_private *fep = netdev_priv(ndev); 1613 int pkts; 1614 1615 pkts = fec_enet_rx(ndev, budget); 1616 1617 fec_enet_tx(ndev); 1618 1619 if (pkts < budget) { 1620 napi_complete(napi); 1621 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1622 } 1623 return pkts; 1624 } 1625 1626 /* ------------------------------------------------------------------------- */ 1627 static void fec_get_mac(struct net_device *ndev) 1628 { 1629 struct fec_enet_private *fep = netdev_priv(ndev); 1630 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1631 unsigned char *iap, tmpaddr[ETH_ALEN]; 1632 1633 /* 1634 * try to get mac address in following order: 1635 * 1636 * 1) module parameter via kernel command line in form 1637 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1638 */ 1639 iap = macaddr; 1640 1641 /* 1642 * 2) from device tree data 1643 */ 1644 if (!is_valid_ether_addr(iap)) { 1645 struct device_node *np = fep->pdev->dev.of_node; 1646 if (np) { 1647 const char *mac = of_get_mac_address(np); 1648 if (mac) 1649 iap = (unsigned char *) mac; 1650 } 1651 } 1652 1653 /* 1654 * 3) from flash or fuse (via platform data) 1655 */ 1656 if (!is_valid_ether_addr(iap)) { 1657 #ifdef CONFIG_M5272 1658 if (FEC_FLASHMAC) 1659 iap = (unsigned char *)FEC_FLASHMAC; 1660 #else 1661 if (pdata) 1662 iap = (unsigned char *)&pdata->mac; 1663 #endif 1664 } 1665 1666 /* 1667 * 4) FEC mac registers set by bootloader 1668 */ 1669 if (!is_valid_ether_addr(iap)) { 1670 *((__be32 *) &tmpaddr[0]) = 1671 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1672 *((__be16 *) &tmpaddr[4]) = 1673 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1674 iap = &tmpaddr[0]; 1675 } 1676 1677 /* 1678 * 5) random mac address 1679 */ 1680 if (!is_valid_ether_addr(iap)) { 1681 /* Report it and use a random ethernet address instead */ 1682 netdev_err(ndev, "Invalid MAC address: %pM\n", iap); 1683 eth_hw_addr_random(ndev); 1684 netdev_info(ndev, "Using random MAC address: %pM\n", 1685 ndev->dev_addr); 1686 return; 1687 } 1688 1689 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1690 1691 /* Adjust MAC if using macaddr */ 1692 if (iap == macaddr) 1693 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1694 } 1695 1696 /* ------------------------------------------------------------------------- */ 1697 1698 /* 1699 * Phy section 1700 */ 1701 static void fec_enet_adjust_link(struct net_device *ndev) 1702 { 1703 struct fec_enet_private *fep = netdev_priv(ndev); 1704 struct phy_device *phy_dev = ndev->phydev; 1705 int status_change = 0; 1706 1707 /* Prevent a state halted on mii error */ 1708 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 1709 phy_dev->state = PHY_RESUMING; 1710 return; 1711 } 1712 1713 /* 1714 * If the netdev is down, or is going down, we're not interested 1715 * in link state events, so just mark our idea of the link as down 1716 * and ignore the event. 1717 */ 1718 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1719 fep->link = 0; 1720 } else if (phy_dev->link) { 1721 if (!fep->link) { 1722 fep->link = phy_dev->link; 1723 status_change = 1; 1724 } 1725 1726 if (fep->full_duplex != phy_dev->duplex) { 1727 fep->full_duplex = phy_dev->duplex; 1728 status_change = 1; 1729 } 1730 1731 if (phy_dev->speed != fep->speed) { 1732 fep->speed = phy_dev->speed; 1733 status_change = 1; 1734 } 1735 1736 /* if any of the above changed restart the FEC */ 1737 if (status_change) { 1738 napi_disable(&fep->napi); 1739 netif_tx_lock_bh(ndev); 1740 fec_restart(ndev); 1741 netif_wake_queue(ndev); 1742 netif_tx_unlock_bh(ndev); 1743 napi_enable(&fep->napi); 1744 } 1745 } else { 1746 if (fep->link) { 1747 napi_disable(&fep->napi); 1748 netif_tx_lock_bh(ndev); 1749 fec_stop(ndev); 1750 netif_tx_unlock_bh(ndev); 1751 napi_enable(&fep->napi); 1752 fep->link = phy_dev->link; 1753 status_change = 1; 1754 } 1755 } 1756 1757 if (status_change) 1758 phy_print_status(phy_dev); 1759 } 1760 1761 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1762 { 1763 struct fec_enet_private *fep = bus->priv; 1764 struct device *dev = &fep->pdev->dev; 1765 unsigned long time_left; 1766 int ret = 0; 1767 1768 ret = pm_runtime_get_sync(dev); 1769 if (ret < 0) 1770 return ret; 1771 1772 fep->mii_timeout = 0; 1773 reinit_completion(&fep->mdio_done); 1774 1775 /* start a read op */ 1776 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 1777 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1778 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1779 1780 /* wait for end of transfer */ 1781 time_left = wait_for_completion_timeout(&fep->mdio_done, 1782 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1783 if (time_left == 0) { 1784 fep->mii_timeout = 1; 1785 netdev_err(fep->netdev, "MDIO read timeout\n"); 1786 ret = -ETIMEDOUT; 1787 goto out; 1788 } 1789 1790 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1791 1792 out: 1793 pm_runtime_mark_last_busy(dev); 1794 pm_runtime_put_autosuspend(dev); 1795 1796 return ret; 1797 } 1798 1799 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1800 u16 value) 1801 { 1802 struct fec_enet_private *fep = bus->priv; 1803 struct device *dev = &fep->pdev->dev; 1804 unsigned long time_left; 1805 int ret; 1806 1807 ret = pm_runtime_get_sync(dev); 1808 if (ret < 0) 1809 return ret; 1810 else 1811 ret = 0; 1812 1813 fep->mii_timeout = 0; 1814 reinit_completion(&fep->mdio_done); 1815 1816 /* start a write op */ 1817 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 1818 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1819 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1820 fep->hwp + FEC_MII_DATA); 1821 1822 /* wait for end of transfer */ 1823 time_left = wait_for_completion_timeout(&fep->mdio_done, 1824 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1825 if (time_left == 0) { 1826 fep->mii_timeout = 1; 1827 netdev_err(fep->netdev, "MDIO write timeout\n"); 1828 ret = -ETIMEDOUT; 1829 } 1830 1831 pm_runtime_mark_last_busy(dev); 1832 pm_runtime_put_autosuspend(dev); 1833 1834 return ret; 1835 } 1836 1837 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1838 { 1839 struct fec_enet_private *fep = netdev_priv(ndev); 1840 int ret; 1841 1842 if (enable) { 1843 ret = clk_prepare_enable(fep->clk_ahb); 1844 if (ret) 1845 return ret; 1846 if (fep->clk_enet_out) { 1847 ret = clk_prepare_enable(fep->clk_enet_out); 1848 if (ret) 1849 goto failed_clk_enet_out; 1850 } 1851 if (fep->clk_ptp) { 1852 mutex_lock(&fep->ptp_clk_mutex); 1853 ret = clk_prepare_enable(fep->clk_ptp); 1854 if (ret) { 1855 mutex_unlock(&fep->ptp_clk_mutex); 1856 goto failed_clk_ptp; 1857 } else { 1858 fep->ptp_clk_on = true; 1859 } 1860 mutex_unlock(&fep->ptp_clk_mutex); 1861 } 1862 if (fep->clk_ref) { 1863 ret = clk_prepare_enable(fep->clk_ref); 1864 if (ret) 1865 goto failed_clk_ref; 1866 } 1867 } else { 1868 clk_disable_unprepare(fep->clk_ahb); 1869 if (fep->clk_enet_out) 1870 clk_disable_unprepare(fep->clk_enet_out); 1871 if (fep->clk_ptp) { 1872 mutex_lock(&fep->ptp_clk_mutex); 1873 clk_disable_unprepare(fep->clk_ptp); 1874 fep->ptp_clk_on = false; 1875 mutex_unlock(&fep->ptp_clk_mutex); 1876 } 1877 if (fep->clk_ref) 1878 clk_disable_unprepare(fep->clk_ref); 1879 } 1880 1881 return 0; 1882 1883 failed_clk_ref: 1884 if (fep->clk_ref) 1885 clk_disable_unprepare(fep->clk_ref); 1886 failed_clk_ptp: 1887 if (fep->clk_enet_out) 1888 clk_disable_unprepare(fep->clk_enet_out); 1889 failed_clk_enet_out: 1890 clk_disable_unprepare(fep->clk_ahb); 1891 1892 return ret; 1893 } 1894 1895 static int fec_enet_mii_probe(struct net_device *ndev) 1896 { 1897 struct fec_enet_private *fep = netdev_priv(ndev); 1898 struct phy_device *phy_dev = NULL; 1899 char mdio_bus_id[MII_BUS_ID_SIZE]; 1900 char phy_name[MII_BUS_ID_SIZE + 3]; 1901 int phy_id; 1902 int dev_id = fep->dev_id; 1903 1904 if (fep->phy_node) { 1905 phy_dev = of_phy_connect(ndev, fep->phy_node, 1906 &fec_enet_adjust_link, 0, 1907 fep->phy_interface); 1908 if (!phy_dev) 1909 return -ENODEV; 1910 } else { 1911 /* check for attached phy */ 1912 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1913 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 1914 continue; 1915 if (dev_id--) 1916 continue; 1917 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1918 break; 1919 } 1920 1921 if (phy_id >= PHY_MAX_ADDR) { 1922 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1923 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 1924 phy_id = 0; 1925 } 1926 1927 snprintf(phy_name, sizeof(phy_name), 1928 PHY_ID_FMT, mdio_bus_id, phy_id); 1929 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 1930 fep->phy_interface); 1931 } 1932 1933 if (IS_ERR(phy_dev)) { 1934 netdev_err(ndev, "could not attach to PHY\n"); 1935 return PTR_ERR(phy_dev); 1936 } 1937 1938 /* mask with MAC supported features */ 1939 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 1940 phy_dev->supported &= PHY_GBIT_FEATURES; 1941 phy_dev->supported &= ~SUPPORTED_1000baseT_Half; 1942 #if !defined(CONFIG_M5272) 1943 phy_dev->supported |= SUPPORTED_Pause; 1944 #endif 1945 } 1946 else 1947 phy_dev->supported &= PHY_BASIC_FEATURES; 1948 1949 phy_dev->advertising = phy_dev->supported; 1950 1951 fep->link = 0; 1952 fep->full_duplex = 0; 1953 1954 phy_attached_info(phy_dev); 1955 1956 return 0; 1957 } 1958 1959 static int fec_enet_mii_init(struct platform_device *pdev) 1960 { 1961 static struct mii_bus *fec0_mii_bus; 1962 struct net_device *ndev = platform_get_drvdata(pdev); 1963 struct fec_enet_private *fep = netdev_priv(ndev); 1964 struct device_node *node; 1965 int err = -ENXIO; 1966 u32 mii_speed, holdtime; 1967 1968 /* 1969 * The i.MX28 dual fec interfaces are not equal. 1970 * Here are the differences: 1971 * 1972 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1973 * - fec0 acts as the 1588 time master while fec1 is slave 1974 * - external phys can only be configured by fec0 1975 * 1976 * That is to say fec1 can not work independently. It only works 1977 * when fec0 is working. The reason behind this design is that the 1978 * second interface is added primarily for Switch mode. 1979 * 1980 * Because of the last point above, both phys are attached on fec0 1981 * mdio interface in board design, and need to be configured by 1982 * fec0 mii_bus. 1983 */ 1984 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 1985 /* fec1 uses fec0 mii_bus */ 1986 if (mii_cnt && fec0_mii_bus) { 1987 fep->mii_bus = fec0_mii_bus; 1988 mii_cnt++; 1989 return 0; 1990 } 1991 return -ENOENT; 1992 } 1993 1994 fep->mii_timeout = 0; 1995 1996 /* 1997 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 1998 * 1999 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2000 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2001 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2002 * document. 2003 */ 2004 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000); 2005 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2006 mii_speed--; 2007 if (mii_speed > 63) { 2008 dev_err(&pdev->dev, 2009 "fec clock (%lu) to fast to get right mii speed\n", 2010 clk_get_rate(fep->clk_ipg)); 2011 err = -EINVAL; 2012 goto err_out; 2013 } 2014 2015 /* 2016 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2017 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2018 * versions are RAZ there, so just ignore the difference and write the 2019 * register always. 2020 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2021 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2022 * output. 2023 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2024 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2025 * holdtime cannot result in a value greater than 3. 2026 */ 2027 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2028 2029 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2030 2031 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2032 2033 fep->mii_bus = mdiobus_alloc(); 2034 if (fep->mii_bus == NULL) { 2035 err = -ENOMEM; 2036 goto err_out; 2037 } 2038 2039 fep->mii_bus->name = "fec_enet_mii_bus"; 2040 fep->mii_bus->read = fec_enet_mdio_read; 2041 fep->mii_bus->write = fec_enet_mdio_write; 2042 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2043 pdev->name, fep->dev_id + 1); 2044 fep->mii_bus->priv = fep; 2045 fep->mii_bus->parent = &pdev->dev; 2046 2047 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2048 if (node) { 2049 err = of_mdiobus_register(fep->mii_bus, node); 2050 of_node_put(node); 2051 } else { 2052 err = mdiobus_register(fep->mii_bus); 2053 } 2054 2055 if (err) 2056 goto err_out_free_mdiobus; 2057 2058 mii_cnt++; 2059 2060 /* save fec0 mii_bus */ 2061 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2062 fec0_mii_bus = fep->mii_bus; 2063 2064 return 0; 2065 2066 err_out_free_mdiobus: 2067 mdiobus_free(fep->mii_bus); 2068 err_out: 2069 return err; 2070 } 2071 2072 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2073 { 2074 if (--mii_cnt == 0) { 2075 mdiobus_unregister(fep->mii_bus); 2076 mdiobus_free(fep->mii_bus); 2077 } 2078 } 2079 2080 static void fec_enet_get_drvinfo(struct net_device *ndev, 2081 struct ethtool_drvinfo *info) 2082 { 2083 struct fec_enet_private *fep = netdev_priv(ndev); 2084 2085 strlcpy(info->driver, fep->pdev->dev.driver->name, 2086 sizeof(info->driver)); 2087 strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); 2088 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2089 } 2090 2091 static int fec_enet_get_regs_len(struct net_device *ndev) 2092 { 2093 struct fec_enet_private *fep = netdev_priv(ndev); 2094 struct resource *r; 2095 int s = 0; 2096 2097 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2098 if (r) 2099 s = resource_size(r); 2100 2101 return s; 2102 } 2103 2104 /* List of registers that can be safety be read to dump them with ethtool */ 2105 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2106 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 2107 static u32 fec_enet_register_offset[] = { 2108 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2109 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2110 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2111 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2112 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2113 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2114 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2115 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2116 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2117 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2118 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2119 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2120 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2121 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2122 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2123 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2124 RMON_T_P_GTE2048, RMON_T_OCTETS, 2125 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2126 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2127 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2128 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2129 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2130 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2131 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2132 RMON_R_P_GTE2048, RMON_R_OCTETS, 2133 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2134 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2135 }; 2136 #else 2137 static u32 fec_enet_register_offset[] = { 2138 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2139 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2140 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2141 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2142 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2143 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2144 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2145 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2146 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2147 }; 2148 #endif 2149 2150 static void fec_enet_get_regs(struct net_device *ndev, 2151 struct ethtool_regs *regs, void *regbuf) 2152 { 2153 struct fec_enet_private *fep = netdev_priv(ndev); 2154 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2155 u32 *buf = (u32 *)regbuf; 2156 u32 i, off; 2157 2158 memset(buf, 0, regs->len); 2159 2160 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2161 off = fec_enet_register_offset[i] / 4; 2162 buf[off] = readl(&theregs[off]); 2163 } 2164 } 2165 2166 static int fec_enet_get_ts_info(struct net_device *ndev, 2167 struct ethtool_ts_info *info) 2168 { 2169 struct fec_enet_private *fep = netdev_priv(ndev); 2170 2171 if (fep->bufdesc_ex) { 2172 2173 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2174 SOF_TIMESTAMPING_RX_SOFTWARE | 2175 SOF_TIMESTAMPING_SOFTWARE | 2176 SOF_TIMESTAMPING_TX_HARDWARE | 2177 SOF_TIMESTAMPING_RX_HARDWARE | 2178 SOF_TIMESTAMPING_RAW_HARDWARE; 2179 if (fep->ptp_clock) 2180 info->phc_index = ptp_clock_index(fep->ptp_clock); 2181 else 2182 info->phc_index = -1; 2183 2184 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2185 (1 << HWTSTAMP_TX_ON); 2186 2187 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2188 (1 << HWTSTAMP_FILTER_ALL); 2189 return 0; 2190 } else { 2191 return ethtool_op_get_ts_info(ndev, info); 2192 } 2193 } 2194 2195 #if !defined(CONFIG_M5272) 2196 2197 static void fec_enet_get_pauseparam(struct net_device *ndev, 2198 struct ethtool_pauseparam *pause) 2199 { 2200 struct fec_enet_private *fep = netdev_priv(ndev); 2201 2202 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2203 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2204 pause->rx_pause = pause->tx_pause; 2205 } 2206 2207 static int fec_enet_set_pauseparam(struct net_device *ndev, 2208 struct ethtool_pauseparam *pause) 2209 { 2210 struct fec_enet_private *fep = netdev_priv(ndev); 2211 2212 if (!ndev->phydev) 2213 return -ENODEV; 2214 2215 if (pause->tx_pause != pause->rx_pause) { 2216 netdev_info(ndev, 2217 "hardware only support enable/disable both tx and rx"); 2218 return -EINVAL; 2219 } 2220 2221 fep->pause_flag = 0; 2222 2223 /* tx pause must be same as rx pause */ 2224 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2225 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2226 2227 if (pause->rx_pause || pause->autoneg) { 2228 ndev->phydev->supported |= ADVERTISED_Pause; 2229 ndev->phydev->advertising |= ADVERTISED_Pause; 2230 } else { 2231 ndev->phydev->supported &= ~ADVERTISED_Pause; 2232 ndev->phydev->advertising &= ~ADVERTISED_Pause; 2233 } 2234 2235 if (pause->autoneg) { 2236 if (netif_running(ndev)) 2237 fec_stop(ndev); 2238 phy_start_aneg(ndev->phydev); 2239 } 2240 if (netif_running(ndev)) { 2241 napi_disable(&fep->napi); 2242 netif_tx_lock_bh(ndev); 2243 fec_restart(ndev); 2244 netif_wake_queue(ndev); 2245 netif_tx_unlock_bh(ndev); 2246 napi_enable(&fep->napi); 2247 } 2248 2249 return 0; 2250 } 2251 2252 static const struct fec_stat { 2253 char name[ETH_GSTRING_LEN]; 2254 u16 offset; 2255 } fec_stats[] = { 2256 /* RMON TX */ 2257 { "tx_dropped", RMON_T_DROP }, 2258 { "tx_packets", RMON_T_PACKETS }, 2259 { "tx_broadcast", RMON_T_BC_PKT }, 2260 { "tx_multicast", RMON_T_MC_PKT }, 2261 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2262 { "tx_undersize", RMON_T_UNDERSIZE }, 2263 { "tx_oversize", RMON_T_OVERSIZE }, 2264 { "tx_fragment", RMON_T_FRAG }, 2265 { "tx_jabber", RMON_T_JAB }, 2266 { "tx_collision", RMON_T_COL }, 2267 { "tx_64byte", RMON_T_P64 }, 2268 { "tx_65to127byte", RMON_T_P65TO127 }, 2269 { "tx_128to255byte", RMON_T_P128TO255 }, 2270 { "tx_256to511byte", RMON_T_P256TO511 }, 2271 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2272 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2273 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2274 { "tx_octets", RMON_T_OCTETS }, 2275 2276 /* IEEE TX */ 2277 { "IEEE_tx_drop", IEEE_T_DROP }, 2278 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2279 { "IEEE_tx_1col", IEEE_T_1COL }, 2280 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2281 { "IEEE_tx_def", IEEE_T_DEF }, 2282 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2283 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2284 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2285 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2286 { "IEEE_tx_sqe", IEEE_T_SQE }, 2287 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2288 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2289 2290 /* RMON RX */ 2291 { "rx_packets", RMON_R_PACKETS }, 2292 { "rx_broadcast", RMON_R_BC_PKT }, 2293 { "rx_multicast", RMON_R_MC_PKT }, 2294 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2295 { "rx_undersize", RMON_R_UNDERSIZE }, 2296 { "rx_oversize", RMON_R_OVERSIZE }, 2297 { "rx_fragment", RMON_R_FRAG }, 2298 { "rx_jabber", RMON_R_JAB }, 2299 { "rx_64byte", RMON_R_P64 }, 2300 { "rx_65to127byte", RMON_R_P65TO127 }, 2301 { "rx_128to255byte", RMON_R_P128TO255 }, 2302 { "rx_256to511byte", RMON_R_P256TO511 }, 2303 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2304 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2305 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2306 { "rx_octets", RMON_R_OCTETS }, 2307 2308 /* IEEE RX */ 2309 { "IEEE_rx_drop", IEEE_R_DROP }, 2310 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2311 { "IEEE_rx_crc", IEEE_R_CRC }, 2312 { "IEEE_rx_align", IEEE_R_ALIGN }, 2313 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2314 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2315 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2316 }; 2317 2318 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2319 struct ethtool_stats *stats, u64 *data) 2320 { 2321 struct fec_enet_private *fep = netdev_priv(dev); 2322 int i; 2323 2324 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2325 data[i] = readl(fep->hwp + fec_stats[i].offset); 2326 } 2327 2328 static void fec_enet_get_strings(struct net_device *netdev, 2329 u32 stringset, u8 *data) 2330 { 2331 int i; 2332 switch (stringset) { 2333 case ETH_SS_STATS: 2334 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2335 memcpy(data + i * ETH_GSTRING_LEN, 2336 fec_stats[i].name, ETH_GSTRING_LEN); 2337 break; 2338 } 2339 } 2340 2341 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2342 { 2343 switch (sset) { 2344 case ETH_SS_STATS: 2345 return ARRAY_SIZE(fec_stats); 2346 default: 2347 return -EOPNOTSUPP; 2348 } 2349 } 2350 #endif /* !defined(CONFIG_M5272) */ 2351 2352 static int fec_enet_nway_reset(struct net_device *dev) 2353 { 2354 struct phy_device *phydev = dev->phydev; 2355 2356 if (!phydev) 2357 return -ENODEV; 2358 2359 return genphy_restart_aneg(phydev); 2360 } 2361 2362 /* ITR clock source is enet system clock (clk_ahb). 2363 * TCTT unit is cycle_ns * 64 cycle 2364 * So, the ICTT value = X us / (cycle_ns * 64) 2365 */ 2366 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2367 { 2368 struct fec_enet_private *fep = netdev_priv(ndev); 2369 2370 return us * (fep->itr_clk_rate / 64000) / 1000; 2371 } 2372 2373 /* Set threshold for interrupt coalescing */ 2374 static void fec_enet_itr_coal_set(struct net_device *ndev) 2375 { 2376 struct fec_enet_private *fep = netdev_priv(ndev); 2377 int rx_itr, tx_itr; 2378 2379 /* Must be greater than zero to avoid unpredictable behavior */ 2380 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2381 !fep->tx_time_itr || !fep->tx_pkts_itr) 2382 return; 2383 2384 /* Select enet system clock as Interrupt Coalescing 2385 * timer Clock Source 2386 */ 2387 rx_itr = FEC_ITR_CLK_SEL; 2388 tx_itr = FEC_ITR_CLK_SEL; 2389 2390 /* set ICFT and ICTT */ 2391 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2392 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2393 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2394 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2395 2396 rx_itr |= FEC_ITR_EN; 2397 tx_itr |= FEC_ITR_EN; 2398 2399 writel(tx_itr, fep->hwp + FEC_TXIC0); 2400 writel(rx_itr, fep->hwp + FEC_RXIC0); 2401 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 2402 writel(tx_itr, fep->hwp + FEC_TXIC1); 2403 writel(rx_itr, fep->hwp + FEC_RXIC1); 2404 writel(tx_itr, fep->hwp + FEC_TXIC2); 2405 writel(rx_itr, fep->hwp + FEC_RXIC2); 2406 } 2407 } 2408 2409 static int 2410 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2411 { 2412 struct fec_enet_private *fep = netdev_priv(ndev); 2413 2414 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2415 return -EOPNOTSUPP; 2416 2417 ec->rx_coalesce_usecs = fep->rx_time_itr; 2418 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2419 2420 ec->tx_coalesce_usecs = fep->tx_time_itr; 2421 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2422 2423 return 0; 2424 } 2425 2426 static int 2427 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2428 { 2429 struct fec_enet_private *fep = netdev_priv(ndev); 2430 unsigned int cycle; 2431 2432 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2433 return -EOPNOTSUPP; 2434 2435 if (ec->rx_max_coalesced_frames > 255) { 2436 pr_err("Rx coalesced frames exceed hardware limitation\n"); 2437 return -EINVAL; 2438 } 2439 2440 if (ec->tx_max_coalesced_frames > 255) { 2441 pr_err("Tx coalesced frame exceed hardware limitation\n"); 2442 return -EINVAL; 2443 } 2444 2445 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); 2446 if (cycle > 0xFFFF) { 2447 pr_err("Rx coalesced usec exceed hardware limitation\n"); 2448 return -EINVAL; 2449 } 2450 2451 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); 2452 if (cycle > 0xFFFF) { 2453 pr_err("Rx coalesced usec exceed hardware limitation\n"); 2454 return -EINVAL; 2455 } 2456 2457 fep->rx_time_itr = ec->rx_coalesce_usecs; 2458 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2459 2460 fep->tx_time_itr = ec->tx_coalesce_usecs; 2461 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2462 2463 fec_enet_itr_coal_set(ndev); 2464 2465 return 0; 2466 } 2467 2468 static void fec_enet_itr_coal_init(struct net_device *ndev) 2469 { 2470 struct ethtool_coalesce ec; 2471 2472 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2473 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2474 2475 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2476 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2477 2478 fec_enet_set_coalesce(ndev, &ec); 2479 } 2480 2481 static int fec_enet_get_tunable(struct net_device *netdev, 2482 const struct ethtool_tunable *tuna, 2483 void *data) 2484 { 2485 struct fec_enet_private *fep = netdev_priv(netdev); 2486 int ret = 0; 2487 2488 switch (tuna->id) { 2489 case ETHTOOL_RX_COPYBREAK: 2490 *(u32 *)data = fep->rx_copybreak; 2491 break; 2492 default: 2493 ret = -EINVAL; 2494 break; 2495 } 2496 2497 return ret; 2498 } 2499 2500 static int fec_enet_set_tunable(struct net_device *netdev, 2501 const struct ethtool_tunable *tuna, 2502 const void *data) 2503 { 2504 struct fec_enet_private *fep = netdev_priv(netdev); 2505 int ret = 0; 2506 2507 switch (tuna->id) { 2508 case ETHTOOL_RX_COPYBREAK: 2509 fep->rx_copybreak = *(u32 *)data; 2510 break; 2511 default: 2512 ret = -EINVAL; 2513 break; 2514 } 2515 2516 return ret; 2517 } 2518 2519 static void 2520 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2521 { 2522 struct fec_enet_private *fep = netdev_priv(ndev); 2523 2524 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2525 wol->supported = WAKE_MAGIC; 2526 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2527 } else { 2528 wol->supported = wol->wolopts = 0; 2529 } 2530 } 2531 2532 static int 2533 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2534 { 2535 struct fec_enet_private *fep = netdev_priv(ndev); 2536 2537 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2538 return -EINVAL; 2539 2540 if (wol->wolopts & ~WAKE_MAGIC) 2541 return -EINVAL; 2542 2543 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2544 if (device_may_wakeup(&ndev->dev)) { 2545 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2546 if (fep->irq[0] > 0) 2547 enable_irq_wake(fep->irq[0]); 2548 } else { 2549 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2550 if (fep->irq[0] > 0) 2551 disable_irq_wake(fep->irq[0]); 2552 } 2553 2554 return 0; 2555 } 2556 2557 static const struct ethtool_ops fec_enet_ethtool_ops = { 2558 .get_drvinfo = fec_enet_get_drvinfo, 2559 .get_regs_len = fec_enet_get_regs_len, 2560 .get_regs = fec_enet_get_regs, 2561 .nway_reset = fec_enet_nway_reset, 2562 .get_link = ethtool_op_get_link, 2563 .get_coalesce = fec_enet_get_coalesce, 2564 .set_coalesce = fec_enet_set_coalesce, 2565 #ifndef CONFIG_M5272 2566 .get_pauseparam = fec_enet_get_pauseparam, 2567 .set_pauseparam = fec_enet_set_pauseparam, 2568 .get_strings = fec_enet_get_strings, 2569 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2570 .get_sset_count = fec_enet_get_sset_count, 2571 #endif 2572 .get_ts_info = fec_enet_get_ts_info, 2573 .get_tunable = fec_enet_get_tunable, 2574 .set_tunable = fec_enet_set_tunable, 2575 .get_wol = fec_enet_get_wol, 2576 .set_wol = fec_enet_set_wol, 2577 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2578 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2579 }; 2580 2581 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2582 { 2583 struct fec_enet_private *fep = netdev_priv(ndev); 2584 struct phy_device *phydev = ndev->phydev; 2585 2586 if (!netif_running(ndev)) 2587 return -EINVAL; 2588 2589 if (!phydev) 2590 return -ENODEV; 2591 2592 if (fep->bufdesc_ex) { 2593 if (cmd == SIOCSHWTSTAMP) 2594 return fec_ptp_set(ndev, rq); 2595 if (cmd == SIOCGHWTSTAMP) 2596 return fec_ptp_get(ndev, rq); 2597 } 2598 2599 return phy_mii_ioctl(phydev, rq, cmd); 2600 } 2601 2602 static void fec_enet_free_buffers(struct net_device *ndev) 2603 { 2604 struct fec_enet_private *fep = netdev_priv(ndev); 2605 unsigned int i; 2606 struct sk_buff *skb; 2607 struct bufdesc *bdp; 2608 struct fec_enet_priv_tx_q *txq; 2609 struct fec_enet_priv_rx_q *rxq; 2610 unsigned int q; 2611 2612 for (q = 0; q < fep->num_rx_queues; q++) { 2613 rxq = fep->rx_queue[q]; 2614 bdp = rxq->bd.base; 2615 for (i = 0; i < rxq->bd.ring_size; i++) { 2616 skb = rxq->rx_skbuff[i]; 2617 rxq->rx_skbuff[i] = NULL; 2618 if (skb) { 2619 dma_unmap_single(&fep->pdev->dev, 2620 fec32_to_cpu(bdp->cbd_bufaddr), 2621 FEC_ENET_RX_FRSIZE - fep->rx_align, 2622 DMA_FROM_DEVICE); 2623 dev_kfree_skb(skb); 2624 } 2625 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2626 } 2627 } 2628 2629 for (q = 0; q < fep->num_tx_queues; q++) { 2630 txq = fep->tx_queue[q]; 2631 bdp = txq->bd.base; 2632 for (i = 0; i < txq->bd.ring_size; i++) { 2633 kfree(txq->tx_bounce[i]); 2634 txq->tx_bounce[i] = NULL; 2635 skb = txq->tx_skbuff[i]; 2636 txq->tx_skbuff[i] = NULL; 2637 dev_kfree_skb(skb); 2638 } 2639 } 2640 } 2641 2642 static void fec_enet_free_queue(struct net_device *ndev) 2643 { 2644 struct fec_enet_private *fep = netdev_priv(ndev); 2645 int i; 2646 struct fec_enet_priv_tx_q *txq; 2647 2648 for (i = 0; i < fep->num_tx_queues; i++) 2649 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2650 txq = fep->tx_queue[i]; 2651 dma_free_coherent(NULL, 2652 txq->bd.ring_size * TSO_HEADER_SIZE, 2653 txq->tso_hdrs, 2654 txq->tso_hdrs_dma); 2655 } 2656 2657 for (i = 0; i < fep->num_rx_queues; i++) 2658 kfree(fep->rx_queue[i]); 2659 for (i = 0; i < fep->num_tx_queues; i++) 2660 kfree(fep->tx_queue[i]); 2661 } 2662 2663 static int fec_enet_alloc_queue(struct net_device *ndev) 2664 { 2665 struct fec_enet_private *fep = netdev_priv(ndev); 2666 int i; 2667 int ret = 0; 2668 struct fec_enet_priv_tx_q *txq; 2669 2670 for (i = 0; i < fep->num_tx_queues; i++) { 2671 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 2672 if (!txq) { 2673 ret = -ENOMEM; 2674 goto alloc_failed; 2675 } 2676 2677 fep->tx_queue[i] = txq; 2678 txq->bd.ring_size = TX_RING_SIZE; 2679 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 2680 2681 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2682 txq->tx_wake_threshold = 2683 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 2684 2685 txq->tso_hdrs = dma_alloc_coherent(NULL, 2686 txq->bd.ring_size * TSO_HEADER_SIZE, 2687 &txq->tso_hdrs_dma, 2688 GFP_KERNEL); 2689 if (!txq->tso_hdrs) { 2690 ret = -ENOMEM; 2691 goto alloc_failed; 2692 } 2693 } 2694 2695 for (i = 0; i < fep->num_rx_queues; i++) { 2696 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 2697 GFP_KERNEL); 2698 if (!fep->rx_queue[i]) { 2699 ret = -ENOMEM; 2700 goto alloc_failed; 2701 } 2702 2703 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 2704 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 2705 } 2706 return ret; 2707 2708 alloc_failed: 2709 fec_enet_free_queue(ndev); 2710 return ret; 2711 } 2712 2713 static int 2714 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 2715 { 2716 struct fec_enet_private *fep = netdev_priv(ndev); 2717 unsigned int i; 2718 struct sk_buff *skb; 2719 struct bufdesc *bdp; 2720 struct fec_enet_priv_rx_q *rxq; 2721 2722 rxq = fep->rx_queue[queue]; 2723 bdp = rxq->bd.base; 2724 for (i = 0; i < rxq->bd.ring_size; i++) { 2725 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2726 if (!skb) 2727 goto err_alloc; 2728 2729 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 2730 dev_kfree_skb(skb); 2731 goto err_alloc; 2732 } 2733 2734 rxq->rx_skbuff[i] = skb; 2735 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 2736 2737 if (fep->bufdesc_ex) { 2738 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2739 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 2740 } 2741 2742 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2743 } 2744 2745 /* Set the last buffer to wrap. */ 2746 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 2747 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2748 return 0; 2749 2750 err_alloc: 2751 fec_enet_free_buffers(ndev); 2752 return -ENOMEM; 2753 } 2754 2755 static int 2756 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 2757 { 2758 struct fec_enet_private *fep = netdev_priv(ndev); 2759 unsigned int i; 2760 struct bufdesc *bdp; 2761 struct fec_enet_priv_tx_q *txq; 2762 2763 txq = fep->tx_queue[queue]; 2764 bdp = txq->bd.base; 2765 for (i = 0; i < txq->bd.ring_size; i++) { 2766 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2767 if (!txq->tx_bounce[i]) 2768 goto err_alloc; 2769 2770 bdp->cbd_sc = cpu_to_fec16(0); 2771 bdp->cbd_bufaddr = cpu_to_fec32(0); 2772 2773 if (fep->bufdesc_ex) { 2774 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2775 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 2776 } 2777 2778 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 2779 } 2780 2781 /* Set the last buffer to wrap. */ 2782 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 2783 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2784 2785 return 0; 2786 2787 err_alloc: 2788 fec_enet_free_buffers(ndev); 2789 return -ENOMEM; 2790 } 2791 2792 static int fec_enet_alloc_buffers(struct net_device *ndev) 2793 { 2794 struct fec_enet_private *fep = netdev_priv(ndev); 2795 unsigned int i; 2796 2797 for (i = 0; i < fep->num_rx_queues; i++) 2798 if (fec_enet_alloc_rxq_buffers(ndev, i)) 2799 return -ENOMEM; 2800 2801 for (i = 0; i < fep->num_tx_queues; i++) 2802 if (fec_enet_alloc_txq_buffers(ndev, i)) 2803 return -ENOMEM; 2804 return 0; 2805 } 2806 2807 static int 2808 fec_enet_open(struct net_device *ndev) 2809 { 2810 struct fec_enet_private *fep = netdev_priv(ndev); 2811 int ret; 2812 2813 ret = pm_runtime_get_sync(&fep->pdev->dev); 2814 if (ret < 0) 2815 return ret; 2816 2817 pinctrl_pm_select_default_state(&fep->pdev->dev); 2818 ret = fec_enet_clk_enable(ndev, true); 2819 if (ret) 2820 goto clk_enable; 2821 2822 /* I should reset the ring buffers here, but I don't yet know 2823 * a simple way to do that. 2824 */ 2825 2826 ret = fec_enet_alloc_buffers(ndev); 2827 if (ret) 2828 goto err_enet_alloc; 2829 2830 /* Init MAC prior to mii bus probe */ 2831 fec_restart(ndev); 2832 2833 /* Probe and connect to PHY when open the interface */ 2834 ret = fec_enet_mii_probe(ndev); 2835 if (ret) 2836 goto err_enet_mii_probe; 2837 2838 if (fep->quirks & FEC_QUIRK_ERR006687) 2839 imx6q_cpuidle_fec_irqs_used(); 2840 2841 napi_enable(&fep->napi); 2842 phy_start(ndev->phydev); 2843 netif_tx_start_all_queues(ndev); 2844 2845 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 2846 FEC_WOL_FLAG_ENABLE); 2847 2848 return 0; 2849 2850 err_enet_mii_probe: 2851 fec_enet_free_buffers(ndev); 2852 err_enet_alloc: 2853 fec_enet_clk_enable(ndev, false); 2854 clk_enable: 2855 pm_runtime_mark_last_busy(&fep->pdev->dev); 2856 pm_runtime_put_autosuspend(&fep->pdev->dev); 2857 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2858 return ret; 2859 } 2860 2861 static int 2862 fec_enet_close(struct net_device *ndev) 2863 { 2864 struct fec_enet_private *fep = netdev_priv(ndev); 2865 2866 phy_stop(ndev->phydev); 2867 2868 if (netif_device_present(ndev)) { 2869 napi_disable(&fep->napi); 2870 netif_tx_disable(ndev); 2871 fec_stop(ndev); 2872 } 2873 2874 phy_disconnect(ndev->phydev); 2875 2876 if (fep->quirks & FEC_QUIRK_ERR006687) 2877 imx6q_cpuidle_fec_irqs_unused(); 2878 2879 fec_enet_clk_enable(ndev, false); 2880 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2881 pm_runtime_mark_last_busy(&fep->pdev->dev); 2882 pm_runtime_put_autosuspend(&fep->pdev->dev); 2883 2884 fec_enet_free_buffers(ndev); 2885 2886 return 0; 2887 } 2888 2889 /* Set or clear the multicast filter for this adaptor. 2890 * Skeleton taken from sunlance driver. 2891 * The CPM Ethernet implementation allows Multicast as well as individual 2892 * MAC address filtering. Some of the drivers check to make sure it is 2893 * a group multicast address, and discard those that are not. I guess I 2894 * will do the same for now, but just remove the test if you want 2895 * individual filtering as well (do the upper net layers want or support 2896 * this kind of feature?). 2897 */ 2898 2899 #define HASH_BITS 6 /* #bits in hash */ 2900 #define CRC32_POLY 0xEDB88320 2901 2902 static void set_multicast_list(struct net_device *ndev) 2903 { 2904 struct fec_enet_private *fep = netdev_priv(ndev); 2905 struct netdev_hw_addr *ha; 2906 unsigned int i, bit, data, crc, tmp; 2907 unsigned char hash; 2908 2909 if (ndev->flags & IFF_PROMISC) { 2910 tmp = readl(fep->hwp + FEC_R_CNTRL); 2911 tmp |= 0x8; 2912 writel(tmp, fep->hwp + FEC_R_CNTRL); 2913 return; 2914 } 2915 2916 tmp = readl(fep->hwp + FEC_R_CNTRL); 2917 tmp &= ~0x8; 2918 writel(tmp, fep->hwp + FEC_R_CNTRL); 2919 2920 if (ndev->flags & IFF_ALLMULTI) { 2921 /* Catch all multicast addresses, so set the 2922 * filter to all 1's 2923 */ 2924 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2925 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2926 2927 return; 2928 } 2929 2930 /* Clear filter and add the addresses in hash register 2931 */ 2932 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2933 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2934 2935 netdev_for_each_mc_addr(ha, ndev) { 2936 /* calculate crc32 value of mac address */ 2937 crc = 0xffffffff; 2938 2939 for (i = 0; i < ndev->addr_len; i++) { 2940 data = ha->addr[i]; 2941 for (bit = 0; bit < 8; bit++, data >>= 1) { 2942 crc = (crc >> 1) ^ 2943 (((crc ^ data) & 1) ? CRC32_POLY : 0); 2944 } 2945 } 2946 2947 /* only upper 6 bits (HASH_BITS) are used 2948 * which point to specific bit in he hash registers 2949 */ 2950 hash = (crc >> (32 - HASH_BITS)) & 0x3f; 2951 2952 if (hash > 31) { 2953 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2954 tmp |= 1 << (hash - 32); 2955 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2956 } else { 2957 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2958 tmp |= 1 << hash; 2959 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2960 } 2961 } 2962 } 2963 2964 /* Set a MAC change in hardware. */ 2965 static int 2966 fec_set_mac_address(struct net_device *ndev, void *p) 2967 { 2968 struct fec_enet_private *fep = netdev_priv(ndev); 2969 struct sockaddr *addr = p; 2970 2971 if (addr) { 2972 if (!is_valid_ether_addr(addr->sa_data)) 2973 return -EADDRNOTAVAIL; 2974 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 2975 } 2976 2977 /* Add netif status check here to avoid system hang in below case: 2978 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 2979 * After ethx down, fec all clocks are gated off and then register 2980 * access causes system hang. 2981 */ 2982 if (!netif_running(ndev)) 2983 return 0; 2984 2985 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 2986 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 2987 fep->hwp + FEC_ADDR_LOW); 2988 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 2989 fep->hwp + FEC_ADDR_HIGH); 2990 return 0; 2991 } 2992 2993 #ifdef CONFIG_NET_POLL_CONTROLLER 2994 /** 2995 * fec_poll_controller - FEC Poll controller function 2996 * @dev: The FEC network adapter 2997 * 2998 * Polled functionality used by netconsole and others in non interrupt mode 2999 * 3000 */ 3001 static void fec_poll_controller(struct net_device *dev) 3002 { 3003 int i; 3004 struct fec_enet_private *fep = netdev_priv(dev); 3005 3006 for (i = 0; i < FEC_IRQ_NUM; i++) { 3007 if (fep->irq[i] > 0) { 3008 disable_irq(fep->irq[i]); 3009 fec_enet_interrupt(fep->irq[i], dev); 3010 enable_irq(fep->irq[i]); 3011 } 3012 } 3013 } 3014 #endif 3015 3016 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3017 netdev_features_t features) 3018 { 3019 struct fec_enet_private *fep = netdev_priv(netdev); 3020 netdev_features_t changed = features ^ netdev->features; 3021 3022 netdev->features = features; 3023 3024 /* Receive checksum has been changed */ 3025 if (changed & NETIF_F_RXCSUM) { 3026 if (features & NETIF_F_RXCSUM) 3027 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3028 else 3029 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3030 } 3031 } 3032 3033 static int fec_set_features(struct net_device *netdev, 3034 netdev_features_t features) 3035 { 3036 struct fec_enet_private *fep = netdev_priv(netdev); 3037 netdev_features_t changed = features ^ netdev->features; 3038 3039 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3040 napi_disable(&fep->napi); 3041 netif_tx_lock_bh(netdev); 3042 fec_stop(netdev); 3043 fec_enet_set_netdev_features(netdev, features); 3044 fec_restart(netdev); 3045 netif_tx_wake_all_queues(netdev); 3046 netif_tx_unlock_bh(netdev); 3047 napi_enable(&fep->napi); 3048 } else { 3049 fec_enet_set_netdev_features(netdev, features); 3050 } 3051 3052 return 0; 3053 } 3054 3055 static const struct net_device_ops fec_netdev_ops = { 3056 .ndo_open = fec_enet_open, 3057 .ndo_stop = fec_enet_close, 3058 .ndo_start_xmit = fec_enet_start_xmit, 3059 .ndo_set_rx_mode = set_multicast_list, 3060 .ndo_change_mtu = eth_change_mtu, 3061 .ndo_validate_addr = eth_validate_addr, 3062 .ndo_tx_timeout = fec_timeout, 3063 .ndo_set_mac_address = fec_set_mac_address, 3064 .ndo_do_ioctl = fec_enet_ioctl, 3065 #ifdef CONFIG_NET_POLL_CONTROLLER 3066 .ndo_poll_controller = fec_poll_controller, 3067 #endif 3068 .ndo_set_features = fec_set_features, 3069 }; 3070 3071 static const unsigned short offset_des_active_rxq[] = { 3072 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3073 }; 3074 3075 static const unsigned short offset_des_active_txq[] = { 3076 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3077 }; 3078 3079 /* 3080 * XXX: We need to clean up on failure exits here. 3081 * 3082 */ 3083 static int fec_enet_init(struct net_device *ndev) 3084 { 3085 struct fec_enet_private *fep = netdev_priv(ndev); 3086 struct bufdesc *cbd_base; 3087 dma_addr_t bd_dma; 3088 int bd_size; 3089 unsigned int i; 3090 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3091 sizeof(struct bufdesc); 3092 unsigned dsize_log2 = __fls(dsize); 3093 3094 WARN_ON(dsize != (1 << dsize_log2)); 3095 #if defined(CONFIG_ARM) 3096 fep->rx_align = 0xf; 3097 fep->tx_align = 0xf; 3098 #else 3099 fep->rx_align = 0x3; 3100 fep->tx_align = 0x3; 3101 #endif 3102 3103 fec_enet_alloc_queue(ndev); 3104 3105 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3106 3107 /* Allocate memory for buffer descriptors. */ 3108 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3109 GFP_KERNEL); 3110 if (!cbd_base) { 3111 return -ENOMEM; 3112 } 3113 3114 memset(cbd_base, 0, bd_size); 3115 3116 /* Get the Ethernet address */ 3117 fec_get_mac(ndev); 3118 /* make sure MAC we just acquired is programmed into the hw */ 3119 fec_set_mac_address(ndev, NULL); 3120 3121 /* Set receive and transmit descriptor base. */ 3122 for (i = 0; i < fep->num_rx_queues; i++) { 3123 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3124 unsigned size = dsize * rxq->bd.ring_size; 3125 3126 rxq->bd.qid = i; 3127 rxq->bd.base = cbd_base; 3128 rxq->bd.cur = cbd_base; 3129 rxq->bd.dma = bd_dma; 3130 rxq->bd.dsize = dsize; 3131 rxq->bd.dsize_log2 = dsize_log2; 3132 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3133 bd_dma += size; 3134 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3135 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3136 } 3137 3138 for (i = 0; i < fep->num_tx_queues; i++) { 3139 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3140 unsigned size = dsize * txq->bd.ring_size; 3141 3142 txq->bd.qid = i; 3143 txq->bd.base = cbd_base; 3144 txq->bd.cur = cbd_base; 3145 txq->bd.dma = bd_dma; 3146 txq->bd.dsize = dsize; 3147 txq->bd.dsize_log2 = dsize_log2; 3148 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3149 bd_dma += size; 3150 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3151 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3152 } 3153 3154 3155 /* The FEC Ethernet specific entries in the device structure */ 3156 ndev->watchdog_timeo = TX_TIMEOUT; 3157 ndev->netdev_ops = &fec_netdev_ops; 3158 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3159 3160 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3161 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3162 3163 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3164 /* enable hw VLAN support */ 3165 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3166 3167 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3168 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3169 3170 /* enable hw accelerator */ 3171 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3172 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3173 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3174 } 3175 3176 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 3177 fep->tx_align = 0; 3178 fep->rx_align = 0x3f; 3179 } 3180 3181 ndev->hw_features = ndev->features; 3182 3183 fec_restart(ndev); 3184 3185 return 0; 3186 } 3187 3188 #ifdef CONFIG_OF 3189 static void fec_reset_phy(struct platform_device *pdev) 3190 { 3191 int err, phy_reset; 3192 bool active_high = false; 3193 int msec = 1; 3194 struct device_node *np = pdev->dev.of_node; 3195 3196 if (!np) 3197 return; 3198 3199 of_property_read_u32(np, "phy-reset-duration", &msec); 3200 /* A sane reset duration should not be longer than 1s */ 3201 if (msec > 1000) 3202 msec = 1; 3203 3204 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3205 if (!gpio_is_valid(phy_reset)) 3206 return; 3207 3208 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3209 3210 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3211 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3212 "phy-reset"); 3213 if (err) { 3214 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3215 return; 3216 } 3217 3218 if (msec > 20) 3219 msleep(msec); 3220 else 3221 usleep_range(msec * 1000, msec * 1000 + 1000); 3222 3223 gpio_set_value_cansleep(phy_reset, !active_high); 3224 } 3225 #else /* CONFIG_OF */ 3226 static void fec_reset_phy(struct platform_device *pdev) 3227 { 3228 /* 3229 * In case of platform probe, the reset has been done 3230 * by machine code. 3231 */ 3232 } 3233 #endif /* CONFIG_OF */ 3234 3235 static void 3236 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3237 { 3238 struct device_node *np = pdev->dev.of_node; 3239 3240 *num_tx = *num_rx = 1; 3241 3242 if (!np || !of_device_is_available(np)) 3243 return; 3244 3245 /* parse the num of tx and rx queues */ 3246 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3247 3248 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3249 3250 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3251 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3252 *num_tx); 3253 *num_tx = 1; 3254 return; 3255 } 3256 3257 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3258 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3259 *num_rx); 3260 *num_rx = 1; 3261 return; 3262 } 3263 3264 } 3265 3266 static int 3267 fec_probe(struct platform_device *pdev) 3268 { 3269 struct fec_enet_private *fep; 3270 struct fec_platform_data *pdata; 3271 struct net_device *ndev; 3272 int i, irq, ret = 0; 3273 struct resource *r; 3274 const struct of_device_id *of_id; 3275 static int dev_id; 3276 struct device_node *np = pdev->dev.of_node, *phy_node; 3277 int num_tx_qs; 3278 int num_rx_qs; 3279 3280 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3281 3282 /* Init network device */ 3283 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private), 3284 num_tx_qs, num_rx_qs); 3285 if (!ndev) 3286 return -ENOMEM; 3287 3288 SET_NETDEV_DEV(ndev, &pdev->dev); 3289 3290 /* setup board info structure */ 3291 fep = netdev_priv(ndev); 3292 3293 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3294 if (of_id) 3295 pdev->id_entry = of_id->data; 3296 fep->quirks = pdev->id_entry->driver_data; 3297 3298 fep->netdev = ndev; 3299 fep->num_rx_queues = num_rx_qs; 3300 fep->num_tx_queues = num_tx_qs; 3301 3302 #if !defined(CONFIG_M5272) 3303 /* default enable pause frame auto negotiation */ 3304 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3305 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3306 #endif 3307 3308 /* Select default pin state */ 3309 pinctrl_pm_select_default_state(&pdev->dev); 3310 3311 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3312 fep->hwp = devm_ioremap_resource(&pdev->dev, r); 3313 if (IS_ERR(fep->hwp)) { 3314 ret = PTR_ERR(fep->hwp); 3315 goto failed_ioremap; 3316 } 3317 3318 fep->pdev = pdev; 3319 fep->dev_id = dev_id++; 3320 3321 platform_set_drvdata(pdev, ndev); 3322 3323 if ((of_machine_is_compatible("fsl,imx6q") || 3324 of_machine_is_compatible("fsl,imx6dl")) && 3325 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3326 fep->quirks |= FEC_QUIRK_ERR006687; 3327 3328 if (of_get_property(np, "fsl,magic-packet", NULL)) 3329 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3330 3331 phy_node = of_parse_phandle(np, "phy-handle", 0); 3332 if (!phy_node && of_phy_is_fixed_link(np)) { 3333 ret = of_phy_register_fixed_link(np); 3334 if (ret < 0) { 3335 dev_err(&pdev->dev, 3336 "broken fixed-link specification\n"); 3337 goto failed_phy; 3338 } 3339 phy_node = of_node_get(np); 3340 } 3341 fep->phy_node = phy_node; 3342 3343 ret = of_get_phy_mode(pdev->dev.of_node); 3344 if (ret < 0) { 3345 pdata = dev_get_platdata(&pdev->dev); 3346 if (pdata) 3347 fep->phy_interface = pdata->phy; 3348 else 3349 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3350 } else { 3351 fep->phy_interface = ret; 3352 } 3353 3354 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3355 if (IS_ERR(fep->clk_ipg)) { 3356 ret = PTR_ERR(fep->clk_ipg); 3357 goto failed_clk; 3358 } 3359 3360 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3361 if (IS_ERR(fep->clk_ahb)) { 3362 ret = PTR_ERR(fep->clk_ahb); 3363 goto failed_clk; 3364 } 3365 3366 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3367 3368 /* enet_out is optional, depends on board */ 3369 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3370 if (IS_ERR(fep->clk_enet_out)) 3371 fep->clk_enet_out = NULL; 3372 3373 fep->ptp_clk_on = false; 3374 mutex_init(&fep->ptp_clk_mutex); 3375 3376 /* clk_ref is optional, depends on board */ 3377 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3378 if (IS_ERR(fep->clk_ref)) 3379 fep->clk_ref = NULL; 3380 3381 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3382 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3383 if (IS_ERR(fep->clk_ptp)) { 3384 fep->clk_ptp = NULL; 3385 fep->bufdesc_ex = false; 3386 } 3387 3388 ret = fec_enet_clk_enable(ndev, true); 3389 if (ret) 3390 goto failed_clk; 3391 3392 ret = clk_prepare_enable(fep->clk_ipg); 3393 if (ret) 3394 goto failed_clk_ipg; 3395 3396 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); 3397 if (!IS_ERR(fep->reg_phy)) { 3398 ret = regulator_enable(fep->reg_phy); 3399 if (ret) { 3400 dev_err(&pdev->dev, 3401 "Failed to enable phy regulator: %d\n", ret); 3402 goto failed_regulator; 3403 } 3404 } else { 3405 fep->reg_phy = NULL; 3406 } 3407 3408 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3409 pm_runtime_use_autosuspend(&pdev->dev); 3410 pm_runtime_get_noresume(&pdev->dev); 3411 pm_runtime_set_active(&pdev->dev); 3412 pm_runtime_enable(&pdev->dev); 3413 3414 fec_reset_phy(pdev); 3415 3416 if (fep->bufdesc_ex) 3417 fec_ptp_init(pdev); 3418 3419 ret = fec_enet_init(ndev); 3420 if (ret) 3421 goto failed_init; 3422 3423 for (i = 0; i < FEC_IRQ_NUM; i++) { 3424 irq = platform_get_irq(pdev, i); 3425 if (irq < 0) { 3426 if (i) 3427 break; 3428 ret = irq; 3429 goto failed_irq; 3430 } 3431 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3432 0, pdev->name, ndev); 3433 if (ret) 3434 goto failed_irq; 3435 3436 fep->irq[i] = irq; 3437 } 3438 3439 init_completion(&fep->mdio_done); 3440 ret = fec_enet_mii_init(pdev); 3441 if (ret) 3442 goto failed_mii_init; 3443 3444 /* Carrier starts down, phylib will bring it up */ 3445 netif_carrier_off(ndev); 3446 fec_enet_clk_enable(ndev, false); 3447 pinctrl_pm_select_sleep_state(&pdev->dev); 3448 3449 ret = register_netdev(ndev); 3450 if (ret) 3451 goto failed_register; 3452 3453 device_init_wakeup(&ndev->dev, fep->wol_flag & 3454 FEC_WOL_HAS_MAGIC_PACKET); 3455 3456 if (fep->bufdesc_ex && fep->ptp_clock) 3457 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3458 3459 fep->rx_copybreak = COPYBREAK_DEFAULT; 3460 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3461 3462 pm_runtime_mark_last_busy(&pdev->dev); 3463 pm_runtime_put_autosuspend(&pdev->dev); 3464 3465 return 0; 3466 3467 failed_register: 3468 fec_enet_mii_remove(fep); 3469 failed_mii_init: 3470 failed_irq: 3471 failed_init: 3472 fec_ptp_stop(pdev); 3473 if (fep->reg_phy) 3474 regulator_disable(fep->reg_phy); 3475 failed_regulator: 3476 clk_disable_unprepare(fep->clk_ipg); 3477 failed_clk_ipg: 3478 fec_enet_clk_enable(ndev, false); 3479 failed_clk: 3480 failed_phy: 3481 of_node_put(phy_node); 3482 failed_ioremap: 3483 free_netdev(ndev); 3484 3485 return ret; 3486 } 3487 3488 static int 3489 fec_drv_remove(struct platform_device *pdev) 3490 { 3491 struct net_device *ndev = platform_get_drvdata(pdev); 3492 struct fec_enet_private *fep = netdev_priv(ndev); 3493 3494 cancel_work_sync(&fep->tx_timeout_work); 3495 fec_ptp_stop(pdev); 3496 unregister_netdev(ndev); 3497 fec_enet_mii_remove(fep); 3498 if (fep->reg_phy) 3499 regulator_disable(fep->reg_phy); 3500 of_node_put(fep->phy_node); 3501 free_netdev(ndev); 3502 3503 return 0; 3504 } 3505 3506 static int __maybe_unused fec_suspend(struct device *dev) 3507 { 3508 struct net_device *ndev = dev_get_drvdata(dev); 3509 struct fec_enet_private *fep = netdev_priv(ndev); 3510 3511 rtnl_lock(); 3512 if (netif_running(ndev)) { 3513 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 3514 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 3515 phy_stop(ndev->phydev); 3516 napi_disable(&fep->napi); 3517 netif_tx_lock_bh(ndev); 3518 netif_device_detach(ndev); 3519 netif_tx_unlock_bh(ndev); 3520 fec_stop(ndev); 3521 fec_enet_clk_enable(ndev, false); 3522 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3523 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3524 } 3525 rtnl_unlock(); 3526 3527 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3528 regulator_disable(fep->reg_phy); 3529 3530 /* SOC supply clock to phy, when clock is disabled, phy link down 3531 * SOC control phy regulator, when regulator is disabled, phy link down 3532 */ 3533 if (fep->clk_enet_out || fep->reg_phy) 3534 fep->link = 0; 3535 3536 return 0; 3537 } 3538 3539 static int __maybe_unused fec_resume(struct device *dev) 3540 { 3541 struct net_device *ndev = dev_get_drvdata(dev); 3542 struct fec_enet_private *fep = netdev_priv(ndev); 3543 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 3544 int ret; 3545 int val; 3546 3547 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 3548 ret = regulator_enable(fep->reg_phy); 3549 if (ret) 3550 return ret; 3551 } 3552 3553 rtnl_lock(); 3554 if (netif_running(ndev)) { 3555 ret = fec_enet_clk_enable(ndev, true); 3556 if (ret) { 3557 rtnl_unlock(); 3558 goto failed_clk; 3559 } 3560 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 3561 if (pdata && pdata->sleep_mode_enable) 3562 pdata->sleep_mode_enable(false); 3563 val = readl(fep->hwp + FEC_ECNTRL); 3564 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 3565 writel(val, fep->hwp + FEC_ECNTRL); 3566 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 3567 } else { 3568 pinctrl_pm_select_default_state(&fep->pdev->dev); 3569 } 3570 fec_restart(ndev); 3571 netif_tx_lock_bh(ndev); 3572 netif_device_attach(ndev); 3573 netif_tx_unlock_bh(ndev); 3574 napi_enable(&fep->napi); 3575 phy_start(ndev->phydev); 3576 } 3577 rtnl_unlock(); 3578 3579 return 0; 3580 3581 failed_clk: 3582 if (fep->reg_phy) 3583 regulator_disable(fep->reg_phy); 3584 return ret; 3585 } 3586 3587 static int __maybe_unused fec_runtime_suspend(struct device *dev) 3588 { 3589 struct net_device *ndev = dev_get_drvdata(dev); 3590 struct fec_enet_private *fep = netdev_priv(ndev); 3591 3592 clk_disable_unprepare(fep->clk_ipg); 3593 3594 return 0; 3595 } 3596 3597 static int __maybe_unused fec_runtime_resume(struct device *dev) 3598 { 3599 struct net_device *ndev = dev_get_drvdata(dev); 3600 struct fec_enet_private *fep = netdev_priv(ndev); 3601 3602 return clk_prepare_enable(fep->clk_ipg); 3603 } 3604 3605 static const struct dev_pm_ops fec_pm_ops = { 3606 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 3607 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 3608 }; 3609 3610 static struct platform_driver fec_driver = { 3611 .driver = { 3612 .name = DRIVER_NAME, 3613 .pm = &fec_pm_ops, 3614 .of_match_table = fec_dt_ids, 3615 }, 3616 .id_table = fec_devtype, 3617 .probe = fec_probe, 3618 .remove = fec_drv_remove, 3619 }; 3620 3621 module_platform_driver(fec_driver); 3622 3623 MODULE_ALIAS("platform:"DRIVER_NAME); 3624 MODULE_LICENSE("GPL"); 3625