1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/selftests.h> 42 #include <net/tso.h> 43 #include <linux/tcp.h> 44 #include <linux/udp.h> 45 #include <linux/icmp.h> 46 #include <linux/spinlock.h> 47 #include <linux/workqueue.h> 48 #include <linux/bitops.h> 49 #include <linux/io.h> 50 #include <linux/irq.h> 51 #include <linux/clk.h> 52 #include <linux/crc32.h> 53 #include <linux/platform_device.h> 54 #include <linux/mdio.h> 55 #include <linux/phy.h> 56 #include <linux/fec.h> 57 #include <linux/of.h> 58 #include <linux/of_device.h> 59 #include <linux/of_mdio.h> 60 #include <linux/of_net.h> 61 #include <linux/regulator/consumer.h> 62 #include <linux/if_vlan.h> 63 #include <linux/pinctrl/consumer.h> 64 #include <linux/gpio/consumer.h> 65 #include <linux/prefetch.h> 66 #include <linux/mfd/syscon.h> 67 #include <linux/regmap.h> 68 #include <soc/imx/cpuidle.h> 69 #include <linux/filter.h> 70 #include <linux/bpf.h> 71 72 #include <asm/cacheflush.h> 73 74 #include "fec.h" 75 76 static void set_multicast_list(struct net_device *ndev); 77 static void fec_enet_itr_coal_set(struct net_device *ndev); 78 79 #define DRIVER_NAME "fec" 80 81 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 82 83 /* Pause frame feild and FIFO threshold */ 84 #define FEC_ENET_FCE (1 << 5) 85 #define FEC_ENET_RSEM_V 0x84 86 #define FEC_ENET_RSFL_V 16 87 #define FEC_ENET_RAEM_V 0x8 88 #define FEC_ENET_RAFL_V 0x8 89 #define FEC_ENET_OPD_V 0xFFF0 90 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 91 92 #define FEC_ENET_XDP_PASS 0 93 #define FEC_ENET_XDP_CONSUMED BIT(0) 94 #define FEC_ENET_XDP_TX BIT(1) 95 #define FEC_ENET_XDP_REDIR BIT(2) 96 97 struct fec_devinfo { 98 u32 quirks; 99 }; 100 101 static const struct fec_devinfo fec_imx25_info = { 102 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 103 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45, 104 }; 105 106 static const struct fec_devinfo fec_imx27_info = { 107 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG | 108 FEC_QUIRK_HAS_MDIO_C45, 109 }; 110 111 static const struct fec_devinfo fec_imx28_info = { 112 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 113 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 114 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 115 FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45, 116 }; 117 118 static const struct fec_devinfo fec_imx6q_info = { 119 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 120 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 121 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 122 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII | 123 FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45, 124 }; 125 126 static const struct fec_devinfo fec_mvf600_info = { 127 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC | 128 FEC_QUIRK_HAS_MDIO_C45, 129 }; 130 131 static const struct fec_devinfo fec_imx6x_info = { 132 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 133 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 134 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 135 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 136 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 137 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 138 FEC_QUIRK_HAS_MDIO_C45, 139 }; 140 141 static const struct fec_devinfo fec_imx6ul_info = { 142 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 143 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 144 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 145 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 146 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII | 147 FEC_QUIRK_HAS_MDIO_C45, 148 }; 149 150 static const struct fec_devinfo fec_imx8mq_info = { 151 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 152 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 153 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 154 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 155 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 156 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 157 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 | 158 FEC_QUIRK_HAS_MDIO_C45, 159 }; 160 161 static const struct fec_devinfo fec_imx8qm_info = { 162 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 163 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 164 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 165 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 166 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 167 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 168 FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45, 169 }; 170 171 static const struct fec_devinfo fec_s32v234_info = { 172 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 173 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 174 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 175 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 176 FEC_QUIRK_HAS_MDIO_C45, 177 }; 178 179 static struct platform_device_id fec_devtype[] = { 180 { 181 /* keep it for coldfire */ 182 .name = DRIVER_NAME, 183 .driver_data = 0, 184 }, { 185 .name = "imx25-fec", 186 .driver_data = (kernel_ulong_t)&fec_imx25_info, 187 }, { 188 .name = "imx27-fec", 189 .driver_data = (kernel_ulong_t)&fec_imx27_info, 190 }, { 191 .name = "imx28-fec", 192 .driver_data = (kernel_ulong_t)&fec_imx28_info, 193 }, { 194 .name = "imx6q-fec", 195 .driver_data = (kernel_ulong_t)&fec_imx6q_info, 196 }, { 197 .name = "mvf600-fec", 198 .driver_data = (kernel_ulong_t)&fec_mvf600_info, 199 }, { 200 .name = "imx6sx-fec", 201 .driver_data = (kernel_ulong_t)&fec_imx6x_info, 202 }, { 203 .name = "imx6ul-fec", 204 .driver_data = (kernel_ulong_t)&fec_imx6ul_info, 205 }, { 206 .name = "imx8mq-fec", 207 .driver_data = (kernel_ulong_t)&fec_imx8mq_info, 208 }, { 209 .name = "imx8qm-fec", 210 .driver_data = (kernel_ulong_t)&fec_imx8qm_info, 211 }, { 212 .name = "s32v234-fec", 213 .driver_data = (kernel_ulong_t)&fec_s32v234_info, 214 }, { 215 /* sentinel */ 216 } 217 }; 218 MODULE_DEVICE_TABLE(platform, fec_devtype); 219 220 enum imx_fec_type { 221 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 222 IMX27_FEC, /* runs on i.mx27/35/51 */ 223 IMX28_FEC, 224 IMX6Q_FEC, 225 MVF600_FEC, 226 IMX6SX_FEC, 227 IMX6UL_FEC, 228 IMX8MQ_FEC, 229 IMX8QM_FEC, 230 S32V234_FEC, 231 }; 232 233 static const struct of_device_id fec_dt_ids[] = { 234 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 235 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 236 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 237 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 238 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 239 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 240 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 241 { .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], }, 242 { .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], }, 243 { .compatible = "fsl,s32v234-fec", .data = &fec_devtype[S32V234_FEC], }, 244 { /* sentinel */ } 245 }; 246 MODULE_DEVICE_TABLE(of, fec_dt_ids); 247 248 static unsigned char macaddr[ETH_ALEN]; 249 module_param_array(macaddr, byte, NULL, 0); 250 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 251 252 #if defined(CONFIG_M5272) 253 /* 254 * Some hardware gets it MAC address out of local flash memory. 255 * if this is non-zero then assume it is the address to get MAC from. 256 */ 257 #if defined(CONFIG_NETtel) 258 #define FEC_FLASHMAC 0xf0006006 259 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 260 #define FEC_FLASHMAC 0xf0006000 261 #elif defined(CONFIG_CANCam) 262 #define FEC_FLASHMAC 0xf0020000 263 #elif defined (CONFIG_M5272C3) 264 #define FEC_FLASHMAC (0xffe04000 + 4) 265 #elif defined(CONFIG_MOD5272) 266 #define FEC_FLASHMAC 0xffc0406b 267 #else 268 #define FEC_FLASHMAC 0 269 #endif 270 #endif /* CONFIG_M5272 */ 271 272 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 273 * 274 * 2048 byte skbufs are allocated. However, alignment requirements 275 * varies between FEC variants. Worst case is 64, so round down by 64. 276 */ 277 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 278 #define PKT_MINBUF_SIZE 64 279 280 /* FEC receive acceleration */ 281 #define FEC_RACC_IPDIS (1 << 1) 282 #define FEC_RACC_PRODIS (1 << 2) 283 #define FEC_RACC_SHIFT16 BIT(7) 284 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 285 286 /* MIB Control Register */ 287 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 288 289 /* 290 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 291 * size bits. Other FEC hardware does not, so we need to take that into 292 * account when setting it. 293 */ 294 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 295 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 296 defined(CONFIG_ARM64) 297 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 298 #else 299 #define OPT_FRAME_SIZE 0 300 #endif 301 302 /* FEC MII MMFR bits definition */ 303 #define FEC_MMFR_ST (1 << 30) 304 #define FEC_MMFR_ST_C45 (0) 305 #define FEC_MMFR_OP_READ (2 << 28) 306 #define FEC_MMFR_OP_READ_C45 (3 << 28) 307 #define FEC_MMFR_OP_WRITE (1 << 28) 308 #define FEC_MMFR_OP_ADDR_WRITE (0) 309 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 310 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 311 #define FEC_MMFR_TA (2 << 16) 312 #define FEC_MMFR_DATA(v) (v & 0xffff) 313 /* FEC ECR bits definition */ 314 #define FEC_ECR_MAGICEN (1 << 2) 315 #define FEC_ECR_SLEEP (1 << 3) 316 317 #define FEC_MII_TIMEOUT 30000 /* us */ 318 319 /* Transmitter timeout */ 320 #define TX_TIMEOUT (2 * HZ) 321 322 #define FEC_PAUSE_FLAG_AUTONEG 0x1 323 #define FEC_PAUSE_FLAG_ENABLE 0x2 324 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 325 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 326 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 327 328 /* Max number of allowed TCP segments for software TSO */ 329 #define FEC_MAX_TSO_SEGS 100 330 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 331 332 #define IS_TSO_HEADER(txq, addr) \ 333 ((addr >= txq->tso_hdrs_dma) && \ 334 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 335 336 static int mii_cnt; 337 338 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 339 struct bufdesc_prop *bd) 340 { 341 return (bdp >= bd->last) ? bd->base 342 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 343 } 344 345 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 346 struct bufdesc_prop *bd) 347 { 348 return (bdp <= bd->base) ? bd->last 349 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 350 } 351 352 static int fec_enet_get_bd_index(struct bufdesc *bdp, 353 struct bufdesc_prop *bd) 354 { 355 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 356 } 357 358 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 359 { 360 int entries; 361 362 entries = (((const char *)txq->dirty_tx - 363 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 364 365 return entries >= 0 ? entries : entries + txq->bd.ring_size; 366 } 367 368 static void swap_buffer(void *bufaddr, int len) 369 { 370 int i; 371 unsigned int *buf = bufaddr; 372 373 for (i = 0; i < len; i += 4, buf++) 374 swab32s(buf); 375 } 376 377 static void fec_dump(struct net_device *ndev) 378 { 379 struct fec_enet_private *fep = netdev_priv(ndev); 380 struct bufdesc *bdp; 381 struct fec_enet_priv_tx_q *txq; 382 int index = 0; 383 384 netdev_info(ndev, "TX ring dump\n"); 385 pr_info("Nr SC addr len SKB\n"); 386 387 txq = fep->tx_queue[0]; 388 bdp = txq->bd.base; 389 390 do { 391 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 392 index, 393 bdp == txq->bd.cur ? 'S' : ' ', 394 bdp == txq->dirty_tx ? 'H' : ' ', 395 fec16_to_cpu(bdp->cbd_sc), 396 fec32_to_cpu(bdp->cbd_bufaddr), 397 fec16_to_cpu(bdp->cbd_datlen), 398 txq->tx_buf[index].skb); 399 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 400 index++; 401 } while (bdp != txq->bd.base); 402 } 403 404 static inline bool is_ipv4_pkt(struct sk_buff *skb) 405 { 406 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 407 } 408 409 static int 410 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 411 { 412 /* Only run for packets requiring a checksum. */ 413 if (skb->ip_summed != CHECKSUM_PARTIAL) 414 return 0; 415 416 if (unlikely(skb_cow_head(skb, 0))) 417 return -1; 418 419 if (is_ipv4_pkt(skb)) 420 ip_hdr(skb)->check = 0; 421 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 422 423 return 0; 424 } 425 426 static int 427 fec_enet_create_page_pool(struct fec_enet_private *fep, 428 struct fec_enet_priv_rx_q *rxq, int size) 429 { 430 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 431 struct page_pool_params pp_params = { 432 .order = 0, 433 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 434 .pool_size = size, 435 .nid = dev_to_node(&fep->pdev->dev), 436 .dev = &fep->pdev->dev, 437 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 438 .offset = FEC_ENET_XDP_HEADROOM, 439 .max_len = FEC_ENET_RX_FRSIZE, 440 }; 441 int err; 442 443 rxq->page_pool = page_pool_create(&pp_params); 444 if (IS_ERR(rxq->page_pool)) { 445 err = PTR_ERR(rxq->page_pool); 446 rxq->page_pool = NULL; 447 return err; 448 } 449 450 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0); 451 if (err < 0) 452 goto err_free_pp; 453 454 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 455 rxq->page_pool); 456 if (err) 457 goto err_unregister_rxq; 458 459 return 0; 460 461 err_unregister_rxq: 462 xdp_rxq_info_unreg(&rxq->xdp_rxq); 463 err_free_pp: 464 page_pool_destroy(rxq->page_pool); 465 rxq->page_pool = NULL; 466 return err; 467 } 468 469 static struct bufdesc * 470 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 471 struct sk_buff *skb, 472 struct net_device *ndev) 473 { 474 struct fec_enet_private *fep = netdev_priv(ndev); 475 struct bufdesc *bdp = txq->bd.cur; 476 struct bufdesc_ex *ebdp; 477 int nr_frags = skb_shinfo(skb)->nr_frags; 478 int frag, frag_len; 479 unsigned short status; 480 unsigned int estatus = 0; 481 skb_frag_t *this_frag; 482 unsigned int index; 483 void *bufaddr; 484 dma_addr_t addr; 485 int i; 486 487 for (frag = 0; frag < nr_frags; frag++) { 488 this_frag = &skb_shinfo(skb)->frags[frag]; 489 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 490 ebdp = (struct bufdesc_ex *)bdp; 491 492 status = fec16_to_cpu(bdp->cbd_sc); 493 status &= ~BD_ENET_TX_STATS; 494 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 495 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 496 497 /* Handle the last BD specially */ 498 if (frag == nr_frags - 1) { 499 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 500 if (fep->bufdesc_ex) { 501 estatus |= BD_ENET_TX_INT; 502 if (unlikely(skb_shinfo(skb)->tx_flags & 503 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 504 estatus |= BD_ENET_TX_TS; 505 } 506 } 507 508 if (fep->bufdesc_ex) { 509 if (fep->quirks & FEC_QUIRK_HAS_AVB) 510 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 511 if (skb->ip_summed == CHECKSUM_PARTIAL) 512 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 513 514 ebdp->cbd_bdu = 0; 515 ebdp->cbd_esc = cpu_to_fec32(estatus); 516 } 517 518 bufaddr = skb_frag_address(this_frag); 519 520 index = fec_enet_get_bd_index(bdp, &txq->bd); 521 if (((unsigned long) bufaddr) & fep->tx_align || 522 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 523 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 524 bufaddr = txq->tx_bounce[index]; 525 526 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 527 swap_buffer(bufaddr, frag_len); 528 } 529 530 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 531 DMA_TO_DEVICE); 532 if (dma_mapping_error(&fep->pdev->dev, addr)) { 533 if (net_ratelimit()) 534 netdev_err(ndev, "Tx DMA memory map failed\n"); 535 goto dma_mapping_error; 536 } 537 538 bdp->cbd_bufaddr = cpu_to_fec32(addr); 539 bdp->cbd_datlen = cpu_to_fec16(frag_len); 540 /* Make sure the updates to rest of the descriptor are 541 * performed before transferring ownership. 542 */ 543 wmb(); 544 bdp->cbd_sc = cpu_to_fec16(status); 545 } 546 547 return bdp; 548 dma_mapping_error: 549 bdp = txq->bd.cur; 550 for (i = 0; i < frag; i++) { 551 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 552 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 553 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 554 } 555 return ERR_PTR(-ENOMEM); 556 } 557 558 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 559 struct sk_buff *skb, struct net_device *ndev) 560 { 561 struct fec_enet_private *fep = netdev_priv(ndev); 562 int nr_frags = skb_shinfo(skb)->nr_frags; 563 struct bufdesc *bdp, *last_bdp; 564 void *bufaddr; 565 dma_addr_t addr; 566 unsigned short status; 567 unsigned short buflen; 568 unsigned int estatus = 0; 569 unsigned int index; 570 int entries_free; 571 572 entries_free = fec_enet_get_free_txdesc_num(txq); 573 if (entries_free < MAX_SKB_FRAGS + 1) { 574 dev_kfree_skb_any(skb); 575 if (net_ratelimit()) 576 netdev_err(ndev, "NOT enough BD for SG!\n"); 577 return NETDEV_TX_OK; 578 } 579 580 /* Protocol checksum off-load for TCP and UDP. */ 581 if (fec_enet_clear_csum(skb, ndev)) { 582 dev_kfree_skb_any(skb); 583 return NETDEV_TX_OK; 584 } 585 586 /* Fill in a Tx ring entry */ 587 bdp = txq->bd.cur; 588 last_bdp = bdp; 589 status = fec16_to_cpu(bdp->cbd_sc); 590 status &= ~BD_ENET_TX_STATS; 591 592 /* Set buffer length and buffer pointer */ 593 bufaddr = skb->data; 594 buflen = skb_headlen(skb); 595 596 index = fec_enet_get_bd_index(bdp, &txq->bd); 597 if (((unsigned long) bufaddr) & fep->tx_align || 598 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 599 memcpy(txq->tx_bounce[index], skb->data, buflen); 600 bufaddr = txq->tx_bounce[index]; 601 602 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 603 swap_buffer(bufaddr, buflen); 604 } 605 606 /* Push the data cache so the CPM does not get stale memory data. */ 607 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 608 if (dma_mapping_error(&fep->pdev->dev, addr)) { 609 dev_kfree_skb_any(skb); 610 if (net_ratelimit()) 611 netdev_err(ndev, "Tx DMA memory map failed\n"); 612 return NETDEV_TX_OK; 613 } 614 615 if (nr_frags) { 616 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 617 if (IS_ERR(last_bdp)) { 618 dma_unmap_single(&fep->pdev->dev, addr, 619 buflen, DMA_TO_DEVICE); 620 dev_kfree_skb_any(skb); 621 return NETDEV_TX_OK; 622 } 623 } else { 624 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 625 if (fep->bufdesc_ex) { 626 estatus = BD_ENET_TX_INT; 627 if (unlikely(skb_shinfo(skb)->tx_flags & 628 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 629 estatus |= BD_ENET_TX_TS; 630 } 631 } 632 bdp->cbd_bufaddr = cpu_to_fec32(addr); 633 bdp->cbd_datlen = cpu_to_fec16(buflen); 634 635 if (fep->bufdesc_ex) { 636 637 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 638 639 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 640 fep->hwts_tx_en)) 641 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 642 643 if (fep->quirks & FEC_QUIRK_HAS_AVB) 644 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 645 646 if (skb->ip_summed == CHECKSUM_PARTIAL) 647 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 648 649 ebdp->cbd_bdu = 0; 650 ebdp->cbd_esc = cpu_to_fec32(estatus); 651 } 652 653 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 654 /* Save skb pointer */ 655 txq->tx_buf[index].skb = skb; 656 657 /* Make sure the updates to rest of the descriptor are performed before 658 * transferring ownership. 659 */ 660 wmb(); 661 662 /* Send it on its way. Tell FEC it's ready, interrupt when done, 663 * it's the last BD of the frame, and to put the CRC on the end. 664 */ 665 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 666 bdp->cbd_sc = cpu_to_fec16(status); 667 668 /* If this was the last BD in the ring, start at the beginning again. */ 669 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 670 671 skb_tx_timestamp(skb); 672 673 /* Make sure the update to bdp is performed before txq->bd.cur. */ 674 wmb(); 675 txq->bd.cur = bdp; 676 677 /* Trigger transmission start */ 678 writel(0, txq->bd.reg_desc_active); 679 680 return 0; 681 } 682 683 static int 684 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 685 struct net_device *ndev, 686 struct bufdesc *bdp, int index, char *data, 687 int size, bool last_tcp, bool is_last) 688 { 689 struct fec_enet_private *fep = netdev_priv(ndev); 690 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 691 unsigned short status; 692 unsigned int estatus = 0; 693 dma_addr_t addr; 694 695 status = fec16_to_cpu(bdp->cbd_sc); 696 status &= ~BD_ENET_TX_STATS; 697 698 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 699 700 if (((unsigned long) data) & fep->tx_align || 701 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 702 memcpy(txq->tx_bounce[index], data, size); 703 data = txq->tx_bounce[index]; 704 705 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 706 swap_buffer(data, size); 707 } 708 709 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 710 if (dma_mapping_error(&fep->pdev->dev, addr)) { 711 dev_kfree_skb_any(skb); 712 if (net_ratelimit()) 713 netdev_err(ndev, "Tx DMA memory map failed\n"); 714 return NETDEV_TX_OK; 715 } 716 717 bdp->cbd_datlen = cpu_to_fec16(size); 718 bdp->cbd_bufaddr = cpu_to_fec32(addr); 719 720 if (fep->bufdesc_ex) { 721 if (fep->quirks & FEC_QUIRK_HAS_AVB) 722 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 723 if (skb->ip_summed == CHECKSUM_PARTIAL) 724 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 725 ebdp->cbd_bdu = 0; 726 ebdp->cbd_esc = cpu_to_fec32(estatus); 727 } 728 729 /* Handle the last BD specially */ 730 if (last_tcp) 731 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 732 if (is_last) { 733 status |= BD_ENET_TX_INTR; 734 if (fep->bufdesc_ex) 735 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 736 } 737 738 bdp->cbd_sc = cpu_to_fec16(status); 739 740 return 0; 741 } 742 743 static int 744 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 745 struct sk_buff *skb, struct net_device *ndev, 746 struct bufdesc *bdp, int index) 747 { 748 struct fec_enet_private *fep = netdev_priv(ndev); 749 int hdr_len = skb_tcp_all_headers(skb); 750 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 751 void *bufaddr; 752 unsigned long dmabuf; 753 unsigned short status; 754 unsigned int estatus = 0; 755 756 status = fec16_to_cpu(bdp->cbd_sc); 757 status &= ~BD_ENET_TX_STATS; 758 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 759 760 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 761 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 762 if (((unsigned long)bufaddr) & fep->tx_align || 763 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 764 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 765 bufaddr = txq->tx_bounce[index]; 766 767 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 768 swap_buffer(bufaddr, hdr_len); 769 770 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 771 hdr_len, DMA_TO_DEVICE); 772 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 773 dev_kfree_skb_any(skb); 774 if (net_ratelimit()) 775 netdev_err(ndev, "Tx DMA memory map failed\n"); 776 return NETDEV_TX_OK; 777 } 778 } 779 780 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 781 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 782 783 if (fep->bufdesc_ex) { 784 if (fep->quirks & FEC_QUIRK_HAS_AVB) 785 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 786 if (skb->ip_summed == CHECKSUM_PARTIAL) 787 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 788 ebdp->cbd_bdu = 0; 789 ebdp->cbd_esc = cpu_to_fec32(estatus); 790 } 791 792 bdp->cbd_sc = cpu_to_fec16(status); 793 794 return 0; 795 } 796 797 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 798 struct sk_buff *skb, 799 struct net_device *ndev) 800 { 801 struct fec_enet_private *fep = netdev_priv(ndev); 802 int hdr_len, total_len, data_left; 803 struct bufdesc *bdp = txq->bd.cur; 804 struct tso_t tso; 805 unsigned int index = 0; 806 int ret; 807 808 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 809 dev_kfree_skb_any(skb); 810 if (net_ratelimit()) 811 netdev_err(ndev, "NOT enough BD for TSO!\n"); 812 return NETDEV_TX_OK; 813 } 814 815 /* Protocol checksum off-load for TCP and UDP. */ 816 if (fec_enet_clear_csum(skb, ndev)) { 817 dev_kfree_skb_any(skb); 818 return NETDEV_TX_OK; 819 } 820 821 /* Initialize the TSO handler, and prepare the first payload */ 822 hdr_len = tso_start(skb, &tso); 823 824 total_len = skb->len - hdr_len; 825 while (total_len > 0) { 826 char *hdr; 827 828 index = fec_enet_get_bd_index(bdp, &txq->bd); 829 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 830 total_len -= data_left; 831 832 /* prepare packet headers: MAC + IP + TCP */ 833 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 834 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 835 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 836 if (ret) 837 goto err_release; 838 839 while (data_left > 0) { 840 int size; 841 842 size = min_t(int, tso.size, data_left); 843 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 844 index = fec_enet_get_bd_index(bdp, &txq->bd); 845 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 846 bdp, index, 847 tso.data, size, 848 size == data_left, 849 total_len == 0); 850 if (ret) 851 goto err_release; 852 853 data_left -= size; 854 tso_build_data(skb, &tso, size); 855 } 856 857 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 858 } 859 860 /* Save skb pointer */ 861 txq->tx_buf[index].skb = skb; 862 863 skb_tx_timestamp(skb); 864 txq->bd.cur = bdp; 865 866 /* Trigger transmission start */ 867 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 868 !readl(txq->bd.reg_desc_active) || 869 !readl(txq->bd.reg_desc_active) || 870 !readl(txq->bd.reg_desc_active) || 871 !readl(txq->bd.reg_desc_active)) 872 writel(0, txq->bd.reg_desc_active); 873 874 return 0; 875 876 err_release: 877 /* TODO: Release all used data descriptors for TSO */ 878 return ret; 879 } 880 881 static netdev_tx_t 882 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 883 { 884 struct fec_enet_private *fep = netdev_priv(ndev); 885 int entries_free; 886 unsigned short queue; 887 struct fec_enet_priv_tx_q *txq; 888 struct netdev_queue *nq; 889 int ret; 890 891 queue = skb_get_queue_mapping(skb); 892 txq = fep->tx_queue[queue]; 893 nq = netdev_get_tx_queue(ndev, queue); 894 895 if (skb_is_gso(skb)) 896 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 897 else 898 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 899 if (ret) 900 return ret; 901 902 entries_free = fec_enet_get_free_txdesc_num(txq); 903 if (entries_free <= txq->tx_stop_threshold) 904 netif_tx_stop_queue(nq); 905 906 return NETDEV_TX_OK; 907 } 908 909 /* Init RX & TX buffer descriptors 910 */ 911 static void fec_enet_bd_init(struct net_device *dev) 912 { 913 struct fec_enet_private *fep = netdev_priv(dev); 914 struct fec_enet_priv_tx_q *txq; 915 struct fec_enet_priv_rx_q *rxq; 916 struct bufdesc *bdp; 917 unsigned int i; 918 unsigned int q; 919 920 for (q = 0; q < fep->num_rx_queues; q++) { 921 /* Initialize the receive buffer descriptors. */ 922 rxq = fep->rx_queue[q]; 923 bdp = rxq->bd.base; 924 925 for (i = 0; i < rxq->bd.ring_size; i++) { 926 927 /* Initialize the BD for every fragment in the page. */ 928 if (bdp->cbd_bufaddr) 929 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 930 else 931 bdp->cbd_sc = cpu_to_fec16(0); 932 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 933 } 934 935 /* Set the last buffer to wrap */ 936 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 937 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 938 939 rxq->bd.cur = rxq->bd.base; 940 } 941 942 for (q = 0; q < fep->num_tx_queues; q++) { 943 /* ...and the same for transmit */ 944 txq = fep->tx_queue[q]; 945 bdp = txq->bd.base; 946 txq->bd.cur = bdp; 947 948 for (i = 0; i < txq->bd.ring_size; i++) { 949 /* Initialize the BD for every fragment in the page. */ 950 bdp->cbd_sc = cpu_to_fec16(0); 951 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 952 if (bdp->cbd_bufaddr && 953 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 954 dma_unmap_single(&fep->pdev->dev, 955 fec32_to_cpu(bdp->cbd_bufaddr), 956 fec16_to_cpu(bdp->cbd_datlen), 957 DMA_TO_DEVICE); 958 if (txq->tx_buf[i].skb) { 959 dev_kfree_skb_any(txq->tx_buf[i].skb); 960 txq->tx_buf[i].skb = NULL; 961 } 962 } else { 963 if (bdp->cbd_bufaddr) 964 dma_unmap_single(&fep->pdev->dev, 965 fec32_to_cpu(bdp->cbd_bufaddr), 966 fec16_to_cpu(bdp->cbd_datlen), 967 DMA_TO_DEVICE); 968 969 if (txq->tx_buf[i].xdp) { 970 xdp_return_frame(txq->tx_buf[i].xdp); 971 txq->tx_buf[i].xdp = NULL; 972 } 973 974 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 975 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 976 } 977 978 bdp->cbd_bufaddr = cpu_to_fec32(0); 979 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 980 } 981 982 /* Set the last buffer to wrap */ 983 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 984 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 985 txq->dirty_tx = bdp; 986 } 987 } 988 989 static void fec_enet_active_rxring(struct net_device *ndev) 990 { 991 struct fec_enet_private *fep = netdev_priv(ndev); 992 int i; 993 994 for (i = 0; i < fep->num_rx_queues; i++) 995 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 996 } 997 998 static void fec_enet_enable_ring(struct net_device *ndev) 999 { 1000 struct fec_enet_private *fep = netdev_priv(ndev); 1001 struct fec_enet_priv_tx_q *txq; 1002 struct fec_enet_priv_rx_q *rxq; 1003 int i; 1004 1005 for (i = 0; i < fep->num_rx_queues; i++) { 1006 rxq = fep->rx_queue[i]; 1007 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 1008 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 1009 1010 /* enable DMA1/2 */ 1011 if (i) 1012 writel(RCMR_MATCHEN | RCMR_CMP(i), 1013 fep->hwp + FEC_RCMR(i)); 1014 } 1015 1016 for (i = 0; i < fep->num_tx_queues; i++) { 1017 txq = fep->tx_queue[i]; 1018 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 1019 1020 /* enable DMA1/2 */ 1021 if (i) 1022 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 1023 fep->hwp + FEC_DMA_CFG(i)); 1024 } 1025 } 1026 1027 /* 1028 * This function is called to start or restart the FEC during a link 1029 * change, transmit timeout, or to reconfigure the FEC. The network 1030 * packet processing for this device must be stopped before this call. 1031 */ 1032 static void 1033 fec_restart(struct net_device *ndev) 1034 { 1035 struct fec_enet_private *fep = netdev_priv(ndev); 1036 u32 temp_mac[2]; 1037 u32 rcntl = OPT_FRAME_SIZE | 0x04; 1038 u32 ecntl = 0x2; /* ETHEREN */ 1039 1040 /* Whack a reset. We should wait for this. 1041 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1042 * instead of reset MAC itself. 1043 */ 1044 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 1045 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 1046 writel(0, fep->hwp + FEC_ECNTRL); 1047 } else { 1048 writel(1, fep->hwp + FEC_ECNTRL); 1049 udelay(10); 1050 } 1051 1052 /* 1053 * enet-mac reset will reset mac address registers too, 1054 * so need to reconfigure it. 1055 */ 1056 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 1057 writel((__force u32)cpu_to_be32(temp_mac[0]), 1058 fep->hwp + FEC_ADDR_LOW); 1059 writel((__force u32)cpu_to_be32(temp_mac[1]), 1060 fep->hwp + FEC_ADDR_HIGH); 1061 1062 /* Clear any outstanding interrupt, except MDIO. */ 1063 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1064 1065 fec_enet_bd_init(ndev); 1066 1067 fec_enet_enable_ring(ndev); 1068 1069 /* Enable MII mode */ 1070 if (fep->full_duplex == DUPLEX_FULL) { 1071 /* FD enable */ 1072 writel(0x04, fep->hwp + FEC_X_CNTRL); 1073 } else { 1074 /* No Rcv on Xmit */ 1075 rcntl |= 0x02; 1076 writel(0x0, fep->hwp + FEC_X_CNTRL); 1077 } 1078 1079 /* Set MII speed */ 1080 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1081 1082 #if !defined(CONFIG_M5272) 1083 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1084 u32 val = readl(fep->hwp + FEC_RACC); 1085 1086 /* align IP header */ 1087 val |= FEC_RACC_SHIFT16; 1088 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1089 /* set RX checksum */ 1090 val |= FEC_RACC_OPTIONS; 1091 else 1092 val &= ~FEC_RACC_OPTIONS; 1093 writel(val, fep->hwp + FEC_RACC); 1094 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1095 } 1096 #endif 1097 1098 /* 1099 * The phy interface and speed need to get configured 1100 * differently on enet-mac. 1101 */ 1102 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1103 /* Enable flow control and length check */ 1104 rcntl |= 0x40000000 | 0x00000020; 1105 1106 /* RGMII, RMII or MII */ 1107 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1108 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1109 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1110 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1111 rcntl |= (1 << 6); 1112 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1113 rcntl |= (1 << 8); 1114 else 1115 rcntl &= ~(1 << 8); 1116 1117 /* 1G, 100M or 10M */ 1118 if (ndev->phydev) { 1119 if (ndev->phydev->speed == SPEED_1000) 1120 ecntl |= (1 << 5); 1121 else if (ndev->phydev->speed == SPEED_100) 1122 rcntl &= ~(1 << 9); 1123 else 1124 rcntl |= (1 << 9); 1125 } 1126 } else { 1127 #ifdef FEC_MIIGSK_ENR 1128 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1129 u32 cfgr; 1130 /* disable the gasket and wait */ 1131 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1132 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1133 udelay(1); 1134 1135 /* 1136 * configure the gasket: 1137 * RMII, 50 MHz, no loopback, no echo 1138 * MII, 25 MHz, no loopback, no echo 1139 */ 1140 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1141 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1142 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1143 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1144 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1145 1146 /* re-enable the gasket */ 1147 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1148 } 1149 #endif 1150 } 1151 1152 #if !defined(CONFIG_M5272) 1153 /* enable pause frame*/ 1154 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1155 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1156 ndev->phydev && ndev->phydev->pause)) { 1157 rcntl |= FEC_ENET_FCE; 1158 1159 /* set FIFO threshold parameter to reduce overrun */ 1160 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1161 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1162 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1163 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1164 1165 /* OPD */ 1166 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1167 } else { 1168 rcntl &= ~FEC_ENET_FCE; 1169 } 1170 #endif /* !defined(CONFIG_M5272) */ 1171 1172 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1173 1174 /* Setup multicast filter. */ 1175 set_multicast_list(ndev); 1176 #ifndef CONFIG_M5272 1177 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1178 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1179 #endif 1180 1181 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1182 /* enable ENET endian swap */ 1183 ecntl |= (1 << 8); 1184 /* enable ENET store and forward mode */ 1185 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1186 } 1187 1188 if (fep->bufdesc_ex) 1189 ecntl |= (1 << 4); 1190 1191 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1192 fep->rgmii_txc_dly) 1193 ecntl |= FEC_ENET_TXC_DLY; 1194 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1195 fep->rgmii_rxc_dly) 1196 ecntl |= FEC_ENET_RXC_DLY; 1197 1198 #ifndef CONFIG_M5272 1199 /* Enable the MIB statistic event counters */ 1200 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1201 #endif 1202 1203 /* And last, enable the transmit and receive processing */ 1204 writel(ecntl, fep->hwp + FEC_ECNTRL); 1205 fec_enet_active_rxring(ndev); 1206 1207 if (fep->bufdesc_ex) 1208 fec_ptp_start_cyclecounter(ndev); 1209 1210 /* Enable interrupts we wish to service */ 1211 if (fep->link) 1212 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1213 else 1214 writel(0, fep->hwp + FEC_IMASK); 1215 1216 /* Init the interrupt coalescing */ 1217 if (fep->quirks & FEC_QUIRK_HAS_COALESCE) 1218 fec_enet_itr_coal_set(ndev); 1219 } 1220 1221 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep) 1222 { 1223 if (!(of_machine_is_compatible("fsl,imx8qm") || 1224 of_machine_is_compatible("fsl,imx8qxp") || 1225 of_machine_is_compatible("fsl,imx8dxl"))) 1226 return 0; 1227 1228 return imx_scu_get_handle(&fep->ipc_handle); 1229 } 1230 1231 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled) 1232 { 1233 struct device_node *np = fep->pdev->dev.of_node; 1234 u32 rsrc_id, val; 1235 int idx; 1236 1237 if (!np || !fep->ipc_handle) 1238 return; 1239 1240 idx = of_alias_get_id(np, "ethernet"); 1241 if (idx < 0) 1242 idx = 0; 1243 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0; 1244 1245 val = enabled ? 1 : 0; 1246 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val); 1247 } 1248 1249 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1250 { 1251 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1252 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1253 1254 if (stop_gpr->gpr) { 1255 if (enabled) 1256 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1257 BIT(stop_gpr->bit), 1258 BIT(stop_gpr->bit)); 1259 else 1260 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1261 BIT(stop_gpr->bit), 0); 1262 } else if (pdata && pdata->sleep_mode_enable) { 1263 pdata->sleep_mode_enable(enabled); 1264 } else { 1265 fec_enet_ipg_stop_set(fep, enabled); 1266 } 1267 } 1268 1269 static void fec_irqs_disable(struct net_device *ndev) 1270 { 1271 struct fec_enet_private *fep = netdev_priv(ndev); 1272 1273 writel(0, fep->hwp + FEC_IMASK); 1274 } 1275 1276 static void fec_irqs_disable_except_wakeup(struct net_device *ndev) 1277 { 1278 struct fec_enet_private *fep = netdev_priv(ndev); 1279 1280 writel(0, fep->hwp + FEC_IMASK); 1281 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1282 } 1283 1284 static void 1285 fec_stop(struct net_device *ndev) 1286 { 1287 struct fec_enet_private *fep = netdev_priv(ndev); 1288 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1289 u32 val; 1290 1291 /* We cannot expect a graceful transmit stop without link !!! */ 1292 if (fep->link) { 1293 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1294 udelay(10); 1295 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1296 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1297 } 1298 1299 /* Whack a reset. We should wait for this. 1300 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1301 * instead of reset MAC itself. 1302 */ 1303 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1304 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 1305 writel(0, fep->hwp + FEC_ECNTRL); 1306 } else { 1307 writel(1, fep->hwp + FEC_ECNTRL); 1308 udelay(10); 1309 } 1310 } else { 1311 val = readl(fep->hwp + FEC_ECNTRL); 1312 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1313 writel(val, fep->hwp + FEC_ECNTRL); 1314 } 1315 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1316 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1317 1318 /* We have to keep ENET enabled to have MII interrupt stay working */ 1319 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1320 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1321 writel(2, fep->hwp + FEC_ECNTRL); 1322 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1323 } 1324 } 1325 1326 1327 static void 1328 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1329 { 1330 struct fec_enet_private *fep = netdev_priv(ndev); 1331 1332 fec_dump(ndev); 1333 1334 ndev->stats.tx_errors++; 1335 1336 schedule_work(&fep->tx_timeout_work); 1337 } 1338 1339 static void fec_enet_timeout_work(struct work_struct *work) 1340 { 1341 struct fec_enet_private *fep = 1342 container_of(work, struct fec_enet_private, tx_timeout_work); 1343 struct net_device *ndev = fep->netdev; 1344 1345 rtnl_lock(); 1346 if (netif_device_present(ndev) || netif_running(ndev)) { 1347 napi_disable(&fep->napi); 1348 netif_tx_lock_bh(ndev); 1349 fec_restart(ndev); 1350 netif_tx_wake_all_queues(ndev); 1351 netif_tx_unlock_bh(ndev); 1352 napi_enable(&fep->napi); 1353 } 1354 rtnl_unlock(); 1355 } 1356 1357 static void 1358 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1359 struct skb_shared_hwtstamps *hwtstamps) 1360 { 1361 unsigned long flags; 1362 u64 ns; 1363 1364 spin_lock_irqsave(&fep->tmreg_lock, flags); 1365 ns = timecounter_cyc2time(&fep->tc, ts); 1366 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1367 1368 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1369 hwtstamps->hwtstamp = ns_to_ktime(ns); 1370 } 1371 1372 static void 1373 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget) 1374 { 1375 struct fec_enet_private *fep; 1376 struct xdp_frame *xdpf; 1377 struct bufdesc *bdp; 1378 unsigned short status; 1379 struct sk_buff *skb; 1380 struct fec_enet_priv_tx_q *txq; 1381 struct netdev_queue *nq; 1382 int index = 0; 1383 int entries_free; 1384 1385 fep = netdev_priv(ndev); 1386 1387 txq = fep->tx_queue[queue_id]; 1388 /* get next bdp of dirty_tx */ 1389 nq = netdev_get_tx_queue(ndev, queue_id); 1390 bdp = txq->dirty_tx; 1391 1392 /* get next bdp of dirty_tx */ 1393 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1394 1395 while (bdp != READ_ONCE(txq->bd.cur)) { 1396 /* Order the load of bd.cur and cbd_sc */ 1397 rmb(); 1398 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1399 if (status & BD_ENET_TX_READY) 1400 break; 1401 1402 index = fec_enet_get_bd_index(bdp, &txq->bd); 1403 1404 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1405 skb = txq->tx_buf[index].skb; 1406 txq->tx_buf[index].skb = NULL; 1407 if (bdp->cbd_bufaddr && 1408 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1409 dma_unmap_single(&fep->pdev->dev, 1410 fec32_to_cpu(bdp->cbd_bufaddr), 1411 fec16_to_cpu(bdp->cbd_datlen), 1412 DMA_TO_DEVICE); 1413 bdp->cbd_bufaddr = cpu_to_fec32(0); 1414 if (!skb) 1415 goto tx_buf_done; 1416 } else { 1417 /* Tx processing cannot call any XDP (or page pool) APIs if 1418 * the "budget" is 0. Because NAPI is called with budget of 1419 * 0 (such as netpoll) indicates we may be in an IRQ context, 1420 * however, we can't use the page pool from IRQ context. 1421 */ 1422 if (unlikely(!budget)) 1423 break; 1424 1425 xdpf = txq->tx_buf[index].xdp; 1426 if (bdp->cbd_bufaddr) 1427 dma_unmap_single(&fep->pdev->dev, 1428 fec32_to_cpu(bdp->cbd_bufaddr), 1429 fec16_to_cpu(bdp->cbd_datlen), 1430 DMA_TO_DEVICE); 1431 bdp->cbd_bufaddr = cpu_to_fec32(0); 1432 if (!xdpf) { 1433 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1434 goto tx_buf_done; 1435 } 1436 } 1437 1438 /* Check for errors. */ 1439 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1440 BD_ENET_TX_RL | BD_ENET_TX_UN | 1441 BD_ENET_TX_CSL)) { 1442 ndev->stats.tx_errors++; 1443 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1444 ndev->stats.tx_heartbeat_errors++; 1445 if (status & BD_ENET_TX_LC) /* Late collision */ 1446 ndev->stats.tx_window_errors++; 1447 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1448 ndev->stats.tx_aborted_errors++; 1449 if (status & BD_ENET_TX_UN) /* Underrun */ 1450 ndev->stats.tx_fifo_errors++; 1451 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1452 ndev->stats.tx_carrier_errors++; 1453 } else { 1454 ndev->stats.tx_packets++; 1455 1456 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) 1457 ndev->stats.tx_bytes += skb->len; 1458 else 1459 ndev->stats.tx_bytes += xdpf->len; 1460 } 1461 1462 /* Deferred means some collisions occurred during transmit, 1463 * but we eventually sent the packet OK. 1464 */ 1465 if (status & BD_ENET_TX_DEF) 1466 ndev->stats.collisions++; 1467 1468 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1469 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1470 * are to time stamp the packet, so we still need to check time 1471 * stamping enabled flag. 1472 */ 1473 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1474 fep->hwts_tx_en) && fep->bufdesc_ex) { 1475 struct skb_shared_hwtstamps shhwtstamps; 1476 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1477 1478 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1479 skb_tstamp_tx(skb, &shhwtstamps); 1480 } 1481 1482 /* Free the sk buffer associated with this last transmit */ 1483 dev_kfree_skb_any(skb); 1484 } else { 1485 xdp_return_frame(xdpf); 1486 1487 txq->tx_buf[index].xdp = NULL; 1488 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1489 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1490 } 1491 1492 tx_buf_done: 1493 /* Make sure the update to bdp and tx_buf are performed 1494 * before dirty_tx 1495 */ 1496 wmb(); 1497 txq->dirty_tx = bdp; 1498 1499 /* Update pointer to next buffer descriptor to be transmitted */ 1500 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1501 1502 /* Since we have freed up a buffer, the ring is no longer full 1503 */ 1504 if (netif_tx_queue_stopped(nq)) { 1505 entries_free = fec_enet_get_free_txdesc_num(txq); 1506 if (entries_free >= txq->tx_wake_threshold) 1507 netif_tx_wake_queue(nq); 1508 } 1509 } 1510 1511 /* ERR006358: Keep the transmitter going */ 1512 if (bdp != txq->bd.cur && 1513 readl(txq->bd.reg_desc_active) == 0) 1514 writel(0, txq->bd.reg_desc_active); 1515 } 1516 1517 static void fec_enet_tx(struct net_device *ndev, int budget) 1518 { 1519 struct fec_enet_private *fep = netdev_priv(ndev); 1520 int i; 1521 1522 /* Make sure that AVB queues are processed first. */ 1523 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1524 fec_enet_tx_queue(ndev, i, budget); 1525 } 1526 1527 static void fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq, 1528 struct bufdesc *bdp, int index) 1529 { 1530 struct page *new_page; 1531 dma_addr_t phys_addr; 1532 1533 new_page = page_pool_dev_alloc_pages(rxq->page_pool); 1534 WARN_ON(!new_page); 1535 rxq->rx_skb_info[index].page = new_page; 1536 1537 rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM; 1538 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM; 1539 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 1540 } 1541 1542 static u32 1543 fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog, 1544 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int index) 1545 { 1546 unsigned int sync, len = xdp->data_end - xdp->data; 1547 u32 ret = FEC_ENET_XDP_PASS; 1548 struct page *page; 1549 int err; 1550 u32 act; 1551 1552 act = bpf_prog_run_xdp(prog, xdp); 1553 1554 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */ 1555 sync = xdp->data_end - xdp->data_hard_start - FEC_ENET_XDP_HEADROOM; 1556 sync = max(sync, len); 1557 1558 switch (act) { 1559 case XDP_PASS: 1560 rxq->stats[RX_XDP_PASS]++; 1561 ret = FEC_ENET_XDP_PASS; 1562 break; 1563 1564 case XDP_REDIRECT: 1565 rxq->stats[RX_XDP_REDIRECT]++; 1566 err = xdp_do_redirect(fep->netdev, xdp, prog); 1567 if (!err) { 1568 ret = FEC_ENET_XDP_REDIR; 1569 } else { 1570 ret = FEC_ENET_XDP_CONSUMED; 1571 page = virt_to_head_page(xdp->data); 1572 page_pool_put_page(rxq->page_pool, page, sync, true); 1573 } 1574 break; 1575 1576 default: 1577 bpf_warn_invalid_xdp_action(fep->netdev, prog, act); 1578 fallthrough; 1579 1580 case XDP_TX: 1581 bpf_warn_invalid_xdp_action(fep->netdev, prog, act); 1582 fallthrough; 1583 1584 case XDP_ABORTED: 1585 fallthrough; /* handle aborts by dropping packet */ 1586 1587 case XDP_DROP: 1588 rxq->stats[RX_XDP_DROP]++; 1589 ret = FEC_ENET_XDP_CONSUMED; 1590 page = virt_to_head_page(xdp->data); 1591 page_pool_put_page(rxq->page_pool, page, sync, true); 1592 break; 1593 } 1594 1595 return ret; 1596 } 1597 1598 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1599 * When we update through the ring, if the next incoming buffer has 1600 * not been given to the system, we just set the empty indicator, 1601 * effectively tossing the packet. 1602 */ 1603 static int 1604 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1605 { 1606 struct fec_enet_private *fep = netdev_priv(ndev); 1607 struct fec_enet_priv_rx_q *rxq; 1608 struct bufdesc *bdp; 1609 unsigned short status; 1610 struct sk_buff *skb; 1611 ushort pkt_len; 1612 __u8 *data; 1613 int pkt_received = 0; 1614 struct bufdesc_ex *ebdp = NULL; 1615 bool vlan_packet_rcvd = false; 1616 u16 vlan_tag; 1617 int index = 0; 1618 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1619 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 1620 u32 ret, xdp_result = FEC_ENET_XDP_PASS; 1621 u32 data_start = FEC_ENET_XDP_HEADROOM; 1622 struct xdp_buff xdp; 1623 struct page *page; 1624 u32 sub_len = 4; 1625 1626 #if !defined(CONFIG_M5272) 1627 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of 1628 * FEC_RACC_SHIFT16 is set by default in the probe function. 1629 */ 1630 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1631 data_start += 2; 1632 sub_len += 2; 1633 } 1634 #endif 1635 1636 #ifdef CONFIG_M532x 1637 flush_cache_all(); 1638 #endif 1639 rxq = fep->rx_queue[queue_id]; 1640 1641 /* First, grab all of the stats for the incoming packet. 1642 * These get messed up if we get called due to a busy condition. 1643 */ 1644 bdp = rxq->bd.cur; 1645 xdp_init_buff(&xdp, PAGE_SIZE, &rxq->xdp_rxq); 1646 1647 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1648 1649 if (pkt_received >= budget) 1650 break; 1651 pkt_received++; 1652 1653 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); 1654 1655 /* Check for errors. */ 1656 status ^= BD_ENET_RX_LAST; 1657 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1658 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1659 BD_ENET_RX_CL)) { 1660 ndev->stats.rx_errors++; 1661 if (status & BD_ENET_RX_OV) { 1662 /* FIFO overrun */ 1663 ndev->stats.rx_fifo_errors++; 1664 goto rx_processing_done; 1665 } 1666 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1667 | BD_ENET_RX_LAST)) { 1668 /* Frame too long or too short. */ 1669 ndev->stats.rx_length_errors++; 1670 if (status & BD_ENET_RX_LAST) 1671 netdev_err(ndev, "rcv is not +last\n"); 1672 } 1673 if (status & BD_ENET_RX_CR) /* CRC Error */ 1674 ndev->stats.rx_crc_errors++; 1675 /* Report late collisions as a frame error. */ 1676 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1677 ndev->stats.rx_frame_errors++; 1678 goto rx_processing_done; 1679 } 1680 1681 /* Process the incoming frame. */ 1682 ndev->stats.rx_packets++; 1683 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1684 ndev->stats.rx_bytes += pkt_len; 1685 1686 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1687 page = rxq->rx_skb_info[index].page; 1688 dma_sync_single_for_cpu(&fep->pdev->dev, 1689 fec32_to_cpu(bdp->cbd_bufaddr), 1690 pkt_len, 1691 DMA_FROM_DEVICE); 1692 prefetch(page_address(page)); 1693 fec_enet_update_cbd(rxq, bdp, index); 1694 1695 if (xdp_prog) { 1696 xdp_buff_clear_frags_flag(&xdp); 1697 /* subtract 16bit shift and FCS */ 1698 xdp_prepare_buff(&xdp, page_address(page), 1699 data_start, pkt_len - sub_len, false); 1700 ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, index); 1701 xdp_result |= ret; 1702 if (ret != FEC_ENET_XDP_PASS) 1703 goto rx_processing_done; 1704 } 1705 1706 /* The packet length includes FCS, but we don't want to 1707 * include that when passing upstream as it messes up 1708 * bridging applications. 1709 */ 1710 skb = build_skb(page_address(page), PAGE_SIZE); 1711 if (unlikely(!skb)) { 1712 page_pool_recycle_direct(rxq->page_pool, page); 1713 ndev->stats.rx_dropped++; 1714 1715 netdev_err_once(ndev, "build_skb failed!\n"); 1716 goto rx_processing_done; 1717 } 1718 1719 skb_reserve(skb, data_start); 1720 skb_put(skb, pkt_len - sub_len); 1721 skb_mark_for_recycle(skb); 1722 1723 if (unlikely(need_swap)) { 1724 data = page_address(page) + FEC_ENET_XDP_HEADROOM; 1725 swap_buffer(data, pkt_len); 1726 } 1727 data = skb->data; 1728 1729 /* Extract the enhanced buffer descriptor */ 1730 ebdp = NULL; 1731 if (fep->bufdesc_ex) 1732 ebdp = (struct bufdesc_ex *)bdp; 1733 1734 /* If this is a VLAN packet remove the VLAN Tag */ 1735 vlan_packet_rcvd = false; 1736 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1737 fep->bufdesc_ex && 1738 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1739 /* Push and remove the vlan tag */ 1740 struct vlan_hdr *vlan_header = 1741 (struct vlan_hdr *) (data + ETH_HLEN); 1742 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1743 1744 vlan_packet_rcvd = true; 1745 1746 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1747 skb_pull(skb, VLAN_HLEN); 1748 } 1749 1750 skb->protocol = eth_type_trans(skb, ndev); 1751 1752 /* Get receive timestamp from the skb */ 1753 if (fep->hwts_rx_en && fep->bufdesc_ex) 1754 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1755 skb_hwtstamps(skb)); 1756 1757 if (fep->bufdesc_ex && 1758 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1759 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1760 /* don't check it */ 1761 skb->ip_summed = CHECKSUM_UNNECESSARY; 1762 } else { 1763 skb_checksum_none_assert(skb); 1764 } 1765 } 1766 1767 /* Handle received VLAN packets */ 1768 if (vlan_packet_rcvd) 1769 __vlan_hwaccel_put_tag(skb, 1770 htons(ETH_P_8021Q), 1771 vlan_tag); 1772 1773 skb_record_rx_queue(skb, queue_id); 1774 napi_gro_receive(&fep->napi, skb); 1775 1776 rx_processing_done: 1777 /* Clear the status flags for this buffer */ 1778 status &= ~BD_ENET_RX_STATS; 1779 1780 /* Mark the buffer empty */ 1781 status |= BD_ENET_RX_EMPTY; 1782 1783 if (fep->bufdesc_ex) { 1784 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1785 1786 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1787 ebdp->cbd_prot = 0; 1788 ebdp->cbd_bdu = 0; 1789 } 1790 /* Make sure the updates to rest of the descriptor are 1791 * performed before transferring ownership. 1792 */ 1793 wmb(); 1794 bdp->cbd_sc = cpu_to_fec16(status); 1795 1796 /* Update BD pointer to next entry */ 1797 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1798 1799 /* Doing this here will keep the FEC running while we process 1800 * incoming frames. On a heavily loaded network, we should be 1801 * able to keep up at the expense of system resources. 1802 */ 1803 writel(0, rxq->bd.reg_desc_active); 1804 } 1805 rxq->bd.cur = bdp; 1806 1807 if (xdp_result & FEC_ENET_XDP_REDIR) 1808 xdp_do_flush_map(); 1809 1810 return pkt_received; 1811 } 1812 1813 static int fec_enet_rx(struct net_device *ndev, int budget) 1814 { 1815 struct fec_enet_private *fep = netdev_priv(ndev); 1816 int i, done = 0; 1817 1818 /* Make sure that AVB queues are processed first. */ 1819 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1820 done += fec_enet_rx_queue(ndev, budget - done, i); 1821 1822 return done; 1823 } 1824 1825 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1826 { 1827 uint int_events; 1828 1829 int_events = readl(fep->hwp + FEC_IEVENT); 1830 1831 /* Don't clear MDIO events, we poll for those */ 1832 int_events &= ~FEC_ENET_MII; 1833 1834 writel(int_events, fep->hwp + FEC_IEVENT); 1835 1836 return int_events != 0; 1837 } 1838 1839 static irqreturn_t 1840 fec_enet_interrupt(int irq, void *dev_id) 1841 { 1842 struct net_device *ndev = dev_id; 1843 struct fec_enet_private *fep = netdev_priv(ndev); 1844 irqreturn_t ret = IRQ_NONE; 1845 1846 if (fec_enet_collect_events(fep) && fep->link) { 1847 ret = IRQ_HANDLED; 1848 1849 if (napi_schedule_prep(&fep->napi)) { 1850 /* Disable interrupts */ 1851 writel(0, fep->hwp + FEC_IMASK); 1852 __napi_schedule(&fep->napi); 1853 } 1854 } 1855 1856 return ret; 1857 } 1858 1859 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1860 { 1861 struct net_device *ndev = napi->dev; 1862 struct fec_enet_private *fep = netdev_priv(ndev); 1863 int done = 0; 1864 1865 do { 1866 done += fec_enet_rx(ndev, budget - done); 1867 fec_enet_tx(ndev, budget); 1868 } while ((done < budget) && fec_enet_collect_events(fep)); 1869 1870 if (done < budget) { 1871 napi_complete_done(napi, done); 1872 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1873 } 1874 1875 return done; 1876 } 1877 1878 /* ------------------------------------------------------------------------- */ 1879 static int fec_get_mac(struct net_device *ndev) 1880 { 1881 struct fec_enet_private *fep = netdev_priv(ndev); 1882 unsigned char *iap, tmpaddr[ETH_ALEN]; 1883 int ret; 1884 1885 /* 1886 * try to get mac address in following order: 1887 * 1888 * 1) module parameter via kernel command line in form 1889 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1890 */ 1891 iap = macaddr; 1892 1893 /* 1894 * 2) from device tree data 1895 */ 1896 if (!is_valid_ether_addr(iap)) { 1897 struct device_node *np = fep->pdev->dev.of_node; 1898 if (np) { 1899 ret = of_get_mac_address(np, tmpaddr); 1900 if (!ret) 1901 iap = tmpaddr; 1902 else if (ret == -EPROBE_DEFER) 1903 return ret; 1904 } 1905 } 1906 1907 /* 1908 * 3) from flash or fuse (via platform data) 1909 */ 1910 if (!is_valid_ether_addr(iap)) { 1911 #ifdef CONFIG_M5272 1912 if (FEC_FLASHMAC) 1913 iap = (unsigned char *)FEC_FLASHMAC; 1914 #else 1915 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1916 1917 if (pdata) 1918 iap = (unsigned char *)&pdata->mac; 1919 #endif 1920 } 1921 1922 /* 1923 * 4) FEC mac registers set by bootloader 1924 */ 1925 if (!is_valid_ether_addr(iap)) { 1926 *((__be32 *) &tmpaddr[0]) = 1927 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1928 *((__be16 *) &tmpaddr[4]) = 1929 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1930 iap = &tmpaddr[0]; 1931 } 1932 1933 /* 1934 * 5) random mac address 1935 */ 1936 if (!is_valid_ether_addr(iap)) { 1937 /* Report it and use a random ethernet address instead */ 1938 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1939 eth_hw_addr_random(ndev); 1940 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1941 ndev->dev_addr); 1942 return 0; 1943 } 1944 1945 /* Adjust MAC if using macaddr */ 1946 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); 1947 1948 return 0; 1949 } 1950 1951 /* ------------------------------------------------------------------------- */ 1952 1953 /* 1954 * Phy section 1955 */ 1956 static void fec_enet_adjust_link(struct net_device *ndev) 1957 { 1958 struct fec_enet_private *fep = netdev_priv(ndev); 1959 struct phy_device *phy_dev = ndev->phydev; 1960 int status_change = 0; 1961 1962 /* 1963 * If the netdev is down, or is going down, we're not interested 1964 * in link state events, so just mark our idea of the link as down 1965 * and ignore the event. 1966 */ 1967 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1968 fep->link = 0; 1969 } else if (phy_dev->link) { 1970 if (!fep->link) { 1971 fep->link = phy_dev->link; 1972 status_change = 1; 1973 } 1974 1975 if (fep->full_duplex != phy_dev->duplex) { 1976 fep->full_duplex = phy_dev->duplex; 1977 status_change = 1; 1978 } 1979 1980 if (phy_dev->speed != fep->speed) { 1981 fep->speed = phy_dev->speed; 1982 status_change = 1; 1983 } 1984 1985 /* if any of the above changed restart the FEC */ 1986 if (status_change) { 1987 napi_disable(&fep->napi); 1988 netif_tx_lock_bh(ndev); 1989 fec_restart(ndev); 1990 netif_tx_wake_all_queues(ndev); 1991 netif_tx_unlock_bh(ndev); 1992 napi_enable(&fep->napi); 1993 } 1994 } else { 1995 if (fep->link) { 1996 napi_disable(&fep->napi); 1997 netif_tx_lock_bh(ndev); 1998 fec_stop(ndev); 1999 netif_tx_unlock_bh(ndev); 2000 napi_enable(&fep->napi); 2001 fep->link = phy_dev->link; 2002 status_change = 1; 2003 } 2004 } 2005 2006 if (status_change) 2007 phy_print_status(phy_dev); 2008 } 2009 2010 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 2011 { 2012 uint ievent; 2013 int ret; 2014 2015 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 2016 ievent & FEC_ENET_MII, 2, 30000); 2017 2018 if (!ret) 2019 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2020 2021 return ret; 2022 } 2023 2024 static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) 2025 { 2026 struct fec_enet_private *fep = bus->priv; 2027 struct device *dev = &fep->pdev->dev; 2028 int ret = 0, frame_start, frame_addr, frame_op; 2029 2030 ret = pm_runtime_resume_and_get(dev); 2031 if (ret < 0) 2032 return ret; 2033 2034 /* C22 read */ 2035 frame_op = FEC_MMFR_OP_READ; 2036 frame_start = FEC_MMFR_ST; 2037 frame_addr = regnum; 2038 2039 /* start a read op */ 2040 writel(frame_start | frame_op | 2041 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2042 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2043 2044 /* wait for end of transfer */ 2045 ret = fec_enet_mdio_wait(fep); 2046 if (ret) { 2047 netdev_err(fep->netdev, "MDIO read timeout\n"); 2048 goto out; 2049 } 2050 2051 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2052 2053 out: 2054 pm_runtime_mark_last_busy(dev); 2055 pm_runtime_put_autosuspend(dev); 2056 2057 return ret; 2058 } 2059 2060 static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id, 2061 int devad, int regnum) 2062 { 2063 struct fec_enet_private *fep = bus->priv; 2064 struct device *dev = &fep->pdev->dev; 2065 int ret = 0, frame_start, frame_op; 2066 2067 ret = pm_runtime_resume_and_get(dev); 2068 if (ret < 0) 2069 return ret; 2070 2071 frame_start = FEC_MMFR_ST_C45; 2072 2073 /* write address */ 2074 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2075 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2076 FEC_MMFR_TA | (regnum & 0xFFFF), 2077 fep->hwp + FEC_MII_DATA); 2078 2079 /* wait for end of transfer */ 2080 ret = fec_enet_mdio_wait(fep); 2081 if (ret) { 2082 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2083 goto out; 2084 } 2085 2086 frame_op = FEC_MMFR_OP_READ_C45; 2087 2088 /* start a read op */ 2089 writel(frame_start | frame_op | 2090 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2091 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2092 2093 /* wait for end of transfer */ 2094 ret = fec_enet_mdio_wait(fep); 2095 if (ret) { 2096 netdev_err(fep->netdev, "MDIO read timeout\n"); 2097 goto out; 2098 } 2099 2100 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2101 2102 out: 2103 pm_runtime_mark_last_busy(dev); 2104 pm_runtime_put_autosuspend(dev); 2105 2106 return ret; 2107 } 2108 2109 static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, 2110 u16 value) 2111 { 2112 struct fec_enet_private *fep = bus->priv; 2113 struct device *dev = &fep->pdev->dev; 2114 int ret, frame_start, frame_addr; 2115 2116 ret = pm_runtime_resume_and_get(dev); 2117 if (ret < 0) 2118 return ret; 2119 2120 /* C22 write */ 2121 frame_start = FEC_MMFR_ST; 2122 frame_addr = regnum; 2123 2124 /* start a write op */ 2125 writel(frame_start | FEC_MMFR_OP_WRITE | 2126 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2127 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2128 fep->hwp + FEC_MII_DATA); 2129 2130 /* wait for end of transfer */ 2131 ret = fec_enet_mdio_wait(fep); 2132 if (ret) 2133 netdev_err(fep->netdev, "MDIO write timeout\n"); 2134 2135 pm_runtime_mark_last_busy(dev); 2136 pm_runtime_put_autosuspend(dev); 2137 2138 return ret; 2139 } 2140 2141 static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id, 2142 int devad, int regnum, u16 value) 2143 { 2144 struct fec_enet_private *fep = bus->priv; 2145 struct device *dev = &fep->pdev->dev; 2146 int ret, frame_start; 2147 2148 ret = pm_runtime_resume_and_get(dev); 2149 if (ret < 0) 2150 return ret; 2151 2152 frame_start = FEC_MMFR_ST_C45; 2153 2154 /* write address */ 2155 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2156 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2157 FEC_MMFR_TA | (regnum & 0xFFFF), 2158 fep->hwp + FEC_MII_DATA); 2159 2160 /* wait for end of transfer */ 2161 ret = fec_enet_mdio_wait(fep); 2162 if (ret) { 2163 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2164 goto out; 2165 } 2166 2167 /* start a write op */ 2168 writel(frame_start | FEC_MMFR_OP_WRITE | 2169 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2170 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2171 fep->hwp + FEC_MII_DATA); 2172 2173 /* wait for end of transfer */ 2174 ret = fec_enet_mdio_wait(fep); 2175 if (ret) 2176 netdev_err(fep->netdev, "MDIO write timeout\n"); 2177 2178 out: 2179 pm_runtime_mark_last_busy(dev); 2180 pm_runtime_put_autosuspend(dev); 2181 2182 return ret; 2183 } 2184 2185 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 2186 { 2187 struct fec_enet_private *fep = netdev_priv(ndev); 2188 struct phy_device *phy_dev = ndev->phydev; 2189 2190 if (phy_dev) { 2191 phy_reset_after_clk_enable(phy_dev); 2192 } else if (fep->phy_node) { 2193 /* 2194 * If the PHY still is not bound to the MAC, but there is 2195 * OF PHY node and a matching PHY device instance already, 2196 * use the OF PHY node to obtain the PHY device instance, 2197 * and then use that PHY device instance when triggering 2198 * the PHY reset. 2199 */ 2200 phy_dev = of_phy_find_device(fep->phy_node); 2201 phy_reset_after_clk_enable(phy_dev); 2202 put_device(&phy_dev->mdio.dev); 2203 } 2204 } 2205 2206 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 2207 { 2208 struct fec_enet_private *fep = netdev_priv(ndev); 2209 int ret; 2210 2211 if (enable) { 2212 ret = clk_prepare_enable(fep->clk_enet_out); 2213 if (ret) 2214 return ret; 2215 2216 if (fep->clk_ptp) { 2217 mutex_lock(&fep->ptp_clk_mutex); 2218 ret = clk_prepare_enable(fep->clk_ptp); 2219 if (ret) { 2220 mutex_unlock(&fep->ptp_clk_mutex); 2221 goto failed_clk_ptp; 2222 } else { 2223 fep->ptp_clk_on = true; 2224 } 2225 mutex_unlock(&fep->ptp_clk_mutex); 2226 } 2227 2228 ret = clk_prepare_enable(fep->clk_ref); 2229 if (ret) 2230 goto failed_clk_ref; 2231 2232 ret = clk_prepare_enable(fep->clk_2x_txclk); 2233 if (ret) 2234 goto failed_clk_2x_txclk; 2235 2236 fec_enet_phy_reset_after_clk_enable(ndev); 2237 } else { 2238 clk_disable_unprepare(fep->clk_enet_out); 2239 if (fep->clk_ptp) { 2240 mutex_lock(&fep->ptp_clk_mutex); 2241 clk_disable_unprepare(fep->clk_ptp); 2242 fep->ptp_clk_on = false; 2243 mutex_unlock(&fep->ptp_clk_mutex); 2244 } 2245 clk_disable_unprepare(fep->clk_ref); 2246 clk_disable_unprepare(fep->clk_2x_txclk); 2247 } 2248 2249 return 0; 2250 2251 failed_clk_2x_txclk: 2252 if (fep->clk_ref) 2253 clk_disable_unprepare(fep->clk_ref); 2254 failed_clk_ref: 2255 if (fep->clk_ptp) { 2256 mutex_lock(&fep->ptp_clk_mutex); 2257 clk_disable_unprepare(fep->clk_ptp); 2258 fep->ptp_clk_on = false; 2259 mutex_unlock(&fep->ptp_clk_mutex); 2260 } 2261 failed_clk_ptp: 2262 clk_disable_unprepare(fep->clk_enet_out); 2263 2264 return ret; 2265 } 2266 2267 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2268 struct device_node *np) 2269 { 2270 u32 rgmii_tx_delay, rgmii_rx_delay; 2271 2272 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2273 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2274 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2275 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2276 return -EINVAL; 2277 } else if (rgmii_tx_delay == 2000) { 2278 fep->rgmii_txc_dly = true; 2279 } 2280 } 2281 2282 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2283 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2284 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2285 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2286 return -EINVAL; 2287 } else if (rgmii_rx_delay == 2000) { 2288 fep->rgmii_rxc_dly = true; 2289 } 2290 } 2291 2292 return 0; 2293 } 2294 2295 static int fec_enet_mii_probe(struct net_device *ndev) 2296 { 2297 struct fec_enet_private *fep = netdev_priv(ndev); 2298 struct phy_device *phy_dev = NULL; 2299 char mdio_bus_id[MII_BUS_ID_SIZE]; 2300 char phy_name[MII_BUS_ID_SIZE + 3]; 2301 int phy_id; 2302 int dev_id = fep->dev_id; 2303 2304 if (fep->phy_node) { 2305 phy_dev = of_phy_connect(ndev, fep->phy_node, 2306 &fec_enet_adjust_link, 0, 2307 fep->phy_interface); 2308 if (!phy_dev) { 2309 netdev_err(ndev, "Unable to connect to phy\n"); 2310 return -ENODEV; 2311 } 2312 } else { 2313 /* check for attached phy */ 2314 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2315 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2316 continue; 2317 if (dev_id--) 2318 continue; 2319 strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2320 break; 2321 } 2322 2323 if (phy_id >= PHY_MAX_ADDR) { 2324 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2325 strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2326 phy_id = 0; 2327 } 2328 2329 snprintf(phy_name, sizeof(phy_name), 2330 PHY_ID_FMT, mdio_bus_id, phy_id); 2331 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2332 fep->phy_interface); 2333 } 2334 2335 if (IS_ERR(phy_dev)) { 2336 netdev_err(ndev, "could not attach to PHY\n"); 2337 return PTR_ERR(phy_dev); 2338 } 2339 2340 /* mask with MAC supported features */ 2341 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2342 phy_set_max_speed(phy_dev, 1000); 2343 phy_remove_link_mode(phy_dev, 2344 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2345 #if !defined(CONFIG_M5272) 2346 phy_support_sym_pause(phy_dev); 2347 #endif 2348 } 2349 else 2350 phy_set_max_speed(phy_dev, 100); 2351 2352 fep->link = 0; 2353 fep->full_duplex = 0; 2354 2355 phy_dev->mac_managed_pm = true; 2356 2357 phy_attached_info(phy_dev); 2358 2359 return 0; 2360 } 2361 2362 static int fec_enet_mii_init(struct platform_device *pdev) 2363 { 2364 static struct mii_bus *fec0_mii_bus; 2365 struct net_device *ndev = platform_get_drvdata(pdev); 2366 struct fec_enet_private *fep = netdev_priv(ndev); 2367 bool suppress_preamble = false; 2368 struct device_node *node; 2369 int err = -ENXIO; 2370 u32 mii_speed, holdtime; 2371 u32 bus_freq; 2372 2373 /* 2374 * The i.MX28 dual fec interfaces are not equal. 2375 * Here are the differences: 2376 * 2377 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2378 * - fec0 acts as the 1588 time master while fec1 is slave 2379 * - external phys can only be configured by fec0 2380 * 2381 * That is to say fec1 can not work independently. It only works 2382 * when fec0 is working. The reason behind this design is that the 2383 * second interface is added primarily for Switch mode. 2384 * 2385 * Because of the last point above, both phys are attached on fec0 2386 * mdio interface in board design, and need to be configured by 2387 * fec0 mii_bus. 2388 */ 2389 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2390 /* fec1 uses fec0 mii_bus */ 2391 if (mii_cnt && fec0_mii_bus) { 2392 fep->mii_bus = fec0_mii_bus; 2393 mii_cnt++; 2394 return 0; 2395 } 2396 return -ENOENT; 2397 } 2398 2399 bus_freq = 2500000; /* 2.5MHz by default */ 2400 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2401 if (node) { 2402 of_property_read_u32(node, "clock-frequency", &bus_freq); 2403 suppress_preamble = of_property_read_bool(node, 2404 "suppress-preamble"); 2405 } 2406 2407 /* 2408 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2409 * 2410 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2411 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2412 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2413 * document. 2414 */ 2415 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2416 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2417 mii_speed--; 2418 if (mii_speed > 63) { 2419 dev_err(&pdev->dev, 2420 "fec clock (%lu) too fast to get right mii speed\n", 2421 clk_get_rate(fep->clk_ipg)); 2422 err = -EINVAL; 2423 goto err_out; 2424 } 2425 2426 /* 2427 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2428 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2429 * versions are RAZ there, so just ignore the difference and write the 2430 * register always. 2431 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2432 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2433 * output. 2434 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2435 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2436 * holdtime cannot result in a value greater than 3. 2437 */ 2438 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2439 2440 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2441 2442 if (suppress_preamble) 2443 fep->phy_speed |= BIT(7); 2444 2445 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2446 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2447 * MII event generation condition: 2448 * - writing MSCR: 2449 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2450 * mscr_reg_data_in[7:0] != 0 2451 * - writing MMFR: 2452 * - mscr[7:0]_not_zero 2453 */ 2454 writel(0, fep->hwp + FEC_MII_DATA); 2455 } 2456 2457 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2458 2459 /* Clear any pending transaction complete indication */ 2460 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2461 2462 fep->mii_bus = mdiobus_alloc(); 2463 if (fep->mii_bus == NULL) { 2464 err = -ENOMEM; 2465 goto err_out; 2466 } 2467 2468 fep->mii_bus->name = "fec_enet_mii_bus"; 2469 fep->mii_bus->read = fec_enet_mdio_read_c22; 2470 fep->mii_bus->write = fec_enet_mdio_write_c22; 2471 if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) { 2472 fep->mii_bus->read_c45 = fec_enet_mdio_read_c45; 2473 fep->mii_bus->write_c45 = fec_enet_mdio_write_c45; 2474 } 2475 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2476 pdev->name, fep->dev_id + 1); 2477 fep->mii_bus->priv = fep; 2478 fep->mii_bus->parent = &pdev->dev; 2479 2480 err = of_mdiobus_register(fep->mii_bus, node); 2481 if (err) 2482 goto err_out_free_mdiobus; 2483 of_node_put(node); 2484 2485 mii_cnt++; 2486 2487 /* save fec0 mii_bus */ 2488 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2489 fec0_mii_bus = fep->mii_bus; 2490 2491 return 0; 2492 2493 err_out_free_mdiobus: 2494 mdiobus_free(fep->mii_bus); 2495 err_out: 2496 of_node_put(node); 2497 return err; 2498 } 2499 2500 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2501 { 2502 if (--mii_cnt == 0) { 2503 mdiobus_unregister(fep->mii_bus); 2504 mdiobus_free(fep->mii_bus); 2505 } 2506 } 2507 2508 static void fec_enet_get_drvinfo(struct net_device *ndev, 2509 struct ethtool_drvinfo *info) 2510 { 2511 struct fec_enet_private *fep = netdev_priv(ndev); 2512 2513 strscpy(info->driver, fep->pdev->dev.driver->name, 2514 sizeof(info->driver)); 2515 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2516 } 2517 2518 static int fec_enet_get_regs_len(struct net_device *ndev) 2519 { 2520 struct fec_enet_private *fep = netdev_priv(ndev); 2521 struct resource *r; 2522 int s = 0; 2523 2524 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2525 if (r) 2526 s = resource_size(r); 2527 2528 return s; 2529 } 2530 2531 /* List of registers that can be safety be read to dump them with ethtool */ 2532 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2533 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2534 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2535 static __u32 fec_enet_register_version = 2; 2536 static u32 fec_enet_register_offset[] = { 2537 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2538 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2539 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2540 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2541 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2542 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2543 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2544 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2545 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2546 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2547 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2548 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2549 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2550 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2551 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2552 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2553 RMON_T_P_GTE2048, RMON_T_OCTETS, 2554 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2555 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2556 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2557 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2558 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2559 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2560 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2561 RMON_R_P_GTE2048, RMON_R_OCTETS, 2562 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2563 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2564 }; 2565 /* for i.MX6ul */ 2566 static u32 fec_enet_register_offset_6ul[] = { 2567 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2568 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2569 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0, 2570 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, 2571 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0, 2572 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2573 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, 2574 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2575 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2576 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2577 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2578 RMON_T_P_GTE2048, RMON_T_OCTETS, 2579 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2580 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2581 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2582 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2583 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2584 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2585 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2586 RMON_R_P_GTE2048, RMON_R_OCTETS, 2587 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2588 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2589 }; 2590 #else 2591 static __u32 fec_enet_register_version = 1; 2592 static u32 fec_enet_register_offset[] = { 2593 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2594 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2595 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2596 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2597 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2598 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2599 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2600 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2601 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2602 }; 2603 #endif 2604 2605 static void fec_enet_get_regs(struct net_device *ndev, 2606 struct ethtool_regs *regs, void *regbuf) 2607 { 2608 struct fec_enet_private *fep = netdev_priv(ndev); 2609 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2610 struct device *dev = &fep->pdev->dev; 2611 u32 *buf = (u32 *)regbuf; 2612 u32 i, off; 2613 int ret; 2614 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2615 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2616 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2617 u32 *reg_list; 2618 u32 reg_cnt; 2619 2620 if (!of_machine_is_compatible("fsl,imx6ul")) { 2621 reg_list = fec_enet_register_offset; 2622 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2623 } else { 2624 reg_list = fec_enet_register_offset_6ul; 2625 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul); 2626 } 2627 #else 2628 /* coldfire */ 2629 static u32 *reg_list = fec_enet_register_offset; 2630 static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2631 #endif 2632 ret = pm_runtime_resume_and_get(dev); 2633 if (ret < 0) 2634 return; 2635 2636 regs->version = fec_enet_register_version; 2637 2638 memset(buf, 0, regs->len); 2639 2640 for (i = 0; i < reg_cnt; i++) { 2641 off = reg_list[i]; 2642 2643 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2644 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2645 continue; 2646 2647 off >>= 2; 2648 buf[off] = readl(&theregs[off]); 2649 } 2650 2651 pm_runtime_mark_last_busy(dev); 2652 pm_runtime_put_autosuspend(dev); 2653 } 2654 2655 static int fec_enet_get_ts_info(struct net_device *ndev, 2656 struct ethtool_ts_info *info) 2657 { 2658 struct fec_enet_private *fep = netdev_priv(ndev); 2659 2660 if (fep->bufdesc_ex) { 2661 2662 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2663 SOF_TIMESTAMPING_RX_SOFTWARE | 2664 SOF_TIMESTAMPING_SOFTWARE | 2665 SOF_TIMESTAMPING_TX_HARDWARE | 2666 SOF_TIMESTAMPING_RX_HARDWARE | 2667 SOF_TIMESTAMPING_RAW_HARDWARE; 2668 if (fep->ptp_clock) 2669 info->phc_index = ptp_clock_index(fep->ptp_clock); 2670 else 2671 info->phc_index = -1; 2672 2673 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2674 (1 << HWTSTAMP_TX_ON); 2675 2676 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2677 (1 << HWTSTAMP_FILTER_ALL); 2678 return 0; 2679 } else { 2680 return ethtool_op_get_ts_info(ndev, info); 2681 } 2682 } 2683 2684 #if !defined(CONFIG_M5272) 2685 2686 static void fec_enet_get_pauseparam(struct net_device *ndev, 2687 struct ethtool_pauseparam *pause) 2688 { 2689 struct fec_enet_private *fep = netdev_priv(ndev); 2690 2691 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2692 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2693 pause->rx_pause = pause->tx_pause; 2694 } 2695 2696 static int fec_enet_set_pauseparam(struct net_device *ndev, 2697 struct ethtool_pauseparam *pause) 2698 { 2699 struct fec_enet_private *fep = netdev_priv(ndev); 2700 2701 if (!ndev->phydev) 2702 return -ENODEV; 2703 2704 if (pause->tx_pause != pause->rx_pause) { 2705 netdev_info(ndev, 2706 "hardware only support enable/disable both tx and rx"); 2707 return -EINVAL; 2708 } 2709 2710 fep->pause_flag = 0; 2711 2712 /* tx pause must be same as rx pause */ 2713 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2714 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2715 2716 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2717 pause->autoneg); 2718 2719 if (pause->autoneg) { 2720 if (netif_running(ndev)) 2721 fec_stop(ndev); 2722 phy_start_aneg(ndev->phydev); 2723 } 2724 if (netif_running(ndev)) { 2725 napi_disable(&fep->napi); 2726 netif_tx_lock_bh(ndev); 2727 fec_restart(ndev); 2728 netif_tx_wake_all_queues(ndev); 2729 netif_tx_unlock_bh(ndev); 2730 napi_enable(&fep->napi); 2731 } 2732 2733 return 0; 2734 } 2735 2736 static const struct fec_stat { 2737 char name[ETH_GSTRING_LEN]; 2738 u16 offset; 2739 } fec_stats[] = { 2740 /* RMON TX */ 2741 { "tx_dropped", RMON_T_DROP }, 2742 { "tx_packets", RMON_T_PACKETS }, 2743 { "tx_broadcast", RMON_T_BC_PKT }, 2744 { "tx_multicast", RMON_T_MC_PKT }, 2745 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2746 { "tx_undersize", RMON_T_UNDERSIZE }, 2747 { "tx_oversize", RMON_T_OVERSIZE }, 2748 { "tx_fragment", RMON_T_FRAG }, 2749 { "tx_jabber", RMON_T_JAB }, 2750 { "tx_collision", RMON_T_COL }, 2751 { "tx_64byte", RMON_T_P64 }, 2752 { "tx_65to127byte", RMON_T_P65TO127 }, 2753 { "tx_128to255byte", RMON_T_P128TO255 }, 2754 { "tx_256to511byte", RMON_T_P256TO511 }, 2755 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2756 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2757 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2758 { "tx_octets", RMON_T_OCTETS }, 2759 2760 /* IEEE TX */ 2761 { "IEEE_tx_drop", IEEE_T_DROP }, 2762 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2763 { "IEEE_tx_1col", IEEE_T_1COL }, 2764 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2765 { "IEEE_tx_def", IEEE_T_DEF }, 2766 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2767 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2768 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2769 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2770 { "IEEE_tx_sqe", IEEE_T_SQE }, 2771 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2772 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2773 2774 /* RMON RX */ 2775 { "rx_packets", RMON_R_PACKETS }, 2776 { "rx_broadcast", RMON_R_BC_PKT }, 2777 { "rx_multicast", RMON_R_MC_PKT }, 2778 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2779 { "rx_undersize", RMON_R_UNDERSIZE }, 2780 { "rx_oversize", RMON_R_OVERSIZE }, 2781 { "rx_fragment", RMON_R_FRAG }, 2782 { "rx_jabber", RMON_R_JAB }, 2783 { "rx_64byte", RMON_R_P64 }, 2784 { "rx_65to127byte", RMON_R_P65TO127 }, 2785 { "rx_128to255byte", RMON_R_P128TO255 }, 2786 { "rx_256to511byte", RMON_R_P256TO511 }, 2787 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2788 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2789 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2790 { "rx_octets", RMON_R_OCTETS }, 2791 2792 /* IEEE RX */ 2793 { "IEEE_rx_drop", IEEE_R_DROP }, 2794 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2795 { "IEEE_rx_crc", IEEE_R_CRC }, 2796 { "IEEE_rx_align", IEEE_R_ALIGN }, 2797 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2798 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2799 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2800 }; 2801 2802 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2803 2804 static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = { 2805 "rx_xdp_redirect", /* RX_XDP_REDIRECT = 0, */ 2806 "rx_xdp_pass", /* RX_XDP_PASS, */ 2807 "rx_xdp_drop", /* RX_XDP_DROP, */ 2808 "rx_xdp_tx", /* RX_XDP_TX, */ 2809 "rx_xdp_tx_errors", /* RX_XDP_TX_ERRORS, */ 2810 "tx_xdp_xmit", /* TX_XDP_XMIT, */ 2811 "tx_xdp_xmit_errors", /* TX_XDP_XMIT_ERRORS, */ 2812 }; 2813 2814 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2815 { 2816 struct fec_enet_private *fep = netdev_priv(dev); 2817 int i; 2818 2819 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2820 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2821 } 2822 2823 static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data) 2824 { 2825 u64 xdp_stats[XDP_STATS_TOTAL] = { 0 }; 2826 struct fec_enet_priv_rx_q *rxq; 2827 int i, j; 2828 2829 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2830 rxq = fep->rx_queue[i]; 2831 2832 for (j = 0; j < XDP_STATS_TOTAL; j++) 2833 xdp_stats[j] += rxq->stats[j]; 2834 } 2835 2836 memcpy(data, xdp_stats, sizeof(xdp_stats)); 2837 } 2838 2839 static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data) 2840 { 2841 #ifdef CONFIG_PAGE_POOL_STATS 2842 struct page_pool_stats stats = {}; 2843 struct fec_enet_priv_rx_q *rxq; 2844 int i; 2845 2846 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2847 rxq = fep->rx_queue[i]; 2848 2849 if (!rxq->page_pool) 2850 continue; 2851 2852 page_pool_get_stats(rxq->page_pool, &stats); 2853 } 2854 2855 page_pool_ethtool_stats_get(data, &stats); 2856 #endif 2857 } 2858 2859 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2860 struct ethtool_stats *stats, u64 *data) 2861 { 2862 struct fec_enet_private *fep = netdev_priv(dev); 2863 2864 if (netif_running(dev)) 2865 fec_enet_update_ethtool_stats(dev); 2866 2867 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2868 data += FEC_STATS_SIZE / sizeof(u64); 2869 2870 fec_enet_get_xdp_stats(fep, data); 2871 data += XDP_STATS_TOTAL; 2872 2873 fec_enet_page_pool_stats(fep, data); 2874 } 2875 2876 static void fec_enet_get_strings(struct net_device *netdev, 2877 u32 stringset, u8 *data) 2878 { 2879 int i; 2880 switch (stringset) { 2881 case ETH_SS_STATS: 2882 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) { 2883 memcpy(data, fec_stats[i].name, ETH_GSTRING_LEN); 2884 data += ETH_GSTRING_LEN; 2885 } 2886 for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) { 2887 strncpy(data, fec_xdp_stat_strs[i], ETH_GSTRING_LEN); 2888 data += ETH_GSTRING_LEN; 2889 } 2890 page_pool_ethtool_stats_get_strings(data); 2891 2892 break; 2893 case ETH_SS_TEST: 2894 net_selftest_get_strings(data); 2895 break; 2896 } 2897 } 2898 2899 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2900 { 2901 int count; 2902 2903 switch (sset) { 2904 case ETH_SS_STATS: 2905 count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL; 2906 count += page_pool_ethtool_stats_get_count(); 2907 return count; 2908 2909 case ETH_SS_TEST: 2910 return net_selftest_get_count(); 2911 default: 2912 return -EOPNOTSUPP; 2913 } 2914 } 2915 2916 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2917 { 2918 struct fec_enet_private *fep = netdev_priv(dev); 2919 struct fec_enet_priv_rx_q *rxq; 2920 int i, j; 2921 2922 /* Disable MIB statistics counters */ 2923 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2924 2925 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2926 writel(0, fep->hwp + fec_stats[i].offset); 2927 2928 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2929 rxq = fep->rx_queue[i]; 2930 for (j = 0; j < XDP_STATS_TOTAL; j++) 2931 rxq->stats[j] = 0; 2932 } 2933 2934 /* Don't disable MIB statistics counters */ 2935 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2936 } 2937 2938 #else /* !defined(CONFIG_M5272) */ 2939 #define FEC_STATS_SIZE 0 2940 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2941 { 2942 } 2943 2944 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2945 { 2946 } 2947 #endif /* !defined(CONFIG_M5272) */ 2948 2949 /* ITR clock source is enet system clock (clk_ahb). 2950 * TCTT unit is cycle_ns * 64 cycle 2951 * So, the ICTT value = X us / (cycle_ns * 64) 2952 */ 2953 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2954 { 2955 struct fec_enet_private *fep = netdev_priv(ndev); 2956 2957 return us * (fep->itr_clk_rate / 64000) / 1000; 2958 } 2959 2960 /* Set threshold for interrupt coalescing */ 2961 static void fec_enet_itr_coal_set(struct net_device *ndev) 2962 { 2963 struct fec_enet_private *fep = netdev_priv(ndev); 2964 int rx_itr, tx_itr; 2965 2966 /* Must be greater than zero to avoid unpredictable behavior */ 2967 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2968 !fep->tx_time_itr || !fep->tx_pkts_itr) 2969 return; 2970 2971 /* Select enet system clock as Interrupt Coalescing 2972 * timer Clock Source 2973 */ 2974 rx_itr = FEC_ITR_CLK_SEL; 2975 tx_itr = FEC_ITR_CLK_SEL; 2976 2977 /* set ICFT and ICTT */ 2978 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2979 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2980 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2981 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2982 2983 rx_itr |= FEC_ITR_EN; 2984 tx_itr |= FEC_ITR_EN; 2985 2986 writel(tx_itr, fep->hwp + FEC_TXIC0); 2987 writel(rx_itr, fep->hwp + FEC_RXIC0); 2988 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 2989 writel(tx_itr, fep->hwp + FEC_TXIC1); 2990 writel(rx_itr, fep->hwp + FEC_RXIC1); 2991 writel(tx_itr, fep->hwp + FEC_TXIC2); 2992 writel(rx_itr, fep->hwp + FEC_RXIC2); 2993 } 2994 } 2995 2996 static int fec_enet_get_coalesce(struct net_device *ndev, 2997 struct ethtool_coalesce *ec, 2998 struct kernel_ethtool_coalesce *kernel_coal, 2999 struct netlink_ext_ack *extack) 3000 { 3001 struct fec_enet_private *fep = netdev_priv(ndev); 3002 3003 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3004 return -EOPNOTSUPP; 3005 3006 ec->rx_coalesce_usecs = fep->rx_time_itr; 3007 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 3008 3009 ec->tx_coalesce_usecs = fep->tx_time_itr; 3010 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 3011 3012 return 0; 3013 } 3014 3015 static int fec_enet_set_coalesce(struct net_device *ndev, 3016 struct ethtool_coalesce *ec, 3017 struct kernel_ethtool_coalesce *kernel_coal, 3018 struct netlink_ext_ack *extack) 3019 { 3020 struct fec_enet_private *fep = netdev_priv(ndev); 3021 struct device *dev = &fep->pdev->dev; 3022 unsigned int cycle; 3023 3024 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3025 return -EOPNOTSUPP; 3026 3027 if (ec->rx_max_coalesced_frames > 255) { 3028 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 3029 return -EINVAL; 3030 } 3031 3032 if (ec->tx_max_coalesced_frames > 255) { 3033 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 3034 return -EINVAL; 3035 } 3036 3037 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 3038 if (cycle > 0xFFFF) { 3039 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 3040 return -EINVAL; 3041 } 3042 3043 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 3044 if (cycle > 0xFFFF) { 3045 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 3046 return -EINVAL; 3047 } 3048 3049 fep->rx_time_itr = ec->rx_coalesce_usecs; 3050 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 3051 3052 fep->tx_time_itr = ec->tx_coalesce_usecs; 3053 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 3054 3055 fec_enet_itr_coal_set(ndev); 3056 3057 return 0; 3058 } 3059 3060 /* LPI Sleep Ts count base on tx clk (clk_ref). 3061 * The lpi sleep cnt value = X us / (cycle_ns). 3062 */ 3063 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 3064 { 3065 struct fec_enet_private *fep = netdev_priv(ndev); 3066 3067 return us * (fep->clk_ref_rate / 1000) / 1000; 3068 } 3069 3070 static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable) 3071 { 3072 struct fec_enet_private *fep = netdev_priv(ndev); 3073 struct ethtool_eee *p = &fep->eee; 3074 unsigned int sleep_cycle, wake_cycle; 3075 int ret = 0; 3076 3077 if (enable) { 3078 ret = phy_init_eee(ndev->phydev, false); 3079 if (ret) 3080 return ret; 3081 3082 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer); 3083 wake_cycle = sleep_cycle; 3084 } else { 3085 sleep_cycle = 0; 3086 wake_cycle = 0; 3087 } 3088 3089 p->tx_lpi_enabled = enable; 3090 p->eee_enabled = enable; 3091 p->eee_active = enable; 3092 3093 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 3094 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 3095 3096 return 0; 3097 } 3098 3099 static int 3100 fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata) 3101 { 3102 struct fec_enet_private *fep = netdev_priv(ndev); 3103 struct ethtool_eee *p = &fep->eee; 3104 3105 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3106 return -EOPNOTSUPP; 3107 3108 if (!netif_running(ndev)) 3109 return -ENETDOWN; 3110 3111 edata->eee_enabled = p->eee_enabled; 3112 edata->eee_active = p->eee_active; 3113 edata->tx_lpi_timer = p->tx_lpi_timer; 3114 edata->tx_lpi_enabled = p->tx_lpi_enabled; 3115 3116 return phy_ethtool_get_eee(ndev->phydev, edata); 3117 } 3118 3119 static int 3120 fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata) 3121 { 3122 struct fec_enet_private *fep = netdev_priv(ndev); 3123 struct ethtool_eee *p = &fep->eee; 3124 int ret = 0; 3125 3126 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3127 return -EOPNOTSUPP; 3128 3129 if (!netif_running(ndev)) 3130 return -ENETDOWN; 3131 3132 p->tx_lpi_timer = edata->tx_lpi_timer; 3133 3134 if (!edata->eee_enabled || !edata->tx_lpi_enabled || 3135 !edata->tx_lpi_timer) 3136 ret = fec_enet_eee_mode_set(ndev, false); 3137 else 3138 ret = fec_enet_eee_mode_set(ndev, true); 3139 3140 if (ret) 3141 return ret; 3142 3143 return phy_ethtool_set_eee(ndev->phydev, edata); 3144 } 3145 3146 static void 3147 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3148 { 3149 struct fec_enet_private *fep = netdev_priv(ndev); 3150 3151 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 3152 wol->supported = WAKE_MAGIC; 3153 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 3154 } else { 3155 wol->supported = wol->wolopts = 0; 3156 } 3157 } 3158 3159 static int 3160 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3161 { 3162 struct fec_enet_private *fep = netdev_priv(ndev); 3163 3164 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 3165 return -EINVAL; 3166 3167 if (wol->wolopts & ~WAKE_MAGIC) 3168 return -EINVAL; 3169 3170 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 3171 if (device_may_wakeup(&ndev->dev)) 3172 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 3173 else 3174 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 3175 3176 return 0; 3177 } 3178 3179 static const struct ethtool_ops fec_enet_ethtool_ops = { 3180 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3181 ETHTOOL_COALESCE_MAX_FRAMES, 3182 .get_drvinfo = fec_enet_get_drvinfo, 3183 .get_regs_len = fec_enet_get_regs_len, 3184 .get_regs = fec_enet_get_regs, 3185 .nway_reset = phy_ethtool_nway_reset, 3186 .get_link = ethtool_op_get_link, 3187 .get_coalesce = fec_enet_get_coalesce, 3188 .set_coalesce = fec_enet_set_coalesce, 3189 #ifndef CONFIG_M5272 3190 .get_pauseparam = fec_enet_get_pauseparam, 3191 .set_pauseparam = fec_enet_set_pauseparam, 3192 .get_strings = fec_enet_get_strings, 3193 .get_ethtool_stats = fec_enet_get_ethtool_stats, 3194 .get_sset_count = fec_enet_get_sset_count, 3195 #endif 3196 .get_ts_info = fec_enet_get_ts_info, 3197 .get_wol = fec_enet_get_wol, 3198 .set_wol = fec_enet_set_wol, 3199 .get_eee = fec_enet_get_eee, 3200 .set_eee = fec_enet_set_eee, 3201 .get_link_ksettings = phy_ethtool_get_link_ksettings, 3202 .set_link_ksettings = phy_ethtool_set_link_ksettings, 3203 .self_test = net_selftest, 3204 }; 3205 3206 static void fec_enet_free_buffers(struct net_device *ndev) 3207 { 3208 struct fec_enet_private *fep = netdev_priv(ndev); 3209 unsigned int i; 3210 struct sk_buff *skb; 3211 struct fec_enet_priv_tx_q *txq; 3212 struct fec_enet_priv_rx_q *rxq; 3213 unsigned int q; 3214 3215 for (q = 0; q < fep->num_rx_queues; q++) { 3216 rxq = fep->rx_queue[q]; 3217 for (i = 0; i < rxq->bd.ring_size; i++) 3218 page_pool_put_full_page(rxq->page_pool, rxq->rx_skb_info[i].page, false); 3219 3220 for (i = 0; i < XDP_STATS_TOTAL; i++) 3221 rxq->stats[i] = 0; 3222 3223 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 3224 xdp_rxq_info_unreg(&rxq->xdp_rxq); 3225 page_pool_destroy(rxq->page_pool); 3226 rxq->page_pool = NULL; 3227 } 3228 3229 for (q = 0; q < fep->num_tx_queues; q++) { 3230 txq = fep->tx_queue[q]; 3231 for (i = 0; i < txq->bd.ring_size; i++) { 3232 kfree(txq->tx_bounce[i]); 3233 txq->tx_bounce[i] = NULL; 3234 3235 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 3236 skb = txq->tx_buf[i].skb; 3237 txq->tx_buf[i].skb = NULL; 3238 dev_kfree_skb(skb); 3239 } else { 3240 if (txq->tx_buf[i].xdp) { 3241 xdp_return_frame(txq->tx_buf[i].xdp); 3242 txq->tx_buf[i].xdp = NULL; 3243 } 3244 3245 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3246 } 3247 } 3248 } 3249 } 3250 3251 static void fec_enet_free_queue(struct net_device *ndev) 3252 { 3253 struct fec_enet_private *fep = netdev_priv(ndev); 3254 int i; 3255 struct fec_enet_priv_tx_q *txq; 3256 3257 for (i = 0; i < fep->num_tx_queues; i++) 3258 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 3259 txq = fep->tx_queue[i]; 3260 dma_free_coherent(&fep->pdev->dev, 3261 txq->bd.ring_size * TSO_HEADER_SIZE, 3262 txq->tso_hdrs, 3263 txq->tso_hdrs_dma); 3264 } 3265 3266 for (i = 0; i < fep->num_rx_queues; i++) 3267 kfree(fep->rx_queue[i]); 3268 for (i = 0; i < fep->num_tx_queues; i++) 3269 kfree(fep->tx_queue[i]); 3270 } 3271 3272 static int fec_enet_alloc_queue(struct net_device *ndev) 3273 { 3274 struct fec_enet_private *fep = netdev_priv(ndev); 3275 int i; 3276 int ret = 0; 3277 struct fec_enet_priv_tx_q *txq; 3278 3279 for (i = 0; i < fep->num_tx_queues; i++) { 3280 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3281 if (!txq) { 3282 ret = -ENOMEM; 3283 goto alloc_failed; 3284 } 3285 3286 fep->tx_queue[i] = txq; 3287 txq->bd.ring_size = TX_RING_SIZE; 3288 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3289 3290 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3291 txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS; 3292 3293 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 3294 txq->bd.ring_size * TSO_HEADER_SIZE, 3295 &txq->tso_hdrs_dma, 3296 GFP_KERNEL); 3297 if (!txq->tso_hdrs) { 3298 ret = -ENOMEM; 3299 goto alloc_failed; 3300 } 3301 } 3302 3303 for (i = 0; i < fep->num_rx_queues; i++) { 3304 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3305 GFP_KERNEL); 3306 if (!fep->rx_queue[i]) { 3307 ret = -ENOMEM; 3308 goto alloc_failed; 3309 } 3310 3311 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3312 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3313 } 3314 return ret; 3315 3316 alloc_failed: 3317 fec_enet_free_queue(ndev); 3318 return ret; 3319 } 3320 3321 static int 3322 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3323 { 3324 struct fec_enet_private *fep = netdev_priv(ndev); 3325 struct fec_enet_priv_rx_q *rxq; 3326 dma_addr_t phys_addr; 3327 struct bufdesc *bdp; 3328 struct page *page; 3329 int i, err; 3330 3331 rxq = fep->rx_queue[queue]; 3332 bdp = rxq->bd.base; 3333 3334 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size); 3335 if (err < 0) { 3336 netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err); 3337 return err; 3338 } 3339 3340 for (i = 0; i < rxq->bd.ring_size; i++) { 3341 page = page_pool_dev_alloc_pages(rxq->page_pool); 3342 if (!page) 3343 goto err_alloc; 3344 3345 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM; 3346 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 3347 3348 rxq->rx_skb_info[i].page = page; 3349 rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM; 3350 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3351 3352 if (fep->bufdesc_ex) { 3353 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3354 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3355 } 3356 3357 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3358 } 3359 3360 /* Set the last buffer to wrap. */ 3361 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3362 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3363 return 0; 3364 3365 err_alloc: 3366 fec_enet_free_buffers(ndev); 3367 return -ENOMEM; 3368 } 3369 3370 static int 3371 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3372 { 3373 struct fec_enet_private *fep = netdev_priv(ndev); 3374 unsigned int i; 3375 struct bufdesc *bdp; 3376 struct fec_enet_priv_tx_q *txq; 3377 3378 txq = fep->tx_queue[queue]; 3379 bdp = txq->bd.base; 3380 for (i = 0; i < txq->bd.ring_size; i++) { 3381 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3382 if (!txq->tx_bounce[i]) 3383 goto err_alloc; 3384 3385 bdp->cbd_sc = cpu_to_fec16(0); 3386 bdp->cbd_bufaddr = cpu_to_fec32(0); 3387 3388 if (fep->bufdesc_ex) { 3389 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3390 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3391 } 3392 3393 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3394 } 3395 3396 /* Set the last buffer to wrap. */ 3397 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3398 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3399 3400 return 0; 3401 3402 err_alloc: 3403 fec_enet_free_buffers(ndev); 3404 return -ENOMEM; 3405 } 3406 3407 static int fec_enet_alloc_buffers(struct net_device *ndev) 3408 { 3409 struct fec_enet_private *fep = netdev_priv(ndev); 3410 unsigned int i; 3411 3412 for (i = 0; i < fep->num_rx_queues; i++) 3413 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3414 return -ENOMEM; 3415 3416 for (i = 0; i < fep->num_tx_queues; i++) 3417 if (fec_enet_alloc_txq_buffers(ndev, i)) 3418 return -ENOMEM; 3419 return 0; 3420 } 3421 3422 static int 3423 fec_enet_open(struct net_device *ndev) 3424 { 3425 struct fec_enet_private *fep = netdev_priv(ndev); 3426 int ret; 3427 bool reset_again; 3428 3429 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3430 if (ret < 0) 3431 return ret; 3432 3433 pinctrl_pm_select_default_state(&fep->pdev->dev); 3434 ret = fec_enet_clk_enable(ndev, true); 3435 if (ret) 3436 goto clk_enable; 3437 3438 /* During the first fec_enet_open call the PHY isn't probed at this 3439 * point. Therefore the phy_reset_after_clk_enable() call within 3440 * fec_enet_clk_enable() fails. As we need this reset in order to be 3441 * sure the PHY is working correctly we check if we need to reset again 3442 * later when the PHY is probed 3443 */ 3444 if (ndev->phydev && ndev->phydev->drv) 3445 reset_again = false; 3446 else 3447 reset_again = true; 3448 3449 /* I should reset the ring buffers here, but I don't yet know 3450 * a simple way to do that. 3451 */ 3452 3453 ret = fec_enet_alloc_buffers(ndev); 3454 if (ret) 3455 goto err_enet_alloc; 3456 3457 /* Init MAC prior to mii bus probe */ 3458 fec_restart(ndev); 3459 3460 /* Call phy_reset_after_clk_enable() again if it failed during 3461 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3462 */ 3463 if (reset_again) 3464 fec_enet_phy_reset_after_clk_enable(ndev); 3465 3466 /* Probe and connect to PHY when open the interface */ 3467 ret = fec_enet_mii_probe(ndev); 3468 if (ret) 3469 goto err_enet_mii_probe; 3470 3471 if (fep->quirks & FEC_QUIRK_ERR006687) 3472 imx6q_cpuidle_fec_irqs_used(); 3473 3474 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3475 cpu_latency_qos_add_request(&fep->pm_qos_req, 0); 3476 3477 napi_enable(&fep->napi); 3478 phy_start(ndev->phydev); 3479 netif_tx_start_all_queues(ndev); 3480 3481 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3482 FEC_WOL_FLAG_ENABLE); 3483 3484 return 0; 3485 3486 err_enet_mii_probe: 3487 fec_enet_free_buffers(ndev); 3488 err_enet_alloc: 3489 fec_enet_clk_enable(ndev, false); 3490 clk_enable: 3491 pm_runtime_mark_last_busy(&fep->pdev->dev); 3492 pm_runtime_put_autosuspend(&fep->pdev->dev); 3493 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3494 return ret; 3495 } 3496 3497 static int 3498 fec_enet_close(struct net_device *ndev) 3499 { 3500 struct fec_enet_private *fep = netdev_priv(ndev); 3501 3502 phy_stop(ndev->phydev); 3503 3504 if (netif_device_present(ndev)) { 3505 napi_disable(&fep->napi); 3506 netif_tx_disable(ndev); 3507 fec_stop(ndev); 3508 } 3509 3510 phy_disconnect(ndev->phydev); 3511 3512 if (fep->quirks & FEC_QUIRK_ERR006687) 3513 imx6q_cpuidle_fec_irqs_unused(); 3514 3515 fec_enet_update_ethtool_stats(ndev); 3516 3517 fec_enet_clk_enable(ndev, false); 3518 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3519 cpu_latency_qos_remove_request(&fep->pm_qos_req); 3520 3521 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3522 pm_runtime_mark_last_busy(&fep->pdev->dev); 3523 pm_runtime_put_autosuspend(&fep->pdev->dev); 3524 3525 fec_enet_free_buffers(ndev); 3526 3527 return 0; 3528 } 3529 3530 /* Set or clear the multicast filter for this adaptor. 3531 * Skeleton taken from sunlance driver. 3532 * The CPM Ethernet implementation allows Multicast as well as individual 3533 * MAC address filtering. Some of the drivers check to make sure it is 3534 * a group multicast address, and discard those that are not. I guess I 3535 * will do the same for now, but just remove the test if you want 3536 * individual filtering as well (do the upper net layers want or support 3537 * this kind of feature?). 3538 */ 3539 3540 #define FEC_HASH_BITS 6 /* #bits in hash */ 3541 3542 static void set_multicast_list(struct net_device *ndev) 3543 { 3544 struct fec_enet_private *fep = netdev_priv(ndev); 3545 struct netdev_hw_addr *ha; 3546 unsigned int crc, tmp; 3547 unsigned char hash; 3548 unsigned int hash_high = 0, hash_low = 0; 3549 3550 if (ndev->flags & IFF_PROMISC) { 3551 tmp = readl(fep->hwp + FEC_R_CNTRL); 3552 tmp |= 0x8; 3553 writel(tmp, fep->hwp + FEC_R_CNTRL); 3554 return; 3555 } 3556 3557 tmp = readl(fep->hwp + FEC_R_CNTRL); 3558 tmp &= ~0x8; 3559 writel(tmp, fep->hwp + FEC_R_CNTRL); 3560 3561 if (ndev->flags & IFF_ALLMULTI) { 3562 /* Catch all multicast addresses, so set the 3563 * filter to all 1's 3564 */ 3565 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3566 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3567 3568 return; 3569 } 3570 3571 /* Add the addresses in hash register */ 3572 netdev_for_each_mc_addr(ha, ndev) { 3573 /* calculate crc32 value of mac address */ 3574 crc = ether_crc_le(ndev->addr_len, ha->addr); 3575 3576 /* only upper 6 bits (FEC_HASH_BITS) are used 3577 * which point to specific bit in the hash registers 3578 */ 3579 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3580 3581 if (hash > 31) 3582 hash_high |= 1 << (hash - 32); 3583 else 3584 hash_low |= 1 << hash; 3585 } 3586 3587 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3588 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3589 } 3590 3591 /* Set a MAC change in hardware. */ 3592 static int 3593 fec_set_mac_address(struct net_device *ndev, void *p) 3594 { 3595 struct fec_enet_private *fep = netdev_priv(ndev); 3596 struct sockaddr *addr = p; 3597 3598 if (addr) { 3599 if (!is_valid_ether_addr(addr->sa_data)) 3600 return -EADDRNOTAVAIL; 3601 eth_hw_addr_set(ndev, addr->sa_data); 3602 } 3603 3604 /* Add netif status check here to avoid system hang in below case: 3605 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3606 * After ethx down, fec all clocks are gated off and then register 3607 * access causes system hang. 3608 */ 3609 if (!netif_running(ndev)) 3610 return 0; 3611 3612 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3613 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3614 fep->hwp + FEC_ADDR_LOW); 3615 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3616 fep->hwp + FEC_ADDR_HIGH); 3617 return 0; 3618 } 3619 3620 #ifdef CONFIG_NET_POLL_CONTROLLER 3621 /** 3622 * fec_poll_controller - FEC Poll controller function 3623 * @dev: The FEC network adapter 3624 * 3625 * Polled functionality used by netconsole and others in non interrupt mode 3626 * 3627 */ 3628 static void fec_poll_controller(struct net_device *dev) 3629 { 3630 int i; 3631 struct fec_enet_private *fep = netdev_priv(dev); 3632 3633 for (i = 0; i < FEC_IRQ_NUM; i++) { 3634 if (fep->irq[i] > 0) { 3635 disable_irq(fep->irq[i]); 3636 fec_enet_interrupt(fep->irq[i], dev); 3637 enable_irq(fep->irq[i]); 3638 } 3639 } 3640 } 3641 #endif 3642 3643 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3644 netdev_features_t features) 3645 { 3646 struct fec_enet_private *fep = netdev_priv(netdev); 3647 netdev_features_t changed = features ^ netdev->features; 3648 3649 netdev->features = features; 3650 3651 /* Receive checksum has been changed */ 3652 if (changed & NETIF_F_RXCSUM) { 3653 if (features & NETIF_F_RXCSUM) 3654 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3655 else 3656 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3657 } 3658 } 3659 3660 static int fec_set_features(struct net_device *netdev, 3661 netdev_features_t features) 3662 { 3663 struct fec_enet_private *fep = netdev_priv(netdev); 3664 netdev_features_t changed = features ^ netdev->features; 3665 3666 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3667 napi_disable(&fep->napi); 3668 netif_tx_lock_bh(netdev); 3669 fec_stop(netdev); 3670 fec_enet_set_netdev_features(netdev, features); 3671 fec_restart(netdev); 3672 netif_tx_wake_all_queues(netdev); 3673 netif_tx_unlock_bh(netdev); 3674 napi_enable(&fep->napi); 3675 } else { 3676 fec_enet_set_netdev_features(netdev, features); 3677 } 3678 3679 return 0; 3680 } 3681 3682 static u16 fec_enet_get_raw_vlan_tci(struct sk_buff *skb) 3683 { 3684 struct vlan_ethhdr *vhdr; 3685 unsigned short vlan_TCI = 0; 3686 3687 if (skb->protocol == htons(ETH_P_ALL)) { 3688 vhdr = (struct vlan_ethhdr *)(skb->data); 3689 vlan_TCI = ntohs(vhdr->h_vlan_TCI); 3690 } 3691 3692 return vlan_TCI; 3693 } 3694 3695 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3696 struct net_device *sb_dev) 3697 { 3698 struct fec_enet_private *fep = netdev_priv(ndev); 3699 u16 vlan_tag; 3700 3701 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3702 return netdev_pick_tx(ndev, skb, NULL); 3703 3704 vlan_tag = fec_enet_get_raw_vlan_tci(skb); 3705 if (!vlan_tag) 3706 return vlan_tag; 3707 3708 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3709 } 3710 3711 static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf) 3712 { 3713 struct fec_enet_private *fep = netdev_priv(dev); 3714 bool is_run = netif_running(dev); 3715 struct bpf_prog *old_prog; 3716 3717 switch (bpf->command) { 3718 case XDP_SETUP_PROG: 3719 /* No need to support the SoCs that require to 3720 * do the frame swap because the performance wouldn't be 3721 * better than the skb mode. 3722 */ 3723 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 3724 return -EOPNOTSUPP; 3725 3726 if (!bpf->prog) 3727 xdp_features_clear_redirect_target(dev); 3728 3729 if (is_run) { 3730 napi_disable(&fep->napi); 3731 netif_tx_disable(dev); 3732 } 3733 3734 old_prog = xchg(&fep->xdp_prog, bpf->prog); 3735 if (old_prog) 3736 bpf_prog_put(old_prog); 3737 3738 fec_restart(dev); 3739 3740 if (is_run) { 3741 napi_enable(&fep->napi); 3742 netif_tx_start_all_queues(dev); 3743 } 3744 3745 if (bpf->prog) 3746 xdp_features_set_redirect_target(dev, false); 3747 3748 return 0; 3749 3750 case XDP_SETUP_XSK_POOL: 3751 return -EOPNOTSUPP; 3752 3753 default: 3754 return -EOPNOTSUPP; 3755 } 3756 } 3757 3758 static int 3759 fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index) 3760 { 3761 if (unlikely(index < 0)) 3762 return 0; 3763 3764 return (index % fep->num_tx_queues); 3765 } 3766 3767 static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep, 3768 struct fec_enet_priv_tx_q *txq, 3769 struct xdp_frame *frame) 3770 { 3771 unsigned int index, status, estatus; 3772 struct bufdesc *bdp; 3773 dma_addr_t dma_addr; 3774 int entries_free; 3775 3776 entries_free = fec_enet_get_free_txdesc_num(txq); 3777 if (entries_free < MAX_SKB_FRAGS + 1) { 3778 netdev_err_once(fep->netdev, "NOT enough BD for SG!\n"); 3779 return -EBUSY; 3780 } 3781 3782 /* Fill in a Tx ring entry */ 3783 bdp = txq->bd.cur; 3784 status = fec16_to_cpu(bdp->cbd_sc); 3785 status &= ~BD_ENET_TX_STATS; 3786 3787 index = fec_enet_get_bd_index(bdp, &txq->bd); 3788 3789 dma_addr = dma_map_single(&fep->pdev->dev, frame->data, 3790 frame->len, DMA_TO_DEVICE); 3791 if (dma_mapping_error(&fep->pdev->dev, dma_addr)) 3792 return -ENOMEM; 3793 3794 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 3795 if (fep->bufdesc_ex) 3796 estatus = BD_ENET_TX_INT; 3797 3798 bdp->cbd_bufaddr = cpu_to_fec32(dma_addr); 3799 bdp->cbd_datlen = cpu_to_fec16(frame->len); 3800 3801 if (fep->bufdesc_ex) { 3802 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3803 3804 if (fep->quirks & FEC_QUIRK_HAS_AVB) 3805 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 3806 3807 ebdp->cbd_bdu = 0; 3808 ebdp->cbd_esc = cpu_to_fec32(estatus); 3809 } 3810 3811 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO; 3812 txq->tx_buf[index].xdp = frame; 3813 3814 /* Make sure the updates to rest of the descriptor are performed before 3815 * transferring ownership. 3816 */ 3817 dma_wmb(); 3818 3819 /* Send it on its way. Tell FEC it's ready, interrupt when done, 3820 * it's the last BD of the frame, and to put the CRC on the end. 3821 */ 3822 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 3823 bdp->cbd_sc = cpu_to_fec16(status); 3824 3825 /* If this was the last BD in the ring, start at the beginning again. */ 3826 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3827 3828 /* Make sure the update to bdp are performed before txq->bd.cur. */ 3829 dma_wmb(); 3830 3831 txq->bd.cur = bdp; 3832 3833 /* Trigger transmission start */ 3834 writel(0, txq->bd.reg_desc_active); 3835 3836 return 0; 3837 } 3838 3839 static int fec_enet_xdp_xmit(struct net_device *dev, 3840 int num_frames, 3841 struct xdp_frame **frames, 3842 u32 flags) 3843 { 3844 struct fec_enet_private *fep = netdev_priv(dev); 3845 struct fec_enet_priv_tx_q *txq; 3846 int cpu = smp_processor_id(); 3847 unsigned int sent_frames = 0; 3848 struct netdev_queue *nq; 3849 unsigned int queue; 3850 int i; 3851 3852 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3853 txq = fep->tx_queue[queue]; 3854 nq = netdev_get_tx_queue(fep->netdev, queue); 3855 3856 __netif_tx_lock(nq, cpu); 3857 3858 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3859 txq_trans_cond_update(nq); 3860 for (i = 0; i < num_frames; i++) { 3861 if (fec_enet_txq_xmit_frame(fep, txq, frames[i]) < 0) 3862 break; 3863 sent_frames++; 3864 } 3865 3866 __netif_tx_unlock(nq); 3867 3868 return sent_frames; 3869 } 3870 3871 static int fec_hwtstamp_get(struct net_device *ndev, 3872 struct kernel_hwtstamp_config *config) 3873 { 3874 struct fec_enet_private *fep = netdev_priv(ndev); 3875 struct phy_device *phydev = ndev->phydev; 3876 3877 if (phy_has_hwtstamp(phydev)) 3878 return phy_mii_ioctl(phydev, config->ifr, SIOCGHWTSTAMP); 3879 3880 if (!netif_running(ndev)) 3881 return -EINVAL; 3882 3883 if (!fep->bufdesc_ex) 3884 return -EOPNOTSUPP; 3885 3886 fec_ptp_get(ndev, config); 3887 3888 return 0; 3889 } 3890 3891 static int fec_hwtstamp_set(struct net_device *ndev, 3892 struct kernel_hwtstamp_config *config, 3893 struct netlink_ext_ack *extack) 3894 { 3895 struct fec_enet_private *fep = netdev_priv(ndev); 3896 struct phy_device *phydev = ndev->phydev; 3897 3898 if (phy_has_hwtstamp(phydev)) 3899 return phy_mii_ioctl(phydev, config->ifr, SIOCSHWTSTAMP); 3900 3901 if (!netif_running(ndev)) 3902 return -EINVAL; 3903 3904 if (!fep->bufdesc_ex) 3905 return -EOPNOTSUPP; 3906 3907 return fec_ptp_set(ndev, config, extack); 3908 } 3909 3910 static const struct net_device_ops fec_netdev_ops = { 3911 .ndo_open = fec_enet_open, 3912 .ndo_stop = fec_enet_close, 3913 .ndo_start_xmit = fec_enet_start_xmit, 3914 .ndo_select_queue = fec_enet_select_queue, 3915 .ndo_set_rx_mode = set_multicast_list, 3916 .ndo_validate_addr = eth_validate_addr, 3917 .ndo_tx_timeout = fec_timeout, 3918 .ndo_set_mac_address = fec_set_mac_address, 3919 .ndo_eth_ioctl = phy_do_ioctl_running, 3920 #ifdef CONFIG_NET_POLL_CONTROLLER 3921 .ndo_poll_controller = fec_poll_controller, 3922 #endif 3923 .ndo_set_features = fec_set_features, 3924 .ndo_bpf = fec_enet_bpf, 3925 .ndo_xdp_xmit = fec_enet_xdp_xmit, 3926 .ndo_hwtstamp_get = fec_hwtstamp_get, 3927 .ndo_hwtstamp_set = fec_hwtstamp_set, 3928 }; 3929 3930 static const unsigned short offset_des_active_rxq[] = { 3931 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3932 }; 3933 3934 static const unsigned short offset_des_active_txq[] = { 3935 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3936 }; 3937 3938 /* 3939 * XXX: We need to clean up on failure exits here. 3940 * 3941 */ 3942 static int fec_enet_init(struct net_device *ndev) 3943 { 3944 struct fec_enet_private *fep = netdev_priv(ndev); 3945 struct bufdesc *cbd_base; 3946 dma_addr_t bd_dma; 3947 int bd_size; 3948 unsigned int i; 3949 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3950 sizeof(struct bufdesc); 3951 unsigned dsize_log2 = __fls(dsize); 3952 int ret; 3953 3954 WARN_ON(dsize != (1 << dsize_log2)); 3955 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 3956 fep->rx_align = 0xf; 3957 fep->tx_align = 0xf; 3958 #else 3959 fep->rx_align = 0x3; 3960 fep->tx_align = 0x3; 3961 #endif 3962 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 3963 fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 3964 fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT; 3965 fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT; 3966 3967 /* Check mask of the streaming and coherent API */ 3968 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 3969 if (ret < 0) { 3970 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 3971 return ret; 3972 } 3973 3974 ret = fec_enet_alloc_queue(ndev); 3975 if (ret) 3976 return ret; 3977 3978 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3979 3980 /* Allocate memory for buffer descriptors. */ 3981 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3982 GFP_KERNEL); 3983 if (!cbd_base) { 3984 ret = -ENOMEM; 3985 goto free_queue_mem; 3986 } 3987 3988 /* Get the Ethernet address */ 3989 ret = fec_get_mac(ndev); 3990 if (ret) 3991 goto free_queue_mem; 3992 3993 /* Set receive and transmit descriptor base. */ 3994 for (i = 0; i < fep->num_rx_queues; i++) { 3995 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3996 unsigned size = dsize * rxq->bd.ring_size; 3997 3998 rxq->bd.qid = i; 3999 rxq->bd.base = cbd_base; 4000 rxq->bd.cur = cbd_base; 4001 rxq->bd.dma = bd_dma; 4002 rxq->bd.dsize = dsize; 4003 rxq->bd.dsize_log2 = dsize_log2; 4004 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 4005 bd_dma += size; 4006 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4007 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4008 } 4009 4010 for (i = 0; i < fep->num_tx_queues; i++) { 4011 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 4012 unsigned size = dsize * txq->bd.ring_size; 4013 4014 txq->bd.qid = i; 4015 txq->bd.base = cbd_base; 4016 txq->bd.cur = cbd_base; 4017 txq->bd.dma = bd_dma; 4018 txq->bd.dsize = dsize; 4019 txq->bd.dsize_log2 = dsize_log2; 4020 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 4021 bd_dma += size; 4022 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4023 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4024 } 4025 4026 4027 /* The FEC Ethernet specific entries in the device structure */ 4028 ndev->watchdog_timeo = TX_TIMEOUT; 4029 ndev->netdev_ops = &fec_netdev_ops; 4030 ndev->ethtool_ops = &fec_enet_ethtool_ops; 4031 4032 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 4033 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi); 4034 4035 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 4036 /* enable hw VLAN support */ 4037 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 4038 4039 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 4040 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS); 4041 4042 /* enable hw accelerator */ 4043 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 4044 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 4045 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 4046 } 4047 4048 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 4049 fep->tx_align = 0; 4050 fep->rx_align = 0x3f; 4051 } 4052 4053 ndev->hw_features = ndev->features; 4054 4055 if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME)) 4056 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 4057 NETDEV_XDP_ACT_REDIRECT; 4058 4059 fec_restart(ndev); 4060 4061 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 4062 fec_enet_clear_ethtool_stats(ndev); 4063 else 4064 fec_enet_update_ethtool_stats(ndev); 4065 4066 return 0; 4067 4068 free_queue_mem: 4069 fec_enet_free_queue(ndev); 4070 return ret; 4071 } 4072 4073 #ifdef CONFIG_OF 4074 static int fec_reset_phy(struct platform_device *pdev) 4075 { 4076 struct gpio_desc *phy_reset; 4077 int msec = 1, phy_post_delay = 0; 4078 struct device_node *np = pdev->dev.of_node; 4079 int err; 4080 4081 if (!np) 4082 return 0; 4083 4084 err = of_property_read_u32(np, "phy-reset-duration", &msec); 4085 /* A sane reset duration should not be longer than 1s */ 4086 if (!err && msec > 1000) 4087 msec = 1; 4088 4089 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 4090 /* valid reset duration should be less than 1s */ 4091 if (!err && phy_post_delay > 1000) 4092 return -EINVAL; 4093 4094 phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset", 4095 GPIOD_OUT_HIGH); 4096 if (IS_ERR(phy_reset)) 4097 return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset), 4098 "failed to get phy-reset-gpios\n"); 4099 4100 if (!phy_reset) 4101 return 0; 4102 4103 if (msec > 20) 4104 msleep(msec); 4105 else 4106 usleep_range(msec * 1000, msec * 1000 + 1000); 4107 4108 gpiod_set_value_cansleep(phy_reset, 0); 4109 4110 if (!phy_post_delay) 4111 return 0; 4112 4113 if (phy_post_delay > 20) 4114 msleep(phy_post_delay); 4115 else 4116 usleep_range(phy_post_delay * 1000, 4117 phy_post_delay * 1000 + 1000); 4118 4119 return 0; 4120 } 4121 #else /* CONFIG_OF */ 4122 static int fec_reset_phy(struct platform_device *pdev) 4123 { 4124 /* 4125 * In case of platform probe, the reset has been done 4126 * by machine code. 4127 */ 4128 return 0; 4129 } 4130 #endif /* CONFIG_OF */ 4131 4132 static void 4133 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 4134 { 4135 struct device_node *np = pdev->dev.of_node; 4136 4137 *num_tx = *num_rx = 1; 4138 4139 if (!np || !of_device_is_available(np)) 4140 return; 4141 4142 /* parse the num of tx and rx queues */ 4143 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 4144 4145 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 4146 4147 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 4148 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 4149 *num_tx); 4150 *num_tx = 1; 4151 return; 4152 } 4153 4154 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 4155 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 4156 *num_rx); 4157 *num_rx = 1; 4158 return; 4159 } 4160 4161 } 4162 4163 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 4164 { 4165 int irq_cnt = platform_irq_count(pdev); 4166 4167 if (irq_cnt > FEC_IRQ_NUM) 4168 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 4169 else if (irq_cnt == 2) 4170 irq_cnt = 1; /* last for pps */ 4171 else if (irq_cnt <= 0) 4172 irq_cnt = 1; /* At least 1 irq is needed */ 4173 return irq_cnt; 4174 } 4175 4176 static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 4177 { 4178 struct net_device *ndev = platform_get_drvdata(pdev); 4179 struct fec_enet_private *fep = netdev_priv(ndev); 4180 4181 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 4182 fep->wake_irq = fep->irq[2]; 4183 else 4184 fep->wake_irq = fep->irq[0]; 4185 } 4186 4187 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 4188 struct device_node *np) 4189 { 4190 struct device_node *gpr_np; 4191 u32 out_val[3]; 4192 int ret = 0; 4193 4194 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 4195 if (!gpr_np) 4196 return 0; 4197 4198 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 4199 ARRAY_SIZE(out_val)); 4200 if (ret) { 4201 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 4202 goto out; 4203 } 4204 4205 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 4206 if (IS_ERR(fep->stop_gpr.gpr)) { 4207 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 4208 ret = PTR_ERR(fep->stop_gpr.gpr); 4209 fep->stop_gpr.gpr = NULL; 4210 goto out; 4211 } 4212 4213 fep->stop_gpr.reg = out_val[1]; 4214 fep->stop_gpr.bit = out_val[2]; 4215 4216 out: 4217 of_node_put(gpr_np); 4218 4219 return ret; 4220 } 4221 4222 static int 4223 fec_probe(struct platform_device *pdev) 4224 { 4225 struct fec_enet_private *fep; 4226 struct fec_platform_data *pdata; 4227 phy_interface_t interface; 4228 struct net_device *ndev; 4229 int i, irq, ret = 0; 4230 const struct of_device_id *of_id; 4231 static int dev_id; 4232 struct device_node *np = pdev->dev.of_node, *phy_node; 4233 int num_tx_qs; 4234 int num_rx_qs; 4235 char irq_name[8]; 4236 int irq_cnt; 4237 struct fec_devinfo *dev_info; 4238 4239 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 4240 4241 /* Init network device */ 4242 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 4243 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 4244 if (!ndev) 4245 return -ENOMEM; 4246 4247 SET_NETDEV_DEV(ndev, &pdev->dev); 4248 4249 /* setup board info structure */ 4250 fep = netdev_priv(ndev); 4251 4252 of_id = of_match_device(fec_dt_ids, &pdev->dev); 4253 if (of_id) 4254 pdev->id_entry = of_id->data; 4255 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; 4256 if (dev_info) 4257 fep->quirks = dev_info->quirks; 4258 4259 fep->netdev = ndev; 4260 fep->num_rx_queues = num_rx_qs; 4261 fep->num_tx_queues = num_tx_qs; 4262 4263 #if !defined(CONFIG_M5272) 4264 /* default enable pause frame auto negotiation */ 4265 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 4266 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 4267 #endif 4268 4269 /* Select default pin state */ 4270 pinctrl_pm_select_default_state(&pdev->dev); 4271 4272 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 4273 if (IS_ERR(fep->hwp)) { 4274 ret = PTR_ERR(fep->hwp); 4275 goto failed_ioremap; 4276 } 4277 4278 fep->pdev = pdev; 4279 fep->dev_id = dev_id++; 4280 4281 platform_set_drvdata(pdev, ndev); 4282 4283 if ((of_machine_is_compatible("fsl,imx6q") || 4284 of_machine_is_compatible("fsl,imx6dl")) && 4285 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 4286 fep->quirks |= FEC_QUIRK_ERR006687; 4287 4288 ret = fec_enet_ipc_handle_init(fep); 4289 if (ret) 4290 goto failed_ipc_init; 4291 4292 if (of_property_read_bool(np, "fsl,magic-packet")) 4293 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 4294 4295 ret = fec_enet_init_stop_mode(fep, np); 4296 if (ret) 4297 goto failed_stop_mode; 4298 4299 phy_node = of_parse_phandle(np, "phy-handle", 0); 4300 if (!phy_node && of_phy_is_fixed_link(np)) { 4301 ret = of_phy_register_fixed_link(np); 4302 if (ret < 0) { 4303 dev_err(&pdev->dev, 4304 "broken fixed-link specification\n"); 4305 goto failed_phy; 4306 } 4307 phy_node = of_node_get(np); 4308 } 4309 fep->phy_node = phy_node; 4310 4311 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 4312 if (ret) { 4313 pdata = dev_get_platdata(&pdev->dev); 4314 if (pdata) 4315 fep->phy_interface = pdata->phy; 4316 else 4317 fep->phy_interface = PHY_INTERFACE_MODE_MII; 4318 } else { 4319 fep->phy_interface = interface; 4320 } 4321 4322 ret = fec_enet_parse_rgmii_delay(fep, np); 4323 if (ret) 4324 goto failed_rgmii_delay; 4325 4326 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 4327 if (IS_ERR(fep->clk_ipg)) { 4328 ret = PTR_ERR(fep->clk_ipg); 4329 goto failed_clk; 4330 } 4331 4332 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 4333 if (IS_ERR(fep->clk_ahb)) { 4334 ret = PTR_ERR(fep->clk_ahb); 4335 goto failed_clk; 4336 } 4337 4338 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 4339 4340 /* enet_out is optional, depends on board */ 4341 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out"); 4342 if (IS_ERR(fep->clk_enet_out)) { 4343 ret = PTR_ERR(fep->clk_enet_out); 4344 goto failed_clk; 4345 } 4346 4347 fep->ptp_clk_on = false; 4348 mutex_init(&fep->ptp_clk_mutex); 4349 4350 /* clk_ref is optional, depends on board */ 4351 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref"); 4352 if (IS_ERR(fep->clk_ref)) { 4353 ret = PTR_ERR(fep->clk_ref); 4354 goto failed_clk; 4355 } 4356 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 4357 4358 /* clk_2x_txclk is optional, depends on board */ 4359 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 4360 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 4361 if (IS_ERR(fep->clk_2x_txclk)) 4362 fep->clk_2x_txclk = NULL; 4363 } 4364 4365 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 4366 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 4367 if (IS_ERR(fep->clk_ptp)) { 4368 fep->clk_ptp = NULL; 4369 fep->bufdesc_ex = false; 4370 } 4371 4372 ret = fec_enet_clk_enable(ndev, true); 4373 if (ret) 4374 goto failed_clk; 4375 4376 ret = clk_prepare_enable(fep->clk_ipg); 4377 if (ret) 4378 goto failed_clk_ipg; 4379 ret = clk_prepare_enable(fep->clk_ahb); 4380 if (ret) 4381 goto failed_clk_ahb; 4382 4383 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 4384 if (!IS_ERR(fep->reg_phy)) { 4385 ret = regulator_enable(fep->reg_phy); 4386 if (ret) { 4387 dev_err(&pdev->dev, 4388 "Failed to enable phy regulator: %d\n", ret); 4389 goto failed_regulator; 4390 } 4391 } else { 4392 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 4393 ret = -EPROBE_DEFER; 4394 goto failed_regulator; 4395 } 4396 fep->reg_phy = NULL; 4397 } 4398 4399 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 4400 pm_runtime_use_autosuspend(&pdev->dev); 4401 pm_runtime_get_noresume(&pdev->dev); 4402 pm_runtime_set_active(&pdev->dev); 4403 pm_runtime_enable(&pdev->dev); 4404 4405 ret = fec_reset_phy(pdev); 4406 if (ret) 4407 goto failed_reset; 4408 4409 irq_cnt = fec_enet_get_irq_cnt(pdev); 4410 if (fep->bufdesc_ex) 4411 fec_ptp_init(pdev, irq_cnt); 4412 4413 ret = fec_enet_init(ndev); 4414 if (ret) 4415 goto failed_init; 4416 4417 for (i = 0; i < irq_cnt; i++) { 4418 snprintf(irq_name, sizeof(irq_name), "int%d", i); 4419 irq = platform_get_irq_byname_optional(pdev, irq_name); 4420 if (irq < 0) 4421 irq = platform_get_irq(pdev, i); 4422 if (irq < 0) { 4423 ret = irq; 4424 goto failed_irq; 4425 } 4426 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 4427 0, pdev->name, ndev); 4428 if (ret) 4429 goto failed_irq; 4430 4431 fep->irq[i] = irq; 4432 } 4433 4434 /* Decide which interrupt line is wakeup capable */ 4435 fec_enet_get_wakeup_irq(pdev); 4436 4437 ret = fec_enet_mii_init(pdev); 4438 if (ret) 4439 goto failed_mii_init; 4440 4441 /* Carrier starts down, phylib will bring it up */ 4442 netif_carrier_off(ndev); 4443 fec_enet_clk_enable(ndev, false); 4444 pinctrl_pm_select_sleep_state(&pdev->dev); 4445 4446 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN; 4447 4448 ret = register_netdev(ndev); 4449 if (ret) 4450 goto failed_register; 4451 4452 device_init_wakeup(&ndev->dev, fep->wol_flag & 4453 FEC_WOL_HAS_MAGIC_PACKET); 4454 4455 if (fep->bufdesc_ex && fep->ptp_clock) 4456 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 4457 4458 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 4459 4460 pm_runtime_mark_last_busy(&pdev->dev); 4461 pm_runtime_put_autosuspend(&pdev->dev); 4462 4463 return 0; 4464 4465 failed_register: 4466 fec_enet_mii_remove(fep); 4467 failed_mii_init: 4468 failed_irq: 4469 failed_init: 4470 fec_ptp_stop(pdev); 4471 failed_reset: 4472 pm_runtime_put_noidle(&pdev->dev); 4473 pm_runtime_disable(&pdev->dev); 4474 if (fep->reg_phy) 4475 regulator_disable(fep->reg_phy); 4476 failed_regulator: 4477 clk_disable_unprepare(fep->clk_ahb); 4478 failed_clk_ahb: 4479 clk_disable_unprepare(fep->clk_ipg); 4480 failed_clk_ipg: 4481 fec_enet_clk_enable(ndev, false); 4482 failed_clk: 4483 failed_rgmii_delay: 4484 if (of_phy_is_fixed_link(np)) 4485 of_phy_deregister_fixed_link(np); 4486 of_node_put(phy_node); 4487 failed_stop_mode: 4488 failed_ipc_init: 4489 failed_phy: 4490 dev_id--; 4491 failed_ioremap: 4492 free_netdev(ndev); 4493 4494 return ret; 4495 } 4496 4497 static void 4498 fec_drv_remove(struct platform_device *pdev) 4499 { 4500 struct net_device *ndev = platform_get_drvdata(pdev); 4501 struct fec_enet_private *fep = netdev_priv(ndev); 4502 struct device_node *np = pdev->dev.of_node; 4503 int ret; 4504 4505 ret = pm_runtime_get_sync(&pdev->dev); 4506 if (ret < 0) 4507 dev_err(&pdev->dev, 4508 "Failed to resume device in remove callback (%pe)\n", 4509 ERR_PTR(ret)); 4510 4511 cancel_work_sync(&fep->tx_timeout_work); 4512 fec_ptp_stop(pdev); 4513 unregister_netdev(ndev); 4514 fec_enet_mii_remove(fep); 4515 if (fep->reg_phy) 4516 regulator_disable(fep->reg_phy); 4517 4518 if (of_phy_is_fixed_link(np)) 4519 of_phy_deregister_fixed_link(np); 4520 of_node_put(fep->phy_node); 4521 4522 /* After pm_runtime_get_sync() failed, the clks are still off, so skip 4523 * disabling them again. 4524 */ 4525 if (ret >= 0) { 4526 clk_disable_unprepare(fep->clk_ahb); 4527 clk_disable_unprepare(fep->clk_ipg); 4528 } 4529 pm_runtime_put_noidle(&pdev->dev); 4530 pm_runtime_disable(&pdev->dev); 4531 4532 free_netdev(ndev); 4533 } 4534 4535 static int __maybe_unused fec_suspend(struct device *dev) 4536 { 4537 struct net_device *ndev = dev_get_drvdata(dev); 4538 struct fec_enet_private *fep = netdev_priv(ndev); 4539 int ret; 4540 4541 rtnl_lock(); 4542 if (netif_running(ndev)) { 4543 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4544 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4545 phy_stop(ndev->phydev); 4546 napi_disable(&fep->napi); 4547 netif_tx_lock_bh(ndev); 4548 netif_device_detach(ndev); 4549 netif_tx_unlock_bh(ndev); 4550 fec_stop(ndev); 4551 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4552 fec_irqs_disable(ndev); 4553 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4554 } else { 4555 fec_irqs_disable_except_wakeup(ndev); 4556 if (fep->wake_irq > 0) { 4557 disable_irq(fep->wake_irq); 4558 enable_irq_wake(fep->wake_irq); 4559 } 4560 fec_enet_stop_mode(fep, true); 4561 } 4562 /* It's safe to disable clocks since interrupts are masked */ 4563 fec_enet_clk_enable(ndev, false); 4564 4565 fep->rpm_active = !pm_runtime_status_suspended(dev); 4566 if (fep->rpm_active) { 4567 ret = pm_runtime_force_suspend(dev); 4568 if (ret < 0) { 4569 rtnl_unlock(); 4570 return ret; 4571 } 4572 } 4573 } 4574 rtnl_unlock(); 4575 4576 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4577 regulator_disable(fep->reg_phy); 4578 4579 /* SOC supply clock to phy, when clock is disabled, phy link down 4580 * SOC control phy regulator, when regulator is disabled, phy link down 4581 */ 4582 if (fep->clk_enet_out || fep->reg_phy) 4583 fep->link = 0; 4584 4585 return 0; 4586 } 4587 4588 static int __maybe_unused fec_resume(struct device *dev) 4589 { 4590 struct net_device *ndev = dev_get_drvdata(dev); 4591 struct fec_enet_private *fep = netdev_priv(ndev); 4592 int ret; 4593 int val; 4594 4595 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4596 ret = regulator_enable(fep->reg_phy); 4597 if (ret) 4598 return ret; 4599 } 4600 4601 rtnl_lock(); 4602 if (netif_running(ndev)) { 4603 if (fep->rpm_active) 4604 pm_runtime_force_resume(dev); 4605 4606 ret = fec_enet_clk_enable(ndev, true); 4607 if (ret) { 4608 rtnl_unlock(); 4609 goto failed_clk; 4610 } 4611 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4612 fec_enet_stop_mode(fep, false); 4613 if (fep->wake_irq) { 4614 disable_irq_wake(fep->wake_irq); 4615 enable_irq(fep->wake_irq); 4616 } 4617 4618 val = readl(fep->hwp + FEC_ECNTRL); 4619 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4620 writel(val, fep->hwp + FEC_ECNTRL); 4621 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4622 } else { 4623 pinctrl_pm_select_default_state(&fep->pdev->dev); 4624 } 4625 fec_restart(ndev); 4626 netif_tx_lock_bh(ndev); 4627 netif_device_attach(ndev); 4628 netif_tx_unlock_bh(ndev); 4629 napi_enable(&fep->napi); 4630 phy_init_hw(ndev->phydev); 4631 phy_start(ndev->phydev); 4632 } 4633 rtnl_unlock(); 4634 4635 return 0; 4636 4637 failed_clk: 4638 if (fep->reg_phy) 4639 regulator_disable(fep->reg_phy); 4640 return ret; 4641 } 4642 4643 static int __maybe_unused fec_runtime_suspend(struct device *dev) 4644 { 4645 struct net_device *ndev = dev_get_drvdata(dev); 4646 struct fec_enet_private *fep = netdev_priv(ndev); 4647 4648 clk_disable_unprepare(fep->clk_ahb); 4649 clk_disable_unprepare(fep->clk_ipg); 4650 4651 return 0; 4652 } 4653 4654 static int __maybe_unused fec_runtime_resume(struct device *dev) 4655 { 4656 struct net_device *ndev = dev_get_drvdata(dev); 4657 struct fec_enet_private *fep = netdev_priv(ndev); 4658 int ret; 4659 4660 ret = clk_prepare_enable(fep->clk_ahb); 4661 if (ret) 4662 return ret; 4663 ret = clk_prepare_enable(fep->clk_ipg); 4664 if (ret) 4665 goto failed_clk_ipg; 4666 4667 return 0; 4668 4669 failed_clk_ipg: 4670 clk_disable_unprepare(fep->clk_ahb); 4671 return ret; 4672 } 4673 4674 static const struct dev_pm_ops fec_pm_ops = { 4675 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4676 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4677 }; 4678 4679 static struct platform_driver fec_driver = { 4680 .driver = { 4681 .name = DRIVER_NAME, 4682 .pm = &fec_pm_ops, 4683 .of_match_table = fec_dt_ids, 4684 .suppress_bind_attrs = true, 4685 }, 4686 .id_table = fec_devtype, 4687 .probe = fec_probe, 4688 .remove_new = fec_drv_remove, 4689 }; 4690 4691 module_platform_driver(fec_driver); 4692 4693 MODULE_LICENSE("GPL"); 4694