1 /* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 * 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/string.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/ptrace.h> 29 #include <linux/errno.h> 30 #include <linux/ioport.h> 31 #include <linux/slab.h> 32 #include <linux/interrupt.h> 33 #include <linux/delay.h> 34 #include <linux/netdevice.h> 35 #include <linux/etherdevice.h> 36 #include <linux/skbuff.h> 37 #include <linux/in.h> 38 #include <linux/ip.h> 39 #include <net/ip.h> 40 #include <net/tso.h> 41 #include <linux/tcp.h> 42 #include <linux/udp.h> 43 #include <linux/icmp.h> 44 #include <linux/spinlock.h> 45 #include <linux/workqueue.h> 46 #include <linux/bitops.h> 47 #include <linux/io.h> 48 #include <linux/irq.h> 49 #include <linux/clk.h> 50 #include <linux/platform_device.h> 51 #include <linux/mdio.h> 52 #include <linux/phy.h> 53 #include <linux/fec.h> 54 #include <linux/of.h> 55 #include <linux/of_device.h> 56 #include <linux/of_gpio.h> 57 #include <linux/of_mdio.h> 58 #include <linux/of_net.h> 59 #include <linux/regulator/consumer.h> 60 #include <linux/if_vlan.h> 61 #include <linux/pinctrl/consumer.h> 62 #include <linux/prefetch.h> 63 #include <soc/imx/cpuidle.h> 64 65 #include <asm/cacheflush.h> 66 67 #include "fec.h" 68 69 static void set_multicast_list(struct net_device *ndev); 70 static void fec_enet_itr_coal_init(struct net_device *ndev); 71 72 #define DRIVER_NAME "fec" 73 74 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0)) 75 76 /* Pause frame feild and FIFO threshold */ 77 #define FEC_ENET_FCE (1 << 5) 78 #define FEC_ENET_RSEM_V 0x84 79 #define FEC_ENET_RSFL_V 16 80 #define FEC_ENET_RAEM_V 0x8 81 #define FEC_ENET_RAFL_V 0x8 82 #define FEC_ENET_OPD_V 0xFFF0 83 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 84 85 static struct platform_device_id fec_devtype[] = { 86 { 87 /* keep it for coldfire */ 88 .name = DRIVER_NAME, 89 .driver_data = 0, 90 }, { 91 .name = "imx25-fec", 92 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR, 93 }, { 94 .name = "imx27-fec", 95 .driver_data = FEC_QUIRK_MIB_CLEAR, 96 }, { 97 .name = "imx28-fec", 98 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 99 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC, 100 }, { 101 .name = "imx6q-fec", 102 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 103 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 104 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 105 FEC_QUIRK_HAS_RACC, 106 }, { 107 .name = "mvf600-fec", 108 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 109 }, { 110 .name = "imx6sx-fec", 111 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 112 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 113 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 114 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 115 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE, 116 }, { 117 .name = "imx6ul-fec", 118 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 119 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 120 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 121 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 122 FEC_QUIRK_HAS_COALESCE, 123 }, { 124 /* sentinel */ 125 } 126 }; 127 MODULE_DEVICE_TABLE(platform, fec_devtype); 128 129 enum imx_fec_type { 130 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 131 IMX27_FEC, /* runs on i.mx27/35/51 */ 132 IMX28_FEC, 133 IMX6Q_FEC, 134 MVF600_FEC, 135 IMX6SX_FEC, 136 IMX6UL_FEC, 137 }; 138 139 static const struct of_device_id fec_dt_ids[] = { 140 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 141 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 142 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 143 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 144 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 145 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 146 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 147 { /* sentinel */ } 148 }; 149 MODULE_DEVICE_TABLE(of, fec_dt_ids); 150 151 static unsigned char macaddr[ETH_ALEN]; 152 module_param_array(macaddr, byte, NULL, 0); 153 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 154 155 #if defined(CONFIG_M5272) 156 /* 157 * Some hardware gets it MAC address out of local flash memory. 158 * if this is non-zero then assume it is the address to get MAC from. 159 */ 160 #if defined(CONFIG_NETtel) 161 #define FEC_FLASHMAC 0xf0006006 162 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 163 #define FEC_FLASHMAC 0xf0006000 164 #elif defined(CONFIG_CANCam) 165 #define FEC_FLASHMAC 0xf0020000 166 #elif defined (CONFIG_M5272C3) 167 #define FEC_FLASHMAC (0xffe04000 + 4) 168 #elif defined(CONFIG_MOD5272) 169 #define FEC_FLASHMAC 0xffc0406b 170 #else 171 #define FEC_FLASHMAC 0 172 #endif 173 #endif /* CONFIG_M5272 */ 174 175 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 176 * 177 * 2048 byte skbufs are allocated. However, alignment requirements 178 * varies between FEC variants. Worst case is 64, so round down by 64. 179 */ 180 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 181 #define PKT_MINBUF_SIZE 64 182 183 /* FEC receive acceleration */ 184 #define FEC_RACC_IPDIS (1 << 1) 185 #define FEC_RACC_PRODIS (1 << 2) 186 #define FEC_RACC_SHIFT16 BIT(7) 187 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 188 189 /* MIB Control Register */ 190 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 191 192 /* 193 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 194 * size bits. Other FEC hardware does not, so we need to take that into 195 * account when setting it. 196 */ 197 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 198 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 199 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 200 #else 201 #define OPT_FRAME_SIZE 0 202 #endif 203 204 /* FEC MII MMFR bits definition */ 205 #define FEC_MMFR_ST (1 << 30) 206 #define FEC_MMFR_OP_READ (2 << 28) 207 #define FEC_MMFR_OP_WRITE (1 << 28) 208 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 209 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 210 #define FEC_MMFR_TA (2 << 16) 211 #define FEC_MMFR_DATA(v) (v & 0xffff) 212 /* FEC ECR bits definition */ 213 #define FEC_ECR_MAGICEN (1 << 2) 214 #define FEC_ECR_SLEEP (1 << 3) 215 216 #define FEC_MII_TIMEOUT 30000 /* us */ 217 218 /* Transmitter timeout */ 219 #define TX_TIMEOUT (2 * HZ) 220 221 #define FEC_PAUSE_FLAG_AUTONEG 0x1 222 #define FEC_PAUSE_FLAG_ENABLE 0x2 223 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 224 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 225 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 226 227 #define COPYBREAK_DEFAULT 256 228 229 /* Max number of allowed TCP segments for software TSO */ 230 #define FEC_MAX_TSO_SEGS 100 231 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 232 233 #define IS_TSO_HEADER(txq, addr) \ 234 ((addr >= txq->tso_hdrs_dma) && \ 235 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 236 237 static int mii_cnt; 238 239 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 240 struct bufdesc_prop *bd) 241 { 242 return (bdp >= bd->last) ? bd->base 243 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 244 } 245 246 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 247 struct bufdesc_prop *bd) 248 { 249 return (bdp <= bd->base) ? bd->last 250 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 251 } 252 253 static int fec_enet_get_bd_index(struct bufdesc *bdp, 254 struct bufdesc_prop *bd) 255 { 256 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 257 } 258 259 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 260 { 261 int entries; 262 263 entries = (((const char *)txq->dirty_tx - 264 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 265 266 return entries >= 0 ? entries : entries + txq->bd.ring_size; 267 } 268 269 static void swap_buffer(void *bufaddr, int len) 270 { 271 int i; 272 unsigned int *buf = bufaddr; 273 274 for (i = 0; i < len; i += 4, buf++) 275 swab32s(buf); 276 } 277 278 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 279 { 280 int i; 281 unsigned int *src = src_buf; 282 unsigned int *dst = dst_buf; 283 284 for (i = 0; i < len; i += 4, src++, dst++) 285 *dst = swab32p(src); 286 } 287 288 static void fec_dump(struct net_device *ndev) 289 { 290 struct fec_enet_private *fep = netdev_priv(ndev); 291 struct bufdesc *bdp; 292 struct fec_enet_priv_tx_q *txq; 293 int index = 0; 294 295 netdev_info(ndev, "TX ring dump\n"); 296 pr_info("Nr SC addr len SKB\n"); 297 298 txq = fep->tx_queue[0]; 299 bdp = txq->bd.base; 300 301 do { 302 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 303 index, 304 bdp == txq->bd.cur ? 'S' : ' ', 305 bdp == txq->dirty_tx ? 'H' : ' ', 306 fec16_to_cpu(bdp->cbd_sc), 307 fec32_to_cpu(bdp->cbd_bufaddr), 308 fec16_to_cpu(bdp->cbd_datlen), 309 txq->tx_skbuff[index]); 310 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 311 index++; 312 } while (bdp != txq->bd.base); 313 } 314 315 static inline bool is_ipv4_pkt(struct sk_buff *skb) 316 { 317 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 318 } 319 320 static int 321 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 322 { 323 /* Only run for packets requiring a checksum. */ 324 if (skb->ip_summed != CHECKSUM_PARTIAL) 325 return 0; 326 327 if (unlikely(skb_cow_head(skb, 0))) 328 return -1; 329 330 if (is_ipv4_pkt(skb)) 331 ip_hdr(skb)->check = 0; 332 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 333 334 return 0; 335 } 336 337 static struct bufdesc * 338 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 339 struct sk_buff *skb, 340 struct net_device *ndev) 341 { 342 struct fec_enet_private *fep = netdev_priv(ndev); 343 struct bufdesc *bdp = txq->bd.cur; 344 struct bufdesc_ex *ebdp; 345 int nr_frags = skb_shinfo(skb)->nr_frags; 346 int frag, frag_len; 347 unsigned short status; 348 unsigned int estatus = 0; 349 skb_frag_t *this_frag; 350 unsigned int index; 351 void *bufaddr; 352 dma_addr_t addr; 353 int i; 354 355 for (frag = 0; frag < nr_frags; frag++) { 356 this_frag = &skb_shinfo(skb)->frags[frag]; 357 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 358 ebdp = (struct bufdesc_ex *)bdp; 359 360 status = fec16_to_cpu(bdp->cbd_sc); 361 status &= ~BD_ENET_TX_STATS; 362 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 363 frag_len = skb_shinfo(skb)->frags[frag].size; 364 365 /* Handle the last BD specially */ 366 if (frag == nr_frags - 1) { 367 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 368 if (fep->bufdesc_ex) { 369 estatus |= BD_ENET_TX_INT; 370 if (unlikely(skb_shinfo(skb)->tx_flags & 371 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 372 estatus |= BD_ENET_TX_TS; 373 } 374 } 375 376 if (fep->bufdesc_ex) { 377 if (fep->quirks & FEC_QUIRK_HAS_AVB) 378 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 379 if (skb->ip_summed == CHECKSUM_PARTIAL) 380 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 381 ebdp->cbd_bdu = 0; 382 ebdp->cbd_esc = cpu_to_fec32(estatus); 383 } 384 385 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset; 386 387 index = fec_enet_get_bd_index(bdp, &txq->bd); 388 if (((unsigned long) bufaddr) & fep->tx_align || 389 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 390 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 391 bufaddr = txq->tx_bounce[index]; 392 393 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 394 swap_buffer(bufaddr, frag_len); 395 } 396 397 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 398 DMA_TO_DEVICE); 399 if (dma_mapping_error(&fep->pdev->dev, addr)) { 400 if (net_ratelimit()) 401 netdev_err(ndev, "Tx DMA memory map failed\n"); 402 goto dma_mapping_error; 403 } 404 405 bdp->cbd_bufaddr = cpu_to_fec32(addr); 406 bdp->cbd_datlen = cpu_to_fec16(frag_len); 407 /* Make sure the updates to rest of the descriptor are 408 * performed before transferring ownership. 409 */ 410 wmb(); 411 bdp->cbd_sc = cpu_to_fec16(status); 412 } 413 414 return bdp; 415 dma_mapping_error: 416 bdp = txq->bd.cur; 417 for (i = 0; i < frag; i++) { 418 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 419 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 420 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 421 } 422 return ERR_PTR(-ENOMEM); 423 } 424 425 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 426 struct sk_buff *skb, struct net_device *ndev) 427 { 428 struct fec_enet_private *fep = netdev_priv(ndev); 429 int nr_frags = skb_shinfo(skb)->nr_frags; 430 struct bufdesc *bdp, *last_bdp; 431 void *bufaddr; 432 dma_addr_t addr; 433 unsigned short status; 434 unsigned short buflen; 435 unsigned int estatus = 0; 436 unsigned int index; 437 int entries_free; 438 439 entries_free = fec_enet_get_free_txdesc_num(txq); 440 if (entries_free < MAX_SKB_FRAGS + 1) { 441 dev_kfree_skb_any(skb); 442 if (net_ratelimit()) 443 netdev_err(ndev, "NOT enough BD for SG!\n"); 444 return NETDEV_TX_OK; 445 } 446 447 /* Protocol checksum off-load for TCP and UDP. */ 448 if (fec_enet_clear_csum(skb, ndev)) { 449 dev_kfree_skb_any(skb); 450 return NETDEV_TX_OK; 451 } 452 453 /* Fill in a Tx ring entry */ 454 bdp = txq->bd.cur; 455 last_bdp = bdp; 456 status = fec16_to_cpu(bdp->cbd_sc); 457 status &= ~BD_ENET_TX_STATS; 458 459 /* Set buffer length and buffer pointer */ 460 bufaddr = skb->data; 461 buflen = skb_headlen(skb); 462 463 index = fec_enet_get_bd_index(bdp, &txq->bd); 464 if (((unsigned long) bufaddr) & fep->tx_align || 465 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 466 memcpy(txq->tx_bounce[index], skb->data, buflen); 467 bufaddr = txq->tx_bounce[index]; 468 469 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 470 swap_buffer(bufaddr, buflen); 471 } 472 473 /* Push the data cache so the CPM does not get stale memory data. */ 474 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 475 if (dma_mapping_error(&fep->pdev->dev, addr)) { 476 dev_kfree_skb_any(skb); 477 if (net_ratelimit()) 478 netdev_err(ndev, "Tx DMA memory map failed\n"); 479 return NETDEV_TX_OK; 480 } 481 482 if (nr_frags) { 483 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 484 if (IS_ERR(last_bdp)) { 485 dma_unmap_single(&fep->pdev->dev, addr, 486 buflen, DMA_TO_DEVICE); 487 dev_kfree_skb_any(skb); 488 return NETDEV_TX_OK; 489 } 490 } else { 491 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 492 if (fep->bufdesc_ex) { 493 estatus = BD_ENET_TX_INT; 494 if (unlikely(skb_shinfo(skb)->tx_flags & 495 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 496 estatus |= BD_ENET_TX_TS; 497 } 498 } 499 bdp->cbd_bufaddr = cpu_to_fec32(addr); 500 bdp->cbd_datlen = cpu_to_fec16(buflen); 501 502 if (fep->bufdesc_ex) { 503 504 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 505 506 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 507 fep->hwts_tx_en)) 508 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 509 510 if (fep->quirks & FEC_QUIRK_HAS_AVB) 511 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 512 513 if (skb->ip_summed == CHECKSUM_PARTIAL) 514 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 515 516 ebdp->cbd_bdu = 0; 517 ebdp->cbd_esc = cpu_to_fec32(estatus); 518 } 519 520 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 521 /* Save skb pointer */ 522 txq->tx_skbuff[index] = skb; 523 524 /* Make sure the updates to rest of the descriptor are performed before 525 * transferring ownership. 526 */ 527 wmb(); 528 529 /* Send it on its way. Tell FEC it's ready, interrupt when done, 530 * it's the last BD of the frame, and to put the CRC on the end. 531 */ 532 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 533 bdp->cbd_sc = cpu_to_fec16(status); 534 535 /* If this was the last BD in the ring, start at the beginning again. */ 536 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 537 538 skb_tx_timestamp(skb); 539 540 /* Make sure the update to bdp and tx_skbuff are performed before 541 * txq->bd.cur. 542 */ 543 wmb(); 544 txq->bd.cur = bdp; 545 546 /* Trigger transmission start */ 547 writel(0, txq->bd.reg_desc_active); 548 549 return 0; 550 } 551 552 static int 553 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 554 struct net_device *ndev, 555 struct bufdesc *bdp, int index, char *data, 556 int size, bool last_tcp, bool is_last) 557 { 558 struct fec_enet_private *fep = netdev_priv(ndev); 559 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 560 unsigned short status; 561 unsigned int estatus = 0; 562 dma_addr_t addr; 563 564 status = fec16_to_cpu(bdp->cbd_sc); 565 status &= ~BD_ENET_TX_STATS; 566 567 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 568 569 if (((unsigned long) data) & fep->tx_align || 570 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 571 memcpy(txq->tx_bounce[index], data, size); 572 data = txq->tx_bounce[index]; 573 574 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 575 swap_buffer(data, size); 576 } 577 578 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 579 if (dma_mapping_error(&fep->pdev->dev, addr)) { 580 dev_kfree_skb_any(skb); 581 if (net_ratelimit()) 582 netdev_err(ndev, "Tx DMA memory map failed\n"); 583 return NETDEV_TX_BUSY; 584 } 585 586 bdp->cbd_datlen = cpu_to_fec16(size); 587 bdp->cbd_bufaddr = cpu_to_fec32(addr); 588 589 if (fep->bufdesc_ex) { 590 if (fep->quirks & FEC_QUIRK_HAS_AVB) 591 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 592 if (skb->ip_summed == CHECKSUM_PARTIAL) 593 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 594 ebdp->cbd_bdu = 0; 595 ebdp->cbd_esc = cpu_to_fec32(estatus); 596 } 597 598 /* Handle the last BD specially */ 599 if (last_tcp) 600 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 601 if (is_last) { 602 status |= BD_ENET_TX_INTR; 603 if (fep->bufdesc_ex) 604 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 605 } 606 607 bdp->cbd_sc = cpu_to_fec16(status); 608 609 return 0; 610 } 611 612 static int 613 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 614 struct sk_buff *skb, struct net_device *ndev, 615 struct bufdesc *bdp, int index) 616 { 617 struct fec_enet_private *fep = netdev_priv(ndev); 618 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 619 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 620 void *bufaddr; 621 unsigned long dmabuf; 622 unsigned short status; 623 unsigned int estatus = 0; 624 625 status = fec16_to_cpu(bdp->cbd_sc); 626 status &= ~BD_ENET_TX_STATS; 627 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 628 629 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 630 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 631 if (((unsigned long)bufaddr) & fep->tx_align || 632 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 633 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 634 bufaddr = txq->tx_bounce[index]; 635 636 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 637 swap_buffer(bufaddr, hdr_len); 638 639 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 640 hdr_len, DMA_TO_DEVICE); 641 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 642 dev_kfree_skb_any(skb); 643 if (net_ratelimit()) 644 netdev_err(ndev, "Tx DMA memory map failed\n"); 645 return NETDEV_TX_BUSY; 646 } 647 } 648 649 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 650 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 651 652 if (fep->bufdesc_ex) { 653 if (fep->quirks & FEC_QUIRK_HAS_AVB) 654 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 655 if (skb->ip_summed == CHECKSUM_PARTIAL) 656 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 657 ebdp->cbd_bdu = 0; 658 ebdp->cbd_esc = cpu_to_fec32(estatus); 659 } 660 661 bdp->cbd_sc = cpu_to_fec16(status); 662 663 return 0; 664 } 665 666 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 667 struct sk_buff *skb, 668 struct net_device *ndev) 669 { 670 struct fec_enet_private *fep = netdev_priv(ndev); 671 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 672 int total_len, data_left; 673 struct bufdesc *bdp = txq->bd.cur; 674 struct tso_t tso; 675 unsigned int index = 0; 676 int ret; 677 678 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 679 dev_kfree_skb_any(skb); 680 if (net_ratelimit()) 681 netdev_err(ndev, "NOT enough BD for TSO!\n"); 682 return NETDEV_TX_OK; 683 } 684 685 /* Protocol checksum off-load for TCP and UDP. */ 686 if (fec_enet_clear_csum(skb, ndev)) { 687 dev_kfree_skb_any(skb); 688 return NETDEV_TX_OK; 689 } 690 691 /* Initialize the TSO handler, and prepare the first payload */ 692 tso_start(skb, &tso); 693 694 total_len = skb->len - hdr_len; 695 while (total_len > 0) { 696 char *hdr; 697 698 index = fec_enet_get_bd_index(bdp, &txq->bd); 699 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 700 total_len -= data_left; 701 702 /* prepare packet headers: MAC + IP + TCP */ 703 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 704 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 705 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 706 if (ret) 707 goto err_release; 708 709 while (data_left > 0) { 710 int size; 711 712 size = min_t(int, tso.size, data_left); 713 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 714 index = fec_enet_get_bd_index(bdp, &txq->bd); 715 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 716 bdp, index, 717 tso.data, size, 718 size == data_left, 719 total_len == 0); 720 if (ret) 721 goto err_release; 722 723 data_left -= size; 724 tso_build_data(skb, &tso, size); 725 } 726 727 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 728 } 729 730 /* Save skb pointer */ 731 txq->tx_skbuff[index] = skb; 732 733 skb_tx_timestamp(skb); 734 txq->bd.cur = bdp; 735 736 /* Trigger transmission start */ 737 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 738 !readl(txq->bd.reg_desc_active) || 739 !readl(txq->bd.reg_desc_active) || 740 !readl(txq->bd.reg_desc_active) || 741 !readl(txq->bd.reg_desc_active)) 742 writel(0, txq->bd.reg_desc_active); 743 744 return 0; 745 746 err_release: 747 /* TODO: Release all used data descriptors for TSO */ 748 return ret; 749 } 750 751 static netdev_tx_t 752 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 753 { 754 struct fec_enet_private *fep = netdev_priv(ndev); 755 int entries_free; 756 unsigned short queue; 757 struct fec_enet_priv_tx_q *txq; 758 struct netdev_queue *nq; 759 int ret; 760 761 queue = skb_get_queue_mapping(skb); 762 txq = fep->tx_queue[queue]; 763 nq = netdev_get_tx_queue(ndev, queue); 764 765 if (skb_is_gso(skb)) 766 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 767 else 768 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 769 if (ret) 770 return ret; 771 772 entries_free = fec_enet_get_free_txdesc_num(txq); 773 if (entries_free <= txq->tx_stop_threshold) 774 netif_tx_stop_queue(nq); 775 776 return NETDEV_TX_OK; 777 } 778 779 /* Init RX & TX buffer descriptors 780 */ 781 static void fec_enet_bd_init(struct net_device *dev) 782 { 783 struct fec_enet_private *fep = netdev_priv(dev); 784 struct fec_enet_priv_tx_q *txq; 785 struct fec_enet_priv_rx_q *rxq; 786 struct bufdesc *bdp; 787 unsigned int i; 788 unsigned int q; 789 790 for (q = 0; q < fep->num_rx_queues; q++) { 791 /* Initialize the receive buffer descriptors. */ 792 rxq = fep->rx_queue[q]; 793 bdp = rxq->bd.base; 794 795 for (i = 0; i < rxq->bd.ring_size; i++) { 796 797 /* Initialize the BD for every fragment in the page. */ 798 if (bdp->cbd_bufaddr) 799 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 800 else 801 bdp->cbd_sc = cpu_to_fec16(0); 802 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 803 } 804 805 /* Set the last buffer to wrap */ 806 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 807 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 808 809 rxq->bd.cur = rxq->bd.base; 810 } 811 812 for (q = 0; q < fep->num_tx_queues; q++) { 813 /* ...and the same for transmit */ 814 txq = fep->tx_queue[q]; 815 bdp = txq->bd.base; 816 txq->bd.cur = bdp; 817 818 for (i = 0; i < txq->bd.ring_size; i++) { 819 /* Initialize the BD for every fragment in the page. */ 820 bdp->cbd_sc = cpu_to_fec16(0); 821 if (txq->tx_skbuff[i]) { 822 dev_kfree_skb_any(txq->tx_skbuff[i]); 823 txq->tx_skbuff[i] = NULL; 824 } 825 bdp->cbd_bufaddr = cpu_to_fec32(0); 826 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 827 } 828 829 /* Set the last buffer to wrap */ 830 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 831 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 832 txq->dirty_tx = bdp; 833 } 834 } 835 836 static void fec_enet_active_rxring(struct net_device *ndev) 837 { 838 struct fec_enet_private *fep = netdev_priv(ndev); 839 int i; 840 841 for (i = 0; i < fep->num_rx_queues; i++) 842 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 843 } 844 845 static void fec_enet_enable_ring(struct net_device *ndev) 846 { 847 struct fec_enet_private *fep = netdev_priv(ndev); 848 struct fec_enet_priv_tx_q *txq; 849 struct fec_enet_priv_rx_q *rxq; 850 int i; 851 852 for (i = 0; i < fep->num_rx_queues; i++) { 853 rxq = fep->rx_queue[i]; 854 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 855 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 856 857 /* enable DMA1/2 */ 858 if (i) 859 writel(RCMR_MATCHEN | RCMR_CMP(i), 860 fep->hwp + FEC_RCMR(i)); 861 } 862 863 for (i = 0; i < fep->num_tx_queues; i++) { 864 txq = fep->tx_queue[i]; 865 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 866 867 /* enable DMA1/2 */ 868 if (i) 869 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 870 fep->hwp + FEC_DMA_CFG(i)); 871 } 872 } 873 874 static void fec_enet_reset_skb(struct net_device *ndev) 875 { 876 struct fec_enet_private *fep = netdev_priv(ndev); 877 struct fec_enet_priv_tx_q *txq; 878 int i, j; 879 880 for (i = 0; i < fep->num_tx_queues; i++) { 881 txq = fep->tx_queue[i]; 882 883 for (j = 0; j < txq->bd.ring_size; j++) { 884 if (txq->tx_skbuff[j]) { 885 dev_kfree_skb_any(txq->tx_skbuff[j]); 886 txq->tx_skbuff[j] = NULL; 887 } 888 } 889 } 890 } 891 892 /* 893 * This function is called to start or restart the FEC during a link 894 * change, transmit timeout, or to reconfigure the FEC. The network 895 * packet processing for this device must be stopped before this call. 896 */ 897 static void 898 fec_restart(struct net_device *ndev) 899 { 900 struct fec_enet_private *fep = netdev_priv(ndev); 901 u32 val; 902 u32 temp_mac[2]; 903 u32 rcntl = OPT_FRAME_SIZE | 0x04; 904 u32 ecntl = 0x2; /* ETHEREN */ 905 906 /* Whack a reset. We should wait for this. 907 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 908 * instead of reset MAC itself. 909 */ 910 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 911 writel(0, fep->hwp + FEC_ECNTRL); 912 } else { 913 writel(1, fep->hwp + FEC_ECNTRL); 914 udelay(10); 915 } 916 917 /* 918 * enet-mac reset will reset mac address registers too, 919 * so need to reconfigure it. 920 */ 921 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 922 writel((__force u32)cpu_to_be32(temp_mac[0]), 923 fep->hwp + FEC_ADDR_LOW); 924 writel((__force u32)cpu_to_be32(temp_mac[1]), 925 fep->hwp + FEC_ADDR_HIGH); 926 927 /* Clear any outstanding interrupt. */ 928 writel(0xffffffff, fep->hwp + FEC_IEVENT); 929 930 fec_enet_bd_init(ndev); 931 932 fec_enet_enable_ring(ndev); 933 934 /* Reset tx SKB buffers. */ 935 fec_enet_reset_skb(ndev); 936 937 /* Enable MII mode */ 938 if (fep->full_duplex == DUPLEX_FULL) { 939 /* FD enable */ 940 writel(0x04, fep->hwp + FEC_X_CNTRL); 941 } else { 942 /* No Rcv on Xmit */ 943 rcntl |= 0x02; 944 writel(0x0, fep->hwp + FEC_X_CNTRL); 945 } 946 947 /* Set MII speed */ 948 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 949 950 #if !defined(CONFIG_M5272) 951 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 952 val = readl(fep->hwp + FEC_RACC); 953 /* align IP header */ 954 val |= FEC_RACC_SHIFT16; 955 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 956 /* set RX checksum */ 957 val |= FEC_RACC_OPTIONS; 958 else 959 val &= ~FEC_RACC_OPTIONS; 960 writel(val, fep->hwp + FEC_RACC); 961 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 962 } 963 #endif 964 965 /* 966 * The phy interface and speed need to get configured 967 * differently on enet-mac. 968 */ 969 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 970 /* Enable flow control and length check */ 971 rcntl |= 0x40000000 | 0x00000020; 972 973 /* RGMII, RMII or MII */ 974 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 975 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 976 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 977 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 978 rcntl |= (1 << 6); 979 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 980 rcntl |= (1 << 8); 981 else 982 rcntl &= ~(1 << 8); 983 984 /* 1G, 100M or 10M */ 985 if (ndev->phydev) { 986 if (ndev->phydev->speed == SPEED_1000) 987 ecntl |= (1 << 5); 988 else if (ndev->phydev->speed == SPEED_100) 989 rcntl &= ~(1 << 9); 990 else 991 rcntl |= (1 << 9); 992 } 993 } else { 994 #ifdef FEC_MIIGSK_ENR 995 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 996 u32 cfgr; 997 /* disable the gasket and wait */ 998 writel(0, fep->hwp + FEC_MIIGSK_ENR); 999 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1000 udelay(1); 1001 1002 /* 1003 * configure the gasket: 1004 * RMII, 50 MHz, no loopback, no echo 1005 * MII, 25 MHz, no loopback, no echo 1006 */ 1007 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1008 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1009 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1010 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1011 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1012 1013 /* re-enable the gasket */ 1014 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1015 } 1016 #endif 1017 } 1018 1019 #if !defined(CONFIG_M5272) 1020 /* enable pause frame*/ 1021 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1022 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1023 ndev->phydev && ndev->phydev->pause)) { 1024 rcntl |= FEC_ENET_FCE; 1025 1026 /* set FIFO threshold parameter to reduce overrun */ 1027 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1028 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1029 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1030 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1031 1032 /* OPD */ 1033 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1034 } else { 1035 rcntl &= ~FEC_ENET_FCE; 1036 } 1037 #endif /* !defined(CONFIG_M5272) */ 1038 1039 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1040 1041 /* Setup multicast filter. */ 1042 set_multicast_list(ndev); 1043 #ifndef CONFIG_M5272 1044 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1045 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1046 #endif 1047 1048 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1049 /* enable ENET endian swap */ 1050 ecntl |= (1 << 8); 1051 /* enable ENET store and forward mode */ 1052 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1053 } 1054 1055 if (fep->bufdesc_ex) 1056 ecntl |= (1 << 4); 1057 1058 #ifndef CONFIG_M5272 1059 /* Enable the MIB statistic event counters */ 1060 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1061 #endif 1062 1063 /* And last, enable the transmit and receive processing */ 1064 writel(ecntl, fep->hwp + FEC_ECNTRL); 1065 fec_enet_active_rxring(ndev); 1066 1067 if (fep->bufdesc_ex) 1068 fec_ptp_start_cyclecounter(ndev); 1069 1070 /* Enable interrupts we wish to service */ 1071 if (fep->link) 1072 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1073 else 1074 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); 1075 1076 /* Init the interrupt coalescing */ 1077 fec_enet_itr_coal_init(ndev); 1078 1079 } 1080 1081 static void 1082 fec_stop(struct net_device *ndev) 1083 { 1084 struct fec_enet_private *fep = netdev_priv(ndev); 1085 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1086 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1087 u32 val; 1088 1089 /* We cannot expect a graceful transmit stop without link !!! */ 1090 if (fep->link) { 1091 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1092 udelay(10); 1093 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1094 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1095 } 1096 1097 /* Whack a reset. We should wait for this. 1098 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1099 * instead of reset MAC itself. 1100 */ 1101 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1102 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 1103 writel(0, fep->hwp + FEC_ECNTRL); 1104 } else { 1105 writel(1, fep->hwp + FEC_ECNTRL); 1106 udelay(10); 1107 } 1108 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1109 } else { 1110 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1111 val = readl(fep->hwp + FEC_ECNTRL); 1112 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1113 writel(val, fep->hwp + FEC_ECNTRL); 1114 1115 if (pdata && pdata->sleep_mode_enable) 1116 pdata->sleep_mode_enable(true); 1117 } 1118 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1119 1120 /* We have to keep ENET enabled to have MII interrupt stay working */ 1121 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1122 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1123 writel(2, fep->hwp + FEC_ECNTRL); 1124 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1125 } 1126 } 1127 1128 1129 static void 1130 fec_timeout(struct net_device *ndev) 1131 { 1132 struct fec_enet_private *fep = netdev_priv(ndev); 1133 1134 fec_dump(ndev); 1135 1136 ndev->stats.tx_errors++; 1137 1138 schedule_work(&fep->tx_timeout_work); 1139 } 1140 1141 static void fec_enet_timeout_work(struct work_struct *work) 1142 { 1143 struct fec_enet_private *fep = 1144 container_of(work, struct fec_enet_private, tx_timeout_work); 1145 struct net_device *ndev = fep->netdev; 1146 1147 rtnl_lock(); 1148 if (netif_device_present(ndev) || netif_running(ndev)) { 1149 napi_disable(&fep->napi); 1150 netif_tx_lock_bh(ndev); 1151 fec_restart(ndev); 1152 netif_wake_queue(ndev); 1153 netif_tx_unlock_bh(ndev); 1154 napi_enable(&fep->napi); 1155 } 1156 rtnl_unlock(); 1157 } 1158 1159 static void 1160 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1161 struct skb_shared_hwtstamps *hwtstamps) 1162 { 1163 unsigned long flags; 1164 u64 ns; 1165 1166 spin_lock_irqsave(&fep->tmreg_lock, flags); 1167 ns = timecounter_cyc2time(&fep->tc, ts); 1168 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1169 1170 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1171 hwtstamps->hwtstamp = ns_to_ktime(ns); 1172 } 1173 1174 static void 1175 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1176 { 1177 struct fec_enet_private *fep; 1178 struct bufdesc *bdp; 1179 unsigned short status; 1180 struct sk_buff *skb; 1181 struct fec_enet_priv_tx_q *txq; 1182 struct netdev_queue *nq; 1183 int index = 0; 1184 int entries_free; 1185 1186 fep = netdev_priv(ndev); 1187 1188 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1189 1190 txq = fep->tx_queue[queue_id]; 1191 /* get next bdp of dirty_tx */ 1192 nq = netdev_get_tx_queue(ndev, queue_id); 1193 bdp = txq->dirty_tx; 1194 1195 /* get next bdp of dirty_tx */ 1196 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1197 1198 while (bdp != READ_ONCE(txq->bd.cur)) { 1199 /* Order the load of bd.cur and cbd_sc */ 1200 rmb(); 1201 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1202 if (status & BD_ENET_TX_READY) 1203 break; 1204 1205 index = fec_enet_get_bd_index(bdp, &txq->bd); 1206 1207 skb = txq->tx_skbuff[index]; 1208 txq->tx_skbuff[index] = NULL; 1209 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1210 dma_unmap_single(&fep->pdev->dev, 1211 fec32_to_cpu(bdp->cbd_bufaddr), 1212 fec16_to_cpu(bdp->cbd_datlen), 1213 DMA_TO_DEVICE); 1214 bdp->cbd_bufaddr = cpu_to_fec32(0); 1215 if (!skb) 1216 goto skb_done; 1217 1218 /* Check for errors. */ 1219 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1220 BD_ENET_TX_RL | BD_ENET_TX_UN | 1221 BD_ENET_TX_CSL)) { 1222 ndev->stats.tx_errors++; 1223 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1224 ndev->stats.tx_heartbeat_errors++; 1225 if (status & BD_ENET_TX_LC) /* Late collision */ 1226 ndev->stats.tx_window_errors++; 1227 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1228 ndev->stats.tx_aborted_errors++; 1229 if (status & BD_ENET_TX_UN) /* Underrun */ 1230 ndev->stats.tx_fifo_errors++; 1231 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1232 ndev->stats.tx_carrier_errors++; 1233 } else { 1234 ndev->stats.tx_packets++; 1235 ndev->stats.tx_bytes += skb->len; 1236 } 1237 1238 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 1239 fep->bufdesc_ex) { 1240 struct skb_shared_hwtstamps shhwtstamps; 1241 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1242 1243 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1244 skb_tstamp_tx(skb, &shhwtstamps); 1245 } 1246 1247 /* Deferred means some collisions occurred during transmit, 1248 * but we eventually sent the packet OK. 1249 */ 1250 if (status & BD_ENET_TX_DEF) 1251 ndev->stats.collisions++; 1252 1253 /* Free the sk buffer associated with this last transmit */ 1254 dev_kfree_skb_any(skb); 1255 skb_done: 1256 /* Make sure the update to bdp and tx_skbuff are performed 1257 * before dirty_tx 1258 */ 1259 wmb(); 1260 txq->dirty_tx = bdp; 1261 1262 /* Update pointer to next buffer descriptor to be transmitted */ 1263 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1264 1265 /* Since we have freed up a buffer, the ring is no longer full 1266 */ 1267 if (netif_queue_stopped(ndev)) { 1268 entries_free = fec_enet_get_free_txdesc_num(txq); 1269 if (entries_free >= txq->tx_wake_threshold) 1270 netif_tx_wake_queue(nq); 1271 } 1272 } 1273 1274 /* ERR006358: Keep the transmitter going */ 1275 if (bdp != txq->bd.cur && 1276 readl(txq->bd.reg_desc_active) == 0) 1277 writel(0, txq->bd.reg_desc_active); 1278 } 1279 1280 static void 1281 fec_enet_tx(struct net_device *ndev) 1282 { 1283 struct fec_enet_private *fep = netdev_priv(ndev); 1284 u16 queue_id; 1285 /* First process class A queue, then Class B and Best Effort queue */ 1286 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) { 1287 clear_bit(queue_id, &fep->work_tx); 1288 fec_enet_tx_queue(ndev, queue_id); 1289 } 1290 return; 1291 } 1292 1293 static int 1294 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1295 { 1296 struct fec_enet_private *fep = netdev_priv(ndev); 1297 int off; 1298 1299 off = ((unsigned long)skb->data) & fep->rx_align; 1300 if (off) 1301 skb_reserve(skb, fep->rx_align + 1 - off); 1302 1303 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1304 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1305 if (net_ratelimit()) 1306 netdev_err(ndev, "Rx DMA memory map failed\n"); 1307 return -ENOMEM; 1308 } 1309 1310 return 0; 1311 } 1312 1313 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1314 struct bufdesc *bdp, u32 length, bool swap) 1315 { 1316 struct fec_enet_private *fep = netdev_priv(ndev); 1317 struct sk_buff *new_skb; 1318 1319 if (length > fep->rx_copybreak) 1320 return false; 1321 1322 new_skb = netdev_alloc_skb(ndev, length); 1323 if (!new_skb) 1324 return false; 1325 1326 dma_sync_single_for_cpu(&fep->pdev->dev, 1327 fec32_to_cpu(bdp->cbd_bufaddr), 1328 FEC_ENET_RX_FRSIZE - fep->rx_align, 1329 DMA_FROM_DEVICE); 1330 if (!swap) 1331 memcpy(new_skb->data, (*skb)->data, length); 1332 else 1333 swap_buffer2(new_skb->data, (*skb)->data, length); 1334 *skb = new_skb; 1335 1336 return true; 1337 } 1338 1339 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1340 * When we update through the ring, if the next incoming buffer has 1341 * not been given to the system, we just set the empty indicator, 1342 * effectively tossing the packet. 1343 */ 1344 static int 1345 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1346 { 1347 struct fec_enet_private *fep = netdev_priv(ndev); 1348 struct fec_enet_priv_rx_q *rxq; 1349 struct bufdesc *bdp; 1350 unsigned short status; 1351 struct sk_buff *skb_new = NULL; 1352 struct sk_buff *skb; 1353 ushort pkt_len; 1354 __u8 *data; 1355 int pkt_received = 0; 1356 struct bufdesc_ex *ebdp = NULL; 1357 bool vlan_packet_rcvd = false; 1358 u16 vlan_tag; 1359 int index = 0; 1360 bool is_copybreak; 1361 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1362 1363 #ifdef CONFIG_M532x 1364 flush_cache_all(); 1365 #endif 1366 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1367 rxq = fep->rx_queue[queue_id]; 1368 1369 /* First, grab all of the stats for the incoming packet. 1370 * These get messed up if we get called due to a busy condition. 1371 */ 1372 bdp = rxq->bd.cur; 1373 1374 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1375 1376 if (pkt_received >= budget) 1377 break; 1378 pkt_received++; 1379 1380 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); 1381 1382 /* Check for errors. */ 1383 status ^= BD_ENET_RX_LAST; 1384 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1385 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1386 BD_ENET_RX_CL)) { 1387 ndev->stats.rx_errors++; 1388 if (status & BD_ENET_RX_OV) { 1389 /* FIFO overrun */ 1390 ndev->stats.rx_fifo_errors++; 1391 goto rx_processing_done; 1392 } 1393 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1394 | BD_ENET_RX_LAST)) { 1395 /* Frame too long or too short. */ 1396 ndev->stats.rx_length_errors++; 1397 if (status & BD_ENET_RX_LAST) 1398 netdev_err(ndev, "rcv is not +last\n"); 1399 } 1400 if (status & BD_ENET_RX_CR) /* CRC Error */ 1401 ndev->stats.rx_crc_errors++; 1402 /* Report late collisions as a frame error. */ 1403 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1404 ndev->stats.rx_frame_errors++; 1405 goto rx_processing_done; 1406 } 1407 1408 /* Process the incoming frame. */ 1409 ndev->stats.rx_packets++; 1410 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1411 ndev->stats.rx_bytes += pkt_len; 1412 1413 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1414 skb = rxq->rx_skbuff[index]; 1415 1416 /* The packet length includes FCS, but we don't want to 1417 * include that when passing upstream as it messes up 1418 * bridging applications. 1419 */ 1420 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1421 need_swap); 1422 if (!is_copybreak) { 1423 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1424 if (unlikely(!skb_new)) { 1425 ndev->stats.rx_dropped++; 1426 goto rx_processing_done; 1427 } 1428 dma_unmap_single(&fep->pdev->dev, 1429 fec32_to_cpu(bdp->cbd_bufaddr), 1430 FEC_ENET_RX_FRSIZE - fep->rx_align, 1431 DMA_FROM_DEVICE); 1432 } 1433 1434 prefetch(skb->data - NET_IP_ALIGN); 1435 skb_put(skb, pkt_len - 4); 1436 data = skb->data; 1437 1438 if (!is_copybreak && need_swap) 1439 swap_buffer(data, pkt_len); 1440 1441 #if !defined(CONFIG_M5272) 1442 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1443 data = skb_pull_inline(skb, 2); 1444 #endif 1445 1446 /* Extract the enhanced buffer descriptor */ 1447 ebdp = NULL; 1448 if (fep->bufdesc_ex) 1449 ebdp = (struct bufdesc_ex *)bdp; 1450 1451 /* If this is a VLAN packet remove the VLAN Tag */ 1452 vlan_packet_rcvd = false; 1453 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1454 fep->bufdesc_ex && 1455 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1456 /* Push and remove the vlan tag */ 1457 struct vlan_hdr *vlan_header = 1458 (struct vlan_hdr *) (data + ETH_HLEN); 1459 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1460 1461 vlan_packet_rcvd = true; 1462 1463 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1464 skb_pull(skb, VLAN_HLEN); 1465 } 1466 1467 skb->protocol = eth_type_trans(skb, ndev); 1468 1469 /* Get receive timestamp from the skb */ 1470 if (fep->hwts_rx_en && fep->bufdesc_ex) 1471 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1472 skb_hwtstamps(skb)); 1473 1474 if (fep->bufdesc_ex && 1475 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1476 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1477 /* don't check it */ 1478 skb->ip_summed = CHECKSUM_UNNECESSARY; 1479 } else { 1480 skb_checksum_none_assert(skb); 1481 } 1482 } 1483 1484 /* Handle received VLAN packets */ 1485 if (vlan_packet_rcvd) 1486 __vlan_hwaccel_put_tag(skb, 1487 htons(ETH_P_8021Q), 1488 vlan_tag); 1489 1490 napi_gro_receive(&fep->napi, skb); 1491 1492 if (is_copybreak) { 1493 dma_sync_single_for_device(&fep->pdev->dev, 1494 fec32_to_cpu(bdp->cbd_bufaddr), 1495 FEC_ENET_RX_FRSIZE - fep->rx_align, 1496 DMA_FROM_DEVICE); 1497 } else { 1498 rxq->rx_skbuff[index] = skb_new; 1499 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1500 } 1501 1502 rx_processing_done: 1503 /* Clear the status flags for this buffer */ 1504 status &= ~BD_ENET_RX_STATS; 1505 1506 /* Mark the buffer empty */ 1507 status |= BD_ENET_RX_EMPTY; 1508 1509 if (fep->bufdesc_ex) { 1510 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1511 1512 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1513 ebdp->cbd_prot = 0; 1514 ebdp->cbd_bdu = 0; 1515 } 1516 /* Make sure the updates to rest of the descriptor are 1517 * performed before transferring ownership. 1518 */ 1519 wmb(); 1520 bdp->cbd_sc = cpu_to_fec16(status); 1521 1522 /* Update BD pointer to next entry */ 1523 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1524 1525 /* Doing this here will keep the FEC running while we process 1526 * incoming frames. On a heavily loaded network, we should be 1527 * able to keep up at the expense of system resources. 1528 */ 1529 writel(0, rxq->bd.reg_desc_active); 1530 } 1531 rxq->bd.cur = bdp; 1532 return pkt_received; 1533 } 1534 1535 static int 1536 fec_enet_rx(struct net_device *ndev, int budget) 1537 { 1538 int pkt_received = 0; 1539 u16 queue_id; 1540 struct fec_enet_private *fep = netdev_priv(ndev); 1541 1542 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) { 1543 int ret; 1544 1545 ret = fec_enet_rx_queue(ndev, 1546 budget - pkt_received, queue_id); 1547 1548 if (ret < budget - pkt_received) 1549 clear_bit(queue_id, &fep->work_rx); 1550 1551 pkt_received += ret; 1552 } 1553 return pkt_received; 1554 } 1555 1556 static bool 1557 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events) 1558 { 1559 if (int_events == 0) 1560 return false; 1561 1562 if (int_events & FEC_ENET_RXF_0) 1563 fep->work_rx |= (1 << 2); 1564 if (int_events & FEC_ENET_RXF_1) 1565 fep->work_rx |= (1 << 0); 1566 if (int_events & FEC_ENET_RXF_2) 1567 fep->work_rx |= (1 << 1); 1568 1569 if (int_events & FEC_ENET_TXF_0) 1570 fep->work_tx |= (1 << 2); 1571 if (int_events & FEC_ENET_TXF_1) 1572 fep->work_tx |= (1 << 0); 1573 if (int_events & FEC_ENET_TXF_2) 1574 fep->work_tx |= (1 << 1); 1575 1576 return true; 1577 } 1578 1579 static irqreturn_t 1580 fec_enet_interrupt(int irq, void *dev_id) 1581 { 1582 struct net_device *ndev = dev_id; 1583 struct fec_enet_private *fep = netdev_priv(ndev); 1584 uint int_events; 1585 irqreturn_t ret = IRQ_NONE; 1586 1587 int_events = readl(fep->hwp + FEC_IEVENT); 1588 writel(int_events, fep->hwp + FEC_IEVENT); 1589 fec_enet_collect_events(fep, int_events); 1590 1591 if ((fep->work_tx || fep->work_rx) && fep->link) { 1592 ret = IRQ_HANDLED; 1593 1594 if (napi_schedule_prep(&fep->napi)) { 1595 /* Disable the NAPI interrupts */ 1596 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK); 1597 __napi_schedule(&fep->napi); 1598 } 1599 } 1600 1601 if (int_events & FEC_ENET_MII) { 1602 ret = IRQ_HANDLED; 1603 complete(&fep->mdio_done); 1604 } 1605 return ret; 1606 } 1607 1608 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1609 { 1610 struct net_device *ndev = napi->dev; 1611 struct fec_enet_private *fep = netdev_priv(ndev); 1612 int pkts; 1613 1614 pkts = fec_enet_rx(ndev, budget); 1615 1616 fec_enet_tx(ndev); 1617 1618 if (pkts < budget) { 1619 napi_complete_done(napi, pkts); 1620 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1621 } 1622 return pkts; 1623 } 1624 1625 /* ------------------------------------------------------------------------- */ 1626 static void fec_get_mac(struct net_device *ndev) 1627 { 1628 struct fec_enet_private *fep = netdev_priv(ndev); 1629 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1630 unsigned char *iap, tmpaddr[ETH_ALEN]; 1631 1632 /* 1633 * try to get mac address in following order: 1634 * 1635 * 1) module parameter via kernel command line in form 1636 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1637 */ 1638 iap = macaddr; 1639 1640 /* 1641 * 2) from device tree data 1642 */ 1643 if (!is_valid_ether_addr(iap)) { 1644 struct device_node *np = fep->pdev->dev.of_node; 1645 if (np) { 1646 const char *mac = of_get_mac_address(np); 1647 if (mac) 1648 iap = (unsigned char *) mac; 1649 } 1650 } 1651 1652 /* 1653 * 3) from flash or fuse (via platform data) 1654 */ 1655 if (!is_valid_ether_addr(iap)) { 1656 #ifdef CONFIG_M5272 1657 if (FEC_FLASHMAC) 1658 iap = (unsigned char *)FEC_FLASHMAC; 1659 #else 1660 if (pdata) 1661 iap = (unsigned char *)&pdata->mac; 1662 #endif 1663 } 1664 1665 /* 1666 * 4) FEC mac registers set by bootloader 1667 */ 1668 if (!is_valid_ether_addr(iap)) { 1669 *((__be32 *) &tmpaddr[0]) = 1670 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1671 *((__be16 *) &tmpaddr[4]) = 1672 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1673 iap = &tmpaddr[0]; 1674 } 1675 1676 /* 1677 * 5) random mac address 1678 */ 1679 if (!is_valid_ether_addr(iap)) { 1680 /* Report it and use a random ethernet address instead */ 1681 netdev_err(ndev, "Invalid MAC address: %pM\n", iap); 1682 eth_hw_addr_random(ndev); 1683 netdev_info(ndev, "Using random MAC address: %pM\n", 1684 ndev->dev_addr); 1685 return; 1686 } 1687 1688 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1689 1690 /* Adjust MAC if using macaddr */ 1691 if (iap == macaddr) 1692 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1693 } 1694 1695 /* ------------------------------------------------------------------------- */ 1696 1697 /* 1698 * Phy section 1699 */ 1700 static void fec_enet_adjust_link(struct net_device *ndev) 1701 { 1702 struct fec_enet_private *fep = netdev_priv(ndev); 1703 struct phy_device *phy_dev = ndev->phydev; 1704 int status_change = 0; 1705 1706 /* Prevent a state halted on mii error */ 1707 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 1708 phy_dev->state = PHY_RESUMING; 1709 return; 1710 } 1711 1712 /* 1713 * If the netdev is down, or is going down, we're not interested 1714 * in link state events, so just mark our idea of the link as down 1715 * and ignore the event. 1716 */ 1717 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1718 fep->link = 0; 1719 } else if (phy_dev->link) { 1720 if (!fep->link) { 1721 fep->link = phy_dev->link; 1722 status_change = 1; 1723 } 1724 1725 if (fep->full_duplex != phy_dev->duplex) { 1726 fep->full_duplex = phy_dev->duplex; 1727 status_change = 1; 1728 } 1729 1730 if (phy_dev->speed != fep->speed) { 1731 fep->speed = phy_dev->speed; 1732 status_change = 1; 1733 } 1734 1735 /* if any of the above changed restart the FEC */ 1736 if (status_change) { 1737 napi_disable(&fep->napi); 1738 netif_tx_lock_bh(ndev); 1739 fec_restart(ndev); 1740 netif_wake_queue(ndev); 1741 netif_tx_unlock_bh(ndev); 1742 napi_enable(&fep->napi); 1743 } 1744 } else { 1745 if (fep->link) { 1746 napi_disable(&fep->napi); 1747 netif_tx_lock_bh(ndev); 1748 fec_stop(ndev); 1749 netif_tx_unlock_bh(ndev); 1750 napi_enable(&fep->napi); 1751 fep->link = phy_dev->link; 1752 status_change = 1; 1753 } 1754 } 1755 1756 if (status_change) 1757 phy_print_status(phy_dev); 1758 } 1759 1760 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1761 { 1762 struct fec_enet_private *fep = bus->priv; 1763 struct device *dev = &fep->pdev->dev; 1764 unsigned long time_left; 1765 int ret = 0; 1766 1767 ret = pm_runtime_get_sync(dev); 1768 if (ret < 0) 1769 return ret; 1770 1771 fep->mii_timeout = 0; 1772 reinit_completion(&fep->mdio_done); 1773 1774 /* start a read op */ 1775 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 1776 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1777 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1778 1779 /* wait for end of transfer */ 1780 time_left = wait_for_completion_timeout(&fep->mdio_done, 1781 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1782 if (time_left == 0) { 1783 fep->mii_timeout = 1; 1784 netdev_err(fep->netdev, "MDIO read timeout\n"); 1785 ret = -ETIMEDOUT; 1786 goto out; 1787 } 1788 1789 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1790 1791 out: 1792 pm_runtime_mark_last_busy(dev); 1793 pm_runtime_put_autosuspend(dev); 1794 1795 return ret; 1796 } 1797 1798 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1799 u16 value) 1800 { 1801 struct fec_enet_private *fep = bus->priv; 1802 struct device *dev = &fep->pdev->dev; 1803 unsigned long time_left; 1804 int ret; 1805 1806 ret = pm_runtime_get_sync(dev); 1807 if (ret < 0) 1808 return ret; 1809 else 1810 ret = 0; 1811 1812 fep->mii_timeout = 0; 1813 reinit_completion(&fep->mdio_done); 1814 1815 /* start a write op */ 1816 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 1817 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1818 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1819 fep->hwp + FEC_MII_DATA); 1820 1821 /* wait for end of transfer */ 1822 time_left = wait_for_completion_timeout(&fep->mdio_done, 1823 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1824 if (time_left == 0) { 1825 fep->mii_timeout = 1; 1826 netdev_err(fep->netdev, "MDIO write timeout\n"); 1827 ret = -ETIMEDOUT; 1828 } 1829 1830 pm_runtime_mark_last_busy(dev); 1831 pm_runtime_put_autosuspend(dev); 1832 1833 return ret; 1834 } 1835 1836 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1837 { 1838 struct fec_enet_private *fep = netdev_priv(ndev); 1839 int ret; 1840 1841 if (enable) { 1842 ret = clk_prepare_enable(fep->clk_ahb); 1843 if (ret) 1844 return ret; 1845 1846 ret = clk_prepare_enable(fep->clk_enet_out); 1847 if (ret) 1848 goto failed_clk_enet_out; 1849 1850 if (fep->clk_ptp) { 1851 mutex_lock(&fep->ptp_clk_mutex); 1852 ret = clk_prepare_enable(fep->clk_ptp); 1853 if (ret) { 1854 mutex_unlock(&fep->ptp_clk_mutex); 1855 goto failed_clk_ptp; 1856 } else { 1857 fep->ptp_clk_on = true; 1858 } 1859 mutex_unlock(&fep->ptp_clk_mutex); 1860 } 1861 1862 ret = clk_prepare_enable(fep->clk_ref); 1863 if (ret) 1864 goto failed_clk_ref; 1865 } else { 1866 clk_disable_unprepare(fep->clk_ahb); 1867 clk_disable_unprepare(fep->clk_enet_out); 1868 if (fep->clk_ptp) { 1869 mutex_lock(&fep->ptp_clk_mutex); 1870 clk_disable_unprepare(fep->clk_ptp); 1871 fep->ptp_clk_on = false; 1872 mutex_unlock(&fep->ptp_clk_mutex); 1873 } 1874 clk_disable_unprepare(fep->clk_ref); 1875 } 1876 1877 return 0; 1878 1879 failed_clk_ref: 1880 if (fep->clk_ref) 1881 clk_disable_unprepare(fep->clk_ref); 1882 failed_clk_ptp: 1883 if (fep->clk_enet_out) 1884 clk_disable_unprepare(fep->clk_enet_out); 1885 failed_clk_enet_out: 1886 clk_disable_unprepare(fep->clk_ahb); 1887 1888 return ret; 1889 } 1890 1891 static int fec_enet_mii_probe(struct net_device *ndev) 1892 { 1893 struct fec_enet_private *fep = netdev_priv(ndev); 1894 struct phy_device *phy_dev = NULL; 1895 char mdio_bus_id[MII_BUS_ID_SIZE]; 1896 char phy_name[MII_BUS_ID_SIZE + 3]; 1897 int phy_id; 1898 int dev_id = fep->dev_id; 1899 1900 if (fep->phy_node) { 1901 phy_dev = of_phy_connect(ndev, fep->phy_node, 1902 &fec_enet_adjust_link, 0, 1903 fep->phy_interface); 1904 if (!phy_dev) { 1905 netdev_err(ndev, "Unable to connect to phy\n"); 1906 return -ENODEV; 1907 } 1908 } else { 1909 /* check for attached phy */ 1910 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1911 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 1912 continue; 1913 if (dev_id--) 1914 continue; 1915 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1916 break; 1917 } 1918 1919 if (phy_id >= PHY_MAX_ADDR) { 1920 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1921 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 1922 phy_id = 0; 1923 } 1924 1925 snprintf(phy_name, sizeof(phy_name), 1926 PHY_ID_FMT, mdio_bus_id, phy_id); 1927 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 1928 fep->phy_interface); 1929 } 1930 1931 if (IS_ERR(phy_dev)) { 1932 netdev_err(ndev, "could not attach to PHY\n"); 1933 return PTR_ERR(phy_dev); 1934 } 1935 1936 /* mask with MAC supported features */ 1937 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 1938 phy_dev->supported &= PHY_GBIT_FEATURES; 1939 phy_dev->supported &= ~SUPPORTED_1000baseT_Half; 1940 #if !defined(CONFIG_M5272) 1941 phy_dev->supported |= SUPPORTED_Pause; 1942 #endif 1943 } 1944 else 1945 phy_dev->supported &= PHY_BASIC_FEATURES; 1946 1947 phy_dev->advertising = phy_dev->supported; 1948 1949 fep->link = 0; 1950 fep->full_duplex = 0; 1951 1952 phy_attached_info(phy_dev); 1953 1954 return 0; 1955 } 1956 1957 static int fec_enet_mii_init(struct platform_device *pdev) 1958 { 1959 static struct mii_bus *fec0_mii_bus; 1960 struct net_device *ndev = platform_get_drvdata(pdev); 1961 struct fec_enet_private *fep = netdev_priv(ndev); 1962 struct device_node *node; 1963 int err = -ENXIO; 1964 u32 mii_speed, holdtime; 1965 1966 /* 1967 * The i.MX28 dual fec interfaces are not equal. 1968 * Here are the differences: 1969 * 1970 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1971 * - fec0 acts as the 1588 time master while fec1 is slave 1972 * - external phys can only be configured by fec0 1973 * 1974 * That is to say fec1 can not work independently. It only works 1975 * when fec0 is working. The reason behind this design is that the 1976 * second interface is added primarily for Switch mode. 1977 * 1978 * Because of the last point above, both phys are attached on fec0 1979 * mdio interface in board design, and need to be configured by 1980 * fec0 mii_bus. 1981 */ 1982 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 1983 /* fec1 uses fec0 mii_bus */ 1984 if (mii_cnt && fec0_mii_bus) { 1985 fep->mii_bus = fec0_mii_bus; 1986 mii_cnt++; 1987 return 0; 1988 } 1989 return -ENOENT; 1990 } 1991 1992 fep->mii_timeout = 0; 1993 1994 /* 1995 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 1996 * 1997 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 1998 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 1999 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2000 * document. 2001 */ 2002 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000); 2003 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2004 mii_speed--; 2005 if (mii_speed > 63) { 2006 dev_err(&pdev->dev, 2007 "fec clock (%lu) too fast to get right mii speed\n", 2008 clk_get_rate(fep->clk_ipg)); 2009 err = -EINVAL; 2010 goto err_out; 2011 } 2012 2013 /* 2014 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2015 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2016 * versions are RAZ there, so just ignore the difference and write the 2017 * register always. 2018 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2019 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2020 * output. 2021 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2022 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2023 * holdtime cannot result in a value greater than 3. 2024 */ 2025 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2026 2027 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2028 2029 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2030 2031 fep->mii_bus = mdiobus_alloc(); 2032 if (fep->mii_bus == NULL) { 2033 err = -ENOMEM; 2034 goto err_out; 2035 } 2036 2037 fep->mii_bus->name = "fec_enet_mii_bus"; 2038 fep->mii_bus->read = fec_enet_mdio_read; 2039 fep->mii_bus->write = fec_enet_mdio_write; 2040 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2041 pdev->name, fep->dev_id + 1); 2042 fep->mii_bus->priv = fep; 2043 fep->mii_bus->parent = &pdev->dev; 2044 2045 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2046 if (node) { 2047 err = of_mdiobus_register(fep->mii_bus, node); 2048 of_node_put(node); 2049 } else { 2050 err = mdiobus_register(fep->mii_bus); 2051 } 2052 2053 if (err) 2054 goto err_out_free_mdiobus; 2055 2056 mii_cnt++; 2057 2058 /* save fec0 mii_bus */ 2059 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2060 fec0_mii_bus = fep->mii_bus; 2061 2062 return 0; 2063 2064 err_out_free_mdiobus: 2065 mdiobus_free(fep->mii_bus); 2066 err_out: 2067 return err; 2068 } 2069 2070 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2071 { 2072 if (--mii_cnt == 0) { 2073 mdiobus_unregister(fep->mii_bus); 2074 mdiobus_free(fep->mii_bus); 2075 } 2076 } 2077 2078 static void fec_enet_get_drvinfo(struct net_device *ndev, 2079 struct ethtool_drvinfo *info) 2080 { 2081 struct fec_enet_private *fep = netdev_priv(ndev); 2082 2083 strlcpy(info->driver, fep->pdev->dev.driver->name, 2084 sizeof(info->driver)); 2085 strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); 2086 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2087 } 2088 2089 static int fec_enet_get_regs_len(struct net_device *ndev) 2090 { 2091 struct fec_enet_private *fep = netdev_priv(ndev); 2092 struct resource *r; 2093 int s = 0; 2094 2095 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2096 if (r) 2097 s = resource_size(r); 2098 2099 return s; 2100 } 2101 2102 /* List of registers that can be safety be read to dump them with ethtool */ 2103 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2104 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 2105 static u32 fec_enet_register_offset[] = { 2106 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2107 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2108 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2109 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2110 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2111 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2112 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2113 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2114 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2115 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2116 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2117 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2118 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2119 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2120 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2121 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2122 RMON_T_P_GTE2048, RMON_T_OCTETS, 2123 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2124 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2125 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2126 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2127 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2128 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2129 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2130 RMON_R_P_GTE2048, RMON_R_OCTETS, 2131 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2132 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2133 }; 2134 #else 2135 static u32 fec_enet_register_offset[] = { 2136 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2137 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2138 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2139 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2140 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2141 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2142 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2143 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2144 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2145 }; 2146 #endif 2147 2148 static void fec_enet_get_regs(struct net_device *ndev, 2149 struct ethtool_regs *regs, void *regbuf) 2150 { 2151 struct fec_enet_private *fep = netdev_priv(ndev); 2152 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2153 u32 *buf = (u32 *)regbuf; 2154 u32 i, off; 2155 2156 memset(buf, 0, regs->len); 2157 2158 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2159 off = fec_enet_register_offset[i] / 4; 2160 buf[off] = readl(&theregs[off]); 2161 } 2162 } 2163 2164 static int fec_enet_get_ts_info(struct net_device *ndev, 2165 struct ethtool_ts_info *info) 2166 { 2167 struct fec_enet_private *fep = netdev_priv(ndev); 2168 2169 if (fep->bufdesc_ex) { 2170 2171 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2172 SOF_TIMESTAMPING_RX_SOFTWARE | 2173 SOF_TIMESTAMPING_SOFTWARE | 2174 SOF_TIMESTAMPING_TX_HARDWARE | 2175 SOF_TIMESTAMPING_RX_HARDWARE | 2176 SOF_TIMESTAMPING_RAW_HARDWARE; 2177 if (fep->ptp_clock) 2178 info->phc_index = ptp_clock_index(fep->ptp_clock); 2179 else 2180 info->phc_index = -1; 2181 2182 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2183 (1 << HWTSTAMP_TX_ON); 2184 2185 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2186 (1 << HWTSTAMP_FILTER_ALL); 2187 return 0; 2188 } else { 2189 return ethtool_op_get_ts_info(ndev, info); 2190 } 2191 } 2192 2193 #if !defined(CONFIG_M5272) 2194 2195 static void fec_enet_get_pauseparam(struct net_device *ndev, 2196 struct ethtool_pauseparam *pause) 2197 { 2198 struct fec_enet_private *fep = netdev_priv(ndev); 2199 2200 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2201 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2202 pause->rx_pause = pause->tx_pause; 2203 } 2204 2205 static int fec_enet_set_pauseparam(struct net_device *ndev, 2206 struct ethtool_pauseparam *pause) 2207 { 2208 struct fec_enet_private *fep = netdev_priv(ndev); 2209 2210 if (!ndev->phydev) 2211 return -ENODEV; 2212 2213 if (pause->tx_pause != pause->rx_pause) { 2214 netdev_info(ndev, 2215 "hardware only support enable/disable both tx and rx"); 2216 return -EINVAL; 2217 } 2218 2219 fep->pause_flag = 0; 2220 2221 /* tx pause must be same as rx pause */ 2222 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2223 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2224 2225 if (pause->rx_pause || pause->autoneg) { 2226 ndev->phydev->supported |= ADVERTISED_Pause; 2227 ndev->phydev->advertising |= ADVERTISED_Pause; 2228 } else { 2229 ndev->phydev->supported &= ~ADVERTISED_Pause; 2230 ndev->phydev->advertising &= ~ADVERTISED_Pause; 2231 } 2232 2233 if (pause->autoneg) { 2234 if (netif_running(ndev)) 2235 fec_stop(ndev); 2236 phy_start_aneg(ndev->phydev); 2237 } 2238 if (netif_running(ndev)) { 2239 napi_disable(&fep->napi); 2240 netif_tx_lock_bh(ndev); 2241 fec_restart(ndev); 2242 netif_wake_queue(ndev); 2243 netif_tx_unlock_bh(ndev); 2244 napi_enable(&fep->napi); 2245 } 2246 2247 return 0; 2248 } 2249 2250 static const struct fec_stat { 2251 char name[ETH_GSTRING_LEN]; 2252 u16 offset; 2253 } fec_stats[] = { 2254 /* RMON TX */ 2255 { "tx_dropped", RMON_T_DROP }, 2256 { "tx_packets", RMON_T_PACKETS }, 2257 { "tx_broadcast", RMON_T_BC_PKT }, 2258 { "tx_multicast", RMON_T_MC_PKT }, 2259 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2260 { "tx_undersize", RMON_T_UNDERSIZE }, 2261 { "tx_oversize", RMON_T_OVERSIZE }, 2262 { "tx_fragment", RMON_T_FRAG }, 2263 { "tx_jabber", RMON_T_JAB }, 2264 { "tx_collision", RMON_T_COL }, 2265 { "tx_64byte", RMON_T_P64 }, 2266 { "tx_65to127byte", RMON_T_P65TO127 }, 2267 { "tx_128to255byte", RMON_T_P128TO255 }, 2268 { "tx_256to511byte", RMON_T_P256TO511 }, 2269 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2270 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2271 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2272 { "tx_octets", RMON_T_OCTETS }, 2273 2274 /* IEEE TX */ 2275 { "IEEE_tx_drop", IEEE_T_DROP }, 2276 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2277 { "IEEE_tx_1col", IEEE_T_1COL }, 2278 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2279 { "IEEE_tx_def", IEEE_T_DEF }, 2280 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2281 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2282 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2283 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2284 { "IEEE_tx_sqe", IEEE_T_SQE }, 2285 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2286 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2287 2288 /* RMON RX */ 2289 { "rx_packets", RMON_R_PACKETS }, 2290 { "rx_broadcast", RMON_R_BC_PKT }, 2291 { "rx_multicast", RMON_R_MC_PKT }, 2292 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2293 { "rx_undersize", RMON_R_UNDERSIZE }, 2294 { "rx_oversize", RMON_R_OVERSIZE }, 2295 { "rx_fragment", RMON_R_FRAG }, 2296 { "rx_jabber", RMON_R_JAB }, 2297 { "rx_64byte", RMON_R_P64 }, 2298 { "rx_65to127byte", RMON_R_P65TO127 }, 2299 { "rx_128to255byte", RMON_R_P128TO255 }, 2300 { "rx_256to511byte", RMON_R_P256TO511 }, 2301 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2302 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2303 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2304 { "rx_octets", RMON_R_OCTETS }, 2305 2306 /* IEEE RX */ 2307 { "IEEE_rx_drop", IEEE_R_DROP }, 2308 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2309 { "IEEE_rx_crc", IEEE_R_CRC }, 2310 { "IEEE_rx_align", IEEE_R_ALIGN }, 2311 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2312 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2313 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2314 }; 2315 2316 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2317 2318 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2319 { 2320 struct fec_enet_private *fep = netdev_priv(dev); 2321 int i; 2322 2323 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2324 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2325 } 2326 2327 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2328 struct ethtool_stats *stats, u64 *data) 2329 { 2330 struct fec_enet_private *fep = netdev_priv(dev); 2331 2332 if (netif_running(dev)) 2333 fec_enet_update_ethtool_stats(dev); 2334 2335 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2336 } 2337 2338 static void fec_enet_get_strings(struct net_device *netdev, 2339 u32 stringset, u8 *data) 2340 { 2341 int i; 2342 switch (stringset) { 2343 case ETH_SS_STATS: 2344 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2345 memcpy(data + i * ETH_GSTRING_LEN, 2346 fec_stats[i].name, ETH_GSTRING_LEN); 2347 break; 2348 } 2349 } 2350 2351 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2352 { 2353 switch (sset) { 2354 case ETH_SS_STATS: 2355 return ARRAY_SIZE(fec_stats); 2356 default: 2357 return -EOPNOTSUPP; 2358 } 2359 } 2360 2361 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2362 { 2363 struct fec_enet_private *fep = netdev_priv(dev); 2364 int i; 2365 2366 /* Disable MIB statistics counters */ 2367 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2368 2369 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2370 writel(0, fep->hwp + fec_stats[i].offset); 2371 2372 /* Don't disable MIB statistics counters */ 2373 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2374 } 2375 2376 #else /* !defined(CONFIG_M5272) */ 2377 #define FEC_STATS_SIZE 0 2378 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2379 { 2380 } 2381 2382 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2383 { 2384 } 2385 #endif /* !defined(CONFIG_M5272) */ 2386 2387 /* ITR clock source is enet system clock (clk_ahb). 2388 * TCTT unit is cycle_ns * 64 cycle 2389 * So, the ICTT value = X us / (cycle_ns * 64) 2390 */ 2391 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2392 { 2393 struct fec_enet_private *fep = netdev_priv(ndev); 2394 2395 return us * (fep->itr_clk_rate / 64000) / 1000; 2396 } 2397 2398 /* Set threshold for interrupt coalescing */ 2399 static void fec_enet_itr_coal_set(struct net_device *ndev) 2400 { 2401 struct fec_enet_private *fep = netdev_priv(ndev); 2402 int rx_itr, tx_itr; 2403 2404 /* Must be greater than zero to avoid unpredictable behavior */ 2405 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2406 !fep->tx_time_itr || !fep->tx_pkts_itr) 2407 return; 2408 2409 /* Select enet system clock as Interrupt Coalescing 2410 * timer Clock Source 2411 */ 2412 rx_itr = FEC_ITR_CLK_SEL; 2413 tx_itr = FEC_ITR_CLK_SEL; 2414 2415 /* set ICFT and ICTT */ 2416 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2417 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2418 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2419 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2420 2421 rx_itr |= FEC_ITR_EN; 2422 tx_itr |= FEC_ITR_EN; 2423 2424 writel(tx_itr, fep->hwp + FEC_TXIC0); 2425 writel(rx_itr, fep->hwp + FEC_RXIC0); 2426 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 2427 writel(tx_itr, fep->hwp + FEC_TXIC1); 2428 writel(rx_itr, fep->hwp + FEC_RXIC1); 2429 writel(tx_itr, fep->hwp + FEC_TXIC2); 2430 writel(rx_itr, fep->hwp + FEC_RXIC2); 2431 } 2432 } 2433 2434 static int 2435 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2436 { 2437 struct fec_enet_private *fep = netdev_priv(ndev); 2438 2439 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2440 return -EOPNOTSUPP; 2441 2442 ec->rx_coalesce_usecs = fep->rx_time_itr; 2443 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2444 2445 ec->tx_coalesce_usecs = fep->tx_time_itr; 2446 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2447 2448 return 0; 2449 } 2450 2451 static int 2452 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2453 { 2454 struct fec_enet_private *fep = netdev_priv(ndev); 2455 unsigned int cycle; 2456 2457 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2458 return -EOPNOTSUPP; 2459 2460 if (ec->rx_max_coalesced_frames > 255) { 2461 pr_err("Rx coalesced frames exceed hardware limitation\n"); 2462 return -EINVAL; 2463 } 2464 2465 if (ec->tx_max_coalesced_frames > 255) { 2466 pr_err("Tx coalesced frame exceed hardware limitation\n"); 2467 return -EINVAL; 2468 } 2469 2470 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); 2471 if (cycle > 0xFFFF) { 2472 pr_err("Rx coalesced usec exceed hardware limitation\n"); 2473 return -EINVAL; 2474 } 2475 2476 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); 2477 if (cycle > 0xFFFF) { 2478 pr_err("Rx coalesced usec exceed hardware limitation\n"); 2479 return -EINVAL; 2480 } 2481 2482 fep->rx_time_itr = ec->rx_coalesce_usecs; 2483 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2484 2485 fep->tx_time_itr = ec->tx_coalesce_usecs; 2486 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2487 2488 fec_enet_itr_coal_set(ndev); 2489 2490 return 0; 2491 } 2492 2493 static void fec_enet_itr_coal_init(struct net_device *ndev) 2494 { 2495 struct ethtool_coalesce ec; 2496 2497 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2498 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2499 2500 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2501 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2502 2503 fec_enet_set_coalesce(ndev, &ec); 2504 } 2505 2506 static int fec_enet_get_tunable(struct net_device *netdev, 2507 const struct ethtool_tunable *tuna, 2508 void *data) 2509 { 2510 struct fec_enet_private *fep = netdev_priv(netdev); 2511 int ret = 0; 2512 2513 switch (tuna->id) { 2514 case ETHTOOL_RX_COPYBREAK: 2515 *(u32 *)data = fep->rx_copybreak; 2516 break; 2517 default: 2518 ret = -EINVAL; 2519 break; 2520 } 2521 2522 return ret; 2523 } 2524 2525 static int fec_enet_set_tunable(struct net_device *netdev, 2526 const struct ethtool_tunable *tuna, 2527 const void *data) 2528 { 2529 struct fec_enet_private *fep = netdev_priv(netdev); 2530 int ret = 0; 2531 2532 switch (tuna->id) { 2533 case ETHTOOL_RX_COPYBREAK: 2534 fep->rx_copybreak = *(u32 *)data; 2535 break; 2536 default: 2537 ret = -EINVAL; 2538 break; 2539 } 2540 2541 return ret; 2542 } 2543 2544 static void 2545 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2546 { 2547 struct fec_enet_private *fep = netdev_priv(ndev); 2548 2549 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2550 wol->supported = WAKE_MAGIC; 2551 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2552 } else { 2553 wol->supported = wol->wolopts = 0; 2554 } 2555 } 2556 2557 static int 2558 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2559 { 2560 struct fec_enet_private *fep = netdev_priv(ndev); 2561 2562 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2563 return -EINVAL; 2564 2565 if (wol->wolopts & ~WAKE_MAGIC) 2566 return -EINVAL; 2567 2568 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2569 if (device_may_wakeup(&ndev->dev)) { 2570 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2571 if (fep->irq[0] > 0) 2572 enable_irq_wake(fep->irq[0]); 2573 } else { 2574 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2575 if (fep->irq[0] > 0) 2576 disable_irq_wake(fep->irq[0]); 2577 } 2578 2579 return 0; 2580 } 2581 2582 static const struct ethtool_ops fec_enet_ethtool_ops = { 2583 .get_drvinfo = fec_enet_get_drvinfo, 2584 .get_regs_len = fec_enet_get_regs_len, 2585 .get_regs = fec_enet_get_regs, 2586 .nway_reset = phy_ethtool_nway_reset, 2587 .get_link = ethtool_op_get_link, 2588 .get_coalesce = fec_enet_get_coalesce, 2589 .set_coalesce = fec_enet_set_coalesce, 2590 #ifndef CONFIG_M5272 2591 .get_pauseparam = fec_enet_get_pauseparam, 2592 .set_pauseparam = fec_enet_set_pauseparam, 2593 .get_strings = fec_enet_get_strings, 2594 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2595 .get_sset_count = fec_enet_get_sset_count, 2596 #endif 2597 .get_ts_info = fec_enet_get_ts_info, 2598 .get_tunable = fec_enet_get_tunable, 2599 .set_tunable = fec_enet_set_tunable, 2600 .get_wol = fec_enet_get_wol, 2601 .set_wol = fec_enet_set_wol, 2602 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2603 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2604 }; 2605 2606 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2607 { 2608 struct fec_enet_private *fep = netdev_priv(ndev); 2609 struct phy_device *phydev = ndev->phydev; 2610 2611 if (!netif_running(ndev)) 2612 return -EINVAL; 2613 2614 if (!phydev) 2615 return -ENODEV; 2616 2617 if (fep->bufdesc_ex) { 2618 if (cmd == SIOCSHWTSTAMP) 2619 return fec_ptp_set(ndev, rq); 2620 if (cmd == SIOCGHWTSTAMP) 2621 return fec_ptp_get(ndev, rq); 2622 } 2623 2624 return phy_mii_ioctl(phydev, rq, cmd); 2625 } 2626 2627 static void fec_enet_free_buffers(struct net_device *ndev) 2628 { 2629 struct fec_enet_private *fep = netdev_priv(ndev); 2630 unsigned int i; 2631 struct sk_buff *skb; 2632 struct bufdesc *bdp; 2633 struct fec_enet_priv_tx_q *txq; 2634 struct fec_enet_priv_rx_q *rxq; 2635 unsigned int q; 2636 2637 for (q = 0; q < fep->num_rx_queues; q++) { 2638 rxq = fep->rx_queue[q]; 2639 bdp = rxq->bd.base; 2640 for (i = 0; i < rxq->bd.ring_size; i++) { 2641 skb = rxq->rx_skbuff[i]; 2642 rxq->rx_skbuff[i] = NULL; 2643 if (skb) { 2644 dma_unmap_single(&fep->pdev->dev, 2645 fec32_to_cpu(bdp->cbd_bufaddr), 2646 FEC_ENET_RX_FRSIZE - fep->rx_align, 2647 DMA_FROM_DEVICE); 2648 dev_kfree_skb(skb); 2649 } 2650 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2651 } 2652 } 2653 2654 for (q = 0; q < fep->num_tx_queues; q++) { 2655 txq = fep->tx_queue[q]; 2656 bdp = txq->bd.base; 2657 for (i = 0; i < txq->bd.ring_size; i++) { 2658 kfree(txq->tx_bounce[i]); 2659 txq->tx_bounce[i] = NULL; 2660 skb = txq->tx_skbuff[i]; 2661 txq->tx_skbuff[i] = NULL; 2662 dev_kfree_skb(skb); 2663 } 2664 } 2665 } 2666 2667 static void fec_enet_free_queue(struct net_device *ndev) 2668 { 2669 struct fec_enet_private *fep = netdev_priv(ndev); 2670 int i; 2671 struct fec_enet_priv_tx_q *txq; 2672 2673 for (i = 0; i < fep->num_tx_queues; i++) 2674 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2675 txq = fep->tx_queue[i]; 2676 dma_free_coherent(&fep->pdev->dev, 2677 txq->bd.ring_size * TSO_HEADER_SIZE, 2678 txq->tso_hdrs, 2679 txq->tso_hdrs_dma); 2680 } 2681 2682 for (i = 0; i < fep->num_rx_queues; i++) 2683 kfree(fep->rx_queue[i]); 2684 for (i = 0; i < fep->num_tx_queues; i++) 2685 kfree(fep->tx_queue[i]); 2686 } 2687 2688 static int fec_enet_alloc_queue(struct net_device *ndev) 2689 { 2690 struct fec_enet_private *fep = netdev_priv(ndev); 2691 int i; 2692 int ret = 0; 2693 struct fec_enet_priv_tx_q *txq; 2694 2695 for (i = 0; i < fep->num_tx_queues; i++) { 2696 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 2697 if (!txq) { 2698 ret = -ENOMEM; 2699 goto alloc_failed; 2700 } 2701 2702 fep->tx_queue[i] = txq; 2703 txq->bd.ring_size = TX_RING_SIZE; 2704 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 2705 2706 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2707 txq->tx_wake_threshold = 2708 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 2709 2710 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 2711 txq->bd.ring_size * TSO_HEADER_SIZE, 2712 &txq->tso_hdrs_dma, 2713 GFP_KERNEL); 2714 if (!txq->tso_hdrs) { 2715 ret = -ENOMEM; 2716 goto alloc_failed; 2717 } 2718 } 2719 2720 for (i = 0; i < fep->num_rx_queues; i++) { 2721 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 2722 GFP_KERNEL); 2723 if (!fep->rx_queue[i]) { 2724 ret = -ENOMEM; 2725 goto alloc_failed; 2726 } 2727 2728 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 2729 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 2730 } 2731 return ret; 2732 2733 alloc_failed: 2734 fec_enet_free_queue(ndev); 2735 return ret; 2736 } 2737 2738 static int 2739 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 2740 { 2741 struct fec_enet_private *fep = netdev_priv(ndev); 2742 unsigned int i; 2743 struct sk_buff *skb; 2744 struct bufdesc *bdp; 2745 struct fec_enet_priv_rx_q *rxq; 2746 2747 rxq = fep->rx_queue[queue]; 2748 bdp = rxq->bd.base; 2749 for (i = 0; i < rxq->bd.ring_size; i++) { 2750 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2751 if (!skb) 2752 goto err_alloc; 2753 2754 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 2755 dev_kfree_skb(skb); 2756 goto err_alloc; 2757 } 2758 2759 rxq->rx_skbuff[i] = skb; 2760 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 2761 2762 if (fep->bufdesc_ex) { 2763 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2764 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 2765 } 2766 2767 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2768 } 2769 2770 /* Set the last buffer to wrap. */ 2771 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 2772 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2773 return 0; 2774 2775 err_alloc: 2776 fec_enet_free_buffers(ndev); 2777 return -ENOMEM; 2778 } 2779 2780 static int 2781 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 2782 { 2783 struct fec_enet_private *fep = netdev_priv(ndev); 2784 unsigned int i; 2785 struct bufdesc *bdp; 2786 struct fec_enet_priv_tx_q *txq; 2787 2788 txq = fep->tx_queue[queue]; 2789 bdp = txq->bd.base; 2790 for (i = 0; i < txq->bd.ring_size; i++) { 2791 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2792 if (!txq->tx_bounce[i]) 2793 goto err_alloc; 2794 2795 bdp->cbd_sc = cpu_to_fec16(0); 2796 bdp->cbd_bufaddr = cpu_to_fec32(0); 2797 2798 if (fep->bufdesc_ex) { 2799 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2800 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 2801 } 2802 2803 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 2804 } 2805 2806 /* Set the last buffer to wrap. */ 2807 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 2808 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2809 2810 return 0; 2811 2812 err_alloc: 2813 fec_enet_free_buffers(ndev); 2814 return -ENOMEM; 2815 } 2816 2817 static int fec_enet_alloc_buffers(struct net_device *ndev) 2818 { 2819 struct fec_enet_private *fep = netdev_priv(ndev); 2820 unsigned int i; 2821 2822 for (i = 0; i < fep->num_rx_queues; i++) 2823 if (fec_enet_alloc_rxq_buffers(ndev, i)) 2824 return -ENOMEM; 2825 2826 for (i = 0; i < fep->num_tx_queues; i++) 2827 if (fec_enet_alloc_txq_buffers(ndev, i)) 2828 return -ENOMEM; 2829 return 0; 2830 } 2831 2832 static int 2833 fec_enet_open(struct net_device *ndev) 2834 { 2835 struct fec_enet_private *fep = netdev_priv(ndev); 2836 int ret; 2837 2838 ret = pm_runtime_get_sync(&fep->pdev->dev); 2839 if (ret < 0) 2840 return ret; 2841 2842 pinctrl_pm_select_default_state(&fep->pdev->dev); 2843 ret = fec_enet_clk_enable(ndev, true); 2844 if (ret) 2845 goto clk_enable; 2846 2847 /* I should reset the ring buffers here, but I don't yet know 2848 * a simple way to do that. 2849 */ 2850 2851 ret = fec_enet_alloc_buffers(ndev); 2852 if (ret) 2853 goto err_enet_alloc; 2854 2855 /* Init MAC prior to mii bus probe */ 2856 fec_restart(ndev); 2857 2858 /* Probe and connect to PHY when open the interface */ 2859 ret = fec_enet_mii_probe(ndev); 2860 if (ret) 2861 goto err_enet_mii_probe; 2862 2863 if (fep->quirks & FEC_QUIRK_ERR006687) 2864 imx6q_cpuidle_fec_irqs_used(); 2865 2866 napi_enable(&fep->napi); 2867 phy_start(ndev->phydev); 2868 netif_tx_start_all_queues(ndev); 2869 2870 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 2871 FEC_WOL_FLAG_ENABLE); 2872 2873 return 0; 2874 2875 err_enet_mii_probe: 2876 fec_enet_free_buffers(ndev); 2877 err_enet_alloc: 2878 fec_enet_clk_enable(ndev, false); 2879 clk_enable: 2880 pm_runtime_mark_last_busy(&fep->pdev->dev); 2881 pm_runtime_put_autosuspend(&fep->pdev->dev); 2882 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2883 return ret; 2884 } 2885 2886 static int 2887 fec_enet_close(struct net_device *ndev) 2888 { 2889 struct fec_enet_private *fep = netdev_priv(ndev); 2890 2891 phy_stop(ndev->phydev); 2892 2893 if (netif_device_present(ndev)) { 2894 napi_disable(&fep->napi); 2895 netif_tx_disable(ndev); 2896 fec_stop(ndev); 2897 } 2898 2899 phy_disconnect(ndev->phydev); 2900 2901 if (fep->quirks & FEC_QUIRK_ERR006687) 2902 imx6q_cpuidle_fec_irqs_unused(); 2903 2904 fec_enet_update_ethtool_stats(ndev); 2905 2906 fec_enet_clk_enable(ndev, false); 2907 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2908 pm_runtime_mark_last_busy(&fep->pdev->dev); 2909 pm_runtime_put_autosuspend(&fep->pdev->dev); 2910 2911 fec_enet_free_buffers(ndev); 2912 2913 return 0; 2914 } 2915 2916 /* Set or clear the multicast filter for this adaptor. 2917 * Skeleton taken from sunlance driver. 2918 * The CPM Ethernet implementation allows Multicast as well as individual 2919 * MAC address filtering. Some of the drivers check to make sure it is 2920 * a group multicast address, and discard those that are not. I guess I 2921 * will do the same for now, but just remove the test if you want 2922 * individual filtering as well (do the upper net layers want or support 2923 * this kind of feature?). 2924 */ 2925 2926 #define FEC_HASH_BITS 6 /* #bits in hash */ 2927 #define CRC32_POLY 0xEDB88320 2928 2929 static void set_multicast_list(struct net_device *ndev) 2930 { 2931 struct fec_enet_private *fep = netdev_priv(ndev); 2932 struct netdev_hw_addr *ha; 2933 unsigned int i, bit, data, crc, tmp; 2934 unsigned char hash; 2935 unsigned int hash_high = 0, hash_low = 0; 2936 2937 if (ndev->flags & IFF_PROMISC) { 2938 tmp = readl(fep->hwp + FEC_R_CNTRL); 2939 tmp |= 0x8; 2940 writel(tmp, fep->hwp + FEC_R_CNTRL); 2941 return; 2942 } 2943 2944 tmp = readl(fep->hwp + FEC_R_CNTRL); 2945 tmp &= ~0x8; 2946 writel(tmp, fep->hwp + FEC_R_CNTRL); 2947 2948 if (ndev->flags & IFF_ALLMULTI) { 2949 /* Catch all multicast addresses, so set the 2950 * filter to all 1's 2951 */ 2952 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2953 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2954 2955 return; 2956 } 2957 2958 /* Add the addresses in hash register */ 2959 netdev_for_each_mc_addr(ha, ndev) { 2960 /* calculate crc32 value of mac address */ 2961 crc = 0xffffffff; 2962 2963 for (i = 0; i < ndev->addr_len; i++) { 2964 data = ha->addr[i]; 2965 for (bit = 0; bit < 8; bit++, data >>= 1) { 2966 crc = (crc >> 1) ^ 2967 (((crc ^ data) & 1) ? CRC32_POLY : 0); 2968 } 2969 } 2970 2971 /* only upper 6 bits (FEC_HASH_BITS) are used 2972 * which point to specific bit in the hash registers 2973 */ 2974 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 2975 2976 if (hash > 31) 2977 hash_high |= 1 << (hash - 32); 2978 else 2979 hash_low |= 1 << hash; 2980 } 2981 2982 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2983 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2984 } 2985 2986 /* Set a MAC change in hardware. */ 2987 static int 2988 fec_set_mac_address(struct net_device *ndev, void *p) 2989 { 2990 struct fec_enet_private *fep = netdev_priv(ndev); 2991 struct sockaddr *addr = p; 2992 2993 if (addr) { 2994 if (!is_valid_ether_addr(addr->sa_data)) 2995 return -EADDRNOTAVAIL; 2996 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 2997 } 2998 2999 /* Add netif status check here to avoid system hang in below case: 3000 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3001 * After ethx down, fec all clocks are gated off and then register 3002 * access causes system hang. 3003 */ 3004 if (!netif_running(ndev)) 3005 return 0; 3006 3007 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3008 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3009 fep->hwp + FEC_ADDR_LOW); 3010 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3011 fep->hwp + FEC_ADDR_HIGH); 3012 return 0; 3013 } 3014 3015 #ifdef CONFIG_NET_POLL_CONTROLLER 3016 /** 3017 * fec_poll_controller - FEC Poll controller function 3018 * @dev: The FEC network adapter 3019 * 3020 * Polled functionality used by netconsole and others in non interrupt mode 3021 * 3022 */ 3023 static void fec_poll_controller(struct net_device *dev) 3024 { 3025 int i; 3026 struct fec_enet_private *fep = netdev_priv(dev); 3027 3028 for (i = 0; i < FEC_IRQ_NUM; i++) { 3029 if (fep->irq[i] > 0) { 3030 disable_irq(fep->irq[i]); 3031 fec_enet_interrupt(fep->irq[i], dev); 3032 enable_irq(fep->irq[i]); 3033 } 3034 } 3035 } 3036 #endif 3037 3038 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3039 netdev_features_t features) 3040 { 3041 struct fec_enet_private *fep = netdev_priv(netdev); 3042 netdev_features_t changed = features ^ netdev->features; 3043 3044 netdev->features = features; 3045 3046 /* Receive checksum has been changed */ 3047 if (changed & NETIF_F_RXCSUM) { 3048 if (features & NETIF_F_RXCSUM) 3049 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3050 else 3051 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3052 } 3053 } 3054 3055 static int fec_set_features(struct net_device *netdev, 3056 netdev_features_t features) 3057 { 3058 struct fec_enet_private *fep = netdev_priv(netdev); 3059 netdev_features_t changed = features ^ netdev->features; 3060 3061 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3062 napi_disable(&fep->napi); 3063 netif_tx_lock_bh(netdev); 3064 fec_stop(netdev); 3065 fec_enet_set_netdev_features(netdev, features); 3066 fec_restart(netdev); 3067 netif_tx_wake_all_queues(netdev); 3068 netif_tx_unlock_bh(netdev); 3069 napi_enable(&fep->napi); 3070 } else { 3071 fec_enet_set_netdev_features(netdev, features); 3072 } 3073 3074 return 0; 3075 } 3076 3077 static const struct net_device_ops fec_netdev_ops = { 3078 .ndo_open = fec_enet_open, 3079 .ndo_stop = fec_enet_close, 3080 .ndo_start_xmit = fec_enet_start_xmit, 3081 .ndo_set_rx_mode = set_multicast_list, 3082 .ndo_validate_addr = eth_validate_addr, 3083 .ndo_tx_timeout = fec_timeout, 3084 .ndo_set_mac_address = fec_set_mac_address, 3085 .ndo_do_ioctl = fec_enet_ioctl, 3086 #ifdef CONFIG_NET_POLL_CONTROLLER 3087 .ndo_poll_controller = fec_poll_controller, 3088 #endif 3089 .ndo_set_features = fec_set_features, 3090 }; 3091 3092 static const unsigned short offset_des_active_rxq[] = { 3093 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3094 }; 3095 3096 static const unsigned short offset_des_active_txq[] = { 3097 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3098 }; 3099 3100 /* 3101 * XXX: We need to clean up on failure exits here. 3102 * 3103 */ 3104 static int fec_enet_init(struct net_device *ndev) 3105 { 3106 struct fec_enet_private *fep = netdev_priv(ndev); 3107 struct bufdesc *cbd_base; 3108 dma_addr_t bd_dma; 3109 int bd_size; 3110 unsigned int i; 3111 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3112 sizeof(struct bufdesc); 3113 unsigned dsize_log2 = __fls(dsize); 3114 3115 WARN_ON(dsize != (1 << dsize_log2)); 3116 #if defined(CONFIG_ARM) 3117 fep->rx_align = 0xf; 3118 fep->tx_align = 0xf; 3119 #else 3120 fep->rx_align = 0x3; 3121 fep->tx_align = 0x3; 3122 #endif 3123 3124 fec_enet_alloc_queue(ndev); 3125 3126 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3127 3128 /* Allocate memory for buffer descriptors. */ 3129 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3130 GFP_KERNEL); 3131 if (!cbd_base) { 3132 return -ENOMEM; 3133 } 3134 3135 memset(cbd_base, 0, bd_size); 3136 3137 /* Get the Ethernet address */ 3138 fec_get_mac(ndev); 3139 /* make sure MAC we just acquired is programmed into the hw */ 3140 fec_set_mac_address(ndev, NULL); 3141 3142 /* Set receive and transmit descriptor base. */ 3143 for (i = 0; i < fep->num_rx_queues; i++) { 3144 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3145 unsigned size = dsize * rxq->bd.ring_size; 3146 3147 rxq->bd.qid = i; 3148 rxq->bd.base = cbd_base; 3149 rxq->bd.cur = cbd_base; 3150 rxq->bd.dma = bd_dma; 3151 rxq->bd.dsize = dsize; 3152 rxq->bd.dsize_log2 = dsize_log2; 3153 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3154 bd_dma += size; 3155 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3156 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3157 } 3158 3159 for (i = 0; i < fep->num_tx_queues; i++) { 3160 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3161 unsigned size = dsize * txq->bd.ring_size; 3162 3163 txq->bd.qid = i; 3164 txq->bd.base = cbd_base; 3165 txq->bd.cur = cbd_base; 3166 txq->bd.dma = bd_dma; 3167 txq->bd.dsize = dsize; 3168 txq->bd.dsize_log2 = dsize_log2; 3169 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3170 bd_dma += size; 3171 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3172 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3173 } 3174 3175 3176 /* The FEC Ethernet specific entries in the device structure */ 3177 ndev->watchdog_timeo = TX_TIMEOUT; 3178 ndev->netdev_ops = &fec_netdev_ops; 3179 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3180 3181 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3182 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3183 3184 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3185 /* enable hw VLAN support */ 3186 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3187 3188 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3189 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3190 3191 /* enable hw accelerator */ 3192 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3193 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3194 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3195 } 3196 3197 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 3198 fep->tx_align = 0; 3199 fep->rx_align = 0x3f; 3200 } 3201 3202 ndev->hw_features = ndev->features; 3203 3204 fec_restart(ndev); 3205 3206 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 3207 fec_enet_clear_ethtool_stats(ndev); 3208 else 3209 fec_enet_update_ethtool_stats(ndev); 3210 3211 return 0; 3212 } 3213 3214 #ifdef CONFIG_OF 3215 static int fec_reset_phy(struct platform_device *pdev) 3216 { 3217 int err, phy_reset; 3218 bool active_high = false; 3219 int msec = 1, phy_post_delay = 0; 3220 struct device_node *np = pdev->dev.of_node; 3221 3222 if (!np) 3223 return 0; 3224 3225 err = of_property_read_u32(np, "phy-reset-duration", &msec); 3226 /* A sane reset duration should not be longer than 1s */ 3227 if (!err && msec > 1000) 3228 msec = 1; 3229 3230 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3231 if (phy_reset == -EPROBE_DEFER) 3232 return phy_reset; 3233 else if (!gpio_is_valid(phy_reset)) 3234 return 0; 3235 3236 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 3237 /* valid reset duration should be less than 1s */ 3238 if (!err && phy_post_delay > 1000) 3239 return -EINVAL; 3240 3241 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3242 3243 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3244 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3245 "phy-reset"); 3246 if (err) { 3247 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3248 return err; 3249 } 3250 3251 if (msec > 20) 3252 msleep(msec); 3253 else 3254 usleep_range(msec * 1000, msec * 1000 + 1000); 3255 3256 gpio_set_value_cansleep(phy_reset, !active_high); 3257 3258 if (!phy_post_delay) 3259 return 0; 3260 3261 if (phy_post_delay > 20) 3262 msleep(phy_post_delay); 3263 else 3264 usleep_range(phy_post_delay * 1000, 3265 phy_post_delay * 1000 + 1000); 3266 3267 return 0; 3268 } 3269 #else /* CONFIG_OF */ 3270 static int fec_reset_phy(struct platform_device *pdev) 3271 { 3272 /* 3273 * In case of platform probe, the reset has been done 3274 * by machine code. 3275 */ 3276 return 0; 3277 } 3278 #endif /* CONFIG_OF */ 3279 3280 static void 3281 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3282 { 3283 struct device_node *np = pdev->dev.of_node; 3284 3285 *num_tx = *num_rx = 1; 3286 3287 if (!np || !of_device_is_available(np)) 3288 return; 3289 3290 /* parse the num of tx and rx queues */ 3291 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3292 3293 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3294 3295 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3296 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3297 *num_tx); 3298 *num_tx = 1; 3299 return; 3300 } 3301 3302 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3303 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3304 *num_rx); 3305 *num_rx = 1; 3306 return; 3307 } 3308 3309 } 3310 3311 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 3312 { 3313 int irq_cnt = platform_irq_count(pdev); 3314 3315 if (irq_cnt > FEC_IRQ_NUM) 3316 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 3317 else if (irq_cnt == 2) 3318 irq_cnt = 1; /* last for pps */ 3319 else if (irq_cnt <= 0) 3320 irq_cnt = 1; /* At least 1 irq is needed */ 3321 return irq_cnt; 3322 } 3323 3324 static int 3325 fec_probe(struct platform_device *pdev) 3326 { 3327 struct fec_enet_private *fep; 3328 struct fec_platform_data *pdata; 3329 struct net_device *ndev; 3330 int i, irq, ret = 0; 3331 struct resource *r; 3332 const struct of_device_id *of_id; 3333 static int dev_id; 3334 struct device_node *np = pdev->dev.of_node, *phy_node; 3335 int num_tx_qs; 3336 int num_rx_qs; 3337 char irq_name[8]; 3338 int irq_cnt; 3339 3340 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3341 3342 /* Init network device */ 3343 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 3344 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 3345 if (!ndev) 3346 return -ENOMEM; 3347 3348 SET_NETDEV_DEV(ndev, &pdev->dev); 3349 3350 /* setup board info structure */ 3351 fep = netdev_priv(ndev); 3352 3353 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3354 if (of_id) 3355 pdev->id_entry = of_id->data; 3356 fep->quirks = pdev->id_entry->driver_data; 3357 3358 fep->netdev = ndev; 3359 fep->num_rx_queues = num_rx_qs; 3360 fep->num_tx_queues = num_tx_qs; 3361 3362 #if !defined(CONFIG_M5272) 3363 /* default enable pause frame auto negotiation */ 3364 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3365 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3366 #endif 3367 3368 /* Select default pin state */ 3369 pinctrl_pm_select_default_state(&pdev->dev); 3370 3371 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3372 fep->hwp = devm_ioremap_resource(&pdev->dev, r); 3373 if (IS_ERR(fep->hwp)) { 3374 ret = PTR_ERR(fep->hwp); 3375 goto failed_ioremap; 3376 } 3377 3378 fep->pdev = pdev; 3379 fep->dev_id = dev_id++; 3380 3381 platform_set_drvdata(pdev, ndev); 3382 3383 if ((of_machine_is_compatible("fsl,imx6q") || 3384 of_machine_is_compatible("fsl,imx6dl")) && 3385 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3386 fep->quirks |= FEC_QUIRK_ERR006687; 3387 3388 if (of_get_property(np, "fsl,magic-packet", NULL)) 3389 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3390 3391 phy_node = of_parse_phandle(np, "phy-handle", 0); 3392 if (!phy_node && of_phy_is_fixed_link(np)) { 3393 ret = of_phy_register_fixed_link(np); 3394 if (ret < 0) { 3395 dev_err(&pdev->dev, 3396 "broken fixed-link specification\n"); 3397 goto failed_phy; 3398 } 3399 phy_node = of_node_get(np); 3400 } 3401 fep->phy_node = phy_node; 3402 3403 ret = of_get_phy_mode(pdev->dev.of_node); 3404 if (ret < 0) { 3405 pdata = dev_get_platdata(&pdev->dev); 3406 if (pdata) 3407 fep->phy_interface = pdata->phy; 3408 else 3409 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3410 } else { 3411 fep->phy_interface = ret; 3412 } 3413 3414 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3415 if (IS_ERR(fep->clk_ipg)) { 3416 ret = PTR_ERR(fep->clk_ipg); 3417 goto failed_clk; 3418 } 3419 3420 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3421 if (IS_ERR(fep->clk_ahb)) { 3422 ret = PTR_ERR(fep->clk_ahb); 3423 goto failed_clk; 3424 } 3425 3426 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3427 3428 /* enet_out is optional, depends on board */ 3429 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3430 if (IS_ERR(fep->clk_enet_out)) 3431 fep->clk_enet_out = NULL; 3432 3433 fep->ptp_clk_on = false; 3434 mutex_init(&fep->ptp_clk_mutex); 3435 3436 /* clk_ref is optional, depends on board */ 3437 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3438 if (IS_ERR(fep->clk_ref)) 3439 fep->clk_ref = NULL; 3440 3441 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3442 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3443 if (IS_ERR(fep->clk_ptp)) { 3444 fep->clk_ptp = NULL; 3445 fep->bufdesc_ex = false; 3446 } 3447 3448 ret = fec_enet_clk_enable(ndev, true); 3449 if (ret) 3450 goto failed_clk; 3451 3452 ret = clk_prepare_enable(fep->clk_ipg); 3453 if (ret) 3454 goto failed_clk_ipg; 3455 3456 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); 3457 if (!IS_ERR(fep->reg_phy)) { 3458 ret = regulator_enable(fep->reg_phy); 3459 if (ret) { 3460 dev_err(&pdev->dev, 3461 "Failed to enable phy regulator: %d\n", ret); 3462 clk_disable_unprepare(fep->clk_ipg); 3463 goto failed_regulator; 3464 } 3465 } else { 3466 fep->reg_phy = NULL; 3467 } 3468 3469 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3470 pm_runtime_use_autosuspend(&pdev->dev); 3471 pm_runtime_get_noresume(&pdev->dev); 3472 pm_runtime_set_active(&pdev->dev); 3473 pm_runtime_enable(&pdev->dev); 3474 3475 ret = fec_reset_phy(pdev); 3476 if (ret) 3477 goto failed_reset; 3478 3479 irq_cnt = fec_enet_get_irq_cnt(pdev); 3480 if (fep->bufdesc_ex) 3481 fec_ptp_init(pdev, irq_cnt); 3482 3483 ret = fec_enet_init(ndev); 3484 if (ret) 3485 goto failed_init; 3486 3487 for (i = 0; i < irq_cnt; i++) { 3488 sprintf(irq_name, "int%d", i); 3489 irq = platform_get_irq_byname(pdev, irq_name); 3490 if (irq < 0) 3491 irq = platform_get_irq(pdev, i); 3492 if (irq < 0) { 3493 ret = irq; 3494 goto failed_irq; 3495 } 3496 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3497 0, pdev->name, ndev); 3498 if (ret) 3499 goto failed_irq; 3500 3501 fep->irq[i] = irq; 3502 } 3503 3504 init_completion(&fep->mdio_done); 3505 ret = fec_enet_mii_init(pdev); 3506 if (ret) 3507 goto failed_mii_init; 3508 3509 /* Carrier starts down, phylib will bring it up */ 3510 netif_carrier_off(ndev); 3511 fec_enet_clk_enable(ndev, false); 3512 pinctrl_pm_select_sleep_state(&pdev->dev); 3513 3514 ret = register_netdev(ndev); 3515 if (ret) 3516 goto failed_register; 3517 3518 device_init_wakeup(&ndev->dev, fep->wol_flag & 3519 FEC_WOL_HAS_MAGIC_PACKET); 3520 3521 if (fep->bufdesc_ex && fep->ptp_clock) 3522 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3523 3524 fep->rx_copybreak = COPYBREAK_DEFAULT; 3525 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3526 3527 pm_runtime_mark_last_busy(&pdev->dev); 3528 pm_runtime_put_autosuspend(&pdev->dev); 3529 3530 return 0; 3531 3532 failed_register: 3533 fec_enet_mii_remove(fep); 3534 failed_mii_init: 3535 failed_irq: 3536 failed_init: 3537 fec_ptp_stop(pdev); 3538 if (fep->reg_phy) 3539 regulator_disable(fep->reg_phy); 3540 failed_reset: 3541 pm_runtime_put(&pdev->dev); 3542 pm_runtime_disable(&pdev->dev); 3543 failed_regulator: 3544 failed_clk_ipg: 3545 fec_enet_clk_enable(ndev, false); 3546 failed_clk: 3547 if (of_phy_is_fixed_link(np)) 3548 of_phy_deregister_fixed_link(np); 3549 failed_phy: 3550 of_node_put(phy_node); 3551 failed_ioremap: 3552 free_netdev(ndev); 3553 3554 return ret; 3555 } 3556 3557 static int 3558 fec_drv_remove(struct platform_device *pdev) 3559 { 3560 struct net_device *ndev = platform_get_drvdata(pdev); 3561 struct fec_enet_private *fep = netdev_priv(ndev); 3562 struct device_node *np = pdev->dev.of_node; 3563 3564 cancel_work_sync(&fep->tx_timeout_work); 3565 fec_ptp_stop(pdev); 3566 unregister_netdev(ndev); 3567 fec_enet_mii_remove(fep); 3568 if (fep->reg_phy) 3569 regulator_disable(fep->reg_phy); 3570 if (of_phy_is_fixed_link(np)) 3571 of_phy_deregister_fixed_link(np); 3572 of_node_put(fep->phy_node); 3573 free_netdev(ndev); 3574 3575 return 0; 3576 } 3577 3578 static int __maybe_unused fec_suspend(struct device *dev) 3579 { 3580 struct net_device *ndev = dev_get_drvdata(dev); 3581 struct fec_enet_private *fep = netdev_priv(ndev); 3582 3583 rtnl_lock(); 3584 if (netif_running(ndev)) { 3585 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 3586 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 3587 phy_stop(ndev->phydev); 3588 napi_disable(&fep->napi); 3589 netif_tx_lock_bh(ndev); 3590 netif_device_detach(ndev); 3591 netif_tx_unlock_bh(ndev); 3592 fec_stop(ndev); 3593 fec_enet_clk_enable(ndev, false); 3594 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3595 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3596 } 3597 rtnl_unlock(); 3598 3599 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3600 regulator_disable(fep->reg_phy); 3601 3602 /* SOC supply clock to phy, when clock is disabled, phy link down 3603 * SOC control phy regulator, when regulator is disabled, phy link down 3604 */ 3605 if (fep->clk_enet_out || fep->reg_phy) 3606 fep->link = 0; 3607 3608 return 0; 3609 } 3610 3611 static int __maybe_unused fec_resume(struct device *dev) 3612 { 3613 struct net_device *ndev = dev_get_drvdata(dev); 3614 struct fec_enet_private *fep = netdev_priv(ndev); 3615 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 3616 int ret; 3617 int val; 3618 3619 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 3620 ret = regulator_enable(fep->reg_phy); 3621 if (ret) 3622 return ret; 3623 } 3624 3625 rtnl_lock(); 3626 if (netif_running(ndev)) { 3627 ret = fec_enet_clk_enable(ndev, true); 3628 if (ret) { 3629 rtnl_unlock(); 3630 goto failed_clk; 3631 } 3632 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 3633 if (pdata && pdata->sleep_mode_enable) 3634 pdata->sleep_mode_enable(false); 3635 val = readl(fep->hwp + FEC_ECNTRL); 3636 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 3637 writel(val, fep->hwp + FEC_ECNTRL); 3638 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 3639 } else { 3640 pinctrl_pm_select_default_state(&fep->pdev->dev); 3641 } 3642 fec_restart(ndev); 3643 netif_tx_lock_bh(ndev); 3644 netif_device_attach(ndev); 3645 netif_tx_unlock_bh(ndev); 3646 napi_enable(&fep->napi); 3647 phy_start(ndev->phydev); 3648 } 3649 rtnl_unlock(); 3650 3651 return 0; 3652 3653 failed_clk: 3654 if (fep->reg_phy) 3655 regulator_disable(fep->reg_phy); 3656 return ret; 3657 } 3658 3659 static int __maybe_unused fec_runtime_suspend(struct device *dev) 3660 { 3661 struct net_device *ndev = dev_get_drvdata(dev); 3662 struct fec_enet_private *fep = netdev_priv(ndev); 3663 3664 clk_disable_unprepare(fep->clk_ipg); 3665 3666 return 0; 3667 } 3668 3669 static int __maybe_unused fec_runtime_resume(struct device *dev) 3670 { 3671 struct net_device *ndev = dev_get_drvdata(dev); 3672 struct fec_enet_private *fep = netdev_priv(ndev); 3673 3674 return clk_prepare_enable(fep->clk_ipg); 3675 } 3676 3677 static const struct dev_pm_ops fec_pm_ops = { 3678 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 3679 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 3680 }; 3681 3682 static struct platform_driver fec_driver = { 3683 .driver = { 3684 .name = DRIVER_NAME, 3685 .pm = &fec_pm_ops, 3686 .of_match_table = fec_dt_ids, 3687 }, 3688 .id_table = fec_devtype, 3689 .probe = fec_probe, 3690 .remove = fec_drv_remove, 3691 }; 3692 3693 module_platform_driver(fec_driver); 3694 3695 MODULE_ALIAS("platform:"DRIVER_NAME); 3696 MODULE_LICENSE("GPL"); 3697