1 /* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 * 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/string.h> 27 #include <linux/ptrace.h> 28 #include <linux/errno.h> 29 #include <linux/ioport.h> 30 #include <linux/slab.h> 31 #include <linux/interrupt.h> 32 #include <linux/delay.h> 33 #include <linux/netdevice.h> 34 #include <linux/etherdevice.h> 35 #include <linux/skbuff.h> 36 #include <linux/in.h> 37 #include <linux/ip.h> 38 #include <net/ip.h> 39 #include <net/tso.h> 40 #include <linux/tcp.h> 41 #include <linux/udp.h> 42 #include <linux/icmp.h> 43 #include <linux/spinlock.h> 44 #include <linux/workqueue.h> 45 #include <linux/bitops.h> 46 #include <linux/io.h> 47 #include <linux/irq.h> 48 #include <linux/clk.h> 49 #include <linux/platform_device.h> 50 #include <linux/phy.h> 51 #include <linux/fec.h> 52 #include <linux/of.h> 53 #include <linux/of_device.h> 54 #include <linux/of_gpio.h> 55 #include <linux/of_mdio.h> 56 #include <linux/of_net.h> 57 #include <linux/regulator/consumer.h> 58 #include <linux/if_vlan.h> 59 #include <linux/pinctrl/consumer.h> 60 #include <linux/prefetch.h> 61 62 #include <asm/cacheflush.h> 63 64 #include "fec.h" 65 66 static void set_multicast_list(struct net_device *ndev); 67 static void fec_enet_itr_coal_init(struct net_device *ndev); 68 69 #define DRIVER_NAME "fec" 70 71 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0)) 72 73 /* Pause frame feild and FIFO threshold */ 74 #define FEC_ENET_FCE (1 << 5) 75 #define FEC_ENET_RSEM_V 0x84 76 #define FEC_ENET_RSFL_V 16 77 #define FEC_ENET_RAEM_V 0x8 78 #define FEC_ENET_RAFL_V 0x8 79 #define FEC_ENET_OPD_V 0xFFF0 80 81 static struct platform_device_id fec_devtype[] = { 82 { 83 /* keep it for coldfire */ 84 .name = DRIVER_NAME, 85 .driver_data = 0, 86 }, { 87 .name = "imx25-fec", 88 .driver_data = FEC_QUIRK_USE_GASKET, 89 }, { 90 .name = "imx27-fec", 91 .driver_data = 0, 92 }, { 93 .name = "imx28-fec", 94 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, 95 }, { 96 .name = "imx6q-fec", 97 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 98 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 99 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358, 100 }, { 101 .name = "mvf600-fec", 102 .driver_data = FEC_QUIRK_ENET_MAC, 103 }, { 104 .name = "imx6sx-fec", 105 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 106 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 107 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 108 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE, 109 }, { 110 /* sentinel */ 111 } 112 }; 113 MODULE_DEVICE_TABLE(platform, fec_devtype); 114 115 enum imx_fec_type { 116 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 117 IMX27_FEC, /* runs on i.mx27/35/51 */ 118 IMX28_FEC, 119 IMX6Q_FEC, 120 MVF600_FEC, 121 IMX6SX_FEC, 122 }; 123 124 static const struct of_device_id fec_dt_ids[] = { 125 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 126 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 127 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 128 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 129 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 130 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 131 { /* sentinel */ } 132 }; 133 MODULE_DEVICE_TABLE(of, fec_dt_ids); 134 135 static unsigned char macaddr[ETH_ALEN]; 136 module_param_array(macaddr, byte, NULL, 0); 137 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 138 139 #if defined(CONFIG_M5272) 140 /* 141 * Some hardware gets it MAC address out of local flash memory. 142 * if this is non-zero then assume it is the address to get MAC from. 143 */ 144 #if defined(CONFIG_NETtel) 145 #define FEC_FLASHMAC 0xf0006006 146 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 147 #define FEC_FLASHMAC 0xf0006000 148 #elif defined(CONFIG_CANCam) 149 #define FEC_FLASHMAC 0xf0020000 150 #elif defined (CONFIG_M5272C3) 151 #define FEC_FLASHMAC (0xffe04000 + 4) 152 #elif defined(CONFIG_MOD5272) 153 #define FEC_FLASHMAC 0xffc0406b 154 #else 155 #define FEC_FLASHMAC 0 156 #endif 157 #endif /* CONFIG_M5272 */ 158 159 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 160 */ 161 #define PKT_MAXBUF_SIZE 1522 162 #define PKT_MINBUF_SIZE 64 163 #define PKT_MAXBLR_SIZE 1536 164 165 /* FEC receive acceleration */ 166 #define FEC_RACC_IPDIS (1 << 1) 167 #define FEC_RACC_PRODIS (1 << 2) 168 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 169 170 /* 171 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 172 * size bits. Other FEC hardware does not, so we need to take that into 173 * account when setting it. 174 */ 175 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 176 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 177 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 178 #else 179 #define OPT_FRAME_SIZE 0 180 #endif 181 182 /* FEC MII MMFR bits definition */ 183 #define FEC_MMFR_ST (1 << 30) 184 #define FEC_MMFR_OP_READ (2 << 28) 185 #define FEC_MMFR_OP_WRITE (1 << 28) 186 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 187 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 188 #define FEC_MMFR_TA (2 << 16) 189 #define FEC_MMFR_DATA(v) (v & 0xffff) 190 191 #define FEC_MII_TIMEOUT 30000 /* us */ 192 193 /* Transmitter timeout */ 194 #define TX_TIMEOUT (2 * HZ) 195 196 #define FEC_PAUSE_FLAG_AUTONEG 0x1 197 #define FEC_PAUSE_FLAG_ENABLE 0x2 198 199 #define COPYBREAK_DEFAULT 256 200 201 #define TSO_HEADER_SIZE 128 202 /* Max number of allowed TCP segments for software TSO */ 203 #define FEC_MAX_TSO_SEGS 100 204 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 205 206 #define IS_TSO_HEADER(txq, addr) \ 207 ((addr >= txq->tso_hdrs_dma) && \ 208 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE)) 209 210 static int mii_cnt; 211 212 static inline 213 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 214 struct fec_enet_private *fep, 215 int queue_id) 216 { 217 struct bufdesc *new_bd = bdp + 1; 218 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1; 219 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id]; 220 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id]; 221 struct bufdesc_ex *ex_base; 222 struct bufdesc *base; 223 int ring_size; 224 225 if (bdp >= txq->tx_bd_base) { 226 base = txq->tx_bd_base; 227 ring_size = txq->tx_ring_size; 228 ex_base = (struct bufdesc_ex *)txq->tx_bd_base; 229 } else { 230 base = rxq->rx_bd_base; 231 ring_size = rxq->rx_ring_size; 232 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base; 233 } 234 235 if (fep->bufdesc_ex) 236 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ? 237 ex_base : ex_new_bd); 238 else 239 return (new_bd >= (base + ring_size)) ? 240 base : new_bd; 241 } 242 243 static inline 244 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 245 struct fec_enet_private *fep, 246 int queue_id) 247 { 248 struct bufdesc *new_bd = bdp - 1; 249 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1; 250 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id]; 251 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id]; 252 struct bufdesc_ex *ex_base; 253 struct bufdesc *base; 254 int ring_size; 255 256 if (bdp >= txq->tx_bd_base) { 257 base = txq->tx_bd_base; 258 ring_size = txq->tx_ring_size; 259 ex_base = (struct bufdesc_ex *)txq->tx_bd_base; 260 } else { 261 base = rxq->rx_bd_base; 262 ring_size = rxq->rx_ring_size; 263 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base; 264 } 265 266 if (fep->bufdesc_ex) 267 return (struct bufdesc *)((ex_new_bd < ex_base) ? 268 (ex_new_bd + ring_size) : ex_new_bd); 269 else 270 return (new_bd < base) ? (new_bd + ring_size) : new_bd; 271 } 272 273 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp, 274 struct fec_enet_private *fep) 275 { 276 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size; 277 } 278 279 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep, 280 struct fec_enet_priv_tx_q *txq) 281 { 282 int entries; 283 284 entries = ((const char *)txq->dirty_tx - 285 (const char *)txq->cur_tx) / fep->bufdesc_size - 1; 286 287 return entries > 0 ? entries : entries + txq->tx_ring_size; 288 } 289 290 static void *swap_buffer(void *bufaddr, int len) 291 { 292 int i; 293 unsigned int *buf = bufaddr; 294 295 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++) 296 *buf = cpu_to_be32(*buf); 297 298 return bufaddr; 299 } 300 301 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 302 { 303 int i; 304 unsigned int *src = src_buf; 305 unsigned int *dst = dst_buf; 306 307 for (i = 0; i < len; i += 4, src++, dst++) 308 *dst = swab32p(src); 309 } 310 311 static void fec_dump(struct net_device *ndev) 312 { 313 struct fec_enet_private *fep = netdev_priv(ndev); 314 struct bufdesc *bdp; 315 struct fec_enet_priv_tx_q *txq; 316 int index = 0; 317 318 netdev_info(ndev, "TX ring dump\n"); 319 pr_info("Nr SC addr len SKB\n"); 320 321 txq = fep->tx_queue[0]; 322 bdp = txq->tx_bd_base; 323 324 do { 325 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n", 326 index, 327 bdp == txq->cur_tx ? 'S' : ' ', 328 bdp == txq->dirty_tx ? 'H' : ' ', 329 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen, 330 txq->tx_skbuff[index]); 331 bdp = fec_enet_get_nextdesc(bdp, fep, 0); 332 index++; 333 } while (bdp != txq->tx_bd_base); 334 } 335 336 static inline bool is_ipv4_pkt(struct sk_buff *skb) 337 { 338 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 339 } 340 341 static int 342 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 343 { 344 /* Only run for packets requiring a checksum. */ 345 if (skb->ip_summed != CHECKSUM_PARTIAL) 346 return 0; 347 348 if (unlikely(skb_cow_head(skb, 0))) 349 return -1; 350 351 if (is_ipv4_pkt(skb)) 352 ip_hdr(skb)->check = 0; 353 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 354 355 return 0; 356 } 357 358 static int 359 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 360 struct sk_buff *skb, 361 struct net_device *ndev) 362 { 363 struct fec_enet_private *fep = netdev_priv(ndev); 364 const struct platform_device_id *id_entry = 365 platform_get_device_id(fep->pdev); 366 struct bufdesc *bdp = txq->cur_tx; 367 struct bufdesc_ex *ebdp; 368 int nr_frags = skb_shinfo(skb)->nr_frags; 369 unsigned short queue = skb_get_queue_mapping(skb); 370 int frag, frag_len; 371 unsigned short status; 372 unsigned int estatus = 0; 373 skb_frag_t *this_frag; 374 unsigned int index; 375 void *bufaddr; 376 dma_addr_t addr; 377 int i; 378 379 for (frag = 0; frag < nr_frags; frag++) { 380 this_frag = &skb_shinfo(skb)->frags[frag]; 381 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 382 ebdp = (struct bufdesc_ex *)bdp; 383 384 status = bdp->cbd_sc; 385 status &= ~BD_ENET_TX_STATS; 386 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 387 frag_len = skb_shinfo(skb)->frags[frag].size; 388 389 /* Handle the last BD specially */ 390 if (frag == nr_frags - 1) { 391 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 392 if (fep->bufdesc_ex) { 393 estatus |= BD_ENET_TX_INT; 394 if (unlikely(skb_shinfo(skb)->tx_flags & 395 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 396 estatus |= BD_ENET_TX_TS; 397 } 398 } 399 400 if (fep->bufdesc_ex) { 401 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB) 402 estatus |= FEC_TX_BD_FTYPE(queue); 403 if (skb->ip_summed == CHECKSUM_PARTIAL) 404 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 405 ebdp->cbd_bdu = 0; 406 ebdp->cbd_esc = estatus; 407 } 408 409 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset; 410 411 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep); 412 if (((unsigned long) bufaddr) & fep->tx_align || 413 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) { 414 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 415 bufaddr = txq->tx_bounce[index]; 416 417 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 418 swap_buffer(bufaddr, frag_len); 419 } 420 421 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 422 DMA_TO_DEVICE); 423 if (dma_mapping_error(&fep->pdev->dev, addr)) { 424 dev_kfree_skb_any(skb); 425 if (net_ratelimit()) 426 netdev_err(ndev, "Tx DMA memory map failed\n"); 427 goto dma_mapping_error; 428 } 429 430 bdp->cbd_bufaddr = addr; 431 bdp->cbd_datlen = frag_len; 432 bdp->cbd_sc = status; 433 } 434 435 txq->cur_tx = bdp; 436 437 return 0; 438 439 dma_mapping_error: 440 bdp = txq->cur_tx; 441 for (i = 0; i < frag; i++) { 442 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 443 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 444 bdp->cbd_datlen, DMA_TO_DEVICE); 445 } 446 return NETDEV_TX_OK; 447 } 448 449 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 450 struct sk_buff *skb, struct net_device *ndev) 451 { 452 struct fec_enet_private *fep = netdev_priv(ndev); 453 const struct platform_device_id *id_entry = 454 platform_get_device_id(fep->pdev); 455 int nr_frags = skb_shinfo(skb)->nr_frags; 456 struct bufdesc *bdp, *last_bdp; 457 void *bufaddr; 458 dma_addr_t addr; 459 unsigned short status; 460 unsigned short buflen; 461 unsigned short queue; 462 unsigned int estatus = 0; 463 unsigned int index; 464 int entries_free; 465 int ret; 466 467 entries_free = fec_enet_get_free_txdesc_num(fep, txq); 468 if (entries_free < MAX_SKB_FRAGS + 1) { 469 dev_kfree_skb_any(skb); 470 if (net_ratelimit()) 471 netdev_err(ndev, "NOT enough BD for SG!\n"); 472 return NETDEV_TX_OK; 473 } 474 475 /* Protocol checksum off-load for TCP and UDP. */ 476 if (fec_enet_clear_csum(skb, ndev)) { 477 dev_kfree_skb_any(skb); 478 return NETDEV_TX_OK; 479 } 480 481 /* Fill in a Tx ring entry */ 482 bdp = txq->cur_tx; 483 status = bdp->cbd_sc; 484 status &= ~BD_ENET_TX_STATS; 485 486 /* Set buffer length and buffer pointer */ 487 bufaddr = skb->data; 488 buflen = skb_headlen(skb); 489 490 queue = skb_get_queue_mapping(skb); 491 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep); 492 if (((unsigned long) bufaddr) & fep->tx_align || 493 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) { 494 memcpy(txq->tx_bounce[index], skb->data, buflen); 495 bufaddr = txq->tx_bounce[index]; 496 497 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 498 swap_buffer(bufaddr, buflen); 499 } 500 501 /* Push the data cache so the CPM does not get stale memory data. */ 502 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 503 if (dma_mapping_error(&fep->pdev->dev, addr)) { 504 dev_kfree_skb_any(skb); 505 if (net_ratelimit()) 506 netdev_err(ndev, "Tx DMA memory map failed\n"); 507 return NETDEV_TX_OK; 508 } 509 510 if (nr_frags) { 511 ret = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 512 if (ret) 513 return ret; 514 } else { 515 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 516 if (fep->bufdesc_ex) { 517 estatus = BD_ENET_TX_INT; 518 if (unlikely(skb_shinfo(skb)->tx_flags & 519 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 520 estatus |= BD_ENET_TX_TS; 521 } 522 } 523 524 if (fep->bufdesc_ex) { 525 526 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 527 528 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 529 fep->hwts_tx_en)) 530 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 531 532 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB) 533 estatus |= FEC_TX_BD_FTYPE(queue); 534 535 if (skb->ip_summed == CHECKSUM_PARTIAL) 536 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 537 538 ebdp->cbd_bdu = 0; 539 ebdp->cbd_esc = estatus; 540 } 541 542 last_bdp = txq->cur_tx; 543 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep); 544 /* Save skb pointer */ 545 txq->tx_skbuff[index] = skb; 546 547 bdp->cbd_datlen = buflen; 548 bdp->cbd_bufaddr = addr; 549 550 /* Send it on its way. Tell FEC it's ready, interrupt when done, 551 * it's the last BD of the frame, and to put the CRC on the end. 552 */ 553 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 554 bdp->cbd_sc = status; 555 556 /* If this was the last BD in the ring, start at the beginning again. */ 557 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue); 558 559 skb_tx_timestamp(skb); 560 561 txq->cur_tx = bdp; 562 563 /* Trigger transmission start */ 564 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue)); 565 566 return 0; 567 } 568 569 static int 570 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 571 struct net_device *ndev, 572 struct bufdesc *bdp, int index, char *data, 573 int size, bool last_tcp, bool is_last) 574 { 575 struct fec_enet_private *fep = netdev_priv(ndev); 576 const struct platform_device_id *id_entry = 577 platform_get_device_id(fep->pdev); 578 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 579 unsigned short queue = skb_get_queue_mapping(skb); 580 unsigned short status; 581 unsigned int estatus = 0; 582 dma_addr_t addr; 583 584 status = bdp->cbd_sc; 585 status &= ~BD_ENET_TX_STATS; 586 587 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 588 589 if (((unsigned long) data) & fep->tx_align || 590 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) { 591 memcpy(txq->tx_bounce[index], data, size); 592 data = txq->tx_bounce[index]; 593 594 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 595 swap_buffer(data, size); 596 } 597 598 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 599 if (dma_mapping_error(&fep->pdev->dev, addr)) { 600 dev_kfree_skb_any(skb); 601 if (net_ratelimit()) 602 netdev_err(ndev, "Tx DMA memory map failed\n"); 603 return NETDEV_TX_BUSY; 604 } 605 606 bdp->cbd_datlen = size; 607 bdp->cbd_bufaddr = addr; 608 609 if (fep->bufdesc_ex) { 610 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB) 611 estatus |= FEC_TX_BD_FTYPE(queue); 612 if (skb->ip_summed == CHECKSUM_PARTIAL) 613 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 614 ebdp->cbd_bdu = 0; 615 ebdp->cbd_esc = estatus; 616 } 617 618 /* Handle the last BD specially */ 619 if (last_tcp) 620 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 621 if (is_last) { 622 status |= BD_ENET_TX_INTR; 623 if (fep->bufdesc_ex) 624 ebdp->cbd_esc |= BD_ENET_TX_INT; 625 } 626 627 bdp->cbd_sc = status; 628 629 return 0; 630 } 631 632 static int 633 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 634 struct sk_buff *skb, struct net_device *ndev, 635 struct bufdesc *bdp, int index) 636 { 637 struct fec_enet_private *fep = netdev_priv(ndev); 638 const struct platform_device_id *id_entry = 639 platform_get_device_id(fep->pdev); 640 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 641 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 642 unsigned short queue = skb_get_queue_mapping(skb); 643 void *bufaddr; 644 unsigned long dmabuf; 645 unsigned short status; 646 unsigned int estatus = 0; 647 648 status = bdp->cbd_sc; 649 status &= ~BD_ENET_TX_STATS; 650 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 651 652 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 653 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 654 if (((unsigned long)bufaddr) & fep->tx_align || 655 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) { 656 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 657 bufaddr = txq->tx_bounce[index]; 658 659 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 660 swap_buffer(bufaddr, hdr_len); 661 662 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 663 hdr_len, DMA_TO_DEVICE); 664 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 665 dev_kfree_skb_any(skb); 666 if (net_ratelimit()) 667 netdev_err(ndev, "Tx DMA memory map failed\n"); 668 return NETDEV_TX_BUSY; 669 } 670 } 671 672 bdp->cbd_bufaddr = dmabuf; 673 bdp->cbd_datlen = hdr_len; 674 675 if (fep->bufdesc_ex) { 676 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB) 677 estatus |= FEC_TX_BD_FTYPE(queue); 678 if (skb->ip_summed == CHECKSUM_PARTIAL) 679 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 680 ebdp->cbd_bdu = 0; 681 ebdp->cbd_esc = estatus; 682 } 683 684 bdp->cbd_sc = status; 685 686 return 0; 687 } 688 689 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 690 struct sk_buff *skb, 691 struct net_device *ndev) 692 { 693 struct fec_enet_private *fep = netdev_priv(ndev); 694 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 695 int total_len, data_left; 696 struct bufdesc *bdp = txq->cur_tx; 697 unsigned short queue = skb_get_queue_mapping(skb); 698 struct tso_t tso; 699 unsigned int index = 0; 700 int ret; 701 const struct platform_device_id *id_entry = 702 platform_get_device_id(fep->pdev); 703 704 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) { 705 dev_kfree_skb_any(skb); 706 if (net_ratelimit()) 707 netdev_err(ndev, "NOT enough BD for TSO!\n"); 708 return NETDEV_TX_OK; 709 } 710 711 /* Protocol checksum off-load for TCP and UDP. */ 712 if (fec_enet_clear_csum(skb, ndev)) { 713 dev_kfree_skb_any(skb); 714 return NETDEV_TX_OK; 715 } 716 717 /* Initialize the TSO handler, and prepare the first payload */ 718 tso_start(skb, &tso); 719 720 total_len = skb->len - hdr_len; 721 while (total_len > 0) { 722 char *hdr; 723 724 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep); 725 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 726 total_len -= data_left; 727 728 /* prepare packet headers: MAC + IP + TCP */ 729 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 730 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 731 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 732 if (ret) 733 goto err_release; 734 735 while (data_left > 0) { 736 int size; 737 738 size = min_t(int, tso.size, data_left); 739 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 740 index = fec_enet_get_bd_index(txq->tx_bd_base, 741 bdp, fep); 742 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 743 bdp, index, 744 tso.data, size, 745 size == data_left, 746 total_len == 0); 747 if (ret) 748 goto err_release; 749 750 data_left -= size; 751 tso_build_data(skb, &tso, size); 752 } 753 754 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 755 } 756 757 /* Save skb pointer */ 758 txq->tx_skbuff[index] = skb; 759 760 skb_tx_timestamp(skb); 761 txq->cur_tx = bdp; 762 763 /* Trigger transmission start */ 764 if (!(id_entry->driver_data & FEC_QUIRK_ERR007885) || 765 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) || 766 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) || 767 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) || 768 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue))) 769 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue)); 770 771 return 0; 772 773 err_release: 774 /* TODO: Release all used data descriptors for TSO */ 775 return ret; 776 } 777 778 static netdev_tx_t 779 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 780 { 781 struct fec_enet_private *fep = netdev_priv(ndev); 782 int entries_free; 783 unsigned short queue; 784 struct fec_enet_priv_tx_q *txq; 785 struct netdev_queue *nq; 786 int ret; 787 788 queue = skb_get_queue_mapping(skb); 789 txq = fep->tx_queue[queue]; 790 nq = netdev_get_tx_queue(ndev, queue); 791 792 if (skb_is_gso(skb)) 793 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 794 else 795 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 796 if (ret) 797 return ret; 798 799 entries_free = fec_enet_get_free_txdesc_num(fep, txq); 800 if (entries_free <= txq->tx_stop_threshold) 801 netif_tx_stop_queue(nq); 802 803 return NETDEV_TX_OK; 804 } 805 806 /* Init RX & TX buffer descriptors 807 */ 808 static void fec_enet_bd_init(struct net_device *dev) 809 { 810 struct fec_enet_private *fep = netdev_priv(dev); 811 struct fec_enet_priv_tx_q *txq; 812 struct fec_enet_priv_rx_q *rxq; 813 struct bufdesc *bdp; 814 unsigned int i; 815 unsigned int q; 816 817 for (q = 0; q < fep->num_rx_queues; q++) { 818 /* Initialize the receive buffer descriptors. */ 819 rxq = fep->rx_queue[q]; 820 bdp = rxq->rx_bd_base; 821 822 for (i = 0; i < rxq->rx_ring_size; i++) { 823 824 /* Initialize the BD for every fragment in the page. */ 825 if (bdp->cbd_bufaddr) 826 bdp->cbd_sc = BD_ENET_RX_EMPTY; 827 else 828 bdp->cbd_sc = 0; 829 bdp = fec_enet_get_nextdesc(bdp, fep, q); 830 } 831 832 /* Set the last buffer to wrap */ 833 bdp = fec_enet_get_prevdesc(bdp, fep, q); 834 bdp->cbd_sc |= BD_SC_WRAP; 835 836 rxq->cur_rx = rxq->rx_bd_base; 837 } 838 839 for (q = 0; q < fep->num_tx_queues; q++) { 840 /* ...and the same for transmit */ 841 txq = fep->tx_queue[q]; 842 bdp = txq->tx_bd_base; 843 txq->cur_tx = bdp; 844 845 for (i = 0; i < txq->tx_ring_size; i++) { 846 /* Initialize the BD for every fragment in the page. */ 847 bdp->cbd_sc = 0; 848 if (txq->tx_skbuff[i]) { 849 dev_kfree_skb_any(txq->tx_skbuff[i]); 850 txq->tx_skbuff[i] = NULL; 851 } 852 bdp->cbd_bufaddr = 0; 853 bdp = fec_enet_get_nextdesc(bdp, fep, q); 854 } 855 856 /* Set the last buffer to wrap */ 857 bdp = fec_enet_get_prevdesc(bdp, fep, q); 858 bdp->cbd_sc |= BD_SC_WRAP; 859 txq->dirty_tx = bdp; 860 } 861 } 862 863 static void fec_enet_active_rxring(struct net_device *ndev) 864 { 865 struct fec_enet_private *fep = netdev_priv(ndev); 866 int i; 867 868 for (i = 0; i < fep->num_rx_queues; i++) 869 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i)); 870 } 871 872 static void fec_enet_enable_ring(struct net_device *ndev) 873 { 874 struct fec_enet_private *fep = netdev_priv(ndev); 875 struct fec_enet_priv_tx_q *txq; 876 struct fec_enet_priv_rx_q *rxq; 877 int i; 878 879 for (i = 0; i < fep->num_rx_queues; i++) { 880 rxq = fep->rx_queue[i]; 881 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i)); 882 883 /* enable DMA1/2 */ 884 if (i) 885 writel(RCMR_MATCHEN | RCMR_CMP(i), 886 fep->hwp + FEC_RCMR(i)); 887 } 888 889 for (i = 0; i < fep->num_tx_queues; i++) { 890 txq = fep->tx_queue[i]; 891 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i)); 892 893 /* enable DMA1/2 */ 894 if (i) 895 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 896 fep->hwp + FEC_DMA_CFG(i)); 897 } 898 } 899 900 static void fec_enet_reset_skb(struct net_device *ndev) 901 { 902 struct fec_enet_private *fep = netdev_priv(ndev); 903 struct fec_enet_priv_tx_q *txq; 904 int i, j; 905 906 for (i = 0; i < fep->num_tx_queues; i++) { 907 txq = fep->tx_queue[i]; 908 909 for (j = 0; j < txq->tx_ring_size; j++) { 910 if (txq->tx_skbuff[j]) { 911 dev_kfree_skb_any(txq->tx_skbuff[j]); 912 txq->tx_skbuff[j] = NULL; 913 } 914 } 915 } 916 } 917 918 /* 919 * This function is called to start or restart the FEC during a link 920 * change, transmit timeout, or to reconfigure the FEC. The network 921 * packet processing for this device must be stopped before this call. 922 */ 923 static void 924 fec_restart(struct net_device *ndev) 925 { 926 struct fec_enet_private *fep = netdev_priv(ndev); 927 const struct platform_device_id *id_entry = 928 platform_get_device_id(fep->pdev); 929 u32 val; 930 u32 temp_mac[2]; 931 u32 rcntl = OPT_FRAME_SIZE | 0x04; 932 u32 ecntl = 0x2; /* ETHEREN */ 933 934 /* Whack a reset. We should wait for this. 935 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 936 * instead of reset MAC itself. 937 */ 938 if (id_entry && id_entry->driver_data & FEC_QUIRK_HAS_AVB) { 939 writel(0, fep->hwp + FEC_ECNTRL); 940 } else { 941 writel(1, fep->hwp + FEC_ECNTRL); 942 udelay(10); 943 } 944 945 /* 946 * enet-mac reset will reset mac address registers too, 947 * so need to reconfigure it. 948 */ 949 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 950 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 951 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); 952 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); 953 } 954 955 /* Clear any outstanding interrupt. */ 956 writel(0xffc00000, fep->hwp + FEC_IEVENT); 957 958 /* Set maximum receive buffer size. */ 959 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); 960 961 fec_enet_bd_init(ndev); 962 963 fec_enet_enable_ring(ndev); 964 965 /* Reset tx SKB buffers. */ 966 fec_enet_reset_skb(ndev); 967 968 /* Enable MII mode */ 969 if (fep->full_duplex == DUPLEX_FULL) { 970 /* FD enable */ 971 writel(0x04, fep->hwp + FEC_X_CNTRL); 972 } else { 973 /* No Rcv on Xmit */ 974 rcntl |= 0x02; 975 writel(0x0, fep->hwp + FEC_X_CNTRL); 976 } 977 978 /* Set MII speed */ 979 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 980 981 #if !defined(CONFIG_M5272) 982 /* set RX checksum */ 983 val = readl(fep->hwp + FEC_RACC); 984 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 985 val |= FEC_RACC_OPTIONS; 986 else 987 val &= ~FEC_RACC_OPTIONS; 988 writel(val, fep->hwp + FEC_RACC); 989 #endif 990 991 /* 992 * The phy interface and speed need to get configured 993 * differently on enet-mac. 994 */ 995 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 996 /* Enable flow control and length check */ 997 rcntl |= 0x40000000 | 0x00000020; 998 999 /* RGMII, RMII or MII */ 1000 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) 1001 rcntl |= (1 << 6); 1002 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1003 rcntl |= (1 << 8); 1004 else 1005 rcntl &= ~(1 << 8); 1006 1007 /* 1G, 100M or 10M */ 1008 if (fep->phy_dev) { 1009 if (fep->phy_dev->speed == SPEED_1000) 1010 ecntl |= (1 << 5); 1011 else if (fep->phy_dev->speed == SPEED_100) 1012 rcntl &= ~(1 << 9); 1013 else 1014 rcntl |= (1 << 9); 1015 } 1016 } else { 1017 #ifdef FEC_MIIGSK_ENR 1018 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { 1019 u32 cfgr; 1020 /* disable the gasket and wait */ 1021 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1022 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1023 udelay(1); 1024 1025 /* 1026 * configure the gasket: 1027 * RMII, 50 MHz, no loopback, no echo 1028 * MII, 25 MHz, no loopback, no echo 1029 */ 1030 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1031 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1032 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) 1033 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1034 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1035 1036 /* re-enable the gasket */ 1037 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1038 } 1039 #endif 1040 } 1041 1042 #if !defined(CONFIG_M5272) 1043 /* enable pause frame*/ 1044 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1045 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1046 fep->phy_dev && fep->phy_dev->pause)) { 1047 rcntl |= FEC_ENET_FCE; 1048 1049 /* set FIFO threshold parameter to reduce overrun */ 1050 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1051 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1052 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1053 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1054 1055 /* OPD */ 1056 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1057 } else { 1058 rcntl &= ~FEC_ENET_FCE; 1059 } 1060 #endif /* !defined(CONFIG_M5272) */ 1061 1062 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1063 1064 /* Setup multicast filter. */ 1065 set_multicast_list(ndev); 1066 #ifndef CONFIG_M5272 1067 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1068 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1069 #endif 1070 1071 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 1072 /* enable ENET endian swap */ 1073 ecntl |= (1 << 8); 1074 /* enable ENET store and forward mode */ 1075 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1076 } 1077 1078 if (fep->bufdesc_ex) 1079 ecntl |= (1 << 4); 1080 1081 #ifndef CONFIG_M5272 1082 /* Enable the MIB statistic event counters */ 1083 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1084 #endif 1085 1086 /* And last, enable the transmit and receive processing */ 1087 writel(ecntl, fep->hwp + FEC_ECNTRL); 1088 fec_enet_active_rxring(ndev); 1089 1090 if (fep->bufdesc_ex) 1091 fec_ptp_start_cyclecounter(ndev); 1092 1093 /* Enable interrupts we wish to service */ 1094 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1095 1096 /* Init the interrupt coalescing */ 1097 fec_enet_itr_coal_init(ndev); 1098 1099 } 1100 1101 static void 1102 fec_stop(struct net_device *ndev) 1103 { 1104 struct fec_enet_private *fep = netdev_priv(ndev); 1105 const struct platform_device_id *id_entry = 1106 platform_get_device_id(fep->pdev); 1107 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1108 1109 /* We cannot expect a graceful transmit stop without link !!! */ 1110 if (fep->link) { 1111 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1112 udelay(10); 1113 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1114 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1115 } 1116 1117 /* Whack a reset. We should wait for this. 1118 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1119 * instead of reset MAC itself. 1120 */ 1121 if (id_entry && id_entry->driver_data & FEC_QUIRK_HAS_AVB) { 1122 writel(0, fep->hwp + FEC_ECNTRL); 1123 } else { 1124 writel(1, fep->hwp + FEC_ECNTRL); 1125 udelay(10); 1126 } 1127 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1128 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1129 1130 /* We have to keep ENET enabled to have MII interrupt stay working */ 1131 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 1132 writel(2, fep->hwp + FEC_ECNTRL); 1133 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1134 } 1135 } 1136 1137 1138 static void 1139 fec_timeout(struct net_device *ndev) 1140 { 1141 struct fec_enet_private *fep = netdev_priv(ndev); 1142 1143 fec_dump(ndev); 1144 1145 ndev->stats.tx_errors++; 1146 1147 schedule_work(&fep->tx_timeout_work); 1148 } 1149 1150 static void fec_enet_timeout_work(struct work_struct *work) 1151 { 1152 struct fec_enet_private *fep = 1153 container_of(work, struct fec_enet_private, tx_timeout_work); 1154 struct net_device *ndev = fep->netdev; 1155 1156 rtnl_lock(); 1157 if (netif_device_present(ndev) || netif_running(ndev)) { 1158 napi_disable(&fep->napi); 1159 netif_tx_lock_bh(ndev); 1160 fec_restart(ndev); 1161 netif_wake_queue(ndev); 1162 netif_tx_unlock_bh(ndev); 1163 napi_enable(&fep->napi); 1164 } 1165 rtnl_unlock(); 1166 } 1167 1168 static void 1169 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1170 struct skb_shared_hwtstamps *hwtstamps) 1171 { 1172 unsigned long flags; 1173 u64 ns; 1174 1175 spin_lock_irqsave(&fep->tmreg_lock, flags); 1176 ns = timecounter_cyc2time(&fep->tc, ts); 1177 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1178 1179 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1180 hwtstamps->hwtstamp = ns_to_ktime(ns); 1181 } 1182 1183 static void 1184 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1185 { 1186 struct fec_enet_private *fep; 1187 struct bufdesc *bdp; 1188 unsigned short status; 1189 struct sk_buff *skb; 1190 struct fec_enet_priv_tx_q *txq; 1191 struct netdev_queue *nq; 1192 int index = 0; 1193 int entries_free; 1194 1195 fep = netdev_priv(ndev); 1196 1197 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1198 1199 txq = fep->tx_queue[queue_id]; 1200 /* get next bdp of dirty_tx */ 1201 nq = netdev_get_tx_queue(ndev, queue_id); 1202 bdp = txq->dirty_tx; 1203 1204 /* get next bdp of dirty_tx */ 1205 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id); 1206 1207 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { 1208 1209 /* current queue is empty */ 1210 if (bdp == txq->cur_tx) 1211 break; 1212 1213 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep); 1214 1215 skb = txq->tx_skbuff[index]; 1216 txq->tx_skbuff[index] = NULL; 1217 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr)) 1218 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 1219 bdp->cbd_datlen, DMA_TO_DEVICE); 1220 bdp->cbd_bufaddr = 0; 1221 if (!skb) { 1222 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id); 1223 continue; 1224 } 1225 1226 /* Check for errors. */ 1227 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1228 BD_ENET_TX_RL | BD_ENET_TX_UN | 1229 BD_ENET_TX_CSL)) { 1230 ndev->stats.tx_errors++; 1231 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1232 ndev->stats.tx_heartbeat_errors++; 1233 if (status & BD_ENET_TX_LC) /* Late collision */ 1234 ndev->stats.tx_window_errors++; 1235 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1236 ndev->stats.tx_aborted_errors++; 1237 if (status & BD_ENET_TX_UN) /* Underrun */ 1238 ndev->stats.tx_fifo_errors++; 1239 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1240 ndev->stats.tx_carrier_errors++; 1241 } else { 1242 ndev->stats.tx_packets++; 1243 ndev->stats.tx_bytes += skb->len; 1244 } 1245 1246 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 1247 fep->bufdesc_ex) { 1248 struct skb_shared_hwtstamps shhwtstamps; 1249 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1250 1251 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps); 1252 skb_tstamp_tx(skb, &shhwtstamps); 1253 } 1254 1255 /* Deferred means some collisions occurred during transmit, 1256 * but we eventually sent the packet OK. 1257 */ 1258 if (status & BD_ENET_TX_DEF) 1259 ndev->stats.collisions++; 1260 1261 /* Free the sk buffer associated with this last transmit */ 1262 dev_kfree_skb_any(skb); 1263 1264 txq->dirty_tx = bdp; 1265 1266 /* Update pointer to next buffer descriptor to be transmitted */ 1267 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id); 1268 1269 /* Since we have freed up a buffer, the ring is no longer full 1270 */ 1271 if (netif_queue_stopped(ndev)) { 1272 entries_free = fec_enet_get_free_txdesc_num(fep, txq); 1273 if (entries_free >= txq->tx_wake_threshold) 1274 netif_tx_wake_queue(nq); 1275 } 1276 } 1277 1278 /* ERR006538: Keep the transmitter going */ 1279 if (bdp != txq->cur_tx && 1280 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0) 1281 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id)); 1282 } 1283 1284 static void 1285 fec_enet_tx(struct net_device *ndev) 1286 { 1287 struct fec_enet_private *fep = netdev_priv(ndev); 1288 u16 queue_id; 1289 /* First process class A queue, then Class B and Best Effort queue */ 1290 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) { 1291 clear_bit(queue_id, &fep->work_tx); 1292 fec_enet_tx_queue(ndev, queue_id); 1293 } 1294 return; 1295 } 1296 1297 static int 1298 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1299 { 1300 struct fec_enet_private *fep = netdev_priv(ndev); 1301 int off; 1302 1303 off = ((unsigned long)skb->data) & fep->rx_align; 1304 if (off) 1305 skb_reserve(skb, fep->rx_align + 1 - off); 1306 1307 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, 1308 FEC_ENET_RX_FRSIZE - fep->rx_align, 1309 DMA_FROM_DEVICE); 1310 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) { 1311 if (net_ratelimit()) 1312 netdev_err(ndev, "Rx DMA memory map failed\n"); 1313 return -ENOMEM; 1314 } 1315 1316 return 0; 1317 } 1318 1319 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1320 struct bufdesc *bdp, u32 length, bool swap) 1321 { 1322 struct fec_enet_private *fep = netdev_priv(ndev); 1323 struct sk_buff *new_skb; 1324 1325 if (length > fep->rx_copybreak) 1326 return false; 1327 1328 new_skb = netdev_alloc_skb(ndev, length); 1329 if (!new_skb) 1330 return false; 1331 1332 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr, 1333 FEC_ENET_RX_FRSIZE - fep->rx_align, 1334 DMA_FROM_DEVICE); 1335 if (!swap) 1336 memcpy(new_skb->data, (*skb)->data, length); 1337 else 1338 swap_buffer2(new_skb->data, (*skb)->data, length); 1339 *skb = new_skb; 1340 1341 return true; 1342 } 1343 1344 /* During a receive, the cur_rx points to the current incoming buffer. 1345 * When we update through the ring, if the next incoming buffer has 1346 * not been given to the system, we just set the empty indicator, 1347 * effectively tossing the packet. 1348 */ 1349 static int 1350 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1351 { 1352 struct fec_enet_private *fep = netdev_priv(ndev); 1353 const struct platform_device_id *id_entry = 1354 platform_get_device_id(fep->pdev); 1355 struct fec_enet_priv_rx_q *rxq; 1356 struct bufdesc *bdp; 1357 unsigned short status; 1358 struct sk_buff *skb_new = NULL; 1359 struct sk_buff *skb; 1360 ushort pkt_len; 1361 __u8 *data; 1362 int pkt_received = 0; 1363 struct bufdesc_ex *ebdp = NULL; 1364 bool vlan_packet_rcvd = false; 1365 u16 vlan_tag; 1366 int index = 0; 1367 bool is_copybreak; 1368 bool need_swap = id_entry->driver_data & FEC_QUIRK_SWAP_FRAME; 1369 1370 #ifdef CONFIG_M532x 1371 flush_cache_all(); 1372 #endif 1373 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1374 rxq = fep->rx_queue[queue_id]; 1375 1376 /* First, grab all of the stats for the incoming packet. 1377 * These get messed up if we get called due to a busy condition. 1378 */ 1379 bdp = rxq->cur_rx; 1380 1381 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { 1382 1383 if (pkt_received >= budget) 1384 break; 1385 pkt_received++; 1386 1387 /* Since we have allocated space to hold a complete frame, 1388 * the last indicator should be set. 1389 */ 1390 if ((status & BD_ENET_RX_LAST) == 0) 1391 netdev_err(ndev, "rcv is not +last\n"); 1392 1393 1394 /* Check for errors. */ 1395 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1396 BD_ENET_RX_CR | BD_ENET_RX_OV)) { 1397 ndev->stats.rx_errors++; 1398 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { 1399 /* Frame too long or too short. */ 1400 ndev->stats.rx_length_errors++; 1401 } 1402 if (status & BD_ENET_RX_NO) /* Frame alignment */ 1403 ndev->stats.rx_frame_errors++; 1404 if (status & BD_ENET_RX_CR) /* CRC Error */ 1405 ndev->stats.rx_crc_errors++; 1406 if (status & BD_ENET_RX_OV) /* FIFO overrun */ 1407 ndev->stats.rx_fifo_errors++; 1408 } 1409 1410 /* Report late collisions as a frame error. 1411 * On this error, the BD is closed, but we don't know what we 1412 * have in the buffer. So, just drop this frame on the floor. 1413 */ 1414 if (status & BD_ENET_RX_CL) { 1415 ndev->stats.rx_errors++; 1416 ndev->stats.rx_frame_errors++; 1417 goto rx_processing_done; 1418 } 1419 1420 /* Process the incoming frame. */ 1421 ndev->stats.rx_packets++; 1422 pkt_len = bdp->cbd_datlen; 1423 ndev->stats.rx_bytes += pkt_len; 1424 1425 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep); 1426 skb = rxq->rx_skbuff[index]; 1427 1428 /* The packet length includes FCS, but we don't want to 1429 * include that when passing upstream as it messes up 1430 * bridging applications. 1431 */ 1432 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1433 need_swap); 1434 if (!is_copybreak) { 1435 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1436 if (unlikely(!skb_new)) { 1437 ndev->stats.rx_dropped++; 1438 goto rx_processing_done; 1439 } 1440 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 1441 FEC_ENET_RX_FRSIZE - fep->rx_align, 1442 DMA_FROM_DEVICE); 1443 } 1444 1445 prefetch(skb->data - NET_IP_ALIGN); 1446 skb_put(skb, pkt_len - 4); 1447 data = skb->data; 1448 if (!is_copybreak && need_swap) 1449 swap_buffer(data, pkt_len); 1450 1451 /* Extract the enhanced buffer descriptor */ 1452 ebdp = NULL; 1453 if (fep->bufdesc_ex) 1454 ebdp = (struct bufdesc_ex *)bdp; 1455 1456 /* If this is a VLAN packet remove the VLAN Tag */ 1457 vlan_packet_rcvd = false; 1458 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1459 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) { 1460 /* Push and remove the vlan tag */ 1461 struct vlan_hdr *vlan_header = 1462 (struct vlan_hdr *) (data + ETH_HLEN); 1463 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1464 1465 vlan_packet_rcvd = true; 1466 1467 skb_copy_to_linear_data_offset(skb, VLAN_HLEN, 1468 data, (2 * ETH_ALEN)); 1469 skb_pull(skb, VLAN_HLEN); 1470 } 1471 1472 skb->protocol = eth_type_trans(skb, ndev); 1473 1474 /* Get receive timestamp from the skb */ 1475 if (fep->hwts_rx_en && fep->bufdesc_ex) 1476 fec_enet_hwtstamp(fep, ebdp->ts, 1477 skb_hwtstamps(skb)); 1478 1479 if (fep->bufdesc_ex && 1480 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1481 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) { 1482 /* don't check it */ 1483 skb->ip_summed = CHECKSUM_UNNECESSARY; 1484 } else { 1485 skb_checksum_none_assert(skb); 1486 } 1487 } 1488 1489 /* Handle received VLAN packets */ 1490 if (vlan_packet_rcvd) 1491 __vlan_hwaccel_put_tag(skb, 1492 htons(ETH_P_8021Q), 1493 vlan_tag); 1494 1495 napi_gro_receive(&fep->napi, skb); 1496 1497 if (is_copybreak) { 1498 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr, 1499 FEC_ENET_RX_FRSIZE - fep->rx_align, 1500 DMA_FROM_DEVICE); 1501 } else { 1502 rxq->rx_skbuff[index] = skb_new; 1503 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1504 } 1505 1506 rx_processing_done: 1507 /* Clear the status flags for this buffer */ 1508 status &= ~BD_ENET_RX_STATS; 1509 1510 /* Mark the buffer empty */ 1511 status |= BD_ENET_RX_EMPTY; 1512 bdp->cbd_sc = status; 1513 1514 if (fep->bufdesc_ex) { 1515 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1516 1517 ebdp->cbd_esc = BD_ENET_RX_INT; 1518 ebdp->cbd_prot = 0; 1519 ebdp->cbd_bdu = 0; 1520 } 1521 1522 /* Update BD pointer to next entry */ 1523 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id); 1524 1525 /* Doing this here will keep the FEC running while we process 1526 * incoming frames. On a heavily loaded network, we should be 1527 * able to keep up at the expense of system resources. 1528 */ 1529 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id)); 1530 } 1531 rxq->cur_rx = bdp; 1532 return pkt_received; 1533 } 1534 1535 static int 1536 fec_enet_rx(struct net_device *ndev, int budget) 1537 { 1538 int pkt_received = 0; 1539 u16 queue_id; 1540 struct fec_enet_private *fep = netdev_priv(ndev); 1541 1542 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) { 1543 clear_bit(queue_id, &fep->work_rx); 1544 pkt_received += fec_enet_rx_queue(ndev, 1545 budget - pkt_received, queue_id); 1546 } 1547 return pkt_received; 1548 } 1549 1550 static bool 1551 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events) 1552 { 1553 if (int_events == 0) 1554 return false; 1555 1556 if (int_events & FEC_ENET_RXF) 1557 fep->work_rx |= (1 << 2); 1558 if (int_events & FEC_ENET_RXF_1) 1559 fep->work_rx |= (1 << 0); 1560 if (int_events & FEC_ENET_RXF_2) 1561 fep->work_rx |= (1 << 1); 1562 1563 if (int_events & FEC_ENET_TXF) 1564 fep->work_tx |= (1 << 2); 1565 if (int_events & FEC_ENET_TXF_1) 1566 fep->work_tx |= (1 << 0); 1567 if (int_events & FEC_ENET_TXF_2) 1568 fep->work_tx |= (1 << 1); 1569 1570 return true; 1571 } 1572 1573 static irqreturn_t 1574 fec_enet_interrupt(int irq, void *dev_id) 1575 { 1576 struct net_device *ndev = dev_id; 1577 struct fec_enet_private *fep = netdev_priv(ndev); 1578 const unsigned napi_mask = FEC_ENET_RXF | FEC_ENET_TXF; 1579 uint int_events; 1580 irqreturn_t ret = IRQ_NONE; 1581 1582 int_events = readl(fep->hwp + FEC_IEVENT); 1583 writel(int_events & ~napi_mask, fep->hwp + FEC_IEVENT); 1584 fec_enet_collect_events(fep, int_events); 1585 1586 if (int_events & napi_mask) { 1587 ret = IRQ_HANDLED; 1588 1589 /* Disable the NAPI interrupts */ 1590 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); 1591 napi_schedule(&fep->napi); 1592 } 1593 1594 if (int_events & FEC_ENET_MII) { 1595 ret = IRQ_HANDLED; 1596 complete(&fep->mdio_done); 1597 } 1598 1599 if (fep->ptp_clock) 1600 fec_ptp_check_pps_event(fep); 1601 1602 return ret; 1603 } 1604 1605 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1606 { 1607 struct net_device *ndev = napi->dev; 1608 struct fec_enet_private *fep = netdev_priv(ndev); 1609 int pkts; 1610 1611 /* 1612 * Clear any pending transmit or receive interrupts before 1613 * processing the rings to avoid racing with the hardware. 1614 */ 1615 writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT); 1616 1617 pkts = fec_enet_rx(ndev, budget); 1618 1619 fec_enet_tx(ndev); 1620 1621 if (pkts < budget) { 1622 napi_complete(napi); 1623 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1624 } 1625 return pkts; 1626 } 1627 1628 /* ------------------------------------------------------------------------- */ 1629 static void fec_get_mac(struct net_device *ndev) 1630 { 1631 struct fec_enet_private *fep = netdev_priv(ndev); 1632 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1633 unsigned char *iap, tmpaddr[ETH_ALEN]; 1634 1635 /* 1636 * try to get mac address in following order: 1637 * 1638 * 1) module parameter via kernel command line in form 1639 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1640 */ 1641 iap = macaddr; 1642 1643 /* 1644 * 2) from device tree data 1645 */ 1646 if (!is_valid_ether_addr(iap)) { 1647 struct device_node *np = fep->pdev->dev.of_node; 1648 if (np) { 1649 const char *mac = of_get_mac_address(np); 1650 if (mac) 1651 iap = (unsigned char *) mac; 1652 } 1653 } 1654 1655 /* 1656 * 3) from flash or fuse (via platform data) 1657 */ 1658 if (!is_valid_ether_addr(iap)) { 1659 #ifdef CONFIG_M5272 1660 if (FEC_FLASHMAC) 1661 iap = (unsigned char *)FEC_FLASHMAC; 1662 #else 1663 if (pdata) 1664 iap = (unsigned char *)&pdata->mac; 1665 #endif 1666 } 1667 1668 /* 1669 * 4) FEC mac registers set by bootloader 1670 */ 1671 if (!is_valid_ether_addr(iap)) { 1672 *((__be32 *) &tmpaddr[0]) = 1673 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1674 *((__be16 *) &tmpaddr[4]) = 1675 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1676 iap = &tmpaddr[0]; 1677 } 1678 1679 /* 1680 * 5) random mac address 1681 */ 1682 if (!is_valid_ether_addr(iap)) { 1683 /* Report it and use a random ethernet address instead */ 1684 netdev_err(ndev, "Invalid MAC address: %pM\n", iap); 1685 eth_hw_addr_random(ndev); 1686 netdev_info(ndev, "Using random MAC address: %pM\n", 1687 ndev->dev_addr); 1688 return; 1689 } 1690 1691 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1692 1693 /* Adjust MAC if using macaddr */ 1694 if (iap == macaddr) 1695 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1696 } 1697 1698 /* ------------------------------------------------------------------------- */ 1699 1700 /* 1701 * Phy section 1702 */ 1703 static void fec_enet_adjust_link(struct net_device *ndev) 1704 { 1705 struct fec_enet_private *fep = netdev_priv(ndev); 1706 struct phy_device *phy_dev = fep->phy_dev; 1707 int status_change = 0; 1708 1709 /* Prevent a state halted on mii error */ 1710 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 1711 phy_dev->state = PHY_RESUMING; 1712 return; 1713 } 1714 1715 /* 1716 * If the netdev is down, or is going down, we're not interested 1717 * in link state events, so just mark our idea of the link as down 1718 * and ignore the event. 1719 */ 1720 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1721 fep->link = 0; 1722 } else if (phy_dev->link) { 1723 if (!fep->link) { 1724 fep->link = phy_dev->link; 1725 status_change = 1; 1726 } 1727 1728 if (fep->full_duplex != phy_dev->duplex) { 1729 fep->full_duplex = phy_dev->duplex; 1730 status_change = 1; 1731 } 1732 1733 if (phy_dev->speed != fep->speed) { 1734 fep->speed = phy_dev->speed; 1735 status_change = 1; 1736 } 1737 1738 /* if any of the above changed restart the FEC */ 1739 if (status_change) { 1740 napi_disable(&fep->napi); 1741 netif_tx_lock_bh(ndev); 1742 fec_restart(ndev); 1743 netif_wake_queue(ndev); 1744 netif_tx_unlock_bh(ndev); 1745 napi_enable(&fep->napi); 1746 } 1747 } else { 1748 if (fep->link) { 1749 napi_disable(&fep->napi); 1750 netif_tx_lock_bh(ndev); 1751 fec_stop(ndev); 1752 netif_tx_unlock_bh(ndev); 1753 napi_enable(&fep->napi); 1754 fep->link = phy_dev->link; 1755 status_change = 1; 1756 } 1757 } 1758 1759 if (status_change) 1760 phy_print_status(phy_dev); 1761 } 1762 1763 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1764 { 1765 struct fec_enet_private *fep = bus->priv; 1766 unsigned long time_left; 1767 1768 fep->mii_timeout = 0; 1769 init_completion(&fep->mdio_done); 1770 1771 /* start a read op */ 1772 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 1773 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1774 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1775 1776 /* wait for end of transfer */ 1777 time_left = wait_for_completion_timeout(&fep->mdio_done, 1778 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1779 if (time_left == 0) { 1780 fep->mii_timeout = 1; 1781 netdev_err(fep->netdev, "MDIO read timeout\n"); 1782 return -ETIMEDOUT; 1783 } 1784 1785 /* return value */ 1786 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1787 } 1788 1789 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1790 u16 value) 1791 { 1792 struct fec_enet_private *fep = bus->priv; 1793 unsigned long time_left; 1794 1795 fep->mii_timeout = 0; 1796 init_completion(&fep->mdio_done); 1797 1798 /* start a write op */ 1799 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 1800 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1801 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1802 fep->hwp + FEC_MII_DATA); 1803 1804 /* wait for end of transfer */ 1805 time_left = wait_for_completion_timeout(&fep->mdio_done, 1806 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1807 if (time_left == 0) { 1808 fep->mii_timeout = 1; 1809 netdev_err(fep->netdev, "MDIO write timeout\n"); 1810 return -ETIMEDOUT; 1811 } 1812 1813 return 0; 1814 } 1815 1816 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1817 { 1818 struct fec_enet_private *fep = netdev_priv(ndev); 1819 int ret; 1820 1821 if (enable) { 1822 ret = clk_prepare_enable(fep->clk_ahb); 1823 if (ret) 1824 return ret; 1825 ret = clk_prepare_enable(fep->clk_ipg); 1826 if (ret) 1827 goto failed_clk_ipg; 1828 if (fep->clk_enet_out) { 1829 ret = clk_prepare_enable(fep->clk_enet_out); 1830 if (ret) 1831 goto failed_clk_enet_out; 1832 } 1833 if (fep->clk_ptp) { 1834 mutex_lock(&fep->ptp_clk_mutex); 1835 ret = clk_prepare_enable(fep->clk_ptp); 1836 if (ret) { 1837 mutex_unlock(&fep->ptp_clk_mutex); 1838 goto failed_clk_ptp; 1839 } else { 1840 fep->ptp_clk_on = true; 1841 } 1842 mutex_unlock(&fep->ptp_clk_mutex); 1843 } 1844 if (fep->clk_ref) { 1845 ret = clk_prepare_enable(fep->clk_ref); 1846 if (ret) 1847 goto failed_clk_ref; 1848 } 1849 } else { 1850 clk_disable_unprepare(fep->clk_ahb); 1851 clk_disable_unprepare(fep->clk_ipg); 1852 if (fep->clk_enet_out) 1853 clk_disable_unprepare(fep->clk_enet_out); 1854 if (fep->clk_ptp) { 1855 mutex_lock(&fep->ptp_clk_mutex); 1856 clk_disable_unprepare(fep->clk_ptp); 1857 fep->ptp_clk_on = false; 1858 mutex_unlock(&fep->ptp_clk_mutex); 1859 } 1860 if (fep->clk_ref) 1861 clk_disable_unprepare(fep->clk_ref); 1862 } 1863 1864 return 0; 1865 1866 failed_clk_ref: 1867 if (fep->clk_ref) 1868 clk_disable_unprepare(fep->clk_ref); 1869 failed_clk_ptp: 1870 if (fep->clk_enet_out) 1871 clk_disable_unprepare(fep->clk_enet_out); 1872 failed_clk_enet_out: 1873 clk_disable_unprepare(fep->clk_ipg); 1874 failed_clk_ipg: 1875 clk_disable_unprepare(fep->clk_ahb); 1876 1877 return ret; 1878 } 1879 1880 static int fec_enet_mii_probe(struct net_device *ndev) 1881 { 1882 struct fec_enet_private *fep = netdev_priv(ndev); 1883 const struct platform_device_id *id_entry = 1884 platform_get_device_id(fep->pdev); 1885 struct phy_device *phy_dev = NULL; 1886 char mdio_bus_id[MII_BUS_ID_SIZE]; 1887 char phy_name[MII_BUS_ID_SIZE + 3]; 1888 int phy_id; 1889 int dev_id = fep->dev_id; 1890 1891 fep->phy_dev = NULL; 1892 1893 if (fep->phy_node) { 1894 phy_dev = of_phy_connect(ndev, fep->phy_node, 1895 &fec_enet_adjust_link, 0, 1896 fep->phy_interface); 1897 } else { 1898 /* check for attached phy */ 1899 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1900 if ((fep->mii_bus->phy_mask & (1 << phy_id))) 1901 continue; 1902 if (fep->mii_bus->phy_map[phy_id] == NULL) 1903 continue; 1904 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) 1905 continue; 1906 if (dev_id--) 1907 continue; 1908 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1909 break; 1910 } 1911 1912 if (phy_id >= PHY_MAX_ADDR) { 1913 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1914 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 1915 phy_id = 0; 1916 } 1917 1918 snprintf(phy_name, sizeof(phy_name), 1919 PHY_ID_FMT, mdio_bus_id, phy_id); 1920 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 1921 fep->phy_interface); 1922 } 1923 1924 if (IS_ERR(phy_dev)) { 1925 netdev_err(ndev, "could not attach to PHY\n"); 1926 return PTR_ERR(phy_dev); 1927 } 1928 1929 /* mask with MAC supported features */ 1930 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) { 1931 phy_dev->supported &= PHY_GBIT_FEATURES; 1932 phy_dev->supported &= ~SUPPORTED_1000baseT_Half; 1933 #if !defined(CONFIG_M5272) 1934 phy_dev->supported |= SUPPORTED_Pause; 1935 #endif 1936 } 1937 else 1938 phy_dev->supported &= PHY_BASIC_FEATURES; 1939 1940 phy_dev->advertising = phy_dev->supported; 1941 1942 fep->phy_dev = phy_dev; 1943 fep->link = 0; 1944 fep->full_duplex = 0; 1945 1946 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 1947 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), 1948 fep->phy_dev->irq); 1949 1950 return 0; 1951 } 1952 1953 static int fec_enet_mii_init(struct platform_device *pdev) 1954 { 1955 static struct mii_bus *fec0_mii_bus; 1956 struct net_device *ndev = platform_get_drvdata(pdev); 1957 struct fec_enet_private *fep = netdev_priv(ndev); 1958 const struct platform_device_id *id_entry = 1959 platform_get_device_id(fep->pdev); 1960 struct device_node *node; 1961 int err = -ENXIO, i; 1962 1963 /* 1964 * The dual fec interfaces are not equivalent with enet-mac. 1965 * Here are the differences: 1966 * 1967 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1968 * - fec0 acts as the 1588 time master while fec1 is slave 1969 * - external phys can only be configured by fec0 1970 * 1971 * That is to say fec1 can not work independently. It only works 1972 * when fec0 is working. The reason behind this design is that the 1973 * second interface is added primarily for Switch mode. 1974 * 1975 * Because of the last point above, both phys are attached on fec0 1976 * mdio interface in board design, and need to be configured by 1977 * fec0 mii_bus. 1978 */ 1979 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { 1980 /* fec1 uses fec0 mii_bus */ 1981 if (mii_cnt && fec0_mii_bus) { 1982 fep->mii_bus = fec0_mii_bus; 1983 mii_cnt++; 1984 return 0; 1985 } 1986 return -ENOENT; 1987 } 1988 1989 fep->mii_timeout = 0; 1990 1991 /* 1992 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 1993 * 1994 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 1995 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 1996 * Reference Manual has an error on this, and gets fixed on i.MX6Q 1997 * document. 1998 */ 1999 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000); 2000 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 2001 fep->phy_speed--; 2002 fep->phy_speed <<= 1; 2003 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2004 2005 fep->mii_bus = mdiobus_alloc(); 2006 if (fep->mii_bus == NULL) { 2007 err = -ENOMEM; 2008 goto err_out; 2009 } 2010 2011 fep->mii_bus->name = "fec_enet_mii_bus"; 2012 fep->mii_bus->read = fec_enet_mdio_read; 2013 fep->mii_bus->write = fec_enet_mdio_write; 2014 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2015 pdev->name, fep->dev_id + 1); 2016 fep->mii_bus->priv = fep; 2017 fep->mii_bus->parent = &pdev->dev; 2018 2019 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 2020 if (!fep->mii_bus->irq) { 2021 err = -ENOMEM; 2022 goto err_out_free_mdiobus; 2023 } 2024 2025 for (i = 0; i < PHY_MAX_ADDR; i++) 2026 fep->mii_bus->irq[i] = PHY_POLL; 2027 2028 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2029 if (node) { 2030 err = of_mdiobus_register(fep->mii_bus, node); 2031 of_node_put(node); 2032 } else { 2033 err = mdiobus_register(fep->mii_bus); 2034 } 2035 2036 if (err) 2037 goto err_out_free_mdio_irq; 2038 2039 mii_cnt++; 2040 2041 /* save fec0 mii_bus */ 2042 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 2043 fec0_mii_bus = fep->mii_bus; 2044 2045 return 0; 2046 2047 err_out_free_mdio_irq: 2048 kfree(fep->mii_bus->irq); 2049 err_out_free_mdiobus: 2050 mdiobus_free(fep->mii_bus); 2051 err_out: 2052 return err; 2053 } 2054 2055 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2056 { 2057 if (--mii_cnt == 0) { 2058 mdiobus_unregister(fep->mii_bus); 2059 kfree(fep->mii_bus->irq); 2060 mdiobus_free(fep->mii_bus); 2061 } 2062 } 2063 2064 static int fec_enet_get_settings(struct net_device *ndev, 2065 struct ethtool_cmd *cmd) 2066 { 2067 struct fec_enet_private *fep = netdev_priv(ndev); 2068 struct phy_device *phydev = fep->phy_dev; 2069 2070 if (!phydev) 2071 return -ENODEV; 2072 2073 return phy_ethtool_gset(phydev, cmd); 2074 } 2075 2076 static int fec_enet_set_settings(struct net_device *ndev, 2077 struct ethtool_cmd *cmd) 2078 { 2079 struct fec_enet_private *fep = netdev_priv(ndev); 2080 struct phy_device *phydev = fep->phy_dev; 2081 2082 if (!phydev) 2083 return -ENODEV; 2084 2085 return phy_ethtool_sset(phydev, cmd); 2086 } 2087 2088 static void fec_enet_get_drvinfo(struct net_device *ndev, 2089 struct ethtool_drvinfo *info) 2090 { 2091 struct fec_enet_private *fep = netdev_priv(ndev); 2092 2093 strlcpy(info->driver, fep->pdev->dev.driver->name, 2094 sizeof(info->driver)); 2095 strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); 2096 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2097 } 2098 2099 static int fec_enet_get_ts_info(struct net_device *ndev, 2100 struct ethtool_ts_info *info) 2101 { 2102 struct fec_enet_private *fep = netdev_priv(ndev); 2103 2104 if (fep->bufdesc_ex) { 2105 2106 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2107 SOF_TIMESTAMPING_RX_SOFTWARE | 2108 SOF_TIMESTAMPING_SOFTWARE | 2109 SOF_TIMESTAMPING_TX_HARDWARE | 2110 SOF_TIMESTAMPING_RX_HARDWARE | 2111 SOF_TIMESTAMPING_RAW_HARDWARE; 2112 if (fep->ptp_clock) 2113 info->phc_index = ptp_clock_index(fep->ptp_clock); 2114 else 2115 info->phc_index = -1; 2116 2117 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2118 (1 << HWTSTAMP_TX_ON); 2119 2120 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2121 (1 << HWTSTAMP_FILTER_ALL); 2122 return 0; 2123 } else { 2124 return ethtool_op_get_ts_info(ndev, info); 2125 } 2126 } 2127 2128 #if !defined(CONFIG_M5272) 2129 2130 static void fec_enet_get_pauseparam(struct net_device *ndev, 2131 struct ethtool_pauseparam *pause) 2132 { 2133 struct fec_enet_private *fep = netdev_priv(ndev); 2134 2135 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2136 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2137 pause->rx_pause = pause->tx_pause; 2138 } 2139 2140 static int fec_enet_set_pauseparam(struct net_device *ndev, 2141 struct ethtool_pauseparam *pause) 2142 { 2143 struct fec_enet_private *fep = netdev_priv(ndev); 2144 2145 if (!fep->phy_dev) 2146 return -ENODEV; 2147 2148 if (pause->tx_pause != pause->rx_pause) { 2149 netdev_info(ndev, 2150 "hardware only support enable/disable both tx and rx"); 2151 return -EINVAL; 2152 } 2153 2154 fep->pause_flag = 0; 2155 2156 /* tx pause must be same as rx pause */ 2157 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2158 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2159 2160 if (pause->rx_pause || pause->autoneg) { 2161 fep->phy_dev->supported |= ADVERTISED_Pause; 2162 fep->phy_dev->advertising |= ADVERTISED_Pause; 2163 } else { 2164 fep->phy_dev->supported &= ~ADVERTISED_Pause; 2165 fep->phy_dev->advertising &= ~ADVERTISED_Pause; 2166 } 2167 2168 if (pause->autoneg) { 2169 if (netif_running(ndev)) 2170 fec_stop(ndev); 2171 phy_start_aneg(fep->phy_dev); 2172 } 2173 if (netif_running(ndev)) { 2174 napi_disable(&fep->napi); 2175 netif_tx_lock_bh(ndev); 2176 fec_restart(ndev); 2177 netif_wake_queue(ndev); 2178 netif_tx_unlock_bh(ndev); 2179 napi_enable(&fep->napi); 2180 } 2181 2182 return 0; 2183 } 2184 2185 static const struct fec_stat { 2186 char name[ETH_GSTRING_LEN]; 2187 u16 offset; 2188 } fec_stats[] = { 2189 /* RMON TX */ 2190 { "tx_dropped", RMON_T_DROP }, 2191 { "tx_packets", RMON_T_PACKETS }, 2192 { "tx_broadcast", RMON_T_BC_PKT }, 2193 { "tx_multicast", RMON_T_MC_PKT }, 2194 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2195 { "tx_undersize", RMON_T_UNDERSIZE }, 2196 { "tx_oversize", RMON_T_OVERSIZE }, 2197 { "tx_fragment", RMON_T_FRAG }, 2198 { "tx_jabber", RMON_T_JAB }, 2199 { "tx_collision", RMON_T_COL }, 2200 { "tx_64byte", RMON_T_P64 }, 2201 { "tx_65to127byte", RMON_T_P65TO127 }, 2202 { "tx_128to255byte", RMON_T_P128TO255 }, 2203 { "tx_256to511byte", RMON_T_P256TO511 }, 2204 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2205 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2206 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2207 { "tx_octets", RMON_T_OCTETS }, 2208 2209 /* IEEE TX */ 2210 { "IEEE_tx_drop", IEEE_T_DROP }, 2211 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2212 { "IEEE_tx_1col", IEEE_T_1COL }, 2213 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2214 { "IEEE_tx_def", IEEE_T_DEF }, 2215 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2216 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2217 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2218 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2219 { "IEEE_tx_sqe", IEEE_T_SQE }, 2220 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2221 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2222 2223 /* RMON RX */ 2224 { "rx_packets", RMON_R_PACKETS }, 2225 { "rx_broadcast", RMON_R_BC_PKT }, 2226 { "rx_multicast", RMON_R_MC_PKT }, 2227 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2228 { "rx_undersize", RMON_R_UNDERSIZE }, 2229 { "rx_oversize", RMON_R_OVERSIZE }, 2230 { "rx_fragment", RMON_R_FRAG }, 2231 { "rx_jabber", RMON_R_JAB }, 2232 { "rx_64byte", RMON_R_P64 }, 2233 { "rx_65to127byte", RMON_R_P65TO127 }, 2234 { "rx_128to255byte", RMON_R_P128TO255 }, 2235 { "rx_256to511byte", RMON_R_P256TO511 }, 2236 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2237 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2238 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2239 { "rx_octets", RMON_R_OCTETS }, 2240 2241 /* IEEE RX */ 2242 { "IEEE_rx_drop", IEEE_R_DROP }, 2243 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2244 { "IEEE_rx_crc", IEEE_R_CRC }, 2245 { "IEEE_rx_align", IEEE_R_ALIGN }, 2246 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2247 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2248 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2249 }; 2250 2251 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2252 struct ethtool_stats *stats, u64 *data) 2253 { 2254 struct fec_enet_private *fep = netdev_priv(dev); 2255 int i; 2256 2257 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2258 data[i] = readl(fep->hwp + fec_stats[i].offset); 2259 } 2260 2261 static void fec_enet_get_strings(struct net_device *netdev, 2262 u32 stringset, u8 *data) 2263 { 2264 int i; 2265 switch (stringset) { 2266 case ETH_SS_STATS: 2267 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2268 memcpy(data + i * ETH_GSTRING_LEN, 2269 fec_stats[i].name, ETH_GSTRING_LEN); 2270 break; 2271 } 2272 } 2273 2274 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2275 { 2276 switch (sset) { 2277 case ETH_SS_STATS: 2278 return ARRAY_SIZE(fec_stats); 2279 default: 2280 return -EOPNOTSUPP; 2281 } 2282 } 2283 #endif /* !defined(CONFIG_M5272) */ 2284 2285 static int fec_enet_nway_reset(struct net_device *dev) 2286 { 2287 struct fec_enet_private *fep = netdev_priv(dev); 2288 struct phy_device *phydev = fep->phy_dev; 2289 2290 if (!phydev) 2291 return -ENODEV; 2292 2293 return genphy_restart_aneg(phydev); 2294 } 2295 2296 /* ITR clock source is enet system clock (clk_ahb). 2297 * TCTT unit is cycle_ns * 64 cycle 2298 * So, the ICTT value = X us / (cycle_ns * 64) 2299 */ 2300 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2301 { 2302 struct fec_enet_private *fep = netdev_priv(ndev); 2303 2304 return us * (fep->itr_clk_rate / 64000) / 1000; 2305 } 2306 2307 /* Set threshold for interrupt coalescing */ 2308 static void fec_enet_itr_coal_set(struct net_device *ndev) 2309 { 2310 struct fec_enet_private *fep = netdev_priv(ndev); 2311 const struct platform_device_id *id_entry = 2312 platform_get_device_id(fep->pdev); 2313 int rx_itr, tx_itr; 2314 2315 if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB)) 2316 return; 2317 2318 /* Must be greater than zero to avoid unpredictable behavior */ 2319 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2320 !fep->tx_time_itr || !fep->tx_pkts_itr) 2321 return; 2322 2323 /* Select enet system clock as Interrupt Coalescing 2324 * timer Clock Source 2325 */ 2326 rx_itr = FEC_ITR_CLK_SEL; 2327 tx_itr = FEC_ITR_CLK_SEL; 2328 2329 /* set ICFT and ICTT */ 2330 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2331 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2332 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2333 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2334 2335 rx_itr |= FEC_ITR_EN; 2336 tx_itr |= FEC_ITR_EN; 2337 2338 writel(tx_itr, fep->hwp + FEC_TXIC0); 2339 writel(rx_itr, fep->hwp + FEC_RXIC0); 2340 writel(tx_itr, fep->hwp + FEC_TXIC1); 2341 writel(rx_itr, fep->hwp + FEC_RXIC1); 2342 writel(tx_itr, fep->hwp + FEC_TXIC2); 2343 writel(rx_itr, fep->hwp + FEC_RXIC2); 2344 } 2345 2346 static int 2347 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2348 { 2349 struct fec_enet_private *fep = netdev_priv(ndev); 2350 const struct platform_device_id *id_entry = 2351 platform_get_device_id(fep->pdev); 2352 2353 if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB)) 2354 return -EOPNOTSUPP; 2355 2356 ec->rx_coalesce_usecs = fep->rx_time_itr; 2357 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2358 2359 ec->tx_coalesce_usecs = fep->tx_time_itr; 2360 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2361 2362 return 0; 2363 } 2364 2365 static int 2366 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2367 { 2368 struct fec_enet_private *fep = netdev_priv(ndev); 2369 const struct platform_device_id *id_entry = 2370 platform_get_device_id(fep->pdev); 2371 2372 unsigned int cycle; 2373 2374 if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB)) 2375 return -EOPNOTSUPP; 2376 2377 if (ec->rx_max_coalesced_frames > 255) { 2378 pr_err("Rx coalesced frames exceed hardware limiation"); 2379 return -EINVAL; 2380 } 2381 2382 if (ec->tx_max_coalesced_frames > 255) { 2383 pr_err("Tx coalesced frame exceed hardware limiation"); 2384 return -EINVAL; 2385 } 2386 2387 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); 2388 if (cycle > 0xFFFF) { 2389 pr_err("Rx coalesed usec exceeed hardware limiation"); 2390 return -EINVAL; 2391 } 2392 2393 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); 2394 if (cycle > 0xFFFF) { 2395 pr_err("Rx coalesed usec exceeed hardware limiation"); 2396 return -EINVAL; 2397 } 2398 2399 fep->rx_time_itr = ec->rx_coalesce_usecs; 2400 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2401 2402 fep->tx_time_itr = ec->tx_coalesce_usecs; 2403 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2404 2405 fec_enet_itr_coal_set(ndev); 2406 2407 return 0; 2408 } 2409 2410 static void fec_enet_itr_coal_init(struct net_device *ndev) 2411 { 2412 struct ethtool_coalesce ec; 2413 2414 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2415 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2416 2417 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2418 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2419 2420 fec_enet_set_coalesce(ndev, &ec); 2421 } 2422 2423 static int fec_enet_get_tunable(struct net_device *netdev, 2424 const struct ethtool_tunable *tuna, 2425 void *data) 2426 { 2427 struct fec_enet_private *fep = netdev_priv(netdev); 2428 int ret = 0; 2429 2430 switch (tuna->id) { 2431 case ETHTOOL_RX_COPYBREAK: 2432 *(u32 *)data = fep->rx_copybreak; 2433 break; 2434 default: 2435 ret = -EINVAL; 2436 break; 2437 } 2438 2439 return ret; 2440 } 2441 2442 static int fec_enet_set_tunable(struct net_device *netdev, 2443 const struct ethtool_tunable *tuna, 2444 const void *data) 2445 { 2446 struct fec_enet_private *fep = netdev_priv(netdev); 2447 int ret = 0; 2448 2449 switch (tuna->id) { 2450 case ETHTOOL_RX_COPYBREAK: 2451 fep->rx_copybreak = *(u32 *)data; 2452 break; 2453 default: 2454 ret = -EINVAL; 2455 break; 2456 } 2457 2458 return ret; 2459 } 2460 2461 static const struct ethtool_ops fec_enet_ethtool_ops = { 2462 .get_settings = fec_enet_get_settings, 2463 .set_settings = fec_enet_set_settings, 2464 .get_drvinfo = fec_enet_get_drvinfo, 2465 .nway_reset = fec_enet_nway_reset, 2466 .get_link = ethtool_op_get_link, 2467 .get_coalesce = fec_enet_get_coalesce, 2468 .set_coalesce = fec_enet_set_coalesce, 2469 #ifndef CONFIG_M5272 2470 .get_pauseparam = fec_enet_get_pauseparam, 2471 .set_pauseparam = fec_enet_set_pauseparam, 2472 .get_strings = fec_enet_get_strings, 2473 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2474 .get_sset_count = fec_enet_get_sset_count, 2475 #endif 2476 .get_ts_info = fec_enet_get_ts_info, 2477 .get_tunable = fec_enet_get_tunable, 2478 .set_tunable = fec_enet_set_tunable, 2479 }; 2480 2481 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2482 { 2483 struct fec_enet_private *fep = netdev_priv(ndev); 2484 struct phy_device *phydev = fep->phy_dev; 2485 2486 if (!netif_running(ndev)) 2487 return -EINVAL; 2488 2489 if (!phydev) 2490 return -ENODEV; 2491 2492 if (fep->bufdesc_ex) { 2493 if (cmd == SIOCSHWTSTAMP) 2494 return fec_ptp_set(ndev, rq); 2495 if (cmd == SIOCGHWTSTAMP) 2496 return fec_ptp_get(ndev, rq); 2497 } 2498 2499 return phy_mii_ioctl(phydev, rq, cmd); 2500 } 2501 2502 static void fec_enet_free_buffers(struct net_device *ndev) 2503 { 2504 struct fec_enet_private *fep = netdev_priv(ndev); 2505 unsigned int i; 2506 struct sk_buff *skb; 2507 struct bufdesc *bdp; 2508 struct fec_enet_priv_tx_q *txq; 2509 struct fec_enet_priv_rx_q *rxq; 2510 unsigned int q; 2511 2512 for (q = 0; q < fep->num_rx_queues; q++) { 2513 rxq = fep->rx_queue[q]; 2514 bdp = rxq->rx_bd_base; 2515 for (i = 0; i < rxq->rx_ring_size; i++) { 2516 skb = rxq->rx_skbuff[i]; 2517 rxq->rx_skbuff[i] = NULL; 2518 if (skb) { 2519 dma_unmap_single(&fep->pdev->dev, 2520 bdp->cbd_bufaddr, 2521 FEC_ENET_RX_FRSIZE - fep->rx_align, 2522 DMA_FROM_DEVICE); 2523 dev_kfree_skb(skb); 2524 } 2525 bdp = fec_enet_get_nextdesc(bdp, fep, q); 2526 } 2527 } 2528 2529 for (q = 0; q < fep->num_tx_queues; q++) { 2530 txq = fep->tx_queue[q]; 2531 bdp = txq->tx_bd_base; 2532 for (i = 0; i < txq->tx_ring_size; i++) { 2533 kfree(txq->tx_bounce[i]); 2534 txq->tx_bounce[i] = NULL; 2535 skb = txq->tx_skbuff[i]; 2536 txq->tx_skbuff[i] = NULL; 2537 dev_kfree_skb(skb); 2538 } 2539 } 2540 } 2541 2542 static void fec_enet_free_queue(struct net_device *ndev) 2543 { 2544 struct fec_enet_private *fep = netdev_priv(ndev); 2545 int i; 2546 struct fec_enet_priv_tx_q *txq; 2547 2548 for (i = 0; i < fep->num_tx_queues; i++) 2549 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2550 txq = fep->tx_queue[i]; 2551 dma_free_coherent(NULL, 2552 txq->tx_ring_size * TSO_HEADER_SIZE, 2553 txq->tso_hdrs, 2554 txq->tso_hdrs_dma); 2555 } 2556 2557 for (i = 0; i < fep->num_rx_queues; i++) 2558 if (fep->rx_queue[i]) 2559 kfree(fep->rx_queue[i]); 2560 2561 for (i = 0; i < fep->num_tx_queues; i++) 2562 if (fep->tx_queue[i]) 2563 kfree(fep->tx_queue[i]); 2564 } 2565 2566 static int fec_enet_alloc_queue(struct net_device *ndev) 2567 { 2568 struct fec_enet_private *fep = netdev_priv(ndev); 2569 int i; 2570 int ret = 0; 2571 struct fec_enet_priv_tx_q *txq; 2572 2573 for (i = 0; i < fep->num_tx_queues; i++) { 2574 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 2575 if (!txq) { 2576 ret = -ENOMEM; 2577 goto alloc_failed; 2578 } 2579 2580 fep->tx_queue[i] = txq; 2581 txq->tx_ring_size = TX_RING_SIZE; 2582 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size; 2583 2584 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2585 txq->tx_wake_threshold = 2586 (txq->tx_ring_size - txq->tx_stop_threshold) / 2; 2587 2588 txq->tso_hdrs = dma_alloc_coherent(NULL, 2589 txq->tx_ring_size * TSO_HEADER_SIZE, 2590 &txq->tso_hdrs_dma, 2591 GFP_KERNEL); 2592 if (!txq->tso_hdrs) { 2593 ret = -ENOMEM; 2594 goto alloc_failed; 2595 } 2596 } 2597 2598 for (i = 0; i < fep->num_rx_queues; i++) { 2599 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 2600 GFP_KERNEL); 2601 if (!fep->rx_queue[i]) { 2602 ret = -ENOMEM; 2603 goto alloc_failed; 2604 } 2605 2606 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE; 2607 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size; 2608 } 2609 return ret; 2610 2611 alloc_failed: 2612 fec_enet_free_queue(ndev); 2613 return ret; 2614 } 2615 2616 static int 2617 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 2618 { 2619 struct fec_enet_private *fep = netdev_priv(ndev); 2620 unsigned int i; 2621 struct sk_buff *skb; 2622 struct bufdesc *bdp; 2623 struct fec_enet_priv_rx_q *rxq; 2624 2625 rxq = fep->rx_queue[queue]; 2626 bdp = rxq->rx_bd_base; 2627 for (i = 0; i < rxq->rx_ring_size; i++) { 2628 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2629 if (!skb) 2630 goto err_alloc; 2631 2632 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 2633 dev_kfree_skb(skb); 2634 goto err_alloc; 2635 } 2636 2637 rxq->rx_skbuff[i] = skb; 2638 bdp->cbd_sc = BD_ENET_RX_EMPTY; 2639 2640 if (fep->bufdesc_ex) { 2641 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2642 ebdp->cbd_esc = BD_ENET_RX_INT; 2643 } 2644 2645 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 2646 } 2647 2648 /* Set the last buffer to wrap. */ 2649 bdp = fec_enet_get_prevdesc(bdp, fep, queue); 2650 bdp->cbd_sc |= BD_SC_WRAP; 2651 return 0; 2652 2653 err_alloc: 2654 fec_enet_free_buffers(ndev); 2655 return -ENOMEM; 2656 } 2657 2658 static int 2659 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 2660 { 2661 struct fec_enet_private *fep = netdev_priv(ndev); 2662 unsigned int i; 2663 struct bufdesc *bdp; 2664 struct fec_enet_priv_tx_q *txq; 2665 2666 txq = fep->tx_queue[queue]; 2667 bdp = txq->tx_bd_base; 2668 for (i = 0; i < txq->tx_ring_size; i++) { 2669 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2670 if (!txq->tx_bounce[i]) 2671 goto err_alloc; 2672 2673 bdp->cbd_sc = 0; 2674 bdp->cbd_bufaddr = 0; 2675 2676 if (fep->bufdesc_ex) { 2677 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2678 ebdp->cbd_esc = BD_ENET_TX_INT; 2679 } 2680 2681 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 2682 } 2683 2684 /* Set the last buffer to wrap. */ 2685 bdp = fec_enet_get_prevdesc(bdp, fep, queue); 2686 bdp->cbd_sc |= BD_SC_WRAP; 2687 2688 return 0; 2689 2690 err_alloc: 2691 fec_enet_free_buffers(ndev); 2692 return -ENOMEM; 2693 } 2694 2695 static int fec_enet_alloc_buffers(struct net_device *ndev) 2696 { 2697 struct fec_enet_private *fep = netdev_priv(ndev); 2698 unsigned int i; 2699 2700 for (i = 0; i < fep->num_rx_queues; i++) 2701 if (fec_enet_alloc_rxq_buffers(ndev, i)) 2702 return -ENOMEM; 2703 2704 for (i = 0; i < fep->num_tx_queues; i++) 2705 if (fec_enet_alloc_txq_buffers(ndev, i)) 2706 return -ENOMEM; 2707 return 0; 2708 } 2709 2710 static int 2711 fec_enet_open(struct net_device *ndev) 2712 { 2713 struct fec_enet_private *fep = netdev_priv(ndev); 2714 int ret; 2715 2716 pinctrl_pm_select_default_state(&fep->pdev->dev); 2717 ret = fec_enet_clk_enable(ndev, true); 2718 if (ret) 2719 return ret; 2720 2721 /* I should reset the ring buffers here, but I don't yet know 2722 * a simple way to do that. 2723 */ 2724 2725 ret = fec_enet_alloc_buffers(ndev); 2726 if (ret) 2727 goto err_enet_alloc; 2728 2729 /* Probe and connect to PHY when open the interface */ 2730 ret = fec_enet_mii_probe(ndev); 2731 if (ret) 2732 goto err_enet_mii_probe; 2733 2734 fec_restart(ndev); 2735 napi_enable(&fep->napi); 2736 phy_start(fep->phy_dev); 2737 netif_tx_start_all_queues(ndev); 2738 2739 return 0; 2740 2741 err_enet_mii_probe: 2742 fec_enet_free_buffers(ndev); 2743 err_enet_alloc: 2744 fec_enet_clk_enable(ndev, false); 2745 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2746 return ret; 2747 } 2748 2749 static int 2750 fec_enet_close(struct net_device *ndev) 2751 { 2752 struct fec_enet_private *fep = netdev_priv(ndev); 2753 2754 phy_stop(fep->phy_dev); 2755 2756 if (netif_device_present(ndev)) { 2757 napi_disable(&fep->napi); 2758 netif_tx_disable(ndev); 2759 fec_stop(ndev); 2760 } 2761 2762 phy_disconnect(fep->phy_dev); 2763 fep->phy_dev = NULL; 2764 2765 fec_enet_clk_enable(ndev, false); 2766 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2767 fec_enet_free_buffers(ndev); 2768 2769 return 0; 2770 } 2771 2772 /* Set or clear the multicast filter for this adaptor. 2773 * Skeleton taken from sunlance driver. 2774 * The CPM Ethernet implementation allows Multicast as well as individual 2775 * MAC address filtering. Some of the drivers check to make sure it is 2776 * a group multicast address, and discard those that are not. I guess I 2777 * will do the same for now, but just remove the test if you want 2778 * individual filtering as well (do the upper net layers want or support 2779 * this kind of feature?). 2780 */ 2781 2782 #define HASH_BITS 6 /* #bits in hash */ 2783 #define CRC32_POLY 0xEDB88320 2784 2785 static void set_multicast_list(struct net_device *ndev) 2786 { 2787 struct fec_enet_private *fep = netdev_priv(ndev); 2788 struct netdev_hw_addr *ha; 2789 unsigned int i, bit, data, crc, tmp; 2790 unsigned char hash; 2791 2792 if (ndev->flags & IFF_PROMISC) { 2793 tmp = readl(fep->hwp + FEC_R_CNTRL); 2794 tmp |= 0x8; 2795 writel(tmp, fep->hwp + FEC_R_CNTRL); 2796 return; 2797 } 2798 2799 tmp = readl(fep->hwp + FEC_R_CNTRL); 2800 tmp &= ~0x8; 2801 writel(tmp, fep->hwp + FEC_R_CNTRL); 2802 2803 if (ndev->flags & IFF_ALLMULTI) { 2804 /* Catch all multicast addresses, so set the 2805 * filter to all 1's 2806 */ 2807 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2808 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2809 2810 return; 2811 } 2812 2813 /* Clear filter and add the addresses in hash register 2814 */ 2815 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2816 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2817 2818 netdev_for_each_mc_addr(ha, ndev) { 2819 /* calculate crc32 value of mac address */ 2820 crc = 0xffffffff; 2821 2822 for (i = 0; i < ndev->addr_len; i++) { 2823 data = ha->addr[i]; 2824 for (bit = 0; bit < 8; bit++, data >>= 1) { 2825 crc = (crc >> 1) ^ 2826 (((crc ^ data) & 1) ? CRC32_POLY : 0); 2827 } 2828 } 2829 2830 /* only upper 6 bits (HASH_BITS) are used 2831 * which point to specific bit in he hash registers 2832 */ 2833 hash = (crc >> (32 - HASH_BITS)) & 0x3f; 2834 2835 if (hash > 31) { 2836 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2837 tmp |= 1 << (hash - 32); 2838 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2839 } else { 2840 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2841 tmp |= 1 << hash; 2842 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2843 } 2844 } 2845 } 2846 2847 /* Set a MAC change in hardware. */ 2848 static int 2849 fec_set_mac_address(struct net_device *ndev, void *p) 2850 { 2851 struct fec_enet_private *fep = netdev_priv(ndev); 2852 struct sockaddr *addr = p; 2853 2854 if (addr) { 2855 if (!is_valid_ether_addr(addr->sa_data)) 2856 return -EADDRNOTAVAIL; 2857 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 2858 } 2859 2860 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 2861 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 2862 fep->hwp + FEC_ADDR_LOW); 2863 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 2864 fep->hwp + FEC_ADDR_HIGH); 2865 return 0; 2866 } 2867 2868 #ifdef CONFIG_NET_POLL_CONTROLLER 2869 /** 2870 * fec_poll_controller - FEC Poll controller function 2871 * @dev: The FEC network adapter 2872 * 2873 * Polled functionality used by netconsole and others in non interrupt mode 2874 * 2875 */ 2876 static void fec_poll_controller(struct net_device *dev) 2877 { 2878 int i; 2879 struct fec_enet_private *fep = netdev_priv(dev); 2880 2881 for (i = 0; i < FEC_IRQ_NUM; i++) { 2882 if (fep->irq[i] > 0) { 2883 disable_irq(fep->irq[i]); 2884 fec_enet_interrupt(fep->irq[i], dev); 2885 enable_irq(fep->irq[i]); 2886 } 2887 } 2888 } 2889 #endif 2890 2891 #define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM 2892 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 2893 netdev_features_t features) 2894 { 2895 struct fec_enet_private *fep = netdev_priv(netdev); 2896 netdev_features_t changed = features ^ netdev->features; 2897 2898 netdev->features = features; 2899 2900 /* Receive checksum has been changed */ 2901 if (changed & NETIF_F_RXCSUM) { 2902 if (features & NETIF_F_RXCSUM) 2903 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 2904 else 2905 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 2906 } 2907 } 2908 2909 static int fec_set_features(struct net_device *netdev, 2910 netdev_features_t features) 2911 { 2912 struct fec_enet_private *fep = netdev_priv(netdev); 2913 netdev_features_t changed = features ^ netdev->features; 2914 2915 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) { 2916 napi_disable(&fep->napi); 2917 netif_tx_lock_bh(netdev); 2918 fec_stop(netdev); 2919 fec_enet_set_netdev_features(netdev, features); 2920 fec_restart(netdev); 2921 netif_tx_wake_all_queues(netdev); 2922 netif_tx_unlock_bh(netdev); 2923 napi_enable(&fep->napi); 2924 } else { 2925 fec_enet_set_netdev_features(netdev, features); 2926 } 2927 2928 return 0; 2929 } 2930 2931 static const struct net_device_ops fec_netdev_ops = { 2932 .ndo_open = fec_enet_open, 2933 .ndo_stop = fec_enet_close, 2934 .ndo_start_xmit = fec_enet_start_xmit, 2935 .ndo_set_rx_mode = set_multicast_list, 2936 .ndo_change_mtu = eth_change_mtu, 2937 .ndo_validate_addr = eth_validate_addr, 2938 .ndo_tx_timeout = fec_timeout, 2939 .ndo_set_mac_address = fec_set_mac_address, 2940 .ndo_do_ioctl = fec_enet_ioctl, 2941 #ifdef CONFIG_NET_POLL_CONTROLLER 2942 .ndo_poll_controller = fec_poll_controller, 2943 #endif 2944 .ndo_set_features = fec_set_features, 2945 }; 2946 2947 /* 2948 * XXX: We need to clean up on failure exits here. 2949 * 2950 */ 2951 static int fec_enet_init(struct net_device *ndev) 2952 { 2953 struct fec_enet_private *fep = netdev_priv(ndev); 2954 const struct platform_device_id *id_entry = 2955 platform_get_device_id(fep->pdev); 2956 struct fec_enet_priv_tx_q *txq; 2957 struct fec_enet_priv_rx_q *rxq; 2958 struct bufdesc *cbd_base; 2959 dma_addr_t bd_dma; 2960 int bd_size; 2961 unsigned int i; 2962 2963 #if defined(CONFIG_ARM) 2964 fep->rx_align = 0xf; 2965 fep->tx_align = 0xf; 2966 #else 2967 fep->rx_align = 0x3; 2968 fep->tx_align = 0x3; 2969 #endif 2970 2971 fec_enet_alloc_queue(ndev); 2972 2973 if (fep->bufdesc_ex) 2974 fep->bufdesc_size = sizeof(struct bufdesc_ex); 2975 else 2976 fep->bufdesc_size = sizeof(struct bufdesc); 2977 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * 2978 fep->bufdesc_size; 2979 2980 /* Allocate memory for buffer descriptors. */ 2981 cbd_base = dma_alloc_coherent(NULL, bd_size, &bd_dma, 2982 GFP_KERNEL); 2983 if (!cbd_base) { 2984 return -ENOMEM; 2985 } 2986 2987 memset(cbd_base, 0, bd_size); 2988 2989 /* Get the Ethernet address */ 2990 fec_get_mac(ndev); 2991 /* make sure MAC we just acquired is programmed into the hw */ 2992 fec_set_mac_address(ndev, NULL); 2993 2994 /* Set receive and transmit descriptor base. */ 2995 for (i = 0; i < fep->num_rx_queues; i++) { 2996 rxq = fep->rx_queue[i]; 2997 rxq->index = i; 2998 rxq->rx_bd_base = (struct bufdesc *)cbd_base; 2999 rxq->bd_dma = bd_dma; 3000 if (fep->bufdesc_ex) { 3001 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size; 3002 cbd_base = (struct bufdesc *) 3003 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size); 3004 } else { 3005 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size; 3006 cbd_base += rxq->rx_ring_size; 3007 } 3008 } 3009 3010 for (i = 0; i < fep->num_tx_queues; i++) { 3011 txq = fep->tx_queue[i]; 3012 txq->index = i; 3013 txq->tx_bd_base = (struct bufdesc *)cbd_base; 3014 txq->bd_dma = bd_dma; 3015 if (fep->bufdesc_ex) { 3016 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size; 3017 cbd_base = (struct bufdesc *) 3018 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size); 3019 } else { 3020 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size; 3021 cbd_base += txq->tx_ring_size; 3022 } 3023 } 3024 3025 3026 /* The FEC Ethernet specific entries in the device structure */ 3027 ndev->watchdog_timeo = TX_TIMEOUT; 3028 ndev->netdev_ops = &fec_netdev_ops; 3029 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3030 3031 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3032 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3033 3034 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) 3035 /* enable hw VLAN support */ 3036 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3037 3038 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) { 3039 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3040 3041 /* enable hw accelerator */ 3042 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3043 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3044 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3045 } 3046 3047 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB) { 3048 fep->tx_align = 0; 3049 fep->rx_align = 0x3f; 3050 } 3051 3052 ndev->hw_features = ndev->features; 3053 3054 fec_restart(ndev); 3055 3056 return 0; 3057 } 3058 3059 #ifdef CONFIG_OF 3060 static void fec_reset_phy(struct platform_device *pdev) 3061 { 3062 int err, phy_reset; 3063 int msec = 1; 3064 struct device_node *np = pdev->dev.of_node; 3065 3066 if (!np) 3067 return; 3068 3069 of_property_read_u32(np, "phy-reset-duration", &msec); 3070 /* A sane reset duration should not be longer than 1s */ 3071 if (msec > 1000) 3072 msec = 1; 3073 3074 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3075 if (!gpio_is_valid(phy_reset)) 3076 return; 3077 3078 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3079 GPIOF_OUT_INIT_LOW, "phy-reset"); 3080 if (err) { 3081 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3082 return; 3083 } 3084 msleep(msec); 3085 gpio_set_value(phy_reset, 1); 3086 } 3087 #else /* CONFIG_OF */ 3088 static void fec_reset_phy(struct platform_device *pdev) 3089 { 3090 /* 3091 * In case of platform probe, the reset has been done 3092 * by machine code. 3093 */ 3094 } 3095 #endif /* CONFIG_OF */ 3096 3097 static void 3098 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3099 { 3100 struct device_node *np = pdev->dev.of_node; 3101 int err; 3102 3103 *num_tx = *num_rx = 1; 3104 3105 if (!np || !of_device_is_available(np)) 3106 return; 3107 3108 /* parse the num of tx and rx queues */ 3109 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3110 if (err) 3111 *num_tx = 1; 3112 3113 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3114 if (err) 3115 *num_rx = 1; 3116 3117 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3118 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3119 *num_tx); 3120 *num_tx = 1; 3121 return; 3122 } 3123 3124 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3125 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3126 *num_rx); 3127 *num_rx = 1; 3128 return; 3129 } 3130 3131 } 3132 3133 static int 3134 fec_probe(struct platform_device *pdev) 3135 { 3136 struct fec_enet_private *fep; 3137 struct fec_platform_data *pdata; 3138 struct net_device *ndev; 3139 int i, irq, ret = 0; 3140 struct resource *r; 3141 const struct of_device_id *of_id; 3142 static int dev_id; 3143 struct device_node *np = pdev->dev.of_node, *phy_node; 3144 int num_tx_qs; 3145 int num_rx_qs; 3146 3147 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3148 if (of_id) 3149 pdev->id_entry = of_id->data; 3150 3151 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3152 3153 /* Init network device */ 3154 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private), 3155 num_tx_qs, num_rx_qs); 3156 if (!ndev) 3157 return -ENOMEM; 3158 3159 SET_NETDEV_DEV(ndev, &pdev->dev); 3160 3161 /* setup board info structure */ 3162 fep = netdev_priv(ndev); 3163 3164 fep->num_rx_queues = num_rx_qs; 3165 fep->num_tx_queues = num_tx_qs; 3166 3167 #if !defined(CONFIG_M5272) 3168 /* default enable pause frame auto negotiation */ 3169 if (pdev->id_entry && 3170 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT)) 3171 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3172 #endif 3173 3174 /* Select default pin state */ 3175 pinctrl_pm_select_default_state(&pdev->dev); 3176 3177 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3178 fep->hwp = devm_ioremap_resource(&pdev->dev, r); 3179 if (IS_ERR(fep->hwp)) { 3180 ret = PTR_ERR(fep->hwp); 3181 goto failed_ioremap; 3182 } 3183 3184 fep->pdev = pdev; 3185 fep->dev_id = dev_id++; 3186 3187 fep->bufdesc_ex = 0; 3188 3189 platform_set_drvdata(pdev, ndev); 3190 3191 phy_node = of_parse_phandle(np, "phy-handle", 0); 3192 if (!phy_node && of_phy_is_fixed_link(np)) { 3193 ret = of_phy_register_fixed_link(np); 3194 if (ret < 0) { 3195 dev_err(&pdev->dev, 3196 "broken fixed-link specification\n"); 3197 goto failed_phy; 3198 } 3199 phy_node = of_node_get(np); 3200 } 3201 fep->phy_node = phy_node; 3202 3203 ret = of_get_phy_mode(pdev->dev.of_node); 3204 if (ret < 0) { 3205 pdata = dev_get_platdata(&pdev->dev); 3206 if (pdata) 3207 fep->phy_interface = pdata->phy; 3208 else 3209 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3210 } else { 3211 fep->phy_interface = ret; 3212 } 3213 3214 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3215 if (IS_ERR(fep->clk_ipg)) { 3216 ret = PTR_ERR(fep->clk_ipg); 3217 goto failed_clk; 3218 } 3219 3220 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3221 if (IS_ERR(fep->clk_ahb)) { 3222 ret = PTR_ERR(fep->clk_ahb); 3223 goto failed_clk; 3224 } 3225 3226 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3227 3228 /* enet_out is optional, depends on board */ 3229 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3230 if (IS_ERR(fep->clk_enet_out)) 3231 fep->clk_enet_out = NULL; 3232 3233 fep->ptp_clk_on = false; 3234 mutex_init(&fep->ptp_clk_mutex); 3235 3236 /* clk_ref is optional, depends on board */ 3237 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3238 if (IS_ERR(fep->clk_ref)) 3239 fep->clk_ref = NULL; 3240 3241 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3242 fep->bufdesc_ex = 3243 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX; 3244 if (IS_ERR(fep->clk_ptp)) { 3245 fep->clk_ptp = NULL; 3246 fep->bufdesc_ex = 0; 3247 } 3248 3249 ret = fec_enet_clk_enable(ndev, true); 3250 if (ret) 3251 goto failed_clk; 3252 3253 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); 3254 if (!IS_ERR(fep->reg_phy)) { 3255 ret = regulator_enable(fep->reg_phy); 3256 if (ret) { 3257 dev_err(&pdev->dev, 3258 "Failed to enable phy regulator: %d\n", ret); 3259 goto failed_regulator; 3260 } 3261 } else { 3262 fep->reg_phy = NULL; 3263 } 3264 3265 fec_reset_phy(pdev); 3266 3267 if (fep->bufdesc_ex) 3268 fec_ptp_init(pdev); 3269 3270 ret = fec_enet_init(ndev); 3271 if (ret) 3272 goto failed_init; 3273 3274 for (i = 0; i < FEC_IRQ_NUM; i++) { 3275 irq = platform_get_irq(pdev, i); 3276 if (irq < 0) { 3277 if (i) 3278 break; 3279 ret = irq; 3280 goto failed_irq; 3281 } 3282 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3283 0, pdev->name, ndev); 3284 if (ret) 3285 goto failed_irq; 3286 } 3287 3288 init_completion(&fep->mdio_done); 3289 ret = fec_enet_mii_init(pdev); 3290 if (ret) 3291 goto failed_mii_init; 3292 3293 /* Carrier starts down, phylib will bring it up */ 3294 netif_carrier_off(ndev); 3295 fec_enet_clk_enable(ndev, false); 3296 pinctrl_pm_select_sleep_state(&pdev->dev); 3297 3298 ret = register_netdev(ndev); 3299 if (ret) 3300 goto failed_register; 3301 3302 if (fep->bufdesc_ex && fep->ptp_clock) 3303 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3304 3305 fep->rx_copybreak = COPYBREAK_DEFAULT; 3306 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3307 return 0; 3308 3309 failed_register: 3310 fec_enet_mii_remove(fep); 3311 failed_mii_init: 3312 failed_irq: 3313 failed_init: 3314 if (fep->reg_phy) 3315 regulator_disable(fep->reg_phy); 3316 failed_regulator: 3317 fec_enet_clk_enable(ndev, false); 3318 failed_clk: 3319 failed_phy: 3320 of_node_put(phy_node); 3321 failed_ioremap: 3322 free_netdev(ndev); 3323 3324 return ret; 3325 } 3326 3327 static int 3328 fec_drv_remove(struct platform_device *pdev) 3329 { 3330 struct net_device *ndev = platform_get_drvdata(pdev); 3331 struct fec_enet_private *fep = netdev_priv(ndev); 3332 3333 cancel_delayed_work_sync(&fep->time_keep); 3334 cancel_work_sync(&fep->tx_timeout_work); 3335 unregister_netdev(ndev); 3336 fec_enet_mii_remove(fep); 3337 if (fep->reg_phy) 3338 regulator_disable(fep->reg_phy); 3339 if (fep->ptp_clock) 3340 ptp_clock_unregister(fep->ptp_clock); 3341 fec_enet_clk_enable(ndev, false); 3342 of_node_put(fep->phy_node); 3343 free_netdev(ndev); 3344 3345 return 0; 3346 } 3347 3348 static int __maybe_unused fec_suspend(struct device *dev) 3349 { 3350 struct net_device *ndev = dev_get_drvdata(dev); 3351 struct fec_enet_private *fep = netdev_priv(ndev); 3352 3353 rtnl_lock(); 3354 if (netif_running(ndev)) { 3355 phy_stop(fep->phy_dev); 3356 napi_disable(&fep->napi); 3357 netif_tx_lock_bh(ndev); 3358 netif_device_detach(ndev); 3359 netif_tx_unlock_bh(ndev); 3360 fec_stop(ndev); 3361 fec_enet_clk_enable(ndev, false); 3362 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3363 } 3364 rtnl_unlock(); 3365 3366 if (fep->reg_phy) 3367 regulator_disable(fep->reg_phy); 3368 3369 return 0; 3370 } 3371 3372 static int __maybe_unused fec_resume(struct device *dev) 3373 { 3374 struct net_device *ndev = dev_get_drvdata(dev); 3375 struct fec_enet_private *fep = netdev_priv(ndev); 3376 int ret; 3377 3378 if (fep->reg_phy) { 3379 ret = regulator_enable(fep->reg_phy); 3380 if (ret) 3381 return ret; 3382 } 3383 3384 rtnl_lock(); 3385 if (netif_running(ndev)) { 3386 pinctrl_pm_select_default_state(&fep->pdev->dev); 3387 ret = fec_enet_clk_enable(ndev, true); 3388 if (ret) { 3389 rtnl_unlock(); 3390 goto failed_clk; 3391 } 3392 fec_restart(ndev); 3393 netif_tx_lock_bh(ndev); 3394 netif_device_attach(ndev); 3395 netif_tx_unlock_bh(ndev); 3396 napi_enable(&fep->napi); 3397 phy_start(fep->phy_dev); 3398 } 3399 rtnl_unlock(); 3400 3401 return 0; 3402 3403 failed_clk: 3404 if (fep->reg_phy) 3405 regulator_disable(fep->reg_phy); 3406 return ret; 3407 } 3408 3409 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume); 3410 3411 static struct platform_driver fec_driver = { 3412 .driver = { 3413 .name = DRIVER_NAME, 3414 .owner = THIS_MODULE, 3415 .pm = &fec_pm_ops, 3416 .of_match_table = fec_dt_ids, 3417 }, 3418 .id_table = fec_devtype, 3419 .probe = fec_probe, 3420 .remove = fec_drv_remove, 3421 }; 3422 3423 module_platform_driver(fec_driver); 3424 3425 MODULE_ALIAS("platform:"DRIVER_NAME); 3426 MODULE_LICENSE("GPL"); 3427