1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/page_pool/helpers.h> 42 #include <net/selftests.h> 43 #include <net/tso.h> 44 #include <linux/tcp.h> 45 #include <linux/udp.h> 46 #include <linux/icmp.h> 47 #include <linux/spinlock.h> 48 #include <linux/workqueue.h> 49 #include <linux/bitops.h> 50 #include <linux/io.h> 51 #include <linux/irq.h> 52 #include <linux/clk.h> 53 #include <linux/crc32.h> 54 #include <linux/platform_device.h> 55 #include <linux/mdio.h> 56 #include <linux/phy.h> 57 #include <linux/fec.h> 58 #include <linux/of.h> 59 #include <linux/of_device.h> 60 #include <linux/of_mdio.h> 61 #include <linux/of_net.h> 62 #include <linux/regulator/consumer.h> 63 #include <linux/if_vlan.h> 64 #include <linux/pinctrl/consumer.h> 65 #include <linux/gpio/consumer.h> 66 #include <linux/prefetch.h> 67 #include <linux/mfd/syscon.h> 68 #include <linux/regmap.h> 69 #include <soc/imx/cpuidle.h> 70 #include <linux/filter.h> 71 #include <linux/bpf.h> 72 73 #include <asm/cacheflush.h> 74 75 #include "fec.h" 76 77 static void set_multicast_list(struct net_device *ndev); 78 static void fec_enet_itr_coal_set(struct net_device *ndev); 79 80 #define DRIVER_NAME "fec" 81 82 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 83 84 /* Pause frame feild and FIFO threshold */ 85 #define FEC_ENET_FCE (1 << 5) 86 #define FEC_ENET_RSEM_V 0x84 87 #define FEC_ENET_RSFL_V 16 88 #define FEC_ENET_RAEM_V 0x8 89 #define FEC_ENET_RAFL_V 0x8 90 #define FEC_ENET_OPD_V 0xFFF0 91 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 92 93 #define FEC_ENET_XDP_PASS 0 94 #define FEC_ENET_XDP_CONSUMED BIT(0) 95 #define FEC_ENET_XDP_TX BIT(1) 96 #define FEC_ENET_XDP_REDIR BIT(2) 97 98 struct fec_devinfo { 99 u32 quirks; 100 }; 101 102 static const struct fec_devinfo fec_imx25_info = { 103 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 104 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45, 105 }; 106 107 static const struct fec_devinfo fec_imx27_info = { 108 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG | 109 FEC_QUIRK_HAS_MDIO_C45, 110 }; 111 112 static const struct fec_devinfo fec_imx28_info = { 113 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 114 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 115 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 116 FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45, 117 }; 118 119 static const struct fec_devinfo fec_imx6q_info = { 120 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 121 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 122 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 123 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII | 124 FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45, 125 }; 126 127 static const struct fec_devinfo fec_mvf600_info = { 128 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC | 129 FEC_QUIRK_HAS_MDIO_C45, 130 }; 131 132 static const struct fec_devinfo fec_imx6x_info = { 133 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 134 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 135 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 136 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 137 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 138 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 139 FEC_QUIRK_HAS_MDIO_C45, 140 }; 141 142 static const struct fec_devinfo fec_imx6ul_info = { 143 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 144 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 145 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 146 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 147 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII | 148 FEC_QUIRK_HAS_MDIO_C45, 149 }; 150 151 static const struct fec_devinfo fec_imx8mq_info = { 152 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 153 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 154 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 155 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 156 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 157 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 158 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 | 159 FEC_QUIRK_HAS_MDIO_C45, 160 }; 161 162 static const struct fec_devinfo fec_imx8qm_info = { 163 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 164 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 165 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 166 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 167 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 168 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 169 FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45, 170 }; 171 172 static const struct fec_devinfo fec_s32v234_info = { 173 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 174 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 175 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 176 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 177 FEC_QUIRK_HAS_MDIO_C45, 178 }; 179 180 static struct platform_device_id fec_devtype[] = { 181 { 182 /* keep it for coldfire */ 183 .name = DRIVER_NAME, 184 .driver_data = 0, 185 }, { 186 .name = "imx25-fec", 187 .driver_data = (kernel_ulong_t)&fec_imx25_info, 188 }, { 189 .name = "imx27-fec", 190 .driver_data = (kernel_ulong_t)&fec_imx27_info, 191 }, { 192 .name = "imx28-fec", 193 .driver_data = (kernel_ulong_t)&fec_imx28_info, 194 }, { 195 .name = "imx6q-fec", 196 .driver_data = (kernel_ulong_t)&fec_imx6q_info, 197 }, { 198 .name = "mvf600-fec", 199 .driver_data = (kernel_ulong_t)&fec_mvf600_info, 200 }, { 201 .name = "imx6sx-fec", 202 .driver_data = (kernel_ulong_t)&fec_imx6x_info, 203 }, { 204 .name = "imx6ul-fec", 205 .driver_data = (kernel_ulong_t)&fec_imx6ul_info, 206 }, { 207 .name = "imx8mq-fec", 208 .driver_data = (kernel_ulong_t)&fec_imx8mq_info, 209 }, { 210 .name = "imx8qm-fec", 211 .driver_data = (kernel_ulong_t)&fec_imx8qm_info, 212 }, { 213 .name = "s32v234-fec", 214 .driver_data = (kernel_ulong_t)&fec_s32v234_info, 215 }, { 216 /* sentinel */ 217 } 218 }; 219 MODULE_DEVICE_TABLE(platform, fec_devtype); 220 221 enum imx_fec_type { 222 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 223 IMX27_FEC, /* runs on i.mx27/35/51 */ 224 IMX28_FEC, 225 IMX6Q_FEC, 226 MVF600_FEC, 227 IMX6SX_FEC, 228 IMX6UL_FEC, 229 IMX8MQ_FEC, 230 IMX8QM_FEC, 231 S32V234_FEC, 232 }; 233 234 static const struct of_device_id fec_dt_ids[] = { 235 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 236 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 237 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 238 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 239 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 240 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 241 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 242 { .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], }, 243 { .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], }, 244 { .compatible = "fsl,s32v234-fec", .data = &fec_devtype[S32V234_FEC], }, 245 { /* sentinel */ } 246 }; 247 MODULE_DEVICE_TABLE(of, fec_dt_ids); 248 249 static unsigned char macaddr[ETH_ALEN]; 250 module_param_array(macaddr, byte, NULL, 0); 251 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 252 253 #if defined(CONFIG_M5272) 254 /* 255 * Some hardware gets it MAC address out of local flash memory. 256 * if this is non-zero then assume it is the address to get MAC from. 257 */ 258 #if defined(CONFIG_NETtel) 259 #define FEC_FLASHMAC 0xf0006006 260 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 261 #define FEC_FLASHMAC 0xf0006000 262 #elif defined(CONFIG_CANCam) 263 #define FEC_FLASHMAC 0xf0020000 264 #elif defined (CONFIG_M5272C3) 265 #define FEC_FLASHMAC (0xffe04000 + 4) 266 #elif defined(CONFIG_MOD5272) 267 #define FEC_FLASHMAC 0xffc0406b 268 #else 269 #define FEC_FLASHMAC 0 270 #endif 271 #endif /* CONFIG_M5272 */ 272 273 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 274 * 275 * 2048 byte skbufs are allocated. However, alignment requirements 276 * varies between FEC variants. Worst case is 64, so round down by 64. 277 */ 278 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 279 #define PKT_MINBUF_SIZE 64 280 281 /* FEC receive acceleration */ 282 #define FEC_RACC_IPDIS (1 << 1) 283 #define FEC_RACC_PRODIS (1 << 2) 284 #define FEC_RACC_SHIFT16 BIT(7) 285 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 286 287 /* MIB Control Register */ 288 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 289 290 /* 291 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 292 * size bits. Other FEC hardware does not, so we need to take that into 293 * account when setting it. 294 */ 295 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 296 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 297 defined(CONFIG_ARM64) 298 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 299 #else 300 #define OPT_FRAME_SIZE 0 301 #endif 302 303 /* FEC MII MMFR bits definition */ 304 #define FEC_MMFR_ST (1 << 30) 305 #define FEC_MMFR_ST_C45 (0) 306 #define FEC_MMFR_OP_READ (2 << 28) 307 #define FEC_MMFR_OP_READ_C45 (3 << 28) 308 #define FEC_MMFR_OP_WRITE (1 << 28) 309 #define FEC_MMFR_OP_ADDR_WRITE (0) 310 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 311 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 312 #define FEC_MMFR_TA (2 << 16) 313 #define FEC_MMFR_DATA(v) (v & 0xffff) 314 /* FEC ECR bits definition */ 315 #define FEC_ECR_MAGICEN (1 << 2) 316 #define FEC_ECR_SLEEP (1 << 3) 317 318 #define FEC_MII_TIMEOUT 30000 /* us */ 319 320 /* Transmitter timeout */ 321 #define TX_TIMEOUT (2 * HZ) 322 323 #define FEC_PAUSE_FLAG_AUTONEG 0x1 324 #define FEC_PAUSE_FLAG_ENABLE 0x2 325 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 326 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 327 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 328 329 /* Max number of allowed TCP segments for software TSO */ 330 #define FEC_MAX_TSO_SEGS 100 331 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 332 333 #define IS_TSO_HEADER(txq, addr) \ 334 ((addr >= txq->tso_hdrs_dma) && \ 335 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 336 337 static int mii_cnt; 338 339 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 340 struct bufdesc_prop *bd) 341 { 342 return (bdp >= bd->last) ? bd->base 343 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 344 } 345 346 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 347 struct bufdesc_prop *bd) 348 { 349 return (bdp <= bd->base) ? bd->last 350 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 351 } 352 353 static int fec_enet_get_bd_index(struct bufdesc *bdp, 354 struct bufdesc_prop *bd) 355 { 356 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 357 } 358 359 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 360 { 361 int entries; 362 363 entries = (((const char *)txq->dirty_tx - 364 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 365 366 return entries >= 0 ? entries : entries + txq->bd.ring_size; 367 } 368 369 static void swap_buffer(void *bufaddr, int len) 370 { 371 int i; 372 unsigned int *buf = bufaddr; 373 374 for (i = 0; i < len; i += 4, buf++) 375 swab32s(buf); 376 } 377 378 static void fec_dump(struct net_device *ndev) 379 { 380 struct fec_enet_private *fep = netdev_priv(ndev); 381 struct bufdesc *bdp; 382 struct fec_enet_priv_tx_q *txq; 383 int index = 0; 384 385 netdev_info(ndev, "TX ring dump\n"); 386 pr_info("Nr SC addr len SKB\n"); 387 388 txq = fep->tx_queue[0]; 389 bdp = txq->bd.base; 390 391 do { 392 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 393 index, 394 bdp == txq->bd.cur ? 'S' : ' ', 395 bdp == txq->dirty_tx ? 'H' : ' ', 396 fec16_to_cpu(bdp->cbd_sc), 397 fec32_to_cpu(bdp->cbd_bufaddr), 398 fec16_to_cpu(bdp->cbd_datlen), 399 txq->tx_buf[index].skb); 400 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 401 index++; 402 } while (bdp != txq->bd.base); 403 } 404 405 static inline bool is_ipv4_pkt(struct sk_buff *skb) 406 { 407 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 408 } 409 410 static int 411 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 412 { 413 /* Only run for packets requiring a checksum. */ 414 if (skb->ip_summed != CHECKSUM_PARTIAL) 415 return 0; 416 417 if (unlikely(skb_cow_head(skb, 0))) 418 return -1; 419 420 if (is_ipv4_pkt(skb)) 421 ip_hdr(skb)->check = 0; 422 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 423 424 return 0; 425 } 426 427 static int 428 fec_enet_create_page_pool(struct fec_enet_private *fep, 429 struct fec_enet_priv_rx_q *rxq, int size) 430 { 431 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 432 struct page_pool_params pp_params = { 433 .order = 0, 434 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 435 .pool_size = size, 436 .nid = dev_to_node(&fep->pdev->dev), 437 .dev = &fep->pdev->dev, 438 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 439 .offset = FEC_ENET_XDP_HEADROOM, 440 .max_len = FEC_ENET_RX_FRSIZE, 441 }; 442 int err; 443 444 rxq->page_pool = page_pool_create(&pp_params); 445 if (IS_ERR(rxq->page_pool)) { 446 err = PTR_ERR(rxq->page_pool); 447 rxq->page_pool = NULL; 448 return err; 449 } 450 451 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0); 452 if (err < 0) 453 goto err_free_pp; 454 455 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 456 rxq->page_pool); 457 if (err) 458 goto err_unregister_rxq; 459 460 return 0; 461 462 err_unregister_rxq: 463 xdp_rxq_info_unreg(&rxq->xdp_rxq); 464 err_free_pp: 465 page_pool_destroy(rxq->page_pool); 466 rxq->page_pool = NULL; 467 return err; 468 } 469 470 static struct bufdesc * 471 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 472 struct sk_buff *skb, 473 struct net_device *ndev) 474 { 475 struct fec_enet_private *fep = netdev_priv(ndev); 476 struct bufdesc *bdp = txq->bd.cur; 477 struct bufdesc_ex *ebdp; 478 int nr_frags = skb_shinfo(skb)->nr_frags; 479 int frag, frag_len; 480 unsigned short status; 481 unsigned int estatus = 0; 482 skb_frag_t *this_frag; 483 unsigned int index; 484 void *bufaddr; 485 dma_addr_t addr; 486 int i; 487 488 for (frag = 0; frag < nr_frags; frag++) { 489 this_frag = &skb_shinfo(skb)->frags[frag]; 490 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 491 ebdp = (struct bufdesc_ex *)bdp; 492 493 status = fec16_to_cpu(bdp->cbd_sc); 494 status &= ~BD_ENET_TX_STATS; 495 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 496 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 497 498 /* Handle the last BD specially */ 499 if (frag == nr_frags - 1) { 500 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 501 if (fep->bufdesc_ex) { 502 estatus |= BD_ENET_TX_INT; 503 if (unlikely(skb_shinfo(skb)->tx_flags & 504 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 505 estatus |= BD_ENET_TX_TS; 506 } 507 } 508 509 if (fep->bufdesc_ex) { 510 if (fep->quirks & FEC_QUIRK_HAS_AVB) 511 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 512 if (skb->ip_summed == CHECKSUM_PARTIAL) 513 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 514 515 ebdp->cbd_bdu = 0; 516 ebdp->cbd_esc = cpu_to_fec32(estatus); 517 } 518 519 bufaddr = skb_frag_address(this_frag); 520 521 index = fec_enet_get_bd_index(bdp, &txq->bd); 522 if (((unsigned long) bufaddr) & fep->tx_align || 523 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 524 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 525 bufaddr = txq->tx_bounce[index]; 526 527 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 528 swap_buffer(bufaddr, frag_len); 529 } 530 531 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 532 DMA_TO_DEVICE); 533 if (dma_mapping_error(&fep->pdev->dev, addr)) { 534 if (net_ratelimit()) 535 netdev_err(ndev, "Tx DMA memory map failed\n"); 536 goto dma_mapping_error; 537 } 538 539 bdp->cbd_bufaddr = cpu_to_fec32(addr); 540 bdp->cbd_datlen = cpu_to_fec16(frag_len); 541 /* Make sure the updates to rest of the descriptor are 542 * performed before transferring ownership. 543 */ 544 wmb(); 545 bdp->cbd_sc = cpu_to_fec16(status); 546 } 547 548 return bdp; 549 dma_mapping_error: 550 bdp = txq->bd.cur; 551 for (i = 0; i < frag; i++) { 552 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 553 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 554 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 555 } 556 return ERR_PTR(-ENOMEM); 557 } 558 559 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 560 struct sk_buff *skb, struct net_device *ndev) 561 { 562 struct fec_enet_private *fep = netdev_priv(ndev); 563 int nr_frags = skb_shinfo(skb)->nr_frags; 564 struct bufdesc *bdp, *last_bdp; 565 void *bufaddr; 566 dma_addr_t addr; 567 unsigned short status; 568 unsigned short buflen; 569 unsigned int estatus = 0; 570 unsigned int index; 571 int entries_free; 572 573 entries_free = fec_enet_get_free_txdesc_num(txq); 574 if (entries_free < MAX_SKB_FRAGS + 1) { 575 dev_kfree_skb_any(skb); 576 if (net_ratelimit()) 577 netdev_err(ndev, "NOT enough BD for SG!\n"); 578 return NETDEV_TX_OK; 579 } 580 581 /* Protocol checksum off-load for TCP and UDP. */ 582 if (fec_enet_clear_csum(skb, ndev)) { 583 dev_kfree_skb_any(skb); 584 return NETDEV_TX_OK; 585 } 586 587 /* Fill in a Tx ring entry */ 588 bdp = txq->bd.cur; 589 last_bdp = bdp; 590 status = fec16_to_cpu(bdp->cbd_sc); 591 status &= ~BD_ENET_TX_STATS; 592 593 /* Set buffer length and buffer pointer */ 594 bufaddr = skb->data; 595 buflen = skb_headlen(skb); 596 597 index = fec_enet_get_bd_index(bdp, &txq->bd); 598 if (((unsigned long) bufaddr) & fep->tx_align || 599 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 600 memcpy(txq->tx_bounce[index], skb->data, buflen); 601 bufaddr = txq->tx_bounce[index]; 602 603 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 604 swap_buffer(bufaddr, buflen); 605 } 606 607 /* Push the data cache so the CPM does not get stale memory data. */ 608 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 609 if (dma_mapping_error(&fep->pdev->dev, addr)) { 610 dev_kfree_skb_any(skb); 611 if (net_ratelimit()) 612 netdev_err(ndev, "Tx DMA memory map failed\n"); 613 return NETDEV_TX_OK; 614 } 615 616 if (nr_frags) { 617 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 618 if (IS_ERR(last_bdp)) { 619 dma_unmap_single(&fep->pdev->dev, addr, 620 buflen, DMA_TO_DEVICE); 621 dev_kfree_skb_any(skb); 622 return NETDEV_TX_OK; 623 } 624 } else { 625 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 626 if (fep->bufdesc_ex) { 627 estatus = BD_ENET_TX_INT; 628 if (unlikely(skb_shinfo(skb)->tx_flags & 629 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 630 estatus |= BD_ENET_TX_TS; 631 } 632 } 633 bdp->cbd_bufaddr = cpu_to_fec32(addr); 634 bdp->cbd_datlen = cpu_to_fec16(buflen); 635 636 if (fep->bufdesc_ex) { 637 638 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 639 640 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 641 fep->hwts_tx_en)) 642 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 643 644 if (fep->quirks & FEC_QUIRK_HAS_AVB) 645 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 646 647 if (skb->ip_summed == CHECKSUM_PARTIAL) 648 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 649 650 ebdp->cbd_bdu = 0; 651 ebdp->cbd_esc = cpu_to_fec32(estatus); 652 } 653 654 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 655 /* Save skb pointer */ 656 txq->tx_buf[index].skb = skb; 657 658 /* Make sure the updates to rest of the descriptor are performed before 659 * transferring ownership. 660 */ 661 wmb(); 662 663 /* Send it on its way. Tell FEC it's ready, interrupt when done, 664 * it's the last BD of the frame, and to put the CRC on the end. 665 */ 666 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 667 bdp->cbd_sc = cpu_to_fec16(status); 668 669 /* If this was the last BD in the ring, start at the beginning again. */ 670 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 671 672 skb_tx_timestamp(skb); 673 674 /* Make sure the update to bdp is performed before txq->bd.cur. */ 675 wmb(); 676 txq->bd.cur = bdp; 677 678 /* Trigger transmission start */ 679 writel(0, txq->bd.reg_desc_active); 680 681 return 0; 682 } 683 684 static int 685 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 686 struct net_device *ndev, 687 struct bufdesc *bdp, int index, char *data, 688 int size, bool last_tcp, bool is_last) 689 { 690 struct fec_enet_private *fep = netdev_priv(ndev); 691 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 692 unsigned short status; 693 unsigned int estatus = 0; 694 dma_addr_t addr; 695 696 status = fec16_to_cpu(bdp->cbd_sc); 697 status &= ~BD_ENET_TX_STATS; 698 699 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 700 701 if (((unsigned long) data) & fep->tx_align || 702 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 703 memcpy(txq->tx_bounce[index], data, size); 704 data = txq->tx_bounce[index]; 705 706 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 707 swap_buffer(data, size); 708 } 709 710 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 711 if (dma_mapping_error(&fep->pdev->dev, addr)) { 712 dev_kfree_skb_any(skb); 713 if (net_ratelimit()) 714 netdev_err(ndev, "Tx DMA memory map failed\n"); 715 return NETDEV_TX_OK; 716 } 717 718 bdp->cbd_datlen = cpu_to_fec16(size); 719 bdp->cbd_bufaddr = cpu_to_fec32(addr); 720 721 if (fep->bufdesc_ex) { 722 if (fep->quirks & FEC_QUIRK_HAS_AVB) 723 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 724 if (skb->ip_summed == CHECKSUM_PARTIAL) 725 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 726 ebdp->cbd_bdu = 0; 727 ebdp->cbd_esc = cpu_to_fec32(estatus); 728 } 729 730 /* Handle the last BD specially */ 731 if (last_tcp) 732 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 733 if (is_last) { 734 status |= BD_ENET_TX_INTR; 735 if (fep->bufdesc_ex) 736 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 737 } 738 739 bdp->cbd_sc = cpu_to_fec16(status); 740 741 return 0; 742 } 743 744 static int 745 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 746 struct sk_buff *skb, struct net_device *ndev, 747 struct bufdesc *bdp, int index) 748 { 749 struct fec_enet_private *fep = netdev_priv(ndev); 750 int hdr_len = skb_tcp_all_headers(skb); 751 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 752 void *bufaddr; 753 unsigned long dmabuf; 754 unsigned short status; 755 unsigned int estatus = 0; 756 757 status = fec16_to_cpu(bdp->cbd_sc); 758 status &= ~BD_ENET_TX_STATS; 759 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 760 761 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 762 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 763 if (((unsigned long)bufaddr) & fep->tx_align || 764 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 765 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 766 bufaddr = txq->tx_bounce[index]; 767 768 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 769 swap_buffer(bufaddr, hdr_len); 770 771 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 772 hdr_len, DMA_TO_DEVICE); 773 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 774 dev_kfree_skb_any(skb); 775 if (net_ratelimit()) 776 netdev_err(ndev, "Tx DMA memory map failed\n"); 777 return NETDEV_TX_OK; 778 } 779 } 780 781 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 782 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 783 784 if (fep->bufdesc_ex) { 785 if (fep->quirks & FEC_QUIRK_HAS_AVB) 786 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 787 if (skb->ip_summed == CHECKSUM_PARTIAL) 788 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 789 ebdp->cbd_bdu = 0; 790 ebdp->cbd_esc = cpu_to_fec32(estatus); 791 } 792 793 bdp->cbd_sc = cpu_to_fec16(status); 794 795 return 0; 796 } 797 798 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 799 struct sk_buff *skb, 800 struct net_device *ndev) 801 { 802 struct fec_enet_private *fep = netdev_priv(ndev); 803 int hdr_len, total_len, data_left; 804 struct bufdesc *bdp = txq->bd.cur; 805 struct tso_t tso; 806 unsigned int index = 0; 807 int ret; 808 809 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 810 dev_kfree_skb_any(skb); 811 if (net_ratelimit()) 812 netdev_err(ndev, "NOT enough BD for TSO!\n"); 813 return NETDEV_TX_OK; 814 } 815 816 /* Protocol checksum off-load for TCP and UDP. */ 817 if (fec_enet_clear_csum(skb, ndev)) { 818 dev_kfree_skb_any(skb); 819 return NETDEV_TX_OK; 820 } 821 822 /* Initialize the TSO handler, and prepare the first payload */ 823 hdr_len = tso_start(skb, &tso); 824 825 total_len = skb->len - hdr_len; 826 while (total_len > 0) { 827 char *hdr; 828 829 index = fec_enet_get_bd_index(bdp, &txq->bd); 830 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 831 total_len -= data_left; 832 833 /* prepare packet headers: MAC + IP + TCP */ 834 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 835 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 836 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 837 if (ret) 838 goto err_release; 839 840 while (data_left > 0) { 841 int size; 842 843 size = min_t(int, tso.size, data_left); 844 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 845 index = fec_enet_get_bd_index(bdp, &txq->bd); 846 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 847 bdp, index, 848 tso.data, size, 849 size == data_left, 850 total_len == 0); 851 if (ret) 852 goto err_release; 853 854 data_left -= size; 855 tso_build_data(skb, &tso, size); 856 } 857 858 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 859 } 860 861 /* Save skb pointer */ 862 txq->tx_buf[index].skb = skb; 863 864 skb_tx_timestamp(skb); 865 txq->bd.cur = bdp; 866 867 /* Trigger transmission start */ 868 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 869 !readl(txq->bd.reg_desc_active) || 870 !readl(txq->bd.reg_desc_active) || 871 !readl(txq->bd.reg_desc_active) || 872 !readl(txq->bd.reg_desc_active)) 873 writel(0, txq->bd.reg_desc_active); 874 875 return 0; 876 877 err_release: 878 /* TODO: Release all used data descriptors for TSO */ 879 return ret; 880 } 881 882 static netdev_tx_t 883 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 884 { 885 struct fec_enet_private *fep = netdev_priv(ndev); 886 int entries_free; 887 unsigned short queue; 888 struct fec_enet_priv_tx_q *txq; 889 struct netdev_queue *nq; 890 int ret; 891 892 queue = skb_get_queue_mapping(skb); 893 txq = fep->tx_queue[queue]; 894 nq = netdev_get_tx_queue(ndev, queue); 895 896 if (skb_is_gso(skb)) 897 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 898 else 899 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 900 if (ret) 901 return ret; 902 903 entries_free = fec_enet_get_free_txdesc_num(txq); 904 if (entries_free <= txq->tx_stop_threshold) 905 netif_tx_stop_queue(nq); 906 907 return NETDEV_TX_OK; 908 } 909 910 /* Init RX & TX buffer descriptors 911 */ 912 static void fec_enet_bd_init(struct net_device *dev) 913 { 914 struct fec_enet_private *fep = netdev_priv(dev); 915 struct fec_enet_priv_tx_q *txq; 916 struct fec_enet_priv_rx_q *rxq; 917 struct bufdesc *bdp; 918 unsigned int i; 919 unsigned int q; 920 921 for (q = 0; q < fep->num_rx_queues; q++) { 922 /* Initialize the receive buffer descriptors. */ 923 rxq = fep->rx_queue[q]; 924 bdp = rxq->bd.base; 925 926 for (i = 0; i < rxq->bd.ring_size; i++) { 927 928 /* Initialize the BD for every fragment in the page. */ 929 if (bdp->cbd_bufaddr) 930 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 931 else 932 bdp->cbd_sc = cpu_to_fec16(0); 933 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 934 } 935 936 /* Set the last buffer to wrap */ 937 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 938 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 939 940 rxq->bd.cur = rxq->bd.base; 941 } 942 943 for (q = 0; q < fep->num_tx_queues; q++) { 944 /* ...and the same for transmit */ 945 txq = fep->tx_queue[q]; 946 bdp = txq->bd.base; 947 txq->bd.cur = bdp; 948 949 for (i = 0; i < txq->bd.ring_size; i++) { 950 /* Initialize the BD for every fragment in the page. */ 951 bdp->cbd_sc = cpu_to_fec16(0); 952 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 953 if (bdp->cbd_bufaddr && 954 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 955 dma_unmap_single(&fep->pdev->dev, 956 fec32_to_cpu(bdp->cbd_bufaddr), 957 fec16_to_cpu(bdp->cbd_datlen), 958 DMA_TO_DEVICE); 959 if (txq->tx_buf[i].skb) { 960 dev_kfree_skb_any(txq->tx_buf[i].skb); 961 txq->tx_buf[i].skb = NULL; 962 } 963 } else { 964 if (bdp->cbd_bufaddr) 965 dma_unmap_single(&fep->pdev->dev, 966 fec32_to_cpu(bdp->cbd_bufaddr), 967 fec16_to_cpu(bdp->cbd_datlen), 968 DMA_TO_DEVICE); 969 970 if (txq->tx_buf[i].xdp) { 971 xdp_return_frame(txq->tx_buf[i].xdp); 972 txq->tx_buf[i].xdp = NULL; 973 } 974 975 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 976 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 977 } 978 979 bdp->cbd_bufaddr = cpu_to_fec32(0); 980 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 981 } 982 983 /* Set the last buffer to wrap */ 984 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 985 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 986 txq->dirty_tx = bdp; 987 } 988 } 989 990 static void fec_enet_active_rxring(struct net_device *ndev) 991 { 992 struct fec_enet_private *fep = netdev_priv(ndev); 993 int i; 994 995 for (i = 0; i < fep->num_rx_queues; i++) 996 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 997 } 998 999 static void fec_enet_enable_ring(struct net_device *ndev) 1000 { 1001 struct fec_enet_private *fep = netdev_priv(ndev); 1002 struct fec_enet_priv_tx_q *txq; 1003 struct fec_enet_priv_rx_q *rxq; 1004 int i; 1005 1006 for (i = 0; i < fep->num_rx_queues; i++) { 1007 rxq = fep->rx_queue[i]; 1008 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 1009 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 1010 1011 /* enable DMA1/2 */ 1012 if (i) 1013 writel(RCMR_MATCHEN | RCMR_CMP(i), 1014 fep->hwp + FEC_RCMR(i)); 1015 } 1016 1017 for (i = 0; i < fep->num_tx_queues; i++) { 1018 txq = fep->tx_queue[i]; 1019 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 1020 1021 /* enable DMA1/2 */ 1022 if (i) 1023 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 1024 fep->hwp + FEC_DMA_CFG(i)); 1025 } 1026 } 1027 1028 /* 1029 * This function is called to start or restart the FEC during a link 1030 * change, transmit timeout, or to reconfigure the FEC. The network 1031 * packet processing for this device must be stopped before this call. 1032 */ 1033 static void 1034 fec_restart(struct net_device *ndev) 1035 { 1036 struct fec_enet_private *fep = netdev_priv(ndev); 1037 u32 temp_mac[2]; 1038 u32 rcntl = OPT_FRAME_SIZE | 0x04; 1039 u32 ecntl = 0x2; /* ETHEREN */ 1040 1041 /* Whack a reset. We should wait for this. 1042 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1043 * instead of reset MAC itself. 1044 */ 1045 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 1046 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 1047 writel(0, fep->hwp + FEC_ECNTRL); 1048 } else { 1049 writel(1, fep->hwp + FEC_ECNTRL); 1050 udelay(10); 1051 } 1052 1053 /* 1054 * enet-mac reset will reset mac address registers too, 1055 * so need to reconfigure it. 1056 */ 1057 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 1058 writel((__force u32)cpu_to_be32(temp_mac[0]), 1059 fep->hwp + FEC_ADDR_LOW); 1060 writel((__force u32)cpu_to_be32(temp_mac[1]), 1061 fep->hwp + FEC_ADDR_HIGH); 1062 1063 /* Clear any outstanding interrupt, except MDIO. */ 1064 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1065 1066 fec_enet_bd_init(ndev); 1067 1068 fec_enet_enable_ring(ndev); 1069 1070 /* Enable MII mode */ 1071 if (fep->full_duplex == DUPLEX_FULL) { 1072 /* FD enable */ 1073 writel(0x04, fep->hwp + FEC_X_CNTRL); 1074 } else { 1075 /* No Rcv on Xmit */ 1076 rcntl |= 0x02; 1077 writel(0x0, fep->hwp + FEC_X_CNTRL); 1078 } 1079 1080 /* Set MII speed */ 1081 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1082 1083 #if !defined(CONFIG_M5272) 1084 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1085 u32 val = readl(fep->hwp + FEC_RACC); 1086 1087 /* align IP header */ 1088 val |= FEC_RACC_SHIFT16; 1089 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1090 /* set RX checksum */ 1091 val |= FEC_RACC_OPTIONS; 1092 else 1093 val &= ~FEC_RACC_OPTIONS; 1094 writel(val, fep->hwp + FEC_RACC); 1095 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1096 } 1097 #endif 1098 1099 /* 1100 * The phy interface and speed need to get configured 1101 * differently on enet-mac. 1102 */ 1103 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1104 /* Enable flow control and length check */ 1105 rcntl |= 0x40000000 | 0x00000020; 1106 1107 /* RGMII, RMII or MII */ 1108 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1109 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1110 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1111 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1112 rcntl |= (1 << 6); 1113 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1114 rcntl |= (1 << 8); 1115 else 1116 rcntl &= ~(1 << 8); 1117 1118 /* 1G, 100M or 10M */ 1119 if (ndev->phydev) { 1120 if (ndev->phydev->speed == SPEED_1000) 1121 ecntl |= (1 << 5); 1122 else if (ndev->phydev->speed == SPEED_100) 1123 rcntl &= ~(1 << 9); 1124 else 1125 rcntl |= (1 << 9); 1126 } 1127 } else { 1128 #ifdef FEC_MIIGSK_ENR 1129 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1130 u32 cfgr; 1131 /* disable the gasket and wait */ 1132 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1133 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1134 udelay(1); 1135 1136 /* 1137 * configure the gasket: 1138 * RMII, 50 MHz, no loopback, no echo 1139 * MII, 25 MHz, no loopback, no echo 1140 */ 1141 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1142 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1143 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1144 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1145 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1146 1147 /* re-enable the gasket */ 1148 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1149 } 1150 #endif 1151 } 1152 1153 #if !defined(CONFIG_M5272) 1154 /* enable pause frame*/ 1155 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1156 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1157 ndev->phydev && ndev->phydev->pause)) { 1158 rcntl |= FEC_ENET_FCE; 1159 1160 /* set FIFO threshold parameter to reduce overrun */ 1161 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1162 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1163 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1164 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1165 1166 /* OPD */ 1167 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1168 } else { 1169 rcntl &= ~FEC_ENET_FCE; 1170 } 1171 #endif /* !defined(CONFIG_M5272) */ 1172 1173 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1174 1175 /* Setup multicast filter. */ 1176 set_multicast_list(ndev); 1177 #ifndef CONFIG_M5272 1178 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1179 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1180 #endif 1181 1182 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1183 /* enable ENET endian swap */ 1184 ecntl |= (1 << 8); 1185 /* enable ENET store and forward mode */ 1186 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1187 } 1188 1189 if (fep->bufdesc_ex) 1190 ecntl |= (1 << 4); 1191 1192 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1193 fep->rgmii_txc_dly) 1194 ecntl |= FEC_ENET_TXC_DLY; 1195 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1196 fep->rgmii_rxc_dly) 1197 ecntl |= FEC_ENET_RXC_DLY; 1198 1199 #ifndef CONFIG_M5272 1200 /* Enable the MIB statistic event counters */ 1201 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1202 #endif 1203 1204 /* And last, enable the transmit and receive processing */ 1205 writel(ecntl, fep->hwp + FEC_ECNTRL); 1206 fec_enet_active_rxring(ndev); 1207 1208 if (fep->bufdesc_ex) 1209 fec_ptp_start_cyclecounter(ndev); 1210 1211 /* Enable interrupts we wish to service */ 1212 if (fep->link) 1213 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1214 else 1215 writel(0, fep->hwp + FEC_IMASK); 1216 1217 /* Init the interrupt coalescing */ 1218 if (fep->quirks & FEC_QUIRK_HAS_COALESCE) 1219 fec_enet_itr_coal_set(ndev); 1220 } 1221 1222 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep) 1223 { 1224 if (!(of_machine_is_compatible("fsl,imx8qm") || 1225 of_machine_is_compatible("fsl,imx8qxp") || 1226 of_machine_is_compatible("fsl,imx8dxl"))) 1227 return 0; 1228 1229 return imx_scu_get_handle(&fep->ipc_handle); 1230 } 1231 1232 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled) 1233 { 1234 struct device_node *np = fep->pdev->dev.of_node; 1235 u32 rsrc_id, val; 1236 int idx; 1237 1238 if (!np || !fep->ipc_handle) 1239 return; 1240 1241 idx = of_alias_get_id(np, "ethernet"); 1242 if (idx < 0) 1243 idx = 0; 1244 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0; 1245 1246 val = enabled ? 1 : 0; 1247 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val); 1248 } 1249 1250 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1251 { 1252 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1253 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1254 1255 if (stop_gpr->gpr) { 1256 if (enabled) 1257 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1258 BIT(stop_gpr->bit), 1259 BIT(stop_gpr->bit)); 1260 else 1261 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1262 BIT(stop_gpr->bit), 0); 1263 } else if (pdata && pdata->sleep_mode_enable) { 1264 pdata->sleep_mode_enable(enabled); 1265 } else { 1266 fec_enet_ipg_stop_set(fep, enabled); 1267 } 1268 } 1269 1270 static void fec_irqs_disable(struct net_device *ndev) 1271 { 1272 struct fec_enet_private *fep = netdev_priv(ndev); 1273 1274 writel(0, fep->hwp + FEC_IMASK); 1275 } 1276 1277 static void fec_irqs_disable_except_wakeup(struct net_device *ndev) 1278 { 1279 struct fec_enet_private *fep = netdev_priv(ndev); 1280 1281 writel(0, fep->hwp + FEC_IMASK); 1282 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1283 } 1284 1285 static void 1286 fec_stop(struct net_device *ndev) 1287 { 1288 struct fec_enet_private *fep = netdev_priv(ndev); 1289 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1290 u32 val; 1291 1292 /* We cannot expect a graceful transmit stop without link !!! */ 1293 if (fep->link) { 1294 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1295 udelay(10); 1296 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1297 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1298 } 1299 1300 /* Whack a reset. We should wait for this. 1301 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1302 * instead of reset MAC itself. 1303 */ 1304 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1305 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 1306 writel(0, fep->hwp + FEC_ECNTRL); 1307 } else { 1308 writel(1, fep->hwp + FEC_ECNTRL); 1309 udelay(10); 1310 } 1311 } else { 1312 val = readl(fep->hwp + FEC_ECNTRL); 1313 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1314 writel(val, fep->hwp + FEC_ECNTRL); 1315 } 1316 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1317 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1318 1319 /* We have to keep ENET enabled to have MII interrupt stay working */ 1320 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1321 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1322 writel(2, fep->hwp + FEC_ECNTRL); 1323 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1324 } 1325 } 1326 1327 1328 static void 1329 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1330 { 1331 struct fec_enet_private *fep = netdev_priv(ndev); 1332 1333 fec_dump(ndev); 1334 1335 ndev->stats.tx_errors++; 1336 1337 schedule_work(&fep->tx_timeout_work); 1338 } 1339 1340 static void fec_enet_timeout_work(struct work_struct *work) 1341 { 1342 struct fec_enet_private *fep = 1343 container_of(work, struct fec_enet_private, tx_timeout_work); 1344 struct net_device *ndev = fep->netdev; 1345 1346 rtnl_lock(); 1347 if (netif_device_present(ndev) || netif_running(ndev)) { 1348 napi_disable(&fep->napi); 1349 netif_tx_lock_bh(ndev); 1350 fec_restart(ndev); 1351 netif_tx_wake_all_queues(ndev); 1352 netif_tx_unlock_bh(ndev); 1353 napi_enable(&fep->napi); 1354 } 1355 rtnl_unlock(); 1356 } 1357 1358 static void 1359 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1360 struct skb_shared_hwtstamps *hwtstamps) 1361 { 1362 unsigned long flags; 1363 u64 ns; 1364 1365 spin_lock_irqsave(&fep->tmreg_lock, flags); 1366 ns = timecounter_cyc2time(&fep->tc, ts); 1367 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1368 1369 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1370 hwtstamps->hwtstamp = ns_to_ktime(ns); 1371 } 1372 1373 static void 1374 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget) 1375 { 1376 struct fec_enet_private *fep; 1377 struct xdp_frame *xdpf; 1378 struct bufdesc *bdp; 1379 unsigned short status; 1380 struct sk_buff *skb; 1381 struct fec_enet_priv_tx_q *txq; 1382 struct netdev_queue *nq; 1383 int index = 0; 1384 int entries_free; 1385 1386 fep = netdev_priv(ndev); 1387 1388 txq = fep->tx_queue[queue_id]; 1389 /* get next bdp of dirty_tx */ 1390 nq = netdev_get_tx_queue(ndev, queue_id); 1391 bdp = txq->dirty_tx; 1392 1393 /* get next bdp of dirty_tx */ 1394 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1395 1396 while (bdp != READ_ONCE(txq->bd.cur)) { 1397 /* Order the load of bd.cur and cbd_sc */ 1398 rmb(); 1399 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1400 if (status & BD_ENET_TX_READY) 1401 break; 1402 1403 index = fec_enet_get_bd_index(bdp, &txq->bd); 1404 1405 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1406 skb = txq->tx_buf[index].skb; 1407 txq->tx_buf[index].skb = NULL; 1408 if (bdp->cbd_bufaddr && 1409 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1410 dma_unmap_single(&fep->pdev->dev, 1411 fec32_to_cpu(bdp->cbd_bufaddr), 1412 fec16_to_cpu(bdp->cbd_datlen), 1413 DMA_TO_DEVICE); 1414 bdp->cbd_bufaddr = cpu_to_fec32(0); 1415 if (!skb) 1416 goto tx_buf_done; 1417 } else { 1418 /* Tx processing cannot call any XDP (or page pool) APIs if 1419 * the "budget" is 0. Because NAPI is called with budget of 1420 * 0 (such as netpoll) indicates we may be in an IRQ context, 1421 * however, we can't use the page pool from IRQ context. 1422 */ 1423 if (unlikely(!budget)) 1424 break; 1425 1426 xdpf = txq->tx_buf[index].xdp; 1427 if (bdp->cbd_bufaddr) 1428 dma_unmap_single(&fep->pdev->dev, 1429 fec32_to_cpu(bdp->cbd_bufaddr), 1430 fec16_to_cpu(bdp->cbd_datlen), 1431 DMA_TO_DEVICE); 1432 bdp->cbd_bufaddr = cpu_to_fec32(0); 1433 if (!xdpf) { 1434 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1435 goto tx_buf_done; 1436 } 1437 } 1438 1439 /* Check for errors. */ 1440 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1441 BD_ENET_TX_RL | BD_ENET_TX_UN | 1442 BD_ENET_TX_CSL)) { 1443 ndev->stats.tx_errors++; 1444 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1445 ndev->stats.tx_heartbeat_errors++; 1446 if (status & BD_ENET_TX_LC) /* Late collision */ 1447 ndev->stats.tx_window_errors++; 1448 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1449 ndev->stats.tx_aborted_errors++; 1450 if (status & BD_ENET_TX_UN) /* Underrun */ 1451 ndev->stats.tx_fifo_errors++; 1452 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1453 ndev->stats.tx_carrier_errors++; 1454 } else { 1455 ndev->stats.tx_packets++; 1456 1457 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) 1458 ndev->stats.tx_bytes += skb->len; 1459 else 1460 ndev->stats.tx_bytes += xdpf->len; 1461 } 1462 1463 /* Deferred means some collisions occurred during transmit, 1464 * but we eventually sent the packet OK. 1465 */ 1466 if (status & BD_ENET_TX_DEF) 1467 ndev->stats.collisions++; 1468 1469 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1470 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1471 * are to time stamp the packet, so we still need to check time 1472 * stamping enabled flag. 1473 */ 1474 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1475 fep->hwts_tx_en) && fep->bufdesc_ex) { 1476 struct skb_shared_hwtstamps shhwtstamps; 1477 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1478 1479 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1480 skb_tstamp_tx(skb, &shhwtstamps); 1481 } 1482 1483 /* Free the sk buffer associated with this last transmit */ 1484 dev_kfree_skb_any(skb); 1485 } else { 1486 xdp_return_frame(xdpf); 1487 1488 txq->tx_buf[index].xdp = NULL; 1489 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1490 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1491 } 1492 1493 tx_buf_done: 1494 /* Make sure the update to bdp and tx_buf are performed 1495 * before dirty_tx 1496 */ 1497 wmb(); 1498 txq->dirty_tx = bdp; 1499 1500 /* Update pointer to next buffer descriptor to be transmitted */ 1501 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1502 1503 /* Since we have freed up a buffer, the ring is no longer full 1504 */ 1505 if (netif_tx_queue_stopped(nq)) { 1506 entries_free = fec_enet_get_free_txdesc_num(txq); 1507 if (entries_free >= txq->tx_wake_threshold) 1508 netif_tx_wake_queue(nq); 1509 } 1510 } 1511 1512 /* ERR006358: Keep the transmitter going */ 1513 if (bdp != txq->bd.cur && 1514 readl(txq->bd.reg_desc_active) == 0) 1515 writel(0, txq->bd.reg_desc_active); 1516 } 1517 1518 static void fec_enet_tx(struct net_device *ndev, int budget) 1519 { 1520 struct fec_enet_private *fep = netdev_priv(ndev); 1521 int i; 1522 1523 /* Make sure that AVB queues are processed first. */ 1524 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1525 fec_enet_tx_queue(ndev, i, budget); 1526 } 1527 1528 static void fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq, 1529 struct bufdesc *bdp, int index) 1530 { 1531 struct page *new_page; 1532 dma_addr_t phys_addr; 1533 1534 new_page = page_pool_dev_alloc_pages(rxq->page_pool); 1535 WARN_ON(!new_page); 1536 rxq->rx_skb_info[index].page = new_page; 1537 1538 rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM; 1539 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM; 1540 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 1541 } 1542 1543 static u32 1544 fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog, 1545 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int index) 1546 { 1547 unsigned int sync, len = xdp->data_end - xdp->data; 1548 u32 ret = FEC_ENET_XDP_PASS; 1549 struct page *page; 1550 int err; 1551 u32 act; 1552 1553 act = bpf_prog_run_xdp(prog, xdp); 1554 1555 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */ 1556 sync = xdp->data_end - xdp->data_hard_start - FEC_ENET_XDP_HEADROOM; 1557 sync = max(sync, len); 1558 1559 switch (act) { 1560 case XDP_PASS: 1561 rxq->stats[RX_XDP_PASS]++; 1562 ret = FEC_ENET_XDP_PASS; 1563 break; 1564 1565 case XDP_REDIRECT: 1566 rxq->stats[RX_XDP_REDIRECT]++; 1567 err = xdp_do_redirect(fep->netdev, xdp, prog); 1568 if (!err) { 1569 ret = FEC_ENET_XDP_REDIR; 1570 } else { 1571 ret = FEC_ENET_XDP_CONSUMED; 1572 page = virt_to_head_page(xdp->data); 1573 page_pool_put_page(rxq->page_pool, page, sync, true); 1574 } 1575 break; 1576 1577 default: 1578 bpf_warn_invalid_xdp_action(fep->netdev, prog, act); 1579 fallthrough; 1580 1581 case XDP_TX: 1582 bpf_warn_invalid_xdp_action(fep->netdev, prog, act); 1583 fallthrough; 1584 1585 case XDP_ABORTED: 1586 fallthrough; /* handle aborts by dropping packet */ 1587 1588 case XDP_DROP: 1589 rxq->stats[RX_XDP_DROP]++; 1590 ret = FEC_ENET_XDP_CONSUMED; 1591 page = virt_to_head_page(xdp->data); 1592 page_pool_put_page(rxq->page_pool, page, sync, true); 1593 break; 1594 } 1595 1596 return ret; 1597 } 1598 1599 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1600 * When we update through the ring, if the next incoming buffer has 1601 * not been given to the system, we just set the empty indicator, 1602 * effectively tossing the packet. 1603 */ 1604 static int 1605 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1606 { 1607 struct fec_enet_private *fep = netdev_priv(ndev); 1608 struct fec_enet_priv_rx_q *rxq; 1609 struct bufdesc *bdp; 1610 unsigned short status; 1611 struct sk_buff *skb; 1612 ushort pkt_len; 1613 __u8 *data; 1614 int pkt_received = 0; 1615 struct bufdesc_ex *ebdp = NULL; 1616 bool vlan_packet_rcvd = false; 1617 u16 vlan_tag; 1618 int index = 0; 1619 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1620 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 1621 u32 ret, xdp_result = FEC_ENET_XDP_PASS; 1622 u32 data_start = FEC_ENET_XDP_HEADROOM; 1623 struct xdp_buff xdp; 1624 struct page *page; 1625 u32 sub_len = 4; 1626 1627 #if !defined(CONFIG_M5272) 1628 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of 1629 * FEC_RACC_SHIFT16 is set by default in the probe function. 1630 */ 1631 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1632 data_start += 2; 1633 sub_len += 2; 1634 } 1635 #endif 1636 1637 #ifdef CONFIG_M532x 1638 flush_cache_all(); 1639 #endif 1640 rxq = fep->rx_queue[queue_id]; 1641 1642 /* First, grab all of the stats for the incoming packet. 1643 * These get messed up if we get called due to a busy condition. 1644 */ 1645 bdp = rxq->bd.cur; 1646 xdp_init_buff(&xdp, PAGE_SIZE, &rxq->xdp_rxq); 1647 1648 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1649 1650 if (pkt_received >= budget) 1651 break; 1652 pkt_received++; 1653 1654 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); 1655 1656 /* Check for errors. */ 1657 status ^= BD_ENET_RX_LAST; 1658 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1659 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1660 BD_ENET_RX_CL)) { 1661 ndev->stats.rx_errors++; 1662 if (status & BD_ENET_RX_OV) { 1663 /* FIFO overrun */ 1664 ndev->stats.rx_fifo_errors++; 1665 goto rx_processing_done; 1666 } 1667 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1668 | BD_ENET_RX_LAST)) { 1669 /* Frame too long or too short. */ 1670 ndev->stats.rx_length_errors++; 1671 if (status & BD_ENET_RX_LAST) 1672 netdev_err(ndev, "rcv is not +last\n"); 1673 } 1674 if (status & BD_ENET_RX_CR) /* CRC Error */ 1675 ndev->stats.rx_crc_errors++; 1676 /* Report late collisions as a frame error. */ 1677 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1678 ndev->stats.rx_frame_errors++; 1679 goto rx_processing_done; 1680 } 1681 1682 /* Process the incoming frame. */ 1683 ndev->stats.rx_packets++; 1684 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1685 ndev->stats.rx_bytes += pkt_len; 1686 1687 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1688 page = rxq->rx_skb_info[index].page; 1689 dma_sync_single_for_cpu(&fep->pdev->dev, 1690 fec32_to_cpu(bdp->cbd_bufaddr), 1691 pkt_len, 1692 DMA_FROM_DEVICE); 1693 prefetch(page_address(page)); 1694 fec_enet_update_cbd(rxq, bdp, index); 1695 1696 if (xdp_prog) { 1697 xdp_buff_clear_frags_flag(&xdp); 1698 /* subtract 16bit shift and FCS */ 1699 xdp_prepare_buff(&xdp, page_address(page), 1700 data_start, pkt_len - sub_len, false); 1701 ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, index); 1702 xdp_result |= ret; 1703 if (ret != FEC_ENET_XDP_PASS) 1704 goto rx_processing_done; 1705 } 1706 1707 /* The packet length includes FCS, but we don't want to 1708 * include that when passing upstream as it messes up 1709 * bridging applications. 1710 */ 1711 skb = build_skb(page_address(page), PAGE_SIZE); 1712 if (unlikely(!skb)) { 1713 page_pool_recycle_direct(rxq->page_pool, page); 1714 ndev->stats.rx_dropped++; 1715 1716 netdev_err_once(ndev, "build_skb failed!\n"); 1717 goto rx_processing_done; 1718 } 1719 1720 skb_reserve(skb, data_start); 1721 skb_put(skb, pkt_len - sub_len); 1722 skb_mark_for_recycle(skb); 1723 1724 if (unlikely(need_swap)) { 1725 data = page_address(page) + FEC_ENET_XDP_HEADROOM; 1726 swap_buffer(data, pkt_len); 1727 } 1728 data = skb->data; 1729 1730 /* Extract the enhanced buffer descriptor */ 1731 ebdp = NULL; 1732 if (fep->bufdesc_ex) 1733 ebdp = (struct bufdesc_ex *)bdp; 1734 1735 /* If this is a VLAN packet remove the VLAN Tag */ 1736 vlan_packet_rcvd = false; 1737 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1738 fep->bufdesc_ex && 1739 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1740 /* Push and remove the vlan tag */ 1741 struct vlan_hdr *vlan_header = 1742 (struct vlan_hdr *) (data + ETH_HLEN); 1743 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1744 1745 vlan_packet_rcvd = true; 1746 1747 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1748 skb_pull(skb, VLAN_HLEN); 1749 } 1750 1751 skb->protocol = eth_type_trans(skb, ndev); 1752 1753 /* Get receive timestamp from the skb */ 1754 if (fep->hwts_rx_en && fep->bufdesc_ex) 1755 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1756 skb_hwtstamps(skb)); 1757 1758 if (fep->bufdesc_ex && 1759 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1760 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1761 /* don't check it */ 1762 skb->ip_summed = CHECKSUM_UNNECESSARY; 1763 } else { 1764 skb_checksum_none_assert(skb); 1765 } 1766 } 1767 1768 /* Handle received VLAN packets */ 1769 if (vlan_packet_rcvd) 1770 __vlan_hwaccel_put_tag(skb, 1771 htons(ETH_P_8021Q), 1772 vlan_tag); 1773 1774 skb_record_rx_queue(skb, queue_id); 1775 napi_gro_receive(&fep->napi, skb); 1776 1777 rx_processing_done: 1778 /* Clear the status flags for this buffer */ 1779 status &= ~BD_ENET_RX_STATS; 1780 1781 /* Mark the buffer empty */ 1782 status |= BD_ENET_RX_EMPTY; 1783 1784 if (fep->bufdesc_ex) { 1785 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1786 1787 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1788 ebdp->cbd_prot = 0; 1789 ebdp->cbd_bdu = 0; 1790 } 1791 /* Make sure the updates to rest of the descriptor are 1792 * performed before transferring ownership. 1793 */ 1794 wmb(); 1795 bdp->cbd_sc = cpu_to_fec16(status); 1796 1797 /* Update BD pointer to next entry */ 1798 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1799 1800 /* Doing this here will keep the FEC running while we process 1801 * incoming frames. On a heavily loaded network, we should be 1802 * able to keep up at the expense of system resources. 1803 */ 1804 writel(0, rxq->bd.reg_desc_active); 1805 } 1806 rxq->bd.cur = bdp; 1807 1808 if (xdp_result & FEC_ENET_XDP_REDIR) 1809 xdp_do_flush_map(); 1810 1811 return pkt_received; 1812 } 1813 1814 static int fec_enet_rx(struct net_device *ndev, int budget) 1815 { 1816 struct fec_enet_private *fep = netdev_priv(ndev); 1817 int i, done = 0; 1818 1819 /* Make sure that AVB queues are processed first. */ 1820 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1821 done += fec_enet_rx_queue(ndev, budget - done, i); 1822 1823 return done; 1824 } 1825 1826 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1827 { 1828 uint int_events; 1829 1830 int_events = readl(fep->hwp + FEC_IEVENT); 1831 1832 /* Don't clear MDIO events, we poll for those */ 1833 int_events &= ~FEC_ENET_MII; 1834 1835 writel(int_events, fep->hwp + FEC_IEVENT); 1836 1837 return int_events != 0; 1838 } 1839 1840 static irqreturn_t 1841 fec_enet_interrupt(int irq, void *dev_id) 1842 { 1843 struct net_device *ndev = dev_id; 1844 struct fec_enet_private *fep = netdev_priv(ndev); 1845 irqreturn_t ret = IRQ_NONE; 1846 1847 if (fec_enet_collect_events(fep) && fep->link) { 1848 ret = IRQ_HANDLED; 1849 1850 if (napi_schedule_prep(&fep->napi)) { 1851 /* Disable interrupts */ 1852 writel(0, fep->hwp + FEC_IMASK); 1853 __napi_schedule(&fep->napi); 1854 } 1855 } 1856 1857 return ret; 1858 } 1859 1860 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1861 { 1862 struct net_device *ndev = napi->dev; 1863 struct fec_enet_private *fep = netdev_priv(ndev); 1864 int done = 0; 1865 1866 do { 1867 done += fec_enet_rx(ndev, budget - done); 1868 fec_enet_tx(ndev, budget); 1869 } while ((done < budget) && fec_enet_collect_events(fep)); 1870 1871 if (done < budget) { 1872 napi_complete_done(napi, done); 1873 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1874 } 1875 1876 return done; 1877 } 1878 1879 /* ------------------------------------------------------------------------- */ 1880 static int fec_get_mac(struct net_device *ndev) 1881 { 1882 struct fec_enet_private *fep = netdev_priv(ndev); 1883 unsigned char *iap, tmpaddr[ETH_ALEN]; 1884 int ret; 1885 1886 /* 1887 * try to get mac address in following order: 1888 * 1889 * 1) module parameter via kernel command line in form 1890 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1891 */ 1892 iap = macaddr; 1893 1894 /* 1895 * 2) from device tree data 1896 */ 1897 if (!is_valid_ether_addr(iap)) { 1898 struct device_node *np = fep->pdev->dev.of_node; 1899 if (np) { 1900 ret = of_get_mac_address(np, tmpaddr); 1901 if (!ret) 1902 iap = tmpaddr; 1903 else if (ret == -EPROBE_DEFER) 1904 return ret; 1905 } 1906 } 1907 1908 /* 1909 * 3) from flash or fuse (via platform data) 1910 */ 1911 if (!is_valid_ether_addr(iap)) { 1912 #ifdef CONFIG_M5272 1913 if (FEC_FLASHMAC) 1914 iap = (unsigned char *)FEC_FLASHMAC; 1915 #else 1916 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1917 1918 if (pdata) 1919 iap = (unsigned char *)&pdata->mac; 1920 #endif 1921 } 1922 1923 /* 1924 * 4) FEC mac registers set by bootloader 1925 */ 1926 if (!is_valid_ether_addr(iap)) { 1927 *((__be32 *) &tmpaddr[0]) = 1928 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1929 *((__be16 *) &tmpaddr[4]) = 1930 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1931 iap = &tmpaddr[0]; 1932 } 1933 1934 /* 1935 * 5) random mac address 1936 */ 1937 if (!is_valid_ether_addr(iap)) { 1938 /* Report it and use a random ethernet address instead */ 1939 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1940 eth_hw_addr_random(ndev); 1941 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1942 ndev->dev_addr); 1943 return 0; 1944 } 1945 1946 /* Adjust MAC if using macaddr */ 1947 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); 1948 1949 return 0; 1950 } 1951 1952 /* ------------------------------------------------------------------------- */ 1953 1954 /* 1955 * Phy section 1956 */ 1957 static void fec_enet_adjust_link(struct net_device *ndev) 1958 { 1959 struct fec_enet_private *fep = netdev_priv(ndev); 1960 struct phy_device *phy_dev = ndev->phydev; 1961 int status_change = 0; 1962 1963 /* 1964 * If the netdev is down, or is going down, we're not interested 1965 * in link state events, so just mark our idea of the link as down 1966 * and ignore the event. 1967 */ 1968 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1969 fep->link = 0; 1970 } else if (phy_dev->link) { 1971 if (!fep->link) { 1972 fep->link = phy_dev->link; 1973 status_change = 1; 1974 } 1975 1976 if (fep->full_duplex != phy_dev->duplex) { 1977 fep->full_duplex = phy_dev->duplex; 1978 status_change = 1; 1979 } 1980 1981 if (phy_dev->speed != fep->speed) { 1982 fep->speed = phy_dev->speed; 1983 status_change = 1; 1984 } 1985 1986 /* if any of the above changed restart the FEC */ 1987 if (status_change) { 1988 napi_disable(&fep->napi); 1989 netif_tx_lock_bh(ndev); 1990 fec_restart(ndev); 1991 netif_tx_wake_all_queues(ndev); 1992 netif_tx_unlock_bh(ndev); 1993 napi_enable(&fep->napi); 1994 } 1995 } else { 1996 if (fep->link) { 1997 napi_disable(&fep->napi); 1998 netif_tx_lock_bh(ndev); 1999 fec_stop(ndev); 2000 netif_tx_unlock_bh(ndev); 2001 napi_enable(&fep->napi); 2002 fep->link = phy_dev->link; 2003 status_change = 1; 2004 } 2005 } 2006 2007 if (status_change) 2008 phy_print_status(phy_dev); 2009 } 2010 2011 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 2012 { 2013 uint ievent; 2014 int ret; 2015 2016 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 2017 ievent & FEC_ENET_MII, 2, 30000); 2018 2019 if (!ret) 2020 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2021 2022 return ret; 2023 } 2024 2025 static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) 2026 { 2027 struct fec_enet_private *fep = bus->priv; 2028 struct device *dev = &fep->pdev->dev; 2029 int ret = 0, frame_start, frame_addr, frame_op; 2030 2031 ret = pm_runtime_resume_and_get(dev); 2032 if (ret < 0) 2033 return ret; 2034 2035 /* C22 read */ 2036 frame_op = FEC_MMFR_OP_READ; 2037 frame_start = FEC_MMFR_ST; 2038 frame_addr = regnum; 2039 2040 /* start a read op */ 2041 writel(frame_start | frame_op | 2042 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2043 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2044 2045 /* wait for end of transfer */ 2046 ret = fec_enet_mdio_wait(fep); 2047 if (ret) { 2048 netdev_err(fep->netdev, "MDIO read timeout\n"); 2049 goto out; 2050 } 2051 2052 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2053 2054 out: 2055 pm_runtime_mark_last_busy(dev); 2056 pm_runtime_put_autosuspend(dev); 2057 2058 return ret; 2059 } 2060 2061 static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id, 2062 int devad, int regnum) 2063 { 2064 struct fec_enet_private *fep = bus->priv; 2065 struct device *dev = &fep->pdev->dev; 2066 int ret = 0, frame_start, frame_op; 2067 2068 ret = pm_runtime_resume_and_get(dev); 2069 if (ret < 0) 2070 return ret; 2071 2072 frame_start = FEC_MMFR_ST_C45; 2073 2074 /* write address */ 2075 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2076 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2077 FEC_MMFR_TA | (regnum & 0xFFFF), 2078 fep->hwp + FEC_MII_DATA); 2079 2080 /* wait for end of transfer */ 2081 ret = fec_enet_mdio_wait(fep); 2082 if (ret) { 2083 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2084 goto out; 2085 } 2086 2087 frame_op = FEC_MMFR_OP_READ_C45; 2088 2089 /* start a read op */ 2090 writel(frame_start | frame_op | 2091 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2092 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2093 2094 /* wait for end of transfer */ 2095 ret = fec_enet_mdio_wait(fep); 2096 if (ret) { 2097 netdev_err(fep->netdev, "MDIO read timeout\n"); 2098 goto out; 2099 } 2100 2101 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2102 2103 out: 2104 pm_runtime_mark_last_busy(dev); 2105 pm_runtime_put_autosuspend(dev); 2106 2107 return ret; 2108 } 2109 2110 static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, 2111 u16 value) 2112 { 2113 struct fec_enet_private *fep = bus->priv; 2114 struct device *dev = &fep->pdev->dev; 2115 int ret, frame_start, frame_addr; 2116 2117 ret = pm_runtime_resume_and_get(dev); 2118 if (ret < 0) 2119 return ret; 2120 2121 /* C22 write */ 2122 frame_start = FEC_MMFR_ST; 2123 frame_addr = regnum; 2124 2125 /* start a write op */ 2126 writel(frame_start | FEC_MMFR_OP_WRITE | 2127 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2128 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2129 fep->hwp + FEC_MII_DATA); 2130 2131 /* wait for end of transfer */ 2132 ret = fec_enet_mdio_wait(fep); 2133 if (ret) 2134 netdev_err(fep->netdev, "MDIO write timeout\n"); 2135 2136 pm_runtime_mark_last_busy(dev); 2137 pm_runtime_put_autosuspend(dev); 2138 2139 return ret; 2140 } 2141 2142 static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id, 2143 int devad, int regnum, u16 value) 2144 { 2145 struct fec_enet_private *fep = bus->priv; 2146 struct device *dev = &fep->pdev->dev; 2147 int ret, frame_start; 2148 2149 ret = pm_runtime_resume_and_get(dev); 2150 if (ret < 0) 2151 return ret; 2152 2153 frame_start = FEC_MMFR_ST_C45; 2154 2155 /* write address */ 2156 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2157 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2158 FEC_MMFR_TA | (regnum & 0xFFFF), 2159 fep->hwp + FEC_MII_DATA); 2160 2161 /* wait for end of transfer */ 2162 ret = fec_enet_mdio_wait(fep); 2163 if (ret) { 2164 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2165 goto out; 2166 } 2167 2168 /* start a write op */ 2169 writel(frame_start | FEC_MMFR_OP_WRITE | 2170 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2171 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2172 fep->hwp + FEC_MII_DATA); 2173 2174 /* wait for end of transfer */ 2175 ret = fec_enet_mdio_wait(fep); 2176 if (ret) 2177 netdev_err(fep->netdev, "MDIO write timeout\n"); 2178 2179 out: 2180 pm_runtime_mark_last_busy(dev); 2181 pm_runtime_put_autosuspend(dev); 2182 2183 return ret; 2184 } 2185 2186 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 2187 { 2188 struct fec_enet_private *fep = netdev_priv(ndev); 2189 struct phy_device *phy_dev = ndev->phydev; 2190 2191 if (phy_dev) { 2192 phy_reset_after_clk_enable(phy_dev); 2193 } else if (fep->phy_node) { 2194 /* 2195 * If the PHY still is not bound to the MAC, but there is 2196 * OF PHY node and a matching PHY device instance already, 2197 * use the OF PHY node to obtain the PHY device instance, 2198 * and then use that PHY device instance when triggering 2199 * the PHY reset. 2200 */ 2201 phy_dev = of_phy_find_device(fep->phy_node); 2202 phy_reset_after_clk_enable(phy_dev); 2203 put_device(&phy_dev->mdio.dev); 2204 } 2205 } 2206 2207 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 2208 { 2209 struct fec_enet_private *fep = netdev_priv(ndev); 2210 int ret; 2211 2212 if (enable) { 2213 ret = clk_prepare_enable(fep->clk_enet_out); 2214 if (ret) 2215 return ret; 2216 2217 if (fep->clk_ptp) { 2218 mutex_lock(&fep->ptp_clk_mutex); 2219 ret = clk_prepare_enable(fep->clk_ptp); 2220 if (ret) { 2221 mutex_unlock(&fep->ptp_clk_mutex); 2222 goto failed_clk_ptp; 2223 } else { 2224 fep->ptp_clk_on = true; 2225 } 2226 mutex_unlock(&fep->ptp_clk_mutex); 2227 } 2228 2229 ret = clk_prepare_enable(fep->clk_ref); 2230 if (ret) 2231 goto failed_clk_ref; 2232 2233 ret = clk_prepare_enable(fep->clk_2x_txclk); 2234 if (ret) 2235 goto failed_clk_2x_txclk; 2236 2237 fec_enet_phy_reset_after_clk_enable(ndev); 2238 } else { 2239 clk_disable_unprepare(fep->clk_enet_out); 2240 if (fep->clk_ptp) { 2241 mutex_lock(&fep->ptp_clk_mutex); 2242 clk_disable_unprepare(fep->clk_ptp); 2243 fep->ptp_clk_on = false; 2244 mutex_unlock(&fep->ptp_clk_mutex); 2245 } 2246 clk_disable_unprepare(fep->clk_ref); 2247 clk_disable_unprepare(fep->clk_2x_txclk); 2248 } 2249 2250 return 0; 2251 2252 failed_clk_2x_txclk: 2253 if (fep->clk_ref) 2254 clk_disable_unprepare(fep->clk_ref); 2255 failed_clk_ref: 2256 if (fep->clk_ptp) { 2257 mutex_lock(&fep->ptp_clk_mutex); 2258 clk_disable_unprepare(fep->clk_ptp); 2259 fep->ptp_clk_on = false; 2260 mutex_unlock(&fep->ptp_clk_mutex); 2261 } 2262 failed_clk_ptp: 2263 clk_disable_unprepare(fep->clk_enet_out); 2264 2265 return ret; 2266 } 2267 2268 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2269 struct device_node *np) 2270 { 2271 u32 rgmii_tx_delay, rgmii_rx_delay; 2272 2273 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2274 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2275 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2276 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2277 return -EINVAL; 2278 } else if (rgmii_tx_delay == 2000) { 2279 fep->rgmii_txc_dly = true; 2280 } 2281 } 2282 2283 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2284 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2285 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2286 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2287 return -EINVAL; 2288 } else if (rgmii_rx_delay == 2000) { 2289 fep->rgmii_rxc_dly = true; 2290 } 2291 } 2292 2293 return 0; 2294 } 2295 2296 static int fec_enet_mii_probe(struct net_device *ndev) 2297 { 2298 struct fec_enet_private *fep = netdev_priv(ndev); 2299 struct phy_device *phy_dev = NULL; 2300 char mdio_bus_id[MII_BUS_ID_SIZE]; 2301 char phy_name[MII_BUS_ID_SIZE + 3]; 2302 int phy_id; 2303 int dev_id = fep->dev_id; 2304 2305 if (fep->phy_node) { 2306 phy_dev = of_phy_connect(ndev, fep->phy_node, 2307 &fec_enet_adjust_link, 0, 2308 fep->phy_interface); 2309 if (!phy_dev) { 2310 netdev_err(ndev, "Unable to connect to phy\n"); 2311 return -ENODEV; 2312 } 2313 } else { 2314 /* check for attached phy */ 2315 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2316 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2317 continue; 2318 if (dev_id--) 2319 continue; 2320 strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2321 break; 2322 } 2323 2324 if (phy_id >= PHY_MAX_ADDR) { 2325 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2326 strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2327 phy_id = 0; 2328 } 2329 2330 snprintf(phy_name, sizeof(phy_name), 2331 PHY_ID_FMT, mdio_bus_id, phy_id); 2332 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2333 fep->phy_interface); 2334 } 2335 2336 if (IS_ERR(phy_dev)) { 2337 netdev_err(ndev, "could not attach to PHY\n"); 2338 return PTR_ERR(phy_dev); 2339 } 2340 2341 /* mask with MAC supported features */ 2342 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2343 phy_set_max_speed(phy_dev, 1000); 2344 phy_remove_link_mode(phy_dev, 2345 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2346 #if !defined(CONFIG_M5272) 2347 phy_support_sym_pause(phy_dev); 2348 #endif 2349 } 2350 else 2351 phy_set_max_speed(phy_dev, 100); 2352 2353 fep->link = 0; 2354 fep->full_duplex = 0; 2355 2356 phy_dev->mac_managed_pm = true; 2357 2358 phy_attached_info(phy_dev); 2359 2360 return 0; 2361 } 2362 2363 static int fec_enet_mii_init(struct platform_device *pdev) 2364 { 2365 static struct mii_bus *fec0_mii_bus; 2366 struct net_device *ndev = platform_get_drvdata(pdev); 2367 struct fec_enet_private *fep = netdev_priv(ndev); 2368 bool suppress_preamble = false; 2369 struct device_node *node; 2370 int err = -ENXIO; 2371 u32 mii_speed, holdtime; 2372 u32 bus_freq; 2373 2374 /* 2375 * The i.MX28 dual fec interfaces are not equal. 2376 * Here are the differences: 2377 * 2378 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2379 * - fec0 acts as the 1588 time master while fec1 is slave 2380 * - external phys can only be configured by fec0 2381 * 2382 * That is to say fec1 can not work independently. It only works 2383 * when fec0 is working. The reason behind this design is that the 2384 * second interface is added primarily for Switch mode. 2385 * 2386 * Because of the last point above, both phys are attached on fec0 2387 * mdio interface in board design, and need to be configured by 2388 * fec0 mii_bus. 2389 */ 2390 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2391 /* fec1 uses fec0 mii_bus */ 2392 if (mii_cnt && fec0_mii_bus) { 2393 fep->mii_bus = fec0_mii_bus; 2394 mii_cnt++; 2395 return 0; 2396 } 2397 return -ENOENT; 2398 } 2399 2400 bus_freq = 2500000; /* 2.5MHz by default */ 2401 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2402 if (node) { 2403 of_property_read_u32(node, "clock-frequency", &bus_freq); 2404 suppress_preamble = of_property_read_bool(node, 2405 "suppress-preamble"); 2406 } 2407 2408 /* 2409 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2410 * 2411 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2412 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2413 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2414 * document. 2415 */ 2416 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2417 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2418 mii_speed--; 2419 if (mii_speed > 63) { 2420 dev_err(&pdev->dev, 2421 "fec clock (%lu) too fast to get right mii speed\n", 2422 clk_get_rate(fep->clk_ipg)); 2423 err = -EINVAL; 2424 goto err_out; 2425 } 2426 2427 /* 2428 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2429 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2430 * versions are RAZ there, so just ignore the difference and write the 2431 * register always. 2432 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2433 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2434 * output. 2435 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2436 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2437 * holdtime cannot result in a value greater than 3. 2438 */ 2439 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2440 2441 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2442 2443 if (suppress_preamble) 2444 fep->phy_speed |= BIT(7); 2445 2446 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2447 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2448 * MII event generation condition: 2449 * - writing MSCR: 2450 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2451 * mscr_reg_data_in[7:0] != 0 2452 * - writing MMFR: 2453 * - mscr[7:0]_not_zero 2454 */ 2455 writel(0, fep->hwp + FEC_MII_DATA); 2456 } 2457 2458 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2459 2460 /* Clear any pending transaction complete indication */ 2461 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2462 2463 fep->mii_bus = mdiobus_alloc(); 2464 if (fep->mii_bus == NULL) { 2465 err = -ENOMEM; 2466 goto err_out; 2467 } 2468 2469 fep->mii_bus->name = "fec_enet_mii_bus"; 2470 fep->mii_bus->read = fec_enet_mdio_read_c22; 2471 fep->mii_bus->write = fec_enet_mdio_write_c22; 2472 if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) { 2473 fep->mii_bus->read_c45 = fec_enet_mdio_read_c45; 2474 fep->mii_bus->write_c45 = fec_enet_mdio_write_c45; 2475 } 2476 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2477 pdev->name, fep->dev_id + 1); 2478 fep->mii_bus->priv = fep; 2479 fep->mii_bus->parent = &pdev->dev; 2480 2481 err = of_mdiobus_register(fep->mii_bus, node); 2482 if (err) 2483 goto err_out_free_mdiobus; 2484 of_node_put(node); 2485 2486 mii_cnt++; 2487 2488 /* save fec0 mii_bus */ 2489 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2490 fec0_mii_bus = fep->mii_bus; 2491 2492 return 0; 2493 2494 err_out_free_mdiobus: 2495 mdiobus_free(fep->mii_bus); 2496 err_out: 2497 of_node_put(node); 2498 return err; 2499 } 2500 2501 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2502 { 2503 if (--mii_cnt == 0) { 2504 mdiobus_unregister(fep->mii_bus); 2505 mdiobus_free(fep->mii_bus); 2506 } 2507 } 2508 2509 static void fec_enet_get_drvinfo(struct net_device *ndev, 2510 struct ethtool_drvinfo *info) 2511 { 2512 struct fec_enet_private *fep = netdev_priv(ndev); 2513 2514 strscpy(info->driver, fep->pdev->dev.driver->name, 2515 sizeof(info->driver)); 2516 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2517 } 2518 2519 static int fec_enet_get_regs_len(struct net_device *ndev) 2520 { 2521 struct fec_enet_private *fep = netdev_priv(ndev); 2522 struct resource *r; 2523 int s = 0; 2524 2525 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2526 if (r) 2527 s = resource_size(r); 2528 2529 return s; 2530 } 2531 2532 /* List of registers that can be safety be read to dump them with ethtool */ 2533 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2534 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2535 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2536 static __u32 fec_enet_register_version = 2; 2537 static u32 fec_enet_register_offset[] = { 2538 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2539 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2540 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2541 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2542 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2543 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2544 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2545 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2546 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2547 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2548 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2549 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2550 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2551 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2552 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2553 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2554 RMON_T_P_GTE2048, RMON_T_OCTETS, 2555 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2556 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2557 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2558 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2559 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2560 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2561 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2562 RMON_R_P_GTE2048, RMON_R_OCTETS, 2563 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2564 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2565 }; 2566 /* for i.MX6ul */ 2567 static u32 fec_enet_register_offset_6ul[] = { 2568 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2569 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2570 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0, 2571 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, 2572 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0, 2573 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2574 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, 2575 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2576 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2577 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2578 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2579 RMON_T_P_GTE2048, RMON_T_OCTETS, 2580 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2581 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2582 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2583 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2584 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2585 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2586 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2587 RMON_R_P_GTE2048, RMON_R_OCTETS, 2588 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2589 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2590 }; 2591 #else 2592 static __u32 fec_enet_register_version = 1; 2593 static u32 fec_enet_register_offset[] = { 2594 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2595 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2596 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2597 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2598 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2599 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2600 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2601 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2602 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2603 }; 2604 #endif 2605 2606 static void fec_enet_get_regs(struct net_device *ndev, 2607 struct ethtool_regs *regs, void *regbuf) 2608 { 2609 struct fec_enet_private *fep = netdev_priv(ndev); 2610 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2611 struct device *dev = &fep->pdev->dev; 2612 u32 *buf = (u32 *)regbuf; 2613 u32 i, off; 2614 int ret; 2615 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2616 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2617 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2618 u32 *reg_list; 2619 u32 reg_cnt; 2620 2621 if (!of_machine_is_compatible("fsl,imx6ul")) { 2622 reg_list = fec_enet_register_offset; 2623 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2624 } else { 2625 reg_list = fec_enet_register_offset_6ul; 2626 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul); 2627 } 2628 #else 2629 /* coldfire */ 2630 static u32 *reg_list = fec_enet_register_offset; 2631 static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2632 #endif 2633 ret = pm_runtime_resume_and_get(dev); 2634 if (ret < 0) 2635 return; 2636 2637 regs->version = fec_enet_register_version; 2638 2639 memset(buf, 0, regs->len); 2640 2641 for (i = 0; i < reg_cnt; i++) { 2642 off = reg_list[i]; 2643 2644 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2645 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2646 continue; 2647 2648 off >>= 2; 2649 buf[off] = readl(&theregs[off]); 2650 } 2651 2652 pm_runtime_mark_last_busy(dev); 2653 pm_runtime_put_autosuspend(dev); 2654 } 2655 2656 static int fec_enet_get_ts_info(struct net_device *ndev, 2657 struct ethtool_ts_info *info) 2658 { 2659 struct fec_enet_private *fep = netdev_priv(ndev); 2660 2661 if (fep->bufdesc_ex) { 2662 2663 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2664 SOF_TIMESTAMPING_RX_SOFTWARE | 2665 SOF_TIMESTAMPING_SOFTWARE | 2666 SOF_TIMESTAMPING_TX_HARDWARE | 2667 SOF_TIMESTAMPING_RX_HARDWARE | 2668 SOF_TIMESTAMPING_RAW_HARDWARE; 2669 if (fep->ptp_clock) 2670 info->phc_index = ptp_clock_index(fep->ptp_clock); 2671 else 2672 info->phc_index = -1; 2673 2674 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2675 (1 << HWTSTAMP_TX_ON); 2676 2677 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2678 (1 << HWTSTAMP_FILTER_ALL); 2679 return 0; 2680 } else { 2681 return ethtool_op_get_ts_info(ndev, info); 2682 } 2683 } 2684 2685 #if !defined(CONFIG_M5272) 2686 2687 static void fec_enet_get_pauseparam(struct net_device *ndev, 2688 struct ethtool_pauseparam *pause) 2689 { 2690 struct fec_enet_private *fep = netdev_priv(ndev); 2691 2692 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2693 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2694 pause->rx_pause = pause->tx_pause; 2695 } 2696 2697 static int fec_enet_set_pauseparam(struct net_device *ndev, 2698 struct ethtool_pauseparam *pause) 2699 { 2700 struct fec_enet_private *fep = netdev_priv(ndev); 2701 2702 if (!ndev->phydev) 2703 return -ENODEV; 2704 2705 if (pause->tx_pause != pause->rx_pause) { 2706 netdev_info(ndev, 2707 "hardware only support enable/disable both tx and rx"); 2708 return -EINVAL; 2709 } 2710 2711 fep->pause_flag = 0; 2712 2713 /* tx pause must be same as rx pause */ 2714 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2715 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2716 2717 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2718 pause->autoneg); 2719 2720 if (pause->autoneg) { 2721 if (netif_running(ndev)) 2722 fec_stop(ndev); 2723 phy_start_aneg(ndev->phydev); 2724 } 2725 if (netif_running(ndev)) { 2726 napi_disable(&fep->napi); 2727 netif_tx_lock_bh(ndev); 2728 fec_restart(ndev); 2729 netif_tx_wake_all_queues(ndev); 2730 netif_tx_unlock_bh(ndev); 2731 napi_enable(&fep->napi); 2732 } 2733 2734 return 0; 2735 } 2736 2737 static const struct fec_stat { 2738 char name[ETH_GSTRING_LEN]; 2739 u16 offset; 2740 } fec_stats[] = { 2741 /* RMON TX */ 2742 { "tx_dropped", RMON_T_DROP }, 2743 { "tx_packets", RMON_T_PACKETS }, 2744 { "tx_broadcast", RMON_T_BC_PKT }, 2745 { "tx_multicast", RMON_T_MC_PKT }, 2746 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2747 { "tx_undersize", RMON_T_UNDERSIZE }, 2748 { "tx_oversize", RMON_T_OVERSIZE }, 2749 { "tx_fragment", RMON_T_FRAG }, 2750 { "tx_jabber", RMON_T_JAB }, 2751 { "tx_collision", RMON_T_COL }, 2752 { "tx_64byte", RMON_T_P64 }, 2753 { "tx_65to127byte", RMON_T_P65TO127 }, 2754 { "tx_128to255byte", RMON_T_P128TO255 }, 2755 { "tx_256to511byte", RMON_T_P256TO511 }, 2756 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2757 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2758 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2759 { "tx_octets", RMON_T_OCTETS }, 2760 2761 /* IEEE TX */ 2762 { "IEEE_tx_drop", IEEE_T_DROP }, 2763 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2764 { "IEEE_tx_1col", IEEE_T_1COL }, 2765 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2766 { "IEEE_tx_def", IEEE_T_DEF }, 2767 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2768 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2769 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2770 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2771 { "IEEE_tx_sqe", IEEE_T_SQE }, 2772 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2773 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2774 2775 /* RMON RX */ 2776 { "rx_packets", RMON_R_PACKETS }, 2777 { "rx_broadcast", RMON_R_BC_PKT }, 2778 { "rx_multicast", RMON_R_MC_PKT }, 2779 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2780 { "rx_undersize", RMON_R_UNDERSIZE }, 2781 { "rx_oversize", RMON_R_OVERSIZE }, 2782 { "rx_fragment", RMON_R_FRAG }, 2783 { "rx_jabber", RMON_R_JAB }, 2784 { "rx_64byte", RMON_R_P64 }, 2785 { "rx_65to127byte", RMON_R_P65TO127 }, 2786 { "rx_128to255byte", RMON_R_P128TO255 }, 2787 { "rx_256to511byte", RMON_R_P256TO511 }, 2788 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2789 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2790 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2791 { "rx_octets", RMON_R_OCTETS }, 2792 2793 /* IEEE RX */ 2794 { "IEEE_rx_drop", IEEE_R_DROP }, 2795 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2796 { "IEEE_rx_crc", IEEE_R_CRC }, 2797 { "IEEE_rx_align", IEEE_R_ALIGN }, 2798 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2799 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2800 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2801 }; 2802 2803 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2804 2805 static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = { 2806 "rx_xdp_redirect", /* RX_XDP_REDIRECT = 0, */ 2807 "rx_xdp_pass", /* RX_XDP_PASS, */ 2808 "rx_xdp_drop", /* RX_XDP_DROP, */ 2809 "rx_xdp_tx", /* RX_XDP_TX, */ 2810 "rx_xdp_tx_errors", /* RX_XDP_TX_ERRORS, */ 2811 "tx_xdp_xmit", /* TX_XDP_XMIT, */ 2812 "tx_xdp_xmit_errors", /* TX_XDP_XMIT_ERRORS, */ 2813 }; 2814 2815 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2816 { 2817 struct fec_enet_private *fep = netdev_priv(dev); 2818 int i; 2819 2820 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2821 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2822 } 2823 2824 static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data) 2825 { 2826 u64 xdp_stats[XDP_STATS_TOTAL] = { 0 }; 2827 struct fec_enet_priv_rx_q *rxq; 2828 int i, j; 2829 2830 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2831 rxq = fep->rx_queue[i]; 2832 2833 for (j = 0; j < XDP_STATS_TOTAL; j++) 2834 xdp_stats[j] += rxq->stats[j]; 2835 } 2836 2837 memcpy(data, xdp_stats, sizeof(xdp_stats)); 2838 } 2839 2840 static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data) 2841 { 2842 #ifdef CONFIG_PAGE_POOL_STATS 2843 struct page_pool_stats stats = {}; 2844 struct fec_enet_priv_rx_q *rxq; 2845 int i; 2846 2847 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2848 rxq = fep->rx_queue[i]; 2849 2850 if (!rxq->page_pool) 2851 continue; 2852 2853 page_pool_get_stats(rxq->page_pool, &stats); 2854 } 2855 2856 page_pool_ethtool_stats_get(data, &stats); 2857 #endif 2858 } 2859 2860 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2861 struct ethtool_stats *stats, u64 *data) 2862 { 2863 struct fec_enet_private *fep = netdev_priv(dev); 2864 2865 if (netif_running(dev)) 2866 fec_enet_update_ethtool_stats(dev); 2867 2868 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2869 data += FEC_STATS_SIZE / sizeof(u64); 2870 2871 fec_enet_get_xdp_stats(fep, data); 2872 data += XDP_STATS_TOTAL; 2873 2874 fec_enet_page_pool_stats(fep, data); 2875 } 2876 2877 static void fec_enet_get_strings(struct net_device *netdev, 2878 u32 stringset, u8 *data) 2879 { 2880 int i; 2881 switch (stringset) { 2882 case ETH_SS_STATS: 2883 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) { 2884 memcpy(data, fec_stats[i].name, ETH_GSTRING_LEN); 2885 data += ETH_GSTRING_LEN; 2886 } 2887 for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) { 2888 strncpy(data, fec_xdp_stat_strs[i], ETH_GSTRING_LEN); 2889 data += ETH_GSTRING_LEN; 2890 } 2891 page_pool_ethtool_stats_get_strings(data); 2892 2893 break; 2894 case ETH_SS_TEST: 2895 net_selftest_get_strings(data); 2896 break; 2897 } 2898 } 2899 2900 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2901 { 2902 int count; 2903 2904 switch (sset) { 2905 case ETH_SS_STATS: 2906 count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL; 2907 count += page_pool_ethtool_stats_get_count(); 2908 return count; 2909 2910 case ETH_SS_TEST: 2911 return net_selftest_get_count(); 2912 default: 2913 return -EOPNOTSUPP; 2914 } 2915 } 2916 2917 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2918 { 2919 struct fec_enet_private *fep = netdev_priv(dev); 2920 struct fec_enet_priv_rx_q *rxq; 2921 int i, j; 2922 2923 /* Disable MIB statistics counters */ 2924 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2925 2926 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2927 writel(0, fep->hwp + fec_stats[i].offset); 2928 2929 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2930 rxq = fep->rx_queue[i]; 2931 for (j = 0; j < XDP_STATS_TOTAL; j++) 2932 rxq->stats[j] = 0; 2933 } 2934 2935 /* Don't disable MIB statistics counters */ 2936 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2937 } 2938 2939 #else /* !defined(CONFIG_M5272) */ 2940 #define FEC_STATS_SIZE 0 2941 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2942 { 2943 } 2944 2945 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2946 { 2947 } 2948 #endif /* !defined(CONFIG_M5272) */ 2949 2950 /* ITR clock source is enet system clock (clk_ahb). 2951 * TCTT unit is cycle_ns * 64 cycle 2952 * So, the ICTT value = X us / (cycle_ns * 64) 2953 */ 2954 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2955 { 2956 struct fec_enet_private *fep = netdev_priv(ndev); 2957 2958 return us * (fep->itr_clk_rate / 64000) / 1000; 2959 } 2960 2961 /* Set threshold for interrupt coalescing */ 2962 static void fec_enet_itr_coal_set(struct net_device *ndev) 2963 { 2964 struct fec_enet_private *fep = netdev_priv(ndev); 2965 int rx_itr, tx_itr; 2966 2967 /* Must be greater than zero to avoid unpredictable behavior */ 2968 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2969 !fep->tx_time_itr || !fep->tx_pkts_itr) 2970 return; 2971 2972 /* Select enet system clock as Interrupt Coalescing 2973 * timer Clock Source 2974 */ 2975 rx_itr = FEC_ITR_CLK_SEL; 2976 tx_itr = FEC_ITR_CLK_SEL; 2977 2978 /* set ICFT and ICTT */ 2979 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2980 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2981 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2982 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2983 2984 rx_itr |= FEC_ITR_EN; 2985 tx_itr |= FEC_ITR_EN; 2986 2987 writel(tx_itr, fep->hwp + FEC_TXIC0); 2988 writel(rx_itr, fep->hwp + FEC_RXIC0); 2989 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 2990 writel(tx_itr, fep->hwp + FEC_TXIC1); 2991 writel(rx_itr, fep->hwp + FEC_RXIC1); 2992 writel(tx_itr, fep->hwp + FEC_TXIC2); 2993 writel(rx_itr, fep->hwp + FEC_RXIC2); 2994 } 2995 } 2996 2997 static int fec_enet_get_coalesce(struct net_device *ndev, 2998 struct ethtool_coalesce *ec, 2999 struct kernel_ethtool_coalesce *kernel_coal, 3000 struct netlink_ext_ack *extack) 3001 { 3002 struct fec_enet_private *fep = netdev_priv(ndev); 3003 3004 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3005 return -EOPNOTSUPP; 3006 3007 ec->rx_coalesce_usecs = fep->rx_time_itr; 3008 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 3009 3010 ec->tx_coalesce_usecs = fep->tx_time_itr; 3011 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 3012 3013 return 0; 3014 } 3015 3016 static int fec_enet_set_coalesce(struct net_device *ndev, 3017 struct ethtool_coalesce *ec, 3018 struct kernel_ethtool_coalesce *kernel_coal, 3019 struct netlink_ext_ack *extack) 3020 { 3021 struct fec_enet_private *fep = netdev_priv(ndev); 3022 struct device *dev = &fep->pdev->dev; 3023 unsigned int cycle; 3024 3025 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3026 return -EOPNOTSUPP; 3027 3028 if (ec->rx_max_coalesced_frames > 255) { 3029 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 3030 return -EINVAL; 3031 } 3032 3033 if (ec->tx_max_coalesced_frames > 255) { 3034 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 3035 return -EINVAL; 3036 } 3037 3038 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 3039 if (cycle > 0xFFFF) { 3040 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 3041 return -EINVAL; 3042 } 3043 3044 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 3045 if (cycle > 0xFFFF) { 3046 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 3047 return -EINVAL; 3048 } 3049 3050 fep->rx_time_itr = ec->rx_coalesce_usecs; 3051 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 3052 3053 fep->tx_time_itr = ec->tx_coalesce_usecs; 3054 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 3055 3056 fec_enet_itr_coal_set(ndev); 3057 3058 return 0; 3059 } 3060 3061 /* LPI Sleep Ts count base on tx clk (clk_ref). 3062 * The lpi sleep cnt value = X us / (cycle_ns). 3063 */ 3064 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 3065 { 3066 struct fec_enet_private *fep = netdev_priv(ndev); 3067 3068 return us * (fep->clk_ref_rate / 1000) / 1000; 3069 } 3070 3071 static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable) 3072 { 3073 struct fec_enet_private *fep = netdev_priv(ndev); 3074 struct ethtool_eee *p = &fep->eee; 3075 unsigned int sleep_cycle, wake_cycle; 3076 int ret = 0; 3077 3078 if (enable) { 3079 ret = phy_init_eee(ndev->phydev, false); 3080 if (ret) 3081 return ret; 3082 3083 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer); 3084 wake_cycle = sleep_cycle; 3085 } else { 3086 sleep_cycle = 0; 3087 wake_cycle = 0; 3088 } 3089 3090 p->tx_lpi_enabled = enable; 3091 p->eee_enabled = enable; 3092 p->eee_active = enable; 3093 3094 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 3095 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 3096 3097 return 0; 3098 } 3099 3100 static int 3101 fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata) 3102 { 3103 struct fec_enet_private *fep = netdev_priv(ndev); 3104 struct ethtool_eee *p = &fep->eee; 3105 3106 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3107 return -EOPNOTSUPP; 3108 3109 if (!netif_running(ndev)) 3110 return -ENETDOWN; 3111 3112 edata->eee_enabled = p->eee_enabled; 3113 edata->eee_active = p->eee_active; 3114 edata->tx_lpi_timer = p->tx_lpi_timer; 3115 edata->tx_lpi_enabled = p->tx_lpi_enabled; 3116 3117 return phy_ethtool_get_eee(ndev->phydev, edata); 3118 } 3119 3120 static int 3121 fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata) 3122 { 3123 struct fec_enet_private *fep = netdev_priv(ndev); 3124 struct ethtool_eee *p = &fep->eee; 3125 int ret = 0; 3126 3127 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3128 return -EOPNOTSUPP; 3129 3130 if (!netif_running(ndev)) 3131 return -ENETDOWN; 3132 3133 p->tx_lpi_timer = edata->tx_lpi_timer; 3134 3135 if (!edata->eee_enabled || !edata->tx_lpi_enabled || 3136 !edata->tx_lpi_timer) 3137 ret = fec_enet_eee_mode_set(ndev, false); 3138 else 3139 ret = fec_enet_eee_mode_set(ndev, true); 3140 3141 if (ret) 3142 return ret; 3143 3144 return phy_ethtool_set_eee(ndev->phydev, edata); 3145 } 3146 3147 static void 3148 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3149 { 3150 struct fec_enet_private *fep = netdev_priv(ndev); 3151 3152 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 3153 wol->supported = WAKE_MAGIC; 3154 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 3155 } else { 3156 wol->supported = wol->wolopts = 0; 3157 } 3158 } 3159 3160 static int 3161 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3162 { 3163 struct fec_enet_private *fep = netdev_priv(ndev); 3164 3165 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 3166 return -EINVAL; 3167 3168 if (wol->wolopts & ~WAKE_MAGIC) 3169 return -EINVAL; 3170 3171 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 3172 if (device_may_wakeup(&ndev->dev)) 3173 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 3174 else 3175 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 3176 3177 return 0; 3178 } 3179 3180 static const struct ethtool_ops fec_enet_ethtool_ops = { 3181 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3182 ETHTOOL_COALESCE_MAX_FRAMES, 3183 .get_drvinfo = fec_enet_get_drvinfo, 3184 .get_regs_len = fec_enet_get_regs_len, 3185 .get_regs = fec_enet_get_regs, 3186 .nway_reset = phy_ethtool_nway_reset, 3187 .get_link = ethtool_op_get_link, 3188 .get_coalesce = fec_enet_get_coalesce, 3189 .set_coalesce = fec_enet_set_coalesce, 3190 #ifndef CONFIG_M5272 3191 .get_pauseparam = fec_enet_get_pauseparam, 3192 .set_pauseparam = fec_enet_set_pauseparam, 3193 .get_strings = fec_enet_get_strings, 3194 .get_ethtool_stats = fec_enet_get_ethtool_stats, 3195 .get_sset_count = fec_enet_get_sset_count, 3196 #endif 3197 .get_ts_info = fec_enet_get_ts_info, 3198 .get_wol = fec_enet_get_wol, 3199 .set_wol = fec_enet_set_wol, 3200 .get_eee = fec_enet_get_eee, 3201 .set_eee = fec_enet_set_eee, 3202 .get_link_ksettings = phy_ethtool_get_link_ksettings, 3203 .set_link_ksettings = phy_ethtool_set_link_ksettings, 3204 .self_test = net_selftest, 3205 }; 3206 3207 static void fec_enet_free_buffers(struct net_device *ndev) 3208 { 3209 struct fec_enet_private *fep = netdev_priv(ndev); 3210 unsigned int i; 3211 struct sk_buff *skb; 3212 struct fec_enet_priv_tx_q *txq; 3213 struct fec_enet_priv_rx_q *rxq; 3214 unsigned int q; 3215 3216 for (q = 0; q < fep->num_rx_queues; q++) { 3217 rxq = fep->rx_queue[q]; 3218 for (i = 0; i < rxq->bd.ring_size; i++) 3219 page_pool_put_full_page(rxq->page_pool, rxq->rx_skb_info[i].page, false); 3220 3221 for (i = 0; i < XDP_STATS_TOTAL; i++) 3222 rxq->stats[i] = 0; 3223 3224 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 3225 xdp_rxq_info_unreg(&rxq->xdp_rxq); 3226 page_pool_destroy(rxq->page_pool); 3227 rxq->page_pool = NULL; 3228 } 3229 3230 for (q = 0; q < fep->num_tx_queues; q++) { 3231 txq = fep->tx_queue[q]; 3232 for (i = 0; i < txq->bd.ring_size; i++) { 3233 kfree(txq->tx_bounce[i]); 3234 txq->tx_bounce[i] = NULL; 3235 3236 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 3237 skb = txq->tx_buf[i].skb; 3238 txq->tx_buf[i].skb = NULL; 3239 dev_kfree_skb(skb); 3240 } else { 3241 if (txq->tx_buf[i].xdp) { 3242 xdp_return_frame(txq->tx_buf[i].xdp); 3243 txq->tx_buf[i].xdp = NULL; 3244 } 3245 3246 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3247 } 3248 } 3249 } 3250 } 3251 3252 static void fec_enet_free_queue(struct net_device *ndev) 3253 { 3254 struct fec_enet_private *fep = netdev_priv(ndev); 3255 int i; 3256 struct fec_enet_priv_tx_q *txq; 3257 3258 for (i = 0; i < fep->num_tx_queues; i++) 3259 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 3260 txq = fep->tx_queue[i]; 3261 dma_free_coherent(&fep->pdev->dev, 3262 txq->bd.ring_size * TSO_HEADER_SIZE, 3263 txq->tso_hdrs, 3264 txq->tso_hdrs_dma); 3265 } 3266 3267 for (i = 0; i < fep->num_rx_queues; i++) 3268 kfree(fep->rx_queue[i]); 3269 for (i = 0; i < fep->num_tx_queues; i++) 3270 kfree(fep->tx_queue[i]); 3271 } 3272 3273 static int fec_enet_alloc_queue(struct net_device *ndev) 3274 { 3275 struct fec_enet_private *fep = netdev_priv(ndev); 3276 int i; 3277 int ret = 0; 3278 struct fec_enet_priv_tx_q *txq; 3279 3280 for (i = 0; i < fep->num_tx_queues; i++) { 3281 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3282 if (!txq) { 3283 ret = -ENOMEM; 3284 goto alloc_failed; 3285 } 3286 3287 fep->tx_queue[i] = txq; 3288 txq->bd.ring_size = TX_RING_SIZE; 3289 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3290 3291 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3292 txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS; 3293 3294 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 3295 txq->bd.ring_size * TSO_HEADER_SIZE, 3296 &txq->tso_hdrs_dma, 3297 GFP_KERNEL); 3298 if (!txq->tso_hdrs) { 3299 ret = -ENOMEM; 3300 goto alloc_failed; 3301 } 3302 } 3303 3304 for (i = 0; i < fep->num_rx_queues; i++) { 3305 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3306 GFP_KERNEL); 3307 if (!fep->rx_queue[i]) { 3308 ret = -ENOMEM; 3309 goto alloc_failed; 3310 } 3311 3312 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3313 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3314 } 3315 return ret; 3316 3317 alloc_failed: 3318 fec_enet_free_queue(ndev); 3319 return ret; 3320 } 3321 3322 static int 3323 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3324 { 3325 struct fec_enet_private *fep = netdev_priv(ndev); 3326 struct fec_enet_priv_rx_q *rxq; 3327 dma_addr_t phys_addr; 3328 struct bufdesc *bdp; 3329 struct page *page; 3330 int i, err; 3331 3332 rxq = fep->rx_queue[queue]; 3333 bdp = rxq->bd.base; 3334 3335 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size); 3336 if (err < 0) { 3337 netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err); 3338 return err; 3339 } 3340 3341 for (i = 0; i < rxq->bd.ring_size; i++) { 3342 page = page_pool_dev_alloc_pages(rxq->page_pool); 3343 if (!page) 3344 goto err_alloc; 3345 3346 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM; 3347 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 3348 3349 rxq->rx_skb_info[i].page = page; 3350 rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM; 3351 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3352 3353 if (fep->bufdesc_ex) { 3354 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3355 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3356 } 3357 3358 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3359 } 3360 3361 /* Set the last buffer to wrap. */ 3362 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3363 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3364 return 0; 3365 3366 err_alloc: 3367 fec_enet_free_buffers(ndev); 3368 return -ENOMEM; 3369 } 3370 3371 static int 3372 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3373 { 3374 struct fec_enet_private *fep = netdev_priv(ndev); 3375 unsigned int i; 3376 struct bufdesc *bdp; 3377 struct fec_enet_priv_tx_q *txq; 3378 3379 txq = fep->tx_queue[queue]; 3380 bdp = txq->bd.base; 3381 for (i = 0; i < txq->bd.ring_size; i++) { 3382 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3383 if (!txq->tx_bounce[i]) 3384 goto err_alloc; 3385 3386 bdp->cbd_sc = cpu_to_fec16(0); 3387 bdp->cbd_bufaddr = cpu_to_fec32(0); 3388 3389 if (fep->bufdesc_ex) { 3390 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3391 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3392 } 3393 3394 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3395 } 3396 3397 /* Set the last buffer to wrap. */ 3398 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3399 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3400 3401 return 0; 3402 3403 err_alloc: 3404 fec_enet_free_buffers(ndev); 3405 return -ENOMEM; 3406 } 3407 3408 static int fec_enet_alloc_buffers(struct net_device *ndev) 3409 { 3410 struct fec_enet_private *fep = netdev_priv(ndev); 3411 unsigned int i; 3412 3413 for (i = 0; i < fep->num_rx_queues; i++) 3414 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3415 return -ENOMEM; 3416 3417 for (i = 0; i < fep->num_tx_queues; i++) 3418 if (fec_enet_alloc_txq_buffers(ndev, i)) 3419 return -ENOMEM; 3420 return 0; 3421 } 3422 3423 static int 3424 fec_enet_open(struct net_device *ndev) 3425 { 3426 struct fec_enet_private *fep = netdev_priv(ndev); 3427 int ret; 3428 bool reset_again; 3429 3430 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3431 if (ret < 0) 3432 return ret; 3433 3434 pinctrl_pm_select_default_state(&fep->pdev->dev); 3435 ret = fec_enet_clk_enable(ndev, true); 3436 if (ret) 3437 goto clk_enable; 3438 3439 /* During the first fec_enet_open call the PHY isn't probed at this 3440 * point. Therefore the phy_reset_after_clk_enable() call within 3441 * fec_enet_clk_enable() fails. As we need this reset in order to be 3442 * sure the PHY is working correctly we check if we need to reset again 3443 * later when the PHY is probed 3444 */ 3445 if (ndev->phydev && ndev->phydev->drv) 3446 reset_again = false; 3447 else 3448 reset_again = true; 3449 3450 /* I should reset the ring buffers here, but I don't yet know 3451 * a simple way to do that. 3452 */ 3453 3454 ret = fec_enet_alloc_buffers(ndev); 3455 if (ret) 3456 goto err_enet_alloc; 3457 3458 /* Init MAC prior to mii bus probe */ 3459 fec_restart(ndev); 3460 3461 /* Call phy_reset_after_clk_enable() again if it failed during 3462 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3463 */ 3464 if (reset_again) 3465 fec_enet_phy_reset_after_clk_enable(ndev); 3466 3467 /* Probe and connect to PHY when open the interface */ 3468 ret = fec_enet_mii_probe(ndev); 3469 if (ret) 3470 goto err_enet_mii_probe; 3471 3472 if (fep->quirks & FEC_QUIRK_ERR006687) 3473 imx6q_cpuidle_fec_irqs_used(); 3474 3475 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3476 cpu_latency_qos_add_request(&fep->pm_qos_req, 0); 3477 3478 napi_enable(&fep->napi); 3479 phy_start(ndev->phydev); 3480 netif_tx_start_all_queues(ndev); 3481 3482 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3483 FEC_WOL_FLAG_ENABLE); 3484 3485 return 0; 3486 3487 err_enet_mii_probe: 3488 fec_enet_free_buffers(ndev); 3489 err_enet_alloc: 3490 fec_enet_clk_enable(ndev, false); 3491 clk_enable: 3492 pm_runtime_mark_last_busy(&fep->pdev->dev); 3493 pm_runtime_put_autosuspend(&fep->pdev->dev); 3494 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3495 return ret; 3496 } 3497 3498 static int 3499 fec_enet_close(struct net_device *ndev) 3500 { 3501 struct fec_enet_private *fep = netdev_priv(ndev); 3502 3503 phy_stop(ndev->phydev); 3504 3505 if (netif_device_present(ndev)) { 3506 napi_disable(&fep->napi); 3507 netif_tx_disable(ndev); 3508 fec_stop(ndev); 3509 } 3510 3511 phy_disconnect(ndev->phydev); 3512 3513 if (fep->quirks & FEC_QUIRK_ERR006687) 3514 imx6q_cpuidle_fec_irqs_unused(); 3515 3516 fec_enet_update_ethtool_stats(ndev); 3517 3518 fec_enet_clk_enable(ndev, false); 3519 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3520 cpu_latency_qos_remove_request(&fep->pm_qos_req); 3521 3522 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3523 pm_runtime_mark_last_busy(&fep->pdev->dev); 3524 pm_runtime_put_autosuspend(&fep->pdev->dev); 3525 3526 fec_enet_free_buffers(ndev); 3527 3528 return 0; 3529 } 3530 3531 /* Set or clear the multicast filter for this adaptor. 3532 * Skeleton taken from sunlance driver. 3533 * The CPM Ethernet implementation allows Multicast as well as individual 3534 * MAC address filtering. Some of the drivers check to make sure it is 3535 * a group multicast address, and discard those that are not. I guess I 3536 * will do the same for now, but just remove the test if you want 3537 * individual filtering as well (do the upper net layers want or support 3538 * this kind of feature?). 3539 */ 3540 3541 #define FEC_HASH_BITS 6 /* #bits in hash */ 3542 3543 static void set_multicast_list(struct net_device *ndev) 3544 { 3545 struct fec_enet_private *fep = netdev_priv(ndev); 3546 struct netdev_hw_addr *ha; 3547 unsigned int crc, tmp; 3548 unsigned char hash; 3549 unsigned int hash_high = 0, hash_low = 0; 3550 3551 if (ndev->flags & IFF_PROMISC) { 3552 tmp = readl(fep->hwp + FEC_R_CNTRL); 3553 tmp |= 0x8; 3554 writel(tmp, fep->hwp + FEC_R_CNTRL); 3555 return; 3556 } 3557 3558 tmp = readl(fep->hwp + FEC_R_CNTRL); 3559 tmp &= ~0x8; 3560 writel(tmp, fep->hwp + FEC_R_CNTRL); 3561 3562 if (ndev->flags & IFF_ALLMULTI) { 3563 /* Catch all multicast addresses, so set the 3564 * filter to all 1's 3565 */ 3566 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3567 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3568 3569 return; 3570 } 3571 3572 /* Add the addresses in hash register */ 3573 netdev_for_each_mc_addr(ha, ndev) { 3574 /* calculate crc32 value of mac address */ 3575 crc = ether_crc_le(ndev->addr_len, ha->addr); 3576 3577 /* only upper 6 bits (FEC_HASH_BITS) are used 3578 * which point to specific bit in the hash registers 3579 */ 3580 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3581 3582 if (hash > 31) 3583 hash_high |= 1 << (hash - 32); 3584 else 3585 hash_low |= 1 << hash; 3586 } 3587 3588 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3589 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3590 } 3591 3592 /* Set a MAC change in hardware. */ 3593 static int 3594 fec_set_mac_address(struct net_device *ndev, void *p) 3595 { 3596 struct fec_enet_private *fep = netdev_priv(ndev); 3597 struct sockaddr *addr = p; 3598 3599 if (addr) { 3600 if (!is_valid_ether_addr(addr->sa_data)) 3601 return -EADDRNOTAVAIL; 3602 eth_hw_addr_set(ndev, addr->sa_data); 3603 } 3604 3605 /* Add netif status check here to avoid system hang in below case: 3606 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3607 * After ethx down, fec all clocks are gated off and then register 3608 * access causes system hang. 3609 */ 3610 if (!netif_running(ndev)) 3611 return 0; 3612 3613 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3614 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3615 fep->hwp + FEC_ADDR_LOW); 3616 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3617 fep->hwp + FEC_ADDR_HIGH); 3618 return 0; 3619 } 3620 3621 #ifdef CONFIG_NET_POLL_CONTROLLER 3622 /** 3623 * fec_poll_controller - FEC Poll controller function 3624 * @dev: The FEC network adapter 3625 * 3626 * Polled functionality used by netconsole and others in non interrupt mode 3627 * 3628 */ 3629 static void fec_poll_controller(struct net_device *dev) 3630 { 3631 int i; 3632 struct fec_enet_private *fep = netdev_priv(dev); 3633 3634 for (i = 0; i < FEC_IRQ_NUM; i++) { 3635 if (fep->irq[i] > 0) { 3636 disable_irq(fep->irq[i]); 3637 fec_enet_interrupt(fep->irq[i], dev); 3638 enable_irq(fep->irq[i]); 3639 } 3640 } 3641 } 3642 #endif 3643 3644 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3645 netdev_features_t features) 3646 { 3647 struct fec_enet_private *fep = netdev_priv(netdev); 3648 netdev_features_t changed = features ^ netdev->features; 3649 3650 netdev->features = features; 3651 3652 /* Receive checksum has been changed */ 3653 if (changed & NETIF_F_RXCSUM) { 3654 if (features & NETIF_F_RXCSUM) 3655 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3656 else 3657 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3658 } 3659 } 3660 3661 static int fec_set_features(struct net_device *netdev, 3662 netdev_features_t features) 3663 { 3664 struct fec_enet_private *fep = netdev_priv(netdev); 3665 netdev_features_t changed = features ^ netdev->features; 3666 3667 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3668 napi_disable(&fep->napi); 3669 netif_tx_lock_bh(netdev); 3670 fec_stop(netdev); 3671 fec_enet_set_netdev_features(netdev, features); 3672 fec_restart(netdev); 3673 netif_tx_wake_all_queues(netdev); 3674 netif_tx_unlock_bh(netdev); 3675 napi_enable(&fep->napi); 3676 } else { 3677 fec_enet_set_netdev_features(netdev, features); 3678 } 3679 3680 return 0; 3681 } 3682 3683 static u16 fec_enet_get_raw_vlan_tci(struct sk_buff *skb) 3684 { 3685 struct vlan_ethhdr *vhdr; 3686 unsigned short vlan_TCI = 0; 3687 3688 if (skb->protocol == htons(ETH_P_ALL)) { 3689 vhdr = (struct vlan_ethhdr *)(skb->data); 3690 vlan_TCI = ntohs(vhdr->h_vlan_TCI); 3691 } 3692 3693 return vlan_TCI; 3694 } 3695 3696 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3697 struct net_device *sb_dev) 3698 { 3699 struct fec_enet_private *fep = netdev_priv(ndev); 3700 u16 vlan_tag; 3701 3702 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3703 return netdev_pick_tx(ndev, skb, NULL); 3704 3705 vlan_tag = fec_enet_get_raw_vlan_tci(skb); 3706 if (!vlan_tag) 3707 return vlan_tag; 3708 3709 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3710 } 3711 3712 static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf) 3713 { 3714 struct fec_enet_private *fep = netdev_priv(dev); 3715 bool is_run = netif_running(dev); 3716 struct bpf_prog *old_prog; 3717 3718 switch (bpf->command) { 3719 case XDP_SETUP_PROG: 3720 /* No need to support the SoCs that require to 3721 * do the frame swap because the performance wouldn't be 3722 * better than the skb mode. 3723 */ 3724 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 3725 return -EOPNOTSUPP; 3726 3727 if (!bpf->prog) 3728 xdp_features_clear_redirect_target(dev); 3729 3730 if (is_run) { 3731 napi_disable(&fep->napi); 3732 netif_tx_disable(dev); 3733 } 3734 3735 old_prog = xchg(&fep->xdp_prog, bpf->prog); 3736 if (old_prog) 3737 bpf_prog_put(old_prog); 3738 3739 fec_restart(dev); 3740 3741 if (is_run) { 3742 napi_enable(&fep->napi); 3743 netif_tx_start_all_queues(dev); 3744 } 3745 3746 if (bpf->prog) 3747 xdp_features_set_redirect_target(dev, false); 3748 3749 return 0; 3750 3751 case XDP_SETUP_XSK_POOL: 3752 return -EOPNOTSUPP; 3753 3754 default: 3755 return -EOPNOTSUPP; 3756 } 3757 } 3758 3759 static int 3760 fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index) 3761 { 3762 if (unlikely(index < 0)) 3763 return 0; 3764 3765 return (index % fep->num_tx_queues); 3766 } 3767 3768 static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep, 3769 struct fec_enet_priv_tx_q *txq, 3770 struct xdp_frame *frame) 3771 { 3772 unsigned int index, status, estatus; 3773 struct bufdesc *bdp; 3774 dma_addr_t dma_addr; 3775 int entries_free; 3776 3777 entries_free = fec_enet_get_free_txdesc_num(txq); 3778 if (entries_free < MAX_SKB_FRAGS + 1) { 3779 netdev_err_once(fep->netdev, "NOT enough BD for SG!\n"); 3780 return -EBUSY; 3781 } 3782 3783 /* Fill in a Tx ring entry */ 3784 bdp = txq->bd.cur; 3785 status = fec16_to_cpu(bdp->cbd_sc); 3786 status &= ~BD_ENET_TX_STATS; 3787 3788 index = fec_enet_get_bd_index(bdp, &txq->bd); 3789 3790 dma_addr = dma_map_single(&fep->pdev->dev, frame->data, 3791 frame->len, DMA_TO_DEVICE); 3792 if (dma_mapping_error(&fep->pdev->dev, dma_addr)) 3793 return -ENOMEM; 3794 3795 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 3796 if (fep->bufdesc_ex) 3797 estatus = BD_ENET_TX_INT; 3798 3799 bdp->cbd_bufaddr = cpu_to_fec32(dma_addr); 3800 bdp->cbd_datlen = cpu_to_fec16(frame->len); 3801 3802 if (fep->bufdesc_ex) { 3803 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3804 3805 if (fep->quirks & FEC_QUIRK_HAS_AVB) 3806 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 3807 3808 ebdp->cbd_bdu = 0; 3809 ebdp->cbd_esc = cpu_to_fec32(estatus); 3810 } 3811 3812 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO; 3813 txq->tx_buf[index].xdp = frame; 3814 3815 /* Make sure the updates to rest of the descriptor are performed before 3816 * transferring ownership. 3817 */ 3818 dma_wmb(); 3819 3820 /* Send it on its way. Tell FEC it's ready, interrupt when done, 3821 * it's the last BD of the frame, and to put the CRC on the end. 3822 */ 3823 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 3824 bdp->cbd_sc = cpu_to_fec16(status); 3825 3826 /* If this was the last BD in the ring, start at the beginning again. */ 3827 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3828 3829 /* Make sure the update to bdp are performed before txq->bd.cur. */ 3830 dma_wmb(); 3831 3832 txq->bd.cur = bdp; 3833 3834 /* Trigger transmission start */ 3835 writel(0, txq->bd.reg_desc_active); 3836 3837 return 0; 3838 } 3839 3840 static int fec_enet_xdp_xmit(struct net_device *dev, 3841 int num_frames, 3842 struct xdp_frame **frames, 3843 u32 flags) 3844 { 3845 struct fec_enet_private *fep = netdev_priv(dev); 3846 struct fec_enet_priv_tx_q *txq; 3847 int cpu = smp_processor_id(); 3848 unsigned int sent_frames = 0; 3849 struct netdev_queue *nq; 3850 unsigned int queue; 3851 int i; 3852 3853 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3854 txq = fep->tx_queue[queue]; 3855 nq = netdev_get_tx_queue(fep->netdev, queue); 3856 3857 __netif_tx_lock(nq, cpu); 3858 3859 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3860 txq_trans_cond_update(nq); 3861 for (i = 0; i < num_frames; i++) { 3862 if (fec_enet_txq_xmit_frame(fep, txq, frames[i]) < 0) 3863 break; 3864 sent_frames++; 3865 } 3866 3867 __netif_tx_unlock(nq); 3868 3869 return sent_frames; 3870 } 3871 3872 static int fec_hwtstamp_get(struct net_device *ndev, 3873 struct kernel_hwtstamp_config *config) 3874 { 3875 struct fec_enet_private *fep = netdev_priv(ndev); 3876 3877 if (!netif_running(ndev)) 3878 return -EINVAL; 3879 3880 if (!fep->bufdesc_ex) 3881 return -EOPNOTSUPP; 3882 3883 fec_ptp_get(ndev, config); 3884 3885 return 0; 3886 } 3887 3888 static int fec_hwtstamp_set(struct net_device *ndev, 3889 struct kernel_hwtstamp_config *config, 3890 struct netlink_ext_ack *extack) 3891 { 3892 struct fec_enet_private *fep = netdev_priv(ndev); 3893 3894 if (!netif_running(ndev)) 3895 return -EINVAL; 3896 3897 if (!fep->bufdesc_ex) 3898 return -EOPNOTSUPP; 3899 3900 return fec_ptp_set(ndev, config, extack); 3901 } 3902 3903 static const struct net_device_ops fec_netdev_ops = { 3904 .ndo_open = fec_enet_open, 3905 .ndo_stop = fec_enet_close, 3906 .ndo_start_xmit = fec_enet_start_xmit, 3907 .ndo_select_queue = fec_enet_select_queue, 3908 .ndo_set_rx_mode = set_multicast_list, 3909 .ndo_validate_addr = eth_validate_addr, 3910 .ndo_tx_timeout = fec_timeout, 3911 .ndo_set_mac_address = fec_set_mac_address, 3912 .ndo_eth_ioctl = phy_do_ioctl_running, 3913 #ifdef CONFIG_NET_POLL_CONTROLLER 3914 .ndo_poll_controller = fec_poll_controller, 3915 #endif 3916 .ndo_set_features = fec_set_features, 3917 .ndo_bpf = fec_enet_bpf, 3918 .ndo_xdp_xmit = fec_enet_xdp_xmit, 3919 .ndo_hwtstamp_get = fec_hwtstamp_get, 3920 .ndo_hwtstamp_set = fec_hwtstamp_set, 3921 }; 3922 3923 static const unsigned short offset_des_active_rxq[] = { 3924 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3925 }; 3926 3927 static const unsigned short offset_des_active_txq[] = { 3928 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3929 }; 3930 3931 /* 3932 * XXX: We need to clean up on failure exits here. 3933 * 3934 */ 3935 static int fec_enet_init(struct net_device *ndev) 3936 { 3937 struct fec_enet_private *fep = netdev_priv(ndev); 3938 struct bufdesc *cbd_base; 3939 dma_addr_t bd_dma; 3940 int bd_size; 3941 unsigned int i; 3942 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3943 sizeof(struct bufdesc); 3944 unsigned dsize_log2 = __fls(dsize); 3945 int ret; 3946 3947 WARN_ON(dsize != (1 << dsize_log2)); 3948 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 3949 fep->rx_align = 0xf; 3950 fep->tx_align = 0xf; 3951 #else 3952 fep->rx_align = 0x3; 3953 fep->tx_align = 0x3; 3954 #endif 3955 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 3956 fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 3957 fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT; 3958 fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT; 3959 3960 /* Check mask of the streaming and coherent API */ 3961 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 3962 if (ret < 0) { 3963 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 3964 return ret; 3965 } 3966 3967 ret = fec_enet_alloc_queue(ndev); 3968 if (ret) 3969 return ret; 3970 3971 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3972 3973 /* Allocate memory for buffer descriptors. */ 3974 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3975 GFP_KERNEL); 3976 if (!cbd_base) { 3977 ret = -ENOMEM; 3978 goto free_queue_mem; 3979 } 3980 3981 /* Get the Ethernet address */ 3982 ret = fec_get_mac(ndev); 3983 if (ret) 3984 goto free_queue_mem; 3985 3986 /* Set receive and transmit descriptor base. */ 3987 for (i = 0; i < fep->num_rx_queues; i++) { 3988 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3989 unsigned size = dsize * rxq->bd.ring_size; 3990 3991 rxq->bd.qid = i; 3992 rxq->bd.base = cbd_base; 3993 rxq->bd.cur = cbd_base; 3994 rxq->bd.dma = bd_dma; 3995 rxq->bd.dsize = dsize; 3996 rxq->bd.dsize_log2 = dsize_log2; 3997 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3998 bd_dma += size; 3999 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4000 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4001 } 4002 4003 for (i = 0; i < fep->num_tx_queues; i++) { 4004 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 4005 unsigned size = dsize * txq->bd.ring_size; 4006 4007 txq->bd.qid = i; 4008 txq->bd.base = cbd_base; 4009 txq->bd.cur = cbd_base; 4010 txq->bd.dma = bd_dma; 4011 txq->bd.dsize = dsize; 4012 txq->bd.dsize_log2 = dsize_log2; 4013 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 4014 bd_dma += size; 4015 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4016 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4017 } 4018 4019 4020 /* The FEC Ethernet specific entries in the device structure */ 4021 ndev->watchdog_timeo = TX_TIMEOUT; 4022 ndev->netdev_ops = &fec_netdev_ops; 4023 ndev->ethtool_ops = &fec_enet_ethtool_ops; 4024 4025 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 4026 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi); 4027 4028 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 4029 /* enable hw VLAN support */ 4030 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 4031 4032 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 4033 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS); 4034 4035 /* enable hw accelerator */ 4036 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 4037 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 4038 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 4039 } 4040 4041 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 4042 fep->tx_align = 0; 4043 fep->rx_align = 0x3f; 4044 } 4045 4046 ndev->hw_features = ndev->features; 4047 4048 if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME)) 4049 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 4050 NETDEV_XDP_ACT_REDIRECT; 4051 4052 fec_restart(ndev); 4053 4054 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 4055 fec_enet_clear_ethtool_stats(ndev); 4056 else 4057 fec_enet_update_ethtool_stats(ndev); 4058 4059 return 0; 4060 4061 free_queue_mem: 4062 fec_enet_free_queue(ndev); 4063 return ret; 4064 } 4065 4066 #ifdef CONFIG_OF 4067 static int fec_reset_phy(struct platform_device *pdev) 4068 { 4069 struct gpio_desc *phy_reset; 4070 int msec = 1, phy_post_delay = 0; 4071 struct device_node *np = pdev->dev.of_node; 4072 int err; 4073 4074 if (!np) 4075 return 0; 4076 4077 err = of_property_read_u32(np, "phy-reset-duration", &msec); 4078 /* A sane reset duration should not be longer than 1s */ 4079 if (!err && msec > 1000) 4080 msec = 1; 4081 4082 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 4083 /* valid reset duration should be less than 1s */ 4084 if (!err && phy_post_delay > 1000) 4085 return -EINVAL; 4086 4087 phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset", 4088 GPIOD_OUT_HIGH); 4089 if (IS_ERR(phy_reset)) 4090 return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset), 4091 "failed to get phy-reset-gpios\n"); 4092 4093 if (!phy_reset) 4094 return 0; 4095 4096 if (msec > 20) 4097 msleep(msec); 4098 else 4099 usleep_range(msec * 1000, msec * 1000 + 1000); 4100 4101 gpiod_set_value_cansleep(phy_reset, 0); 4102 4103 if (!phy_post_delay) 4104 return 0; 4105 4106 if (phy_post_delay > 20) 4107 msleep(phy_post_delay); 4108 else 4109 usleep_range(phy_post_delay * 1000, 4110 phy_post_delay * 1000 + 1000); 4111 4112 return 0; 4113 } 4114 #else /* CONFIG_OF */ 4115 static int fec_reset_phy(struct platform_device *pdev) 4116 { 4117 /* 4118 * In case of platform probe, the reset has been done 4119 * by machine code. 4120 */ 4121 return 0; 4122 } 4123 #endif /* CONFIG_OF */ 4124 4125 static void 4126 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 4127 { 4128 struct device_node *np = pdev->dev.of_node; 4129 4130 *num_tx = *num_rx = 1; 4131 4132 if (!np || !of_device_is_available(np)) 4133 return; 4134 4135 /* parse the num of tx and rx queues */ 4136 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 4137 4138 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 4139 4140 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 4141 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 4142 *num_tx); 4143 *num_tx = 1; 4144 return; 4145 } 4146 4147 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 4148 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 4149 *num_rx); 4150 *num_rx = 1; 4151 return; 4152 } 4153 4154 } 4155 4156 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 4157 { 4158 int irq_cnt = platform_irq_count(pdev); 4159 4160 if (irq_cnt > FEC_IRQ_NUM) 4161 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 4162 else if (irq_cnt == 2) 4163 irq_cnt = 1; /* last for pps */ 4164 else if (irq_cnt <= 0) 4165 irq_cnt = 1; /* At least 1 irq is needed */ 4166 return irq_cnt; 4167 } 4168 4169 static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 4170 { 4171 struct net_device *ndev = platform_get_drvdata(pdev); 4172 struct fec_enet_private *fep = netdev_priv(ndev); 4173 4174 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 4175 fep->wake_irq = fep->irq[2]; 4176 else 4177 fep->wake_irq = fep->irq[0]; 4178 } 4179 4180 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 4181 struct device_node *np) 4182 { 4183 struct device_node *gpr_np; 4184 u32 out_val[3]; 4185 int ret = 0; 4186 4187 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 4188 if (!gpr_np) 4189 return 0; 4190 4191 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 4192 ARRAY_SIZE(out_val)); 4193 if (ret) { 4194 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 4195 goto out; 4196 } 4197 4198 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 4199 if (IS_ERR(fep->stop_gpr.gpr)) { 4200 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 4201 ret = PTR_ERR(fep->stop_gpr.gpr); 4202 fep->stop_gpr.gpr = NULL; 4203 goto out; 4204 } 4205 4206 fep->stop_gpr.reg = out_val[1]; 4207 fep->stop_gpr.bit = out_val[2]; 4208 4209 out: 4210 of_node_put(gpr_np); 4211 4212 return ret; 4213 } 4214 4215 static int 4216 fec_probe(struct platform_device *pdev) 4217 { 4218 struct fec_enet_private *fep; 4219 struct fec_platform_data *pdata; 4220 phy_interface_t interface; 4221 struct net_device *ndev; 4222 int i, irq, ret = 0; 4223 const struct of_device_id *of_id; 4224 static int dev_id; 4225 struct device_node *np = pdev->dev.of_node, *phy_node; 4226 int num_tx_qs; 4227 int num_rx_qs; 4228 char irq_name[8]; 4229 int irq_cnt; 4230 struct fec_devinfo *dev_info; 4231 4232 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 4233 4234 /* Init network device */ 4235 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 4236 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 4237 if (!ndev) 4238 return -ENOMEM; 4239 4240 SET_NETDEV_DEV(ndev, &pdev->dev); 4241 4242 /* setup board info structure */ 4243 fep = netdev_priv(ndev); 4244 4245 of_id = of_match_device(fec_dt_ids, &pdev->dev); 4246 if (of_id) 4247 pdev->id_entry = of_id->data; 4248 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; 4249 if (dev_info) 4250 fep->quirks = dev_info->quirks; 4251 4252 fep->netdev = ndev; 4253 fep->num_rx_queues = num_rx_qs; 4254 fep->num_tx_queues = num_tx_qs; 4255 4256 #if !defined(CONFIG_M5272) 4257 /* default enable pause frame auto negotiation */ 4258 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 4259 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 4260 #endif 4261 4262 /* Select default pin state */ 4263 pinctrl_pm_select_default_state(&pdev->dev); 4264 4265 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 4266 if (IS_ERR(fep->hwp)) { 4267 ret = PTR_ERR(fep->hwp); 4268 goto failed_ioremap; 4269 } 4270 4271 fep->pdev = pdev; 4272 fep->dev_id = dev_id++; 4273 4274 platform_set_drvdata(pdev, ndev); 4275 4276 if ((of_machine_is_compatible("fsl,imx6q") || 4277 of_machine_is_compatible("fsl,imx6dl")) && 4278 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 4279 fep->quirks |= FEC_QUIRK_ERR006687; 4280 4281 ret = fec_enet_ipc_handle_init(fep); 4282 if (ret) 4283 goto failed_ipc_init; 4284 4285 if (of_property_read_bool(np, "fsl,magic-packet")) 4286 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 4287 4288 ret = fec_enet_init_stop_mode(fep, np); 4289 if (ret) 4290 goto failed_stop_mode; 4291 4292 phy_node = of_parse_phandle(np, "phy-handle", 0); 4293 if (!phy_node && of_phy_is_fixed_link(np)) { 4294 ret = of_phy_register_fixed_link(np); 4295 if (ret < 0) { 4296 dev_err(&pdev->dev, 4297 "broken fixed-link specification\n"); 4298 goto failed_phy; 4299 } 4300 phy_node = of_node_get(np); 4301 } 4302 fep->phy_node = phy_node; 4303 4304 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 4305 if (ret) { 4306 pdata = dev_get_platdata(&pdev->dev); 4307 if (pdata) 4308 fep->phy_interface = pdata->phy; 4309 else 4310 fep->phy_interface = PHY_INTERFACE_MODE_MII; 4311 } else { 4312 fep->phy_interface = interface; 4313 } 4314 4315 ret = fec_enet_parse_rgmii_delay(fep, np); 4316 if (ret) 4317 goto failed_rgmii_delay; 4318 4319 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 4320 if (IS_ERR(fep->clk_ipg)) { 4321 ret = PTR_ERR(fep->clk_ipg); 4322 goto failed_clk; 4323 } 4324 4325 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 4326 if (IS_ERR(fep->clk_ahb)) { 4327 ret = PTR_ERR(fep->clk_ahb); 4328 goto failed_clk; 4329 } 4330 4331 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 4332 4333 /* enet_out is optional, depends on board */ 4334 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out"); 4335 if (IS_ERR(fep->clk_enet_out)) { 4336 ret = PTR_ERR(fep->clk_enet_out); 4337 goto failed_clk; 4338 } 4339 4340 fep->ptp_clk_on = false; 4341 mutex_init(&fep->ptp_clk_mutex); 4342 4343 /* clk_ref is optional, depends on board */ 4344 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref"); 4345 if (IS_ERR(fep->clk_ref)) { 4346 ret = PTR_ERR(fep->clk_ref); 4347 goto failed_clk; 4348 } 4349 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 4350 4351 /* clk_2x_txclk is optional, depends on board */ 4352 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 4353 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 4354 if (IS_ERR(fep->clk_2x_txclk)) 4355 fep->clk_2x_txclk = NULL; 4356 } 4357 4358 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 4359 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 4360 if (IS_ERR(fep->clk_ptp)) { 4361 fep->clk_ptp = NULL; 4362 fep->bufdesc_ex = false; 4363 } 4364 4365 ret = fec_enet_clk_enable(ndev, true); 4366 if (ret) 4367 goto failed_clk; 4368 4369 ret = clk_prepare_enable(fep->clk_ipg); 4370 if (ret) 4371 goto failed_clk_ipg; 4372 ret = clk_prepare_enable(fep->clk_ahb); 4373 if (ret) 4374 goto failed_clk_ahb; 4375 4376 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 4377 if (!IS_ERR(fep->reg_phy)) { 4378 ret = regulator_enable(fep->reg_phy); 4379 if (ret) { 4380 dev_err(&pdev->dev, 4381 "Failed to enable phy regulator: %d\n", ret); 4382 goto failed_regulator; 4383 } 4384 } else { 4385 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 4386 ret = -EPROBE_DEFER; 4387 goto failed_regulator; 4388 } 4389 fep->reg_phy = NULL; 4390 } 4391 4392 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 4393 pm_runtime_use_autosuspend(&pdev->dev); 4394 pm_runtime_get_noresume(&pdev->dev); 4395 pm_runtime_set_active(&pdev->dev); 4396 pm_runtime_enable(&pdev->dev); 4397 4398 ret = fec_reset_phy(pdev); 4399 if (ret) 4400 goto failed_reset; 4401 4402 irq_cnt = fec_enet_get_irq_cnt(pdev); 4403 if (fep->bufdesc_ex) 4404 fec_ptp_init(pdev, irq_cnt); 4405 4406 ret = fec_enet_init(ndev); 4407 if (ret) 4408 goto failed_init; 4409 4410 for (i = 0; i < irq_cnt; i++) { 4411 snprintf(irq_name, sizeof(irq_name), "int%d", i); 4412 irq = platform_get_irq_byname_optional(pdev, irq_name); 4413 if (irq < 0) 4414 irq = platform_get_irq(pdev, i); 4415 if (irq < 0) { 4416 ret = irq; 4417 goto failed_irq; 4418 } 4419 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 4420 0, pdev->name, ndev); 4421 if (ret) 4422 goto failed_irq; 4423 4424 fep->irq[i] = irq; 4425 } 4426 4427 /* Decide which interrupt line is wakeup capable */ 4428 fec_enet_get_wakeup_irq(pdev); 4429 4430 ret = fec_enet_mii_init(pdev); 4431 if (ret) 4432 goto failed_mii_init; 4433 4434 /* Carrier starts down, phylib will bring it up */ 4435 netif_carrier_off(ndev); 4436 fec_enet_clk_enable(ndev, false); 4437 pinctrl_pm_select_sleep_state(&pdev->dev); 4438 4439 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN; 4440 4441 ret = register_netdev(ndev); 4442 if (ret) 4443 goto failed_register; 4444 4445 device_init_wakeup(&ndev->dev, fep->wol_flag & 4446 FEC_WOL_HAS_MAGIC_PACKET); 4447 4448 if (fep->bufdesc_ex && fep->ptp_clock) 4449 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 4450 4451 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 4452 4453 pm_runtime_mark_last_busy(&pdev->dev); 4454 pm_runtime_put_autosuspend(&pdev->dev); 4455 4456 return 0; 4457 4458 failed_register: 4459 fec_enet_mii_remove(fep); 4460 failed_mii_init: 4461 failed_irq: 4462 failed_init: 4463 fec_ptp_stop(pdev); 4464 failed_reset: 4465 pm_runtime_put_noidle(&pdev->dev); 4466 pm_runtime_disable(&pdev->dev); 4467 if (fep->reg_phy) 4468 regulator_disable(fep->reg_phy); 4469 failed_regulator: 4470 clk_disable_unprepare(fep->clk_ahb); 4471 failed_clk_ahb: 4472 clk_disable_unprepare(fep->clk_ipg); 4473 failed_clk_ipg: 4474 fec_enet_clk_enable(ndev, false); 4475 failed_clk: 4476 failed_rgmii_delay: 4477 if (of_phy_is_fixed_link(np)) 4478 of_phy_deregister_fixed_link(np); 4479 of_node_put(phy_node); 4480 failed_stop_mode: 4481 failed_ipc_init: 4482 failed_phy: 4483 dev_id--; 4484 failed_ioremap: 4485 free_netdev(ndev); 4486 4487 return ret; 4488 } 4489 4490 static void 4491 fec_drv_remove(struct platform_device *pdev) 4492 { 4493 struct net_device *ndev = platform_get_drvdata(pdev); 4494 struct fec_enet_private *fep = netdev_priv(ndev); 4495 struct device_node *np = pdev->dev.of_node; 4496 int ret; 4497 4498 ret = pm_runtime_get_sync(&pdev->dev); 4499 if (ret < 0) 4500 dev_err(&pdev->dev, 4501 "Failed to resume device in remove callback (%pe)\n", 4502 ERR_PTR(ret)); 4503 4504 cancel_work_sync(&fep->tx_timeout_work); 4505 fec_ptp_stop(pdev); 4506 unregister_netdev(ndev); 4507 fec_enet_mii_remove(fep); 4508 if (fep->reg_phy) 4509 regulator_disable(fep->reg_phy); 4510 4511 if (of_phy_is_fixed_link(np)) 4512 of_phy_deregister_fixed_link(np); 4513 of_node_put(fep->phy_node); 4514 4515 /* After pm_runtime_get_sync() failed, the clks are still off, so skip 4516 * disabling them again. 4517 */ 4518 if (ret >= 0) { 4519 clk_disable_unprepare(fep->clk_ahb); 4520 clk_disable_unprepare(fep->clk_ipg); 4521 } 4522 pm_runtime_put_noidle(&pdev->dev); 4523 pm_runtime_disable(&pdev->dev); 4524 4525 free_netdev(ndev); 4526 } 4527 4528 static int __maybe_unused fec_suspend(struct device *dev) 4529 { 4530 struct net_device *ndev = dev_get_drvdata(dev); 4531 struct fec_enet_private *fep = netdev_priv(ndev); 4532 int ret; 4533 4534 rtnl_lock(); 4535 if (netif_running(ndev)) { 4536 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4537 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4538 phy_stop(ndev->phydev); 4539 napi_disable(&fep->napi); 4540 netif_tx_lock_bh(ndev); 4541 netif_device_detach(ndev); 4542 netif_tx_unlock_bh(ndev); 4543 fec_stop(ndev); 4544 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4545 fec_irqs_disable(ndev); 4546 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4547 } else { 4548 fec_irqs_disable_except_wakeup(ndev); 4549 if (fep->wake_irq > 0) { 4550 disable_irq(fep->wake_irq); 4551 enable_irq_wake(fep->wake_irq); 4552 } 4553 fec_enet_stop_mode(fep, true); 4554 } 4555 /* It's safe to disable clocks since interrupts are masked */ 4556 fec_enet_clk_enable(ndev, false); 4557 4558 fep->rpm_active = !pm_runtime_status_suspended(dev); 4559 if (fep->rpm_active) { 4560 ret = pm_runtime_force_suspend(dev); 4561 if (ret < 0) { 4562 rtnl_unlock(); 4563 return ret; 4564 } 4565 } 4566 } 4567 rtnl_unlock(); 4568 4569 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4570 regulator_disable(fep->reg_phy); 4571 4572 /* SOC supply clock to phy, when clock is disabled, phy link down 4573 * SOC control phy regulator, when regulator is disabled, phy link down 4574 */ 4575 if (fep->clk_enet_out || fep->reg_phy) 4576 fep->link = 0; 4577 4578 return 0; 4579 } 4580 4581 static int __maybe_unused fec_resume(struct device *dev) 4582 { 4583 struct net_device *ndev = dev_get_drvdata(dev); 4584 struct fec_enet_private *fep = netdev_priv(ndev); 4585 int ret; 4586 int val; 4587 4588 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4589 ret = regulator_enable(fep->reg_phy); 4590 if (ret) 4591 return ret; 4592 } 4593 4594 rtnl_lock(); 4595 if (netif_running(ndev)) { 4596 if (fep->rpm_active) 4597 pm_runtime_force_resume(dev); 4598 4599 ret = fec_enet_clk_enable(ndev, true); 4600 if (ret) { 4601 rtnl_unlock(); 4602 goto failed_clk; 4603 } 4604 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4605 fec_enet_stop_mode(fep, false); 4606 if (fep->wake_irq) { 4607 disable_irq_wake(fep->wake_irq); 4608 enable_irq(fep->wake_irq); 4609 } 4610 4611 val = readl(fep->hwp + FEC_ECNTRL); 4612 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4613 writel(val, fep->hwp + FEC_ECNTRL); 4614 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4615 } else { 4616 pinctrl_pm_select_default_state(&fep->pdev->dev); 4617 } 4618 fec_restart(ndev); 4619 netif_tx_lock_bh(ndev); 4620 netif_device_attach(ndev); 4621 netif_tx_unlock_bh(ndev); 4622 napi_enable(&fep->napi); 4623 phy_init_hw(ndev->phydev); 4624 phy_start(ndev->phydev); 4625 } 4626 rtnl_unlock(); 4627 4628 return 0; 4629 4630 failed_clk: 4631 if (fep->reg_phy) 4632 regulator_disable(fep->reg_phy); 4633 return ret; 4634 } 4635 4636 static int __maybe_unused fec_runtime_suspend(struct device *dev) 4637 { 4638 struct net_device *ndev = dev_get_drvdata(dev); 4639 struct fec_enet_private *fep = netdev_priv(ndev); 4640 4641 clk_disable_unprepare(fep->clk_ahb); 4642 clk_disable_unprepare(fep->clk_ipg); 4643 4644 return 0; 4645 } 4646 4647 static int __maybe_unused fec_runtime_resume(struct device *dev) 4648 { 4649 struct net_device *ndev = dev_get_drvdata(dev); 4650 struct fec_enet_private *fep = netdev_priv(ndev); 4651 int ret; 4652 4653 ret = clk_prepare_enable(fep->clk_ahb); 4654 if (ret) 4655 return ret; 4656 ret = clk_prepare_enable(fep->clk_ipg); 4657 if (ret) 4658 goto failed_clk_ipg; 4659 4660 return 0; 4661 4662 failed_clk_ipg: 4663 clk_disable_unprepare(fep->clk_ahb); 4664 return ret; 4665 } 4666 4667 static const struct dev_pm_ops fec_pm_ops = { 4668 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4669 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4670 }; 4671 4672 static struct platform_driver fec_driver = { 4673 .driver = { 4674 .name = DRIVER_NAME, 4675 .pm = &fec_pm_ops, 4676 .of_match_table = fec_dt_ids, 4677 .suppress_bind_attrs = true, 4678 }, 4679 .id_table = fec_devtype, 4680 .probe = fec_probe, 4681 .remove_new = fec_drv_remove, 4682 }; 4683 4684 module_platform_driver(fec_driver); 4685 4686 MODULE_LICENSE("GPL"); 4687