1 /* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 * 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/string.h> 27 #include <linux/ptrace.h> 28 #include <linux/errno.h> 29 #include <linux/ioport.h> 30 #include <linux/slab.h> 31 #include <linux/interrupt.h> 32 #include <linux/delay.h> 33 #include <linux/netdevice.h> 34 #include <linux/etherdevice.h> 35 #include <linux/skbuff.h> 36 #include <linux/in.h> 37 #include <linux/ip.h> 38 #include <net/ip.h> 39 #include <net/tso.h> 40 #include <linux/tcp.h> 41 #include <linux/udp.h> 42 #include <linux/icmp.h> 43 #include <linux/spinlock.h> 44 #include <linux/workqueue.h> 45 #include <linux/bitops.h> 46 #include <linux/io.h> 47 #include <linux/irq.h> 48 #include <linux/clk.h> 49 #include <linux/platform_device.h> 50 #include <linux/phy.h> 51 #include <linux/fec.h> 52 #include <linux/of.h> 53 #include <linux/of_device.h> 54 #include <linux/of_gpio.h> 55 #include <linux/of_net.h> 56 #include <linux/regulator/consumer.h> 57 #include <linux/if_vlan.h> 58 #include <linux/pinctrl/consumer.h> 59 60 #include <asm/cacheflush.h> 61 62 #include "fec.h" 63 64 static void set_multicast_list(struct net_device *ndev); 65 66 #if defined(CONFIG_ARM) 67 #define FEC_ALIGNMENT 0xf 68 #else 69 #define FEC_ALIGNMENT 0x3 70 #endif 71 72 #define DRIVER_NAME "fec" 73 74 /* Pause frame feild and FIFO threshold */ 75 #define FEC_ENET_FCE (1 << 5) 76 #define FEC_ENET_RSEM_V 0x84 77 #define FEC_ENET_RSFL_V 16 78 #define FEC_ENET_RAEM_V 0x8 79 #define FEC_ENET_RAFL_V 0x8 80 #define FEC_ENET_OPD_V 0xFFF0 81 82 /* Controller is ENET-MAC */ 83 #define FEC_QUIRK_ENET_MAC (1 << 0) 84 /* Controller needs driver to swap frame */ 85 #define FEC_QUIRK_SWAP_FRAME (1 << 1) 86 /* Controller uses gasket */ 87 #define FEC_QUIRK_USE_GASKET (1 << 2) 88 /* Controller has GBIT support */ 89 #define FEC_QUIRK_HAS_GBIT (1 << 3) 90 /* Controller has extend desc buffer */ 91 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) 92 /* Controller has hardware checksum support */ 93 #define FEC_QUIRK_HAS_CSUM (1 << 5) 94 /* Controller has hardware vlan support */ 95 #define FEC_QUIRK_HAS_VLAN (1 << 6) 96 /* ENET IP errata ERR006358 97 * 98 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously 99 * detected as not set during a prior frame transmission, then the 100 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs 101 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in 102 * frames not being transmitted until there is a 0-to-1 transition on 103 * ENET_TDAR[TDAR]. 104 */ 105 #define FEC_QUIRK_ERR006358 (1 << 7) 106 107 static struct platform_device_id fec_devtype[] = { 108 { 109 /* keep it for coldfire */ 110 .name = DRIVER_NAME, 111 .driver_data = 0, 112 }, { 113 .name = "imx25-fec", 114 .driver_data = FEC_QUIRK_USE_GASKET, 115 }, { 116 .name = "imx27-fec", 117 .driver_data = 0, 118 }, { 119 .name = "imx28-fec", 120 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, 121 }, { 122 .name = "imx6q-fec", 123 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 124 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 125 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358, 126 }, { 127 .name = "mvf600-fec", 128 .driver_data = FEC_QUIRK_ENET_MAC, 129 }, { 130 /* sentinel */ 131 } 132 }; 133 MODULE_DEVICE_TABLE(platform, fec_devtype); 134 135 enum imx_fec_type { 136 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 137 IMX27_FEC, /* runs on i.mx27/35/51 */ 138 IMX28_FEC, 139 IMX6Q_FEC, 140 MVF600_FEC, 141 }; 142 143 static const struct of_device_id fec_dt_ids[] = { 144 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 145 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 146 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 147 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 148 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 149 { /* sentinel */ } 150 }; 151 MODULE_DEVICE_TABLE(of, fec_dt_ids); 152 153 static unsigned char macaddr[ETH_ALEN]; 154 module_param_array(macaddr, byte, NULL, 0); 155 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 156 157 #if defined(CONFIG_M5272) 158 /* 159 * Some hardware gets it MAC address out of local flash memory. 160 * if this is non-zero then assume it is the address to get MAC from. 161 */ 162 #if defined(CONFIG_NETtel) 163 #define FEC_FLASHMAC 0xf0006006 164 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 165 #define FEC_FLASHMAC 0xf0006000 166 #elif defined(CONFIG_CANCam) 167 #define FEC_FLASHMAC 0xf0020000 168 #elif defined (CONFIG_M5272C3) 169 #define FEC_FLASHMAC (0xffe04000 + 4) 170 #elif defined(CONFIG_MOD5272) 171 #define FEC_FLASHMAC 0xffc0406b 172 #else 173 #define FEC_FLASHMAC 0 174 #endif 175 #endif /* CONFIG_M5272 */ 176 177 /* Interrupt events/masks. */ 178 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ 179 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ 180 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ 181 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ 182 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ 183 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ 184 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ 185 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ 186 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ 187 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ 188 189 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) 190 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) 191 192 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 193 */ 194 #define PKT_MAXBUF_SIZE 1522 195 #define PKT_MINBUF_SIZE 64 196 #define PKT_MAXBLR_SIZE 1536 197 198 /* FEC receive acceleration */ 199 #define FEC_RACC_IPDIS (1 << 1) 200 #define FEC_RACC_PRODIS (1 << 2) 201 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 202 203 /* 204 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 205 * size bits. Other FEC hardware does not, so we need to take that into 206 * account when setting it. 207 */ 208 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 209 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 210 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 211 #else 212 #define OPT_FRAME_SIZE 0 213 #endif 214 215 /* FEC MII MMFR bits definition */ 216 #define FEC_MMFR_ST (1 << 30) 217 #define FEC_MMFR_OP_READ (2 << 28) 218 #define FEC_MMFR_OP_WRITE (1 << 28) 219 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 220 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 221 #define FEC_MMFR_TA (2 << 16) 222 #define FEC_MMFR_DATA(v) (v & 0xffff) 223 224 #define FEC_MII_TIMEOUT 30000 /* us */ 225 226 /* Transmitter timeout */ 227 #define TX_TIMEOUT (2 * HZ) 228 229 #define FEC_PAUSE_FLAG_AUTONEG 0x1 230 #define FEC_PAUSE_FLAG_ENABLE 0x2 231 232 #define TSO_HEADER_SIZE 128 233 /* Max number of allowed TCP segments for software TSO */ 234 #define FEC_MAX_TSO_SEGS 100 235 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 236 237 #define IS_TSO_HEADER(txq, addr) \ 238 ((addr >= txq->tso_hdrs_dma) && \ 239 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE)) 240 241 static int mii_cnt; 242 243 static inline 244 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep) 245 { 246 struct bufdesc *new_bd = bdp + 1; 247 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1; 248 struct bufdesc_ex *ex_base; 249 struct bufdesc *base; 250 int ring_size; 251 252 if (bdp >= fep->tx_bd_base) { 253 base = fep->tx_bd_base; 254 ring_size = fep->tx_ring_size; 255 ex_base = (struct bufdesc_ex *)fep->tx_bd_base; 256 } else { 257 base = fep->rx_bd_base; 258 ring_size = fep->rx_ring_size; 259 ex_base = (struct bufdesc_ex *)fep->rx_bd_base; 260 } 261 262 if (fep->bufdesc_ex) 263 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ? 264 ex_base : ex_new_bd); 265 else 266 return (new_bd >= (base + ring_size)) ? 267 base : new_bd; 268 } 269 270 static inline 271 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep) 272 { 273 struct bufdesc *new_bd = bdp - 1; 274 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1; 275 struct bufdesc_ex *ex_base; 276 struct bufdesc *base; 277 int ring_size; 278 279 if (bdp >= fep->tx_bd_base) { 280 base = fep->tx_bd_base; 281 ring_size = fep->tx_ring_size; 282 ex_base = (struct bufdesc_ex *)fep->tx_bd_base; 283 } else { 284 base = fep->rx_bd_base; 285 ring_size = fep->rx_ring_size; 286 ex_base = (struct bufdesc_ex *)fep->rx_bd_base; 287 } 288 289 if (fep->bufdesc_ex) 290 return (struct bufdesc *)((ex_new_bd < ex_base) ? 291 (ex_new_bd + ring_size) : ex_new_bd); 292 else 293 return (new_bd < base) ? (new_bd + ring_size) : new_bd; 294 } 295 296 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp, 297 struct fec_enet_private *fep) 298 { 299 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size; 300 } 301 302 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep) 303 { 304 int entries; 305 306 entries = ((const char *)fep->dirty_tx - 307 (const char *)fep->cur_tx) / fep->bufdesc_size - 1; 308 309 return entries > 0 ? entries : entries + fep->tx_ring_size; 310 } 311 312 static void *swap_buffer(void *bufaddr, int len) 313 { 314 int i; 315 unsigned int *buf = bufaddr; 316 317 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++) 318 *buf = cpu_to_be32(*buf); 319 320 return bufaddr; 321 } 322 323 static void fec_dump(struct net_device *ndev) 324 { 325 struct fec_enet_private *fep = netdev_priv(ndev); 326 struct bufdesc *bdp = fep->tx_bd_base; 327 unsigned int index = 0; 328 329 netdev_info(ndev, "TX ring dump\n"); 330 pr_info("Nr SC addr len SKB\n"); 331 332 do { 333 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n", 334 index, 335 bdp == fep->cur_tx ? 'S' : ' ', 336 bdp == fep->dirty_tx ? 'H' : ' ', 337 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen, 338 fep->tx_skbuff[index]); 339 bdp = fec_enet_get_nextdesc(bdp, fep); 340 index++; 341 } while (bdp != fep->tx_bd_base); 342 } 343 344 static inline bool is_ipv4_pkt(struct sk_buff *skb) 345 { 346 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 347 } 348 349 static int 350 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 351 { 352 /* Only run for packets requiring a checksum. */ 353 if (skb->ip_summed != CHECKSUM_PARTIAL) 354 return 0; 355 356 if (unlikely(skb_cow_head(skb, 0))) 357 return -1; 358 359 if (is_ipv4_pkt(skb)) 360 ip_hdr(skb)->check = 0; 361 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 362 363 return 0; 364 } 365 366 static int 367 fec_enet_txq_submit_frag_skb(struct sk_buff *skb, struct net_device *ndev) 368 { 369 struct fec_enet_private *fep = netdev_priv(ndev); 370 const struct platform_device_id *id_entry = 371 platform_get_device_id(fep->pdev); 372 struct bufdesc *bdp = fep->cur_tx; 373 struct bufdesc_ex *ebdp; 374 int nr_frags = skb_shinfo(skb)->nr_frags; 375 int frag, frag_len; 376 unsigned short status; 377 unsigned int estatus = 0; 378 skb_frag_t *this_frag; 379 unsigned int index; 380 void *bufaddr; 381 dma_addr_t addr; 382 int i; 383 384 for (frag = 0; frag < nr_frags; frag++) { 385 this_frag = &skb_shinfo(skb)->frags[frag]; 386 bdp = fec_enet_get_nextdesc(bdp, fep); 387 ebdp = (struct bufdesc_ex *)bdp; 388 389 status = bdp->cbd_sc; 390 status &= ~BD_ENET_TX_STATS; 391 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 392 frag_len = skb_shinfo(skb)->frags[frag].size; 393 394 /* Handle the last BD specially */ 395 if (frag == nr_frags - 1) { 396 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 397 if (fep->bufdesc_ex) { 398 estatus |= BD_ENET_TX_INT; 399 if (unlikely(skb_shinfo(skb)->tx_flags & 400 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 401 estatus |= BD_ENET_TX_TS; 402 } 403 } 404 405 if (fep->bufdesc_ex) { 406 if (skb->ip_summed == CHECKSUM_PARTIAL) 407 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 408 ebdp->cbd_bdu = 0; 409 ebdp->cbd_esc = estatus; 410 } 411 412 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset; 413 414 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep); 415 if (((unsigned long) bufaddr) & FEC_ALIGNMENT || 416 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) { 417 memcpy(fep->tx_bounce[index], bufaddr, frag_len); 418 bufaddr = fep->tx_bounce[index]; 419 420 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 421 swap_buffer(bufaddr, frag_len); 422 } 423 424 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 425 DMA_TO_DEVICE); 426 if (dma_mapping_error(&fep->pdev->dev, addr)) { 427 dev_kfree_skb_any(skb); 428 if (net_ratelimit()) 429 netdev_err(ndev, "Tx DMA memory map failed\n"); 430 goto dma_mapping_error; 431 } 432 433 bdp->cbd_bufaddr = addr; 434 bdp->cbd_datlen = frag_len; 435 bdp->cbd_sc = status; 436 } 437 438 fep->cur_tx = bdp; 439 440 return 0; 441 442 dma_mapping_error: 443 bdp = fep->cur_tx; 444 for (i = 0; i < frag; i++) { 445 bdp = fec_enet_get_nextdesc(bdp, fep); 446 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 447 bdp->cbd_datlen, DMA_TO_DEVICE); 448 } 449 return NETDEV_TX_OK; 450 } 451 452 static int fec_enet_txq_submit_skb(struct sk_buff *skb, struct net_device *ndev) 453 { 454 struct fec_enet_private *fep = netdev_priv(ndev); 455 const struct platform_device_id *id_entry = 456 platform_get_device_id(fep->pdev); 457 int nr_frags = skb_shinfo(skb)->nr_frags; 458 struct bufdesc *bdp, *last_bdp; 459 void *bufaddr; 460 dma_addr_t addr; 461 unsigned short status; 462 unsigned short buflen; 463 unsigned int estatus = 0; 464 unsigned int index; 465 int entries_free; 466 int ret; 467 468 entries_free = fec_enet_get_free_txdesc_num(fep); 469 if (entries_free < MAX_SKB_FRAGS + 1) { 470 dev_kfree_skb_any(skb); 471 if (net_ratelimit()) 472 netdev_err(ndev, "NOT enough BD for SG!\n"); 473 return NETDEV_TX_OK; 474 } 475 476 /* Protocol checksum off-load for TCP and UDP. */ 477 if (fec_enet_clear_csum(skb, ndev)) { 478 dev_kfree_skb_any(skb); 479 return NETDEV_TX_OK; 480 } 481 482 /* Fill in a Tx ring entry */ 483 bdp = fep->cur_tx; 484 status = bdp->cbd_sc; 485 status &= ~BD_ENET_TX_STATS; 486 487 /* Set buffer length and buffer pointer */ 488 bufaddr = skb->data; 489 buflen = skb_headlen(skb); 490 491 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep); 492 if (((unsigned long) bufaddr) & FEC_ALIGNMENT || 493 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) { 494 memcpy(fep->tx_bounce[index], skb->data, buflen); 495 bufaddr = fep->tx_bounce[index]; 496 497 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 498 swap_buffer(bufaddr, buflen); 499 } 500 501 /* Push the data cache so the CPM does not get stale memory data. */ 502 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 503 if (dma_mapping_error(&fep->pdev->dev, addr)) { 504 dev_kfree_skb_any(skb); 505 if (net_ratelimit()) 506 netdev_err(ndev, "Tx DMA memory map failed\n"); 507 return NETDEV_TX_OK; 508 } 509 510 if (nr_frags) { 511 ret = fec_enet_txq_submit_frag_skb(skb, ndev); 512 if (ret) 513 return ret; 514 } else { 515 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 516 if (fep->bufdesc_ex) { 517 estatus = BD_ENET_TX_INT; 518 if (unlikely(skb_shinfo(skb)->tx_flags & 519 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 520 estatus |= BD_ENET_TX_TS; 521 } 522 } 523 524 if (fep->bufdesc_ex) { 525 526 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 527 528 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 529 fep->hwts_tx_en)) 530 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 531 532 if (skb->ip_summed == CHECKSUM_PARTIAL) 533 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 534 535 ebdp->cbd_bdu = 0; 536 ebdp->cbd_esc = estatus; 537 } 538 539 last_bdp = fep->cur_tx; 540 index = fec_enet_get_bd_index(fep->tx_bd_base, last_bdp, fep); 541 /* Save skb pointer */ 542 fep->tx_skbuff[index] = skb; 543 544 bdp->cbd_datlen = buflen; 545 bdp->cbd_bufaddr = addr; 546 547 /* Send it on its way. Tell FEC it's ready, interrupt when done, 548 * it's the last BD of the frame, and to put the CRC on the end. 549 */ 550 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 551 bdp->cbd_sc = status; 552 553 /* If this was the last BD in the ring, start at the beginning again. */ 554 bdp = fec_enet_get_nextdesc(last_bdp, fep); 555 556 skb_tx_timestamp(skb); 557 558 fep->cur_tx = bdp; 559 560 /* Trigger transmission start */ 561 writel(0, fep->hwp + FEC_X_DES_ACTIVE); 562 563 return 0; 564 } 565 566 static int 567 fec_enet_txq_put_data_tso(struct sk_buff *skb, struct net_device *ndev, 568 struct bufdesc *bdp, int index, char *data, 569 int size, bool last_tcp, bool is_last) 570 { 571 struct fec_enet_private *fep = netdev_priv(ndev); 572 const struct platform_device_id *id_entry = 573 platform_get_device_id(fep->pdev); 574 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 575 unsigned short status; 576 unsigned int estatus = 0; 577 dma_addr_t addr; 578 579 status = bdp->cbd_sc; 580 status &= ~BD_ENET_TX_STATS; 581 582 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 583 584 if (((unsigned long) data) & FEC_ALIGNMENT || 585 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) { 586 memcpy(fep->tx_bounce[index], data, size); 587 data = fep->tx_bounce[index]; 588 589 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 590 swap_buffer(data, size); 591 } 592 593 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 594 if (dma_mapping_error(&fep->pdev->dev, addr)) { 595 dev_kfree_skb_any(skb); 596 if (net_ratelimit()) 597 netdev_err(ndev, "Tx DMA memory map failed\n"); 598 return NETDEV_TX_BUSY; 599 } 600 601 bdp->cbd_datlen = size; 602 bdp->cbd_bufaddr = addr; 603 604 if (fep->bufdesc_ex) { 605 if (skb->ip_summed == CHECKSUM_PARTIAL) 606 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 607 ebdp->cbd_bdu = 0; 608 ebdp->cbd_esc = estatus; 609 } 610 611 /* Handle the last BD specially */ 612 if (last_tcp) 613 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 614 if (is_last) { 615 status |= BD_ENET_TX_INTR; 616 if (fep->bufdesc_ex) 617 ebdp->cbd_esc |= BD_ENET_TX_INT; 618 } 619 620 bdp->cbd_sc = status; 621 622 return 0; 623 } 624 625 static int 626 fec_enet_txq_put_hdr_tso(struct sk_buff *skb, struct net_device *ndev, 627 struct bufdesc *bdp, int index) 628 { 629 struct fec_enet_private *fep = netdev_priv(ndev); 630 const struct platform_device_id *id_entry = 631 platform_get_device_id(fep->pdev); 632 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 633 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 634 void *bufaddr; 635 unsigned long dmabuf; 636 unsigned short status; 637 unsigned int estatus = 0; 638 639 status = bdp->cbd_sc; 640 status &= ~BD_ENET_TX_STATS; 641 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 642 643 bufaddr = fep->tso_hdrs + index * TSO_HEADER_SIZE; 644 dmabuf = fep->tso_hdrs_dma + index * TSO_HEADER_SIZE; 645 if (((unsigned long) bufaddr) & FEC_ALIGNMENT || 646 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) { 647 memcpy(fep->tx_bounce[index], skb->data, hdr_len); 648 bufaddr = fep->tx_bounce[index]; 649 650 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 651 swap_buffer(bufaddr, hdr_len); 652 653 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 654 hdr_len, DMA_TO_DEVICE); 655 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 656 dev_kfree_skb_any(skb); 657 if (net_ratelimit()) 658 netdev_err(ndev, "Tx DMA memory map failed\n"); 659 return NETDEV_TX_BUSY; 660 } 661 } 662 663 bdp->cbd_bufaddr = dmabuf; 664 bdp->cbd_datlen = hdr_len; 665 666 if (fep->bufdesc_ex) { 667 if (skb->ip_summed == CHECKSUM_PARTIAL) 668 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 669 ebdp->cbd_bdu = 0; 670 ebdp->cbd_esc = estatus; 671 } 672 673 bdp->cbd_sc = status; 674 675 return 0; 676 } 677 678 static int fec_enet_txq_submit_tso(struct sk_buff *skb, struct net_device *ndev) 679 { 680 struct fec_enet_private *fep = netdev_priv(ndev); 681 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 682 int total_len, data_left; 683 struct bufdesc *bdp = fep->cur_tx; 684 struct tso_t tso; 685 unsigned int index = 0; 686 int ret; 687 688 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep)) { 689 dev_kfree_skb_any(skb); 690 if (net_ratelimit()) 691 netdev_err(ndev, "NOT enough BD for TSO!\n"); 692 return NETDEV_TX_OK; 693 } 694 695 /* Protocol checksum off-load for TCP and UDP. */ 696 if (fec_enet_clear_csum(skb, ndev)) { 697 dev_kfree_skb_any(skb); 698 return NETDEV_TX_OK; 699 } 700 701 /* Initialize the TSO handler, and prepare the first payload */ 702 tso_start(skb, &tso); 703 704 total_len = skb->len - hdr_len; 705 while (total_len > 0) { 706 char *hdr; 707 708 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep); 709 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 710 total_len -= data_left; 711 712 /* prepare packet headers: MAC + IP + TCP */ 713 hdr = fep->tso_hdrs + index * TSO_HEADER_SIZE; 714 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 715 ret = fec_enet_txq_put_hdr_tso(skb, ndev, bdp, index); 716 if (ret) 717 goto err_release; 718 719 while (data_left > 0) { 720 int size; 721 722 size = min_t(int, tso.size, data_left); 723 bdp = fec_enet_get_nextdesc(bdp, fep); 724 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep); 725 ret = fec_enet_txq_put_data_tso(skb, ndev, bdp, index, tso.data, 726 size, size == data_left, 727 total_len == 0); 728 if (ret) 729 goto err_release; 730 731 data_left -= size; 732 tso_build_data(skb, &tso, size); 733 } 734 735 bdp = fec_enet_get_nextdesc(bdp, fep); 736 } 737 738 /* Save skb pointer */ 739 fep->tx_skbuff[index] = skb; 740 741 skb_tx_timestamp(skb); 742 fep->cur_tx = bdp; 743 744 /* Trigger transmission start */ 745 writel(0, fep->hwp + FEC_X_DES_ACTIVE); 746 747 return 0; 748 749 err_release: 750 /* TODO: Release all used data descriptors for TSO */ 751 return ret; 752 } 753 754 static netdev_tx_t 755 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 756 { 757 struct fec_enet_private *fep = netdev_priv(ndev); 758 int entries_free; 759 int ret; 760 761 if (skb_is_gso(skb)) 762 ret = fec_enet_txq_submit_tso(skb, ndev); 763 else 764 ret = fec_enet_txq_submit_skb(skb, ndev); 765 if (ret) 766 return ret; 767 768 entries_free = fec_enet_get_free_txdesc_num(fep); 769 if (entries_free <= fep->tx_stop_threshold) 770 netif_stop_queue(ndev); 771 772 return NETDEV_TX_OK; 773 } 774 775 /* Init RX & TX buffer descriptors 776 */ 777 static void fec_enet_bd_init(struct net_device *dev) 778 { 779 struct fec_enet_private *fep = netdev_priv(dev); 780 struct bufdesc *bdp; 781 unsigned int i; 782 783 /* Initialize the receive buffer descriptors. */ 784 bdp = fep->rx_bd_base; 785 for (i = 0; i < fep->rx_ring_size; i++) { 786 787 /* Initialize the BD for every fragment in the page. */ 788 if (bdp->cbd_bufaddr) 789 bdp->cbd_sc = BD_ENET_RX_EMPTY; 790 else 791 bdp->cbd_sc = 0; 792 bdp = fec_enet_get_nextdesc(bdp, fep); 793 } 794 795 /* Set the last buffer to wrap */ 796 bdp = fec_enet_get_prevdesc(bdp, fep); 797 bdp->cbd_sc |= BD_SC_WRAP; 798 799 fep->cur_rx = fep->rx_bd_base; 800 801 /* ...and the same for transmit */ 802 bdp = fep->tx_bd_base; 803 fep->cur_tx = bdp; 804 for (i = 0; i < fep->tx_ring_size; i++) { 805 806 /* Initialize the BD for every fragment in the page. */ 807 bdp->cbd_sc = 0; 808 if (fep->tx_skbuff[i]) { 809 dev_kfree_skb_any(fep->tx_skbuff[i]); 810 fep->tx_skbuff[i] = NULL; 811 } 812 bdp->cbd_bufaddr = 0; 813 bdp = fec_enet_get_nextdesc(bdp, fep); 814 } 815 816 /* Set the last buffer to wrap */ 817 bdp = fec_enet_get_prevdesc(bdp, fep); 818 bdp->cbd_sc |= BD_SC_WRAP; 819 fep->dirty_tx = bdp; 820 } 821 822 /* 823 * This function is called to start or restart the FEC during a link 824 * change, transmit timeout, or to reconfigure the FEC. The network 825 * packet processing for this device must be stopped before this call. 826 */ 827 static void 828 fec_restart(struct net_device *ndev) 829 { 830 struct fec_enet_private *fep = netdev_priv(ndev); 831 const struct platform_device_id *id_entry = 832 platform_get_device_id(fep->pdev); 833 int i; 834 u32 val; 835 u32 temp_mac[2]; 836 u32 rcntl = OPT_FRAME_SIZE | 0x04; 837 u32 ecntl = 0x2; /* ETHEREN */ 838 839 /* Whack a reset. We should wait for this. */ 840 writel(1, fep->hwp + FEC_ECNTRL); 841 udelay(10); 842 843 /* 844 * enet-mac reset will reset mac address registers too, 845 * so need to reconfigure it. 846 */ 847 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 848 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 849 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); 850 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); 851 } 852 853 /* Clear any outstanding interrupt. */ 854 writel(0xffc00000, fep->hwp + FEC_IEVENT); 855 856 /* Set maximum receive buffer size. */ 857 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); 858 859 fec_enet_bd_init(ndev); 860 861 /* Set receive and transmit descriptor base. */ 862 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); 863 if (fep->bufdesc_ex) 864 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex) 865 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START); 866 else 867 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) 868 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START); 869 870 871 for (i = 0; i <= TX_RING_MOD_MASK; i++) { 872 if (fep->tx_skbuff[i]) { 873 dev_kfree_skb_any(fep->tx_skbuff[i]); 874 fep->tx_skbuff[i] = NULL; 875 } 876 } 877 878 /* Enable MII mode */ 879 if (fep->full_duplex == DUPLEX_FULL) { 880 /* FD enable */ 881 writel(0x04, fep->hwp + FEC_X_CNTRL); 882 } else { 883 /* No Rcv on Xmit */ 884 rcntl |= 0x02; 885 writel(0x0, fep->hwp + FEC_X_CNTRL); 886 } 887 888 /* Set MII speed */ 889 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 890 891 #if !defined(CONFIG_M5272) 892 /* set RX checksum */ 893 val = readl(fep->hwp + FEC_RACC); 894 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 895 val |= FEC_RACC_OPTIONS; 896 else 897 val &= ~FEC_RACC_OPTIONS; 898 writel(val, fep->hwp + FEC_RACC); 899 #endif 900 901 /* 902 * The phy interface and speed need to get configured 903 * differently on enet-mac. 904 */ 905 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 906 /* Enable flow control and length check */ 907 rcntl |= 0x40000000 | 0x00000020; 908 909 /* RGMII, RMII or MII */ 910 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) 911 rcntl |= (1 << 6); 912 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 913 rcntl |= (1 << 8); 914 else 915 rcntl &= ~(1 << 8); 916 917 /* 1G, 100M or 10M */ 918 if (fep->phy_dev) { 919 if (fep->phy_dev->speed == SPEED_1000) 920 ecntl |= (1 << 5); 921 else if (fep->phy_dev->speed == SPEED_100) 922 rcntl &= ~(1 << 9); 923 else 924 rcntl |= (1 << 9); 925 } 926 } else { 927 #ifdef FEC_MIIGSK_ENR 928 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { 929 u32 cfgr; 930 /* disable the gasket and wait */ 931 writel(0, fep->hwp + FEC_MIIGSK_ENR); 932 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 933 udelay(1); 934 935 /* 936 * configure the gasket: 937 * RMII, 50 MHz, no loopback, no echo 938 * MII, 25 MHz, no loopback, no echo 939 */ 940 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 941 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 942 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) 943 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 944 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 945 946 /* re-enable the gasket */ 947 writel(2, fep->hwp + FEC_MIIGSK_ENR); 948 } 949 #endif 950 } 951 952 #if !defined(CONFIG_M5272) 953 /* enable pause frame*/ 954 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 955 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 956 fep->phy_dev && fep->phy_dev->pause)) { 957 rcntl |= FEC_ENET_FCE; 958 959 /* set FIFO threshold parameter to reduce overrun */ 960 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 961 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 962 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 963 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 964 965 /* OPD */ 966 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 967 } else { 968 rcntl &= ~FEC_ENET_FCE; 969 } 970 #endif /* !defined(CONFIG_M5272) */ 971 972 writel(rcntl, fep->hwp + FEC_R_CNTRL); 973 974 /* Setup multicast filter. */ 975 set_multicast_list(ndev); 976 #ifndef CONFIG_M5272 977 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 978 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 979 #endif 980 981 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 982 /* enable ENET endian swap */ 983 ecntl |= (1 << 8); 984 /* enable ENET store and forward mode */ 985 writel(1 << 8, fep->hwp + FEC_X_WMRK); 986 } 987 988 if (fep->bufdesc_ex) 989 ecntl |= (1 << 4); 990 991 #ifndef CONFIG_M5272 992 /* Enable the MIB statistic event counters */ 993 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 994 #endif 995 996 /* And last, enable the transmit and receive processing */ 997 writel(ecntl, fep->hwp + FEC_ECNTRL); 998 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 999 1000 if (fep->bufdesc_ex) 1001 fec_ptp_start_cyclecounter(ndev); 1002 1003 /* Enable interrupts we wish to service */ 1004 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1005 } 1006 1007 static void 1008 fec_stop(struct net_device *ndev) 1009 { 1010 struct fec_enet_private *fep = netdev_priv(ndev); 1011 const struct platform_device_id *id_entry = 1012 platform_get_device_id(fep->pdev); 1013 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1014 1015 /* We cannot expect a graceful transmit stop without link !!! */ 1016 if (fep->link) { 1017 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1018 udelay(10); 1019 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1020 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1021 } 1022 1023 /* Whack a reset. We should wait for this. */ 1024 writel(1, fep->hwp + FEC_ECNTRL); 1025 udelay(10); 1026 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1027 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1028 1029 /* We have to keep ENET enabled to have MII interrupt stay working */ 1030 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 1031 writel(2, fep->hwp + FEC_ECNTRL); 1032 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1033 } 1034 } 1035 1036 1037 static void 1038 fec_timeout(struct net_device *ndev) 1039 { 1040 struct fec_enet_private *fep = netdev_priv(ndev); 1041 1042 fec_dump(ndev); 1043 1044 ndev->stats.tx_errors++; 1045 1046 schedule_work(&fep->tx_timeout_work); 1047 } 1048 1049 static void fec_enet_timeout_work(struct work_struct *work) 1050 { 1051 struct fec_enet_private *fep = 1052 container_of(work, struct fec_enet_private, tx_timeout_work); 1053 struct net_device *ndev = fep->netdev; 1054 1055 rtnl_lock(); 1056 if (netif_device_present(ndev) || netif_running(ndev)) { 1057 napi_disable(&fep->napi); 1058 netif_tx_lock_bh(ndev); 1059 fec_restart(ndev); 1060 netif_wake_queue(ndev); 1061 netif_tx_unlock_bh(ndev); 1062 napi_enable(&fep->napi); 1063 } 1064 rtnl_unlock(); 1065 } 1066 1067 static void 1068 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1069 struct skb_shared_hwtstamps *hwtstamps) 1070 { 1071 unsigned long flags; 1072 u64 ns; 1073 1074 spin_lock_irqsave(&fep->tmreg_lock, flags); 1075 ns = timecounter_cyc2time(&fep->tc, ts); 1076 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1077 1078 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1079 hwtstamps->hwtstamp = ns_to_ktime(ns); 1080 } 1081 1082 static void 1083 fec_enet_tx(struct net_device *ndev) 1084 { 1085 struct fec_enet_private *fep; 1086 struct bufdesc *bdp; 1087 unsigned short status; 1088 struct sk_buff *skb; 1089 int index = 0; 1090 int entries_free; 1091 1092 fep = netdev_priv(ndev); 1093 bdp = fep->dirty_tx; 1094 1095 /* get next bdp of dirty_tx */ 1096 bdp = fec_enet_get_nextdesc(bdp, fep); 1097 1098 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { 1099 1100 /* current queue is empty */ 1101 if (bdp == fep->cur_tx) 1102 break; 1103 1104 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep); 1105 1106 skb = fep->tx_skbuff[index]; 1107 fep->tx_skbuff[index] = NULL; 1108 if (!IS_TSO_HEADER(fep, bdp->cbd_bufaddr)) 1109 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 1110 bdp->cbd_datlen, DMA_TO_DEVICE); 1111 bdp->cbd_bufaddr = 0; 1112 if (!skb) { 1113 bdp = fec_enet_get_nextdesc(bdp, fep); 1114 continue; 1115 } 1116 1117 /* Check for errors. */ 1118 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1119 BD_ENET_TX_RL | BD_ENET_TX_UN | 1120 BD_ENET_TX_CSL)) { 1121 ndev->stats.tx_errors++; 1122 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1123 ndev->stats.tx_heartbeat_errors++; 1124 if (status & BD_ENET_TX_LC) /* Late collision */ 1125 ndev->stats.tx_window_errors++; 1126 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1127 ndev->stats.tx_aborted_errors++; 1128 if (status & BD_ENET_TX_UN) /* Underrun */ 1129 ndev->stats.tx_fifo_errors++; 1130 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1131 ndev->stats.tx_carrier_errors++; 1132 } else { 1133 ndev->stats.tx_packets++; 1134 ndev->stats.tx_bytes += skb->len; 1135 } 1136 1137 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 1138 fep->bufdesc_ex) { 1139 struct skb_shared_hwtstamps shhwtstamps; 1140 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1141 1142 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps); 1143 skb_tstamp_tx(skb, &shhwtstamps); 1144 } 1145 1146 /* Deferred means some collisions occurred during transmit, 1147 * but we eventually sent the packet OK. 1148 */ 1149 if (status & BD_ENET_TX_DEF) 1150 ndev->stats.collisions++; 1151 1152 /* Free the sk buffer associated with this last transmit */ 1153 dev_kfree_skb_any(skb); 1154 1155 fep->dirty_tx = bdp; 1156 1157 /* Update pointer to next buffer descriptor to be transmitted */ 1158 bdp = fec_enet_get_nextdesc(bdp, fep); 1159 1160 /* Since we have freed up a buffer, the ring is no longer full 1161 */ 1162 if (netif_queue_stopped(ndev)) { 1163 entries_free = fec_enet_get_free_txdesc_num(fep); 1164 if (entries_free >= fep->tx_wake_threshold) 1165 netif_wake_queue(ndev); 1166 } 1167 } 1168 1169 /* ERR006538: Keep the transmitter going */ 1170 if (bdp != fep->cur_tx && readl(fep->hwp + FEC_X_DES_ACTIVE) == 0) 1171 writel(0, fep->hwp + FEC_X_DES_ACTIVE); 1172 } 1173 1174 /* During a receive, the cur_rx points to the current incoming buffer. 1175 * When we update through the ring, if the next incoming buffer has 1176 * not been given to the system, we just set the empty indicator, 1177 * effectively tossing the packet. 1178 */ 1179 static int 1180 fec_enet_rx(struct net_device *ndev, int budget) 1181 { 1182 struct fec_enet_private *fep = netdev_priv(ndev); 1183 const struct platform_device_id *id_entry = 1184 platform_get_device_id(fep->pdev); 1185 struct bufdesc *bdp; 1186 unsigned short status; 1187 struct sk_buff *skb; 1188 ushort pkt_len; 1189 __u8 *data; 1190 int pkt_received = 0; 1191 struct bufdesc_ex *ebdp = NULL; 1192 bool vlan_packet_rcvd = false; 1193 u16 vlan_tag; 1194 int index = 0; 1195 1196 #ifdef CONFIG_M532x 1197 flush_cache_all(); 1198 #endif 1199 1200 /* First, grab all of the stats for the incoming packet. 1201 * These get messed up if we get called due to a busy condition. 1202 */ 1203 bdp = fep->cur_rx; 1204 1205 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { 1206 1207 if (pkt_received >= budget) 1208 break; 1209 pkt_received++; 1210 1211 /* Since we have allocated space to hold a complete frame, 1212 * the last indicator should be set. 1213 */ 1214 if ((status & BD_ENET_RX_LAST) == 0) 1215 netdev_err(ndev, "rcv is not +last\n"); 1216 1217 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); 1218 1219 /* Check for errors. */ 1220 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1221 BD_ENET_RX_CR | BD_ENET_RX_OV)) { 1222 ndev->stats.rx_errors++; 1223 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { 1224 /* Frame too long or too short. */ 1225 ndev->stats.rx_length_errors++; 1226 } 1227 if (status & BD_ENET_RX_NO) /* Frame alignment */ 1228 ndev->stats.rx_frame_errors++; 1229 if (status & BD_ENET_RX_CR) /* CRC Error */ 1230 ndev->stats.rx_crc_errors++; 1231 if (status & BD_ENET_RX_OV) /* FIFO overrun */ 1232 ndev->stats.rx_fifo_errors++; 1233 } 1234 1235 /* Report late collisions as a frame error. 1236 * On this error, the BD is closed, but we don't know what we 1237 * have in the buffer. So, just drop this frame on the floor. 1238 */ 1239 if (status & BD_ENET_RX_CL) { 1240 ndev->stats.rx_errors++; 1241 ndev->stats.rx_frame_errors++; 1242 goto rx_processing_done; 1243 } 1244 1245 /* Process the incoming frame. */ 1246 ndev->stats.rx_packets++; 1247 pkt_len = bdp->cbd_datlen; 1248 ndev->stats.rx_bytes += pkt_len; 1249 1250 index = fec_enet_get_bd_index(fep->rx_bd_base, bdp, fep); 1251 data = fep->rx_skbuff[index]->data; 1252 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr, 1253 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1254 1255 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 1256 swap_buffer(data, pkt_len); 1257 1258 /* Extract the enhanced buffer descriptor */ 1259 ebdp = NULL; 1260 if (fep->bufdesc_ex) 1261 ebdp = (struct bufdesc_ex *)bdp; 1262 1263 /* If this is a VLAN packet remove the VLAN Tag */ 1264 vlan_packet_rcvd = false; 1265 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1266 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) { 1267 /* Push and remove the vlan tag */ 1268 struct vlan_hdr *vlan_header = 1269 (struct vlan_hdr *) (data + ETH_HLEN); 1270 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1271 pkt_len -= VLAN_HLEN; 1272 1273 vlan_packet_rcvd = true; 1274 } 1275 1276 /* This does 16 byte alignment, exactly what we need. 1277 * The packet length includes FCS, but we don't want to 1278 * include that when passing upstream as it messes up 1279 * bridging applications. 1280 */ 1281 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); 1282 1283 if (unlikely(!skb)) { 1284 ndev->stats.rx_dropped++; 1285 } else { 1286 int payload_offset = (2 * ETH_ALEN); 1287 skb_reserve(skb, NET_IP_ALIGN); 1288 skb_put(skb, pkt_len - 4); /* Make room */ 1289 1290 /* Extract the frame data without the VLAN header. */ 1291 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN)); 1292 if (vlan_packet_rcvd) 1293 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN; 1294 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN), 1295 data + payload_offset, 1296 pkt_len - 4 - (2 * ETH_ALEN)); 1297 1298 skb->protocol = eth_type_trans(skb, ndev); 1299 1300 /* Get receive timestamp from the skb */ 1301 if (fep->hwts_rx_en && fep->bufdesc_ex) 1302 fec_enet_hwtstamp(fep, ebdp->ts, 1303 skb_hwtstamps(skb)); 1304 1305 if (fep->bufdesc_ex && 1306 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1307 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) { 1308 /* don't check it */ 1309 skb->ip_summed = CHECKSUM_UNNECESSARY; 1310 } else { 1311 skb_checksum_none_assert(skb); 1312 } 1313 } 1314 1315 /* Handle received VLAN packets */ 1316 if (vlan_packet_rcvd) 1317 __vlan_hwaccel_put_tag(skb, 1318 htons(ETH_P_8021Q), 1319 vlan_tag); 1320 1321 napi_gro_receive(&fep->napi, skb); 1322 } 1323 1324 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr, 1325 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1326 rx_processing_done: 1327 /* Clear the status flags for this buffer */ 1328 status &= ~BD_ENET_RX_STATS; 1329 1330 /* Mark the buffer empty */ 1331 status |= BD_ENET_RX_EMPTY; 1332 bdp->cbd_sc = status; 1333 1334 if (fep->bufdesc_ex) { 1335 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1336 1337 ebdp->cbd_esc = BD_ENET_RX_INT; 1338 ebdp->cbd_prot = 0; 1339 ebdp->cbd_bdu = 0; 1340 } 1341 1342 /* Update BD pointer to next entry */ 1343 bdp = fec_enet_get_nextdesc(bdp, fep); 1344 1345 /* Doing this here will keep the FEC running while we process 1346 * incoming frames. On a heavily loaded network, we should be 1347 * able to keep up at the expense of system resources. 1348 */ 1349 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 1350 } 1351 fep->cur_rx = bdp; 1352 1353 return pkt_received; 1354 } 1355 1356 static irqreturn_t 1357 fec_enet_interrupt(int irq, void *dev_id) 1358 { 1359 struct net_device *ndev = dev_id; 1360 struct fec_enet_private *fep = netdev_priv(ndev); 1361 const unsigned napi_mask = FEC_ENET_RXF | FEC_ENET_TXF; 1362 uint int_events; 1363 irqreturn_t ret = IRQ_NONE; 1364 1365 int_events = readl(fep->hwp + FEC_IEVENT); 1366 writel(int_events & ~napi_mask, fep->hwp + FEC_IEVENT); 1367 1368 if (int_events & napi_mask) { 1369 ret = IRQ_HANDLED; 1370 1371 /* Disable the NAPI interrupts */ 1372 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); 1373 napi_schedule(&fep->napi); 1374 } 1375 1376 if (int_events & FEC_ENET_MII) { 1377 ret = IRQ_HANDLED; 1378 complete(&fep->mdio_done); 1379 } 1380 1381 return ret; 1382 } 1383 1384 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1385 { 1386 struct net_device *ndev = napi->dev; 1387 struct fec_enet_private *fep = netdev_priv(ndev); 1388 int pkts; 1389 1390 /* 1391 * Clear any pending transmit or receive interrupts before 1392 * processing the rings to avoid racing with the hardware. 1393 */ 1394 writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT); 1395 1396 pkts = fec_enet_rx(ndev, budget); 1397 1398 fec_enet_tx(ndev); 1399 1400 if (pkts < budget) { 1401 napi_complete(napi); 1402 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1403 } 1404 return pkts; 1405 } 1406 1407 /* ------------------------------------------------------------------------- */ 1408 static void fec_get_mac(struct net_device *ndev) 1409 { 1410 struct fec_enet_private *fep = netdev_priv(ndev); 1411 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1412 unsigned char *iap, tmpaddr[ETH_ALEN]; 1413 1414 /* 1415 * try to get mac address in following order: 1416 * 1417 * 1) module parameter via kernel command line in form 1418 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1419 */ 1420 iap = macaddr; 1421 1422 /* 1423 * 2) from device tree data 1424 */ 1425 if (!is_valid_ether_addr(iap)) { 1426 struct device_node *np = fep->pdev->dev.of_node; 1427 if (np) { 1428 const char *mac = of_get_mac_address(np); 1429 if (mac) 1430 iap = (unsigned char *) mac; 1431 } 1432 } 1433 1434 /* 1435 * 3) from flash or fuse (via platform data) 1436 */ 1437 if (!is_valid_ether_addr(iap)) { 1438 #ifdef CONFIG_M5272 1439 if (FEC_FLASHMAC) 1440 iap = (unsigned char *)FEC_FLASHMAC; 1441 #else 1442 if (pdata) 1443 iap = (unsigned char *)&pdata->mac; 1444 #endif 1445 } 1446 1447 /* 1448 * 4) FEC mac registers set by bootloader 1449 */ 1450 if (!is_valid_ether_addr(iap)) { 1451 *((__be32 *) &tmpaddr[0]) = 1452 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1453 *((__be16 *) &tmpaddr[4]) = 1454 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1455 iap = &tmpaddr[0]; 1456 } 1457 1458 /* 1459 * 5) random mac address 1460 */ 1461 if (!is_valid_ether_addr(iap)) { 1462 /* Report it and use a random ethernet address instead */ 1463 netdev_err(ndev, "Invalid MAC address: %pM\n", iap); 1464 eth_hw_addr_random(ndev); 1465 netdev_info(ndev, "Using random MAC address: %pM\n", 1466 ndev->dev_addr); 1467 return; 1468 } 1469 1470 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1471 1472 /* Adjust MAC if using macaddr */ 1473 if (iap == macaddr) 1474 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1475 } 1476 1477 /* ------------------------------------------------------------------------- */ 1478 1479 /* 1480 * Phy section 1481 */ 1482 static void fec_enet_adjust_link(struct net_device *ndev) 1483 { 1484 struct fec_enet_private *fep = netdev_priv(ndev); 1485 struct phy_device *phy_dev = fep->phy_dev; 1486 int status_change = 0; 1487 1488 /* Prevent a state halted on mii error */ 1489 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 1490 phy_dev->state = PHY_RESUMING; 1491 return; 1492 } 1493 1494 /* 1495 * If the netdev is down, or is going down, we're not interested 1496 * in link state events, so just mark our idea of the link as down 1497 * and ignore the event. 1498 */ 1499 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1500 fep->link = 0; 1501 } else if (phy_dev->link) { 1502 if (!fep->link) { 1503 fep->link = phy_dev->link; 1504 status_change = 1; 1505 } 1506 1507 if (fep->full_duplex != phy_dev->duplex) { 1508 fep->full_duplex = phy_dev->duplex; 1509 status_change = 1; 1510 } 1511 1512 if (phy_dev->speed != fep->speed) { 1513 fep->speed = phy_dev->speed; 1514 status_change = 1; 1515 } 1516 1517 /* if any of the above changed restart the FEC */ 1518 if (status_change) { 1519 napi_disable(&fep->napi); 1520 netif_tx_lock_bh(ndev); 1521 fec_restart(ndev); 1522 netif_wake_queue(ndev); 1523 netif_tx_unlock_bh(ndev); 1524 napi_enable(&fep->napi); 1525 } 1526 } else { 1527 if (fep->link) { 1528 napi_disable(&fep->napi); 1529 netif_tx_lock_bh(ndev); 1530 fec_stop(ndev); 1531 netif_tx_unlock_bh(ndev); 1532 napi_enable(&fep->napi); 1533 fep->link = phy_dev->link; 1534 status_change = 1; 1535 } 1536 } 1537 1538 if (status_change) 1539 phy_print_status(phy_dev); 1540 } 1541 1542 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1543 { 1544 struct fec_enet_private *fep = bus->priv; 1545 unsigned long time_left; 1546 1547 fep->mii_timeout = 0; 1548 init_completion(&fep->mdio_done); 1549 1550 /* start a read op */ 1551 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 1552 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1553 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1554 1555 /* wait for end of transfer */ 1556 time_left = wait_for_completion_timeout(&fep->mdio_done, 1557 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1558 if (time_left == 0) { 1559 fep->mii_timeout = 1; 1560 netdev_err(fep->netdev, "MDIO read timeout\n"); 1561 return -ETIMEDOUT; 1562 } 1563 1564 /* return value */ 1565 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1566 } 1567 1568 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1569 u16 value) 1570 { 1571 struct fec_enet_private *fep = bus->priv; 1572 unsigned long time_left; 1573 1574 fep->mii_timeout = 0; 1575 init_completion(&fep->mdio_done); 1576 1577 /* start a write op */ 1578 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 1579 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1580 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1581 fep->hwp + FEC_MII_DATA); 1582 1583 /* wait for end of transfer */ 1584 time_left = wait_for_completion_timeout(&fep->mdio_done, 1585 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1586 if (time_left == 0) { 1587 fep->mii_timeout = 1; 1588 netdev_err(fep->netdev, "MDIO write timeout\n"); 1589 return -ETIMEDOUT; 1590 } 1591 1592 return 0; 1593 } 1594 1595 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1596 { 1597 struct fec_enet_private *fep = netdev_priv(ndev); 1598 int ret; 1599 1600 if (enable) { 1601 ret = clk_prepare_enable(fep->clk_ahb); 1602 if (ret) 1603 return ret; 1604 ret = clk_prepare_enable(fep->clk_ipg); 1605 if (ret) 1606 goto failed_clk_ipg; 1607 if (fep->clk_enet_out) { 1608 ret = clk_prepare_enable(fep->clk_enet_out); 1609 if (ret) 1610 goto failed_clk_enet_out; 1611 } 1612 if (fep->clk_ptp) { 1613 ret = clk_prepare_enable(fep->clk_ptp); 1614 if (ret) 1615 goto failed_clk_ptp; 1616 } 1617 } else { 1618 clk_disable_unprepare(fep->clk_ahb); 1619 clk_disable_unprepare(fep->clk_ipg); 1620 if (fep->clk_enet_out) 1621 clk_disable_unprepare(fep->clk_enet_out); 1622 if (fep->clk_ptp) 1623 clk_disable_unprepare(fep->clk_ptp); 1624 } 1625 1626 return 0; 1627 failed_clk_ptp: 1628 if (fep->clk_enet_out) 1629 clk_disable_unprepare(fep->clk_enet_out); 1630 failed_clk_enet_out: 1631 clk_disable_unprepare(fep->clk_ipg); 1632 failed_clk_ipg: 1633 clk_disable_unprepare(fep->clk_ahb); 1634 1635 return ret; 1636 } 1637 1638 static int fec_enet_mii_probe(struct net_device *ndev) 1639 { 1640 struct fec_enet_private *fep = netdev_priv(ndev); 1641 const struct platform_device_id *id_entry = 1642 platform_get_device_id(fep->pdev); 1643 struct phy_device *phy_dev = NULL; 1644 char mdio_bus_id[MII_BUS_ID_SIZE]; 1645 char phy_name[MII_BUS_ID_SIZE + 3]; 1646 int phy_id; 1647 int dev_id = fep->dev_id; 1648 1649 fep->phy_dev = NULL; 1650 1651 /* check for attached phy */ 1652 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1653 if ((fep->mii_bus->phy_mask & (1 << phy_id))) 1654 continue; 1655 if (fep->mii_bus->phy_map[phy_id] == NULL) 1656 continue; 1657 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) 1658 continue; 1659 if (dev_id--) 1660 continue; 1661 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1662 break; 1663 } 1664 1665 if (phy_id >= PHY_MAX_ADDR) { 1666 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1667 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 1668 phy_id = 0; 1669 } 1670 1671 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); 1672 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 1673 fep->phy_interface); 1674 if (IS_ERR(phy_dev)) { 1675 netdev_err(ndev, "could not attach to PHY\n"); 1676 return PTR_ERR(phy_dev); 1677 } 1678 1679 /* mask with MAC supported features */ 1680 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) { 1681 phy_dev->supported &= PHY_GBIT_FEATURES; 1682 phy_dev->supported &= ~SUPPORTED_1000baseT_Half; 1683 #if !defined(CONFIG_M5272) 1684 phy_dev->supported |= SUPPORTED_Pause; 1685 #endif 1686 } 1687 else 1688 phy_dev->supported &= PHY_BASIC_FEATURES; 1689 1690 phy_dev->advertising = phy_dev->supported; 1691 1692 fep->phy_dev = phy_dev; 1693 fep->link = 0; 1694 fep->full_duplex = 0; 1695 1696 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 1697 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), 1698 fep->phy_dev->irq); 1699 1700 return 0; 1701 } 1702 1703 static int fec_enet_mii_init(struct platform_device *pdev) 1704 { 1705 static struct mii_bus *fec0_mii_bus; 1706 struct net_device *ndev = platform_get_drvdata(pdev); 1707 struct fec_enet_private *fep = netdev_priv(ndev); 1708 const struct platform_device_id *id_entry = 1709 platform_get_device_id(fep->pdev); 1710 int err = -ENXIO, i; 1711 1712 /* 1713 * The dual fec interfaces are not equivalent with enet-mac. 1714 * Here are the differences: 1715 * 1716 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1717 * - fec0 acts as the 1588 time master while fec1 is slave 1718 * - external phys can only be configured by fec0 1719 * 1720 * That is to say fec1 can not work independently. It only works 1721 * when fec0 is working. The reason behind this design is that the 1722 * second interface is added primarily for Switch mode. 1723 * 1724 * Because of the last point above, both phys are attached on fec0 1725 * mdio interface in board design, and need to be configured by 1726 * fec0 mii_bus. 1727 */ 1728 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { 1729 /* fec1 uses fec0 mii_bus */ 1730 if (mii_cnt && fec0_mii_bus) { 1731 fep->mii_bus = fec0_mii_bus; 1732 mii_cnt++; 1733 return 0; 1734 } 1735 return -ENOENT; 1736 } 1737 1738 fep->mii_timeout = 0; 1739 1740 /* 1741 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 1742 * 1743 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 1744 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 1745 * Reference Manual has an error on this, and gets fixed on i.MX6Q 1746 * document. 1747 */ 1748 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000); 1749 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1750 fep->phy_speed--; 1751 fep->phy_speed <<= 1; 1752 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1753 1754 fep->mii_bus = mdiobus_alloc(); 1755 if (fep->mii_bus == NULL) { 1756 err = -ENOMEM; 1757 goto err_out; 1758 } 1759 1760 fep->mii_bus->name = "fec_enet_mii_bus"; 1761 fep->mii_bus->read = fec_enet_mdio_read; 1762 fep->mii_bus->write = fec_enet_mdio_write; 1763 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1764 pdev->name, fep->dev_id + 1); 1765 fep->mii_bus->priv = fep; 1766 fep->mii_bus->parent = &pdev->dev; 1767 1768 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 1769 if (!fep->mii_bus->irq) { 1770 err = -ENOMEM; 1771 goto err_out_free_mdiobus; 1772 } 1773 1774 for (i = 0; i < PHY_MAX_ADDR; i++) 1775 fep->mii_bus->irq[i] = PHY_POLL; 1776 1777 if (mdiobus_register(fep->mii_bus)) 1778 goto err_out_free_mdio_irq; 1779 1780 mii_cnt++; 1781 1782 /* save fec0 mii_bus */ 1783 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1784 fec0_mii_bus = fep->mii_bus; 1785 1786 return 0; 1787 1788 err_out_free_mdio_irq: 1789 kfree(fep->mii_bus->irq); 1790 err_out_free_mdiobus: 1791 mdiobus_free(fep->mii_bus); 1792 err_out: 1793 return err; 1794 } 1795 1796 static void fec_enet_mii_remove(struct fec_enet_private *fep) 1797 { 1798 if (--mii_cnt == 0) { 1799 mdiobus_unregister(fep->mii_bus); 1800 kfree(fep->mii_bus->irq); 1801 mdiobus_free(fep->mii_bus); 1802 } 1803 } 1804 1805 static int fec_enet_get_settings(struct net_device *ndev, 1806 struct ethtool_cmd *cmd) 1807 { 1808 struct fec_enet_private *fep = netdev_priv(ndev); 1809 struct phy_device *phydev = fep->phy_dev; 1810 1811 if (!phydev) 1812 return -ENODEV; 1813 1814 return phy_ethtool_gset(phydev, cmd); 1815 } 1816 1817 static int fec_enet_set_settings(struct net_device *ndev, 1818 struct ethtool_cmd *cmd) 1819 { 1820 struct fec_enet_private *fep = netdev_priv(ndev); 1821 struct phy_device *phydev = fep->phy_dev; 1822 1823 if (!phydev) 1824 return -ENODEV; 1825 1826 return phy_ethtool_sset(phydev, cmd); 1827 } 1828 1829 static void fec_enet_get_drvinfo(struct net_device *ndev, 1830 struct ethtool_drvinfo *info) 1831 { 1832 struct fec_enet_private *fep = netdev_priv(ndev); 1833 1834 strlcpy(info->driver, fep->pdev->dev.driver->name, 1835 sizeof(info->driver)); 1836 strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); 1837 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 1838 } 1839 1840 static int fec_enet_get_ts_info(struct net_device *ndev, 1841 struct ethtool_ts_info *info) 1842 { 1843 struct fec_enet_private *fep = netdev_priv(ndev); 1844 1845 if (fep->bufdesc_ex) { 1846 1847 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1848 SOF_TIMESTAMPING_RX_SOFTWARE | 1849 SOF_TIMESTAMPING_SOFTWARE | 1850 SOF_TIMESTAMPING_TX_HARDWARE | 1851 SOF_TIMESTAMPING_RX_HARDWARE | 1852 SOF_TIMESTAMPING_RAW_HARDWARE; 1853 if (fep->ptp_clock) 1854 info->phc_index = ptp_clock_index(fep->ptp_clock); 1855 else 1856 info->phc_index = -1; 1857 1858 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 1859 (1 << HWTSTAMP_TX_ON); 1860 1861 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 1862 (1 << HWTSTAMP_FILTER_ALL); 1863 return 0; 1864 } else { 1865 return ethtool_op_get_ts_info(ndev, info); 1866 } 1867 } 1868 1869 #if !defined(CONFIG_M5272) 1870 1871 static void fec_enet_get_pauseparam(struct net_device *ndev, 1872 struct ethtool_pauseparam *pause) 1873 { 1874 struct fec_enet_private *fep = netdev_priv(ndev); 1875 1876 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 1877 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 1878 pause->rx_pause = pause->tx_pause; 1879 } 1880 1881 static int fec_enet_set_pauseparam(struct net_device *ndev, 1882 struct ethtool_pauseparam *pause) 1883 { 1884 struct fec_enet_private *fep = netdev_priv(ndev); 1885 1886 if (!fep->phy_dev) 1887 return -ENODEV; 1888 1889 if (pause->tx_pause != pause->rx_pause) { 1890 netdev_info(ndev, 1891 "hardware only support enable/disable both tx and rx"); 1892 return -EINVAL; 1893 } 1894 1895 fep->pause_flag = 0; 1896 1897 /* tx pause must be same as rx pause */ 1898 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 1899 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 1900 1901 if (pause->rx_pause || pause->autoneg) { 1902 fep->phy_dev->supported |= ADVERTISED_Pause; 1903 fep->phy_dev->advertising |= ADVERTISED_Pause; 1904 } else { 1905 fep->phy_dev->supported &= ~ADVERTISED_Pause; 1906 fep->phy_dev->advertising &= ~ADVERTISED_Pause; 1907 } 1908 1909 if (pause->autoneg) { 1910 if (netif_running(ndev)) 1911 fec_stop(ndev); 1912 phy_start_aneg(fep->phy_dev); 1913 } 1914 if (netif_running(ndev)) { 1915 napi_disable(&fep->napi); 1916 netif_tx_lock_bh(ndev); 1917 fec_restart(ndev); 1918 netif_wake_queue(ndev); 1919 netif_tx_unlock_bh(ndev); 1920 napi_enable(&fep->napi); 1921 } 1922 1923 return 0; 1924 } 1925 1926 static const struct fec_stat { 1927 char name[ETH_GSTRING_LEN]; 1928 u16 offset; 1929 } fec_stats[] = { 1930 /* RMON TX */ 1931 { "tx_dropped", RMON_T_DROP }, 1932 { "tx_packets", RMON_T_PACKETS }, 1933 { "tx_broadcast", RMON_T_BC_PKT }, 1934 { "tx_multicast", RMON_T_MC_PKT }, 1935 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 1936 { "tx_undersize", RMON_T_UNDERSIZE }, 1937 { "tx_oversize", RMON_T_OVERSIZE }, 1938 { "tx_fragment", RMON_T_FRAG }, 1939 { "tx_jabber", RMON_T_JAB }, 1940 { "tx_collision", RMON_T_COL }, 1941 { "tx_64byte", RMON_T_P64 }, 1942 { "tx_65to127byte", RMON_T_P65TO127 }, 1943 { "tx_128to255byte", RMON_T_P128TO255 }, 1944 { "tx_256to511byte", RMON_T_P256TO511 }, 1945 { "tx_512to1023byte", RMON_T_P512TO1023 }, 1946 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 1947 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 1948 { "tx_octets", RMON_T_OCTETS }, 1949 1950 /* IEEE TX */ 1951 { "IEEE_tx_drop", IEEE_T_DROP }, 1952 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 1953 { "IEEE_tx_1col", IEEE_T_1COL }, 1954 { "IEEE_tx_mcol", IEEE_T_MCOL }, 1955 { "IEEE_tx_def", IEEE_T_DEF }, 1956 { "IEEE_tx_lcol", IEEE_T_LCOL }, 1957 { "IEEE_tx_excol", IEEE_T_EXCOL }, 1958 { "IEEE_tx_macerr", IEEE_T_MACERR }, 1959 { "IEEE_tx_cserr", IEEE_T_CSERR }, 1960 { "IEEE_tx_sqe", IEEE_T_SQE }, 1961 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 1962 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 1963 1964 /* RMON RX */ 1965 { "rx_packets", RMON_R_PACKETS }, 1966 { "rx_broadcast", RMON_R_BC_PKT }, 1967 { "rx_multicast", RMON_R_MC_PKT }, 1968 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 1969 { "rx_undersize", RMON_R_UNDERSIZE }, 1970 { "rx_oversize", RMON_R_OVERSIZE }, 1971 { "rx_fragment", RMON_R_FRAG }, 1972 { "rx_jabber", RMON_R_JAB }, 1973 { "rx_64byte", RMON_R_P64 }, 1974 { "rx_65to127byte", RMON_R_P65TO127 }, 1975 { "rx_128to255byte", RMON_R_P128TO255 }, 1976 { "rx_256to511byte", RMON_R_P256TO511 }, 1977 { "rx_512to1023byte", RMON_R_P512TO1023 }, 1978 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 1979 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 1980 { "rx_octets", RMON_R_OCTETS }, 1981 1982 /* IEEE RX */ 1983 { "IEEE_rx_drop", IEEE_R_DROP }, 1984 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 1985 { "IEEE_rx_crc", IEEE_R_CRC }, 1986 { "IEEE_rx_align", IEEE_R_ALIGN }, 1987 { "IEEE_rx_macerr", IEEE_R_MACERR }, 1988 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 1989 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 1990 }; 1991 1992 static void fec_enet_get_ethtool_stats(struct net_device *dev, 1993 struct ethtool_stats *stats, u64 *data) 1994 { 1995 struct fec_enet_private *fep = netdev_priv(dev); 1996 int i; 1997 1998 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 1999 data[i] = readl(fep->hwp + fec_stats[i].offset); 2000 } 2001 2002 static void fec_enet_get_strings(struct net_device *netdev, 2003 u32 stringset, u8 *data) 2004 { 2005 int i; 2006 switch (stringset) { 2007 case ETH_SS_STATS: 2008 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2009 memcpy(data + i * ETH_GSTRING_LEN, 2010 fec_stats[i].name, ETH_GSTRING_LEN); 2011 break; 2012 } 2013 } 2014 2015 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2016 { 2017 switch (sset) { 2018 case ETH_SS_STATS: 2019 return ARRAY_SIZE(fec_stats); 2020 default: 2021 return -EOPNOTSUPP; 2022 } 2023 } 2024 #endif /* !defined(CONFIG_M5272) */ 2025 2026 static int fec_enet_nway_reset(struct net_device *dev) 2027 { 2028 struct fec_enet_private *fep = netdev_priv(dev); 2029 struct phy_device *phydev = fep->phy_dev; 2030 2031 if (!phydev) 2032 return -ENODEV; 2033 2034 return genphy_restart_aneg(phydev); 2035 } 2036 2037 static const struct ethtool_ops fec_enet_ethtool_ops = { 2038 .get_settings = fec_enet_get_settings, 2039 .set_settings = fec_enet_set_settings, 2040 .get_drvinfo = fec_enet_get_drvinfo, 2041 .nway_reset = fec_enet_nway_reset, 2042 .get_link = ethtool_op_get_link, 2043 #ifndef CONFIG_M5272 2044 .get_pauseparam = fec_enet_get_pauseparam, 2045 .set_pauseparam = fec_enet_set_pauseparam, 2046 .get_strings = fec_enet_get_strings, 2047 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2048 .get_sset_count = fec_enet_get_sset_count, 2049 #endif 2050 .get_ts_info = fec_enet_get_ts_info, 2051 }; 2052 2053 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2054 { 2055 struct fec_enet_private *fep = netdev_priv(ndev); 2056 struct phy_device *phydev = fep->phy_dev; 2057 2058 if (!netif_running(ndev)) 2059 return -EINVAL; 2060 2061 if (!phydev) 2062 return -ENODEV; 2063 2064 if (fep->bufdesc_ex) { 2065 if (cmd == SIOCSHWTSTAMP) 2066 return fec_ptp_set(ndev, rq); 2067 if (cmd == SIOCGHWTSTAMP) 2068 return fec_ptp_get(ndev, rq); 2069 } 2070 2071 return phy_mii_ioctl(phydev, rq, cmd); 2072 } 2073 2074 static void fec_enet_free_buffers(struct net_device *ndev) 2075 { 2076 struct fec_enet_private *fep = netdev_priv(ndev); 2077 unsigned int i; 2078 struct sk_buff *skb; 2079 struct bufdesc *bdp; 2080 2081 bdp = fep->rx_bd_base; 2082 for (i = 0; i < fep->rx_ring_size; i++) { 2083 skb = fep->rx_skbuff[i]; 2084 fep->rx_skbuff[i] = NULL; 2085 if (skb) { 2086 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 2087 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 2088 dev_kfree_skb(skb); 2089 } 2090 bdp = fec_enet_get_nextdesc(bdp, fep); 2091 } 2092 2093 bdp = fep->tx_bd_base; 2094 for (i = 0; i < fep->tx_ring_size; i++) { 2095 kfree(fep->tx_bounce[i]); 2096 fep->tx_bounce[i] = NULL; 2097 skb = fep->tx_skbuff[i]; 2098 fep->tx_skbuff[i] = NULL; 2099 dev_kfree_skb(skb); 2100 } 2101 } 2102 2103 static int fec_enet_alloc_buffers(struct net_device *ndev) 2104 { 2105 struct fec_enet_private *fep = netdev_priv(ndev); 2106 unsigned int i; 2107 struct sk_buff *skb; 2108 struct bufdesc *bdp; 2109 2110 bdp = fep->rx_bd_base; 2111 for (i = 0; i < fep->rx_ring_size; i++) { 2112 dma_addr_t addr; 2113 2114 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2115 if (!skb) 2116 goto err_alloc; 2117 2118 addr = dma_map_single(&fep->pdev->dev, skb->data, 2119 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 2120 if (dma_mapping_error(&fep->pdev->dev, addr)) { 2121 dev_kfree_skb(skb); 2122 if (net_ratelimit()) 2123 netdev_err(ndev, "Rx DMA memory map failed\n"); 2124 goto err_alloc; 2125 } 2126 2127 fep->rx_skbuff[i] = skb; 2128 bdp->cbd_bufaddr = addr; 2129 bdp->cbd_sc = BD_ENET_RX_EMPTY; 2130 2131 if (fep->bufdesc_ex) { 2132 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2133 ebdp->cbd_esc = BD_ENET_RX_INT; 2134 } 2135 2136 bdp = fec_enet_get_nextdesc(bdp, fep); 2137 } 2138 2139 /* Set the last buffer to wrap. */ 2140 bdp = fec_enet_get_prevdesc(bdp, fep); 2141 bdp->cbd_sc |= BD_SC_WRAP; 2142 2143 bdp = fep->tx_bd_base; 2144 for (i = 0; i < fep->tx_ring_size; i++) { 2145 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2146 if (!fep->tx_bounce[i]) 2147 goto err_alloc; 2148 2149 bdp->cbd_sc = 0; 2150 bdp->cbd_bufaddr = 0; 2151 2152 if (fep->bufdesc_ex) { 2153 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2154 ebdp->cbd_esc = BD_ENET_TX_INT; 2155 } 2156 2157 bdp = fec_enet_get_nextdesc(bdp, fep); 2158 } 2159 2160 /* Set the last buffer to wrap. */ 2161 bdp = fec_enet_get_prevdesc(bdp, fep); 2162 bdp->cbd_sc |= BD_SC_WRAP; 2163 2164 return 0; 2165 2166 err_alloc: 2167 fec_enet_free_buffers(ndev); 2168 return -ENOMEM; 2169 } 2170 2171 static int 2172 fec_enet_open(struct net_device *ndev) 2173 { 2174 struct fec_enet_private *fep = netdev_priv(ndev); 2175 int ret; 2176 2177 pinctrl_pm_select_default_state(&fep->pdev->dev); 2178 ret = fec_enet_clk_enable(ndev, true); 2179 if (ret) 2180 return ret; 2181 2182 /* I should reset the ring buffers here, but I don't yet know 2183 * a simple way to do that. 2184 */ 2185 2186 ret = fec_enet_alloc_buffers(ndev); 2187 if (ret) 2188 return ret; 2189 2190 /* Probe and connect to PHY when open the interface */ 2191 ret = fec_enet_mii_probe(ndev); 2192 if (ret) { 2193 fec_enet_free_buffers(ndev); 2194 return ret; 2195 } 2196 2197 fec_restart(ndev); 2198 napi_enable(&fep->napi); 2199 phy_start(fep->phy_dev); 2200 netif_start_queue(ndev); 2201 return 0; 2202 } 2203 2204 static int 2205 fec_enet_close(struct net_device *ndev) 2206 { 2207 struct fec_enet_private *fep = netdev_priv(ndev); 2208 2209 phy_stop(fep->phy_dev); 2210 2211 if (netif_device_present(ndev)) { 2212 napi_disable(&fep->napi); 2213 netif_tx_disable(ndev); 2214 fec_stop(ndev); 2215 } 2216 2217 phy_disconnect(fep->phy_dev); 2218 fep->phy_dev = NULL; 2219 2220 fec_enet_clk_enable(ndev, false); 2221 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2222 fec_enet_free_buffers(ndev); 2223 2224 return 0; 2225 } 2226 2227 /* Set or clear the multicast filter for this adaptor. 2228 * Skeleton taken from sunlance driver. 2229 * The CPM Ethernet implementation allows Multicast as well as individual 2230 * MAC address filtering. Some of the drivers check to make sure it is 2231 * a group multicast address, and discard those that are not. I guess I 2232 * will do the same for now, but just remove the test if you want 2233 * individual filtering as well (do the upper net layers want or support 2234 * this kind of feature?). 2235 */ 2236 2237 #define HASH_BITS 6 /* #bits in hash */ 2238 #define CRC32_POLY 0xEDB88320 2239 2240 static void set_multicast_list(struct net_device *ndev) 2241 { 2242 struct fec_enet_private *fep = netdev_priv(ndev); 2243 struct netdev_hw_addr *ha; 2244 unsigned int i, bit, data, crc, tmp; 2245 unsigned char hash; 2246 2247 if (ndev->flags & IFF_PROMISC) { 2248 tmp = readl(fep->hwp + FEC_R_CNTRL); 2249 tmp |= 0x8; 2250 writel(tmp, fep->hwp + FEC_R_CNTRL); 2251 return; 2252 } 2253 2254 tmp = readl(fep->hwp + FEC_R_CNTRL); 2255 tmp &= ~0x8; 2256 writel(tmp, fep->hwp + FEC_R_CNTRL); 2257 2258 if (ndev->flags & IFF_ALLMULTI) { 2259 /* Catch all multicast addresses, so set the 2260 * filter to all 1's 2261 */ 2262 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2263 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2264 2265 return; 2266 } 2267 2268 /* Clear filter and add the addresses in hash register 2269 */ 2270 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2271 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2272 2273 netdev_for_each_mc_addr(ha, ndev) { 2274 /* calculate crc32 value of mac address */ 2275 crc = 0xffffffff; 2276 2277 for (i = 0; i < ndev->addr_len; i++) { 2278 data = ha->addr[i]; 2279 for (bit = 0; bit < 8; bit++, data >>= 1) { 2280 crc = (crc >> 1) ^ 2281 (((crc ^ data) & 1) ? CRC32_POLY : 0); 2282 } 2283 } 2284 2285 /* only upper 6 bits (HASH_BITS) are used 2286 * which point to specific bit in he hash registers 2287 */ 2288 hash = (crc >> (32 - HASH_BITS)) & 0x3f; 2289 2290 if (hash > 31) { 2291 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2292 tmp |= 1 << (hash - 32); 2293 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2294 } else { 2295 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2296 tmp |= 1 << hash; 2297 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2298 } 2299 } 2300 } 2301 2302 /* Set a MAC change in hardware. */ 2303 static int 2304 fec_set_mac_address(struct net_device *ndev, void *p) 2305 { 2306 struct fec_enet_private *fep = netdev_priv(ndev); 2307 struct sockaddr *addr = p; 2308 2309 if (addr) { 2310 if (!is_valid_ether_addr(addr->sa_data)) 2311 return -EADDRNOTAVAIL; 2312 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 2313 } 2314 2315 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 2316 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 2317 fep->hwp + FEC_ADDR_LOW); 2318 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 2319 fep->hwp + FEC_ADDR_HIGH); 2320 return 0; 2321 } 2322 2323 #ifdef CONFIG_NET_POLL_CONTROLLER 2324 /** 2325 * fec_poll_controller - FEC Poll controller function 2326 * @dev: The FEC network adapter 2327 * 2328 * Polled functionality used by netconsole and others in non interrupt mode 2329 * 2330 */ 2331 static void fec_poll_controller(struct net_device *dev) 2332 { 2333 int i; 2334 struct fec_enet_private *fep = netdev_priv(dev); 2335 2336 for (i = 0; i < FEC_IRQ_NUM; i++) { 2337 if (fep->irq[i] > 0) { 2338 disable_irq(fep->irq[i]); 2339 fec_enet_interrupt(fep->irq[i], dev); 2340 enable_irq(fep->irq[i]); 2341 } 2342 } 2343 } 2344 #endif 2345 2346 #define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM 2347 2348 static int fec_set_features(struct net_device *netdev, 2349 netdev_features_t features) 2350 { 2351 struct fec_enet_private *fep = netdev_priv(netdev); 2352 netdev_features_t changed = features ^ netdev->features; 2353 2354 /* Quiesce the device if necessary */ 2355 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) { 2356 napi_disable(&fep->napi); 2357 netif_tx_lock_bh(netdev); 2358 fec_stop(netdev); 2359 } 2360 2361 netdev->features = features; 2362 2363 /* Receive checksum has been changed */ 2364 if (changed & NETIF_F_RXCSUM) { 2365 if (features & NETIF_F_RXCSUM) 2366 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 2367 else 2368 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 2369 } 2370 2371 /* Resume the device after updates */ 2372 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) { 2373 fec_restart(netdev); 2374 netif_wake_queue(netdev); 2375 netif_tx_unlock_bh(netdev); 2376 napi_enable(&fep->napi); 2377 } 2378 2379 return 0; 2380 } 2381 2382 static const struct net_device_ops fec_netdev_ops = { 2383 .ndo_open = fec_enet_open, 2384 .ndo_stop = fec_enet_close, 2385 .ndo_start_xmit = fec_enet_start_xmit, 2386 .ndo_set_rx_mode = set_multicast_list, 2387 .ndo_change_mtu = eth_change_mtu, 2388 .ndo_validate_addr = eth_validate_addr, 2389 .ndo_tx_timeout = fec_timeout, 2390 .ndo_set_mac_address = fec_set_mac_address, 2391 .ndo_do_ioctl = fec_enet_ioctl, 2392 #ifdef CONFIG_NET_POLL_CONTROLLER 2393 .ndo_poll_controller = fec_poll_controller, 2394 #endif 2395 .ndo_set_features = fec_set_features, 2396 }; 2397 2398 /* 2399 * XXX: We need to clean up on failure exits here. 2400 * 2401 */ 2402 static int fec_enet_init(struct net_device *ndev) 2403 { 2404 struct fec_enet_private *fep = netdev_priv(ndev); 2405 const struct platform_device_id *id_entry = 2406 platform_get_device_id(fep->pdev); 2407 struct bufdesc *cbd_base; 2408 int bd_size; 2409 2410 /* init the tx & rx ring size */ 2411 fep->tx_ring_size = TX_RING_SIZE; 2412 fep->rx_ring_size = RX_RING_SIZE; 2413 2414 fep->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2415 fep->tx_wake_threshold = (fep->tx_ring_size - fep->tx_stop_threshold) / 2; 2416 2417 if (fep->bufdesc_ex) 2418 fep->bufdesc_size = sizeof(struct bufdesc_ex); 2419 else 2420 fep->bufdesc_size = sizeof(struct bufdesc); 2421 bd_size = (fep->tx_ring_size + fep->rx_ring_size) * 2422 fep->bufdesc_size; 2423 2424 /* Allocate memory for buffer descriptors. */ 2425 cbd_base = dma_alloc_coherent(NULL, bd_size, &fep->bd_dma, 2426 GFP_KERNEL); 2427 if (!cbd_base) 2428 return -ENOMEM; 2429 2430 fep->tso_hdrs = dma_alloc_coherent(NULL, fep->tx_ring_size * TSO_HEADER_SIZE, 2431 &fep->tso_hdrs_dma, GFP_KERNEL); 2432 if (!fep->tso_hdrs) { 2433 dma_free_coherent(NULL, bd_size, cbd_base, fep->bd_dma); 2434 return -ENOMEM; 2435 } 2436 2437 memset(cbd_base, 0, PAGE_SIZE); 2438 2439 fep->netdev = ndev; 2440 2441 /* Get the Ethernet address */ 2442 fec_get_mac(ndev); 2443 /* make sure MAC we just acquired is programmed into the hw */ 2444 fec_set_mac_address(ndev, NULL); 2445 2446 /* Set receive and transmit descriptor base. */ 2447 fep->rx_bd_base = cbd_base; 2448 if (fep->bufdesc_ex) 2449 fep->tx_bd_base = (struct bufdesc *) 2450 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size); 2451 else 2452 fep->tx_bd_base = cbd_base + fep->rx_ring_size; 2453 2454 /* The FEC Ethernet specific entries in the device structure */ 2455 ndev->watchdog_timeo = TX_TIMEOUT; 2456 ndev->netdev_ops = &fec_netdev_ops; 2457 ndev->ethtool_ops = &fec_enet_ethtool_ops; 2458 2459 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 2460 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 2461 2462 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) 2463 /* enable hw VLAN support */ 2464 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 2465 2466 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) { 2467 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 2468 2469 /* enable hw accelerator */ 2470 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 2471 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 2472 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 2473 } 2474 2475 ndev->hw_features = ndev->features; 2476 2477 fec_restart(ndev); 2478 2479 return 0; 2480 } 2481 2482 #ifdef CONFIG_OF 2483 static void fec_reset_phy(struct platform_device *pdev) 2484 { 2485 int err, phy_reset; 2486 int msec = 1; 2487 struct device_node *np = pdev->dev.of_node; 2488 2489 if (!np) 2490 return; 2491 2492 of_property_read_u32(np, "phy-reset-duration", &msec); 2493 /* A sane reset duration should not be longer than 1s */ 2494 if (msec > 1000) 2495 msec = 1; 2496 2497 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 2498 if (!gpio_is_valid(phy_reset)) 2499 return; 2500 2501 err = devm_gpio_request_one(&pdev->dev, phy_reset, 2502 GPIOF_OUT_INIT_LOW, "phy-reset"); 2503 if (err) { 2504 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 2505 return; 2506 } 2507 msleep(msec); 2508 gpio_set_value(phy_reset, 1); 2509 } 2510 #else /* CONFIG_OF */ 2511 static void fec_reset_phy(struct platform_device *pdev) 2512 { 2513 /* 2514 * In case of platform probe, the reset has been done 2515 * by machine code. 2516 */ 2517 } 2518 #endif /* CONFIG_OF */ 2519 2520 static int 2521 fec_probe(struct platform_device *pdev) 2522 { 2523 struct fec_enet_private *fep; 2524 struct fec_platform_data *pdata; 2525 struct net_device *ndev; 2526 int i, irq, ret = 0; 2527 struct resource *r; 2528 const struct of_device_id *of_id; 2529 static int dev_id; 2530 2531 of_id = of_match_device(fec_dt_ids, &pdev->dev); 2532 if (of_id) 2533 pdev->id_entry = of_id->data; 2534 2535 /* Init network device */ 2536 ndev = alloc_etherdev(sizeof(struct fec_enet_private)); 2537 if (!ndev) 2538 return -ENOMEM; 2539 2540 SET_NETDEV_DEV(ndev, &pdev->dev); 2541 2542 /* setup board info structure */ 2543 fep = netdev_priv(ndev); 2544 2545 #if !defined(CONFIG_M5272) 2546 /* default enable pause frame auto negotiation */ 2547 if (pdev->id_entry && 2548 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT)) 2549 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 2550 #endif 2551 2552 /* Select default pin state */ 2553 pinctrl_pm_select_default_state(&pdev->dev); 2554 2555 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2556 fep->hwp = devm_ioremap_resource(&pdev->dev, r); 2557 if (IS_ERR(fep->hwp)) { 2558 ret = PTR_ERR(fep->hwp); 2559 goto failed_ioremap; 2560 } 2561 2562 fep->pdev = pdev; 2563 fep->dev_id = dev_id++; 2564 2565 fep->bufdesc_ex = 0; 2566 2567 platform_set_drvdata(pdev, ndev); 2568 2569 ret = of_get_phy_mode(pdev->dev.of_node); 2570 if (ret < 0) { 2571 pdata = dev_get_platdata(&pdev->dev); 2572 if (pdata) 2573 fep->phy_interface = pdata->phy; 2574 else 2575 fep->phy_interface = PHY_INTERFACE_MODE_MII; 2576 } else { 2577 fep->phy_interface = ret; 2578 } 2579 2580 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2581 if (IS_ERR(fep->clk_ipg)) { 2582 ret = PTR_ERR(fep->clk_ipg); 2583 goto failed_clk; 2584 } 2585 2586 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 2587 if (IS_ERR(fep->clk_ahb)) { 2588 ret = PTR_ERR(fep->clk_ahb); 2589 goto failed_clk; 2590 } 2591 2592 /* enet_out is optional, depends on board */ 2593 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 2594 if (IS_ERR(fep->clk_enet_out)) 2595 fep->clk_enet_out = NULL; 2596 2597 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 2598 fep->bufdesc_ex = 2599 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX; 2600 if (IS_ERR(fep->clk_ptp)) { 2601 fep->clk_ptp = NULL; 2602 fep->bufdesc_ex = 0; 2603 } 2604 2605 ret = fec_enet_clk_enable(ndev, true); 2606 if (ret) 2607 goto failed_clk; 2608 2609 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); 2610 if (!IS_ERR(fep->reg_phy)) { 2611 ret = regulator_enable(fep->reg_phy); 2612 if (ret) { 2613 dev_err(&pdev->dev, 2614 "Failed to enable phy regulator: %d\n", ret); 2615 goto failed_regulator; 2616 } 2617 } else { 2618 fep->reg_phy = NULL; 2619 } 2620 2621 fec_reset_phy(pdev); 2622 2623 if (fep->bufdesc_ex) 2624 fec_ptp_init(pdev); 2625 2626 ret = fec_enet_init(ndev); 2627 if (ret) 2628 goto failed_init; 2629 2630 for (i = 0; i < FEC_IRQ_NUM; i++) { 2631 irq = platform_get_irq(pdev, i); 2632 if (irq < 0) { 2633 if (i) 2634 break; 2635 ret = irq; 2636 goto failed_irq; 2637 } 2638 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 2639 0, pdev->name, ndev); 2640 if (ret) 2641 goto failed_irq; 2642 } 2643 2644 ret = fec_enet_mii_init(pdev); 2645 if (ret) 2646 goto failed_mii_init; 2647 2648 /* Carrier starts down, phylib will bring it up */ 2649 netif_carrier_off(ndev); 2650 fec_enet_clk_enable(ndev, false); 2651 pinctrl_pm_select_sleep_state(&pdev->dev); 2652 2653 ret = register_netdev(ndev); 2654 if (ret) 2655 goto failed_register; 2656 2657 if (fep->bufdesc_ex && fep->ptp_clock) 2658 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 2659 2660 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 2661 return 0; 2662 2663 failed_register: 2664 fec_enet_mii_remove(fep); 2665 failed_mii_init: 2666 failed_irq: 2667 failed_init: 2668 if (fep->reg_phy) 2669 regulator_disable(fep->reg_phy); 2670 failed_regulator: 2671 fec_enet_clk_enable(ndev, false); 2672 failed_clk: 2673 failed_ioremap: 2674 free_netdev(ndev); 2675 2676 return ret; 2677 } 2678 2679 static int 2680 fec_drv_remove(struct platform_device *pdev) 2681 { 2682 struct net_device *ndev = platform_get_drvdata(pdev); 2683 struct fec_enet_private *fep = netdev_priv(ndev); 2684 2685 cancel_work_sync(&fep->tx_timeout_work); 2686 unregister_netdev(ndev); 2687 fec_enet_mii_remove(fep); 2688 del_timer_sync(&fep->time_keep); 2689 if (fep->reg_phy) 2690 regulator_disable(fep->reg_phy); 2691 if (fep->ptp_clock) 2692 ptp_clock_unregister(fep->ptp_clock); 2693 fec_enet_clk_enable(ndev, false); 2694 free_netdev(ndev); 2695 2696 return 0; 2697 } 2698 2699 static int __maybe_unused fec_suspend(struct device *dev) 2700 { 2701 struct net_device *ndev = dev_get_drvdata(dev); 2702 struct fec_enet_private *fep = netdev_priv(ndev); 2703 2704 rtnl_lock(); 2705 if (netif_running(ndev)) { 2706 phy_stop(fep->phy_dev); 2707 napi_disable(&fep->napi); 2708 netif_tx_lock_bh(ndev); 2709 netif_device_detach(ndev); 2710 netif_tx_unlock_bh(ndev); 2711 fec_stop(ndev); 2712 } 2713 rtnl_unlock(); 2714 2715 fec_enet_clk_enable(ndev, false); 2716 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2717 2718 if (fep->reg_phy) 2719 regulator_disable(fep->reg_phy); 2720 2721 return 0; 2722 } 2723 2724 static int __maybe_unused fec_resume(struct device *dev) 2725 { 2726 struct net_device *ndev = dev_get_drvdata(dev); 2727 struct fec_enet_private *fep = netdev_priv(ndev); 2728 int ret; 2729 2730 if (fep->reg_phy) { 2731 ret = regulator_enable(fep->reg_phy); 2732 if (ret) 2733 return ret; 2734 } 2735 2736 pinctrl_pm_select_default_state(&fep->pdev->dev); 2737 ret = fec_enet_clk_enable(ndev, true); 2738 if (ret) 2739 goto failed_clk; 2740 2741 rtnl_lock(); 2742 if (netif_running(ndev)) { 2743 fec_restart(ndev); 2744 netif_tx_lock_bh(ndev); 2745 netif_device_attach(ndev); 2746 netif_tx_unlock_bh(ndev); 2747 napi_enable(&fep->napi); 2748 phy_start(fep->phy_dev); 2749 } 2750 rtnl_unlock(); 2751 2752 return 0; 2753 2754 failed_clk: 2755 if (fep->reg_phy) 2756 regulator_disable(fep->reg_phy); 2757 return ret; 2758 } 2759 2760 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume); 2761 2762 static struct platform_driver fec_driver = { 2763 .driver = { 2764 .name = DRIVER_NAME, 2765 .owner = THIS_MODULE, 2766 .pm = &fec_pm_ops, 2767 .of_match_table = fec_dt_ids, 2768 }, 2769 .id_table = fec_devtype, 2770 .probe = fec_probe, 2771 .remove = fec_drv_remove, 2772 }; 2773 2774 module_platform_driver(fec_driver); 2775 2776 MODULE_ALIAS("platform:"DRIVER_NAME); 2777 MODULE_LICENSE("GPL"); 2778