1 /* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 * 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/string.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/ptrace.h> 29 #include <linux/errno.h> 30 #include <linux/ioport.h> 31 #include <linux/slab.h> 32 #include <linux/interrupt.h> 33 #include <linux/delay.h> 34 #include <linux/netdevice.h> 35 #include <linux/etherdevice.h> 36 #include <linux/skbuff.h> 37 #include <linux/in.h> 38 #include <linux/ip.h> 39 #include <net/ip.h> 40 #include <net/tso.h> 41 #include <linux/tcp.h> 42 #include <linux/udp.h> 43 #include <linux/icmp.h> 44 #include <linux/spinlock.h> 45 #include <linux/workqueue.h> 46 #include <linux/bitops.h> 47 #include <linux/io.h> 48 #include <linux/irq.h> 49 #include <linux/clk.h> 50 #include <linux/platform_device.h> 51 #include <linux/mdio.h> 52 #include <linux/phy.h> 53 #include <linux/fec.h> 54 #include <linux/of.h> 55 #include <linux/of_device.h> 56 #include <linux/of_gpio.h> 57 #include <linux/of_mdio.h> 58 #include <linux/of_net.h> 59 #include <linux/regulator/consumer.h> 60 #include <linux/if_vlan.h> 61 #include <linux/pinctrl/consumer.h> 62 #include <linux/prefetch.h> 63 #include <soc/imx/cpuidle.h> 64 65 #include <asm/cacheflush.h> 66 67 #include "fec.h" 68 69 static void set_multicast_list(struct net_device *ndev); 70 static void fec_enet_itr_coal_init(struct net_device *ndev); 71 72 #define DRIVER_NAME "fec" 73 74 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0)) 75 76 /* Pause frame feild and FIFO threshold */ 77 #define FEC_ENET_FCE (1 << 5) 78 #define FEC_ENET_RSEM_V 0x84 79 #define FEC_ENET_RSFL_V 16 80 #define FEC_ENET_RAEM_V 0x8 81 #define FEC_ENET_RAFL_V 0x8 82 #define FEC_ENET_OPD_V 0xFFF0 83 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 84 85 static struct platform_device_id fec_devtype[] = { 86 { 87 /* keep it for coldfire */ 88 .name = DRIVER_NAME, 89 .driver_data = 0, 90 }, { 91 .name = "imx25-fec", 92 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR, 93 }, { 94 .name = "imx27-fec", 95 .driver_data = FEC_QUIRK_MIB_CLEAR, 96 }, { 97 .name = "imx28-fec", 98 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 99 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC, 100 }, { 101 .name = "imx6q-fec", 102 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 103 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 104 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 105 FEC_QUIRK_HAS_RACC, 106 }, { 107 .name = "mvf600-fec", 108 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 109 }, { 110 .name = "imx6sx-fec", 111 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 112 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 113 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 114 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 115 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE, 116 }, { 117 .name = "imx6ul-fec", 118 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 119 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 120 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 121 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 122 FEC_QUIRK_HAS_COALESCE, 123 }, { 124 /* sentinel */ 125 } 126 }; 127 MODULE_DEVICE_TABLE(platform, fec_devtype); 128 129 enum imx_fec_type { 130 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 131 IMX27_FEC, /* runs on i.mx27/35/51 */ 132 IMX28_FEC, 133 IMX6Q_FEC, 134 MVF600_FEC, 135 IMX6SX_FEC, 136 IMX6UL_FEC, 137 }; 138 139 static const struct of_device_id fec_dt_ids[] = { 140 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 141 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 142 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 143 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 144 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 145 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 146 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 147 { /* sentinel */ } 148 }; 149 MODULE_DEVICE_TABLE(of, fec_dt_ids); 150 151 static unsigned char macaddr[ETH_ALEN]; 152 module_param_array(macaddr, byte, NULL, 0); 153 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 154 155 #if defined(CONFIG_M5272) 156 /* 157 * Some hardware gets it MAC address out of local flash memory. 158 * if this is non-zero then assume it is the address to get MAC from. 159 */ 160 #if defined(CONFIG_NETtel) 161 #define FEC_FLASHMAC 0xf0006006 162 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 163 #define FEC_FLASHMAC 0xf0006000 164 #elif defined(CONFIG_CANCam) 165 #define FEC_FLASHMAC 0xf0020000 166 #elif defined (CONFIG_M5272C3) 167 #define FEC_FLASHMAC (0xffe04000 + 4) 168 #elif defined(CONFIG_MOD5272) 169 #define FEC_FLASHMAC 0xffc0406b 170 #else 171 #define FEC_FLASHMAC 0 172 #endif 173 #endif /* CONFIG_M5272 */ 174 175 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 176 * 177 * 2048 byte skbufs are allocated. However, alignment requirements 178 * varies between FEC variants. Worst case is 64, so round down by 64. 179 */ 180 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 181 #define PKT_MINBUF_SIZE 64 182 183 /* FEC receive acceleration */ 184 #define FEC_RACC_IPDIS (1 << 1) 185 #define FEC_RACC_PRODIS (1 << 2) 186 #define FEC_RACC_SHIFT16 BIT(7) 187 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 188 189 /* MIB Control Register */ 190 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 191 192 /* 193 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 194 * size bits. Other FEC hardware does not, so we need to take that into 195 * account when setting it. 196 */ 197 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 198 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 199 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 200 #else 201 #define OPT_FRAME_SIZE 0 202 #endif 203 204 /* FEC MII MMFR bits definition */ 205 #define FEC_MMFR_ST (1 << 30) 206 #define FEC_MMFR_OP_READ (2 << 28) 207 #define FEC_MMFR_OP_WRITE (1 << 28) 208 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 209 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 210 #define FEC_MMFR_TA (2 << 16) 211 #define FEC_MMFR_DATA(v) (v & 0xffff) 212 /* FEC ECR bits definition */ 213 #define FEC_ECR_MAGICEN (1 << 2) 214 #define FEC_ECR_SLEEP (1 << 3) 215 216 #define FEC_MII_TIMEOUT 30000 /* us */ 217 218 /* Transmitter timeout */ 219 #define TX_TIMEOUT (2 * HZ) 220 221 #define FEC_PAUSE_FLAG_AUTONEG 0x1 222 #define FEC_PAUSE_FLAG_ENABLE 0x2 223 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 224 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 225 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 226 227 #define COPYBREAK_DEFAULT 256 228 229 /* Max number of allowed TCP segments for software TSO */ 230 #define FEC_MAX_TSO_SEGS 100 231 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 232 233 #define IS_TSO_HEADER(txq, addr) \ 234 ((addr >= txq->tso_hdrs_dma) && \ 235 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 236 237 static int mii_cnt; 238 239 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 240 struct bufdesc_prop *bd) 241 { 242 return (bdp >= bd->last) ? bd->base 243 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 244 } 245 246 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 247 struct bufdesc_prop *bd) 248 { 249 return (bdp <= bd->base) ? bd->last 250 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 251 } 252 253 static int fec_enet_get_bd_index(struct bufdesc *bdp, 254 struct bufdesc_prop *bd) 255 { 256 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 257 } 258 259 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 260 { 261 int entries; 262 263 entries = (((const char *)txq->dirty_tx - 264 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 265 266 return entries >= 0 ? entries : entries + txq->bd.ring_size; 267 } 268 269 static void swap_buffer(void *bufaddr, int len) 270 { 271 int i; 272 unsigned int *buf = bufaddr; 273 274 for (i = 0; i < len; i += 4, buf++) 275 swab32s(buf); 276 } 277 278 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 279 { 280 int i; 281 unsigned int *src = src_buf; 282 unsigned int *dst = dst_buf; 283 284 for (i = 0; i < len; i += 4, src++, dst++) 285 *dst = swab32p(src); 286 } 287 288 static void fec_dump(struct net_device *ndev) 289 { 290 struct fec_enet_private *fep = netdev_priv(ndev); 291 struct bufdesc *bdp; 292 struct fec_enet_priv_tx_q *txq; 293 int index = 0; 294 295 netdev_info(ndev, "TX ring dump\n"); 296 pr_info("Nr SC addr len SKB\n"); 297 298 txq = fep->tx_queue[0]; 299 bdp = txq->bd.base; 300 301 do { 302 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 303 index, 304 bdp == txq->bd.cur ? 'S' : ' ', 305 bdp == txq->dirty_tx ? 'H' : ' ', 306 fec16_to_cpu(bdp->cbd_sc), 307 fec32_to_cpu(bdp->cbd_bufaddr), 308 fec16_to_cpu(bdp->cbd_datlen), 309 txq->tx_skbuff[index]); 310 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 311 index++; 312 } while (bdp != txq->bd.base); 313 } 314 315 static inline bool is_ipv4_pkt(struct sk_buff *skb) 316 { 317 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 318 } 319 320 static int 321 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 322 { 323 /* Only run for packets requiring a checksum. */ 324 if (skb->ip_summed != CHECKSUM_PARTIAL) 325 return 0; 326 327 if (unlikely(skb_cow_head(skb, 0))) 328 return -1; 329 330 if (is_ipv4_pkt(skb)) 331 ip_hdr(skb)->check = 0; 332 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 333 334 return 0; 335 } 336 337 static struct bufdesc * 338 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 339 struct sk_buff *skb, 340 struct net_device *ndev) 341 { 342 struct fec_enet_private *fep = netdev_priv(ndev); 343 struct bufdesc *bdp = txq->bd.cur; 344 struct bufdesc_ex *ebdp; 345 int nr_frags = skb_shinfo(skb)->nr_frags; 346 int frag, frag_len; 347 unsigned short status; 348 unsigned int estatus = 0; 349 skb_frag_t *this_frag; 350 unsigned int index; 351 void *bufaddr; 352 dma_addr_t addr; 353 int i; 354 355 for (frag = 0; frag < nr_frags; frag++) { 356 this_frag = &skb_shinfo(skb)->frags[frag]; 357 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 358 ebdp = (struct bufdesc_ex *)bdp; 359 360 status = fec16_to_cpu(bdp->cbd_sc); 361 status &= ~BD_ENET_TX_STATS; 362 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 363 frag_len = skb_shinfo(skb)->frags[frag].size; 364 365 /* Handle the last BD specially */ 366 if (frag == nr_frags - 1) { 367 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 368 if (fep->bufdesc_ex) { 369 estatus |= BD_ENET_TX_INT; 370 if (unlikely(skb_shinfo(skb)->tx_flags & 371 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 372 estatus |= BD_ENET_TX_TS; 373 } 374 } 375 376 if (fep->bufdesc_ex) { 377 if (fep->quirks & FEC_QUIRK_HAS_AVB) 378 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 379 if (skb->ip_summed == CHECKSUM_PARTIAL) 380 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 381 ebdp->cbd_bdu = 0; 382 ebdp->cbd_esc = cpu_to_fec32(estatus); 383 } 384 385 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset; 386 387 index = fec_enet_get_bd_index(bdp, &txq->bd); 388 if (((unsigned long) bufaddr) & fep->tx_align || 389 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 390 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 391 bufaddr = txq->tx_bounce[index]; 392 393 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 394 swap_buffer(bufaddr, frag_len); 395 } 396 397 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 398 DMA_TO_DEVICE); 399 if (dma_mapping_error(&fep->pdev->dev, addr)) { 400 if (net_ratelimit()) 401 netdev_err(ndev, "Tx DMA memory map failed\n"); 402 goto dma_mapping_error; 403 } 404 405 bdp->cbd_bufaddr = cpu_to_fec32(addr); 406 bdp->cbd_datlen = cpu_to_fec16(frag_len); 407 /* Make sure the updates to rest of the descriptor are 408 * performed before transferring ownership. 409 */ 410 wmb(); 411 bdp->cbd_sc = cpu_to_fec16(status); 412 } 413 414 return bdp; 415 dma_mapping_error: 416 bdp = txq->bd.cur; 417 for (i = 0; i < frag; i++) { 418 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 419 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 420 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 421 } 422 return ERR_PTR(-ENOMEM); 423 } 424 425 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 426 struct sk_buff *skb, struct net_device *ndev) 427 { 428 struct fec_enet_private *fep = netdev_priv(ndev); 429 int nr_frags = skb_shinfo(skb)->nr_frags; 430 struct bufdesc *bdp, *last_bdp; 431 void *bufaddr; 432 dma_addr_t addr; 433 unsigned short status; 434 unsigned short buflen; 435 unsigned int estatus = 0; 436 unsigned int index; 437 int entries_free; 438 439 entries_free = fec_enet_get_free_txdesc_num(txq); 440 if (entries_free < MAX_SKB_FRAGS + 1) { 441 dev_kfree_skb_any(skb); 442 if (net_ratelimit()) 443 netdev_err(ndev, "NOT enough BD for SG!\n"); 444 return NETDEV_TX_OK; 445 } 446 447 /* Protocol checksum off-load for TCP and UDP. */ 448 if (fec_enet_clear_csum(skb, ndev)) { 449 dev_kfree_skb_any(skb); 450 return NETDEV_TX_OK; 451 } 452 453 /* Fill in a Tx ring entry */ 454 bdp = txq->bd.cur; 455 last_bdp = bdp; 456 status = fec16_to_cpu(bdp->cbd_sc); 457 status &= ~BD_ENET_TX_STATS; 458 459 /* Set buffer length and buffer pointer */ 460 bufaddr = skb->data; 461 buflen = skb_headlen(skb); 462 463 index = fec_enet_get_bd_index(bdp, &txq->bd); 464 if (((unsigned long) bufaddr) & fep->tx_align || 465 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 466 memcpy(txq->tx_bounce[index], skb->data, buflen); 467 bufaddr = txq->tx_bounce[index]; 468 469 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 470 swap_buffer(bufaddr, buflen); 471 } 472 473 /* Push the data cache so the CPM does not get stale memory data. */ 474 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 475 if (dma_mapping_error(&fep->pdev->dev, addr)) { 476 dev_kfree_skb_any(skb); 477 if (net_ratelimit()) 478 netdev_err(ndev, "Tx DMA memory map failed\n"); 479 return NETDEV_TX_OK; 480 } 481 482 if (nr_frags) { 483 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 484 if (IS_ERR(last_bdp)) { 485 dma_unmap_single(&fep->pdev->dev, addr, 486 buflen, DMA_TO_DEVICE); 487 dev_kfree_skb_any(skb); 488 return NETDEV_TX_OK; 489 } 490 } else { 491 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 492 if (fep->bufdesc_ex) { 493 estatus = BD_ENET_TX_INT; 494 if (unlikely(skb_shinfo(skb)->tx_flags & 495 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 496 estatus |= BD_ENET_TX_TS; 497 } 498 } 499 bdp->cbd_bufaddr = cpu_to_fec32(addr); 500 bdp->cbd_datlen = cpu_to_fec16(buflen); 501 502 if (fep->bufdesc_ex) { 503 504 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 505 506 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 507 fep->hwts_tx_en)) 508 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 509 510 if (fep->quirks & FEC_QUIRK_HAS_AVB) 511 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 512 513 if (skb->ip_summed == CHECKSUM_PARTIAL) 514 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 515 516 ebdp->cbd_bdu = 0; 517 ebdp->cbd_esc = cpu_to_fec32(estatus); 518 } 519 520 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 521 /* Save skb pointer */ 522 txq->tx_skbuff[index] = skb; 523 524 /* Make sure the updates to rest of the descriptor are performed before 525 * transferring ownership. 526 */ 527 wmb(); 528 529 /* Send it on its way. Tell FEC it's ready, interrupt when done, 530 * it's the last BD of the frame, and to put the CRC on the end. 531 */ 532 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 533 bdp->cbd_sc = cpu_to_fec16(status); 534 535 /* If this was the last BD in the ring, start at the beginning again. */ 536 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 537 538 skb_tx_timestamp(skb); 539 540 /* Make sure the update to bdp and tx_skbuff are performed before 541 * txq->bd.cur. 542 */ 543 wmb(); 544 txq->bd.cur = bdp; 545 546 /* Trigger transmission start */ 547 writel(0, txq->bd.reg_desc_active); 548 549 return 0; 550 } 551 552 static int 553 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 554 struct net_device *ndev, 555 struct bufdesc *bdp, int index, char *data, 556 int size, bool last_tcp, bool is_last) 557 { 558 struct fec_enet_private *fep = netdev_priv(ndev); 559 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 560 unsigned short status; 561 unsigned int estatus = 0; 562 dma_addr_t addr; 563 564 status = fec16_to_cpu(bdp->cbd_sc); 565 status &= ~BD_ENET_TX_STATS; 566 567 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 568 569 if (((unsigned long) data) & fep->tx_align || 570 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 571 memcpy(txq->tx_bounce[index], data, size); 572 data = txq->tx_bounce[index]; 573 574 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 575 swap_buffer(data, size); 576 } 577 578 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 579 if (dma_mapping_error(&fep->pdev->dev, addr)) { 580 dev_kfree_skb_any(skb); 581 if (net_ratelimit()) 582 netdev_err(ndev, "Tx DMA memory map failed\n"); 583 return NETDEV_TX_BUSY; 584 } 585 586 bdp->cbd_datlen = cpu_to_fec16(size); 587 bdp->cbd_bufaddr = cpu_to_fec32(addr); 588 589 if (fep->bufdesc_ex) { 590 if (fep->quirks & FEC_QUIRK_HAS_AVB) 591 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 592 if (skb->ip_summed == CHECKSUM_PARTIAL) 593 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 594 ebdp->cbd_bdu = 0; 595 ebdp->cbd_esc = cpu_to_fec32(estatus); 596 } 597 598 /* Handle the last BD specially */ 599 if (last_tcp) 600 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 601 if (is_last) { 602 status |= BD_ENET_TX_INTR; 603 if (fep->bufdesc_ex) 604 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 605 } 606 607 bdp->cbd_sc = cpu_to_fec16(status); 608 609 return 0; 610 } 611 612 static int 613 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 614 struct sk_buff *skb, struct net_device *ndev, 615 struct bufdesc *bdp, int index) 616 { 617 struct fec_enet_private *fep = netdev_priv(ndev); 618 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 619 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 620 void *bufaddr; 621 unsigned long dmabuf; 622 unsigned short status; 623 unsigned int estatus = 0; 624 625 status = fec16_to_cpu(bdp->cbd_sc); 626 status &= ~BD_ENET_TX_STATS; 627 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 628 629 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 630 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 631 if (((unsigned long)bufaddr) & fep->tx_align || 632 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 633 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 634 bufaddr = txq->tx_bounce[index]; 635 636 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 637 swap_buffer(bufaddr, hdr_len); 638 639 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 640 hdr_len, DMA_TO_DEVICE); 641 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 642 dev_kfree_skb_any(skb); 643 if (net_ratelimit()) 644 netdev_err(ndev, "Tx DMA memory map failed\n"); 645 return NETDEV_TX_BUSY; 646 } 647 } 648 649 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 650 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 651 652 if (fep->bufdesc_ex) { 653 if (fep->quirks & FEC_QUIRK_HAS_AVB) 654 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 655 if (skb->ip_summed == CHECKSUM_PARTIAL) 656 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 657 ebdp->cbd_bdu = 0; 658 ebdp->cbd_esc = cpu_to_fec32(estatus); 659 } 660 661 bdp->cbd_sc = cpu_to_fec16(status); 662 663 return 0; 664 } 665 666 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 667 struct sk_buff *skb, 668 struct net_device *ndev) 669 { 670 struct fec_enet_private *fep = netdev_priv(ndev); 671 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 672 int total_len, data_left; 673 struct bufdesc *bdp = txq->bd.cur; 674 struct tso_t tso; 675 unsigned int index = 0; 676 int ret; 677 678 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 679 dev_kfree_skb_any(skb); 680 if (net_ratelimit()) 681 netdev_err(ndev, "NOT enough BD for TSO!\n"); 682 return NETDEV_TX_OK; 683 } 684 685 /* Protocol checksum off-load for TCP and UDP. */ 686 if (fec_enet_clear_csum(skb, ndev)) { 687 dev_kfree_skb_any(skb); 688 return NETDEV_TX_OK; 689 } 690 691 /* Initialize the TSO handler, and prepare the first payload */ 692 tso_start(skb, &tso); 693 694 total_len = skb->len - hdr_len; 695 while (total_len > 0) { 696 char *hdr; 697 698 index = fec_enet_get_bd_index(bdp, &txq->bd); 699 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 700 total_len -= data_left; 701 702 /* prepare packet headers: MAC + IP + TCP */ 703 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 704 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 705 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 706 if (ret) 707 goto err_release; 708 709 while (data_left > 0) { 710 int size; 711 712 size = min_t(int, tso.size, data_left); 713 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 714 index = fec_enet_get_bd_index(bdp, &txq->bd); 715 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 716 bdp, index, 717 tso.data, size, 718 size == data_left, 719 total_len == 0); 720 if (ret) 721 goto err_release; 722 723 data_left -= size; 724 tso_build_data(skb, &tso, size); 725 } 726 727 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 728 } 729 730 /* Save skb pointer */ 731 txq->tx_skbuff[index] = skb; 732 733 skb_tx_timestamp(skb); 734 txq->bd.cur = bdp; 735 736 /* Trigger transmission start */ 737 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 738 !readl(txq->bd.reg_desc_active) || 739 !readl(txq->bd.reg_desc_active) || 740 !readl(txq->bd.reg_desc_active) || 741 !readl(txq->bd.reg_desc_active)) 742 writel(0, txq->bd.reg_desc_active); 743 744 return 0; 745 746 err_release: 747 /* TODO: Release all used data descriptors for TSO */ 748 return ret; 749 } 750 751 static netdev_tx_t 752 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 753 { 754 struct fec_enet_private *fep = netdev_priv(ndev); 755 int entries_free; 756 unsigned short queue; 757 struct fec_enet_priv_tx_q *txq; 758 struct netdev_queue *nq; 759 int ret; 760 761 queue = skb_get_queue_mapping(skb); 762 txq = fep->tx_queue[queue]; 763 nq = netdev_get_tx_queue(ndev, queue); 764 765 if (skb_is_gso(skb)) 766 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 767 else 768 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 769 if (ret) 770 return ret; 771 772 entries_free = fec_enet_get_free_txdesc_num(txq); 773 if (entries_free <= txq->tx_stop_threshold) 774 netif_tx_stop_queue(nq); 775 776 return NETDEV_TX_OK; 777 } 778 779 /* Init RX & TX buffer descriptors 780 */ 781 static void fec_enet_bd_init(struct net_device *dev) 782 { 783 struct fec_enet_private *fep = netdev_priv(dev); 784 struct fec_enet_priv_tx_q *txq; 785 struct fec_enet_priv_rx_q *rxq; 786 struct bufdesc *bdp; 787 unsigned int i; 788 unsigned int q; 789 790 for (q = 0; q < fep->num_rx_queues; q++) { 791 /* Initialize the receive buffer descriptors. */ 792 rxq = fep->rx_queue[q]; 793 bdp = rxq->bd.base; 794 795 for (i = 0; i < rxq->bd.ring_size; i++) { 796 797 /* Initialize the BD for every fragment in the page. */ 798 if (bdp->cbd_bufaddr) 799 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 800 else 801 bdp->cbd_sc = cpu_to_fec16(0); 802 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 803 } 804 805 /* Set the last buffer to wrap */ 806 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 807 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 808 809 rxq->bd.cur = rxq->bd.base; 810 } 811 812 for (q = 0; q < fep->num_tx_queues; q++) { 813 /* ...and the same for transmit */ 814 txq = fep->tx_queue[q]; 815 bdp = txq->bd.base; 816 txq->bd.cur = bdp; 817 818 for (i = 0; i < txq->bd.ring_size; i++) { 819 /* Initialize the BD for every fragment in the page. */ 820 bdp->cbd_sc = cpu_to_fec16(0); 821 if (txq->tx_skbuff[i]) { 822 dev_kfree_skb_any(txq->tx_skbuff[i]); 823 txq->tx_skbuff[i] = NULL; 824 } 825 bdp->cbd_bufaddr = cpu_to_fec32(0); 826 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 827 } 828 829 /* Set the last buffer to wrap */ 830 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 831 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 832 txq->dirty_tx = bdp; 833 } 834 } 835 836 static void fec_enet_active_rxring(struct net_device *ndev) 837 { 838 struct fec_enet_private *fep = netdev_priv(ndev); 839 int i; 840 841 for (i = 0; i < fep->num_rx_queues; i++) 842 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 843 } 844 845 static void fec_enet_enable_ring(struct net_device *ndev) 846 { 847 struct fec_enet_private *fep = netdev_priv(ndev); 848 struct fec_enet_priv_tx_q *txq; 849 struct fec_enet_priv_rx_q *rxq; 850 int i; 851 852 for (i = 0; i < fep->num_rx_queues; i++) { 853 rxq = fep->rx_queue[i]; 854 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 855 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 856 857 /* enable DMA1/2 */ 858 if (i) 859 writel(RCMR_MATCHEN | RCMR_CMP(i), 860 fep->hwp + FEC_RCMR(i)); 861 } 862 863 for (i = 0; i < fep->num_tx_queues; i++) { 864 txq = fep->tx_queue[i]; 865 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 866 867 /* enable DMA1/2 */ 868 if (i) 869 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 870 fep->hwp + FEC_DMA_CFG(i)); 871 } 872 } 873 874 static void fec_enet_reset_skb(struct net_device *ndev) 875 { 876 struct fec_enet_private *fep = netdev_priv(ndev); 877 struct fec_enet_priv_tx_q *txq; 878 int i, j; 879 880 for (i = 0; i < fep->num_tx_queues; i++) { 881 txq = fep->tx_queue[i]; 882 883 for (j = 0; j < txq->bd.ring_size; j++) { 884 if (txq->tx_skbuff[j]) { 885 dev_kfree_skb_any(txq->tx_skbuff[j]); 886 txq->tx_skbuff[j] = NULL; 887 } 888 } 889 } 890 } 891 892 /* 893 * This function is called to start or restart the FEC during a link 894 * change, transmit timeout, or to reconfigure the FEC. The network 895 * packet processing for this device must be stopped before this call. 896 */ 897 static void 898 fec_restart(struct net_device *ndev) 899 { 900 struct fec_enet_private *fep = netdev_priv(ndev); 901 u32 val; 902 u32 temp_mac[2]; 903 u32 rcntl = OPT_FRAME_SIZE | 0x04; 904 u32 ecntl = 0x2; /* ETHEREN */ 905 906 /* Whack a reset. We should wait for this. 907 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 908 * instead of reset MAC itself. 909 */ 910 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 911 writel(0, fep->hwp + FEC_ECNTRL); 912 } else { 913 writel(1, fep->hwp + FEC_ECNTRL); 914 udelay(10); 915 } 916 917 /* 918 * enet-mac reset will reset mac address registers too, 919 * so need to reconfigure it. 920 */ 921 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 922 writel((__force u32)cpu_to_be32(temp_mac[0]), 923 fep->hwp + FEC_ADDR_LOW); 924 writel((__force u32)cpu_to_be32(temp_mac[1]), 925 fep->hwp + FEC_ADDR_HIGH); 926 927 /* Clear any outstanding interrupt. */ 928 writel(0xffffffff, fep->hwp + FEC_IEVENT); 929 930 fec_enet_bd_init(ndev); 931 932 fec_enet_enable_ring(ndev); 933 934 /* Reset tx SKB buffers. */ 935 fec_enet_reset_skb(ndev); 936 937 /* Enable MII mode */ 938 if (fep->full_duplex == DUPLEX_FULL) { 939 /* FD enable */ 940 writel(0x04, fep->hwp + FEC_X_CNTRL); 941 } else { 942 /* No Rcv on Xmit */ 943 rcntl |= 0x02; 944 writel(0x0, fep->hwp + FEC_X_CNTRL); 945 } 946 947 /* Set MII speed */ 948 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 949 950 #if !defined(CONFIG_M5272) 951 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 952 val = readl(fep->hwp + FEC_RACC); 953 /* align IP header */ 954 val |= FEC_RACC_SHIFT16; 955 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 956 /* set RX checksum */ 957 val |= FEC_RACC_OPTIONS; 958 else 959 val &= ~FEC_RACC_OPTIONS; 960 writel(val, fep->hwp + FEC_RACC); 961 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 962 } 963 #endif 964 965 /* 966 * The phy interface and speed need to get configured 967 * differently on enet-mac. 968 */ 969 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 970 /* Enable flow control and length check */ 971 rcntl |= 0x40000000 | 0x00000020; 972 973 /* RGMII, RMII or MII */ 974 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 975 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 976 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 977 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 978 rcntl |= (1 << 6); 979 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 980 rcntl |= (1 << 8); 981 else 982 rcntl &= ~(1 << 8); 983 984 /* 1G, 100M or 10M */ 985 if (ndev->phydev) { 986 if (ndev->phydev->speed == SPEED_1000) 987 ecntl |= (1 << 5); 988 else if (ndev->phydev->speed == SPEED_100) 989 rcntl &= ~(1 << 9); 990 else 991 rcntl |= (1 << 9); 992 } 993 } else { 994 #ifdef FEC_MIIGSK_ENR 995 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 996 u32 cfgr; 997 /* disable the gasket and wait */ 998 writel(0, fep->hwp + FEC_MIIGSK_ENR); 999 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1000 udelay(1); 1001 1002 /* 1003 * configure the gasket: 1004 * RMII, 50 MHz, no loopback, no echo 1005 * MII, 25 MHz, no loopback, no echo 1006 */ 1007 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1008 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1009 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1010 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1011 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1012 1013 /* re-enable the gasket */ 1014 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1015 } 1016 #endif 1017 } 1018 1019 #if !defined(CONFIG_M5272) 1020 /* enable pause frame*/ 1021 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1022 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1023 ndev->phydev && ndev->phydev->pause)) { 1024 rcntl |= FEC_ENET_FCE; 1025 1026 /* set FIFO threshold parameter to reduce overrun */ 1027 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1028 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1029 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1030 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1031 1032 /* OPD */ 1033 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1034 } else { 1035 rcntl &= ~FEC_ENET_FCE; 1036 } 1037 #endif /* !defined(CONFIG_M5272) */ 1038 1039 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1040 1041 /* Setup multicast filter. */ 1042 set_multicast_list(ndev); 1043 #ifndef CONFIG_M5272 1044 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1045 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1046 #endif 1047 1048 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1049 /* enable ENET endian swap */ 1050 ecntl |= (1 << 8); 1051 /* enable ENET store and forward mode */ 1052 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1053 } 1054 1055 if (fep->bufdesc_ex) 1056 ecntl |= (1 << 4); 1057 1058 #ifndef CONFIG_M5272 1059 /* Enable the MIB statistic event counters */ 1060 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1061 #endif 1062 1063 /* And last, enable the transmit and receive processing */ 1064 writel(ecntl, fep->hwp + FEC_ECNTRL); 1065 fec_enet_active_rxring(ndev); 1066 1067 if (fep->bufdesc_ex) 1068 fec_ptp_start_cyclecounter(ndev); 1069 1070 /* Enable interrupts we wish to service */ 1071 if (fep->link) 1072 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1073 else 1074 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); 1075 1076 /* Init the interrupt coalescing */ 1077 fec_enet_itr_coal_init(ndev); 1078 1079 } 1080 1081 static void 1082 fec_stop(struct net_device *ndev) 1083 { 1084 struct fec_enet_private *fep = netdev_priv(ndev); 1085 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1086 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1087 u32 val; 1088 1089 /* We cannot expect a graceful transmit stop without link !!! */ 1090 if (fep->link) { 1091 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1092 udelay(10); 1093 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1094 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1095 } 1096 1097 /* Whack a reset. We should wait for this. 1098 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1099 * instead of reset MAC itself. 1100 */ 1101 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1102 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 1103 writel(0, fep->hwp + FEC_ECNTRL); 1104 } else { 1105 writel(1, fep->hwp + FEC_ECNTRL); 1106 udelay(10); 1107 } 1108 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1109 } else { 1110 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1111 val = readl(fep->hwp + FEC_ECNTRL); 1112 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1113 writel(val, fep->hwp + FEC_ECNTRL); 1114 1115 if (pdata && pdata->sleep_mode_enable) 1116 pdata->sleep_mode_enable(true); 1117 } 1118 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1119 1120 /* We have to keep ENET enabled to have MII interrupt stay working */ 1121 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1122 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1123 writel(2, fep->hwp + FEC_ECNTRL); 1124 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1125 } 1126 } 1127 1128 1129 static void 1130 fec_timeout(struct net_device *ndev) 1131 { 1132 struct fec_enet_private *fep = netdev_priv(ndev); 1133 1134 fec_dump(ndev); 1135 1136 ndev->stats.tx_errors++; 1137 1138 schedule_work(&fep->tx_timeout_work); 1139 } 1140 1141 static void fec_enet_timeout_work(struct work_struct *work) 1142 { 1143 struct fec_enet_private *fep = 1144 container_of(work, struct fec_enet_private, tx_timeout_work); 1145 struct net_device *ndev = fep->netdev; 1146 1147 rtnl_lock(); 1148 if (netif_device_present(ndev) || netif_running(ndev)) { 1149 napi_disable(&fep->napi); 1150 netif_tx_lock_bh(ndev); 1151 fec_restart(ndev); 1152 netif_wake_queue(ndev); 1153 netif_tx_unlock_bh(ndev); 1154 napi_enable(&fep->napi); 1155 } 1156 rtnl_unlock(); 1157 } 1158 1159 static void 1160 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1161 struct skb_shared_hwtstamps *hwtstamps) 1162 { 1163 unsigned long flags; 1164 u64 ns; 1165 1166 spin_lock_irqsave(&fep->tmreg_lock, flags); 1167 ns = timecounter_cyc2time(&fep->tc, ts); 1168 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1169 1170 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1171 hwtstamps->hwtstamp = ns_to_ktime(ns); 1172 } 1173 1174 static void 1175 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1176 { 1177 struct fec_enet_private *fep; 1178 struct bufdesc *bdp; 1179 unsigned short status; 1180 struct sk_buff *skb; 1181 struct fec_enet_priv_tx_q *txq; 1182 struct netdev_queue *nq; 1183 int index = 0; 1184 int entries_free; 1185 1186 fep = netdev_priv(ndev); 1187 1188 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1189 1190 txq = fep->tx_queue[queue_id]; 1191 /* get next bdp of dirty_tx */ 1192 nq = netdev_get_tx_queue(ndev, queue_id); 1193 bdp = txq->dirty_tx; 1194 1195 /* get next bdp of dirty_tx */ 1196 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1197 1198 while (bdp != READ_ONCE(txq->bd.cur)) { 1199 /* Order the load of bd.cur and cbd_sc */ 1200 rmb(); 1201 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1202 if (status & BD_ENET_TX_READY) 1203 break; 1204 1205 index = fec_enet_get_bd_index(bdp, &txq->bd); 1206 1207 skb = txq->tx_skbuff[index]; 1208 txq->tx_skbuff[index] = NULL; 1209 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1210 dma_unmap_single(&fep->pdev->dev, 1211 fec32_to_cpu(bdp->cbd_bufaddr), 1212 fec16_to_cpu(bdp->cbd_datlen), 1213 DMA_TO_DEVICE); 1214 bdp->cbd_bufaddr = cpu_to_fec32(0); 1215 if (!skb) 1216 goto skb_done; 1217 1218 /* Check for errors. */ 1219 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1220 BD_ENET_TX_RL | BD_ENET_TX_UN | 1221 BD_ENET_TX_CSL)) { 1222 ndev->stats.tx_errors++; 1223 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1224 ndev->stats.tx_heartbeat_errors++; 1225 if (status & BD_ENET_TX_LC) /* Late collision */ 1226 ndev->stats.tx_window_errors++; 1227 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1228 ndev->stats.tx_aborted_errors++; 1229 if (status & BD_ENET_TX_UN) /* Underrun */ 1230 ndev->stats.tx_fifo_errors++; 1231 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1232 ndev->stats.tx_carrier_errors++; 1233 } else { 1234 ndev->stats.tx_packets++; 1235 ndev->stats.tx_bytes += skb->len; 1236 } 1237 1238 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 1239 fep->bufdesc_ex) { 1240 struct skb_shared_hwtstamps shhwtstamps; 1241 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1242 1243 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1244 skb_tstamp_tx(skb, &shhwtstamps); 1245 } 1246 1247 /* Deferred means some collisions occurred during transmit, 1248 * but we eventually sent the packet OK. 1249 */ 1250 if (status & BD_ENET_TX_DEF) 1251 ndev->stats.collisions++; 1252 1253 /* Free the sk buffer associated with this last transmit */ 1254 dev_kfree_skb_any(skb); 1255 skb_done: 1256 /* Make sure the update to bdp and tx_skbuff are performed 1257 * before dirty_tx 1258 */ 1259 wmb(); 1260 txq->dirty_tx = bdp; 1261 1262 /* Update pointer to next buffer descriptor to be transmitted */ 1263 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1264 1265 /* Since we have freed up a buffer, the ring is no longer full 1266 */ 1267 if (netif_queue_stopped(ndev)) { 1268 entries_free = fec_enet_get_free_txdesc_num(txq); 1269 if (entries_free >= txq->tx_wake_threshold) 1270 netif_tx_wake_queue(nq); 1271 } 1272 } 1273 1274 /* ERR006358: Keep the transmitter going */ 1275 if (bdp != txq->bd.cur && 1276 readl(txq->bd.reg_desc_active) == 0) 1277 writel(0, txq->bd.reg_desc_active); 1278 } 1279 1280 static void 1281 fec_enet_tx(struct net_device *ndev) 1282 { 1283 struct fec_enet_private *fep = netdev_priv(ndev); 1284 u16 queue_id; 1285 /* First process class A queue, then Class B and Best Effort queue */ 1286 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) { 1287 clear_bit(queue_id, &fep->work_tx); 1288 fec_enet_tx_queue(ndev, queue_id); 1289 } 1290 return; 1291 } 1292 1293 static int 1294 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1295 { 1296 struct fec_enet_private *fep = netdev_priv(ndev); 1297 int off; 1298 1299 off = ((unsigned long)skb->data) & fep->rx_align; 1300 if (off) 1301 skb_reserve(skb, fep->rx_align + 1 - off); 1302 1303 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1304 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1305 if (net_ratelimit()) 1306 netdev_err(ndev, "Rx DMA memory map failed\n"); 1307 return -ENOMEM; 1308 } 1309 1310 return 0; 1311 } 1312 1313 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1314 struct bufdesc *bdp, u32 length, bool swap) 1315 { 1316 struct fec_enet_private *fep = netdev_priv(ndev); 1317 struct sk_buff *new_skb; 1318 1319 if (length > fep->rx_copybreak) 1320 return false; 1321 1322 new_skb = netdev_alloc_skb(ndev, length); 1323 if (!new_skb) 1324 return false; 1325 1326 dma_sync_single_for_cpu(&fep->pdev->dev, 1327 fec32_to_cpu(bdp->cbd_bufaddr), 1328 FEC_ENET_RX_FRSIZE - fep->rx_align, 1329 DMA_FROM_DEVICE); 1330 if (!swap) 1331 memcpy(new_skb->data, (*skb)->data, length); 1332 else 1333 swap_buffer2(new_skb->data, (*skb)->data, length); 1334 *skb = new_skb; 1335 1336 return true; 1337 } 1338 1339 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1340 * When we update through the ring, if the next incoming buffer has 1341 * not been given to the system, we just set the empty indicator, 1342 * effectively tossing the packet. 1343 */ 1344 static int 1345 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1346 { 1347 struct fec_enet_private *fep = netdev_priv(ndev); 1348 struct fec_enet_priv_rx_q *rxq; 1349 struct bufdesc *bdp; 1350 unsigned short status; 1351 struct sk_buff *skb_new = NULL; 1352 struct sk_buff *skb; 1353 ushort pkt_len; 1354 __u8 *data; 1355 int pkt_received = 0; 1356 struct bufdesc_ex *ebdp = NULL; 1357 bool vlan_packet_rcvd = false; 1358 u16 vlan_tag; 1359 int index = 0; 1360 bool is_copybreak; 1361 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1362 1363 #ifdef CONFIG_M532x 1364 flush_cache_all(); 1365 #endif 1366 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1367 rxq = fep->rx_queue[queue_id]; 1368 1369 /* First, grab all of the stats for the incoming packet. 1370 * These get messed up if we get called due to a busy condition. 1371 */ 1372 bdp = rxq->bd.cur; 1373 1374 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1375 1376 if (pkt_received >= budget) 1377 break; 1378 pkt_received++; 1379 1380 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); 1381 1382 /* Check for errors. */ 1383 status ^= BD_ENET_RX_LAST; 1384 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1385 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1386 BD_ENET_RX_CL)) { 1387 ndev->stats.rx_errors++; 1388 if (status & BD_ENET_RX_OV) { 1389 /* FIFO overrun */ 1390 ndev->stats.rx_fifo_errors++; 1391 goto rx_processing_done; 1392 } 1393 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1394 | BD_ENET_RX_LAST)) { 1395 /* Frame too long or too short. */ 1396 ndev->stats.rx_length_errors++; 1397 if (status & BD_ENET_RX_LAST) 1398 netdev_err(ndev, "rcv is not +last\n"); 1399 } 1400 if (status & BD_ENET_RX_CR) /* CRC Error */ 1401 ndev->stats.rx_crc_errors++; 1402 /* Report late collisions as a frame error. */ 1403 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1404 ndev->stats.rx_frame_errors++; 1405 goto rx_processing_done; 1406 } 1407 1408 /* Process the incoming frame. */ 1409 ndev->stats.rx_packets++; 1410 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1411 ndev->stats.rx_bytes += pkt_len; 1412 1413 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1414 skb = rxq->rx_skbuff[index]; 1415 1416 /* The packet length includes FCS, but we don't want to 1417 * include that when passing upstream as it messes up 1418 * bridging applications. 1419 */ 1420 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1421 need_swap); 1422 if (!is_copybreak) { 1423 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1424 if (unlikely(!skb_new)) { 1425 ndev->stats.rx_dropped++; 1426 goto rx_processing_done; 1427 } 1428 dma_unmap_single(&fep->pdev->dev, 1429 fec32_to_cpu(bdp->cbd_bufaddr), 1430 FEC_ENET_RX_FRSIZE - fep->rx_align, 1431 DMA_FROM_DEVICE); 1432 } 1433 1434 prefetch(skb->data - NET_IP_ALIGN); 1435 skb_put(skb, pkt_len - 4); 1436 data = skb->data; 1437 1438 if (!is_copybreak && need_swap) 1439 swap_buffer(data, pkt_len); 1440 1441 #if !defined(CONFIG_M5272) 1442 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1443 data = skb_pull_inline(skb, 2); 1444 #endif 1445 1446 /* Extract the enhanced buffer descriptor */ 1447 ebdp = NULL; 1448 if (fep->bufdesc_ex) 1449 ebdp = (struct bufdesc_ex *)bdp; 1450 1451 /* If this is a VLAN packet remove the VLAN Tag */ 1452 vlan_packet_rcvd = false; 1453 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1454 fep->bufdesc_ex && 1455 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1456 /* Push and remove the vlan tag */ 1457 struct vlan_hdr *vlan_header = 1458 (struct vlan_hdr *) (data + ETH_HLEN); 1459 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1460 1461 vlan_packet_rcvd = true; 1462 1463 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1464 skb_pull(skb, VLAN_HLEN); 1465 } 1466 1467 skb->protocol = eth_type_trans(skb, ndev); 1468 1469 /* Get receive timestamp from the skb */ 1470 if (fep->hwts_rx_en && fep->bufdesc_ex) 1471 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1472 skb_hwtstamps(skb)); 1473 1474 if (fep->bufdesc_ex && 1475 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1476 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1477 /* don't check it */ 1478 skb->ip_summed = CHECKSUM_UNNECESSARY; 1479 } else { 1480 skb_checksum_none_assert(skb); 1481 } 1482 } 1483 1484 /* Handle received VLAN packets */ 1485 if (vlan_packet_rcvd) 1486 __vlan_hwaccel_put_tag(skb, 1487 htons(ETH_P_8021Q), 1488 vlan_tag); 1489 1490 napi_gro_receive(&fep->napi, skb); 1491 1492 if (is_copybreak) { 1493 dma_sync_single_for_device(&fep->pdev->dev, 1494 fec32_to_cpu(bdp->cbd_bufaddr), 1495 FEC_ENET_RX_FRSIZE - fep->rx_align, 1496 DMA_FROM_DEVICE); 1497 } else { 1498 rxq->rx_skbuff[index] = skb_new; 1499 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1500 } 1501 1502 rx_processing_done: 1503 /* Clear the status flags for this buffer */ 1504 status &= ~BD_ENET_RX_STATS; 1505 1506 /* Mark the buffer empty */ 1507 status |= BD_ENET_RX_EMPTY; 1508 1509 if (fep->bufdesc_ex) { 1510 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1511 1512 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1513 ebdp->cbd_prot = 0; 1514 ebdp->cbd_bdu = 0; 1515 } 1516 /* Make sure the updates to rest of the descriptor are 1517 * performed before transferring ownership. 1518 */ 1519 wmb(); 1520 bdp->cbd_sc = cpu_to_fec16(status); 1521 1522 /* Update BD pointer to next entry */ 1523 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1524 1525 /* Doing this here will keep the FEC running while we process 1526 * incoming frames. On a heavily loaded network, we should be 1527 * able to keep up at the expense of system resources. 1528 */ 1529 writel(0, rxq->bd.reg_desc_active); 1530 } 1531 rxq->bd.cur = bdp; 1532 return pkt_received; 1533 } 1534 1535 static int 1536 fec_enet_rx(struct net_device *ndev, int budget) 1537 { 1538 int pkt_received = 0; 1539 u16 queue_id; 1540 struct fec_enet_private *fep = netdev_priv(ndev); 1541 1542 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) { 1543 int ret; 1544 1545 ret = fec_enet_rx_queue(ndev, 1546 budget - pkt_received, queue_id); 1547 1548 if (ret < budget - pkt_received) 1549 clear_bit(queue_id, &fep->work_rx); 1550 1551 pkt_received += ret; 1552 } 1553 return pkt_received; 1554 } 1555 1556 static bool 1557 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events) 1558 { 1559 if (int_events == 0) 1560 return false; 1561 1562 if (int_events & FEC_ENET_RXF_0) 1563 fep->work_rx |= (1 << 2); 1564 if (int_events & FEC_ENET_RXF_1) 1565 fep->work_rx |= (1 << 0); 1566 if (int_events & FEC_ENET_RXF_2) 1567 fep->work_rx |= (1 << 1); 1568 1569 if (int_events & FEC_ENET_TXF_0) 1570 fep->work_tx |= (1 << 2); 1571 if (int_events & FEC_ENET_TXF_1) 1572 fep->work_tx |= (1 << 0); 1573 if (int_events & FEC_ENET_TXF_2) 1574 fep->work_tx |= (1 << 1); 1575 1576 return true; 1577 } 1578 1579 static irqreturn_t 1580 fec_enet_interrupt(int irq, void *dev_id) 1581 { 1582 struct net_device *ndev = dev_id; 1583 struct fec_enet_private *fep = netdev_priv(ndev); 1584 uint int_events; 1585 irqreturn_t ret = IRQ_NONE; 1586 1587 int_events = readl(fep->hwp + FEC_IEVENT); 1588 writel(int_events, fep->hwp + FEC_IEVENT); 1589 fec_enet_collect_events(fep, int_events); 1590 1591 if ((fep->work_tx || fep->work_rx) && fep->link) { 1592 ret = IRQ_HANDLED; 1593 1594 if (napi_schedule_prep(&fep->napi)) { 1595 /* Disable the NAPI interrupts */ 1596 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK); 1597 __napi_schedule(&fep->napi); 1598 } 1599 } 1600 1601 if (int_events & FEC_ENET_MII) { 1602 ret = IRQ_HANDLED; 1603 complete(&fep->mdio_done); 1604 } 1605 1606 if (fep->ptp_clock) 1607 if (fec_ptp_check_pps_event(fep)) 1608 ret = IRQ_HANDLED; 1609 return ret; 1610 } 1611 1612 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1613 { 1614 struct net_device *ndev = napi->dev; 1615 struct fec_enet_private *fep = netdev_priv(ndev); 1616 int pkts; 1617 1618 pkts = fec_enet_rx(ndev, budget); 1619 1620 fec_enet_tx(ndev); 1621 1622 if (pkts < budget) { 1623 napi_complete_done(napi, pkts); 1624 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1625 } 1626 return pkts; 1627 } 1628 1629 /* ------------------------------------------------------------------------- */ 1630 static void fec_get_mac(struct net_device *ndev) 1631 { 1632 struct fec_enet_private *fep = netdev_priv(ndev); 1633 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1634 unsigned char *iap, tmpaddr[ETH_ALEN]; 1635 1636 /* 1637 * try to get mac address in following order: 1638 * 1639 * 1) module parameter via kernel command line in form 1640 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1641 */ 1642 iap = macaddr; 1643 1644 /* 1645 * 2) from device tree data 1646 */ 1647 if (!is_valid_ether_addr(iap)) { 1648 struct device_node *np = fep->pdev->dev.of_node; 1649 if (np) { 1650 const char *mac = of_get_mac_address(np); 1651 if (mac) 1652 iap = (unsigned char *) mac; 1653 } 1654 } 1655 1656 /* 1657 * 3) from flash or fuse (via platform data) 1658 */ 1659 if (!is_valid_ether_addr(iap)) { 1660 #ifdef CONFIG_M5272 1661 if (FEC_FLASHMAC) 1662 iap = (unsigned char *)FEC_FLASHMAC; 1663 #else 1664 if (pdata) 1665 iap = (unsigned char *)&pdata->mac; 1666 #endif 1667 } 1668 1669 /* 1670 * 4) FEC mac registers set by bootloader 1671 */ 1672 if (!is_valid_ether_addr(iap)) { 1673 *((__be32 *) &tmpaddr[0]) = 1674 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1675 *((__be16 *) &tmpaddr[4]) = 1676 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1677 iap = &tmpaddr[0]; 1678 } 1679 1680 /* 1681 * 5) random mac address 1682 */ 1683 if (!is_valid_ether_addr(iap)) { 1684 /* Report it and use a random ethernet address instead */ 1685 netdev_err(ndev, "Invalid MAC address: %pM\n", iap); 1686 eth_hw_addr_random(ndev); 1687 netdev_info(ndev, "Using random MAC address: %pM\n", 1688 ndev->dev_addr); 1689 return; 1690 } 1691 1692 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1693 1694 /* Adjust MAC if using macaddr */ 1695 if (iap == macaddr) 1696 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1697 } 1698 1699 /* ------------------------------------------------------------------------- */ 1700 1701 /* 1702 * Phy section 1703 */ 1704 static void fec_enet_adjust_link(struct net_device *ndev) 1705 { 1706 struct fec_enet_private *fep = netdev_priv(ndev); 1707 struct phy_device *phy_dev = ndev->phydev; 1708 int status_change = 0; 1709 1710 /* Prevent a state halted on mii error */ 1711 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 1712 phy_dev->state = PHY_RESUMING; 1713 return; 1714 } 1715 1716 /* 1717 * If the netdev is down, or is going down, we're not interested 1718 * in link state events, so just mark our idea of the link as down 1719 * and ignore the event. 1720 */ 1721 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1722 fep->link = 0; 1723 } else if (phy_dev->link) { 1724 if (!fep->link) { 1725 fep->link = phy_dev->link; 1726 status_change = 1; 1727 } 1728 1729 if (fep->full_duplex != phy_dev->duplex) { 1730 fep->full_duplex = phy_dev->duplex; 1731 status_change = 1; 1732 } 1733 1734 if (phy_dev->speed != fep->speed) { 1735 fep->speed = phy_dev->speed; 1736 status_change = 1; 1737 } 1738 1739 /* if any of the above changed restart the FEC */ 1740 if (status_change) { 1741 napi_disable(&fep->napi); 1742 netif_tx_lock_bh(ndev); 1743 fec_restart(ndev); 1744 netif_wake_queue(ndev); 1745 netif_tx_unlock_bh(ndev); 1746 napi_enable(&fep->napi); 1747 } 1748 } else { 1749 if (fep->link) { 1750 napi_disable(&fep->napi); 1751 netif_tx_lock_bh(ndev); 1752 fec_stop(ndev); 1753 netif_tx_unlock_bh(ndev); 1754 napi_enable(&fep->napi); 1755 fep->link = phy_dev->link; 1756 status_change = 1; 1757 } 1758 } 1759 1760 if (status_change) 1761 phy_print_status(phy_dev); 1762 } 1763 1764 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1765 { 1766 struct fec_enet_private *fep = bus->priv; 1767 struct device *dev = &fep->pdev->dev; 1768 unsigned long time_left; 1769 int ret = 0; 1770 1771 ret = pm_runtime_get_sync(dev); 1772 if (ret < 0) 1773 return ret; 1774 1775 fep->mii_timeout = 0; 1776 reinit_completion(&fep->mdio_done); 1777 1778 /* start a read op */ 1779 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 1780 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1781 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1782 1783 /* wait for end of transfer */ 1784 time_left = wait_for_completion_timeout(&fep->mdio_done, 1785 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1786 if (time_left == 0) { 1787 fep->mii_timeout = 1; 1788 netdev_err(fep->netdev, "MDIO read timeout\n"); 1789 ret = -ETIMEDOUT; 1790 goto out; 1791 } 1792 1793 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1794 1795 out: 1796 pm_runtime_mark_last_busy(dev); 1797 pm_runtime_put_autosuspend(dev); 1798 1799 return ret; 1800 } 1801 1802 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1803 u16 value) 1804 { 1805 struct fec_enet_private *fep = bus->priv; 1806 struct device *dev = &fep->pdev->dev; 1807 unsigned long time_left; 1808 int ret; 1809 1810 ret = pm_runtime_get_sync(dev); 1811 if (ret < 0) 1812 return ret; 1813 else 1814 ret = 0; 1815 1816 fep->mii_timeout = 0; 1817 reinit_completion(&fep->mdio_done); 1818 1819 /* start a write op */ 1820 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 1821 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1822 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1823 fep->hwp + FEC_MII_DATA); 1824 1825 /* wait for end of transfer */ 1826 time_left = wait_for_completion_timeout(&fep->mdio_done, 1827 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1828 if (time_left == 0) { 1829 fep->mii_timeout = 1; 1830 netdev_err(fep->netdev, "MDIO write timeout\n"); 1831 ret = -ETIMEDOUT; 1832 } 1833 1834 pm_runtime_mark_last_busy(dev); 1835 pm_runtime_put_autosuspend(dev); 1836 1837 return ret; 1838 } 1839 1840 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1841 { 1842 struct fec_enet_private *fep = netdev_priv(ndev); 1843 int ret; 1844 1845 if (enable) { 1846 ret = clk_prepare_enable(fep->clk_ahb); 1847 if (ret) 1848 return ret; 1849 1850 ret = clk_prepare_enable(fep->clk_enet_out); 1851 if (ret) 1852 goto failed_clk_enet_out; 1853 1854 if (fep->clk_ptp) { 1855 mutex_lock(&fep->ptp_clk_mutex); 1856 ret = clk_prepare_enable(fep->clk_ptp); 1857 if (ret) { 1858 mutex_unlock(&fep->ptp_clk_mutex); 1859 goto failed_clk_ptp; 1860 } else { 1861 fep->ptp_clk_on = true; 1862 } 1863 mutex_unlock(&fep->ptp_clk_mutex); 1864 } 1865 1866 ret = clk_prepare_enable(fep->clk_ref); 1867 if (ret) 1868 goto failed_clk_ref; 1869 } else { 1870 clk_disable_unprepare(fep->clk_ahb); 1871 clk_disable_unprepare(fep->clk_enet_out); 1872 if (fep->clk_ptp) { 1873 mutex_lock(&fep->ptp_clk_mutex); 1874 clk_disable_unprepare(fep->clk_ptp); 1875 fep->ptp_clk_on = false; 1876 mutex_unlock(&fep->ptp_clk_mutex); 1877 } 1878 clk_disable_unprepare(fep->clk_ref); 1879 } 1880 1881 return 0; 1882 1883 failed_clk_ref: 1884 if (fep->clk_ref) 1885 clk_disable_unprepare(fep->clk_ref); 1886 failed_clk_ptp: 1887 if (fep->clk_enet_out) 1888 clk_disable_unprepare(fep->clk_enet_out); 1889 failed_clk_enet_out: 1890 clk_disable_unprepare(fep->clk_ahb); 1891 1892 return ret; 1893 } 1894 1895 static int fec_enet_mii_probe(struct net_device *ndev) 1896 { 1897 struct fec_enet_private *fep = netdev_priv(ndev); 1898 struct phy_device *phy_dev = NULL; 1899 char mdio_bus_id[MII_BUS_ID_SIZE]; 1900 char phy_name[MII_BUS_ID_SIZE + 3]; 1901 int phy_id; 1902 int dev_id = fep->dev_id; 1903 1904 if (fep->phy_node) { 1905 phy_dev = of_phy_connect(ndev, fep->phy_node, 1906 &fec_enet_adjust_link, 0, 1907 fep->phy_interface); 1908 if (!phy_dev) { 1909 netdev_err(ndev, "Unable to connect to phy\n"); 1910 return -ENODEV; 1911 } 1912 } else { 1913 /* check for attached phy */ 1914 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1915 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 1916 continue; 1917 if (dev_id--) 1918 continue; 1919 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1920 break; 1921 } 1922 1923 if (phy_id >= PHY_MAX_ADDR) { 1924 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1925 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 1926 phy_id = 0; 1927 } 1928 1929 snprintf(phy_name, sizeof(phy_name), 1930 PHY_ID_FMT, mdio_bus_id, phy_id); 1931 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 1932 fep->phy_interface); 1933 } 1934 1935 if (IS_ERR(phy_dev)) { 1936 netdev_err(ndev, "could not attach to PHY\n"); 1937 return PTR_ERR(phy_dev); 1938 } 1939 1940 /* mask with MAC supported features */ 1941 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 1942 phy_dev->supported &= PHY_GBIT_FEATURES; 1943 phy_dev->supported &= ~SUPPORTED_1000baseT_Half; 1944 #if !defined(CONFIG_M5272) 1945 phy_dev->supported |= SUPPORTED_Pause; 1946 #endif 1947 } 1948 else 1949 phy_dev->supported &= PHY_BASIC_FEATURES; 1950 1951 phy_dev->advertising = phy_dev->supported; 1952 1953 fep->link = 0; 1954 fep->full_duplex = 0; 1955 1956 phy_attached_info(phy_dev); 1957 1958 return 0; 1959 } 1960 1961 static int fec_enet_mii_init(struct platform_device *pdev) 1962 { 1963 static struct mii_bus *fec0_mii_bus; 1964 struct net_device *ndev = platform_get_drvdata(pdev); 1965 struct fec_enet_private *fep = netdev_priv(ndev); 1966 struct device_node *node; 1967 int err = -ENXIO; 1968 u32 mii_speed, holdtime; 1969 1970 /* 1971 * The i.MX28 dual fec interfaces are not equal. 1972 * Here are the differences: 1973 * 1974 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1975 * - fec0 acts as the 1588 time master while fec1 is slave 1976 * - external phys can only be configured by fec0 1977 * 1978 * That is to say fec1 can not work independently. It only works 1979 * when fec0 is working. The reason behind this design is that the 1980 * second interface is added primarily for Switch mode. 1981 * 1982 * Because of the last point above, both phys are attached on fec0 1983 * mdio interface in board design, and need to be configured by 1984 * fec0 mii_bus. 1985 */ 1986 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 1987 /* fec1 uses fec0 mii_bus */ 1988 if (mii_cnt && fec0_mii_bus) { 1989 fep->mii_bus = fec0_mii_bus; 1990 mii_cnt++; 1991 return 0; 1992 } 1993 return -ENOENT; 1994 } 1995 1996 fep->mii_timeout = 0; 1997 1998 /* 1999 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 2000 * 2001 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2002 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2003 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2004 * document. 2005 */ 2006 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000); 2007 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2008 mii_speed--; 2009 if (mii_speed > 63) { 2010 dev_err(&pdev->dev, 2011 "fec clock (%lu) too fast to get right mii speed\n", 2012 clk_get_rate(fep->clk_ipg)); 2013 err = -EINVAL; 2014 goto err_out; 2015 } 2016 2017 /* 2018 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2019 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2020 * versions are RAZ there, so just ignore the difference and write the 2021 * register always. 2022 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2023 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2024 * output. 2025 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2026 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2027 * holdtime cannot result in a value greater than 3. 2028 */ 2029 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2030 2031 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2032 2033 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2034 2035 fep->mii_bus = mdiobus_alloc(); 2036 if (fep->mii_bus == NULL) { 2037 err = -ENOMEM; 2038 goto err_out; 2039 } 2040 2041 fep->mii_bus->name = "fec_enet_mii_bus"; 2042 fep->mii_bus->read = fec_enet_mdio_read; 2043 fep->mii_bus->write = fec_enet_mdio_write; 2044 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2045 pdev->name, fep->dev_id + 1); 2046 fep->mii_bus->priv = fep; 2047 fep->mii_bus->parent = &pdev->dev; 2048 2049 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2050 if (node) { 2051 err = of_mdiobus_register(fep->mii_bus, node); 2052 of_node_put(node); 2053 } else { 2054 err = mdiobus_register(fep->mii_bus); 2055 } 2056 2057 if (err) 2058 goto err_out_free_mdiobus; 2059 2060 mii_cnt++; 2061 2062 /* save fec0 mii_bus */ 2063 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2064 fec0_mii_bus = fep->mii_bus; 2065 2066 return 0; 2067 2068 err_out_free_mdiobus: 2069 mdiobus_free(fep->mii_bus); 2070 err_out: 2071 return err; 2072 } 2073 2074 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2075 { 2076 if (--mii_cnt == 0) { 2077 mdiobus_unregister(fep->mii_bus); 2078 mdiobus_free(fep->mii_bus); 2079 } 2080 } 2081 2082 static void fec_enet_get_drvinfo(struct net_device *ndev, 2083 struct ethtool_drvinfo *info) 2084 { 2085 struct fec_enet_private *fep = netdev_priv(ndev); 2086 2087 strlcpy(info->driver, fep->pdev->dev.driver->name, 2088 sizeof(info->driver)); 2089 strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); 2090 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2091 } 2092 2093 static int fec_enet_get_regs_len(struct net_device *ndev) 2094 { 2095 struct fec_enet_private *fep = netdev_priv(ndev); 2096 struct resource *r; 2097 int s = 0; 2098 2099 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2100 if (r) 2101 s = resource_size(r); 2102 2103 return s; 2104 } 2105 2106 /* List of registers that can be safety be read to dump them with ethtool */ 2107 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2108 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 2109 static u32 fec_enet_register_offset[] = { 2110 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2111 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2112 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2113 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2114 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2115 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2116 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2117 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2118 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2119 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2120 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2121 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2122 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2123 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2124 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2125 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2126 RMON_T_P_GTE2048, RMON_T_OCTETS, 2127 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2128 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2129 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2130 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2131 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2132 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2133 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2134 RMON_R_P_GTE2048, RMON_R_OCTETS, 2135 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2136 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2137 }; 2138 #else 2139 static u32 fec_enet_register_offset[] = { 2140 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2141 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2142 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2143 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2144 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2145 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2146 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2147 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2148 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2149 }; 2150 #endif 2151 2152 static void fec_enet_get_regs(struct net_device *ndev, 2153 struct ethtool_regs *regs, void *regbuf) 2154 { 2155 struct fec_enet_private *fep = netdev_priv(ndev); 2156 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2157 u32 *buf = (u32 *)regbuf; 2158 u32 i, off; 2159 2160 memset(buf, 0, regs->len); 2161 2162 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2163 off = fec_enet_register_offset[i] / 4; 2164 buf[off] = readl(&theregs[off]); 2165 } 2166 } 2167 2168 static int fec_enet_get_ts_info(struct net_device *ndev, 2169 struct ethtool_ts_info *info) 2170 { 2171 struct fec_enet_private *fep = netdev_priv(ndev); 2172 2173 if (fep->bufdesc_ex) { 2174 2175 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2176 SOF_TIMESTAMPING_RX_SOFTWARE | 2177 SOF_TIMESTAMPING_SOFTWARE | 2178 SOF_TIMESTAMPING_TX_HARDWARE | 2179 SOF_TIMESTAMPING_RX_HARDWARE | 2180 SOF_TIMESTAMPING_RAW_HARDWARE; 2181 if (fep->ptp_clock) 2182 info->phc_index = ptp_clock_index(fep->ptp_clock); 2183 else 2184 info->phc_index = -1; 2185 2186 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2187 (1 << HWTSTAMP_TX_ON); 2188 2189 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2190 (1 << HWTSTAMP_FILTER_ALL); 2191 return 0; 2192 } else { 2193 return ethtool_op_get_ts_info(ndev, info); 2194 } 2195 } 2196 2197 #if !defined(CONFIG_M5272) 2198 2199 static void fec_enet_get_pauseparam(struct net_device *ndev, 2200 struct ethtool_pauseparam *pause) 2201 { 2202 struct fec_enet_private *fep = netdev_priv(ndev); 2203 2204 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2205 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2206 pause->rx_pause = pause->tx_pause; 2207 } 2208 2209 static int fec_enet_set_pauseparam(struct net_device *ndev, 2210 struct ethtool_pauseparam *pause) 2211 { 2212 struct fec_enet_private *fep = netdev_priv(ndev); 2213 2214 if (!ndev->phydev) 2215 return -ENODEV; 2216 2217 if (pause->tx_pause != pause->rx_pause) { 2218 netdev_info(ndev, 2219 "hardware only support enable/disable both tx and rx"); 2220 return -EINVAL; 2221 } 2222 2223 fep->pause_flag = 0; 2224 2225 /* tx pause must be same as rx pause */ 2226 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2227 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2228 2229 if (pause->rx_pause || pause->autoneg) { 2230 ndev->phydev->supported |= ADVERTISED_Pause; 2231 ndev->phydev->advertising |= ADVERTISED_Pause; 2232 } else { 2233 ndev->phydev->supported &= ~ADVERTISED_Pause; 2234 ndev->phydev->advertising &= ~ADVERTISED_Pause; 2235 } 2236 2237 if (pause->autoneg) { 2238 if (netif_running(ndev)) 2239 fec_stop(ndev); 2240 phy_start_aneg(ndev->phydev); 2241 } 2242 if (netif_running(ndev)) { 2243 napi_disable(&fep->napi); 2244 netif_tx_lock_bh(ndev); 2245 fec_restart(ndev); 2246 netif_wake_queue(ndev); 2247 netif_tx_unlock_bh(ndev); 2248 napi_enable(&fep->napi); 2249 } 2250 2251 return 0; 2252 } 2253 2254 static const struct fec_stat { 2255 char name[ETH_GSTRING_LEN]; 2256 u16 offset; 2257 } fec_stats[] = { 2258 /* RMON TX */ 2259 { "tx_dropped", RMON_T_DROP }, 2260 { "tx_packets", RMON_T_PACKETS }, 2261 { "tx_broadcast", RMON_T_BC_PKT }, 2262 { "tx_multicast", RMON_T_MC_PKT }, 2263 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2264 { "tx_undersize", RMON_T_UNDERSIZE }, 2265 { "tx_oversize", RMON_T_OVERSIZE }, 2266 { "tx_fragment", RMON_T_FRAG }, 2267 { "tx_jabber", RMON_T_JAB }, 2268 { "tx_collision", RMON_T_COL }, 2269 { "tx_64byte", RMON_T_P64 }, 2270 { "tx_65to127byte", RMON_T_P65TO127 }, 2271 { "tx_128to255byte", RMON_T_P128TO255 }, 2272 { "tx_256to511byte", RMON_T_P256TO511 }, 2273 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2274 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2275 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2276 { "tx_octets", RMON_T_OCTETS }, 2277 2278 /* IEEE TX */ 2279 { "IEEE_tx_drop", IEEE_T_DROP }, 2280 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2281 { "IEEE_tx_1col", IEEE_T_1COL }, 2282 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2283 { "IEEE_tx_def", IEEE_T_DEF }, 2284 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2285 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2286 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2287 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2288 { "IEEE_tx_sqe", IEEE_T_SQE }, 2289 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2290 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2291 2292 /* RMON RX */ 2293 { "rx_packets", RMON_R_PACKETS }, 2294 { "rx_broadcast", RMON_R_BC_PKT }, 2295 { "rx_multicast", RMON_R_MC_PKT }, 2296 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2297 { "rx_undersize", RMON_R_UNDERSIZE }, 2298 { "rx_oversize", RMON_R_OVERSIZE }, 2299 { "rx_fragment", RMON_R_FRAG }, 2300 { "rx_jabber", RMON_R_JAB }, 2301 { "rx_64byte", RMON_R_P64 }, 2302 { "rx_65to127byte", RMON_R_P65TO127 }, 2303 { "rx_128to255byte", RMON_R_P128TO255 }, 2304 { "rx_256to511byte", RMON_R_P256TO511 }, 2305 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2306 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2307 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2308 { "rx_octets", RMON_R_OCTETS }, 2309 2310 /* IEEE RX */ 2311 { "IEEE_rx_drop", IEEE_R_DROP }, 2312 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2313 { "IEEE_rx_crc", IEEE_R_CRC }, 2314 { "IEEE_rx_align", IEEE_R_ALIGN }, 2315 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2316 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2317 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2318 }; 2319 2320 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2321 2322 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2323 { 2324 struct fec_enet_private *fep = netdev_priv(dev); 2325 int i; 2326 2327 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2328 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2329 } 2330 2331 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2332 struct ethtool_stats *stats, u64 *data) 2333 { 2334 struct fec_enet_private *fep = netdev_priv(dev); 2335 2336 if (netif_running(dev)) 2337 fec_enet_update_ethtool_stats(dev); 2338 2339 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2340 } 2341 2342 static void fec_enet_get_strings(struct net_device *netdev, 2343 u32 stringset, u8 *data) 2344 { 2345 int i; 2346 switch (stringset) { 2347 case ETH_SS_STATS: 2348 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2349 memcpy(data + i * ETH_GSTRING_LEN, 2350 fec_stats[i].name, ETH_GSTRING_LEN); 2351 break; 2352 } 2353 } 2354 2355 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2356 { 2357 switch (sset) { 2358 case ETH_SS_STATS: 2359 return ARRAY_SIZE(fec_stats); 2360 default: 2361 return -EOPNOTSUPP; 2362 } 2363 } 2364 2365 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2366 { 2367 struct fec_enet_private *fep = netdev_priv(dev); 2368 int i; 2369 2370 /* Disable MIB statistics counters */ 2371 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2372 2373 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2374 writel(0, fep->hwp + fec_stats[i].offset); 2375 2376 /* Don't disable MIB statistics counters */ 2377 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2378 } 2379 2380 #else /* !defined(CONFIG_M5272) */ 2381 #define FEC_STATS_SIZE 0 2382 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2383 { 2384 } 2385 2386 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2387 { 2388 } 2389 #endif /* !defined(CONFIG_M5272) */ 2390 2391 /* ITR clock source is enet system clock (clk_ahb). 2392 * TCTT unit is cycle_ns * 64 cycle 2393 * So, the ICTT value = X us / (cycle_ns * 64) 2394 */ 2395 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2396 { 2397 struct fec_enet_private *fep = netdev_priv(ndev); 2398 2399 return us * (fep->itr_clk_rate / 64000) / 1000; 2400 } 2401 2402 /* Set threshold for interrupt coalescing */ 2403 static void fec_enet_itr_coal_set(struct net_device *ndev) 2404 { 2405 struct fec_enet_private *fep = netdev_priv(ndev); 2406 int rx_itr, tx_itr; 2407 2408 /* Must be greater than zero to avoid unpredictable behavior */ 2409 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2410 !fep->tx_time_itr || !fep->tx_pkts_itr) 2411 return; 2412 2413 /* Select enet system clock as Interrupt Coalescing 2414 * timer Clock Source 2415 */ 2416 rx_itr = FEC_ITR_CLK_SEL; 2417 tx_itr = FEC_ITR_CLK_SEL; 2418 2419 /* set ICFT and ICTT */ 2420 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2421 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2422 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2423 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2424 2425 rx_itr |= FEC_ITR_EN; 2426 tx_itr |= FEC_ITR_EN; 2427 2428 writel(tx_itr, fep->hwp + FEC_TXIC0); 2429 writel(rx_itr, fep->hwp + FEC_RXIC0); 2430 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 2431 writel(tx_itr, fep->hwp + FEC_TXIC1); 2432 writel(rx_itr, fep->hwp + FEC_RXIC1); 2433 writel(tx_itr, fep->hwp + FEC_TXIC2); 2434 writel(rx_itr, fep->hwp + FEC_RXIC2); 2435 } 2436 } 2437 2438 static int 2439 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2440 { 2441 struct fec_enet_private *fep = netdev_priv(ndev); 2442 2443 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2444 return -EOPNOTSUPP; 2445 2446 ec->rx_coalesce_usecs = fep->rx_time_itr; 2447 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2448 2449 ec->tx_coalesce_usecs = fep->tx_time_itr; 2450 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2451 2452 return 0; 2453 } 2454 2455 static int 2456 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2457 { 2458 struct fec_enet_private *fep = netdev_priv(ndev); 2459 unsigned int cycle; 2460 2461 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2462 return -EOPNOTSUPP; 2463 2464 if (ec->rx_max_coalesced_frames > 255) { 2465 pr_err("Rx coalesced frames exceed hardware limitation\n"); 2466 return -EINVAL; 2467 } 2468 2469 if (ec->tx_max_coalesced_frames > 255) { 2470 pr_err("Tx coalesced frame exceed hardware limitation\n"); 2471 return -EINVAL; 2472 } 2473 2474 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); 2475 if (cycle > 0xFFFF) { 2476 pr_err("Rx coalesced usec exceed hardware limitation\n"); 2477 return -EINVAL; 2478 } 2479 2480 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); 2481 if (cycle > 0xFFFF) { 2482 pr_err("Rx coalesced usec exceed hardware limitation\n"); 2483 return -EINVAL; 2484 } 2485 2486 fep->rx_time_itr = ec->rx_coalesce_usecs; 2487 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2488 2489 fep->tx_time_itr = ec->tx_coalesce_usecs; 2490 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2491 2492 fec_enet_itr_coal_set(ndev); 2493 2494 return 0; 2495 } 2496 2497 static void fec_enet_itr_coal_init(struct net_device *ndev) 2498 { 2499 struct ethtool_coalesce ec; 2500 2501 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2502 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2503 2504 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2505 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2506 2507 fec_enet_set_coalesce(ndev, &ec); 2508 } 2509 2510 static int fec_enet_get_tunable(struct net_device *netdev, 2511 const struct ethtool_tunable *tuna, 2512 void *data) 2513 { 2514 struct fec_enet_private *fep = netdev_priv(netdev); 2515 int ret = 0; 2516 2517 switch (tuna->id) { 2518 case ETHTOOL_RX_COPYBREAK: 2519 *(u32 *)data = fep->rx_copybreak; 2520 break; 2521 default: 2522 ret = -EINVAL; 2523 break; 2524 } 2525 2526 return ret; 2527 } 2528 2529 static int fec_enet_set_tunable(struct net_device *netdev, 2530 const struct ethtool_tunable *tuna, 2531 const void *data) 2532 { 2533 struct fec_enet_private *fep = netdev_priv(netdev); 2534 int ret = 0; 2535 2536 switch (tuna->id) { 2537 case ETHTOOL_RX_COPYBREAK: 2538 fep->rx_copybreak = *(u32 *)data; 2539 break; 2540 default: 2541 ret = -EINVAL; 2542 break; 2543 } 2544 2545 return ret; 2546 } 2547 2548 static void 2549 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2550 { 2551 struct fec_enet_private *fep = netdev_priv(ndev); 2552 2553 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2554 wol->supported = WAKE_MAGIC; 2555 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2556 } else { 2557 wol->supported = wol->wolopts = 0; 2558 } 2559 } 2560 2561 static int 2562 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2563 { 2564 struct fec_enet_private *fep = netdev_priv(ndev); 2565 2566 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2567 return -EINVAL; 2568 2569 if (wol->wolopts & ~WAKE_MAGIC) 2570 return -EINVAL; 2571 2572 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2573 if (device_may_wakeup(&ndev->dev)) { 2574 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2575 if (fep->irq[0] > 0) 2576 enable_irq_wake(fep->irq[0]); 2577 } else { 2578 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2579 if (fep->irq[0] > 0) 2580 disable_irq_wake(fep->irq[0]); 2581 } 2582 2583 return 0; 2584 } 2585 2586 static const struct ethtool_ops fec_enet_ethtool_ops = { 2587 .get_drvinfo = fec_enet_get_drvinfo, 2588 .get_regs_len = fec_enet_get_regs_len, 2589 .get_regs = fec_enet_get_regs, 2590 .nway_reset = phy_ethtool_nway_reset, 2591 .get_link = ethtool_op_get_link, 2592 .get_coalesce = fec_enet_get_coalesce, 2593 .set_coalesce = fec_enet_set_coalesce, 2594 #ifndef CONFIG_M5272 2595 .get_pauseparam = fec_enet_get_pauseparam, 2596 .set_pauseparam = fec_enet_set_pauseparam, 2597 .get_strings = fec_enet_get_strings, 2598 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2599 .get_sset_count = fec_enet_get_sset_count, 2600 #endif 2601 .get_ts_info = fec_enet_get_ts_info, 2602 .get_tunable = fec_enet_get_tunable, 2603 .set_tunable = fec_enet_set_tunable, 2604 .get_wol = fec_enet_get_wol, 2605 .set_wol = fec_enet_set_wol, 2606 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2607 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2608 }; 2609 2610 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2611 { 2612 struct fec_enet_private *fep = netdev_priv(ndev); 2613 struct phy_device *phydev = ndev->phydev; 2614 2615 if (!netif_running(ndev)) 2616 return -EINVAL; 2617 2618 if (!phydev) 2619 return -ENODEV; 2620 2621 if (fep->bufdesc_ex) { 2622 if (cmd == SIOCSHWTSTAMP) 2623 return fec_ptp_set(ndev, rq); 2624 if (cmd == SIOCGHWTSTAMP) 2625 return fec_ptp_get(ndev, rq); 2626 } 2627 2628 return phy_mii_ioctl(phydev, rq, cmd); 2629 } 2630 2631 static void fec_enet_free_buffers(struct net_device *ndev) 2632 { 2633 struct fec_enet_private *fep = netdev_priv(ndev); 2634 unsigned int i; 2635 struct sk_buff *skb; 2636 struct bufdesc *bdp; 2637 struct fec_enet_priv_tx_q *txq; 2638 struct fec_enet_priv_rx_q *rxq; 2639 unsigned int q; 2640 2641 for (q = 0; q < fep->num_rx_queues; q++) { 2642 rxq = fep->rx_queue[q]; 2643 bdp = rxq->bd.base; 2644 for (i = 0; i < rxq->bd.ring_size; i++) { 2645 skb = rxq->rx_skbuff[i]; 2646 rxq->rx_skbuff[i] = NULL; 2647 if (skb) { 2648 dma_unmap_single(&fep->pdev->dev, 2649 fec32_to_cpu(bdp->cbd_bufaddr), 2650 FEC_ENET_RX_FRSIZE - fep->rx_align, 2651 DMA_FROM_DEVICE); 2652 dev_kfree_skb(skb); 2653 } 2654 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2655 } 2656 } 2657 2658 for (q = 0; q < fep->num_tx_queues; q++) { 2659 txq = fep->tx_queue[q]; 2660 bdp = txq->bd.base; 2661 for (i = 0; i < txq->bd.ring_size; i++) { 2662 kfree(txq->tx_bounce[i]); 2663 txq->tx_bounce[i] = NULL; 2664 skb = txq->tx_skbuff[i]; 2665 txq->tx_skbuff[i] = NULL; 2666 dev_kfree_skb(skb); 2667 } 2668 } 2669 } 2670 2671 static void fec_enet_free_queue(struct net_device *ndev) 2672 { 2673 struct fec_enet_private *fep = netdev_priv(ndev); 2674 int i; 2675 struct fec_enet_priv_tx_q *txq; 2676 2677 for (i = 0; i < fep->num_tx_queues; i++) 2678 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2679 txq = fep->tx_queue[i]; 2680 dma_free_coherent(&fep->pdev->dev, 2681 txq->bd.ring_size * TSO_HEADER_SIZE, 2682 txq->tso_hdrs, 2683 txq->tso_hdrs_dma); 2684 } 2685 2686 for (i = 0; i < fep->num_rx_queues; i++) 2687 kfree(fep->rx_queue[i]); 2688 for (i = 0; i < fep->num_tx_queues; i++) 2689 kfree(fep->tx_queue[i]); 2690 } 2691 2692 static int fec_enet_alloc_queue(struct net_device *ndev) 2693 { 2694 struct fec_enet_private *fep = netdev_priv(ndev); 2695 int i; 2696 int ret = 0; 2697 struct fec_enet_priv_tx_q *txq; 2698 2699 for (i = 0; i < fep->num_tx_queues; i++) { 2700 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 2701 if (!txq) { 2702 ret = -ENOMEM; 2703 goto alloc_failed; 2704 } 2705 2706 fep->tx_queue[i] = txq; 2707 txq->bd.ring_size = TX_RING_SIZE; 2708 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 2709 2710 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2711 txq->tx_wake_threshold = 2712 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 2713 2714 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 2715 txq->bd.ring_size * TSO_HEADER_SIZE, 2716 &txq->tso_hdrs_dma, 2717 GFP_KERNEL); 2718 if (!txq->tso_hdrs) { 2719 ret = -ENOMEM; 2720 goto alloc_failed; 2721 } 2722 } 2723 2724 for (i = 0; i < fep->num_rx_queues; i++) { 2725 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 2726 GFP_KERNEL); 2727 if (!fep->rx_queue[i]) { 2728 ret = -ENOMEM; 2729 goto alloc_failed; 2730 } 2731 2732 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 2733 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 2734 } 2735 return ret; 2736 2737 alloc_failed: 2738 fec_enet_free_queue(ndev); 2739 return ret; 2740 } 2741 2742 static int 2743 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 2744 { 2745 struct fec_enet_private *fep = netdev_priv(ndev); 2746 unsigned int i; 2747 struct sk_buff *skb; 2748 struct bufdesc *bdp; 2749 struct fec_enet_priv_rx_q *rxq; 2750 2751 rxq = fep->rx_queue[queue]; 2752 bdp = rxq->bd.base; 2753 for (i = 0; i < rxq->bd.ring_size; i++) { 2754 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2755 if (!skb) 2756 goto err_alloc; 2757 2758 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 2759 dev_kfree_skb(skb); 2760 goto err_alloc; 2761 } 2762 2763 rxq->rx_skbuff[i] = skb; 2764 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 2765 2766 if (fep->bufdesc_ex) { 2767 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2768 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 2769 } 2770 2771 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2772 } 2773 2774 /* Set the last buffer to wrap. */ 2775 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 2776 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2777 return 0; 2778 2779 err_alloc: 2780 fec_enet_free_buffers(ndev); 2781 return -ENOMEM; 2782 } 2783 2784 static int 2785 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 2786 { 2787 struct fec_enet_private *fep = netdev_priv(ndev); 2788 unsigned int i; 2789 struct bufdesc *bdp; 2790 struct fec_enet_priv_tx_q *txq; 2791 2792 txq = fep->tx_queue[queue]; 2793 bdp = txq->bd.base; 2794 for (i = 0; i < txq->bd.ring_size; i++) { 2795 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2796 if (!txq->tx_bounce[i]) 2797 goto err_alloc; 2798 2799 bdp->cbd_sc = cpu_to_fec16(0); 2800 bdp->cbd_bufaddr = cpu_to_fec32(0); 2801 2802 if (fep->bufdesc_ex) { 2803 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2804 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 2805 } 2806 2807 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 2808 } 2809 2810 /* Set the last buffer to wrap. */ 2811 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 2812 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2813 2814 return 0; 2815 2816 err_alloc: 2817 fec_enet_free_buffers(ndev); 2818 return -ENOMEM; 2819 } 2820 2821 static int fec_enet_alloc_buffers(struct net_device *ndev) 2822 { 2823 struct fec_enet_private *fep = netdev_priv(ndev); 2824 unsigned int i; 2825 2826 for (i = 0; i < fep->num_rx_queues; i++) 2827 if (fec_enet_alloc_rxq_buffers(ndev, i)) 2828 return -ENOMEM; 2829 2830 for (i = 0; i < fep->num_tx_queues; i++) 2831 if (fec_enet_alloc_txq_buffers(ndev, i)) 2832 return -ENOMEM; 2833 return 0; 2834 } 2835 2836 static int 2837 fec_enet_open(struct net_device *ndev) 2838 { 2839 struct fec_enet_private *fep = netdev_priv(ndev); 2840 int ret; 2841 2842 ret = pm_runtime_get_sync(&fep->pdev->dev); 2843 if (ret < 0) 2844 return ret; 2845 2846 pinctrl_pm_select_default_state(&fep->pdev->dev); 2847 ret = fec_enet_clk_enable(ndev, true); 2848 if (ret) 2849 goto clk_enable; 2850 2851 /* I should reset the ring buffers here, but I don't yet know 2852 * a simple way to do that. 2853 */ 2854 2855 ret = fec_enet_alloc_buffers(ndev); 2856 if (ret) 2857 goto err_enet_alloc; 2858 2859 /* Init MAC prior to mii bus probe */ 2860 fec_restart(ndev); 2861 2862 /* Probe and connect to PHY when open the interface */ 2863 ret = fec_enet_mii_probe(ndev); 2864 if (ret) 2865 goto err_enet_mii_probe; 2866 2867 if (fep->quirks & FEC_QUIRK_ERR006687) 2868 imx6q_cpuidle_fec_irqs_used(); 2869 2870 napi_enable(&fep->napi); 2871 phy_start(ndev->phydev); 2872 netif_tx_start_all_queues(ndev); 2873 2874 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 2875 FEC_WOL_FLAG_ENABLE); 2876 2877 return 0; 2878 2879 err_enet_mii_probe: 2880 fec_enet_free_buffers(ndev); 2881 err_enet_alloc: 2882 fec_enet_clk_enable(ndev, false); 2883 clk_enable: 2884 pm_runtime_mark_last_busy(&fep->pdev->dev); 2885 pm_runtime_put_autosuspend(&fep->pdev->dev); 2886 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2887 return ret; 2888 } 2889 2890 static int 2891 fec_enet_close(struct net_device *ndev) 2892 { 2893 struct fec_enet_private *fep = netdev_priv(ndev); 2894 2895 phy_stop(ndev->phydev); 2896 2897 if (netif_device_present(ndev)) { 2898 napi_disable(&fep->napi); 2899 netif_tx_disable(ndev); 2900 fec_stop(ndev); 2901 } 2902 2903 phy_disconnect(ndev->phydev); 2904 2905 if (fep->quirks & FEC_QUIRK_ERR006687) 2906 imx6q_cpuidle_fec_irqs_unused(); 2907 2908 fec_enet_update_ethtool_stats(ndev); 2909 2910 fec_enet_clk_enable(ndev, false); 2911 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2912 pm_runtime_mark_last_busy(&fep->pdev->dev); 2913 pm_runtime_put_autosuspend(&fep->pdev->dev); 2914 2915 fec_enet_free_buffers(ndev); 2916 2917 return 0; 2918 } 2919 2920 /* Set or clear the multicast filter for this adaptor. 2921 * Skeleton taken from sunlance driver. 2922 * The CPM Ethernet implementation allows Multicast as well as individual 2923 * MAC address filtering. Some of the drivers check to make sure it is 2924 * a group multicast address, and discard those that are not. I guess I 2925 * will do the same for now, but just remove the test if you want 2926 * individual filtering as well (do the upper net layers want or support 2927 * this kind of feature?). 2928 */ 2929 2930 #define FEC_HASH_BITS 6 /* #bits in hash */ 2931 #define CRC32_POLY 0xEDB88320 2932 2933 static void set_multicast_list(struct net_device *ndev) 2934 { 2935 struct fec_enet_private *fep = netdev_priv(ndev); 2936 struct netdev_hw_addr *ha; 2937 unsigned int i, bit, data, crc, tmp; 2938 unsigned char hash; 2939 unsigned int hash_high = 0, hash_low = 0; 2940 2941 if (ndev->flags & IFF_PROMISC) { 2942 tmp = readl(fep->hwp + FEC_R_CNTRL); 2943 tmp |= 0x8; 2944 writel(tmp, fep->hwp + FEC_R_CNTRL); 2945 return; 2946 } 2947 2948 tmp = readl(fep->hwp + FEC_R_CNTRL); 2949 tmp &= ~0x8; 2950 writel(tmp, fep->hwp + FEC_R_CNTRL); 2951 2952 if (ndev->flags & IFF_ALLMULTI) { 2953 /* Catch all multicast addresses, so set the 2954 * filter to all 1's 2955 */ 2956 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2957 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2958 2959 return; 2960 } 2961 2962 /* Add the addresses in hash register */ 2963 netdev_for_each_mc_addr(ha, ndev) { 2964 /* calculate crc32 value of mac address */ 2965 crc = 0xffffffff; 2966 2967 for (i = 0; i < ndev->addr_len; i++) { 2968 data = ha->addr[i]; 2969 for (bit = 0; bit < 8; bit++, data >>= 1) { 2970 crc = (crc >> 1) ^ 2971 (((crc ^ data) & 1) ? CRC32_POLY : 0); 2972 } 2973 } 2974 2975 /* only upper 6 bits (FEC_HASH_BITS) are used 2976 * which point to specific bit in the hash registers 2977 */ 2978 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 2979 2980 if (hash > 31) 2981 hash_high |= 1 << (hash - 32); 2982 else 2983 hash_low |= 1 << hash; 2984 } 2985 2986 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2987 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2988 } 2989 2990 /* Set a MAC change in hardware. */ 2991 static int 2992 fec_set_mac_address(struct net_device *ndev, void *p) 2993 { 2994 struct fec_enet_private *fep = netdev_priv(ndev); 2995 struct sockaddr *addr = p; 2996 2997 if (addr) { 2998 if (!is_valid_ether_addr(addr->sa_data)) 2999 return -EADDRNOTAVAIL; 3000 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 3001 } 3002 3003 /* Add netif status check here to avoid system hang in below case: 3004 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3005 * After ethx down, fec all clocks are gated off and then register 3006 * access causes system hang. 3007 */ 3008 if (!netif_running(ndev)) 3009 return 0; 3010 3011 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3012 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3013 fep->hwp + FEC_ADDR_LOW); 3014 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3015 fep->hwp + FEC_ADDR_HIGH); 3016 return 0; 3017 } 3018 3019 #ifdef CONFIG_NET_POLL_CONTROLLER 3020 /** 3021 * fec_poll_controller - FEC Poll controller function 3022 * @dev: The FEC network adapter 3023 * 3024 * Polled functionality used by netconsole and others in non interrupt mode 3025 * 3026 */ 3027 static void fec_poll_controller(struct net_device *dev) 3028 { 3029 int i; 3030 struct fec_enet_private *fep = netdev_priv(dev); 3031 3032 for (i = 0; i < FEC_IRQ_NUM; i++) { 3033 if (fep->irq[i] > 0) { 3034 disable_irq(fep->irq[i]); 3035 fec_enet_interrupt(fep->irq[i], dev); 3036 enable_irq(fep->irq[i]); 3037 } 3038 } 3039 } 3040 #endif 3041 3042 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3043 netdev_features_t features) 3044 { 3045 struct fec_enet_private *fep = netdev_priv(netdev); 3046 netdev_features_t changed = features ^ netdev->features; 3047 3048 netdev->features = features; 3049 3050 /* Receive checksum has been changed */ 3051 if (changed & NETIF_F_RXCSUM) { 3052 if (features & NETIF_F_RXCSUM) 3053 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3054 else 3055 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3056 } 3057 } 3058 3059 static int fec_set_features(struct net_device *netdev, 3060 netdev_features_t features) 3061 { 3062 struct fec_enet_private *fep = netdev_priv(netdev); 3063 netdev_features_t changed = features ^ netdev->features; 3064 3065 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3066 napi_disable(&fep->napi); 3067 netif_tx_lock_bh(netdev); 3068 fec_stop(netdev); 3069 fec_enet_set_netdev_features(netdev, features); 3070 fec_restart(netdev); 3071 netif_tx_wake_all_queues(netdev); 3072 netif_tx_unlock_bh(netdev); 3073 napi_enable(&fep->napi); 3074 } else { 3075 fec_enet_set_netdev_features(netdev, features); 3076 } 3077 3078 return 0; 3079 } 3080 3081 static const struct net_device_ops fec_netdev_ops = { 3082 .ndo_open = fec_enet_open, 3083 .ndo_stop = fec_enet_close, 3084 .ndo_start_xmit = fec_enet_start_xmit, 3085 .ndo_set_rx_mode = set_multicast_list, 3086 .ndo_validate_addr = eth_validate_addr, 3087 .ndo_tx_timeout = fec_timeout, 3088 .ndo_set_mac_address = fec_set_mac_address, 3089 .ndo_do_ioctl = fec_enet_ioctl, 3090 #ifdef CONFIG_NET_POLL_CONTROLLER 3091 .ndo_poll_controller = fec_poll_controller, 3092 #endif 3093 .ndo_set_features = fec_set_features, 3094 }; 3095 3096 static const unsigned short offset_des_active_rxq[] = { 3097 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3098 }; 3099 3100 static const unsigned short offset_des_active_txq[] = { 3101 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3102 }; 3103 3104 /* 3105 * XXX: We need to clean up on failure exits here. 3106 * 3107 */ 3108 static int fec_enet_init(struct net_device *ndev) 3109 { 3110 struct fec_enet_private *fep = netdev_priv(ndev); 3111 struct bufdesc *cbd_base; 3112 dma_addr_t bd_dma; 3113 int bd_size; 3114 unsigned int i; 3115 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3116 sizeof(struct bufdesc); 3117 unsigned dsize_log2 = __fls(dsize); 3118 3119 WARN_ON(dsize != (1 << dsize_log2)); 3120 #if defined(CONFIG_ARM) 3121 fep->rx_align = 0xf; 3122 fep->tx_align = 0xf; 3123 #else 3124 fep->rx_align = 0x3; 3125 fep->tx_align = 0x3; 3126 #endif 3127 3128 fec_enet_alloc_queue(ndev); 3129 3130 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3131 3132 /* Allocate memory for buffer descriptors. */ 3133 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3134 GFP_KERNEL); 3135 if (!cbd_base) { 3136 return -ENOMEM; 3137 } 3138 3139 memset(cbd_base, 0, bd_size); 3140 3141 /* Get the Ethernet address */ 3142 fec_get_mac(ndev); 3143 /* make sure MAC we just acquired is programmed into the hw */ 3144 fec_set_mac_address(ndev, NULL); 3145 3146 /* Set receive and transmit descriptor base. */ 3147 for (i = 0; i < fep->num_rx_queues; i++) { 3148 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3149 unsigned size = dsize * rxq->bd.ring_size; 3150 3151 rxq->bd.qid = i; 3152 rxq->bd.base = cbd_base; 3153 rxq->bd.cur = cbd_base; 3154 rxq->bd.dma = bd_dma; 3155 rxq->bd.dsize = dsize; 3156 rxq->bd.dsize_log2 = dsize_log2; 3157 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3158 bd_dma += size; 3159 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3160 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3161 } 3162 3163 for (i = 0; i < fep->num_tx_queues; i++) { 3164 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3165 unsigned size = dsize * txq->bd.ring_size; 3166 3167 txq->bd.qid = i; 3168 txq->bd.base = cbd_base; 3169 txq->bd.cur = cbd_base; 3170 txq->bd.dma = bd_dma; 3171 txq->bd.dsize = dsize; 3172 txq->bd.dsize_log2 = dsize_log2; 3173 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3174 bd_dma += size; 3175 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3176 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3177 } 3178 3179 3180 /* The FEC Ethernet specific entries in the device structure */ 3181 ndev->watchdog_timeo = TX_TIMEOUT; 3182 ndev->netdev_ops = &fec_netdev_ops; 3183 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3184 3185 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3186 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3187 3188 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3189 /* enable hw VLAN support */ 3190 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3191 3192 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3193 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3194 3195 /* enable hw accelerator */ 3196 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3197 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3198 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3199 } 3200 3201 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 3202 fep->tx_align = 0; 3203 fep->rx_align = 0x3f; 3204 } 3205 3206 ndev->hw_features = ndev->features; 3207 3208 fec_restart(ndev); 3209 3210 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 3211 fec_enet_clear_ethtool_stats(ndev); 3212 else 3213 fec_enet_update_ethtool_stats(ndev); 3214 3215 return 0; 3216 } 3217 3218 #ifdef CONFIG_OF 3219 static int fec_reset_phy(struct platform_device *pdev) 3220 { 3221 int err, phy_reset; 3222 bool active_high = false; 3223 int msec = 1, phy_post_delay = 0; 3224 struct device_node *np = pdev->dev.of_node; 3225 3226 if (!np) 3227 return 0; 3228 3229 err = of_property_read_u32(np, "phy-reset-duration", &msec); 3230 /* A sane reset duration should not be longer than 1s */ 3231 if (!err && msec > 1000) 3232 msec = 1; 3233 3234 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3235 if (phy_reset == -EPROBE_DEFER) 3236 return phy_reset; 3237 else if (!gpio_is_valid(phy_reset)) 3238 return 0; 3239 3240 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 3241 /* valid reset duration should be less than 1s */ 3242 if (!err && phy_post_delay > 1000) 3243 return -EINVAL; 3244 3245 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3246 3247 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3248 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3249 "phy-reset"); 3250 if (err) { 3251 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3252 return err; 3253 } 3254 3255 if (msec > 20) 3256 msleep(msec); 3257 else 3258 usleep_range(msec * 1000, msec * 1000 + 1000); 3259 3260 gpio_set_value_cansleep(phy_reset, !active_high); 3261 3262 if (!phy_post_delay) 3263 return 0; 3264 3265 if (phy_post_delay > 20) 3266 msleep(phy_post_delay); 3267 else 3268 usleep_range(phy_post_delay * 1000, 3269 phy_post_delay * 1000 + 1000); 3270 3271 return 0; 3272 } 3273 #else /* CONFIG_OF */ 3274 static int fec_reset_phy(struct platform_device *pdev) 3275 { 3276 /* 3277 * In case of platform probe, the reset has been done 3278 * by machine code. 3279 */ 3280 return 0; 3281 } 3282 #endif /* CONFIG_OF */ 3283 3284 static void 3285 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3286 { 3287 struct device_node *np = pdev->dev.of_node; 3288 3289 *num_tx = *num_rx = 1; 3290 3291 if (!np || !of_device_is_available(np)) 3292 return; 3293 3294 /* parse the num of tx and rx queues */ 3295 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3296 3297 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3298 3299 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3300 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3301 *num_tx); 3302 *num_tx = 1; 3303 return; 3304 } 3305 3306 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3307 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3308 *num_rx); 3309 *num_rx = 1; 3310 return; 3311 } 3312 3313 } 3314 3315 static int 3316 fec_probe(struct platform_device *pdev) 3317 { 3318 struct fec_enet_private *fep; 3319 struct fec_platform_data *pdata; 3320 struct net_device *ndev; 3321 int i, irq, ret = 0; 3322 struct resource *r; 3323 const struct of_device_id *of_id; 3324 static int dev_id; 3325 struct device_node *np = pdev->dev.of_node, *phy_node; 3326 int num_tx_qs; 3327 int num_rx_qs; 3328 3329 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3330 3331 /* Init network device */ 3332 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 3333 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 3334 if (!ndev) 3335 return -ENOMEM; 3336 3337 SET_NETDEV_DEV(ndev, &pdev->dev); 3338 3339 /* setup board info structure */ 3340 fep = netdev_priv(ndev); 3341 3342 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3343 if (of_id) 3344 pdev->id_entry = of_id->data; 3345 fep->quirks = pdev->id_entry->driver_data; 3346 3347 fep->netdev = ndev; 3348 fep->num_rx_queues = num_rx_qs; 3349 fep->num_tx_queues = num_tx_qs; 3350 3351 #if !defined(CONFIG_M5272) 3352 /* default enable pause frame auto negotiation */ 3353 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3354 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3355 #endif 3356 3357 /* Select default pin state */ 3358 pinctrl_pm_select_default_state(&pdev->dev); 3359 3360 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3361 fep->hwp = devm_ioremap_resource(&pdev->dev, r); 3362 if (IS_ERR(fep->hwp)) { 3363 ret = PTR_ERR(fep->hwp); 3364 goto failed_ioremap; 3365 } 3366 3367 fep->pdev = pdev; 3368 fep->dev_id = dev_id++; 3369 3370 platform_set_drvdata(pdev, ndev); 3371 3372 if ((of_machine_is_compatible("fsl,imx6q") || 3373 of_machine_is_compatible("fsl,imx6dl")) && 3374 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3375 fep->quirks |= FEC_QUIRK_ERR006687; 3376 3377 if (of_get_property(np, "fsl,magic-packet", NULL)) 3378 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3379 3380 phy_node = of_parse_phandle(np, "phy-handle", 0); 3381 if (!phy_node && of_phy_is_fixed_link(np)) { 3382 ret = of_phy_register_fixed_link(np); 3383 if (ret < 0) { 3384 dev_err(&pdev->dev, 3385 "broken fixed-link specification\n"); 3386 goto failed_phy; 3387 } 3388 phy_node = of_node_get(np); 3389 } 3390 fep->phy_node = phy_node; 3391 3392 ret = of_get_phy_mode(pdev->dev.of_node); 3393 if (ret < 0) { 3394 pdata = dev_get_platdata(&pdev->dev); 3395 if (pdata) 3396 fep->phy_interface = pdata->phy; 3397 else 3398 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3399 } else { 3400 fep->phy_interface = ret; 3401 } 3402 3403 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3404 if (IS_ERR(fep->clk_ipg)) { 3405 ret = PTR_ERR(fep->clk_ipg); 3406 goto failed_clk; 3407 } 3408 3409 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3410 if (IS_ERR(fep->clk_ahb)) { 3411 ret = PTR_ERR(fep->clk_ahb); 3412 goto failed_clk; 3413 } 3414 3415 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3416 3417 /* enet_out is optional, depends on board */ 3418 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3419 if (IS_ERR(fep->clk_enet_out)) 3420 fep->clk_enet_out = NULL; 3421 3422 fep->ptp_clk_on = false; 3423 mutex_init(&fep->ptp_clk_mutex); 3424 3425 /* clk_ref is optional, depends on board */ 3426 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3427 if (IS_ERR(fep->clk_ref)) 3428 fep->clk_ref = NULL; 3429 3430 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3431 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3432 if (IS_ERR(fep->clk_ptp)) { 3433 fep->clk_ptp = NULL; 3434 fep->bufdesc_ex = false; 3435 } 3436 3437 ret = fec_enet_clk_enable(ndev, true); 3438 if (ret) 3439 goto failed_clk; 3440 3441 ret = clk_prepare_enable(fep->clk_ipg); 3442 if (ret) 3443 goto failed_clk_ipg; 3444 3445 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); 3446 if (!IS_ERR(fep->reg_phy)) { 3447 ret = regulator_enable(fep->reg_phy); 3448 if (ret) { 3449 dev_err(&pdev->dev, 3450 "Failed to enable phy regulator: %d\n", ret); 3451 clk_disable_unprepare(fep->clk_ipg); 3452 goto failed_regulator; 3453 } 3454 } else { 3455 fep->reg_phy = NULL; 3456 } 3457 3458 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3459 pm_runtime_use_autosuspend(&pdev->dev); 3460 pm_runtime_get_noresume(&pdev->dev); 3461 pm_runtime_set_active(&pdev->dev); 3462 pm_runtime_enable(&pdev->dev); 3463 3464 ret = fec_reset_phy(pdev); 3465 if (ret) 3466 goto failed_reset; 3467 3468 if (fep->bufdesc_ex) 3469 fec_ptp_init(pdev); 3470 3471 ret = fec_enet_init(ndev); 3472 if (ret) 3473 goto failed_init; 3474 3475 for (i = 0; i < FEC_IRQ_NUM; i++) { 3476 irq = platform_get_irq(pdev, i); 3477 if (irq < 0) { 3478 if (i) 3479 break; 3480 ret = irq; 3481 goto failed_irq; 3482 } 3483 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3484 0, pdev->name, ndev); 3485 if (ret) 3486 goto failed_irq; 3487 3488 fep->irq[i] = irq; 3489 } 3490 3491 init_completion(&fep->mdio_done); 3492 ret = fec_enet_mii_init(pdev); 3493 if (ret) 3494 goto failed_mii_init; 3495 3496 /* Carrier starts down, phylib will bring it up */ 3497 netif_carrier_off(ndev); 3498 fec_enet_clk_enable(ndev, false); 3499 pinctrl_pm_select_sleep_state(&pdev->dev); 3500 3501 ret = register_netdev(ndev); 3502 if (ret) 3503 goto failed_register; 3504 3505 device_init_wakeup(&ndev->dev, fep->wol_flag & 3506 FEC_WOL_HAS_MAGIC_PACKET); 3507 3508 if (fep->bufdesc_ex && fep->ptp_clock) 3509 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3510 3511 fep->rx_copybreak = COPYBREAK_DEFAULT; 3512 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3513 3514 pm_runtime_mark_last_busy(&pdev->dev); 3515 pm_runtime_put_autosuspend(&pdev->dev); 3516 3517 return 0; 3518 3519 failed_register: 3520 fec_enet_mii_remove(fep); 3521 failed_mii_init: 3522 failed_irq: 3523 failed_init: 3524 fec_ptp_stop(pdev); 3525 if (fep->reg_phy) 3526 regulator_disable(fep->reg_phy); 3527 failed_reset: 3528 pm_runtime_put(&pdev->dev); 3529 pm_runtime_disable(&pdev->dev); 3530 failed_regulator: 3531 failed_clk_ipg: 3532 fec_enet_clk_enable(ndev, false); 3533 failed_clk: 3534 if (of_phy_is_fixed_link(np)) 3535 of_phy_deregister_fixed_link(np); 3536 failed_phy: 3537 of_node_put(phy_node); 3538 failed_ioremap: 3539 free_netdev(ndev); 3540 3541 return ret; 3542 } 3543 3544 static int 3545 fec_drv_remove(struct platform_device *pdev) 3546 { 3547 struct net_device *ndev = platform_get_drvdata(pdev); 3548 struct fec_enet_private *fep = netdev_priv(ndev); 3549 struct device_node *np = pdev->dev.of_node; 3550 3551 cancel_work_sync(&fep->tx_timeout_work); 3552 fec_ptp_stop(pdev); 3553 unregister_netdev(ndev); 3554 fec_enet_mii_remove(fep); 3555 if (fep->reg_phy) 3556 regulator_disable(fep->reg_phy); 3557 if (of_phy_is_fixed_link(np)) 3558 of_phy_deregister_fixed_link(np); 3559 of_node_put(fep->phy_node); 3560 free_netdev(ndev); 3561 3562 return 0; 3563 } 3564 3565 static int __maybe_unused fec_suspend(struct device *dev) 3566 { 3567 struct net_device *ndev = dev_get_drvdata(dev); 3568 struct fec_enet_private *fep = netdev_priv(ndev); 3569 3570 rtnl_lock(); 3571 if (netif_running(ndev)) { 3572 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 3573 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 3574 phy_stop(ndev->phydev); 3575 napi_disable(&fep->napi); 3576 netif_tx_lock_bh(ndev); 3577 netif_device_detach(ndev); 3578 netif_tx_unlock_bh(ndev); 3579 fec_stop(ndev); 3580 fec_enet_clk_enable(ndev, false); 3581 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3582 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3583 } 3584 rtnl_unlock(); 3585 3586 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3587 regulator_disable(fep->reg_phy); 3588 3589 /* SOC supply clock to phy, when clock is disabled, phy link down 3590 * SOC control phy regulator, when regulator is disabled, phy link down 3591 */ 3592 if (fep->clk_enet_out || fep->reg_phy) 3593 fep->link = 0; 3594 3595 return 0; 3596 } 3597 3598 static int __maybe_unused fec_resume(struct device *dev) 3599 { 3600 struct net_device *ndev = dev_get_drvdata(dev); 3601 struct fec_enet_private *fep = netdev_priv(ndev); 3602 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 3603 int ret; 3604 int val; 3605 3606 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 3607 ret = regulator_enable(fep->reg_phy); 3608 if (ret) 3609 return ret; 3610 } 3611 3612 rtnl_lock(); 3613 if (netif_running(ndev)) { 3614 ret = fec_enet_clk_enable(ndev, true); 3615 if (ret) { 3616 rtnl_unlock(); 3617 goto failed_clk; 3618 } 3619 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 3620 if (pdata && pdata->sleep_mode_enable) 3621 pdata->sleep_mode_enable(false); 3622 val = readl(fep->hwp + FEC_ECNTRL); 3623 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 3624 writel(val, fep->hwp + FEC_ECNTRL); 3625 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 3626 } else { 3627 pinctrl_pm_select_default_state(&fep->pdev->dev); 3628 } 3629 fec_restart(ndev); 3630 netif_tx_lock_bh(ndev); 3631 netif_device_attach(ndev); 3632 netif_tx_unlock_bh(ndev); 3633 napi_enable(&fep->napi); 3634 phy_start(ndev->phydev); 3635 } 3636 rtnl_unlock(); 3637 3638 return 0; 3639 3640 failed_clk: 3641 if (fep->reg_phy) 3642 regulator_disable(fep->reg_phy); 3643 return ret; 3644 } 3645 3646 static int __maybe_unused fec_runtime_suspend(struct device *dev) 3647 { 3648 struct net_device *ndev = dev_get_drvdata(dev); 3649 struct fec_enet_private *fep = netdev_priv(ndev); 3650 3651 clk_disable_unprepare(fep->clk_ipg); 3652 3653 return 0; 3654 } 3655 3656 static int __maybe_unused fec_runtime_resume(struct device *dev) 3657 { 3658 struct net_device *ndev = dev_get_drvdata(dev); 3659 struct fec_enet_private *fep = netdev_priv(ndev); 3660 3661 return clk_prepare_enable(fep->clk_ipg); 3662 } 3663 3664 static const struct dev_pm_ops fec_pm_ops = { 3665 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 3666 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 3667 }; 3668 3669 static struct platform_driver fec_driver = { 3670 .driver = { 3671 .name = DRIVER_NAME, 3672 .pm = &fec_pm_ops, 3673 .of_match_table = fec_dt_ids, 3674 }, 3675 .id_table = fec_devtype, 3676 .probe = fec_probe, 3677 .remove = fec_drv_remove, 3678 }; 3679 3680 module_platform_driver(fec_driver); 3681 3682 MODULE_ALIAS("platform:"DRIVER_NAME); 3683 MODULE_LICENSE("GPL"); 3684