1 /* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 * 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/string.h> 27 #include <linux/ptrace.h> 28 #include <linux/errno.h> 29 #include <linux/ioport.h> 30 #include <linux/slab.h> 31 #include <linux/interrupt.h> 32 #include <linux/delay.h> 33 #include <linux/netdevice.h> 34 #include <linux/etherdevice.h> 35 #include <linux/skbuff.h> 36 #include <linux/in.h> 37 #include <linux/ip.h> 38 #include <net/ip.h> 39 #include <net/tso.h> 40 #include <linux/tcp.h> 41 #include <linux/udp.h> 42 #include <linux/icmp.h> 43 #include <linux/spinlock.h> 44 #include <linux/workqueue.h> 45 #include <linux/bitops.h> 46 #include <linux/io.h> 47 #include <linux/irq.h> 48 #include <linux/clk.h> 49 #include <linux/platform_device.h> 50 #include <linux/phy.h> 51 #include <linux/fec.h> 52 #include <linux/of.h> 53 #include <linux/of_device.h> 54 #include <linux/of_gpio.h> 55 #include <linux/of_mdio.h> 56 #include <linux/of_net.h> 57 #include <linux/regulator/consumer.h> 58 #include <linux/if_vlan.h> 59 #include <linux/pinctrl/consumer.h> 60 #include <linux/prefetch.h> 61 62 #include <asm/cacheflush.h> 63 64 #include "fec.h" 65 66 static void set_multicast_list(struct net_device *ndev); 67 static void fec_enet_itr_coal_init(struct net_device *ndev); 68 69 #define DRIVER_NAME "fec" 70 71 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0)) 72 73 /* Pause frame feild and FIFO threshold */ 74 #define FEC_ENET_FCE (1 << 5) 75 #define FEC_ENET_RSEM_V 0x84 76 #define FEC_ENET_RSFL_V 16 77 #define FEC_ENET_RAEM_V 0x8 78 #define FEC_ENET_RAFL_V 0x8 79 #define FEC_ENET_OPD_V 0xFFF0 80 81 static struct platform_device_id fec_devtype[] = { 82 { 83 /* keep it for coldfire */ 84 .name = DRIVER_NAME, 85 .driver_data = 0, 86 }, { 87 .name = "imx25-fec", 88 .driver_data = FEC_QUIRK_USE_GASKET, 89 }, { 90 .name = "imx27-fec", 91 .driver_data = 0, 92 }, { 93 .name = "imx28-fec", 94 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, 95 }, { 96 .name = "imx6q-fec", 97 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 98 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 99 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358, 100 }, { 101 .name = "mvf600-fec", 102 .driver_data = FEC_QUIRK_ENET_MAC, 103 }, { 104 .name = "imx6sx-fec", 105 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 106 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 107 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 108 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE, 109 }, { 110 /* sentinel */ 111 } 112 }; 113 MODULE_DEVICE_TABLE(platform, fec_devtype); 114 115 enum imx_fec_type { 116 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 117 IMX27_FEC, /* runs on i.mx27/35/51 */ 118 IMX28_FEC, 119 IMX6Q_FEC, 120 MVF600_FEC, 121 IMX6SX_FEC, 122 }; 123 124 static const struct of_device_id fec_dt_ids[] = { 125 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 126 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 127 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 128 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 129 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 130 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 131 { /* sentinel */ } 132 }; 133 MODULE_DEVICE_TABLE(of, fec_dt_ids); 134 135 static unsigned char macaddr[ETH_ALEN]; 136 module_param_array(macaddr, byte, NULL, 0); 137 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 138 139 #if defined(CONFIG_M5272) 140 /* 141 * Some hardware gets it MAC address out of local flash memory. 142 * if this is non-zero then assume it is the address to get MAC from. 143 */ 144 #if defined(CONFIG_NETtel) 145 #define FEC_FLASHMAC 0xf0006006 146 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 147 #define FEC_FLASHMAC 0xf0006000 148 #elif defined(CONFIG_CANCam) 149 #define FEC_FLASHMAC 0xf0020000 150 #elif defined (CONFIG_M5272C3) 151 #define FEC_FLASHMAC (0xffe04000 + 4) 152 #elif defined(CONFIG_MOD5272) 153 #define FEC_FLASHMAC 0xffc0406b 154 #else 155 #define FEC_FLASHMAC 0 156 #endif 157 #endif /* CONFIG_M5272 */ 158 159 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 160 */ 161 #define PKT_MAXBUF_SIZE 1522 162 #define PKT_MINBUF_SIZE 64 163 #define PKT_MAXBLR_SIZE 1536 164 165 /* FEC receive acceleration */ 166 #define FEC_RACC_IPDIS (1 << 1) 167 #define FEC_RACC_PRODIS (1 << 2) 168 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 169 170 /* 171 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 172 * size bits. Other FEC hardware does not, so we need to take that into 173 * account when setting it. 174 */ 175 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 176 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 177 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 178 #else 179 #define OPT_FRAME_SIZE 0 180 #endif 181 182 /* FEC MII MMFR bits definition */ 183 #define FEC_MMFR_ST (1 << 30) 184 #define FEC_MMFR_OP_READ (2 << 28) 185 #define FEC_MMFR_OP_WRITE (1 << 28) 186 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 187 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 188 #define FEC_MMFR_TA (2 << 16) 189 #define FEC_MMFR_DATA(v) (v & 0xffff) 190 191 #define FEC_MII_TIMEOUT 30000 /* us */ 192 193 /* Transmitter timeout */ 194 #define TX_TIMEOUT (2 * HZ) 195 196 #define FEC_PAUSE_FLAG_AUTONEG 0x1 197 #define FEC_PAUSE_FLAG_ENABLE 0x2 198 199 #define COPYBREAK_DEFAULT 256 200 201 #define TSO_HEADER_SIZE 128 202 /* Max number of allowed TCP segments for software TSO */ 203 #define FEC_MAX_TSO_SEGS 100 204 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 205 206 #define IS_TSO_HEADER(txq, addr) \ 207 ((addr >= txq->tso_hdrs_dma) && \ 208 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE)) 209 210 static int mii_cnt; 211 212 static inline 213 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 214 struct fec_enet_private *fep, 215 int queue_id) 216 { 217 struct bufdesc *new_bd = bdp + 1; 218 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1; 219 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id]; 220 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id]; 221 struct bufdesc_ex *ex_base; 222 struct bufdesc *base; 223 int ring_size; 224 225 if (bdp >= txq->tx_bd_base) { 226 base = txq->tx_bd_base; 227 ring_size = txq->tx_ring_size; 228 ex_base = (struct bufdesc_ex *)txq->tx_bd_base; 229 } else { 230 base = rxq->rx_bd_base; 231 ring_size = rxq->rx_ring_size; 232 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base; 233 } 234 235 if (fep->bufdesc_ex) 236 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ? 237 ex_base : ex_new_bd); 238 else 239 return (new_bd >= (base + ring_size)) ? 240 base : new_bd; 241 } 242 243 static inline 244 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 245 struct fec_enet_private *fep, 246 int queue_id) 247 { 248 struct bufdesc *new_bd = bdp - 1; 249 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1; 250 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id]; 251 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id]; 252 struct bufdesc_ex *ex_base; 253 struct bufdesc *base; 254 int ring_size; 255 256 if (bdp >= txq->tx_bd_base) { 257 base = txq->tx_bd_base; 258 ring_size = txq->tx_ring_size; 259 ex_base = (struct bufdesc_ex *)txq->tx_bd_base; 260 } else { 261 base = rxq->rx_bd_base; 262 ring_size = rxq->rx_ring_size; 263 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base; 264 } 265 266 if (fep->bufdesc_ex) 267 return (struct bufdesc *)((ex_new_bd < ex_base) ? 268 (ex_new_bd + ring_size) : ex_new_bd); 269 else 270 return (new_bd < base) ? (new_bd + ring_size) : new_bd; 271 } 272 273 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp, 274 struct fec_enet_private *fep) 275 { 276 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size; 277 } 278 279 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep, 280 struct fec_enet_priv_tx_q *txq) 281 { 282 int entries; 283 284 entries = ((const char *)txq->dirty_tx - 285 (const char *)txq->cur_tx) / fep->bufdesc_size - 1; 286 287 return entries > 0 ? entries : entries + txq->tx_ring_size; 288 } 289 290 static void *swap_buffer(void *bufaddr, int len) 291 { 292 int i; 293 unsigned int *buf = bufaddr; 294 295 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++) 296 *buf = cpu_to_be32(*buf); 297 298 return bufaddr; 299 } 300 301 static void fec_dump(struct net_device *ndev) 302 { 303 struct fec_enet_private *fep = netdev_priv(ndev); 304 struct bufdesc *bdp; 305 struct fec_enet_priv_tx_q *txq; 306 int index = 0; 307 308 netdev_info(ndev, "TX ring dump\n"); 309 pr_info("Nr SC addr len SKB\n"); 310 311 txq = fep->tx_queue[0]; 312 bdp = txq->tx_bd_base; 313 314 do { 315 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n", 316 index, 317 bdp == txq->cur_tx ? 'S' : ' ', 318 bdp == txq->dirty_tx ? 'H' : ' ', 319 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen, 320 txq->tx_skbuff[index]); 321 bdp = fec_enet_get_nextdesc(bdp, fep, 0); 322 index++; 323 } while (bdp != txq->tx_bd_base); 324 } 325 326 static inline bool is_ipv4_pkt(struct sk_buff *skb) 327 { 328 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 329 } 330 331 static int 332 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 333 { 334 /* Only run for packets requiring a checksum. */ 335 if (skb->ip_summed != CHECKSUM_PARTIAL) 336 return 0; 337 338 if (unlikely(skb_cow_head(skb, 0))) 339 return -1; 340 341 if (is_ipv4_pkt(skb)) 342 ip_hdr(skb)->check = 0; 343 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 344 345 return 0; 346 } 347 348 static int 349 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 350 struct sk_buff *skb, 351 struct net_device *ndev) 352 { 353 struct fec_enet_private *fep = netdev_priv(ndev); 354 const struct platform_device_id *id_entry = 355 platform_get_device_id(fep->pdev); 356 struct bufdesc *bdp = txq->cur_tx; 357 struct bufdesc_ex *ebdp; 358 int nr_frags = skb_shinfo(skb)->nr_frags; 359 unsigned short queue = skb_get_queue_mapping(skb); 360 int frag, frag_len; 361 unsigned short status; 362 unsigned int estatus = 0; 363 skb_frag_t *this_frag; 364 unsigned int index; 365 void *bufaddr; 366 dma_addr_t addr; 367 int i; 368 369 for (frag = 0; frag < nr_frags; frag++) { 370 this_frag = &skb_shinfo(skb)->frags[frag]; 371 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 372 ebdp = (struct bufdesc_ex *)bdp; 373 374 status = bdp->cbd_sc; 375 status &= ~BD_ENET_TX_STATS; 376 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 377 frag_len = skb_shinfo(skb)->frags[frag].size; 378 379 /* Handle the last BD specially */ 380 if (frag == nr_frags - 1) { 381 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 382 if (fep->bufdesc_ex) { 383 estatus |= BD_ENET_TX_INT; 384 if (unlikely(skb_shinfo(skb)->tx_flags & 385 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 386 estatus |= BD_ENET_TX_TS; 387 } 388 } 389 390 if (fep->bufdesc_ex) { 391 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB) 392 estatus |= FEC_TX_BD_FTYPE(queue); 393 if (skb->ip_summed == CHECKSUM_PARTIAL) 394 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 395 ebdp->cbd_bdu = 0; 396 ebdp->cbd_esc = estatus; 397 } 398 399 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset; 400 401 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep); 402 if (((unsigned long) bufaddr) & fep->tx_align || 403 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) { 404 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 405 bufaddr = txq->tx_bounce[index]; 406 407 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 408 swap_buffer(bufaddr, frag_len); 409 } 410 411 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 412 DMA_TO_DEVICE); 413 if (dma_mapping_error(&fep->pdev->dev, addr)) { 414 dev_kfree_skb_any(skb); 415 if (net_ratelimit()) 416 netdev_err(ndev, "Tx DMA memory map failed\n"); 417 goto dma_mapping_error; 418 } 419 420 bdp->cbd_bufaddr = addr; 421 bdp->cbd_datlen = frag_len; 422 bdp->cbd_sc = status; 423 } 424 425 txq->cur_tx = bdp; 426 427 return 0; 428 429 dma_mapping_error: 430 bdp = txq->cur_tx; 431 for (i = 0; i < frag; i++) { 432 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 433 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 434 bdp->cbd_datlen, DMA_TO_DEVICE); 435 } 436 return NETDEV_TX_OK; 437 } 438 439 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 440 struct sk_buff *skb, struct net_device *ndev) 441 { 442 struct fec_enet_private *fep = netdev_priv(ndev); 443 const struct platform_device_id *id_entry = 444 platform_get_device_id(fep->pdev); 445 int nr_frags = skb_shinfo(skb)->nr_frags; 446 struct bufdesc *bdp, *last_bdp; 447 void *bufaddr; 448 dma_addr_t addr; 449 unsigned short status; 450 unsigned short buflen; 451 unsigned short queue; 452 unsigned int estatus = 0; 453 unsigned int index; 454 int entries_free; 455 int ret; 456 457 entries_free = fec_enet_get_free_txdesc_num(fep, txq); 458 if (entries_free < MAX_SKB_FRAGS + 1) { 459 dev_kfree_skb_any(skb); 460 if (net_ratelimit()) 461 netdev_err(ndev, "NOT enough BD for SG!\n"); 462 return NETDEV_TX_OK; 463 } 464 465 /* Protocol checksum off-load for TCP and UDP. */ 466 if (fec_enet_clear_csum(skb, ndev)) { 467 dev_kfree_skb_any(skb); 468 return NETDEV_TX_OK; 469 } 470 471 /* Fill in a Tx ring entry */ 472 bdp = txq->cur_tx; 473 status = bdp->cbd_sc; 474 status &= ~BD_ENET_TX_STATS; 475 476 /* Set buffer length and buffer pointer */ 477 bufaddr = skb->data; 478 buflen = skb_headlen(skb); 479 480 queue = skb_get_queue_mapping(skb); 481 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep); 482 if (((unsigned long) bufaddr) & fep->tx_align || 483 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) { 484 memcpy(txq->tx_bounce[index], skb->data, buflen); 485 bufaddr = txq->tx_bounce[index]; 486 487 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 488 swap_buffer(bufaddr, buflen); 489 } 490 491 /* Push the data cache so the CPM does not get stale memory data. */ 492 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 493 if (dma_mapping_error(&fep->pdev->dev, addr)) { 494 dev_kfree_skb_any(skb); 495 if (net_ratelimit()) 496 netdev_err(ndev, "Tx DMA memory map failed\n"); 497 return NETDEV_TX_OK; 498 } 499 500 if (nr_frags) { 501 ret = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 502 if (ret) 503 return ret; 504 } else { 505 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 506 if (fep->bufdesc_ex) { 507 estatus = BD_ENET_TX_INT; 508 if (unlikely(skb_shinfo(skb)->tx_flags & 509 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 510 estatus |= BD_ENET_TX_TS; 511 } 512 } 513 514 if (fep->bufdesc_ex) { 515 516 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 517 518 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 519 fep->hwts_tx_en)) 520 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 521 522 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB) 523 estatus |= FEC_TX_BD_FTYPE(queue); 524 525 if (skb->ip_summed == CHECKSUM_PARTIAL) 526 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 527 528 ebdp->cbd_bdu = 0; 529 ebdp->cbd_esc = estatus; 530 } 531 532 last_bdp = txq->cur_tx; 533 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep); 534 /* Save skb pointer */ 535 txq->tx_skbuff[index] = skb; 536 537 bdp->cbd_datlen = buflen; 538 bdp->cbd_bufaddr = addr; 539 540 /* Send it on its way. Tell FEC it's ready, interrupt when done, 541 * it's the last BD of the frame, and to put the CRC on the end. 542 */ 543 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 544 bdp->cbd_sc = status; 545 546 /* If this was the last BD in the ring, start at the beginning again. */ 547 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue); 548 549 skb_tx_timestamp(skb); 550 551 txq->cur_tx = bdp; 552 553 /* Trigger transmission start */ 554 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue)); 555 556 return 0; 557 } 558 559 static int 560 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 561 struct net_device *ndev, 562 struct bufdesc *bdp, int index, char *data, 563 int size, bool last_tcp, bool is_last) 564 { 565 struct fec_enet_private *fep = netdev_priv(ndev); 566 const struct platform_device_id *id_entry = 567 platform_get_device_id(fep->pdev); 568 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 569 unsigned short queue = skb_get_queue_mapping(skb); 570 unsigned short status; 571 unsigned int estatus = 0; 572 dma_addr_t addr; 573 574 status = bdp->cbd_sc; 575 status &= ~BD_ENET_TX_STATS; 576 577 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 578 579 if (((unsigned long) data) & fep->tx_align || 580 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) { 581 memcpy(txq->tx_bounce[index], data, size); 582 data = txq->tx_bounce[index]; 583 584 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 585 swap_buffer(data, size); 586 } 587 588 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 589 if (dma_mapping_error(&fep->pdev->dev, addr)) { 590 dev_kfree_skb_any(skb); 591 if (net_ratelimit()) 592 netdev_err(ndev, "Tx DMA memory map failed\n"); 593 return NETDEV_TX_BUSY; 594 } 595 596 bdp->cbd_datlen = size; 597 bdp->cbd_bufaddr = addr; 598 599 if (fep->bufdesc_ex) { 600 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB) 601 estatus |= FEC_TX_BD_FTYPE(queue); 602 if (skb->ip_summed == CHECKSUM_PARTIAL) 603 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 604 ebdp->cbd_bdu = 0; 605 ebdp->cbd_esc = estatus; 606 } 607 608 /* Handle the last BD specially */ 609 if (last_tcp) 610 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 611 if (is_last) { 612 status |= BD_ENET_TX_INTR; 613 if (fep->bufdesc_ex) 614 ebdp->cbd_esc |= BD_ENET_TX_INT; 615 } 616 617 bdp->cbd_sc = status; 618 619 return 0; 620 } 621 622 static int 623 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 624 struct sk_buff *skb, struct net_device *ndev, 625 struct bufdesc *bdp, int index) 626 { 627 struct fec_enet_private *fep = netdev_priv(ndev); 628 const struct platform_device_id *id_entry = 629 platform_get_device_id(fep->pdev); 630 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 631 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 632 unsigned short queue = skb_get_queue_mapping(skb); 633 void *bufaddr; 634 unsigned long dmabuf; 635 unsigned short status; 636 unsigned int estatus = 0; 637 638 status = bdp->cbd_sc; 639 status &= ~BD_ENET_TX_STATS; 640 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 641 642 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 643 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 644 if (((unsigned long)bufaddr) & fep->tx_align || 645 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) { 646 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 647 bufaddr = txq->tx_bounce[index]; 648 649 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 650 swap_buffer(bufaddr, hdr_len); 651 652 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 653 hdr_len, DMA_TO_DEVICE); 654 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 655 dev_kfree_skb_any(skb); 656 if (net_ratelimit()) 657 netdev_err(ndev, "Tx DMA memory map failed\n"); 658 return NETDEV_TX_BUSY; 659 } 660 } 661 662 bdp->cbd_bufaddr = dmabuf; 663 bdp->cbd_datlen = hdr_len; 664 665 if (fep->bufdesc_ex) { 666 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB) 667 estatus |= FEC_TX_BD_FTYPE(queue); 668 if (skb->ip_summed == CHECKSUM_PARTIAL) 669 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 670 ebdp->cbd_bdu = 0; 671 ebdp->cbd_esc = estatus; 672 } 673 674 bdp->cbd_sc = status; 675 676 return 0; 677 } 678 679 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 680 struct sk_buff *skb, 681 struct net_device *ndev) 682 { 683 struct fec_enet_private *fep = netdev_priv(ndev); 684 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 685 int total_len, data_left; 686 struct bufdesc *bdp = txq->cur_tx; 687 unsigned short queue = skb_get_queue_mapping(skb); 688 struct tso_t tso; 689 unsigned int index = 0; 690 int ret; 691 const struct platform_device_id *id_entry = 692 platform_get_device_id(fep->pdev); 693 694 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) { 695 dev_kfree_skb_any(skb); 696 if (net_ratelimit()) 697 netdev_err(ndev, "NOT enough BD for TSO!\n"); 698 return NETDEV_TX_OK; 699 } 700 701 /* Protocol checksum off-load for TCP and UDP. */ 702 if (fec_enet_clear_csum(skb, ndev)) { 703 dev_kfree_skb_any(skb); 704 return NETDEV_TX_OK; 705 } 706 707 /* Initialize the TSO handler, and prepare the first payload */ 708 tso_start(skb, &tso); 709 710 total_len = skb->len - hdr_len; 711 while (total_len > 0) { 712 char *hdr; 713 714 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep); 715 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 716 total_len -= data_left; 717 718 /* prepare packet headers: MAC + IP + TCP */ 719 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 720 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 721 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 722 if (ret) 723 goto err_release; 724 725 while (data_left > 0) { 726 int size; 727 728 size = min_t(int, tso.size, data_left); 729 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 730 index = fec_enet_get_bd_index(txq->tx_bd_base, 731 bdp, fep); 732 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 733 bdp, index, 734 tso.data, size, 735 size == data_left, 736 total_len == 0); 737 if (ret) 738 goto err_release; 739 740 data_left -= size; 741 tso_build_data(skb, &tso, size); 742 } 743 744 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 745 } 746 747 /* Save skb pointer */ 748 txq->tx_skbuff[index] = skb; 749 750 skb_tx_timestamp(skb); 751 txq->cur_tx = bdp; 752 753 /* Trigger transmission start */ 754 if (!(id_entry->driver_data & FEC_QUIRK_ERR007885) || 755 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) || 756 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) || 757 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) || 758 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue))) 759 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue)); 760 761 return 0; 762 763 err_release: 764 /* TODO: Release all used data descriptors for TSO */ 765 return ret; 766 } 767 768 static netdev_tx_t 769 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 770 { 771 struct fec_enet_private *fep = netdev_priv(ndev); 772 int entries_free; 773 unsigned short queue; 774 struct fec_enet_priv_tx_q *txq; 775 struct netdev_queue *nq; 776 int ret; 777 778 queue = skb_get_queue_mapping(skb); 779 txq = fep->tx_queue[queue]; 780 nq = netdev_get_tx_queue(ndev, queue); 781 782 if (skb_is_gso(skb)) 783 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 784 else 785 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 786 if (ret) 787 return ret; 788 789 entries_free = fec_enet_get_free_txdesc_num(fep, txq); 790 if (entries_free <= txq->tx_stop_threshold) 791 netif_tx_stop_queue(nq); 792 793 return NETDEV_TX_OK; 794 } 795 796 /* Init RX & TX buffer descriptors 797 */ 798 static void fec_enet_bd_init(struct net_device *dev) 799 { 800 struct fec_enet_private *fep = netdev_priv(dev); 801 struct fec_enet_priv_tx_q *txq; 802 struct fec_enet_priv_rx_q *rxq; 803 struct bufdesc *bdp; 804 unsigned int i; 805 unsigned int q; 806 807 for (q = 0; q < fep->num_rx_queues; q++) { 808 /* Initialize the receive buffer descriptors. */ 809 rxq = fep->rx_queue[q]; 810 bdp = rxq->rx_bd_base; 811 812 for (i = 0; i < rxq->rx_ring_size; i++) { 813 814 /* Initialize the BD for every fragment in the page. */ 815 if (bdp->cbd_bufaddr) 816 bdp->cbd_sc = BD_ENET_RX_EMPTY; 817 else 818 bdp->cbd_sc = 0; 819 bdp = fec_enet_get_nextdesc(bdp, fep, q); 820 } 821 822 /* Set the last buffer to wrap */ 823 bdp = fec_enet_get_prevdesc(bdp, fep, q); 824 bdp->cbd_sc |= BD_SC_WRAP; 825 826 rxq->cur_rx = rxq->rx_bd_base; 827 } 828 829 for (q = 0; q < fep->num_tx_queues; q++) { 830 /* ...and the same for transmit */ 831 txq = fep->tx_queue[q]; 832 bdp = txq->tx_bd_base; 833 txq->cur_tx = bdp; 834 835 for (i = 0; i < txq->tx_ring_size; i++) { 836 /* Initialize the BD for every fragment in the page. */ 837 bdp->cbd_sc = 0; 838 if (txq->tx_skbuff[i]) { 839 dev_kfree_skb_any(txq->tx_skbuff[i]); 840 txq->tx_skbuff[i] = NULL; 841 } 842 bdp->cbd_bufaddr = 0; 843 bdp = fec_enet_get_nextdesc(bdp, fep, q); 844 } 845 846 /* Set the last buffer to wrap */ 847 bdp = fec_enet_get_prevdesc(bdp, fep, q); 848 bdp->cbd_sc |= BD_SC_WRAP; 849 txq->dirty_tx = bdp; 850 } 851 } 852 853 static void fec_enet_active_rxring(struct net_device *ndev) 854 { 855 struct fec_enet_private *fep = netdev_priv(ndev); 856 int i; 857 858 for (i = 0; i < fep->num_rx_queues; i++) 859 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i)); 860 } 861 862 static void fec_enet_enable_ring(struct net_device *ndev) 863 { 864 struct fec_enet_private *fep = netdev_priv(ndev); 865 struct fec_enet_priv_tx_q *txq; 866 struct fec_enet_priv_rx_q *rxq; 867 int i; 868 869 for (i = 0; i < fep->num_rx_queues; i++) { 870 rxq = fep->rx_queue[i]; 871 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i)); 872 873 /* enable DMA1/2 */ 874 if (i) 875 writel(RCMR_MATCHEN | RCMR_CMP(i), 876 fep->hwp + FEC_RCMR(i)); 877 } 878 879 for (i = 0; i < fep->num_tx_queues; i++) { 880 txq = fep->tx_queue[i]; 881 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i)); 882 883 /* enable DMA1/2 */ 884 if (i) 885 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 886 fep->hwp + FEC_DMA_CFG(i)); 887 } 888 } 889 890 static void fec_enet_reset_skb(struct net_device *ndev) 891 { 892 struct fec_enet_private *fep = netdev_priv(ndev); 893 struct fec_enet_priv_tx_q *txq; 894 int i, j; 895 896 for (i = 0; i < fep->num_tx_queues; i++) { 897 txq = fep->tx_queue[i]; 898 899 for (j = 0; j < txq->tx_ring_size; j++) { 900 if (txq->tx_skbuff[j]) { 901 dev_kfree_skb_any(txq->tx_skbuff[j]); 902 txq->tx_skbuff[j] = NULL; 903 } 904 } 905 } 906 } 907 908 /* 909 * This function is called to start or restart the FEC during a link 910 * change, transmit timeout, or to reconfigure the FEC. The network 911 * packet processing for this device must be stopped before this call. 912 */ 913 static void 914 fec_restart(struct net_device *ndev) 915 { 916 struct fec_enet_private *fep = netdev_priv(ndev); 917 const struct platform_device_id *id_entry = 918 platform_get_device_id(fep->pdev); 919 u32 val; 920 u32 temp_mac[2]; 921 u32 rcntl = OPT_FRAME_SIZE | 0x04; 922 u32 ecntl = 0x2; /* ETHEREN */ 923 924 /* Whack a reset. We should wait for this. 925 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 926 * instead of reset MAC itself. 927 */ 928 if (id_entry && id_entry->driver_data & FEC_QUIRK_HAS_AVB) { 929 writel(0, fep->hwp + FEC_ECNTRL); 930 } else { 931 writel(1, fep->hwp + FEC_ECNTRL); 932 udelay(10); 933 } 934 935 /* 936 * enet-mac reset will reset mac address registers too, 937 * so need to reconfigure it. 938 */ 939 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 940 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 941 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); 942 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); 943 } 944 945 /* Clear any outstanding interrupt. */ 946 writel(0xffc00000, fep->hwp + FEC_IEVENT); 947 948 /* Set maximum receive buffer size. */ 949 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); 950 951 fec_enet_bd_init(ndev); 952 953 fec_enet_enable_ring(ndev); 954 955 /* Reset tx SKB buffers. */ 956 fec_enet_reset_skb(ndev); 957 958 /* Enable MII mode */ 959 if (fep->full_duplex == DUPLEX_FULL) { 960 /* FD enable */ 961 writel(0x04, fep->hwp + FEC_X_CNTRL); 962 } else { 963 /* No Rcv on Xmit */ 964 rcntl |= 0x02; 965 writel(0x0, fep->hwp + FEC_X_CNTRL); 966 } 967 968 /* Set MII speed */ 969 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 970 971 #if !defined(CONFIG_M5272) 972 /* set RX checksum */ 973 val = readl(fep->hwp + FEC_RACC); 974 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 975 val |= FEC_RACC_OPTIONS; 976 else 977 val &= ~FEC_RACC_OPTIONS; 978 writel(val, fep->hwp + FEC_RACC); 979 #endif 980 981 /* 982 * The phy interface and speed need to get configured 983 * differently on enet-mac. 984 */ 985 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 986 /* Enable flow control and length check */ 987 rcntl |= 0x40000000 | 0x00000020; 988 989 /* RGMII, RMII or MII */ 990 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) 991 rcntl |= (1 << 6); 992 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 993 rcntl |= (1 << 8); 994 else 995 rcntl &= ~(1 << 8); 996 997 /* 1G, 100M or 10M */ 998 if (fep->phy_dev) { 999 if (fep->phy_dev->speed == SPEED_1000) 1000 ecntl |= (1 << 5); 1001 else if (fep->phy_dev->speed == SPEED_100) 1002 rcntl &= ~(1 << 9); 1003 else 1004 rcntl |= (1 << 9); 1005 } 1006 } else { 1007 #ifdef FEC_MIIGSK_ENR 1008 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { 1009 u32 cfgr; 1010 /* disable the gasket and wait */ 1011 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1012 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1013 udelay(1); 1014 1015 /* 1016 * configure the gasket: 1017 * RMII, 50 MHz, no loopback, no echo 1018 * MII, 25 MHz, no loopback, no echo 1019 */ 1020 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1021 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1022 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) 1023 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1024 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1025 1026 /* re-enable the gasket */ 1027 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1028 } 1029 #endif 1030 } 1031 1032 #if !defined(CONFIG_M5272) 1033 /* enable pause frame*/ 1034 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1035 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1036 fep->phy_dev && fep->phy_dev->pause)) { 1037 rcntl |= FEC_ENET_FCE; 1038 1039 /* set FIFO threshold parameter to reduce overrun */ 1040 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1041 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1042 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1043 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1044 1045 /* OPD */ 1046 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1047 } else { 1048 rcntl &= ~FEC_ENET_FCE; 1049 } 1050 #endif /* !defined(CONFIG_M5272) */ 1051 1052 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1053 1054 /* Setup multicast filter. */ 1055 set_multicast_list(ndev); 1056 #ifndef CONFIG_M5272 1057 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1058 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1059 #endif 1060 1061 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 1062 /* enable ENET endian swap */ 1063 ecntl |= (1 << 8); 1064 /* enable ENET store and forward mode */ 1065 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1066 } 1067 1068 if (fep->bufdesc_ex) 1069 ecntl |= (1 << 4); 1070 1071 #ifndef CONFIG_M5272 1072 /* Enable the MIB statistic event counters */ 1073 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1074 #endif 1075 1076 /* And last, enable the transmit and receive processing */ 1077 writel(ecntl, fep->hwp + FEC_ECNTRL); 1078 fec_enet_active_rxring(ndev); 1079 1080 if (fep->bufdesc_ex) 1081 fec_ptp_start_cyclecounter(ndev); 1082 1083 /* Enable interrupts we wish to service */ 1084 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1085 1086 /* Init the interrupt coalescing */ 1087 fec_enet_itr_coal_init(ndev); 1088 1089 } 1090 1091 static void 1092 fec_stop(struct net_device *ndev) 1093 { 1094 struct fec_enet_private *fep = netdev_priv(ndev); 1095 const struct platform_device_id *id_entry = 1096 platform_get_device_id(fep->pdev); 1097 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1098 1099 /* We cannot expect a graceful transmit stop without link !!! */ 1100 if (fep->link) { 1101 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1102 udelay(10); 1103 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1104 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1105 } 1106 1107 /* Whack a reset. We should wait for this. 1108 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1109 * instead of reset MAC itself. 1110 */ 1111 if (id_entry && id_entry->driver_data & FEC_QUIRK_HAS_AVB) { 1112 writel(0, fep->hwp + FEC_ECNTRL); 1113 } else { 1114 writel(1, fep->hwp + FEC_ECNTRL); 1115 udelay(10); 1116 } 1117 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1118 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1119 1120 /* We have to keep ENET enabled to have MII interrupt stay working */ 1121 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 1122 writel(2, fep->hwp + FEC_ECNTRL); 1123 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1124 } 1125 } 1126 1127 1128 static void 1129 fec_timeout(struct net_device *ndev) 1130 { 1131 struct fec_enet_private *fep = netdev_priv(ndev); 1132 1133 fec_dump(ndev); 1134 1135 ndev->stats.tx_errors++; 1136 1137 schedule_work(&fep->tx_timeout_work); 1138 } 1139 1140 static void fec_enet_timeout_work(struct work_struct *work) 1141 { 1142 struct fec_enet_private *fep = 1143 container_of(work, struct fec_enet_private, tx_timeout_work); 1144 struct net_device *ndev = fep->netdev; 1145 1146 rtnl_lock(); 1147 if (netif_device_present(ndev) || netif_running(ndev)) { 1148 napi_disable(&fep->napi); 1149 netif_tx_lock_bh(ndev); 1150 fec_restart(ndev); 1151 netif_wake_queue(ndev); 1152 netif_tx_unlock_bh(ndev); 1153 napi_enable(&fep->napi); 1154 } 1155 rtnl_unlock(); 1156 } 1157 1158 static void 1159 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1160 struct skb_shared_hwtstamps *hwtstamps) 1161 { 1162 unsigned long flags; 1163 u64 ns; 1164 1165 spin_lock_irqsave(&fep->tmreg_lock, flags); 1166 ns = timecounter_cyc2time(&fep->tc, ts); 1167 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1168 1169 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1170 hwtstamps->hwtstamp = ns_to_ktime(ns); 1171 } 1172 1173 static void 1174 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1175 { 1176 struct fec_enet_private *fep; 1177 struct bufdesc *bdp; 1178 unsigned short status; 1179 struct sk_buff *skb; 1180 struct fec_enet_priv_tx_q *txq; 1181 struct netdev_queue *nq; 1182 int index = 0; 1183 int entries_free; 1184 1185 fep = netdev_priv(ndev); 1186 1187 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1188 1189 txq = fep->tx_queue[queue_id]; 1190 /* get next bdp of dirty_tx */ 1191 nq = netdev_get_tx_queue(ndev, queue_id); 1192 bdp = txq->dirty_tx; 1193 1194 /* get next bdp of dirty_tx */ 1195 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id); 1196 1197 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { 1198 1199 /* current queue is empty */ 1200 if (bdp == txq->cur_tx) 1201 break; 1202 1203 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep); 1204 1205 skb = txq->tx_skbuff[index]; 1206 txq->tx_skbuff[index] = NULL; 1207 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr)) 1208 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 1209 bdp->cbd_datlen, DMA_TO_DEVICE); 1210 bdp->cbd_bufaddr = 0; 1211 if (!skb) { 1212 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id); 1213 continue; 1214 } 1215 1216 /* Check for errors. */ 1217 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1218 BD_ENET_TX_RL | BD_ENET_TX_UN | 1219 BD_ENET_TX_CSL)) { 1220 ndev->stats.tx_errors++; 1221 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1222 ndev->stats.tx_heartbeat_errors++; 1223 if (status & BD_ENET_TX_LC) /* Late collision */ 1224 ndev->stats.tx_window_errors++; 1225 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1226 ndev->stats.tx_aborted_errors++; 1227 if (status & BD_ENET_TX_UN) /* Underrun */ 1228 ndev->stats.tx_fifo_errors++; 1229 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1230 ndev->stats.tx_carrier_errors++; 1231 } else { 1232 ndev->stats.tx_packets++; 1233 ndev->stats.tx_bytes += skb->len; 1234 } 1235 1236 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 1237 fep->bufdesc_ex) { 1238 struct skb_shared_hwtstamps shhwtstamps; 1239 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1240 1241 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps); 1242 skb_tstamp_tx(skb, &shhwtstamps); 1243 } 1244 1245 /* Deferred means some collisions occurred during transmit, 1246 * but we eventually sent the packet OK. 1247 */ 1248 if (status & BD_ENET_TX_DEF) 1249 ndev->stats.collisions++; 1250 1251 /* Free the sk buffer associated with this last transmit */ 1252 dev_kfree_skb_any(skb); 1253 1254 txq->dirty_tx = bdp; 1255 1256 /* Update pointer to next buffer descriptor to be transmitted */ 1257 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id); 1258 1259 /* Since we have freed up a buffer, the ring is no longer full 1260 */ 1261 if (netif_queue_stopped(ndev)) { 1262 entries_free = fec_enet_get_free_txdesc_num(fep, txq); 1263 if (entries_free >= txq->tx_wake_threshold) 1264 netif_tx_wake_queue(nq); 1265 } 1266 } 1267 1268 /* ERR006538: Keep the transmitter going */ 1269 if (bdp != txq->cur_tx && 1270 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0) 1271 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id)); 1272 } 1273 1274 static void 1275 fec_enet_tx(struct net_device *ndev) 1276 { 1277 struct fec_enet_private *fep = netdev_priv(ndev); 1278 u16 queue_id; 1279 /* First process class A queue, then Class B and Best Effort queue */ 1280 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) { 1281 clear_bit(queue_id, &fep->work_tx); 1282 fec_enet_tx_queue(ndev, queue_id); 1283 } 1284 return; 1285 } 1286 1287 static int 1288 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1289 { 1290 struct fec_enet_private *fep = netdev_priv(ndev); 1291 int off; 1292 1293 off = ((unsigned long)skb->data) & fep->rx_align; 1294 if (off) 1295 skb_reserve(skb, fep->rx_align + 1 - off); 1296 1297 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, 1298 FEC_ENET_RX_FRSIZE - fep->rx_align, 1299 DMA_FROM_DEVICE); 1300 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) { 1301 if (net_ratelimit()) 1302 netdev_err(ndev, "Rx DMA memory map failed\n"); 1303 return -ENOMEM; 1304 } 1305 1306 return 0; 1307 } 1308 1309 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1310 struct bufdesc *bdp, u32 length) 1311 { 1312 struct fec_enet_private *fep = netdev_priv(ndev); 1313 struct sk_buff *new_skb; 1314 1315 if (length > fep->rx_copybreak) 1316 return false; 1317 1318 new_skb = netdev_alloc_skb(ndev, length); 1319 if (!new_skb) 1320 return false; 1321 1322 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr, 1323 FEC_ENET_RX_FRSIZE - fep->rx_align, 1324 DMA_FROM_DEVICE); 1325 memcpy(new_skb->data, (*skb)->data, length); 1326 *skb = new_skb; 1327 1328 return true; 1329 } 1330 1331 /* During a receive, the cur_rx points to the current incoming buffer. 1332 * When we update through the ring, if the next incoming buffer has 1333 * not been given to the system, we just set the empty indicator, 1334 * effectively tossing the packet. 1335 */ 1336 static int 1337 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1338 { 1339 struct fec_enet_private *fep = netdev_priv(ndev); 1340 const struct platform_device_id *id_entry = 1341 platform_get_device_id(fep->pdev); 1342 struct fec_enet_priv_rx_q *rxq; 1343 struct bufdesc *bdp; 1344 unsigned short status; 1345 struct sk_buff *skb_new = NULL; 1346 struct sk_buff *skb; 1347 ushort pkt_len; 1348 __u8 *data; 1349 int pkt_received = 0; 1350 struct bufdesc_ex *ebdp = NULL; 1351 bool vlan_packet_rcvd = false; 1352 u16 vlan_tag; 1353 int index = 0; 1354 bool is_copybreak; 1355 1356 #ifdef CONFIG_M532x 1357 flush_cache_all(); 1358 #endif 1359 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1360 rxq = fep->rx_queue[queue_id]; 1361 1362 /* First, grab all of the stats for the incoming packet. 1363 * These get messed up if we get called due to a busy condition. 1364 */ 1365 bdp = rxq->cur_rx; 1366 1367 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { 1368 1369 if (pkt_received >= budget) 1370 break; 1371 pkt_received++; 1372 1373 /* Since we have allocated space to hold a complete frame, 1374 * the last indicator should be set. 1375 */ 1376 if ((status & BD_ENET_RX_LAST) == 0) 1377 netdev_err(ndev, "rcv is not +last\n"); 1378 1379 1380 /* Check for errors. */ 1381 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1382 BD_ENET_RX_CR | BD_ENET_RX_OV)) { 1383 ndev->stats.rx_errors++; 1384 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { 1385 /* Frame too long or too short. */ 1386 ndev->stats.rx_length_errors++; 1387 } 1388 if (status & BD_ENET_RX_NO) /* Frame alignment */ 1389 ndev->stats.rx_frame_errors++; 1390 if (status & BD_ENET_RX_CR) /* CRC Error */ 1391 ndev->stats.rx_crc_errors++; 1392 if (status & BD_ENET_RX_OV) /* FIFO overrun */ 1393 ndev->stats.rx_fifo_errors++; 1394 } 1395 1396 /* Report late collisions as a frame error. 1397 * On this error, the BD is closed, but we don't know what we 1398 * have in the buffer. So, just drop this frame on the floor. 1399 */ 1400 if (status & BD_ENET_RX_CL) { 1401 ndev->stats.rx_errors++; 1402 ndev->stats.rx_frame_errors++; 1403 goto rx_processing_done; 1404 } 1405 1406 /* Process the incoming frame. */ 1407 ndev->stats.rx_packets++; 1408 pkt_len = bdp->cbd_datlen; 1409 ndev->stats.rx_bytes += pkt_len; 1410 1411 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep); 1412 skb = rxq->rx_skbuff[index]; 1413 1414 /* The packet length includes FCS, but we don't want to 1415 * include that when passing upstream as it messes up 1416 * bridging applications. 1417 */ 1418 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4); 1419 if (!is_copybreak) { 1420 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1421 if (unlikely(!skb_new)) { 1422 ndev->stats.rx_dropped++; 1423 goto rx_processing_done; 1424 } 1425 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 1426 FEC_ENET_RX_FRSIZE - fep->rx_align, 1427 DMA_FROM_DEVICE); 1428 } 1429 1430 prefetch(skb->data - NET_IP_ALIGN); 1431 skb_put(skb, pkt_len - 4); 1432 data = skb->data; 1433 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 1434 swap_buffer(data, pkt_len); 1435 1436 /* Extract the enhanced buffer descriptor */ 1437 ebdp = NULL; 1438 if (fep->bufdesc_ex) 1439 ebdp = (struct bufdesc_ex *)bdp; 1440 1441 /* If this is a VLAN packet remove the VLAN Tag */ 1442 vlan_packet_rcvd = false; 1443 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1444 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) { 1445 /* Push and remove the vlan tag */ 1446 struct vlan_hdr *vlan_header = 1447 (struct vlan_hdr *) (data + ETH_HLEN); 1448 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1449 1450 vlan_packet_rcvd = true; 1451 1452 skb_copy_to_linear_data_offset(skb, VLAN_HLEN, 1453 data, (2 * ETH_ALEN)); 1454 skb_pull(skb, VLAN_HLEN); 1455 } 1456 1457 skb->protocol = eth_type_trans(skb, ndev); 1458 1459 /* Get receive timestamp from the skb */ 1460 if (fep->hwts_rx_en && fep->bufdesc_ex) 1461 fec_enet_hwtstamp(fep, ebdp->ts, 1462 skb_hwtstamps(skb)); 1463 1464 if (fep->bufdesc_ex && 1465 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1466 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) { 1467 /* don't check it */ 1468 skb->ip_summed = CHECKSUM_UNNECESSARY; 1469 } else { 1470 skb_checksum_none_assert(skb); 1471 } 1472 } 1473 1474 /* Handle received VLAN packets */ 1475 if (vlan_packet_rcvd) 1476 __vlan_hwaccel_put_tag(skb, 1477 htons(ETH_P_8021Q), 1478 vlan_tag); 1479 1480 napi_gro_receive(&fep->napi, skb); 1481 1482 if (is_copybreak) { 1483 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr, 1484 FEC_ENET_RX_FRSIZE - fep->rx_align, 1485 DMA_FROM_DEVICE); 1486 } else { 1487 rxq->rx_skbuff[index] = skb_new; 1488 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1489 } 1490 1491 rx_processing_done: 1492 /* Clear the status flags for this buffer */ 1493 status &= ~BD_ENET_RX_STATS; 1494 1495 /* Mark the buffer empty */ 1496 status |= BD_ENET_RX_EMPTY; 1497 bdp->cbd_sc = status; 1498 1499 if (fep->bufdesc_ex) { 1500 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1501 1502 ebdp->cbd_esc = BD_ENET_RX_INT; 1503 ebdp->cbd_prot = 0; 1504 ebdp->cbd_bdu = 0; 1505 } 1506 1507 /* Update BD pointer to next entry */ 1508 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id); 1509 1510 /* Doing this here will keep the FEC running while we process 1511 * incoming frames. On a heavily loaded network, we should be 1512 * able to keep up at the expense of system resources. 1513 */ 1514 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id)); 1515 } 1516 rxq->cur_rx = bdp; 1517 return pkt_received; 1518 } 1519 1520 static int 1521 fec_enet_rx(struct net_device *ndev, int budget) 1522 { 1523 int pkt_received = 0; 1524 u16 queue_id; 1525 struct fec_enet_private *fep = netdev_priv(ndev); 1526 1527 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) { 1528 clear_bit(queue_id, &fep->work_rx); 1529 pkt_received += fec_enet_rx_queue(ndev, 1530 budget - pkt_received, queue_id); 1531 } 1532 return pkt_received; 1533 } 1534 1535 static bool 1536 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events) 1537 { 1538 if (int_events == 0) 1539 return false; 1540 1541 if (int_events & FEC_ENET_RXF) 1542 fep->work_rx |= (1 << 2); 1543 if (int_events & FEC_ENET_RXF_1) 1544 fep->work_rx |= (1 << 0); 1545 if (int_events & FEC_ENET_RXF_2) 1546 fep->work_rx |= (1 << 1); 1547 1548 if (int_events & FEC_ENET_TXF) 1549 fep->work_tx |= (1 << 2); 1550 if (int_events & FEC_ENET_TXF_1) 1551 fep->work_tx |= (1 << 0); 1552 if (int_events & FEC_ENET_TXF_2) 1553 fep->work_tx |= (1 << 1); 1554 1555 return true; 1556 } 1557 1558 static irqreturn_t 1559 fec_enet_interrupt(int irq, void *dev_id) 1560 { 1561 struct net_device *ndev = dev_id; 1562 struct fec_enet_private *fep = netdev_priv(ndev); 1563 const unsigned napi_mask = FEC_ENET_RXF | FEC_ENET_TXF; 1564 uint int_events; 1565 irqreturn_t ret = IRQ_NONE; 1566 1567 int_events = readl(fep->hwp + FEC_IEVENT); 1568 writel(int_events & ~napi_mask, fep->hwp + FEC_IEVENT); 1569 fec_enet_collect_events(fep, int_events); 1570 1571 if (int_events & napi_mask) { 1572 ret = IRQ_HANDLED; 1573 1574 /* Disable the NAPI interrupts */ 1575 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); 1576 napi_schedule(&fep->napi); 1577 } 1578 1579 if (int_events & FEC_ENET_MII) { 1580 ret = IRQ_HANDLED; 1581 complete(&fep->mdio_done); 1582 } 1583 1584 fec_ptp_check_pps_event(fep); 1585 1586 return ret; 1587 } 1588 1589 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1590 { 1591 struct net_device *ndev = napi->dev; 1592 struct fec_enet_private *fep = netdev_priv(ndev); 1593 int pkts; 1594 1595 /* 1596 * Clear any pending transmit or receive interrupts before 1597 * processing the rings to avoid racing with the hardware. 1598 */ 1599 writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT); 1600 1601 pkts = fec_enet_rx(ndev, budget); 1602 1603 fec_enet_tx(ndev); 1604 1605 if (pkts < budget) { 1606 napi_complete(napi); 1607 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1608 } 1609 return pkts; 1610 } 1611 1612 /* ------------------------------------------------------------------------- */ 1613 static void fec_get_mac(struct net_device *ndev) 1614 { 1615 struct fec_enet_private *fep = netdev_priv(ndev); 1616 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1617 unsigned char *iap, tmpaddr[ETH_ALEN]; 1618 1619 /* 1620 * try to get mac address in following order: 1621 * 1622 * 1) module parameter via kernel command line in form 1623 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1624 */ 1625 iap = macaddr; 1626 1627 /* 1628 * 2) from device tree data 1629 */ 1630 if (!is_valid_ether_addr(iap)) { 1631 struct device_node *np = fep->pdev->dev.of_node; 1632 if (np) { 1633 const char *mac = of_get_mac_address(np); 1634 if (mac) 1635 iap = (unsigned char *) mac; 1636 } 1637 } 1638 1639 /* 1640 * 3) from flash or fuse (via platform data) 1641 */ 1642 if (!is_valid_ether_addr(iap)) { 1643 #ifdef CONFIG_M5272 1644 if (FEC_FLASHMAC) 1645 iap = (unsigned char *)FEC_FLASHMAC; 1646 #else 1647 if (pdata) 1648 iap = (unsigned char *)&pdata->mac; 1649 #endif 1650 } 1651 1652 /* 1653 * 4) FEC mac registers set by bootloader 1654 */ 1655 if (!is_valid_ether_addr(iap)) { 1656 *((__be32 *) &tmpaddr[0]) = 1657 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1658 *((__be16 *) &tmpaddr[4]) = 1659 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1660 iap = &tmpaddr[0]; 1661 } 1662 1663 /* 1664 * 5) random mac address 1665 */ 1666 if (!is_valid_ether_addr(iap)) { 1667 /* Report it and use a random ethernet address instead */ 1668 netdev_err(ndev, "Invalid MAC address: %pM\n", iap); 1669 eth_hw_addr_random(ndev); 1670 netdev_info(ndev, "Using random MAC address: %pM\n", 1671 ndev->dev_addr); 1672 return; 1673 } 1674 1675 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1676 1677 /* Adjust MAC if using macaddr */ 1678 if (iap == macaddr) 1679 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1680 } 1681 1682 /* ------------------------------------------------------------------------- */ 1683 1684 /* 1685 * Phy section 1686 */ 1687 static void fec_enet_adjust_link(struct net_device *ndev) 1688 { 1689 struct fec_enet_private *fep = netdev_priv(ndev); 1690 struct phy_device *phy_dev = fep->phy_dev; 1691 int status_change = 0; 1692 1693 /* Prevent a state halted on mii error */ 1694 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 1695 phy_dev->state = PHY_RESUMING; 1696 return; 1697 } 1698 1699 /* 1700 * If the netdev is down, or is going down, we're not interested 1701 * in link state events, so just mark our idea of the link as down 1702 * and ignore the event. 1703 */ 1704 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1705 fep->link = 0; 1706 } else if (phy_dev->link) { 1707 if (!fep->link) { 1708 fep->link = phy_dev->link; 1709 status_change = 1; 1710 } 1711 1712 if (fep->full_duplex != phy_dev->duplex) { 1713 fep->full_duplex = phy_dev->duplex; 1714 status_change = 1; 1715 } 1716 1717 if (phy_dev->speed != fep->speed) { 1718 fep->speed = phy_dev->speed; 1719 status_change = 1; 1720 } 1721 1722 /* if any of the above changed restart the FEC */ 1723 if (status_change) { 1724 napi_disable(&fep->napi); 1725 netif_tx_lock_bh(ndev); 1726 fec_restart(ndev); 1727 netif_wake_queue(ndev); 1728 netif_tx_unlock_bh(ndev); 1729 napi_enable(&fep->napi); 1730 } 1731 } else { 1732 if (fep->link) { 1733 napi_disable(&fep->napi); 1734 netif_tx_lock_bh(ndev); 1735 fec_stop(ndev); 1736 netif_tx_unlock_bh(ndev); 1737 napi_enable(&fep->napi); 1738 fep->link = phy_dev->link; 1739 status_change = 1; 1740 } 1741 } 1742 1743 if (status_change) 1744 phy_print_status(phy_dev); 1745 } 1746 1747 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1748 { 1749 struct fec_enet_private *fep = bus->priv; 1750 unsigned long time_left; 1751 1752 fep->mii_timeout = 0; 1753 init_completion(&fep->mdio_done); 1754 1755 /* start a read op */ 1756 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 1757 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1758 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1759 1760 /* wait for end of transfer */ 1761 time_left = wait_for_completion_timeout(&fep->mdio_done, 1762 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1763 if (time_left == 0) { 1764 fep->mii_timeout = 1; 1765 netdev_err(fep->netdev, "MDIO read timeout\n"); 1766 return -ETIMEDOUT; 1767 } 1768 1769 /* return value */ 1770 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1771 } 1772 1773 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1774 u16 value) 1775 { 1776 struct fec_enet_private *fep = bus->priv; 1777 unsigned long time_left; 1778 1779 fep->mii_timeout = 0; 1780 init_completion(&fep->mdio_done); 1781 1782 /* start a write op */ 1783 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 1784 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1785 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1786 fep->hwp + FEC_MII_DATA); 1787 1788 /* wait for end of transfer */ 1789 time_left = wait_for_completion_timeout(&fep->mdio_done, 1790 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1791 if (time_left == 0) { 1792 fep->mii_timeout = 1; 1793 netdev_err(fep->netdev, "MDIO write timeout\n"); 1794 return -ETIMEDOUT; 1795 } 1796 1797 return 0; 1798 } 1799 1800 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1801 { 1802 struct fec_enet_private *fep = netdev_priv(ndev); 1803 int ret; 1804 1805 if (enable) { 1806 ret = clk_prepare_enable(fep->clk_ahb); 1807 if (ret) 1808 return ret; 1809 ret = clk_prepare_enable(fep->clk_ipg); 1810 if (ret) 1811 goto failed_clk_ipg; 1812 if (fep->clk_enet_out) { 1813 ret = clk_prepare_enable(fep->clk_enet_out); 1814 if (ret) 1815 goto failed_clk_enet_out; 1816 } 1817 if (fep->clk_ptp) { 1818 mutex_lock(&fep->ptp_clk_mutex); 1819 ret = clk_prepare_enable(fep->clk_ptp); 1820 if (ret) { 1821 mutex_unlock(&fep->ptp_clk_mutex); 1822 goto failed_clk_ptp; 1823 } else { 1824 fep->ptp_clk_on = true; 1825 } 1826 mutex_unlock(&fep->ptp_clk_mutex); 1827 } 1828 if (fep->clk_ref) { 1829 ret = clk_prepare_enable(fep->clk_ref); 1830 if (ret) 1831 goto failed_clk_ref; 1832 } 1833 } else { 1834 clk_disable_unprepare(fep->clk_ahb); 1835 clk_disable_unprepare(fep->clk_ipg); 1836 if (fep->clk_enet_out) 1837 clk_disable_unprepare(fep->clk_enet_out); 1838 if (fep->clk_ptp) { 1839 mutex_lock(&fep->ptp_clk_mutex); 1840 clk_disable_unprepare(fep->clk_ptp); 1841 fep->ptp_clk_on = false; 1842 mutex_unlock(&fep->ptp_clk_mutex); 1843 } 1844 if (fep->clk_ref) 1845 clk_disable_unprepare(fep->clk_ref); 1846 } 1847 1848 return 0; 1849 1850 failed_clk_ref: 1851 if (fep->clk_ref) 1852 clk_disable_unprepare(fep->clk_ref); 1853 failed_clk_ptp: 1854 if (fep->clk_enet_out) 1855 clk_disable_unprepare(fep->clk_enet_out); 1856 failed_clk_enet_out: 1857 clk_disable_unprepare(fep->clk_ipg); 1858 failed_clk_ipg: 1859 clk_disable_unprepare(fep->clk_ahb); 1860 1861 return ret; 1862 } 1863 1864 static int fec_enet_mii_probe(struct net_device *ndev) 1865 { 1866 struct fec_enet_private *fep = netdev_priv(ndev); 1867 const struct platform_device_id *id_entry = 1868 platform_get_device_id(fep->pdev); 1869 struct phy_device *phy_dev = NULL; 1870 char mdio_bus_id[MII_BUS_ID_SIZE]; 1871 char phy_name[MII_BUS_ID_SIZE + 3]; 1872 int phy_id; 1873 int dev_id = fep->dev_id; 1874 1875 fep->phy_dev = NULL; 1876 1877 if (fep->phy_node) { 1878 phy_dev = of_phy_connect(ndev, fep->phy_node, 1879 &fec_enet_adjust_link, 0, 1880 fep->phy_interface); 1881 } else { 1882 /* check for attached phy */ 1883 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1884 if ((fep->mii_bus->phy_mask & (1 << phy_id))) 1885 continue; 1886 if (fep->mii_bus->phy_map[phy_id] == NULL) 1887 continue; 1888 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) 1889 continue; 1890 if (dev_id--) 1891 continue; 1892 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1893 break; 1894 } 1895 1896 if (phy_id >= PHY_MAX_ADDR) { 1897 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1898 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 1899 phy_id = 0; 1900 } 1901 1902 snprintf(phy_name, sizeof(phy_name), 1903 PHY_ID_FMT, mdio_bus_id, phy_id); 1904 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 1905 fep->phy_interface); 1906 } 1907 1908 if (IS_ERR(phy_dev)) { 1909 netdev_err(ndev, "could not attach to PHY\n"); 1910 return PTR_ERR(phy_dev); 1911 } 1912 1913 /* mask with MAC supported features */ 1914 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) { 1915 phy_dev->supported &= PHY_GBIT_FEATURES; 1916 phy_dev->supported &= ~SUPPORTED_1000baseT_Half; 1917 #if !defined(CONFIG_M5272) 1918 phy_dev->supported |= SUPPORTED_Pause; 1919 #endif 1920 } 1921 else 1922 phy_dev->supported &= PHY_BASIC_FEATURES; 1923 1924 phy_dev->advertising = phy_dev->supported; 1925 1926 fep->phy_dev = phy_dev; 1927 fep->link = 0; 1928 fep->full_duplex = 0; 1929 1930 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 1931 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), 1932 fep->phy_dev->irq); 1933 1934 return 0; 1935 } 1936 1937 static int fec_enet_mii_init(struct platform_device *pdev) 1938 { 1939 static struct mii_bus *fec0_mii_bus; 1940 struct net_device *ndev = platform_get_drvdata(pdev); 1941 struct fec_enet_private *fep = netdev_priv(ndev); 1942 const struct platform_device_id *id_entry = 1943 platform_get_device_id(fep->pdev); 1944 struct device_node *node; 1945 int err = -ENXIO, i; 1946 1947 /* 1948 * The dual fec interfaces are not equivalent with enet-mac. 1949 * Here are the differences: 1950 * 1951 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1952 * - fec0 acts as the 1588 time master while fec1 is slave 1953 * - external phys can only be configured by fec0 1954 * 1955 * That is to say fec1 can not work independently. It only works 1956 * when fec0 is working. The reason behind this design is that the 1957 * second interface is added primarily for Switch mode. 1958 * 1959 * Because of the last point above, both phys are attached on fec0 1960 * mdio interface in board design, and need to be configured by 1961 * fec0 mii_bus. 1962 */ 1963 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { 1964 /* fec1 uses fec0 mii_bus */ 1965 if (mii_cnt && fec0_mii_bus) { 1966 fep->mii_bus = fec0_mii_bus; 1967 mii_cnt++; 1968 return 0; 1969 } 1970 return -ENOENT; 1971 } 1972 1973 fep->mii_timeout = 0; 1974 1975 /* 1976 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 1977 * 1978 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 1979 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 1980 * Reference Manual has an error on this, and gets fixed on i.MX6Q 1981 * document. 1982 */ 1983 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000); 1984 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1985 fep->phy_speed--; 1986 fep->phy_speed <<= 1; 1987 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1988 1989 fep->mii_bus = mdiobus_alloc(); 1990 if (fep->mii_bus == NULL) { 1991 err = -ENOMEM; 1992 goto err_out; 1993 } 1994 1995 fep->mii_bus->name = "fec_enet_mii_bus"; 1996 fep->mii_bus->read = fec_enet_mdio_read; 1997 fep->mii_bus->write = fec_enet_mdio_write; 1998 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1999 pdev->name, fep->dev_id + 1); 2000 fep->mii_bus->priv = fep; 2001 fep->mii_bus->parent = &pdev->dev; 2002 2003 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 2004 if (!fep->mii_bus->irq) { 2005 err = -ENOMEM; 2006 goto err_out_free_mdiobus; 2007 } 2008 2009 for (i = 0; i < PHY_MAX_ADDR; i++) 2010 fep->mii_bus->irq[i] = PHY_POLL; 2011 2012 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2013 if (node) { 2014 err = of_mdiobus_register(fep->mii_bus, node); 2015 of_node_put(node); 2016 } else { 2017 err = mdiobus_register(fep->mii_bus); 2018 } 2019 2020 if (err) 2021 goto err_out_free_mdio_irq; 2022 2023 mii_cnt++; 2024 2025 /* save fec0 mii_bus */ 2026 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 2027 fec0_mii_bus = fep->mii_bus; 2028 2029 return 0; 2030 2031 err_out_free_mdio_irq: 2032 kfree(fep->mii_bus->irq); 2033 err_out_free_mdiobus: 2034 mdiobus_free(fep->mii_bus); 2035 err_out: 2036 return err; 2037 } 2038 2039 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2040 { 2041 if (--mii_cnt == 0) { 2042 mdiobus_unregister(fep->mii_bus); 2043 kfree(fep->mii_bus->irq); 2044 mdiobus_free(fep->mii_bus); 2045 } 2046 } 2047 2048 static int fec_enet_get_settings(struct net_device *ndev, 2049 struct ethtool_cmd *cmd) 2050 { 2051 struct fec_enet_private *fep = netdev_priv(ndev); 2052 struct phy_device *phydev = fep->phy_dev; 2053 2054 if (!phydev) 2055 return -ENODEV; 2056 2057 return phy_ethtool_gset(phydev, cmd); 2058 } 2059 2060 static int fec_enet_set_settings(struct net_device *ndev, 2061 struct ethtool_cmd *cmd) 2062 { 2063 struct fec_enet_private *fep = netdev_priv(ndev); 2064 struct phy_device *phydev = fep->phy_dev; 2065 2066 if (!phydev) 2067 return -ENODEV; 2068 2069 return phy_ethtool_sset(phydev, cmd); 2070 } 2071 2072 static void fec_enet_get_drvinfo(struct net_device *ndev, 2073 struct ethtool_drvinfo *info) 2074 { 2075 struct fec_enet_private *fep = netdev_priv(ndev); 2076 2077 strlcpy(info->driver, fep->pdev->dev.driver->name, 2078 sizeof(info->driver)); 2079 strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); 2080 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2081 } 2082 2083 static int fec_enet_get_ts_info(struct net_device *ndev, 2084 struct ethtool_ts_info *info) 2085 { 2086 struct fec_enet_private *fep = netdev_priv(ndev); 2087 2088 if (fep->bufdesc_ex) { 2089 2090 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2091 SOF_TIMESTAMPING_RX_SOFTWARE | 2092 SOF_TIMESTAMPING_SOFTWARE | 2093 SOF_TIMESTAMPING_TX_HARDWARE | 2094 SOF_TIMESTAMPING_RX_HARDWARE | 2095 SOF_TIMESTAMPING_RAW_HARDWARE; 2096 if (fep->ptp_clock) 2097 info->phc_index = ptp_clock_index(fep->ptp_clock); 2098 else 2099 info->phc_index = -1; 2100 2101 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2102 (1 << HWTSTAMP_TX_ON); 2103 2104 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2105 (1 << HWTSTAMP_FILTER_ALL); 2106 return 0; 2107 } else { 2108 return ethtool_op_get_ts_info(ndev, info); 2109 } 2110 } 2111 2112 #if !defined(CONFIG_M5272) 2113 2114 static void fec_enet_get_pauseparam(struct net_device *ndev, 2115 struct ethtool_pauseparam *pause) 2116 { 2117 struct fec_enet_private *fep = netdev_priv(ndev); 2118 2119 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2120 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2121 pause->rx_pause = pause->tx_pause; 2122 } 2123 2124 static int fec_enet_set_pauseparam(struct net_device *ndev, 2125 struct ethtool_pauseparam *pause) 2126 { 2127 struct fec_enet_private *fep = netdev_priv(ndev); 2128 2129 if (!fep->phy_dev) 2130 return -ENODEV; 2131 2132 if (pause->tx_pause != pause->rx_pause) { 2133 netdev_info(ndev, 2134 "hardware only support enable/disable both tx and rx"); 2135 return -EINVAL; 2136 } 2137 2138 fep->pause_flag = 0; 2139 2140 /* tx pause must be same as rx pause */ 2141 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2142 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2143 2144 if (pause->rx_pause || pause->autoneg) { 2145 fep->phy_dev->supported |= ADVERTISED_Pause; 2146 fep->phy_dev->advertising |= ADVERTISED_Pause; 2147 } else { 2148 fep->phy_dev->supported &= ~ADVERTISED_Pause; 2149 fep->phy_dev->advertising &= ~ADVERTISED_Pause; 2150 } 2151 2152 if (pause->autoneg) { 2153 if (netif_running(ndev)) 2154 fec_stop(ndev); 2155 phy_start_aneg(fep->phy_dev); 2156 } 2157 if (netif_running(ndev)) { 2158 napi_disable(&fep->napi); 2159 netif_tx_lock_bh(ndev); 2160 fec_restart(ndev); 2161 netif_wake_queue(ndev); 2162 netif_tx_unlock_bh(ndev); 2163 napi_enable(&fep->napi); 2164 } 2165 2166 return 0; 2167 } 2168 2169 static const struct fec_stat { 2170 char name[ETH_GSTRING_LEN]; 2171 u16 offset; 2172 } fec_stats[] = { 2173 /* RMON TX */ 2174 { "tx_dropped", RMON_T_DROP }, 2175 { "tx_packets", RMON_T_PACKETS }, 2176 { "tx_broadcast", RMON_T_BC_PKT }, 2177 { "tx_multicast", RMON_T_MC_PKT }, 2178 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2179 { "tx_undersize", RMON_T_UNDERSIZE }, 2180 { "tx_oversize", RMON_T_OVERSIZE }, 2181 { "tx_fragment", RMON_T_FRAG }, 2182 { "tx_jabber", RMON_T_JAB }, 2183 { "tx_collision", RMON_T_COL }, 2184 { "tx_64byte", RMON_T_P64 }, 2185 { "tx_65to127byte", RMON_T_P65TO127 }, 2186 { "tx_128to255byte", RMON_T_P128TO255 }, 2187 { "tx_256to511byte", RMON_T_P256TO511 }, 2188 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2189 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2190 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2191 { "tx_octets", RMON_T_OCTETS }, 2192 2193 /* IEEE TX */ 2194 { "IEEE_tx_drop", IEEE_T_DROP }, 2195 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2196 { "IEEE_tx_1col", IEEE_T_1COL }, 2197 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2198 { "IEEE_tx_def", IEEE_T_DEF }, 2199 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2200 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2201 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2202 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2203 { "IEEE_tx_sqe", IEEE_T_SQE }, 2204 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2205 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2206 2207 /* RMON RX */ 2208 { "rx_packets", RMON_R_PACKETS }, 2209 { "rx_broadcast", RMON_R_BC_PKT }, 2210 { "rx_multicast", RMON_R_MC_PKT }, 2211 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2212 { "rx_undersize", RMON_R_UNDERSIZE }, 2213 { "rx_oversize", RMON_R_OVERSIZE }, 2214 { "rx_fragment", RMON_R_FRAG }, 2215 { "rx_jabber", RMON_R_JAB }, 2216 { "rx_64byte", RMON_R_P64 }, 2217 { "rx_65to127byte", RMON_R_P65TO127 }, 2218 { "rx_128to255byte", RMON_R_P128TO255 }, 2219 { "rx_256to511byte", RMON_R_P256TO511 }, 2220 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2221 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2222 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2223 { "rx_octets", RMON_R_OCTETS }, 2224 2225 /* IEEE RX */ 2226 { "IEEE_rx_drop", IEEE_R_DROP }, 2227 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2228 { "IEEE_rx_crc", IEEE_R_CRC }, 2229 { "IEEE_rx_align", IEEE_R_ALIGN }, 2230 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2231 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2232 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2233 }; 2234 2235 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2236 struct ethtool_stats *stats, u64 *data) 2237 { 2238 struct fec_enet_private *fep = netdev_priv(dev); 2239 int i; 2240 2241 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2242 data[i] = readl(fep->hwp + fec_stats[i].offset); 2243 } 2244 2245 static void fec_enet_get_strings(struct net_device *netdev, 2246 u32 stringset, u8 *data) 2247 { 2248 int i; 2249 switch (stringset) { 2250 case ETH_SS_STATS: 2251 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2252 memcpy(data + i * ETH_GSTRING_LEN, 2253 fec_stats[i].name, ETH_GSTRING_LEN); 2254 break; 2255 } 2256 } 2257 2258 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2259 { 2260 switch (sset) { 2261 case ETH_SS_STATS: 2262 return ARRAY_SIZE(fec_stats); 2263 default: 2264 return -EOPNOTSUPP; 2265 } 2266 } 2267 #endif /* !defined(CONFIG_M5272) */ 2268 2269 static int fec_enet_nway_reset(struct net_device *dev) 2270 { 2271 struct fec_enet_private *fep = netdev_priv(dev); 2272 struct phy_device *phydev = fep->phy_dev; 2273 2274 if (!phydev) 2275 return -ENODEV; 2276 2277 return genphy_restart_aneg(phydev); 2278 } 2279 2280 /* ITR clock source is enet system clock (clk_ahb). 2281 * TCTT unit is cycle_ns * 64 cycle 2282 * So, the ICTT value = X us / (cycle_ns * 64) 2283 */ 2284 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2285 { 2286 struct fec_enet_private *fep = netdev_priv(ndev); 2287 2288 return us * (fep->itr_clk_rate / 64000) / 1000; 2289 } 2290 2291 /* Set threshold for interrupt coalescing */ 2292 static void fec_enet_itr_coal_set(struct net_device *ndev) 2293 { 2294 struct fec_enet_private *fep = netdev_priv(ndev); 2295 const struct platform_device_id *id_entry = 2296 platform_get_device_id(fep->pdev); 2297 int rx_itr, tx_itr; 2298 2299 if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB)) 2300 return; 2301 2302 /* Must be greater than zero to avoid unpredictable behavior */ 2303 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2304 !fep->tx_time_itr || !fep->tx_pkts_itr) 2305 return; 2306 2307 /* Select enet system clock as Interrupt Coalescing 2308 * timer Clock Source 2309 */ 2310 rx_itr = FEC_ITR_CLK_SEL; 2311 tx_itr = FEC_ITR_CLK_SEL; 2312 2313 /* set ICFT and ICTT */ 2314 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2315 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2316 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2317 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2318 2319 rx_itr |= FEC_ITR_EN; 2320 tx_itr |= FEC_ITR_EN; 2321 2322 writel(tx_itr, fep->hwp + FEC_TXIC0); 2323 writel(rx_itr, fep->hwp + FEC_RXIC0); 2324 writel(tx_itr, fep->hwp + FEC_TXIC1); 2325 writel(rx_itr, fep->hwp + FEC_RXIC1); 2326 writel(tx_itr, fep->hwp + FEC_TXIC2); 2327 writel(rx_itr, fep->hwp + FEC_RXIC2); 2328 } 2329 2330 static int 2331 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2332 { 2333 struct fec_enet_private *fep = netdev_priv(ndev); 2334 const struct platform_device_id *id_entry = 2335 platform_get_device_id(fep->pdev); 2336 2337 if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB)) 2338 return -EOPNOTSUPP; 2339 2340 ec->rx_coalesce_usecs = fep->rx_time_itr; 2341 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2342 2343 ec->tx_coalesce_usecs = fep->tx_time_itr; 2344 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2345 2346 return 0; 2347 } 2348 2349 static int 2350 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2351 { 2352 struct fec_enet_private *fep = netdev_priv(ndev); 2353 const struct platform_device_id *id_entry = 2354 platform_get_device_id(fep->pdev); 2355 2356 unsigned int cycle; 2357 2358 if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB)) 2359 return -EOPNOTSUPP; 2360 2361 if (ec->rx_max_coalesced_frames > 255) { 2362 pr_err("Rx coalesced frames exceed hardware limiation"); 2363 return -EINVAL; 2364 } 2365 2366 if (ec->tx_max_coalesced_frames > 255) { 2367 pr_err("Tx coalesced frame exceed hardware limiation"); 2368 return -EINVAL; 2369 } 2370 2371 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); 2372 if (cycle > 0xFFFF) { 2373 pr_err("Rx coalesed usec exceeed hardware limiation"); 2374 return -EINVAL; 2375 } 2376 2377 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); 2378 if (cycle > 0xFFFF) { 2379 pr_err("Rx coalesed usec exceeed hardware limiation"); 2380 return -EINVAL; 2381 } 2382 2383 fep->rx_time_itr = ec->rx_coalesce_usecs; 2384 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2385 2386 fep->tx_time_itr = ec->tx_coalesce_usecs; 2387 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2388 2389 fec_enet_itr_coal_set(ndev); 2390 2391 return 0; 2392 } 2393 2394 static void fec_enet_itr_coal_init(struct net_device *ndev) 2395 { 2396 struct ethtool_coalesce ec; 2397 2398 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2399 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2400 2401 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2402 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2403 2404 fec_enet_set_coalesce(ndev, &ec); 2405 } 2406 2407 static int fec_enet_get_tunable(struct net_device *netdev, 2408 const struct ethtool_tunable *tuna, 2409 void *data) 2410 { 2411 struct fec_enet_private *fep = netdev_priv(netdev); 2412 int ret = 0; 2413 2414 switch (tuna->id) { 2415 case ETHTOOL_RX_COPYBREAK: 2416 *(u32 *)data = fep->rx_copybreak; 2417 break; 2418 default: 2419 ret = -EINVAL; 2420 break; 2421 } 2422 2423 return ret; 2424 } 2425 2426 static int fec_enet_set_tunable(struct net_device *netdev, 2427 const struct ethtool_tunable *tuna, 2428 const void *data) 2429 { 2430 struct fec_enet_private *fep = netdev_priv(netdev); 2431 int ret = 0; 2432 2433 switch (tuna->id) { 2434 case ETHTOOL_RX_COPYBREAK: 2435 fep->rx_copybreak = *(u32 *)data; 2436 break; 2437 default: 2438 ret = -EINVAL; 2439 break; 2440 } 2441 2442 return ret; 2443 } 2444 2445 static const struct ethtool_ops fec_enet_ethtool_ops = { 2446 .get_settings = fec_enet_get_settings, 2447 .set_settings = fec_enet_set_settings, 2448 .get_drvinfo = fec_enet_get_drvinfo, 2449 .nway_reset = fec_enet_nway_reset, 2450 .get_link = ethtool_op_get_link, 2451 .get_coalesce = fec_enet_get_coalesce, 2452 .set_coalesce = fec_enet_set_coalesce, 2453 #ifndef CONFIG_M5272 2454 .get_pauseparam = fec_enet_get_pauseparam, 2455 .set_pauseparam = fec_enet_set_pauseparam, 2456 .get_strings = fec_enet_get_strings, 2457 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2458 .get_sset_count = fec_enet_get_sset_count, 2459 #endif 2460 .get_ts_info = fec_enet_get_ts_info, 2461 .get_tunable = fec_enet_get_tunable, 2462 .set_tunable = fec_enet_set_tunable, 2463 }; 2464 2465 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2466 { 2467 struct fec_enet_private *fep = netdev_priv(ndev); 2468 struct phy_device *phydev = fep->phy_dev; 2469 2470 if (!netif_running(ndev)) 2471 return -EINVAL; 2472 2473 if (!phydev) 2474 return -ENODEV; 2475 2476 if (fep->bufdesc_ex) { 2477 if (cmd == SIOCSHWTSTAMP) 2478 return fec_ptp_set(ndev, rq); 2479 if (cmd == SIOCGHWTSTAMP) 2480 return fec_ptp_get(ndev, rq); 2481 } 2482 2483 return phy_mii_ioctl(phydev, rq, cmd); 2484 } 2485 2486 static void fec_enet_free_buffers(struct net_device *ndev) 2487 { 2488 struct fec_enet_private *fep = netdev_priv(ndev); 2489 unsigned int i; 2490 struct sk_buff *skb; 2491 struct bufdesc *bdp; 2492 struct fec_enet_priv_tx_q *txq; 2493 struct fec_enet_priv_rx_q *rxq; 2494 unsigned int q; 2495 2496 for (q = 0; q < fep->num_rx_queues; q++) { 2497 rxq = fep->rx_queue[q]; 2498 bdp = rxq->rx_bd_base; 2499 for (i = 0; i < rxq->rx_ring_size; i++) { 2500 skb = rxq->rx_skbuff[i]; 2501 rxq->rx_skbuff[i] = NULL; 2502 if (skb) { 2503 dma_unmap_single(&fep->pdev->dev, 2504 bdp->cbd_bufaddr, 2505 FEC_ENET_RX_FRSIZE - fep->rx_align, 2506 DMA_FROM_DEVICE); 2507 dev_kfree_skb(skb); 2508 } 2509 bdp = fec_enet_get_nextdesc(bdp, fep, q); 2510 } 2511 } 2512 2513 for (q = 0; q < fep->num_tx_queues; q++) { 2514 txq = fep->tx_queue[q]; 2515 bdp = txq->tx_bd_base; 2516 for (i = 0; i < txq->tx_ring_size; i++) { 2517 kfree(txq->tx_bounce[i]); 2518 txq->tx_bounce[i] = NULL; 2519 skb = txq->tx_skbuff[i]; 2520 txq->tx_skbuff[i] = NULL; 2521 dev_kfree_skb(skb); 2522 } 2523 } 2524 } 2525 2526 static void fec_enet_free_queue(struct net_device *ndev) 2527 { 2528 struct fec_enet_private *fep = netdev_priv(ndev); 2529 int i; 2530 struct fec_enet_priv_tx_q *txq; 2531 2532 for (i = 0; i < fep->num_tx_queues; i++) 2533 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2534 txq = fep->tx_queue[i]; 2535 dma_free_coherent(NULL, 2536 txq->tx_ring_size * TSO_HEADER_SIZE, 2537 txq->tso_hdrs, 2538 txq->tso_hdrs_dma); 2539 } 2540 2541 for (i = 0; i < fep->num_rx_queues; i++) 2542 if (fep->rx_queue[i]) 2543 kfree(fep->rx_queue[i]); 2544 2545 for (i = 0; i < fep->num_tx_queues; i++) 2546 if (fep->tx_queue[i]) 2547 kfree(fep->tx_queue[i]); 2548 } 2549 2550 static int fec_enet_alloc_queue(struct net_device *ndev) 2551 { 2552 struct fec_enet_private *fep = netdev_priv(ndev); 2553 int i; 2554 int ret = 0; 2555 struct fec_enet_priv_tx_q *txq; 2556 2557 for (i = 0; i < fep->num_tx_queues; i++) { 2558 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 2559 if (!txq) { 2560 ret = -ENOMEM; 2561 goto alloc_failed; 2562 } 2563 2564 fep->tx_queue[i] = txq; 2565 txq->tx_ring_size = TX_RING_SIZE; 2566 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size; 2567 2568 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2569 txq->tx_wake_threshold = 2570 (txq->tx_ring_size - txq->tx_stop_threshold) / 2; 2571 2572 txq->tso_hdrs = dma_alloc_coherent(NULL, 2573 txq->tx_ring_size * TSO_HEADER_SIZE, 2574 &txq->tso_hdrs_dma, 2575 GFP_KERNEL); 2576 if (!txq->tso_hdrs) { 2577 ret = -ENOMEM; 2578 goto alloc_failed; 2579 } 2580 } 2581 2582 for (i = 0; i < fep->num_rx_queues; i++) { 2583 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 2584 GFP_KERNEL); 2585 if (!fep->rx_queue[i]) { 2586 ret = -ENOMEM; 2587 goto alloc_failed; 2588 } 2589 2590 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE; 2591 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size; 2592 } 2593 return ret; 2594 2595 alloc_failed: 2596 fec_enet_free_queue(ndev); 2597 return ret; 2598 } 2599 2600 static int 2601 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 2602 { 2603 struct fec_enet_private *fep = netdev_priv(ndev); 2604 unsigned int i; 2605 struct sk_buff *skb; 2606 struct bufdesc *bdp; 2607 struct fec_enet_priv_rx_q *rxq; 2608 2609 rxq = fep->rx_queue[queue]; 2610 bdp = rxq->rx_bd_base; 2611 for (i = 0; i < rxq->rx_ring_size; i++) { 2612 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2613 if (!skb) 2614 goto err_alloc; 2615 2616 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 2617 dev_kfree_skb(skb); 2618 goto err_alloc; 2619 } 2620 2621 rxq->rx_skbuff[i] = skb; 2622 bdp->cbd_sc = BD_ENET_RX_EMPTY; 2623 2624 if (fep->bufdesc_ex) { 2625 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2626 ebdp->cbd_esc = BD_ENET_RX_INT; 2627 } 2628 2629 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 2630 } 2631 2632 /* Set the last buffer to wrap. */ 2633 bdp = fec_enet_get_prevdesc(bdp, fep, queue); 2634 bdp->cbd_sc |= BD_SC_WRAP; 2635 return 0; 2636 2637 err_alloc: 2638 fec_enet_free_buffers(ndev); 2639 return -ENOMEM; 2640 } 2641 2642 static int 2643 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 2644 { 2645 struct fec_enet_private *fep = netdev_priv(ndev); 2646 unsigned int i; 2647 struct bufdesc *bdp; 2648 struct fec_enet_priv_tx_q *txq; 2649 2650 txq = fep->tx_queue[queue]; 2651 bdp = txq->tx_bd_base; 2652 for (i = 0; i < txq->tx_ring_size; i++) { 2653 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2654 if (!txq->tx_bounce[i]) 2655 goto err_alloc; 2656 2657 bdp->cbd_sc = 0; 2658 bdp->cbd_bufaddr = 0; 2659 2660 if (fep->bufdesc_ex) { 2661 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2662 ebdp->cbd_esc = BD_ENET_TX_INT; 2663 } 2664 2665 bdp = fec_enet_get_nextdesc(bdp, fep, queue); 2666 } 2667 2668 /* Set the last buffer to wrap. */ 2669 bdp = fec_enet_get_prevdesc(bdp, fep, queue); 2670 bdp->cbd_sc |= BD_SC_WRAP; 2671 2672 return 0; 2673 2674 err_alloc: 2675 fec_enet_free_buffers(ndev); 2676 return -ENOMEM; 2677 } 2678 2679 static int fec_enet_alloc_buffers(struct net_device *ndev) 2680 { 2681 struct fec_enet_private *fep = netdev_priv(ndev); 2682 unsigned int i; 2683 2684 for (i = 0; i < fep->num_rx_queues; i++) 2685 if (fec_enet_alloc_rxq_buffers(ndev, i)) 2686 return -ENOMEM; 2687 2688 for (i = 0; i < fep->num_tx_queues; i++) 2689 if (fec_enet_alloc_txq_buffers(ndev, i)) 2690 return -ENOMEM; 2691 return 0; 2692 } 2693 2694 static int 2695 fec_enet_open(struct net_device *ndev) 2696 { 2697 struct fec_enet_private *fep = netdev_priv(ndev); 2698 int ret; 2699 2700 pinctrl_pm_select_default_state(&fep->pdev->dev); 2701 ret = fec_enet_clk_enable(ndev, true); 2702 if (ret) 2703 return ret; 2704 2705 /* I should reset the ring buffers here, but I don't yet know 2706 * a simple way to do that. 2707 */ 2708 2709 ret = fec_enet_alloc_buffers(ndev); 2710 if (ret) 2711 goto err_enet_alloc; 2712 2713 /* Probe and connect to PHY when open the interface */ 2714 ret = fec_enet_mii_probe(ndev); 2715 if (ret) 2716 goto err_enet_mii_probe; 2717 2718 fec_restart(ndev); 2719 napi_enable(&fep->napi); 2720 phy_start(fep->phy_dev); 2721 netif_tx_start_all_queues(ndev); 2722 2723 return 0; 2724 2725 err_enet_mii_probe: 2726 fec_enet_free_buffers(ndev); 2727 err_enet_alloc: 2728 fec_enet_clk_enable(ndev, false); 2729 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2730 return ret; 2731 } 2732 2733 static int 2734 fec_enet_close(struct net_device *ndev) 2735 { 2736 struct fec_enet_private *fep = netdev_priv(ndev); 2737 2738 phy_stop(fep->phy_dev); 2739 2740 if (netif_device_present(ndev)) { 2741 napi_disable(&fep->napi); 2742 netif_tx_disable(ndev); 2743 fec_stop(ndev); 2744 } 2745 2746 phy_disconnect(fep->phy_dev); 2747 fep->phy_dev = NULL; 2748 2749 fec_enet_clk_enable(ndev, false); 2750 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 2751 fec_enet_free_buffers(ndev); 2752 2753 return 0; 2754 } 2755 2756 /* Set or clear the multicast filter for this adaptor. 2757 * Skeleton taken from sunlance driver. 2758 * The CPM Ethernet implementation allows Multicast as well as individual 2759 * MAC address filtering. Some of the drivers check to make sure it is 2760 * a group multicast address, and discard those that are not. I guess I 2761 * will do the same for now, but just remove the test if you want 2762 * individual filtering as well (do the upper net layers want or support 2763 * this kind of feature?). 2764 */ 2765 2766 #define HASH_BITS 6 /* #bits in hash */ 2767 #define CRC32_POLY 0xEDB88320 2768 2769 static void set_multicast_list(struct net_device *ndev) 2770 { 2771 struct fec_enet_private *fep = netdev_priv(ndev); 2772 struct netdev_hw_addr *ha; 2773 unsigned int i, bit, data, crc, tmp; 2774 unsigned char hash; 2775 2776 if (ndev->flags & IFF_PROMISC) { 2777 tmp = readl(fep->hwp + FEC_R_CNTRL); 2778 tmp |= 0x8; 2779 writel(tmp, fep->hwp + FEC_R_CNTRL); 2780 return; 2781 } 2782 2783 tmp = readl(fep->hwp + FEC_R_CNTRL); 2784 tmp &= ~0x8; 2785 writel(tmp, fep->hwp + FEC_R_CNTRL); 2786 2787 if (ndev->flags & IFF_ALLMULTI) { 2788 /* Catch all multicast addresses, so set the 2789 * filter to all 1's 2790 */ 2791 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2792 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2793 2794 return; 2795 } 2796 2797 /* Clear filter and add the addresses in hash register 2798 */ 2799 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2800 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2801 2802 netdev_for_each_mc_addr(ha, ndev) { 2803 /* calculate crc32 value of mac address */ 2804 crc = 0xffffffff; 2805 2806 for (i = 0; i < ndev->addr_len; i++) { 2807 data = ha->addr[i]; 2808 for (bit = 0; bit < 8; bit++, data >>= 1) { 2809 crc = (crc >> 1) ^ 2810 (((crc ^ data) & 1) ? CRC32_POLY : 0); 2811 } 2812 } 2813 2814 /* only upper 6 bits (HASH_BITS) are used 2815 * which point to specific bit in he hash registers 2816 */ 2817 hash = (crc >> (32 - HASH_BITS)) & 0x3f; 2818 2819 if (hash > 31) { 2820 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2821 tmp |= 1 << (hash - 32); 2822 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 2823 } else { 2824 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2825 tmp |= 1 << hash; 2826 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 2827 } 2828 } 2829 } 2830 2831 /* Set a MAC change in hardware. */ 2832 static int 2833 fec_set_mac_address(struct net_device *ndev, void *p) 2834 { 2835 struct fec_enet_private *fep = netdev_priv(ndev); 2836 struct sockaddr *addr = p; 2837 2838 if (addr) { 2839 if (!is_valid_ether_addr(addr->sa_data)) 2840 return -EADDRNOTAVAIL; 2841 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 2842 } 2843 2844 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 2845 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 2846 fep->hwp + FEC_ADDR_LOW); 2847 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 2848 fep->hwp + FEC_ADDR_HIGH); 2849 return 0; 2850 } 2851 2852 #ifdef CONFIG_NET_POLL_CONTROLLER 2853 /** 2854 * fec_poll_controller - FEC Poll controller function 2855 * @dev: The FEC network adapter 2856 * 2857 * Polled functionality used by netconsole and others in non interrupt mode 2858 * 2859 */ 2860 static void fec_poll_controller(struct net_device *dev) 2861 { 2862 int i; 2863 struct fec_enet_private *fep = netdev_priv(dev); 2864 2865 for (i = 0; i < FEC_IRQ_NUM; i++) { 2866 if (fep->irq[i] > 0) { 2867 disable_irq(fep->irq[i]); 2868 fec_enet_interrupt(fep->irq[i], dev); 2869 enable_irq(fep->irq[i]); 2870 } 2871 } 2872 } 2873 #endif 2874 2875 #define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM 2876 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 2877 netdev_features_t features) 2878 { 2879 struct fec_enet_private *fep = netdev_priv(netdev); 2880 netdev_features_t changed = features ^ netdev->features; 2881 2882 netdev->features = features; 2883 2884 /* Receive checksum has been changed */ 2885 if (changed & NETIF_F_RXCSUM) { 2886 if (features & NETIF_F_RXCSUM) 2887 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 2888 else 2889 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 2890 } 2891 } 2892 2893 static int fec_set_features(struct net_device *netdev, 2894 netdev_features_t features) 2895 { 2896 struct fec_enet_private *fep = netdev_priv(netdev); 2897 netdev_features_t changed = features ^ netdev->features; 2898 2899 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) { 2900 napi_disable(&fep->napi); 2901 netif_tx_lock_bh(netdev); 2902 fec_stop(netdev); 2903 fec_enet_set_netdev_features(netdev, features); 2904 fec_restart(netdev); 2905 netif_tx_wake_all_queues(netdev); 2906 netif_tx_unlock_bh(netdev); 2907 napi_enable(&fep->napi); 2908 } else { 2909 fec_enet_set_netdev_features(netdev, features); 2910 } 2911 2912 return 0; 2913 } 2914 2915 static const struct net_device_ops fec_netdev_ops = { 2916 .ndo_open = fec_enet_open, 2917 .ndo_stop = fec_enet_close, 2918 .ndo_start_xmit = fec_enet_start_xmit, 2919 .ndo_set_rx_mode = set_multicast_list, 2920 .ndo_change_mtu = eth_change_mtu, 2921 .ndo_validate_addr = eth_validate_addr, 2922 .ndo_tx_timeout = fec_timeout, 2923 .ndo_set_mac_address = fec_set_mac_address, 2924 .ndo_do_ioctl = fec_enet_ioctl, 2925 #ifdef CONFIG_NET_POLL_CONTROLLER 2926 .ndo_poll_controller = fec_poll_controller, 2927 #endif 2928 .ndo_set_features = fec_set_features, 2929 }; 2930 2931 /* 2932 * XXX: We need to clean up on failure exits here. 2933 * 2934 */ 2935 static int fec_enet_init(struct net_device *ndev) 2936 { 2937 struct fec_enet_private *fep = netdev_priv(ndev); 2938 const struct platform_device_id *id_entry = 2939 platform_get_device_id(fep->pdev); 2940 struct fec_enet_priv_tx_q *txq; 2941 struct fec_enet_priv_rx_q *rxq; 2942 struct bufdesc *cbd_base; 2943 dma_addr_t bd_dma; 2944 int bd_size; 2945 unsigned int i; 2946 2947 #if defined(CONFIG_ARM) 2948 fep->rx_align = 0xf; 2949 fep->tx_align = 0xf; 2950 #else 2951 fep->rx_align = 0x3; 2952 fep->tx_align = 0x3; 2953 #endif 2954 2955 fec_enet_alloc_queue(ndev); 2956 2957 if (fep->bufdesc_ex) 2958 fep->bufdesc_size = sizeof(struct bufdesc_ex); 2959 else 2960 fep->bufdesc_size = sizeof(struct bufdesc); 2961 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * 2962 fep->bufdesc_size; 2963 2964 /* Allocate memory for buffer descriptors. */ 2965 cbd_base = dma_alloc_coherent(NULL, bd_size, &bd_dma, 2966 GFP_KERNEL); 2967 if (!cbd_base) { 2968 return -ENOMEM; 2969 } 2970 2971 memset(cbd_base, 0, bd_size); 2972 2973 /* Get the Ethernet address */ 2974 fec_get_mac(ndev); 2975 /* make sure MAC we just acquired is programmed into the hw */ 2976 fec_set_mac_address(ndev, NULL); 2977 2978 /* Set receive and transmit descriptor base. */ 2979 for (i = 0; i < fep->num_rx_queues; i++) { 2980 rxq = fep->rx_queue[i]; 2981 rxq->index = i; 2982 rxq->rx_bd_base = (struct bufdesc *)cbd_base; 2983 rxq->bd_dma = bd_dma; 2984 if (fep->bufdesc_ex) { 2985 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size; 2986 cbd_base = (struct bufdesc *) 2987 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size); 2988 } else { 2989 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size; 2990 cbd_base += rxq->rx_ring_size; 2991 } 2992 } 2993 2994 for (i = 0; i < fep->num_tx_queues; i++) { 2995 txq = fep->tx_queue[i]; 2996 txq->index = i; 2997 txq->tx_bd_base = (struct bufdesc *)cbd_base; 2998 txq->bd_dma = bd_dma; 2999 if (fep->bufdesc_ex) { 3000 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size; 3001 cbd_base = (struct bufdesc *) 3002 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size); 3003 } else { 3004 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size; 3005 cbd_base += txq->tx_ring_size; 3006 } 3007 } 3008 3009 3010 /* The FEC Ethernet specific entries in the device structure */ 3011 ndev->watchdog_timeo = TX_TIMEOUT; 3012 ndev->netdev_ops = &fec_netdev_ops; 3013 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3014 3015 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3016 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3017 3018 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) 3019 /* enable hw VLAN support */ 3020 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3021 3022 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) { 3023 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3024 3025 /* enable hw accelerator */ 3026 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3027 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3028 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3029 } 3030 3031 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB) { 3032 fep->tx_align = 0; 3033 fep->rx_align = 0x3f; 3034 } 3035 3036 ndev->hw_features = ndev->features; 3037 3038 fec_restart(ndev); 3039 3040 return 0; 3041 } 3042 3043 #ifdef CONFIG_OF 3044 static void fec_reset_phy(struct platform_device *pdev) 3045 { 3046 int err, phy_reset; 3047 int msec = 1; 3048 struct device_node *np = pdev->dev.of_node; 3049 3050 if (!np) 3051 return; 3052 3053 of_property_read_u32(np, "phy-reset-duration", &msec); 3054 /* A sane reset duration should not be longer than 1s */ 3055 if (msec > 1000) 3056 msec = 1; 3057 3058 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3059 if (!gpio_is_valid(phy_reset)) 3060 return; 3061 3062 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3063 GPIOF_OUT_INIT_LOW, "phy-reset"); 3064 if (err) { 3065 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3066 return; 3067 } 3068 msleep(msec); 3069 gpio_set_value(phy_reset, 1); 3070 } 3071 #else /* CONFIG_OF */ 3072 static void fec_reset_phy(struct platform_device *pdev) 3073 { 3074 /* 3075 * In case of platform probe, the reset has been done 3076 * by machine code. 3077 */ 3078 } 3079 #endif /* CONFIG_OF */ 3080 3081 static void 3082 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3083 { 3084 struct device_node *np = pdev->dev.of_node; 3085 int err; 3086 3087 *num_tx = *num_rx = 1; 3088 3089 if (!np || !of_device_is_available(np)) 3090 return; 3091 3092 /* parse the num of tx and rx queues */ 3093 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3094 if (err) 3095 *num_tx = 1; 3096 3097 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3098 if (err) 3099 *num_rx = 1; 3100 3101 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3102 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3103 *num_tx); 3104 *num_tx = 1; 3105 return; 3106 } 3107 3108 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3109 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3110 *num_rx); 3111 *num_rx = 1; 3112 return; 3113 } 3114 3115 } 3116 3117 static int 3118 fec_probe(struct platform_device *pdev) 3119 { 3120 struct fec_enet_private *fep; 3121 struct fec_platform_data *pdata; 3122 struct net_device *ndev; 3123 int i, irq, ret = 0; 3124 struct resource *r; 3125 const struct of_device_id *of_id; 3126 static int dev_id; 3127 struct device_node *np = pdev->dev.of_node, *phy_node; 3128 int num_tx_qs; 3129 int num_rx_qs; 3130 3131 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3132 if (of_id) 3133 pdev->id_entry = of_id->data; 3134 3135 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3136 3137 /* Init network device */ 3138 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private), 3139 num_tx_qs, num_rx_qs); 3140 if (!ndev) 3141 return -ENOMEM; 3142 3143 SET_NETDEV_DEV(ndev, &pdev->dev); 3144 3145 /* setup board info structure */ 3146 fep = netdev_priv(ndev); 3147 3148 fep->num_rx_queues = num_rx_qs; 3149 fep->num_tx_queues = num_tx_qs; 3150 3151 #if !defined(CONFIG_M5272) 3152 /* default enable pause frame auto negotiation */ 3153 if (pdev->id_entry && 3154 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT)) 3155 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3156 #endif 3157 3158 /* Select default pin state */ 3159 pinctrl_pm_select_default_state(&pdev->dev); 3160 3161 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3162 fep->hwp = devm_ioremap_resource(&pdev->dev, r); 3163 if (IS_ERR(fep->hwp)) { 3164 ret = PTR_ERR(fep->hwp); 3165 goto failed_ioremap; 3166 } 3167 3168 fep->pdev = pdev; 3169 fep->dev_id = dev_id++; 3170 3171 fep->bufdesc_ex = 0; 3172 3173 platform_set_drvdata(pdev, ndev); 3174 3175 phy_node = of_parse_phandle(np, "phy-handle", 0); 3176 if (!phy_node && of_phy_is_fixed_link(np)) { 3177 ret = of_phy_register_fixed_link(np); 3178 if (ret < 0) { 3179 dev_err(&pdev->dev, 3180 "broken fixed-link specification\n"); 3181 goto failed_phy; 3182 } 3183 phy_node = of_node_get(np); 3184 } 3185 fep->phy_node = phy_node; 3186 3187 ret = of_get_phy_mode(pdev->dev.of_node); 3188 if (ret < 0) { 3189 pdata = dev_get_platdata(&pdev->dev); 3190 if (pdata) 3191 fep->phy_interface = pdata->phy; 3192 else 3193 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3194 } else { 3195 fep->phy_interface = ret; 3196 } 3197 3198 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3199 if (IS_ERR(fep->clk_ipg)) { 3200 ret = PTR_ERR(fep->clk_ipg); 3201 goto failed_clk; 3202 } 3203 3204 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3205 if (IS_ERR(fep->clk_ahb)) { 3206 ret = PTR_ERR(fep->clk_ahb); 3207 goto failed_clk; 3208 } 3209 3210 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3211 3212 /* enet_out is optional, depends on board */ 3213 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3214 if (IS_ERR(fep->clk_enet_out)) 3215 fep->clk_enet_out = NULL; 3216 3217 fep->ptp_clk_on = false; 3218 mutex_init(&fep->ptp_clk_mutex); 3219 3220 /* clk_ref is optional, depends on board */ 3221 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3222 if (IS_ERR(fep->clk_ref)) 3223 fep->clk_ref = NULL; 3224 3225 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3226 fep->bufdesc_ex = 3227 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX; 3228 if (IS_ERR(fep->clk_ptp)) { 3229 fep->clk_ptp = NULL; 3230 fep->bufdesc_ex = 0; 3231 } 3232 3233 ret = fec_enet_clk_enable(ndev, true); 3234 if (ret) 3235 goto failed_clk; 3236 3237 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); 3238 if (!IS_ERR(fep->reg_phy)) { 3239 ret = regulator_enable(fep->reg_phy); 3240 if (ret) { 3241 dev_err(&pdev->dev, 3242 "Failed to enable phy regulator: %d\n", ret); 3243 goto failed_regulator; 3244 } 3245 } else { 3246 fep->reg_phy = NULL; 3247 } 3248 3249 fec_reset_phy(pdev); 3250 3251 if (fep->bufdesc_ex) 3252 fec_ptp_init(pdev); 3253 3254 ret = fec_enet_init(ndev); 3255 if (ret) 3256 goto failed_init; 3257 3258 for (i = 0; i < FEC_IRQ_NUM; i++) { 3259 irq = platform_get_irq(pdev, i); 3260 if (irq < 0) { 3261 if (i) 3262 break; 3263 ret = irq; 3264 goto failed_irq; 3265 } 3266 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3267 0, pdev->name, ndev); 3268 if (ret) 3269 goto failed_irq; 3270 } 3271 3272 init_completion(&fep->mdio_done); 3273 ret = fec_enet_mii_init(pdev); 3274 if (ret) 3275 goto failed_mii_init; 3276 3277 /* Carrier starts down, phylib will bring it up */ 3278 netif_carrier_off(ndev); 3279 fec_enet_clk_enable(ndev, false); 3280 pinctrl_pm_select_sleep_state(&pdev->dev); 3281 3282 ret = register_netdev(ndev); 3283 if (ret) 3284 goto failed_register; 3285 3286 if (fep->bufdesc_ex && fep->ptp_clock) 3287 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3288 3289 fep->rx_copybreak = COPYBREAK_DEFAULT; 3290 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3291 return 0; 3292 3293 failed_register: 3294 fec_enet_mii_remove(fep); 3295 failed_mii_init: 3296 failed_irq: 3297 failed_init: 3298 if (fep->reg_phy) 3299 regulator_disable(fep->reg_phy); 3300 failed_regulator: 3301 fec_enet_clk_enable(ndev, false); 3302 failed_clk: 3303 failed_phy: 3304 of_node_put(phy_node); 3305 failed_ioremap: 3306 free_netdev(ndev); 3307 3308 return ret; 3309 } 3310 3311 static int 3312 fec_drv_remove(struct platform_device *pdev) 3313 { 3314 struct net_device *ndev = platform_get_drvdata(pdev); 3315 struct fec_enet_private *fep = netdev_priv(ndev); 3316 3317 cancel_delayed_work_sync(&fep->time_keep); 3318 cancel_work_sync(&fep->tx_timeout_work); 3319 unregister_netdev(ndev); 3320 fec_enet_mii_remove(fep); 3321 if (fep->reg_phy) 3322 regulator_disable(fep->reg_phy); 3323 if (fep->ptp_clock) 3324 ptp_clock_unregister(fep->ptp_clock); 3325 fec_enet_clk_enable(ndev, false); 3326 of_node_put(fep->phy_node); 3327 free_netdev(ndev); 3328 3329 return 0; 3330 } 3331 3332 static int __maybe_unused fec_suspend(struct device *dev) 3333 { 3334 struct net_device *ndev = dev_get_drvdata(dev); 3335 struct fec_enet_private *fep = netdev_priv(ndev); 3336 3337 rtnl_lock(); 3338 if (netif_running(ndev)) { 3339 phy_stop(fep->phy_dev); 3340 napi_disable(&fep->napi); 3341 netif_tx_lock_bh(ndev); 3342 netif_device_detach(ndev); 3343 netif_tx_unlock_bh(ndev); 3344 fec_stop(ndev); 3345 } 3346 rtnl_unlock(); 3347 3348 fec_enet_clk_enable(ndev, false); 3349 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3350 3351 if (fep->reg_phy) 3352 regulator_disable(fep->reg_phy); 3353 3354 return 0; 3355 } 3356 3357 static int __maybe_unused fec_resume(struct device *dev) 3358 { 3359 struct net_device *ndev = dev_get_drvdata(dev); 3360 struct fec_enet_private *fep = netdev_priv(ndev); 3361 int ret; 3362 3363 if (fep->reg_phy) { 3364 ret = regulator_enable(fep->reg_phy); 3365 if (ret) 3366 return ret; 3367 } 3368 3369 pinctrl_pm_select_default_state(&fep->pdev->dev); 3370 ret = fec_enet_clk_enable(ndev, true); 3371 if (ret) 3372 goto failed_clk; 3373 3374 rtnl_lock(); 3375 if (netif_running(ndev)) { 3376 fec_restart(ndev); 3377 netif_tx_lock_bh(ndev); 3378 netif_device_attach(ndev); 3379 netif_tx_unlock_bh(ndev); 3380 napi_enable(&fep->napi); 3381 phy_start(fep->phy_dev); 3382 } 3383 rtnl_unlock(); 3384 3385 return 0; 3386 3387 failed_clk: 3388 if (fep->reg_phy) 3389 regulator_disable(fep->reg_phy); 3390 return ret; 3391 } 3392 3393 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume); 3394 3395 static struct platform_driver fec_driver = { 3396 .driver = { 3397 .name = DRIVER_NAME, 3398 .owner = THIS_MODULE, 3399 .pm = &fec_pm_ops, 3400 .of_match_table = fec_dt_ids, 3401 }, 3402 .id_table = fec_devtype, 3403 .probe = fec_probe, 3404 .remove = fec_drv_remove, 3405 }; 3406 3407 module_platform_driver(fec_driver); 3408 3409 MODULE_ALIAS("platform:"DRIVER_NAME); 3410 MODULE_LICENSE("GPL"); 3411