1 /* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 * 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/string.h> 27 #include <linux/ptrace.h> 28 #include <linux/errno.h> 29 #include <linux/ioport.h> 30 #include <linux/slab.h> 31 #include <linux/interrupt.h> 32 #include <linux/init.h> 33 #include <linux/delay.h> 34 #include <linux/netdevice.h> 35 #include <linux/etherdevice.h> 36 #include <linux/skbuff.h> 37 #include <linux/in.h> 38 #include <linux/ip.h> 39 #include <net/ip.h> 40 #include <linux/tcp.h> 41 #include <linux/udp.h> 42 #include <linux/icmp.h> 43 #include <linux/spinlock.h> 44 #include <linux/workqueue.h> 45 #include <linux/bitops.h> 46 #include <linux/io.h> 47 #include <linux/irq.h> 48 #include <linux/clk.h> 49 #include <linux/platform_device.h> 50 #include <linux/phy.h> 51 #include <linux/fec.h> 52 #include <linux/of.h> 53 #include <linux/of_device.h> 54 #include <linux/of_gpio.h> 55 #include <linux/of_net.h> 56 #include <linux/regulator/consumer.h> 57 #include <linux/if_vlan.h> 58 59 #include <asm/cacheflush.h> 60 61 #include "fec.h" 62 63 static void set_multicast_list(struct net_device *ndev); 64 65 #if defined(CONFIG_ARM) 66 #define FEC_ALIGNMENT 0xf 67 #else 68 #define FEC_ALIGNMENT 0x3 69 #endif 70 71 #define DRIVER_NAME "fec" 72 #define FEC_NAPI_WEIGHT 64 73 74 /* Pause frame feild and FIFO threshold */ 75 #define FEC_ENET_FCE (1 << 5) 76 #define FEC_ENET_RSEM_V 0x84 77 #define FEC_ENET_RSFL_V 16 78 #define FEC_ENET_RAEM_V 0x8 79 #define FEC_ENET_RAFL_V 0x8 80 #define FEC_ENET_OPD_V 0xFFF0 81 82 /* Controller is ENET-MAC */ 83 #define FEC_QUIRK_ENET_MAC (1 << 0) 84 /* Controller needs driver to swap frame */ 85 #define FEC_QUIRK_SWAP_FRAME (1 << 1) 86 /* Controller uses gasket */ 87 #define FEC_QUIRK_USE_GASKET (1 << 2) 88 /* Controller has GBIT support */ 89 #define FEC_QUIRK_HAS_GBIT (1 << 3) 90 /* Controller has extend desc buffer */ 91 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) 92 /* Controller has hardware checksum support */ 93 #define FEC_QUIRK_HAS_CSUM (1 << 5) 94 /* Controller has hardware vlan support */ 95 #define FEC_QUIRK_HAS_VLAN (1 << 6) 96 97 static struct platform_device_id fec_devtype[] = { 98 { 99 /* keep it for coldfire */ 100 .name = DRIVER_NAME, 101 .driver_data = 0, 102 }, { 103 .name = "imx25-fec", 104 .driver_data = FEC_QUIRK_USE_GASKET, 105 }, { 106 .name = "imx27-fec", 107 .driver_data = 0, 108 }, { 109 .name = "imx28-fec", 110 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, 111 }, { 112 .name = "imx6q-fec", 113 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 114 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 115 FEC_QUIRK_HAS_VLAN, 116 }, { 117 .name = "mvf600-fec", 118 .driver_data = FEC_QUIRK_ENET_MAC, 119 }, { 120 /* sentinel */ 121 } 122 }; 123 MODULE_DEVICE_TABLE(platform, fec_devtype); 124 125 enum imx_fec_type { 126 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 127 IMX27_FEC, /* runs on i.mx27/35/51 */ 128 IMX28_FEC, 129 IMX6Q_FEC, 130 MVF600_FEC, 131 }; 132 133 static const struct of_device_id fec_dt_ids[] = { 134 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 135 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 136 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 137 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 138 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 139 { /* sentinel */ } 140 }; 141 MODULE_DEVICE_TABLE(of, fec_dt_ids); 142 143 static unsigned char macaddr[ETH_ALEN]; 144 module_param_array(macaddr, byte, NULL, 0); 145 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 146 147 #if defined(CONFIG_M5272) 148 /* 149 * Some hardware gets it MAC address out of local flash memory. 150 * if this is non-zero then assume it is the address to get MAC from. 151 */ 152 #if defined(CONFIG_NETtel) 153 #define FEC_FLASHMAC 0xf0006006 154 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 155 #define FEC_FLASHMAC 0xf0006000 156 #elif defined(CONFIG_CANCam) 157 #define FEC_FLASHMAC 0xf0020000 158 #elif defined (CONFIG_M5272C3) 159 #define FEC_FLASHMAC (0xffe04000 + 4) 160 #elif defined(CONFIG_MOD5272) 161 #define FEC_FLASHMAC 0xffc0406b 162 #else 163 #define FEC_FLASHMAC 0 164 #endif 165 #endif /* CONFIG_M5272 */ 166 167 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE) 168 #error "FEC: descriptor ring size constants too large" 169 #endif 170 171 /* Interrupt events/masks. */ 172 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ 173 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ 174 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ 175 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ 176 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ 177 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ 178 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ 179 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ 180 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ 181 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ 182 183 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) 184 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) 185 186 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 187 */ 188 #define PKT_MAXBUF_SIZE 1522 189 #define PKT_MINBUF_SIZE 64 190 #define PKT_MAXBLR_SIZE 1536 191 192 /* FEC receive acceleration */ 193 #define FEC_RACC_IPDIS (1 << 1) 194 #define FEC_RACC_PRODIS (1 << 2) 195 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 196 197 /* 198 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 199 * size bits. Other FEC hardware does not, so we need to take that into 200 * account when setting it. 201 */ 202 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 203 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 204 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 205 #else 206 #define OPT_FRAME_SIZE 0 207 #endif 208 209 /* FEC MII MMFR bits definition */ 210 #define FEC_MMFR_ST (1 << 30) 211 #define FEC_MMFR_OP_READ (2 << 28) 212 #define FEC_MMFR_OP_WRITE (1 << 28) 213 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 214 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 215 #define FEC_MMFR_TA (2 << 16) 216 #define FEC_MMFR_DATA(v) (v & 0xffff) 217 218 #define FEC_MII_TIMEOUT 30000 /* us */ 219 220 /* Transmitter timeout */ 221 #define TX_TIMEOUT (2 * HZ) 222 223 #define FEC_PAUSE_FLAG_AUTONEG 0x1 224 #define FEC_PAUSE_FLAG_ENABLE 0x2 225 226 static int mii_cnt; 227 228 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex) 229 { 230 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; 231 if (is_ex) 232 return (struct bufdesc *)(ex + 1); 233 else 234 return bdp + 1; 235 } 236 237 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex) 238 { 239 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; 240 if (is_ex) 241 return (struct bufdesc *)(ex - 1); 242 else 243 return bdp - 1; 244 } 245 246 static void *swap_buffer(void *bufaddr, int len) 247 { 248 int i; 249 unsigned int *buf = bufaddr; 250 251 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++) 252 *buf = cpu_to_be32(*buf); 253 254 return bufaddr; 255 } 256 257 static int 258 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 259 { 260 /* Only run for packets requiring a checksum. */ 261 if (skb->ip_summed != CHECKSUM_PARTIAL) 262 return 0; 263 264 if (unlikely(skb_cow_head(skb, 0))) 265 return -1; 266 267 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 268 269 return 0; 270 } 271 272 static netdev_tx_t 273 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 274 { 275 struct fec_enet_private *fep = netdev_priv(ndev); 276 const struct platform_device_id *id_entry = 277 platform_get_device_id(fep->pdev); 278 struct bufdesc *bdp; 279 void *bufaddr; 280 unsigned short status; 281 unsigned int index; 282 283 if (!fep->link) { 284 /* Link is down or auto-negotiation is in progress. */ 285 return NETDEV_TX_BUSY; 286 } 287 288 /* Fill in a Tx ring entry */ 289 bdp = fep->cur_tx; 290 291 status = bdp->cbd_sc; 292 293 if (status & BD_ENET_TX_READY) { 294 /* Ooops. All transmit buffers are full. Bail out. 295 * This should not happen, since ndev->tbusy should be set. 296 */ 297 netdev_err(ndev, "tx queue full!\n"); 298 return NETDEV_TX_BUSY; 299 } 300 301 /* Protocol checksum off-load for TCP and UDP. */ 302 if (fec_enet_clear_csum(skb, ndev)) { 303 kfree_skb(skb); 304 return NETDEV_TX_OK; 305 } 306 307 /* Clear all of the status flags */ 308 status &= ~BD_ENET_TX_STATS; 309 310 /* Set buffer length and buffer pointer */ 311 bufaddr = skb->data; 312 bdp->cbd_datlen = skb->len; 313 314 /* 315 * On some FEC implementations data must be aligned on 316 * 4-byte boundaries. Use bounce buffers to copy data 317 * and get it aligned. Ugh. 318 */ 319 if (fep->bufdesc_ex) 320 index = (struct bufdesc_ex *)bdp - 321 (struct bufdesc_ex *)fep->tx_bd_base; 322 else 323 index = bdp - fep->tx_bd_base; 324 325 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { 326 memcpy(fep->tx_bounce[index], skb->data, skb->len); 327 bufaddr = fep->tx_bounce[index]; 328 } 329 330 /* 331 * Some design made an incorrect assumption on endian mode of 332 * the system that it's running on. As the result, driver has to 333 * swap every frame going to and coming from the controller. 334 */ 335 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 336 swap_buffer(bufaddr, skb->len); 337 338 /* Save skb pointer */ 339 fep->tx_skbuff[index] = skb; 340 341 /* Push the data cache so the CPM does not get stale memory 342 * data. 343 */ 344 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, 345 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); 346 347 /* Send it on its way. Tell FEC it's ready, interrupt when done, 348 * it's the last BD of the frame, and to put the CRC on the end. 349 */ 350 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR 351 | BD_ENET_TX_LAST | BD_ENET_TX_TC); 352 bdp->cbd_sc = status; 353 354 if (fep->bufdesc_ex) { 355 356 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 357 ebdp->cbd_bdu = 0; 358 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 359 fep->hwts_tx_en)) { 360 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT); 361 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 362 } else { 363 ebdp->cbd_esc = BD_ENET_TX_INT; 364 365 /* Enable protocol checksum flags 366 * We do not bother with the IP Checksum bits as they 367 * are done by the kernel 368 */ 369 if (skb->ip_summed == CHECKSUM_PARTIAL) 370 ebdp->cbd_esc |= BD_ENET_TX_PINS; 371 } 372 } 373 /* If this was the last BD in the ring, start at the beginning again. */ 374 if (status & BD_ENET_TX_WRAP) 375 bdp = fep->tx_bd_base; 376 else 377 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 378 379 fep->cur_tx = bdp; 380 381 if (fep->cur_tx == fep->dirty_tx) 382 netif_stop_queue(ndev); 383 384 /* Trigger transmission start */ 385 writel(0, fep->hwp + FEC_X_DES_ACTIVE); 386 387 skb_tx_timestamp(skb); 388 389 return NETDEV_TX_OK; 390 } 391 392 /* Init RX & TX buffer descriptors 393 */ 394 static void fec_enet_bd_init(struct net_device *dev) 395 { 396 struct fec_enet_private *fep = netdev_priv(dev); 397 struct bufdesc *bdp; 398 unsigned int i; 399 400 /* Initialize the receive buffer descriptors. */ 401 bdp = fep->rx_bd_base; 402 for (i = 0; i < RX_RING_SIZE; i++) { 403 404 /* Initialize the BD for every fragment in the page. */ 405 if (bdp->cbd_bufaddr) 406 bdp->cbd_sc = BD_ENET_RX_EMPTY; 407 else 408 bdp->cbd_sc = 0; 409 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 410 } 411 412 /* Set the last buffer to wrap */ 413 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); 414 bdp->cbd_sc |= BD_SC_WRAP; 415 416 fep->cur_rx = fep->rx_bd_base; 417 418 /* ...and the same for transmit */ 419 bdp = fep->tx_bd_base; 420 fep->cur_tx = bdp; 421 for (i = 0; i < TX_RING_SIZE; i++) { 422 423 /* Initialize the BD for every fragment in the page. */ 424 bdp->cbd_sc = 0; 425 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) { 426 dev_kfree_skb_any(fep->tx_skbuff[i]); 427 fep->tx_skbuff[i] = NULL; 428 } 429 bdp->cbd_bufaddr = 0; 430 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 431 } 432 433 /* Set the last buffer to wrap */ 434 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); 435 bdp->cbd_sc |= BD_SC_WRAP; 436 fep->dirty_tx = bdp; 437 } 438 439 /* This function is called to start or restart the FEC during a link 440 * change. This only happens when switching between half and full 441 * duplex. 442 */ 443 static void 444 fec_restart(struct net_device *ndev, int duplex) 445 { 446 struct fec_enet_private *fep = netdev_priv(ndev); 447 const struct platform_device_id *id_entry = 448 platform_get_device_id(fep->pdev); 449 int i; 450 u32 val; 451 u32 temp_mac[2]; 452 u32 rcntl = OPT_FRAME_SIZE | 0x04; 453 u32 ecntl = 0x2; /* ETHEREN */ 454 455 if (netif_running(ndev)) { 456 netif_device_detach(ndev); 457 napi_disable(&fep->napi); 458 netif_stop_queue(ndev); 459 netif_tx_lock_bh(ndev); 460 } 461 462 /* Whack a reset. We should wait for this. */ 463 writel(1, fep->hwp + FEC_ECNTRL); 464 udelay(10); 465 466 /* 467 * enet-mac reset will reset mac address registers too, 468 * so need to reconfigure it. 469 */ 470 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 471 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 472 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); 473 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); 474 } 475 476 /* Clear any outstanding interrupt. */ 477 writel(0xffc00000, fep->hwp + FEC_IEVENT); 478 479 /* Setup multicast filter. */ 480 set_multicast_list(ndev); 481 #ifndef CONFIG_M5272 482 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 483 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 484 #endif 485 486 /* Set maximum receive buffer size. */ 487 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); 488 489 fec_enet_bd_init(ndev); 490 491 /* Set receive and transmit descriptor base. */ 492 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); 493 if (fep->bufdesc_ex) 494 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex) 495 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); 496 else 497 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) 498 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); 499 500 501 for (i = 0; i <= TX_RING_MOD_MASK; i++) { 502 if (fep->tx_skbuff[i]) { 503 dev_kfree_skb_any(fep->tx_skbuff[i]); 504 fep->tx_skbuff[i] = NULL; 505 } 506 } 507 508 /* Enable MII mode */ 509 if (duplex) { 510 /* FD enable */ 511 writel(0x04, fep->hwp + FEC_X_CNTRL); 512 } else { 513 /* No Rcv on Xmit */ 514 rcntl |= 0x02; 515 writel(0x0, fep->hwp + FEC_X_CNTRL); 516 } 517 518 fep->full_duplex = duplex; 519 520 /* Set MII speed */ 521 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 522 523 #if !defined(CONFIG_M5272) 524 /* set RX checksum */ 525 val = readl(fep->hwp + FEC_RACC); 526 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 527 val |= FEC_RACC_OPTIONS; 528 else 529 val &= ~FEC_RACC_OPTIONS; 530 writel(val, fep->hwp + FEC_RACC); 531 #endif 532 533 /* 534 * The phy interface and speed need to get configured 535 * differently on enet-mac. 536 */ 537 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 538 /* Enable flow control and length check */ 539 rcntl |= 0x40000000 | 0x00000020; 540 541 /* RGMII, RMII or MII */ 542 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) 543 rcntl |= (1 << 6); 544 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 545 rcntl |= (1 << 8); 546 else 547 rcntl &= ~(1 << 8); 548 549 /* 1G, 100M or 10M */ 550 if (fep->phy_dev) { 551 if (fep->phy_dev->speed == SPEED_1000) 552 ecntl |= (1 << 5); 553 else if (fep->phy_dev->speed == SPEED_100) 554 rcntl &= ~(1 << 9); 555 else 556 rcntl |= (1 << 9); 557 } 558 } else { 559 #ifdef FEC_MIIGSK_ENR 560 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { 561 u32 cfgr; 562 /* disable the gasket and wait */ 563 writel(0, fep->hwp + FEC_MIIGSK_ENR); 564 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 565 udelay(1); 566 567 /* 568 * configure the gasket: 569 * RMII, 50 MHz, no loopback, no echo 570 * MII, 25 MHz, no loopback, no echo 571 */ 572 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 573 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 574 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) 575 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 576 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 577 578 /* re-enable the gasket */ 579 writel(2, fep->hwp + FEC_MIIGSK_ENR); 580 } 581 #endif 582 } 583 584 #if !defined(CONFIG_M5272) 585 /* enable pause frame*/ 586 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 587 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 588 fep->phy_dev && fep->phy_dev->pause)) { 589 rcntl |= FEC_ENET_FCE; 590 591 /* set FIFO threshold parameter to reduce overrun */ 592 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 593 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 594 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 595 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 596 597 /* OPD */ 598 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 599 } else { 600 rcntl &= ~FEC_ENET_FCE; 601 } 602 #endif /* !defined(CONFIG_M5272) */ 603 604 writel(rcntl, fep->hwp + FEC_R_CNTRL); 605 606 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 607 /* enable ENET endian swap */ 608 ecntl |= (1 << 8); 609 /* enable ENET store and forward mode */ 610 writel(1 << 8, fep->hwp + FEC_X_WMRK); 611 } 612 613 if (fep->bufdesc_ex) 614 ecntl |= (1 << 4); 615 616 #ifndef CONFIG_M5272 617 /* Enable the MIB statistic event counters */ 618 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 619 #endif 620 621 /* And last, enable the transmit and receive processing */ 622 writel(ecntl, fep->hwp + FEC_ECNTRL); 623 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 624 625 if (fep->bufdesc_ex) 626 fec_ptp_start_cyclecounter(ndev); 627 628 /* Enable interrupts we wish to service */ 629 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 630 631 if (netif_running(ndev)) { 632 netif_tx_unlock_bh(ndev); 633 netif_wake_queue(ndev); 634 napi_enable(&fep->napi); 635 netif_device_attach(ndev); 636 } 637 } 638 639 static void 640 fec_stop(struct net_device *ndev) 641 { 642 struct fec_enet_private *fep = netdev_priv(ndev); 643 const struct platform_device_id *id_entry = 644 platform_get_device_id(fep->pdev); 645 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 646 647 /* We cannot expect a graceful transmit stop without link !!! */ 648 if (fep->link) { 649 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 650 udelay(10); 651 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 652 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 653 } 654 655 /* Whack a reset. We should wait for this. */ 656 writel(1, fep->hwp + FEC_ECNTRL); 657 udelay(10); 658 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 659 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 660 661 /* We have to keep ENET enabled to have MII interrupt stay working */ 662 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 663 writel(2, fep->hwp + FEC_ECNTRL); 664 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 665 } 666 } 667 668 669 static void 670 fec_timeout(struct net_device *ndev) 671 { 672 struct fec_enet_private *fep = netdev_priv(ndev); 673 674 ndev->stats.tx_errors++; 675 676 fep->delay_work.timeout = true; 677 schedule_delayed_work(&(fep->delay_work.delay_work), 0); 678 } 679 680 static void fec_enet_work(struct work_struct *work) 681 { 682 struct fec_enet_private *fep = 683 container_of(work, 684 struct fec_enet_private, 685 delay_work.delay_work.work); 686 687 if (fep->delay_work.timeout) { 688 fep->delay_work.timeout = false; 689 fec_restart(fep->netdev, fep->full_duplex); 690 netif_wake_queue(fep->netdev); 691 } 692 } 693 694 static void 695 fec_enet_tx(struct net_device *ndev) 696 { 697 struct fec_enet_private *fep; 698 struct bufdesc *bdp; 699 unsigned short status; 700 struct sk_buff *skb; 701 int index = 0; 702 703 fep = netdev_priv(ndev); 704 bdp = fep->dirty_tx; 705 706 /* get next bdp of dirty_tx */ 707 if (bdp->cbd_sc & BD_ENET_TX_WRAP) 708 bdp = fep->tx_bd_base; 709 else 710 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 711 712 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { 713 714 /* current queue is empty */ 715 if (bdp == fep->cur_tx) 716 break; 717 718 if (fep->bufdesc_ex) 719 index = (struct bufdesc_ex *)bdp - 720 (struct bufdesc_ex *)fep->tx_bd_base; 721 else 722 index = bdp - fep->tx_bd_base; 723 724 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 725 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); 726 bdp->cbd_bufaddr = 0; 727 728 skb = fep->tx_skbuff[index]; 729 730 /* Check for errors. */ 731 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 732 BD_ENET_TX_RL | BD_ENET_TX_UN | 733 BD_ENET_TX_CSL)) { 734 ndev->stats.tx_errors++; 735 if (status & BD_ENET_TX_HB) /* No heartbeat */ 736 ndev->stats.tx_heartbeat_errors++; 737 if (status & BD_ENET_TX_LC) /* Late collision */ 738 ndev->stats.tx_window_errors++; 739 if (status & BD_ENET_TX_RL) /* Retrans limit */ 740 ndev->stats.tx_aborted_errors++; 741 if (status & BD_ENET_TX_UN) /* Underrun */ 742 ndev->stats.tx_fifo_errors++; 743 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 744 ndev->stats.tx_carrier_errors++; 745 } else { 746 ndev->stats.tx_packets++; 747 ndev->stats.tx_bytes += bdp->cbd_datlen; 748 } 749 750 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 751 fep->bufdesc_ex) { 752 struct skb_shared_hwtstamps shhwtstamps; 753 unsigned long flags; 754 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 755 756 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 757 spin_lock_irqsave(&fep->tmreg_lock, flags); 758 shhwtstamps.hwtstamp = ns_to_ktime( 759 timecounter_cyc2time(&fep->tc, ebdp->ts)); 760 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 761 skb_tstamp_tx(skb, &shhwtstamps); 762 } 763 764 if (status & BD_ENET_TX_READY) 765 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n"); 766 767 /* Deferred means some collisions occurred during transmit, 768 * but we eventually sent the packet OK. 769 */ 770 if (status & BD_ENET_TX_DEF) 771 ndev->stats.collisions++; 772 773 /* Free the sk buffer associated with this last transmit */ 774 dev_kfree_skb_any(skb); 775 fep->tx_skbuff[index] = NULL; 776 777 fep->dirty_tx = bdp; 778 779 /* Update pointer to next buffer descriptor to be transmitted */ 780 if (status & BD_ENET_TX_WRAP) 781 bdp = fep->tx_bd_base; 782 else 783 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 784 785 /* Since we have freed up a buffer, the ring is no longer full 786 */ 787 if (fep->dirty_tx != fep->cur_tx) { 788 if (netif_queue_stopped(ndev)) 789 netif_wake_queue(ndev); 790 } 791 } 792 return; 793 } 794 795 796 /* During a receive, the cur_rx points to the current incoming buffer. 797 * When we update through the ring, if the next incoming buffer has 798 * not been given to the system, we just set the empty indicator, 799 * effectively tossing the packet. 800 */ 801 static int 802 fec_enet_rx(struct net_device *ndev, int budget) 803 { 804 struct fec_enet_private *fep = netdev_priv(ndev); 805 const struct platform_device_id *id_entry = 806 platform_get_device_id(fep->pdev); 807 struct bufdesc *bdp; 808 unsigned short status; 809 struct sk_buff *skb; 810 ushort pkt_len; 811 __u8 *data; 812 int pkt_received = 0; 813 struct bufdesc_ex *ebdp = NULL; 814 bool vlan_packet_rcvd = false; 815 u16 vlan_tag; 816 817 #ifdef CONFIG_M532x 818 flush_cache_all(); 819 #endif 820 821 /* First, grab all of the stats for the incoming packet. 822 * These get messed up if we get called due to a busy condition. 823 */ 824 bdp = fep->cur_rx; 825 826 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { 827 828 if (pkt_received >= budget) 829 break; 830 pkt_received++; 831 832 /* Since we have allocated space to hold a complete frame, 833 * the last indicator should be set. 834 */ 835 if ((status & BD_ENET_RX_LAST) == 0) 836 netdev_err(ndev, "rcv is not +last\n"); 837 838 if (!fep->opened) 839 goto rx_processing_done; 840 841 /* Check for errors. */ 842 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 843 BD_ENET_RX_CR | BD_ENET_RX_OV)) { 844 ndev->stats.rx_errors++; 845 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { 846 /* Frame too long or too short. */ 847 ndev->stats.rx_length_errors++; 848 } 849 if (status & BD_ENET_RX_NO) /* Frame alignment */ 850 ndev->stats.rx_frame_errors++; 851 if (status & BD_ENET_RX_CR) /* CRC Error */ 852 ndev->stats.rx_crc_errors++; 853 if (status & BD_ENET_RX_OV) /* FIFO overrun */ 854 ndev->stats.rx_fifo_errors++; 855 } 856 857 /* Report late collisions as a frame error. 858 * On this error, the BD is closed, but we don't know what we 859 * have in the buffer. So, just drop this frame on the floor. 860 */ 861 if (status & BD_ENET_RX_CL) { 862 ndev->stats.rx_errors++; 863 ndev->stats.rx_frame_errors++; 864 goto rx_processing_done; 865 } 866 867 /* Process the incoming frame. */ 868 ndev->stats.rx_packets++; 869 pkt_len = bdp->cbd_datlen; 870 ndev->stats.rx_bytes += pkt_len; 871 data = (__u8*)__va(bdp->cbd_bufaddr); 872 873 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 874 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); 875 876 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 877 swap_buffer(data, pkt_len); 878 879 /* Extract the enhanced buffer descriptor */ 880 ebdp = NULL; 881 if (fep->bufdesc_ex) 882 ebdp = (struct bufdesc_ex *)bdp; 883 884 /* If this is a VLAN packet remove the VLAN Tag */ 885 vlan_packet_rcvd = false; 886 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 887 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) { 888 /* Push and remove the vlan tag */ 889 struct vlan_hdr *vlan_header = 890 (struct vlan_hdr *) (data + ETH_HLEN); 891 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 892 pkt_len -= VLAN_HLEN; 893 894 vlan_packet_rcvd = true; 895 } 896 897 /* This does 16 byte alignment, exactly what we need. 898 * The packet length includes FCS, but we don't want to 899 * include that when passing upstream as it messes up 900 * bridging applications. 901 */ 902 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); 903 904 if (unlikely(!skb)) { 905 ndev->stats.rx_dropped++; 906 } else { 907 int payload_offset = (2 * ETH_ALEN); 908 skb_reserve(skb, NET_IP_ALIGN); 909 skb_put(skb, pkt_len - 4); /* Make room */ 910 911 /* Extract the frame data without the VLAN header. */ 912 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN)); 913 if (vlan_packet_rcvd) 914 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN; 915 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN), 916 data + payload_offset, 917 pkt_len - 4 - (2 * ETH_ALEN)); 918 919 skb->protocol = eth_type_trans(skb, ndev); 920 921 /* Get receive timestamp from the skb */ 922 if (fep->hwts_rx_en && fep->bufdesc_ex) { 923 struct skb_shared_hwtstamps *shhwtstamps = 924 skb_hwtstamps(skb); 925 unsigned long flags; 926 927 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 928 929 spin_lock_irqsave(&fep->tmreg_lock, flags); 930 shhwtstamps->hwtstamp = ns_to_ktime( 931 timecounter_cyc2time(&fep->tc, ebdp->ts)); 932 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 933 } 934 935 if (fep->bufdesc_ex && 936 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 937 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) { 938 /* don't check it */ 939 skb->ip_summed = CHECKSUM_UNNECESSARY; 940 } else { 941 skb_checksum_none_assert(skb); 942 } 943 } 944 945 /* Handle received VLAN packets */ 946 if (vlan_packet_rcvd) 947 __vlan_hwaccel_put_tag(skb, 948 htons(ETH_P_8021Q), 949 vlan_tag); 950 951 if (!skb_defer_rx_timestamp(skb)) 952 napi_gro_receive(&fep->napi, skb); 953 } 954 955 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data, 956 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); 957 rx_processing_done: 958 /* Clear the status flags for this buffer */ 959 status &= ~BD_ENET_RX_STATS; 960 961 /* Mark the buffer empty */ 962 status |= BD_ENET_RX_EMPTY; 963 bdp->cbd_sc = status; 964 965 if (fep->bufdesc_ex) { 966 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 967 968 ebdp->cbd_esc = BD_ENET_RX_INT; 969 ebdp->cbd_prot = 0; 970 ebdp->cbd_bdu = 0; 971 } 972 973 /* Update BD pointer to next entry */ 974 if (status & BD_ENET_RX_WRAP) 975 bdp = fep->rx_bd_base; 976 else 977 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 978 /* Doing this here will keep the FEC running while we process 979 * incoming frames. On a heavily loaded network, we should be 980 * able to keep up at the expense of system resources. 981 */ 982 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 983 } 984 fep->cur_rx = bdp; 985 986 return pkt_received; 987 } 988 989 static irqreturn_t 990 fec_enet_interrupt(int irq, void *dev_id) 991 { 992 struct net_device *ndev = dev_id; 993 struct fec_enet_private *fep = netdev_priv(ndev); 994 uint int_events; 995 irqreturn_t ret = IRQ_NONE; 996 997 do { 998 int_events = readl(fep->hwp + FEC_IEVENT); 999 writel(int_events, fep->hwp + FEC_IEVENT); 1000 1001 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) { 1002 ret = IRQ_HANDLED; 1003 1004 /* Disable the RX interrupt */ 1005 if (napi_schedule_prep(&fep->napi)) { 1006 writel(FEC_RX_DISABLED_IMASK, 1007 fep->hwp + FEC_IMASK); 1008 __napi_schedule(&fep->napi); 1009 } 1010 } 1011 1012 if (int_events & FEC_ENET_MII) { 1013 ret = IRQ_HANDLED; 1014 complete(&fep->mdio_done); 1015 } 1016 } while (int_events); 1017 1018 return ret; 1019 } 1020 1021 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1022 { 1023 struct net_device *ndev = napi->dev; 1024 int pkts = fec_enet_rx(ndev, budget); 1025 struct fec_enet_private *fep = netdev_priv(ndev); 1026 1027 fec_enet_tx(ndev); 1028 1029 if (pkts < budget) { 1030 napi_complete(napi); 1031 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1032 } 1033 return pkts; 1034 } 1035 1036 /* ------------------------------------------------------------------------- */ 1037 static void fec_get_mac(struct net_device *ndev) 1038 { 1039 struct fec_enet_private *fep = netdev_priv(ndev); 1040 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1041 unsigned char *iap, tmpaddr[ETH_ALEN]; 1042 1043 /* 1044 * try to get mac address in following order: 1045 * 1046 * 1) module parameter via kernel command line in form 1047 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1048 */ 1049 iap = macaddr; 1050 1051 /* 1052 * 2) from device tree data 1053 */ 1054 if (!is_valid_ether_addr(iap)) { 1055 struct device_node *np = fep->pdev->dev.of_node; 1056 if (np) { 1057 const char *mac = of_get_mac_address(np); 1058 if (mac) 1059 iap = (unsigned char *) mac; 1060 } 1061 } 1062 1063 /* 1064 * 3) from flash or fuse (via platform data) 1065 */ 1066 if (!is_valid_ether_addr(iap)) { 1067 #ifdef CONFIG_M5272 1068 if (FEC_FLASHMAC) 1069 iap = (unsigned char *)FEC_FLASHMAC; 1070 #else 1071 if (pdata) 1072 iap = (unsigned char *)&pdata->mac; 1073 #endif 1074 } 1075 1076 /* 1077 * 4) FEC mac registers set by bootloader 1078 */ 1079 if (!is_valid_ether_addr(iap)) { 1080 *((unsigned long *) &tmpaddr[0]) = 1081 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); 1082 *((unsigned short *) &tmpaddr[4]) = 1083 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1084 iap = &tmpaddr[0]; 1085 } 1086 1087 /* 1088 * 5) random mac address 1089 */ 1090 if (!is_valid_ether_addr(iap)) { 1091 /* Report it and use a random ethernet address instead */ 1092 netdev_err(ndev, "Invalid MAC address: %pM\n", iap); 1093 eth_hw_addr_random(ndev); 1094 netdev_info(ndev, "Using random MAC address: %pM\n", 1095 ndev->dev_addr); 1096 return; 1097 } 1098 1099 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1100 1101 /* Adjust MAC if using macaddr */ 1102 if (iap == macaddr) 1103 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1104 } 1105 1106 /* ------------------------------------------------------------------------- */ 1107 1108 /* 1109 * Phy section 1110 */ 1111 static void fec_enet_adjust_link(struct net_device *ndev) 1112 { 1113 struct fec_enet_private *fep = netdev_priv(ndev); 1114 struct phy_device *phy_dev = fep->phy_dev; 1115 int status_change = 0; 1116 1117 /* Prevent a state halted on mii error */ 1118 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 1119 phy_dev->state = PHY_RESUMING; 1120 return; 1121 } 1122 1123 if (phy_dev->link) { 1124 if (!fep->link) { 1125 fep->link = phy_dev->link; 1126 status_change = 1; 1127 } 1128 1129 if (fep->full_duplex != phy_dev->duplex) 1130 status_change = 1; 1131 1132 if (phy_dev->speed != fep->speed) { 1133 fep->speed = phy_dev->speed; 1134 status_change = 1; 1135 } 1136 1137 /* if any of the above changed restart the FEC */ 1138 if (status_change) 1139 fec_restart(ndev, phy_dev->duplex); 1140 } else { 1141 if (fep->link) { 1142 fec_stop(ndev); 1143 fep->link = phy_dev->link; 1144 status_change = 1; 1145 } 1146 } 1147 1148 if (status_change) 1149 phy_print_status(phy_dev); 1150 } 1151 1152 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1153 { 1154 struct fec_enet_private *fep = bus->priv; 1155 unsigned long time_left; 1156 1157 fep->mii_timeout = 0; 1158 init_completion(&fep->mdio_done); 1159 1160 /* start a read op */ 1161 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 1162 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1163 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1164 1165 /* wait for end of transfer */ 1166 time_left = wait_for_completion_timeout(&fep->mdio_done, 1167 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1168 if (time_left == 0) { 1169 fep->mii_timeout = 1; 1170 netdev_err(fep->netdev, "MDIO read timeout\n"); 1171 return -ETIMEDOUT; 1172 } 1173 1174 /* return value */ 1175 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1176 } 1177 1178 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1179 u16 value) 1180 { 1181 struct fec_enet_private *fep = bus->priv; 1182 unsigned long time_left; 1183 1184 fep->mii_timeout = 0; 1185 init_completion(&fep->mdio_done); 1186 1187 /* start a write op */ 1188 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 1189 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1190 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1191 fep->hwp + FEC_MII_DATA); 1192 1193 /* wait for end of transfer */ 1194 time_left = wait_for_completion_timeout(&fep->mdio_done, 1195 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1196 if (time_left == 0) { 1197 fep->mii_timeout = 1; 1198 netdev_err(fep->netdev, "MDIO write timeout\n"); 1199 return -ETIMEDOUT; 1200 } 1201 1202 return 0; 1203 } 1204 1205 static int fec_enet_mdio_reset(struct mii_bus *bus) 1206 { 1207 return 0; 1208 } 1209 1210 static int fec_enet_mii_probe(struct net_device *ndev) 1211 { 1212 struct fec_enet_private *fep = netdev_priv(ndev); 1213 const struct platform_device_id *id_entry = 1214 platform_get_device_id(fep->pdev); 1215 struct phy_device *phy_dev = NULL; 1216 char mdio_bus_id[MII_BUS_ID_SIZE]; 1217 char phy_name[MII_BUS_ID_SIZE + 3]; 1218 int phy_id; 1219 int dev_id = fep->dev_id; 1220 1221 fep->phy_dev = NULL; 1222 1223 /* check for attached phy */ 1224 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1225 if ((fep->mii_bus->phy_mask & (1 << phy_id))) 1226 continue; 1227 if (fep->mii_bus->phy_map[phy_id] == NULL) 1228 continue; 1229 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) 1230 continue; 1231 if (dev_id--) 1232 continue; 1233 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1234 break; 1235 } 1236 1237 if (phy_id >= PHY_MAX_ADDR) { 1238 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1239 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 1240 phy_id = 0; 1241 } 1242 1243 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); 1244 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 1245 fep->phy_interface); 1246 if (IS_ERR(phy_dev)) { 1247 netdev_err(ndev, "could not attach to PHY\n"); 1248 return PTR_ERR(phy_dev); 1249 } 1250 1251 /* mask with MAC supported features */ 1252 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) { 1253 phy_dev->supported &= PHY_GBIT_FEATURES; 1254 #if !defined(CONFIG_M5272) 1255 phy_dev->supported |= SUPPORTED_Pause; 1256 #endif 1257 } 1258 else 1259 phy_dev->supported &= PHY_BASIC_FEATURES; 1260 1261 phy_dev->advertising = phy_dev->supported; 1262 1263 fep->phy_dev = phy_dev; 1264 fep->link = 0; 1265 fep->full_duplex = 0; 1266 1267 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 1268 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), 1269 fep->phy_dev->irq); 1270 1271 return 0; 1272 } 1273 1274 static int fec_enet_mii_init(struct platform_device *pdev) 1275 { 1276 static struct mii_bus *fec0_mii_bus; 1277 struct net_device *ndev = platform_get_drvdata(pdev); 1278 struct fec_enet_private *fep = netdev_priv(ndev); 1279 const struct platform_device_id *id_entry = 1280 platform_get_device_id(fep->pdev); 1281 int err = -ENXIO, i; 1282 1283 /* 1284 * The dual fec interfaces are not equivalent with enet-mac. 1285 * Here are the differences: 1286 * 1287 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1288 * - fec0 acts as the 1588 time master while fec1 is slave 1289 * - external phys can only be configured by fec0 1290 * 1291 * That is to say fec1 can not work independently. It only works 1292 * when fec0 is working. The reason behind this design is that the 1293 * second interface is added primarily for Switch mode. 1294 * 1295 * Because of the last point above, both phys are attached on fec0 1296 * mdio interface in board design, and need to be configured by 1297 * fec0 mii_bus. 1298 */ 1299 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { 1300 /* fec1 uses fec0 mii_bus */ 1301 if (mii_cnt && fec0_mii_bus) { 1302 fep->mii_bus = fec0_mii_bus; 1303 mii_cnt++; 1304 return 0; 1305 } 1306 return -ENOENT; 1307 } 1308 1309 fep->mii_timeout = 0; 1310 1311 /* 1312 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 1313 * 1314 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 1315 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 1316 * Reference Manual has an error on this, and gets fixed on i.MX6Q 1317 * document. 1318 */ 1319 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000); 1320 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1321 fep->phy_speed--; 1322 fep->phy_speed <<= 1; 1323 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1324 1325 fep->mii_bus = mdiobus_alloc(); 1326 if (fep->mii_bus == NULL) { 1327 err = -ENOMEM; 1328 goto err_out; 1329 } 1330 1331 fep->mii_bus->name = "fec_enet_mii_bus"; 1332 fep->mii_bus->read = fec_enet_mdio_read; 1333 fep->mii_bus->write = fec_enet_mdio_write; 1334 fep->mii_bus->reset = fec_enet_mdio_reset; 1335 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1336 pdev->name, fep->dev_id + 1); 1337 fep->mii_bus->priv = fep; 1338 fep->mii_bus->parent = &pdev->dev; 1339 1340 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 1341 if (!fep->mii_bus->irq) { 1342 err = -ENOMEM; 1343 goto err_out_free_mdiobus; 1344 } 1345 1346 for (i = 0; i < PHY_MAX_ADDR; i++) 1347 fep->mii_bus->irq[i] = PHY_POLL; 1348 1349 if (mdiobus_register(fep->mii_bus)) 1350 goto err_out_free_mdio_irq; 1351 1352 mii_cnt++; 1353 1354 /* save fec0 mii_bus */ 1355 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1356 fec0_mii_bus = fep->mii_bus; 1357 1358 return 0; 1359 1360 err_out_free_mdio_irq: 1361 kfree(fep->mii_bus->irq); 1362 err_out_free_mdiobus: 1363 mdiobus_free(fep->mii_bus); 1364 err_out: 1365 return err; 1366 } 1367 1368 static void fec_enet_mii_remove(struct fec_enet_private *fep) 1369 { 1370 if (--mii_cnt == 0) { 1371 mdiobus_unregister(fep->mii_bus); 1372 kfree(fep->mii_bus->irq); 1373 mdiobus_free(fep->mii_bus); 1374 } 1375 } 1376 1377 static int fec_enet_get_settings(struct net_device *ndev, 1378 struct ethtool_cmd *cmd) 1379 { 1380 struct fec_enet_private *fep = netdev_priv(ndev); 1381 struct phy_device *phydev = fep->phy_dev; 1382 1383 if (!phydev) 1384 return -ENODEV; 1385 1386 return phy_ethtool_gset(phydev, cmd); 1387 } 1388 1389 static int fec_enet_set_settings(struct net_device *ndev, 1390 struct ethtool_cmd *cmd) 1391 { 1392 struct fec_enet_private *fep = netdev_priv(ndev); 1393 struct phy_device *phydev = fep->phy_dev; 1394 1395 if (!phydev) 1396 return -ENODEV; 1397 1398 return phy_ethtool_sset(phydev, cmd); 1399 } 1400 1401 static void fec_enet_get_drvinfo(struct net_device *ndev, 1402 struct ethtool_drvinfo *info) 1403 { 1404 struct fec_enet_private *fep = netdev_priv(ndev); 1405 1406 strlcpy(info->driver, fep->pdev->dev.driver->name, 1407 sizeof(info->driver)); 1408 strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); 1409 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 1410 } 1411 1412 static int fec_enet_get_ts_info(struct net_device *ndev, 1413 struct ethtool_ts_info *info) 1414 { 1415 struct fec_enet_private *fep = netdev_priv(ndev); 1416 1417 if (fep->bufdesc_ex) { 1418 1419 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1420 SOF_TIMESTAMPING_RX_SOFTWARE | 1421 SOF_TIMESTAMPING_SOFTWARE | 1422 SOF_TIMESTAMPING_TX_HARDWARE | 1423 SOF_TIMESTAMPING_RX_HARDWARE | 1424 SOF_TIMESTAMPING_RAW_HARDWARE; 1425 if (fep->ptp_clock) 1426 info->phc_index = ptp_clock_index(fep->ptp_clock); 1427 else 1428 info->phc_index = -1; 1429 1430 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 1431 (1 << HWTSTAMP_TX_ON); 1432 1433 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 1434 (1 << HWTSTAMP_FILTER_ALL); 1435 return 0; 1436 } else { 1437 return ethtool_op_get_ts_info(ndev, info); 1438 } 1439 } 1440 1441 #if !defined(CONFIG_M5272) 1442 1443 static void fec_enet_get_pauseparam(struct net_device *ndev, 1444 struct ethtool_pauseparam *pause) 1445 { 1446 struct fec_enet_private *fep = netdev_priv(ndev); 1447 1448 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 1449 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 1450 pause->rx_pause = pause->tx_pause; 1451 } 1452 1453 static int fec_enet_set_pauseparam(struct net_device *ndev, 1454 struct ethtool_pauseparam *pause) 1455 { 1456 struct fec_enet_private *fep = netdev_priv(ndev); 1457 1458 if (pause->tx_pause != pause->rx_pause) { 1459 netdev_info(ndev, 1460 "hardware only support enable/disable both tx and rx"); 1461 return -EINVAL; 1462 } 1463 1464 fep->pause_flag = 0; 1465 1466 /* tx pause must be same as rx pause */ 1467 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 1468 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 1469 1470 if (pause->rx_pause || pause->autoneg) { 1471 fep->phy_dev->supported |= ADVERTISED_Pause; 1472 fep->phy_dev->advertising |= ADVERTISED_Pause; 1473 } else { 1474 fep->phy_dev->supported &= ~ADVERTISED_Pause; 1475 fep->phy_dev->advertising &= ~ADVERTISED_Pause; 1476 } 1477 1478 if (pause->autoneg) { 1479 if (netif_running(ndev)) 1480 fec_stop(ndev); 1481 phy_start_aneg(fep->phy_dev); 1482 } 1483 if (netif_running(ndev)) 1484 fec_restart(ndev, 0); 1485 1486 return 0; 1487 } 1488 1489 static const struct fec_stat { 1490 char name[ETH_GSTRING_LEN]; 1491 u16 offset; 1492 } fec_stats[] = { 1493 /* RMON TX */ 1494 { "tx_dropped", RMON_T_DROP }, 1495 { "tx_packets", RMON_T_PACKETS }, 1496 { "tx_broadcast", RMON_T_BC_PKT }, 1497 { "tx_multicast", RMON_T_MC_PKT }, 1498 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 1499 { "tx_undersize", RMON_T_UNDERSIZE }, 1500 { "tx_oversize", RMON_T_OVERSIZE }, 1501 { "tx_fragment", RMON_T_FRAG }, 1502 { "tx_jabber", RMON_T_JAB }, 1503 { "tx_collision", RMON_T_COL }, 1504 { "tx_64byte", RMON_T_P64 }, 1505 { "tx_65to127byte", RMON_T_P65TO127 }, 1506 { "tx_128to255byte", RMON_T_P128TO255 }, 1507 { "tx_256to511byte", RMON_T_P256TO511 }, 1508 { "tx_512to1023byte", RMON_T_P512TO1023 }, 1509 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 1510 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 1511 { "tx_octets", RMON_T_OCTETS }, 1512 1513 /* IEEE TX */ 1514 { "IEEE_tx_drop", IEEE_T_DROP }, 1515 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 1516 { "IEEE_tx_1col", IEEE_T_1COL }, 1517 { "IEEE_tx_mcol", IEEE_T_MCOL }, 1518 { "IEEE_tx_def", IEEE_T_DEF }, 1519 { "IEEE_tx_lcol", IEEE_T_LCOL }, 1520 { "IEEE_tx_excol", IEEE_T_EXCOL }, 1521 { "IEEE_tx_macerr", IEEE_T_MACERR }, 1522 { "IEEE_tx_cserr", IEEE_T_CSERR }, 1523 { "IEEE_tx_sqe", IEEE_T_SQE }, 1524 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 1525 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 1526 1527 /* RMON RX */ 1528 { "rx_packets", RMON_R_PACKETS }, 1529 { "rx_broadcast", RMON_R_BC_PKT }, 1530 { "rx_multicast", RMON_R_MC_PKT }, 1531 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 1532 { "rx_undersize", RMON_R_UNDERSIZE }, 1533 { "rx_oversize", RMON_R_OVERSIZE }, 1534 { "rx_fragment", RMON_R_FRAG }, 1535 { "rx_jabber", RMON_R_JAB }, 1536 { "rx_64byte", RMON_R_P64 }, 1537 { "rx_65to127byte", RMON_R_P65TO127 }, 1538 { "rx_128to255byte", RMON_R_P128TO255 }, 1539 { "rx_256to511byte", RMON_R_P256TO511 }, 1540 { "rx_512to1023byte", RMON_R_P512TO1023 }, 1541 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 1542 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 1543 { "rx_octets", RMON_R_OCTETS }, 1544 1545 /* IEEE RX */ 1546 { "IEEE_rx_drop", IEEE_R_DROP }, 1547 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 1548 { "IEEE_rx_crc", IEEE_R_CRC }, 1549 { "IEEE_rx_align", IEEE_R_ALIGN }, 1550 { "IEEE_rx_macerr", IEEE_R_MACERR }, 1551 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 1552 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 1553 }; 1554 1555 static void fec_enet_get_ethtool_stats(struct net_device *dev, 1556 struct ethtool_stats *stats, u64 *data) 1557 { 1558 struct fec_enet_private *fep = netdev_priv(dev); 1559 int i; 1560 1561 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 1562 data[i] = readl(fep->hwp + fec_stats[i].offset); 1563 } 1564 1565 static void fec_enet_get_strings(struct net_device *netdev, 1566 u32 stringset, u8 *data) 1567 { 1568 int i; 1569 switch (stringset) { 1570 case ETH_SS_STATS: 1571 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 1572 memcpy(data + i * ETH_GSTRING_LEN, 1573 fec_stats[i].name, ETH_GSTRING_LEN); 1574 break; 1575 } 1576 } 1577 1578 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 1579 { 1580 switch (sset) { 1581 case ETH_SS_STATS: 1582 return ARRAY_SIZE(fec_stats); 1583 default: 1584 return -EOPNOTSUPP; 1585 } 1586 } 1587 #endif /* !defined(CONFIG_M5272) */ 1588 1589 static int fec_enet_nway_reset(struct net_device *dev) 1590 { 1591 struct fec_enet_private *fep = netdev_priv(dev); 1592 struct phy_device *phydev = fep->phy_dev; 1593 1594 if (!phydev) 1595 return -ENODEV; 1596 1597 return genphy_restart_aneg(phydev); 1598 } 1599 1600 static const struct ethtool_ops fec_enet_ethtool_ops = { 1601 #if !defined(CONFIG_M5272) 1602 .get_pauseparam = fec_enet_get_pauseparam, 1603 .set_pauseparam = fec_enet_set_pauseparam, 1604 #endif 1605 .get_settings = fec_enet_get_settings, 1606 .set_settings = fec_enet_set_settings, 1607 .get_drvinfo = fec_enet_get_drvinfo, 1608 .get_link = ethtool_op_get_link, 1609 .get_ts_info = fec_enet_get_ts_info, 1610 .nway_reset = fec_enet_nway_reset, 1611 #ifndef CONFIG_M5272 1612 .get_ethtool_stats = fec_enet_get_ethtool_stats, 1613 .get_strings = fec_enet_get_strings, 1614 .get_sset_count = fec_enet_get_sset_count, 1615 #endif 1616 }; 1617 1618 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 1619 { 1620 struct fec_enet_private *fep = netdev_priv(ndev); 1621 struct phy_device *phydev = fep->phy_dev; 1622 1623 if (!netif_running(ndev)) 1624 return -EINVAL; 1625 1626 if (!phydev) 1627 return -ENODEV; 1628 1629 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex) 1630 return fec_ptp_ioctl(ndev, rq, cmd); 1631 1632 return phy_mii_ioctl(phydev, rq, cmd); 1633 } 1634 1635 static void fec_enet_free_buffers(struct net_device *ndev) 1636 { 1637 struct fec_enet_private *fep = netdev_priv(ndev); 1638 unsigned int i; 1639 struct sk_buff *skb; 1640 struct bufdesc *bdp; 1641 1642 bdp = fep->rx_bd_base; 1643 for (i = 0; i < RX_RING_SIZE; i++) { 1644 skb = fep->rx_skbuff[i]; 1645 1646 if (bdp->cbd_bufaddr) 1647 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 1648 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1649 if (skb) 1650 dev_kfree_skb(skb); 1651 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 1652 } 1653 1654 bdp = fep->tx_bd_base; 1655 for (i = 0; i < TX_RING_SIZE; i++) 1656 kfree(fep->tx_bounce[i]); 1657 } 1658 1659 static int fec_enet_alloc_buffers(struct net_device *ndev) 1660 { 1661 struct fec_enet_private *fep = netdev_priv(ndev); 1662 unsigned int i; 1663 struct sk_buff *skb; 1664 struct bufdesc *bdp; 1665 1666 bdp = fep->rx_bd_base; 1667 for (i = 0; i < RX_RING_SIZE; i++) { 1668 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1669 if (!skb) { 1670 fec_enet_free_buffers(ndev); 1671 return -ENOMEM; 1672 } 1673 fep->rx_skbuff[i] = skb; 1674 1675 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, 1676 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1677 bdp->cbd_sc = BD_ENET_RX_EMPTY; 1678 1679 if (fep->bufdesc_ex) { 1680 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1681 ebdp->cbd_esc = BD_ENET_RX_INT; 1682 } 1683 1684 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 1685 } 1686 1687 /* Set the last buffer to wrap. */ 1688 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); 1689 bdp->cbd_sc |= BD_SC_WRAP; 1690 1691 bdp = fep->tx_bd_base; 1692 for (i = 0; i < TX_RING_SIZE; i++) { 1693 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 1694 1695 bdp->cbd_sc = 0; 1696 bdp->cbd_bufaddr = 0; 1697 1698 if (fep->bufdesc_ex) { 1699 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1700 ebdp->cbd_esc = BD_ENET_TX_INT; 1701 } 1702 1703 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); 1704 } 1705 1706 /* Set the last buffer to wrap. */ 1707 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); 1708 bdp->cbd_sc |= BD_SC_WRAP; 1709 1710 return 0; 1711 } 1712 1713 static int 1714 fec_enet_open(struct net_device *ndev) 1715 { 1716 struct fec_enet_private *fep = netdev_priv(ndev); 1717 int ret; 1718 1719 napi_enable(&fep->napi); 1720 1721 /* I should reset the ring buffers here, but I don't yet know 1722 * a simple way to do that. 1723 */ 1724 1725 ret = fec_enet_alloc_buffers(ndev); 1726 if (ret) 1727 return ret; 1728 1729 /* Probe and connect to PHY when open the interface */ 1730 ret = fec_enet_mii_probe(ndev); 1731 if (ret) { 1732 fec_enet_free_buffers(ndev); 1733 return ret; 1734 } 1735 phy_start(fep->phy_dev); 1736 netif_start_queue(ndev); 1737 fep->opened = 1; 1738 return 0; 1739 } 1740 1741 static int 1742 fec_enet_close(struct net_device *ndev) 1743 { 1744 struct fec_enet_private *fep = netdev_priv(ndev); 1745 1746 /* Don't know what to do yet. */ 1747 napi_disable(&fep->napi); 1748 fep->opened = 0; 1749 netif_stop_queue(ndev); 1750 fec_stop(ndev); 1751 1752 if (fep->phy_dev) { 1753 phy_stop(fep->phy_dev); 1754 phy_disconnect(fep->phy_dev); 1755 } 1756 1757 fec_enet_free_buffers(ndev); 1758 1759 return 0; 1760 } 1761 1762 /* Set or clear the multicast filter for this adaptor. 1763 * Skeleton taken from sunlance driver. 1764 * The CPM Ethernet implementation allows Multicast as well as individual 1765 * MAC address filtering. Some of the drivers check to make sure it is 1766 * a group multicast address, and discard those that are not. I guess I 1767 * will do the same for now, but just remove the test if you want 1768 * individual filtering as well (do the upper net layers want or support 1769 * this kind of feature?). 1770 */ 1771 1772 #define HASH_BITS 6 /* #bits in hash */ 1773 #define CRC32_POLY 0xEDB88320 1774 1775 static void set_multicast_list(struct net_device *ndev) 1776 { 1777 struct fec_enet_private *fep = netdev_priv(ndev); 1778 struct netdev_hw_addr *ha; 1779 unsigned int i, bit, data, crc, tmp; 1780 unsigned char hash; 1781 1782 if (ndev->flags & IFF_PROMISC) { 1783 tmp = readl(fep->hwp + FEC_R_CNTRL); 1784 tmp |= 0x8; 1785 writel(tmp, fep->hwp + FEC_R_CNTRL); 1786 return; 1787 } 1788 1789 tmp = readl(fep->hwp + FEC_R_CNTRL); 1790 tmp &= ~0x8; 1791 writel(tmp, fep->hwp + FEC_R_CNTRL); 1792 1793 if (ndev->flags & IFF_ALLMULTI) { 1794 /* Catch all multicast addresses, so set the 1795 * filter to all 1's 1796 */ 1797 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1798 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1799 1800 return; 1801 } 1802 1803 /* Clear filter and add the addresses in hash register 1804 */ 1805 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1806 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1807 1808 netdev_for_each_mc_addr(ha, ndev) { 1809 /* calculate crc32 value of mac address */ 1810 crc = 0xffffffff; 1811 1812 for (i = 0; i < ndev->addr_len; i++) { 1813 data = ha->addr[i]; 1814 for (bit = 0; bit < 8; bit++, data >>= 1) { 1815 crc = (crc >> 1) ^ 1816 (((crc ^ data) & 1) ? CRC32_POLY : 0); 1817 } 1818 } 1819 1820 /* only upper 6 bits (HASH_BITS) are used 1821 * which point to specific bit in he hash registers 1822 */ 1823 hash = (crc >> (32 - HASH_BITS)) & 0x3f; 1824 1825 if (hash > 31) { 1826 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1827 tmp |= 1 << (hash - 32); 1828 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1829 } else { 1830 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1831 tmp |= 1 << hash; 1832 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1833 } 1834 } 1835 } 1836 1837 /* Set a MAC change in hardware. */ 1838 static int 1839 fec_set_mac_address(struct net_device *ndev, void *p) 1840 { 1841 struct fec_enet_private *fep = netdev_priv(ndev); 1842 struct sockaddr *addr = p; 1843 1844 if (!is_valid_ether_addr(addr->sa_data)) 1845 return -EADDRNOTAVAIL; 1846 1847 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 1848 1849 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 1850 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 1851 fep->hwp + FEC_ADDR_LOW); 1852 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 1853 fep->hwp + FEC_ADDR_HIGH); 1854 return 0; 1855 } 1856 1857 #ifdef CONFIG_NET_POLL_CONTROLLER 1858 /** 1859 * fec_poll_controller - FEC Poll controller function 1860 * @dev: The FEC network adapter 1861 * 1862 * Polled functionality used by netconsole and others in non interrupt mode 1863 * 1864 */ 1865 static void fec_poll_controller(struct net_device *dev) 1866 { 1867 int i; 1868 struct fec_enet_private *fep = netdev_priv(dev); 1869 1870 for (i = 0; i < FEC_IRQ_NUM; i++) { 1871 if (fep->irq[i] > 0) { 1872 disable_irq(fep->irq[i]); 1873 fec_enet_interrupt(fep->irq[i], dev); 1874 enable_irq(fep->irq[i]); 1875 } 1876 } 1877 } 1878 #endif 1879 1880 static int fec_set_features(struct net_device *netdev, 1881 netdev_features_t features) 1882 { 1883 struct fec_enet_private *fep = netdev_priv(netdev); 1884 netdev_features_t changed = features ^ netdev->features; 1885 1886 netdev->features = features; 1887 1888 /* Receive checksum has been changed */ 1889 if (changed & NETIF_F_RXCSUM) { 1890 if (features & NETIF_F_RXCSUM) 1891 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 1892 else 1893 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 1894 1895 if (netif_running(netdev)) { 1896 fec_stop(netdev); 1897 fec_restart(netdev, fep->phy_dev->duplex); 1898 netif_wake_queue(netdev); 1899 } else { 1900 fec_restart(netdev, fep->phy_dev->duplex); 1901 } 1902 } 1903 1904 return 0; 1905 } 1906 1907 static const struct net_device_ops fec_netdev_ops = { 1908 .ndo_open = fec_enet_open, 1909 .ndo_stop = fec_enet_close, 1910 .ndo_start_xmit = fec_enet_start_xmit, 1911 .ndo_set_rx_mode = set_multicast_list, 1912 .ndo_change_mtu = eth_change_mtu, 1913 .ndo_validate_addr = eth_validate_addr, 1914 .ndo_tx_timeout = fec_timeout, 1915 .ndo_set_mac_address = fec_set_mac_address, 1916 .ndo_do_ioctl = fec_enet_ioctl, 1917 #ifdef CONFIG_NET_POLL_CONTROLLER 1918 .ndo_poll_controller = fec_poll_controller, 1919 #endif 1920 .ndo_set_features = fec_set_features, 1921 }; 1922 1923 /* 1924 * XXX: We need to clean up on failure exits here. 1925 * 1926 */ 1927 static int fec_enet_init(struct net_device *ndev) 1928 { 1929 struct fec_enet_private *fep = netdev_priv(ndev); 1930 const struct platform_device_id *id_entry = 1931 platform_get_device_id(fep->pdev); 1932 struct bufdesc *cbd_base; 1933 1934 /* Allocate memory for buffer descriptors. */ 1935 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, 1936 GFP_KERNEL); 1937 if (!cbd_base) 1938 return -ENOMEM; 1939 1940 memset(cbd_base, 0, PAGE_SIZE); 1941 1942 fep->netdev = ndev; 1943 1944 /* Get the Ethernet address */ 1945 fec_get_mac(ndev); 1946 1947 /* Set receive and transmit descriptor base. */ 1948 fep->rx_bd_base = cbd_base; 1949 if (fep->bufdesc_ex) 1950 fep->tx_bd_base = (struct bufdesc *) 1951 (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE); 1952 else 1953 fep->tx_bd_base = cbd_base + RX_RING_SIZE; 1954 1955 /* The FEC Ethernet specific entries in the device structure */ 1956 ndev->watchdog_timeo = TX_TIMEOUT; 1957 ndev->netdev_ops = &fec_netdev_ops; 1958 ndev->ethtool_ops = &fec_enet_ethtool_ops; 1959 1960 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 1961 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT); 1962 1963 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) { 1964 /* enable hw VLAN support */ 1965 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 1966 ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 1967 } 1968 1969 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) { 1970 /* enable hw accelerator */ 1971 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 1972 | NETIF_F_RXCSUM); 1973 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 1974 | NETIF_F_RXCSUM); 1975 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 1976 } 1977 1978 fec_restart(ndev, 0); 1979 1980 return 0; 1981 } 1982 1983 #ifdef CONFIG_OF 1984 static void fec_reset_phy(struct platform_device *pdev) 1985 { 1986 int err, phy_reset; 1987 int msec = 1; 1988 struct device_node *np = pdev->dev.of_node; 1989 1990 if (!np) 1991 return; 1992 1993 of_property_read_u32(np, "phy-reset-duration", &msec); 1994 /* A sane reset duration should not be longer than 1s */ 1995 if (msec > 1000) 1996 msec = 1; 1997 1998 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 1999 if (!gpio_is_valid(phy_reset)) 2000 return; 2001 2002 err = devm_gpio_request_one(&pdev->dev, phy_reset, 2003 GPIOF_OUT_INIT_LOW, "phy-reset"); 2004 if (err) { 2005 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 2006 return; 2007 } 2008 msleep(msec); 2009 gpio_set_value(phy_reset, 1); 2010 } 2011 #else /* CONFIG_OF */ 2012 static void fec_reset_phy(struct platform_device *pdev) 2013 { 2014 /* 2015 * In case of platform probe, the reset has been done 2016 * by machine code. 2017 */ 2018 } 2019 #endif /* CONFIG_OF */ 2020 2021 static int 2022 fec_probe(struct platform_device *pdev) 2023 { 2024 struct fec_enet_private *fep; 2025 struct fec_platform_data *pdata; 2026 struct net_device *ndev; 2027 int i, irq, ret = 0; 2028 struct resource *r; 2029 const struct of_device_id *of_id; 2030 static int dev_id; 2031 2032 of_id = of_match_device(fec_dt_ids, &pdev->dev); 2033 if (of_id) 2034 pdev->id_entry = of_id->data; 2035 2036 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2037 if (!r) 2038 return -ENXIO; 2039 2040 /* Init network device */ 2041 ndev = alloc_etherdev(sizeof(struct fec_enet_private)); 2042 if (!ndev) 2043 return -ENOMEM; 2044 2045 SET_NETDEV_DEV(ndev, &pdev->dev); 2046 2047 /* setup board info structure */ 2048 fep = netdev_priv(ndev); 2049 2050 #if !defined(CONFIG_M5272) 2051 /* default enable pause frame auto negotiation */ 2052 if (pdev->id_entry && 2053 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT)) 2054 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 2055 #endif 2056 2057 fep->hwp = devm_ioremap_resource(&pdev->dev, r); 2058 if (IS_ERR(fep->hwp)) { 2059 ret = PTR_ERR(fep->hwp); 2060 goto failed_ioremap; 2061 } 2062 2063 fep->pdev = pdev; 2064 fep->dev_id = dev_id++; 2065 2066 fep->bufdesc_ex = 0; 2067 2068 platform_set_drvdata(pdev, ndev); 2069 2070 ret = of_get_phy_mode(pdev->dev.of_node); 2071 if (ret < 0) { 2072 pdata = pdev->dev.platform_data; 2073 if (pdata) 2074 fep->phy_interface = pdata->phy; 2075 else 2076 fep->phy_interface = PHY_INTERFACE_MODE_MII; 2077 } else { 2078 fep->phy_interface = ret; 2079 } 2080 2081 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2082 if (IS_ERR(fep->clk_ipg)) { 2083 ret = PTR_ERR(fep->clk_ipg); 2084 goto failed_clk; 2085 } 2086 2087 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 2088 if (IS_ERR(fep->clk_ahb)) { 2089 ret = PTR_ERR(fep->clk_ahb); 2090 goto failed_clk; 2091 } 2092 2093 /* enet_out is optional, depends on board */ 2094 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 2095 if (IS_ERR(fep->clk_enet_out)) 2096 fep->clk_enet_out = NULL; 2097 2098 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 2099 fep->bufdesc_ex = 2100 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX; 2101 if (IS_ERR(fep->clk_ptp)) { 2102 fep->clk_ptp = NULL; 2103 fep->bufdesc_ex = 0; 2104 } 2105 2106 clk_prepare_enable(fep->clk_ahb); 2107 clk_prepare_enable(fep->clk_ipg); 2108 clk_prepare_enable(fep->clk_enet_out); 2109 clk_prepare_enable(fep->clk_ptp); 2110 2111 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); 2112 if (!IS_ERR(fep->reg_phy)) { 2113 ret = regulator_enable(fep->reg_phy); 2114 if (ret) { 2115 dev_err(&pdev->dev, 2116 "Failed to enable phy regulator: %d\n", ret); 2117 goto failed_regulator; 2118 } 2119 } else { 2120 fep->reg_phy = NULL; 2121 } 2122 2123 fec_reset_phy(pdev); 2124 2125 if (fep->bufdesc_ex) 2126 fec_ptp_init(pdev); 2127 2128 ret = fec_enet_init(ndev); 2129 if (ret) 2130 goto failed_init; 2131 2132 for (i = 0; i < FEC_IRQ_NUM; i++) { 2133 irq = platform_get_irq(pdev, i); 2134 if (irq < 0) { 2135 if (i) 2136 break; 2137 ret = irq; 2138 goto failed_irq; 2139 } 2140 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); 2141 if (ret) { 2142 while (--i >= 0) { 2143 irq = platform_get_irq(pdev, i); 2144 free_irq(irq, ndev); 2145 } 2146 goto failed_irq; 2147 } 2148 } 2149 2150 ret = fec_enet_mii_init(pdev); 2151 if (ret) 2152 goto failed_mii_init; 2153 2154 /* Carrier starts down, phylib will bring it up */ 2155 netif_carrier_off(ndev); 2156 2157 ret = register_netdev(ndev); 2158 if (ret) 2159 goto failed_register; 2160 2161 if (fep->bufdesc_ex && fep->ptp_clock) 2162 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 2163 2164 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work); 2165 return 0; 2166 2167 failed_register: 2168 fec_enet_mii_remove(fep); 2169 failed_mii_init: 2170 failed_irq: 2171 for (i = 0; i < FEC_IRQ_NUM; i++) { 2172 irq = platform_get_irq(pdev, i); 2173 if (irq > 0) 2174 free_irq(irq, ndev); 2175 } 2176 failed_init: 2177 if (fep->reg_phy) 2178 regulator_disable(fep->reg_phy); 2179 failed_regulator: 2180 clk_disable_unprepare(fep->clk_ahb); 2181 clk_disable_unprepare(fep->clk_ipg); 2182 clk_disable_unprepare(fep->clk_enet_out); 2183 clk_disable_unprepare(fep->clk_ptp); 2184 failed_clk: 2185 failed_ioremap: 2186 free_netdev(ndev); 2187 2188 return ret; 2189 } 2190 2191 static int 2192 fec_drv_remove(struct platform_device *pdev) 2193 { 2194 struct net_device *ndev = platform_get_drvdata(pdev); 2195 struct fec_enet_private *fep = netdev_priv(ndev); 2196 int i; 2197 2198 cancel_delayed_work_sync(&(fep->delay_work.delay_work)); 2199 unregister_netdev(ndev); 2200 fec_enet_mii_remove(fep); 2201 del_timer_sync(&fep->time_keep); 2202 for (i = 0; i < FEC_IRQ_NUM; i++) { 2203 int irq = platform_get_irq(pdev, i); 2204 if (irq > 0) 2205 free_irq(irq, ndev); 2206 } 2207 if (fep->reg_phy) 2208 regulator_disable(fep->reg_phy); 2209 clk_disable_unprepare(fep->clk_ptp); 2210 if (fep->ptp_clock) 2211 ptp_clock_unregister(fep->ptp_clock); 2212 clk_disable_unprepare(fep->clk_enet_out); 2213 clk_disable_unprepare(fep->clk_ahb); 2214 clk_disable_unprepare(fep->clk_ipg); 2215 free_netdev(ndev); 2216 2217 return 0; 2218 } 2219 2220 #ifdef CONFIG_PM_SLEEP 2221 static int 2222 fec_suspend(struct device *dev) 2223 { 2224 struct net_device *ndev = dev_get_drvdata(dev); 2225 struct fec_enet_private *fep = netdev_priv(ndev); 2226 2227 if (netif_running(ndev)) { 2228 fec_stop(ndev); 2229 netif_device_detach(ndev); 2230 } 2231 clk_disable_unprepare(fep->clk_enet_out); 2232 clk_disable_unprepare(fep->clk_ahb); 2233 clk_disable_unprepare(fep->clk_ipg); 2234 2235 if (fep->reg_phy) 2236 regulator_disable(fep->reg_phy); 2237 2238 return 0; 2239 } 2240 2241 static int 2242 fec_resume(struct device *dev) 2243 { 2244 struct net_device *ndev = dev_get_drvdata(dev); 2245 struct fec_enet_private *fep = netdev_priv(ndev); 2246 int ret; 2247 2248 if (fep->reg_phy) { 2249 ret = regulator_enable(fep->reg_phy); 2250 if (ret) 2251 return ret; 2252 } 2253 2254 clk_prepare_enable(fep->clk_enet_out); 2255 clk_prepare_enable(fep->clk_ahb); 2256 clk_prepare_enable(fep->clk_ipg); 2257 if (netif_running(ndev)) { 2258 fec_restart(ndev, fep->full_duplex); 2259 netif_device_attach(ndev); 2260 } 2261 2262 return 0; 2263 } 2264 #endif /* CONFIG_PM_SLEEP */ 2265 2266 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume); 2267 2268 static struct platform_driver fec_driver = { 2269 .driver = { 2270 .name = DRIVER_NAME, 2271 .owner = THIS_MODULE, 2272 .pm = &fec_pm_ops, 2273 .of_match_table = fec_dt_ids, 2274 }, 2275 .id_table = fec_devtype, 2276 .probe = fec_probe, 2277 .remove = fec_drv_remove, 2278 }; 2279 2280 module_platform_driver(fec_driver); 2281 2282 MODULE_LICENSE("GPL"); 2283