1 /* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 * 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/string.h> 27 #include <linux/ptrace.h> 28 #include <linux/errno.h> 29 #include <linux/ioport.h> 30 #include <linux/slab.h> 31 #include <linux/interrupt.h> 32 #include <linux/init.h> 33 #include <linux/delay.h> 34 #include <linux/netdevice.h> 35 #include <linux/etherdevice.h> 36 #include <linux/skbuff.h> 37 #include <linux/in.h> 38 #include <linux/ip.h> 39 #include <net/ip.h> 40 #include <linux/tcp.h> 41 #include <linux/udp.h> 42 #include <linux/icmp.h> 43 #include <linux/spinlock.h> 44 #include <linux/workqueue.h> 45 #include <linux/bitops.h> 46 #include <linux/io.h> 47 #include <linux/irq.h> 48 #include <linux/clk.h> 49 #include <linux/platform_device.h> 50 #include <linux/phy.h> 51 #include <linux/fec.h> 52 #include <linux/of.h> 53 #include <linux/of_device.h> 54 #include <linux/of_gpio.h> 55 #include <linux/of_net.h> 56 #include <linux/regulator/consumer.h> 57 #include <linux/if_vlan.h> 58 59 #include <asm/cacheflush.h> 60 61 #include "fec.h" 62 63 static void set_multicast_list(struct net_device *ndev); 64 65 #if defined(CONFIG_ARM) 66 #define FEC_ALIGNMENT 0xf 67 #else 68 #define FEC_ALIGNMENT 0x3 69 #endif 70 71 #define DRIVER_NAME "fec" 72 73 /* Pause frame feild and FIFO threshold */ 74 #define FEC_ENET_FCE (1 << 5) 75 #define FEC_ENET_RSEM_V 0x84 76 #define FEC_ENET_RSFL_V 16 77 #define FEC_ENET_RAEM_V 0x8 78 #define FEC_ENET_RAFL_V 0x8 79 #define FEC_ENET_OPD_V 0xFFF0 80 81 /* Controller is ENET-MAC */ 82 #define FEC_QUIRK_ENET_MAC (1 << 0) 83 /* Controller needs driver to swap frame */ 84 #define FEC_QUIRK_SWAP_FRAME (1 << 1) 85 /* Controller uses gasket */ 86 #define FEC_QUIRK_USE_GASKET (1 << 2) 87 /* Controller has GBIT support */ 88 #define FEC_QUIRK_HAS_GBIT (1 << 3) 89 /* Controller has extend desc buffer */ 90 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) 91 /* Controller has hardware checksum support */ 92 #define FEC_QUIRK_HAS_CSUM (1 << 5) 93 /* Controller has hardware vlan support */ 94 #define FEC_QUIRK_HAS_VLAN (1 << 6) 95 /* ENET IP errata ERR006358 96 * 97 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously 98 * detected as not set during a prior frame transmission, then the 99 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs 100 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in 101 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously 102 * detected as not set during a prior frame transmission, then the 103 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs 104 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in 105 * frames not being transmitted until there is a 0-to-1 transition on 106 * ENET_TDAR[TDAR]. 107 */ 108 #define FEC_QUIRK_ERR006358 (1 << 7) 109 110 static struct platform_device_id fec_devtype[] = { 111 { 112 /* keep it for coldfire */ 113 .name = DRIVER_NAME, 114 .driver_data = 0, 115 }, { 116 .name = "imx25-fec", 117 .driver_data = FEC_QUIRK_USE_GASKET, 118 }, { 119 .name = "imx27-fec", 120 .driver_data = 0, 121 }, { 122 .name = "imx28-fec", 123 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, 124 }, { 125 .name = "imx6q-fec", 126 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 127 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 128 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358, 129 }, { 130 .name = "mvf600-fec", 131 .driver_data = FEC_QUIRK_ENET_MAC, 132 }, { 133 /* sentinel */ 134 } 135 }; 136 MODULE_DEVICE_TABLE(platform, fec_devtype); 137 138 enum imx_fec_type { 139 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 140 IMX27_FEC, /* runs on i.mx27/35/51 */ 141 IMX28_FEC, 142 IMX6Q_FEC, 143 MVF600_FEC, 144 }; 145 146 static const struct of_device_id fec_dt_ids[] = { 147 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 148 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 149 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 150 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 151 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 152 { /* sentinel */ } 153 }; 154 MODULE_DEVICE_TABLE(of, fec_dt_ids); 155 156 static unsigned char macaddr[ETH_ALEN]; 157 module_param_array(macaddr, byte, NULL, 0); 158 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 159 160 #if defined(CONFIG_M5272) 161 /* 162 * Some hardware gets it MAC address out of local flash memory. 163 * if this is non-zero then assume it is the address to get MAC from. 164 */ 165 #if defined(CONFIG_NETtel) 166 #define FEC_FLASHMAC 0xf0006006 167 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 168 #define FEC_FLASHMAC 0xf0006000 169 #elif defined(CONFIG_CANCam) 170 #define FEC_FLASHMAC 0xf0020000 171 #elif defined (CONFIG_M5272C3) 172 #define FEC_FLASHMAC (0xffe04000 + 4) 173 #elif defined(CONFIG_MOD5272) 174 #define FEC_FLASHMAC 0xffc0406b 175 #else 176 #define FEC_FLASHMAC 0 177 #endif 178 #endif /* CONFIG_M5272 */ 179 180 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE) 181 #error "FEC: descriptor ring size constants too large" 182 #endif 183 184 /* Interrupt events/masks. */ 185 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ 186 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ 187 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ 188 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ 189 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ 190 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ 191 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ 192 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ 193 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ 194 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ 195 196 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) 197 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) 198 199 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 200 */ 201 #define PKT_MAXBUF_SIZE 1522 202 #define PKT_MINBUF_SIZE 64 203 #define PKT_MAXBLR_SIZE 1536 204 205 /* FEC receive acceleration */ 206 #define FEC_RACC_IPDIS (1 << 1) 207 #define FEC_RACC_PRODIS (1 << 2) 208 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 209 210 /* 211 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 212 * size bits. Other FEC hardware does not, so we need to take that into 213 * account when setting it. 214 */ 215 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 216 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 217 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 218 #else 219 #define OPT_FRAME_SIZE 0 220 #endif 221 222 /* FEC MII MMFR bits definition */ 223 #define FEC_MMFR_ST (1 << 30) 224 #define FEC_MMFR_OP_READ (2 << 28) 225 #define FEC_MMFR_OP_WRITE (1 << 28) 226 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 227 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 228 #define FEC_MMFR_TA (2 << 16) 229 #define FEC_MMFR_DATA(v) (v & 0xffff) 230 231 #define FEC_MII_TIMEOUT 30000 /* us */ 232 233 /* Transmitter timeout */ 234 #define TX_TIMEOUT (2 * HZ) 235 236 #define FEC_PAUSE_FLAG_AUTONEG 0x1 237 #define FEC_PAUSE_FLAG_ENABLE 0x2 238 239 static int mii_cnt; 240 241 static inline 242 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep) 243 { 244 struct bufdesc *new_bd = bdp + 1; 245 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1; 246 struct bufdesc_ex *ex_base; 247 struct bufdesc *base; 248 int ring_size; 249 250 if (bdp >= fep->tx_bd_base) { 251 base = fep->tx_bd_base; 252 ring_size = fep->tx_ring_size; 253 ex_base = (struct bufdesc_ex *)fep->tx_bd_base; 254 } else { 255 base = fep->rx_bd_base; 256 ring_size = fep->rx_ring_size; 257 ex_base = (struct bufdesc_ex *)fep->rx_bd_base; 258 } 259 260 if (fep->bufdesc_ex) 261 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ? 262 ex_base : ex_new_bd); 263 else 264 return (new_bd >= (base + ring_size)) ? 265 base : new_bd; 266 } 267 268 static inline 269 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep) 270 { 271 struct bufdesc *new_bd = bdp - 1; 272 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1; 273 struct bufdesc_ex *ex_base; 274 struct bufdesc *base; 275 int ring_size; 276 277 if (bdp >= fep->tx_bd_base) { 278 base = fep->tx_bd_base; 279 ring_size = fep->tx_ring_size; 280 ex_base = (struct bufdesc_ex *)fep->tx_bd_base; 281 } else { 282 base = fep->rx_bd_base; 283 ring_size = fep->rx_ring_size; 284 ex_base = (struct bufdesc_ex *)fep->rx_bd_base; 285 } 286 287 if (fep->bufdesc_ex) 288 return (struct bufdesc *)((ex_new_bd < ex_base) ? 289 (ex_new_bd + ring_size) : ex_new_bd); 290 else 291 return (new_bd < base) ? (new_bd + ring_size) : new_bd; 292 } 293 294 static void *swap_buffer(void *bufaddr, int len) 295 { 296 int i; 297 unsigned int *buf = bufaddr; 298 299 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++) 300 *buf = cpu_to_be32(*buf); 301 302 return bufaddr; 303 } 304 305 static int 306 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 307 { 308 /* Only run for packets requiring a checksum. */ 309 if (skb->ip_summed != CHECKSUM_PARTIAL) 310 return 0; 311 312 if (unlikely(skb_cow_head(skb, 0))) 313 return -1; 314 315 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 316 317 return 0; 318 } 319 320 static netdev_tx_t 321 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 322 { 323 struct fec_enet_private *fep = netdev_priv(ndev); 324 const struct platform_device_id *id_entry = 325 platform_get_device_id(fep->pdev); 326 struct bufdesc *bdp, *bdp_pre; 327 void *bufaddr; 328 unsigned short status; 329 unsigned int index; 330 331 /* Fill in a Tx ring entry */ 332 bdp = fep->cur_tx; 333 334 status = bdp->cbd_sc; 335 336 if (status & BD_ENET_TX_READY) { 337 /* Ooops. All transmit buffers are full. Bail out. 338 * This should not happen, since ndev->tbusy should be set. 339 */ 340 netdev_err(ndev, "tx queue full!\n"); 341 return NETDEV_TX_BUSY; 342 } 343 344 /* Protocol checksum off-load for TCP and UDP. */ 345 if (fec_enet_clear_csum(skb, ndev)) { 346 kfree_skb(skb); 347 return NETDEV_TX_OK; 348 } 349 350 /* Clear all of the status flags */ 351 status &= ~BD_ENET_TX_STATS; 352 353 /* Set buffer length and buffer pointer */ 354 bufaddr = skb->data; 355 bdp->cbd_datlen = skb->len; 356 357 /* 358 * On some FEC implementations data must be aligned on 359 * 4-byte boundaries. Use bounce buffers to copy data 360 * and get it aligned. Ugh. 361 */ 362 if (fep->bufdesc_ex) 363 index = (struct bufdesc_ex *)bdp - 364 (struct bufdesc_ex *)fep->tx_bd_base; 365 else 366 index = bdp - fep->tx_bd_base; 367 368 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { 369 memcpy(fep->tx_bounce[index], skb->data, skb->len); 370 bufaddr = fep->tx_bounce[index]; 371 } 372 373 /* 374 * Some design made an incorrect assumption on endian mode of 375 * the system that it's running on. As the result, driver has to 376 * swap every frame going to and coming from the controller. 377 */ 378 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 379 swap_buffer(bufaddr, skb->len); 380 381 /* Save skb pointer */ 382 fep->tx_skbuff[index] = skb; 383 384 /* Push the data cache so the CPM does not get stale memory 385 * data. 386 */ 387 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, 388 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); 389 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) { 390 bdp->cbd_bufaddr = 0; 391 fep->tx_skbuff[index] = NULL; 392 dev_kfree_skb_any(skb); 393 if (net_ratelimit()) 394 netdev_err(ndev, "Tx DMA memory map failed\n"); 395 return NETDEV_TX_OK; 396 } 397 /* Send it on its way. Tell FEC it's ready, interrupt when done, 398 * it's the last BD of the frame, and to put the CRC on the end. 399 */ 400 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR 401 | BD_ENET_TX_LAST | BD_ENET_TX_TC); 402 bdp->cbd_sc = status; 403 404 if (fep->bufdesc_ex) { 405 406 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 407 ebdp->cbd_bdu = 0; 408 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 409 fep->hwts_tx_en)) { 410 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT); 411 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 412 } else { 413 ebdp->cbd_esc = BD_ENET_TX_INT; 414 415 /* Enable protocol checksum flags 416 * We do not bother with the IP Checksum bits as they 417 * are done by the kernel 418 */ 419 if (skb->ip_summed == CHECKSUM_PARTIAL) 420 ebdp->cbd_esc |= BD_ENET_TX_PINS; 421 } 422 } 423 424 bdp_pre = fec_enet_get_prevdesc(bdp, fep); 425 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) && 426 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) { 427 fep->delay_work.trig_tx = true; 428 schedule_delayed_work(&(fep->delay_work.delay_work), 429 msecs_to_jiffies(1)); 430 } 431 432 /* If this was the last BD in the ring, start at the beginning again. */ 433 bdp = fec_enet_get_nextdesc(bdp, fep); 434 435 fep->cur_tx = bdp; 436 437 if (fep->cur_tx == fep->dirty_tx) 438 netif_stop_queue(ndev); 439 440 /* Trigger transmission start */ 441 writel(0, fep->hwp + FEC_X_DES_ACTIVE); 442 443 skb_tx_timestamp(skb); 444 445 return NETDEV_TX_OK; 446 } 447 448 /* Init RX & TX buffer descriptors 449 */ 450 static void fec_enet_bd_init(struct net_device *dev) 451 { 452 struct fec_enet_private *fep = netdev_priv(dev); 453 struct bufdesc *bdp; 454 unsigned int i; 455 456 /* Initialize the receive buffer descriptors. */ 457 bdp = fep->rx_bd_base; 458 for (i = 0; i < fep->rx_ring_size; i++) { 459 460 /* Initialize the BD for every fragment in the page. */ 461 if (bdp->cbd_bufaddr) 462 bdp->cbd_sc = BD_ENET_RX_EMPTY; 463 else 464 bdp->cbd_sc = 0; 465 bdp = fec_enet_get_nextdesc(bdp, fep); 466 } 467 468 /* Set the last buffer to wrap */ 469 bdp = fec_enet_get_prevdesc(bdp, fep); 470 bdp->cbd_sc |= BD_SC_WRAP; 471 472 fep->cur_rx = fep->rx_bd_base; 473 474 /* ...and the same for transmit */ 475 bdp = fep->tx_bd_base; 476 fep->cur_tx = bdp; 477 for (i = 0; i < fep->tx_ring_size; i++) { 478 479 /* Initialize the BD for every fragment in the page. */ 480 bdp->cbd_sc = 0; 481 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) { 482 dev_kfree_skb_any(fep->tx_skbuff[i]); 483 fep->tx_skbuff[i] = NULL; 484 } 485 bdp->cbd_bufaddr = 0; 486 bdp = fec_enet_get_nextdesc(bdp, fep); 487 } 488 489 /* Set the last buffer to wrap */ 490 bdp = fec_enet_get_prevdesc(bdp, fep); 491 bdp->cbd_sc |= BD_SC_WRAP; 492 fep->dirty_tx = bdp; 493 } 494 495 /* This function is called to start or restart the FEC during a link 496 * change. This only happens when switching between half and full 497 * duplex. 498 */ 499 static void 500 fec_restart(struct net_device *ndev, int duplex) 501 { 502 struct fec_enet_private *fep = netdev_priv(ndev); 503 const struct platform_device_id *id_entry = 504 platform_get_device_id(fep->pdev); 505 int i; 506 u32 val; 507 u32 temp_mac[2]; 508 u32 rcntl = OPT_FRAME_SIZE | 0x04; 509 u32 ecntl = 0x2; /* ETHEREN */ 510 511 if (netif_running(ndev)) { 512 netif_device_detach(ndev); 513 napi_disable(&fep->napi); 514 netif_stop_queue(ndev); 515 netif_tx_lock_bh(ndev); 516 } 517 518 /* Whack a reset. We should wait for this. */ 519 writel(1, fep->hwp + FEC_ECNTRL); 520 udelay(10); 521 522 /* 523 * enet-mac reset will reset mac address registers too, 524 * so need to reconfigure it. 525 */ 526 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 527 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 528 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); 529 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); 530 } 531 532 /* Clear any outstanding interrupt. */ 533 writel(0xffc00000, fep->hwp + FEC_IEVENT); 534 535 /* Setup multicast filter. */ 536 set_multicast_list(ndev); 537 #ifndef CONFIG_M5272 538 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 539 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 540 #endif 541 542 /* Set maximum receive buffer size. */ 543 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); 544 545 fec_enet_bd_init(ndev); 546 547 /* Set receive and transmit descriptor base. */ 548 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); 549 if (fep->bufdesc_ex) 550 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex) 551 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START); 552 else 553 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) 554 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START); 555 556 557 for (i = 0; i <= TX_RING_MOD_MASK; i++) { 558 if (fep->tx_skbuff[i]) { 559 dev_kfree_skb_any(fep->tx_skbuff[i]); 560 fep->tx_skbuff[i] = NULL; 561 } 562 } 563 564 /* Enable MII mode */ 565 if (duplex) { 566 /* FD enable */ 567 writel(0x04, fep->hwp + FEC_X_CNTRL); 568 } else { 569 /* No Rcv on Xmit */ 570 rcntl |= 0x02; 571 writel(0x0, fep->hwp + FEC_X_CNTRL); 572 } 573 574 fep->full_duplex = duplex; 575 576 /* Set MII speed */ 577 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 578 579 #if !defined(CONFIG_M5272) 580 /* set RX checksum */ 581 val = readl(fep->hwp + FEC_RACC); 582 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 583 val |= FEC_RACC_OPTIONS; 584 else 585 val &= ~FEC_RACC_OPTIONS; 586 writel(val, fep->hwp + FEC_RACC); 587 #endif 588 589 /* 590 * The phy interface and speed need to get configured 591 * differently on enet-mac. 592 */ 593 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 594 /* Enable flow control and length check */ 595 rcntl |= 0x40000000 | 0x00000020; 596 597 /* RGMII, RMII or MII */ 598 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) 599 rcntl |= (1 << 6); 600 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 601 rcntl |= (1 << 8); 602 else 603 rcntl &= ~(1 << 8); 604 605 /* 1G, 100M or 10M */ 606 if (fep->phy_dev) { 607 if (fep->phy_dev->speed == SPEED_1000) 608 ecntl |= (1 << 5); 609 else if (fep->phy_dev->speed == SPEED_100) 610 rcntl &= ~(1 << 9); 611 else 612 rcntl |= (1 << 9); 613 } 614 } else { 615 #ifdef FEC_MIIGSK_ENR 616 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { 617 u32 cfgr; 618 /* disable the gasket and wait */ 619 writel(0, fep->hwp + FEC_MIIGSK_ENR); 620 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 621 udelay(1); 622 623 /* 624 * configure the gasket: 625 * RMII, 50 MHz, no loopback, no echo 626 * MII, 25 MHz, no loopback, no echo 627 */ 628 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 629 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 630 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) 631 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 632 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 633 634 /* re-enable the gasket */ 635 writel(2, fep->hwp + FEC_MIIGSK_ENR); 636 } 637 #endif 638 } 639 640 #if !defined(CONFIG_M5272) 641 /* enable pause frame*/ 642 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 643 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 644 fep->phy_dev && fep->phy_dev->pause)) { 645 rcntl |= FEC_ENET_FCE; 646 647 /* set FIFO threshold parameter to reduce overrun */ 648 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 649 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 650 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 651 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 652 653 /* OPD */ 654 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 655 } else { 656 rcntl &= ~FEC_ENET_FCE; 657 } 658 #endif /* !defined(CONFIG_M5272) */ 659 660 writel(rcntl, fep->hwp + FEC_R_CNTRL); 661 662 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 663 /* enable ENET endian swap */ 664 ecntl |= (1 << 8); 665 /* enable ENET store and forward mode */ 666 writel(1 << 8, fep->hwp + FEC_X_WMRK); 667 } 668 669 if (fep->bufdesc_ex) 670 ecntl |= (1 << 4); 671 672 #ifndef CONFIG_M5272 673 /* Enable the MIB statistic event counters */ 674 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 675 #endif 676 677 /* And last, enable the transmit and receive processing */ 678 writel(ecntl, fep->hwp + FEC_ECNTRL); 679 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 680 681 if (fep->bufdesc_ex) 682 fec_ptp_start_cyclecounter(ndev); 683 684 /* Enable interrupts we wish to service */ 685 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 686 687 if (netif_running(ndev)) { 688 netif_tx_unlock_bh(ndev); 689 netif_wake_queue(ndev); 690 napi_enable(&fep->napi); 691 netif_device_attach(ndev); 692 } 693 } 694 695 static void 696 fec_stop(struct net_device *ndev) 697 { 698 struct fec_enet_private *fep = netdev_priv(ndev); 699 const struct platform_device_id *id_entry = 700 platform_get_device_id(fep->pdev); 701 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 702 703 /* We cannot expect a graceful transmit stop without link !!! */ 704 if (fep->link) { 705 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 706 udelay(10); 707 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 708 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 709 } 710 711 /* Whack a reset. We should wait for this. */ 712 writel(1, fep->hwp + FEC_ECNTRL); 713 udelay(10); 714 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 715 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 716 717 /* We have to keep ENET enabled to have MII interrupt stay working */ 718 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 719 writel(2, fep->hwp + FEC_ECNTRL); 720 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 721 } 722 } 723 724 725 static void 726 fec_timeout(struct net_device *ndev) 727 { 728 struct fec_enet_private *fep = netdev_priv(ndev); 729 730 ndev->stats.tx_errors++; 731 732 fep->delay_work.timeout = true; 733 schedule_delayed_work(&(fep->delay_work.delay_work), 0); 734 } 735 736 static void fec_enet_work(struct work_struct *work) 737 { 738 struct fec_enet_private *fep = 739 container_of(work, 740 struct fec_enet_private, 741 delay_work.delay_work.work); 742 743 if (fep->delay_work.timeout) { 744 fep->delay_work.timeout = false; 745 fec_restart(fep->netdev, fep->full_duplex); 746 netif_wake_queue(fep->netdev); 747 } 748 749 if (fep->delay_work.trig_tx) { 750 fep->delay_work.trig_tx = false; 751 writel(0, fep->hwp + FEC_X_DES_ACTIVE); 752 } 753 } 754 755 static void 756 fec_enet_tx(struct net_device *ndev) 757 { 758 struct fec_enet_private *fep; 759 struct bufdesc *bdp; 760 unsigned short status; 761 struct sk_buff *skb; 762 int index = 0; 763 764 fep = netdev_priv(ndev); 765 bdp = fep->dirty_tx; 766 767 /* get next bdp of dirty_tx */ 768 bdp = fec_enet_get_nextdesc(bdp, fep); 769 770 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { 771 772 /* current queue is empty */ 773 if (bdp == fep->cur_tx) 774 break; 775 776 if (fep->bufdesc_ex) 777 index = (struct bufdesc_ex *)bdp - 778 (struct bufdesc_ex *)fep->tx_bd_base; 779 else 780 index = bdp - fep->tx_bd_base; 781 782 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 783 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); 784 bdp->cbd_bufaddr = 0; 785 786 skb = fep->tx_skbuff[index]; 787 788 /* Check for errors. */ 789 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 790 BD_ENET_TX_RL | BD_ENET_TX_UN | 791 BD_ENET_TX_CSL)) { 792 ndev->stats.tx_errors++; 793 if (status & BD_ENET_TX_HB) /* No heartbeat */ 794 ndev->stats.tx_heartbeat_errors++; 795 if (status & BD_ENET_TX_LC) /* Late collision */ 796 ndev->stats.tx_window_errors++; 797 if (status & BD_ENET_TX_RL) /* Retrans limit */ 798 ndev->stats.tx_aborted_errors++; 799 if (status & BD_ENET_TX_UN) /* Underrun */ 800 ndev->stats.tx_fifo_errors++; 801 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 802 ndev->stats.tx_carrier_errors++; 803 } else { 804 ndev->stats.tx_packets++; 805 ndev->stats.tx_bytes += bdp->cbd_datlen; 806 } 807 808 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 809 fep->bufdesc_ex) { 810 struct skb_shared_hwtstamps shhwtstamps; 811 unsigned long flags; 812 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 813 814 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 815 spin_lock_irqsave(&fep->tmreg_lock, flags); 816 shhwtstamps.hwtstamp = ns_to_ktime( 817 timecounter_cyc2time(&fep->tc, ebdp->ts)); 818 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 819 skb_tstamp_tx(skb, &shhwtstamps); 820 } 821 822 if (status & BD_ENET_TX_READY) 823 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n"); 824 825 /* Deferred means some collisions occurred during transmit, 826 * but we eventually sent the packet OK. 827 */ 828 if (status & BD_ENET_TX_DEF) 829 ndev->stats.collisions++; 830 831 /* Free the sk buffer associated with this last transmit */ 832 dev_kfree_skb_any(skb); 833 fep->tx_skbuff[index] = NULL; 834 835 fep->dirty_tx = bdp; 836 837 /* Update pointer to next buffer descriptor to be transmitted */ 838 bdp = fec_enet_get_nextdesc(bdp, fep); 839 840 /* Since we have freed up a buffer, the ring is no longer full 841 */ 842 if (fep->dirty_tx != fep->cur_tx) { 843 if (netif_queue_stopped(ndev)) 844 netif_wake_queue(ndev); 845 } 846 } 847 return; 848 } 849 850 851 /* During a receive, the cur_rx points to the current incoming buffer. 852 * When we update through the ring, if the next incoming buffer has 853 * not been given to the system, we just set the empty indicator, 854 * effectively tossing the packet. 855 */ 856 static int 857 fec_enet_rx(struct net_device *ndev, int budget) 858 { 859 struct fec_enet_private *fep = netdev_priv(ndev); 860 const struct platform_device_id *id_entry = 861 platform_get_device_id(fep->pdev); 862 struct bufdesc *bdp; 863 unsigned short status; 864 struct sk_buff *skb; 865 ushort pkt_len; 866 __u8 *data; 867 int pkt_received = 0; 868 struct bufdesc_ex *ebdp = NULL; 869 bool vlan_packet_rcvd = false; 870 u16 vlan_tag; 871 int index = 0; 872 873 #ifdef CONFIG_M532x 874 flush_cache_all(); 875 #endif 876 877 /* First, grab all of the stats for the incoming packet. 878 * These get messed up if we get called due to a busy condition. 879 */ 880 bdp = fep->cur_rx; 881 882 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { 883 884 if (pkt_received >= budget) 885 break; 886 pkt_received++; 887 888 /* Since we have allocated space to hold a complete frame, 889 * the last indicator should be set. 890 */ 891 if ((status & BD_ENET_RX_LAST) == 0) 892 netdev_err(ndev, "rcv is not +last\n"); 893 894 if (!fep->opened) 895 goto rx_processing_done; 896 897 /* Check for errors. */ 898 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 899 BD_ENET_RX_CR | BD_ENET_RX_OV)) { 900 ndev->stats.rx_errors++; 901 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { 902 /* Frame too long or too short. */ 903 ndev->stats.rx_length_errors++; 904 } 905 if (status & BD_ENET_RX_NO) /* Frame alignment */ 906 ndev->stats.rx_frame_errors++; 907 if (status & BD_ENET_RX_CR) /* CRC Error */ 908 ndev->stats.rx_crc_errors++; 909 if (status & BD_ENET_RX_OV) /* FIFO overrun */ 910 ndev->stats.rx_fifo_errors++; 911 } 912 913 /* Report late collisions as a frame error. 914 * On this error, the BD is closed, but we don't know what we 915 * have in the buffer. So, just drop this frame on the floor. 916 */ 917 if (status & BD_ENET_RX_CL) { 918 ndev->stats.rx_errors++; 919 ndev->stats.rx_frame_errors++; 920 goto rx_processing_done; 921 } 922 923 /* Process the incoming frame. */ 924 ndev->stats.rx_packets++; 925 pkt_len = bdp->cbd_datlen; 926 ndev->stats.rx_bytes += pkt_len; 927 928 if (fep->bufdesc_ex) 929 index = (struct bufdesc_ex *)bdp - 930 (struct bufdesc_ex *)fep->rx_bd_base; 931 else 932 index = bdp - fep->rx_bd_base; 933 data = fep->rx_skbuff[index]->data; 934 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr, 935 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 936 937 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 938 swap_buffer(data, pkt_len); 939 940 /* Extract the enhanced buffer descriptor */ 941 ebdp = NULL; 942 if (fep->bufdesc_ex) 943 ebdp = (struct bufdesc_ex *)bdp; 944 945 /* If this is a VLAN packet remove the VLAN Tag */ 946 vlan_packet_rcvd = false; 947 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 948 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) { 949 /* Push and remove the vlan tag */ 950 struct vlan_hdr *vlan_header = 951 (struct vlan_hdr *) (data + ETH_HLEN); 952 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 953 pkt_len -= VLAN_HLEN; 954 955 vlan_packet_rcvd = true; 956 } 957 958 /* This does 16 byte alignment, exactly what we need. 959 * The packet length includes FCS, but we don't want to 960 * include that when passing upstream as it messes up 961 * bridging applications. 962 */ 963 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); 964 965 if (unlikely(!skb)) { 966 ndev->stats.rx_dropped++; 967 } else { 968 int payload_offset = (2 * ETH_ALEN); 969 skb_reserve(skb, NET_IP_ALIGN); 970 skb_put(skb, pkt_len - 4); /* Make room */ 971 972 /* Extract the frame data without the VLAN header. */ 973 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN)); 974 if (vlan_packet_rcvd) 975 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN; 976 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN), 977 data + payload_offset, 978 pkt_len - 4 - (2 * ETH_ALEN)); 979 980 skb->protocol = eth_type_trans(skb, ndev); 981 982 /* Get receive timestamp from the skb */ 983 if (fep->hwts_rx_en && fep->bufdesc_ex) { 984 struct skb_shared_hwtstamps *shhwtstamps = 985 skb_hwtstamps(skb); 986 unsigned long flags; 987 988 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 989 990 spin_lock_irqsave(&fep->tmreg_lock, flags); 991 shhwtstamps->hwtstamp = ns_to_ktime( 992 timecounter_cyc2time(&fep->tc, ebdp->ts)); 993 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 994 } 995 996 if (fep->bufdesc_ex && 997 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 998 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) { 999 /* don't check it */ 1000 skb->ip_summed = CHECKSUM_UNNECESSARY; 1001 } else { 1002 skb_checksum_none_assert(skb); 1003 } 1004 } 1005 1006 /* Handle received VLAN packets */ 1007 if (vlan_packet_rcvd) 1008 __vlan_hwaccel_put_tag(skb, 1009 htons(ETH_P_8021Q), 1010 vlan_tag); 1011 1012 napi_gro_receive(&fep->napi, skb); 1013 } 1014 1015 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr, 1016 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1017 rx_processing_done: 1018 /* Clear the status flags for this buffer */ 1019 status &= ~BD_ENET_RX_STATS; 1020 1021 /* Mark the buffer empty */ 1022 status |= BD_ENET_RX_EMPTY; 1023 bdp->cbd_sc = status; 1024 1025 if (fep->bufdesc_ex) { 1026 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1027 1028 ebdp->cbd_esc = BD_ENET_RX_INT; 1029 ebdp->cbd_prot = 0; 1030 ebdp->cbd_bdu = 0; 1031 } 1032 1033 /* Update BD pointer to next entry */ 1034 bdp = fec_enet_get_nextdesc(bdp, fep); 1035 1036 /* Doing this here will keep the FEC running while we process 1037 * incoming frames. On a heavily loaded network, we should be 1038 * able to keep up at the expense of system resources. 1039 */ 1040 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 1041 } 1042 fep->cur_rx = bdp; 1043 1044 return pkt_received; 1045 } 1046 1047 static irqreturn_t 1048 fec_enet_interrupt(int irq, void *dev_id) 1049 { 1050 struct net_device *ndev = dev_id; 1051 struct fec_enet_private *fep = netdev_priv(ndev); 1052 uint int_events; 1053 irqreturn_t ret = IRQ_NONE; 1054 1055 do { 1056 int_events = readl(fep->hwp + FEC_IEVENT); 1057 writel(int_events, fep->hwp + FEC_IEVENT); 1058 1059 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) { 1060 ret = IRQ_HANDLED; 1061 1062 /* Disable the RX interrupt */ 1063 if (napi_schedule_prep(&fep->napi)) { 1064 writel(FEC_RX_DISABLED_IMASK, 1065 fep->hwp + FEC_IMASK); 1066 __napi_schedule(&fep->napi); 1067 } 1068 } 1069 1070 if (int_events & FEC_ENET_MII) { 1071 ret = IRQ_HANDLED; 1072 complete(&fep->mdio_done); 1073 } 1074 } while (int_events); 1075 1076 return ret; 1077 } 1078 1079 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1080 { 1081 struct net_device *ndev = napi->dev; 1082 int pkts = fec_enet_rx(ndev, budget); 1083 struct fec_enet_private *fep = netdev_priv(ndev); 1084 1085 fec_enet_tx(ndev); 1086 1087 if (pkts < budget) { 1088 napi_complete(napi); 1089 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1090 } 1091 return pkts; 1092 } 1093 1094 /* ------------------------------------------------------------------------- */ 1095 static void fec_get_mac(struct net_device *ndev) 1096 { 1097 struct fec_enet_private *fep = netdev_priv(ndev); 1098 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1099 unsigned char *iap, tmpaddr[ETH_ALEN]; 1100 1101 /* 1102 * try to get mac address in following order: 1103 * 1104 * 1) module parameter via kernel command line in form 1105 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1106 */ 1107 iap = macaddr; 1108 1109 /* 1110 * 2) from device tree data 1111 */ 1112 if (!is_valid_ether_addr(iap)) { 1113 struct device_node *np = fep->pdev->dev.of_node; 1114 if (np) { 1115 const char *mac = of_get_mac_address(np); 1116 if (mac) 1117 iap = (unsigned char *) mac; 1118 } 1119 } 1120 1121 /* 1122 * 3) from flash or fuse (via platform data) 1123 */ 1124 if (!is_valid_ether_addr(iap)) { 1125 #ifdef CONFIG_M5272 1126 if (FEC_FLASHMAC) 1127 iap = (unsigned char *)FEC_FLASHMAC; 1128 #else 1129 if (pdata) 1130 iap = (unsigned char *)&pdata->mac; 1131 #endif 1132 } 1133 1134 /* 1135 * 4) FEC mac registers set by bootloader 1136 */ 1137 if (!is_valid_ether_addr(iap)) { 1138 *((__be32 *) &tmpaddr[0]) = 1139 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1140 *((__be16 *) &tmpaddr[4]) = 1141 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1142 iap = &tmpaddr[0]; 1143 } 1144 1145 /* 1146 * 5) random mac address 1147 */ 1148 if (!is_valid_ether_addr(iap)) { 1149 /* Report it and use a random ethernet address instead */ 1150 netdev_err(ndev, "Invalid MAC address: %pM\n", iap); 1151 eth_hw_addr_random(ndev); 1152 netdev_info(ndev, "Using random MAC address: %pM\n", 1153 ndev->dev_addr); 1154 return; 1155 } 1156 1157 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1158 1159 /* Adjust MAC if using macaddr */ 1160 if (iap == macaddr) 1161 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1162 } 1163 1164 /* ------------------------------------------------------------------------- */ 1165 1166 /* 1167 * Phy section 1168 */ 1169 static void fec_enet_adjust_link(struct net_device *ndev) 1170 { 1171 struct fec_enet_private *fep = netdev_priv(ndev); 1172 struct phy_device *phy_dev = fep->phy_dev; 1173 int status_change = 0; 1174 1175 /* Prevent a state halted on mii error */ 1176 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 1177 phy_dev->state = PHY_RESUMING; 1178 return; 1179 } 1180 1181 if (phy_dev->link) { 1182 if (!fep->link) { 1183 fep->link = phy_dev->link; 1184 status_change = 1; 1185 } 1186 1187 if (fep->full_duplex != phy_dev->duplex) 1188 status_change = 1; 1189 1190 if (phy_dev->speed != fep->speed) { 1191 fep->speed = phy_dev->speed; 1192 status_change = 1; 1193 } 1194 1195 /* if any of the above changed restart the FEC */ 1196 if (status_change) 1197 fec_restart(ndev, phy_dev->duplex); 1198 } else { 1199 if (fep->link) { 1200 fec_stop(ndev); 1201 fep->link = phy_dev->link; 1202 status_change = 1; 1203 } 1204 } 1205 1206 if (status_change) 1207 phy_print_status(phy_dev); 1208 } 1209 1210 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1211 { 1212 struct fec_enet_private *fep = bus->priv; 1213 unsigned long time_left; 1214 1215 fep->mii_timeout = 0; 1216 init_completion(&fep->mdio_done); 1217 1218 /* start a read op */ 1219 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 1220 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1221 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1222 1223 /* wait for end of transfer */ 1224 time_left = wait_for_completion_timeout(&fep->mdio_done, 1225 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1226 if (time_left == 0) { 1227 fep->mii_timeout = 1; 1228 netdev_err(fep->netdev, "MDIO read timeout\n"); 1229 return -ETIMEDOUT; 1230 } 1231 1232 /* return value */ 1233 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1234 } 1235 1236 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1237 u16 value) 1238 { 1239 struct fec_enet_private *fep = bus->priv; 1240 unsigned long time_left; 1241 1242 fep->mii_timeout = 0; 1243 init_completion(&fep->mdio_done); 1244 1245 /* start a write op */ 1246 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 1247 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 1248 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1249 fep->hwp + FEC_MII_DATA); 1250 1251 /* wait for end of transfer */ 1252 time_left = wait_for_completion_timeout(&fep->mdio_done, 1253 usecs_to_jiffies(FEC_MII_TIMEOUT)); 1254 if (time_left == 0) { 1255 fep->mii_timeout = 1; 1256 netdev_err(fep->netdev, "MDIO write timeout\n"); 1257 return -ETIMEDOUT; 1258 } 1259 1260 return 0; 1261 } 1262 1263 static int fec_enet_mdio_reset(struct mii_bus *bus) 1264 { 1265 return 0; 1266 } 1267 1268 static int fec_enet_mii_probe(struct net_device *ndev) 1269 { 1270 struct fec_enet_private *fep = netdev_priv(ndev); 1271 const struct platform_device_id *id_entry = 1272 platform_get_device_id(fep->pdev); 1273 struct phy_device *phy_dev = NULL; 1274 char mdio_bus_id[MII_BUS_ID_SIZE]; 1275 char phy_name[MII_BUS_ID_SIZE + 3]; 1276 int phy_id; 1277 int dev_id = fep->dev_id; 1278 1279 fep->phy_dev = NULL; 1280 1281 /* check for attached phy */ 1282 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 1283 if ((fep->mii_bus->phy_mask & (1 << phy_id))) 1284 continue; 1285 if (fep->mii_bus->phy_map[phy_id] == NULL) 1286 continue; 1287 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) 1288 continue; 1289 if (dev_id--) 1290 continue; 1291 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 1292 break; 1293 } 1294 1295 if (phy_id >= PHY_MAX_ADDR) { 1296 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 1297 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 1298 phy_id = 0; 1299 } 1300 1301 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); 1302 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 1303 fep->phy_interface); 1304 if (IS_ERR(phy_dev)) { 1305 netdev_err(ndev, "could not attach to PHY\n"); 1306 return PTR_ERR(phy_dev); 1307 } 1308 1309 /* mask with MAC supported features */ 1310 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) { 1311 phy_dev->supported &= PHY_GBIT_FEATURES; 1312 #if !defined(CONFIG_M5272) 1313 phy_dev->supported |= SUPPORTED_Pause; 1314 #endif 1315 } 1316 else 1317 phy_dev->supported &= PHY_BASIC_FEATURES; 1318 1319 phy_dev->advertising = phy_dev->supported; 1320 1321 fep->phy_dev = phy_dev; 1322 fep->link = 0; 1323 fep->full_duplex = 0; 1324 1325 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 1326 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), 1327 fep->phy_dev->irq); 1328 1329 return 0; 1330 } 1331 1332 static int fec_enet_mii_init(struct platform_device *pdev) 1333 { 1334 static struct mii_bus *fec0_mii_bus; 1335 struct net_device *ndev = platform_get_drvdata(pdev); 1336 struct fec_enet_private *fep = netdev_priv(ndev); 1337 const struct platform_device_id *id_entry = 1338 platform_get_device_id(fep->pdev); 1339 int err = -ENXIO, i; 1340 1341 /* 1342 * The dual fec interfaces are not equivalent with enet-mac. 1343 * Here are the differences: 1344 * 1345 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1346 * - fec0 acts as the 1588 time master while fec1 is slave 1347 * - external phys can only be configured by fec0 1348 * 1349 * That is to say fec1 can not work independently. It only works 1350 * when fec0 is working. The reason behind this design is that the 1351 * second interface is added primarily for Switch mode. 1352 * 1353 * Because of the last point above, both phys are attached on fec0 1354 * mdio interface in board design, and need to be configured by 1355 * fec0 mii_bus. 1356 */ 1357 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { 1358 /* fec1 uses fec0 mii_bus */ 1359 if (mii_cnt && fec0_mii_bus) { 1360 fep->mii_bus = fec0_mii_bus; 1361 mii_cnt++; 1362 return 0; 1363 } 1364 return -ENOENT; 1365 } 1366 1367 fep->mii_timeout = 0; 1368 1369 /* 1370 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 1371 * 1372 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 1373 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 1374 * Reference Manual has an error on this, and gets fixed on i.MX6Q 1375 * document. 1376 */ 1377 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000); 1378 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1379 fep->phy_speed--; 1380 fep->phy_speed <<= 1; 1381 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1382 1383 fep->mii_bus = mdiobus_alloc(); 1384 if (fep->mii_bus == NULL) { 1385 err = -ENOMEM; 1386 goto err_out; 1387 } 1388 1389 fep->mii_bus->name = "fec_enet_mii_bus"; 1390 fep->mii_bus->read = fec_enet_mdio_read; 1391 fep->mii_bus->write = fec_enet_mdio_write; 1392 fep->mii_bus->reset = fec_enet_mdio_reset; 1393 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1394 pdev->name, fep->dev_id + 1); 1395 fep->mii_bus->priv = fep; 1396 fep->mii_bus->parent = &pdev->dev; 1397 1398 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 1399 if (!fep->mii_bus->irq) { 1400 err = -ENOMEM; 1401 goto err_out_free_mdiobus; 1402 } 1403 1404 for (i = 0; i < PHY_MAX_ADDR; i++) 1405 fep->mii_bus->irq[i] = PHY_POLL; 1406 1407 if (mdiobus_register(fep->mii_bus)) 1408 goto err_out_free_mdio_irq; 1409 1410 mii_cnt++; 1411 1412 /* save fec0 mii_bus */ 1413 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1414 fec0_mii_bus = fep->mii_bus; 1415 1416 return 0; 1417 1418 err_out_free_mdio_irq: 1419 kfree(fep->mii_bus->irq); 1420 err_out_free_mdiobus: 1421 mdiobus_free(fep->mii_bus); 1422 err_out: 1423 return err; 1424 } 1425 1426 static void fec_enet_mii_remove(struct fec_enet_private *fep) 1427 { 1428 if (--mii_cnt == 0) { 1429 mdiobus_unregister(fep->mii_bus); 1430 kfree(fep->mii_bus->irq); 1431 mdiobus_free(fep->mii_bus); 1432 } 1433 } 1434 1435 static int fec_enet_get_settings(struct net_device *ndev, 1436 struct ethtool_cmd *cmd) 1437 { 1438 struct fec_enet_private *fep = netdev_priv(ndev); 1439 struct phy_device *phydev = fep->phy_dev; 1440 1441 if (!phydev) 1442 return -ENODEV; 1443 1444 return phy_ethtool_gset(phydev, cmd); 1445 } 1446 1447 static int fec_enet_set_settings(struct net_device *ndev, 1448 struct ethtool_cmd *cmd) 1449 { 1450 struct fec_enet_private *fep = netdev_priv(ndev); 1451 struct phy_device *phydev = fep->phy_dev; 1452 1453 if (!phydev) 1454 return -ENODEV; 1455 1456 return phy_ethtool_sset(phydev, cmd); 1457 } 1458 1459 static void fec_enet_get_drvinfo(struct net_device *ndev, 1460 struct ethtool_drvinfo *info) 1461 { 1462 struct fec_enet_private *fep = netdev_priv(ndev); 1463 1464 strlcpy(info->driver, fep->pdev->dev.driver->name, 1465 sizeof(info->driver)); 1466 strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); 1467 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 1468 } 1469 1470 static int fec_enet_get_ts_info(struct net_device *ndev, 1471 struct ethtool_ts_info *info) 1472 { 1473 struct fec_enet_private *fep = netdev_priv(ndev); 1474 1475 if (fep->bufdesc_ex) { 1476 1477 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1478 SOF_TIMESTAMPING_RX_SOFTWARE | 1479 SOF_TIMESTAMPING_SOFTWARE | 1480 SOF_TIMESTAMPING_TX_HARDWARE | 1481 SOF_TIMESTAMPING_RX_HARDWARE | 1482 SOF_TIMESTAMPING_RAW_HARDWARE; 1483 if (fep->ptp_clock) 1484 info->phc_index = ptp_clock_index(fep->ptp_clock); 1485 else 1486 info->phc_index = -1; 1487 1488 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 1489 (1 << HWTSTAMP_TX_ON); 1490 1491 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 1492 (1 << HWTSTAMP_FILTER_ALL); 1493 return 0; 1494 } else { 1495 return ethtool_op_get_ts_info(ndev, info); 1496 } 1497 } 1498 1499 #if !defined(CONFIG_M5272) 1500 1501 static void fec_enet_get_pauseparam(struct net_device *ndev, 1502 struct ethtool_pauseparam *pause) 1503 { 1504 struct fec_enet_private *fep = netdev_priv(ndev); 1505 1506 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 1507 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 1508 pause->rx_pause = pause->tx_pause; 1509 } 1510 1511 static int fec_enet_set_pauseparam(struct net_device *ndev, 1512 struct ethtool_pauseparam *pause) 1513 { 1514 struct fec_enet_private *fep = netdev_priv(ndev); 1515 1516 if (pause->tx_pause != pause->rx_pause) { 1517 netdev_info(ndev, 1518 "hardware only support enable/disable both tx and rx"); 1519 return -EINVAL; 1520 } 1521 1522 fep->pause_flag = 0; 1523 1524 /* tx pause must be same as rx pause */ 1525 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 1526 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 1527 1528 if (pause->rx_pause || pause->autoneg) { 1529 fep->phy_dev->supported |= ADVERTISED_Pause; 1530 fep->phy_dev->advertising |= ADVERTISED_Pause; 1531 } else { 1532 fep->phy_dev->supported &= ~ADVERTISED_Pause; 1533 fep->phy_dev->advertising &= ~ADVERTISED_Pause; 1534 } 1535 1536 if (pause->autoneg) { 1537 if (netif_running(ndev)) 1538 fec_stop(ndev); 1539 phy_start_aneg(fep->phy_dev); 1540 } 1541 if (netif_running(ndev)) 1542 fec_restart(ndev, 0); 1543 1544 return 0; 1545 } 1546 1547 static const struct fec_stat { 1548 char name[ETH_GSTRING_LEN]; 1549 u16 offset; 1550 } fec_stats[] = { 1551 /* RMON TX */ 1552 { "tx_dropped", RMON_T_DROP }, 1553 { "tx_packets", RMON_T_PACKETS }, 1554 { "tx_broadcast", RMON_T_BC_PKT }, 1555 { "tx_multicast", RMON_T_MC_PKT }, 1556 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 1557 { "tx_undersize", RMON_T_UNDERSIZE }, 1558 { "tx_oversize", RMON_T_OVERSIZE }, 1559 { "tx_fragment", RMON_T_FRAG }, 1560 { "tx_jabber", RMON_T_JAB }, 1561 { "tx_collision", RMON_T_COL }, 1562 { "tx_64byte", RMON_T_P64 }, 1563 { "tx_65to127byte", RMON_T_P65TO127 }, 1564 { "tx_128to255byte", RMON_T_P128TO255 }, 1565 { "tx_256to511byte", RMON_T_P256TO511 }, 1566 { "tx_512to1023byte", RMON_T_P512TO1023 }, 1567 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 1568 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 1569 { "tx_octets", RMON_T_OCTETS }, 1570 1571 /* IEEE TX */ 1572 { "IEEE_tx_drop", IEEE_T_DROP }, 1573 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 1574 { "IEEE_tx_1col", IEEE_T_1COL }, 1575 { "IEEE_tx_mcol", IEEE_T_MCOL }, 1576 { "IEEE_tx_def", IEEE_T_DEF }, 1577 { "IEEE_tx_lcol", IEEE_T_LCOL }, 1578 { "IEEE_tx_excol", IEEE_T_EXCOL }, 1579 { "IEEE_tx_macerr", IEEE_T_MACERR }, 1580 { "IEEE_tx_cserr", IEEE_T_CSERR }, 1581 { "IEEE_tx_sqe", IEEE_T_SQE }, 1582 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 1583 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 1584 1585 /* RMON RX */ 1586 { "rx_packets", RMON_R_PACKETS }, 1587 { "rx_broadcast", RMON_R_BC_PKT }, 1588 { "rx_multicast", RMON_R_MC_PKT }, 1589 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 1590 { "rx_undersize", RMON_R_UNDERSIZE }, 1591 { "rx_oversize", RMON_R_OVERSIZE }, 1592 { "rx_fragment", RMON_R_FRAG }, 1593 { "rx_jabber", RMON_R_JAB }, 1594 { "rx_64byte", RMON_R_P64 }, 1595 { "rx_65to127byte", RMON_R_P65TO127 }, 1596 { "rx_128to255byte", RMON_R_P128TO255 }, 1597 { "rx_256to511byte", RMON_R_P256TO511 }, 1598 { "rx_512to1023byte", RMON_R_P512TO1023 }, 1599 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 1600 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 1601 { "rx_octets", RMON_R_OCTETS }, 1602 1603 /* IEEE RX */ 1604 { "IEEE_rx_drop", IEEE_R_DROP }, 1605 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 1606 { "IEEE_rx_crc", IEEE_R_CRC }, 1607 { "IEEE_rx_align", IEEE_R_ALIGN }, 1608 { "IEEE_rx_macerr", IEEE_R_MACERR }, 1609 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 1610 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 1611 }; 1612 1613 static void fec_enet_get_ethtool_stats(struct net_device *dev, 1614 struct ethtool_stats *stats, u64 *data) 1615 { 1616 struct fec_enet_private *fep = netdev_priv(dev); 1617 int i; 1618 1619 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 1620 data[i] = readl(fep->hwp + fec_stats[i].offset); 1621 } 1622 1623 static void fec_enet_get_strings(struct net_device *netdev, 1624 u32 stringset, u8 *data) 1625 { 1626 int i; 1627 switch (stringset) { 1628 case ETH_SS_STATS: 1629 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 1630 memcpy(data + i * ETH_GSTRING_LEN, 1631 fec_stats[i].name, ETH_GSTRING_LEN); 1632 break; 1633 } 1634 } 1635 1636 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 1637 { 1638 switch (sset) { 1639 case ETH_SS_STATS: 1640 return ARRAY_SIZE(fec_stats); 1641 default: 1642 return -EOPNOTSUPP; 1643 } 1644 } 1645 #endif /* !defined(CONFIG_M5272) */ 1646 1647 static int fec_enet_nway_reset(struct net_device *dev) 1648 { 1649 struct fec_enet_private *fep = netdev_priv(dev); 1650 struct phy_device *phydev = fep->phy_dev; 1651 1652 if (!phydev) 1653 return -ENODEV; 1654 1655 return genphy_restart_aneg(phydev); 1656 } 1657 1658 static const struct ethtool_ops fec_enet_ethtool_ops = { 1659 #if !defined(CONFIG_M5272) 1660 .get_pauseparam = fec_enet_get_pauseparam, 1661 .set_pauseparam = fec_enet_set_pauseparam, 1662 #endif 1663 .get_settings = fec_enet_get_settings, 1664 .set_settings = fec_enet_set_settings, 1665 .get_drvinfo = fec_enet_get_drvinfo, 1666 .get_link = ethtool_op_get_link, 1667 .get_ts_info = fec_enet_get_ts_info, 1668 .nway_reset = fec_enet_nway_reset, 1669 #ifndef CONFIG_M5272 1670 .get_ethtool_stats = fec_enet_get_ethtool_stats, 1671 .get_strings = fec_enet_get_strings, 1672 .get_sset_count = fec_enet_get_sset_count, 1673 #endif 1674 }; 1675 1676 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 1677 { 1678 struct fec_enet_private *fep = netdev_priv(ndev); 1679 struct phy_device *phydev = fep->phy_dev; 1680 1681 if (!netif_running(ndev)) 1682 return -EINVAL; 1683 1684 if (!phydev) 1685 return -ENODEV; 1686 1687 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex) 1688 return fec_ptp_ioctl(ndev, rq, cmd); 1689 1690 return phy_mii_ioctl(phydev, rq, cmd); 1691 } 1692 1693 static void fec_enet_free_buffers(struct net_device *ndev) 1694 { 1695 struct fec_enet_private *fep = netdev_priv(ndev); 1696 unsigned int i; 1697 struct sk_buff *skb; 1698 struct bufdesc *bdp; 1699 1700 bdp = fep->rx_bd_base; 1701 for (i = 0; i < fep->rx_ring_size; i++) { 1702 skb = fep->rx_skbuff[i]; 1703 1704 if (bdp->cbd_bufaddr) 1705 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 1706 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1707 if (skb) 1708 dev_kfree_skb(skb); 1709 bdp = fec_enet_get_nextdesc(bdp, fep); 1710 } 1711 1712 bdp = fep->tx_bd_base; 1713 for (i = 0; i < fep->tx_ring_size; i++) 1714 kfree(fep->tx_bounce[i]); 1715 } 1716 1717 static int fec_enet_alloc_buffers(struct net_device *ndev) 1718 { 1719 struct fec_enet_private *fep = netdev_priv(ndev); 1720 unsigned int i; 1721 struct sk_buff *skb; 1722 struct bufdesc *bdp; 1723 1724 bdp = fep->rx_bd_base; 1725 for (i = 0; i < fep->rx_ring_size; i++) { 1726 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1727 if (!skb) { 1728 fec_enet_free_buffers(ndev); 1729 return -ENOMEM; 1730 } 1731 fep->rx_skbuff[i] = skb; 1732 1733 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, 1734 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1735 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) { 1736 fec_enet_free_buffers(ndev); 1737 if (net_ratelimit()) 1738 netdev_err(ndev, "Rx DMA memory map failed\n"); 1739 return -ENOMEM; 1740 } 1741 bdp->cbd_sc = BD_ENET_RX_EMPTY; 1742 1743 if (fep->bufdesc_ex) { 1744 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1745 ebdp->cbd_esc = BD_ENET_RX_INT; 1746 } 1747 1748 bdp = fec_enet_get_nextdesc(bdp, fep); 1749 } 1750 1751 /* Set the last buffer to wrap. */ 1752 bdp = fec_enet_get_prevdesc(bdp, fep); 1753 bdp->cbd_sc |= BD_SC_WRAP; 1754 1755 bdp = fep->tx_bd_base; 1756 for (i = 0; i < fep->tx_ring_size; i++) { 1757 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 1758 1759 bdp->cbd_sc = 0; 1760 bdp->cbd_bufaddr = 0; 1761 1762 if (fep->bufdesc_ex) { 1763 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1764 ebdp->cbd_esc = BD_ENET_TX_INT; 1765 } 1766 1767 bdp = fec_enet_get_nextdesc(bdp, fep); 1768 } 1769 1770 /* Set the last buffer to wrap. */ 1771 bdp = fec_enet_get_prevdesc(bdp, fep); 1772 bdp->cbd_sc |= BD_SC_WRAP; 1773 1774 return 0; 1775 } 1776 1777 static int 1778 fec_enet_open(struct net_device *ndev) 1779 { 1780 struct fec_enet_private *fep = netdev_priv(ndev); 1781 int ret; 1782 1783 napi_enable(&fep->napi); 1784 1785 /* I should reset the ring buffers here, but I don't yet know 1786 * a simple way to do that. 1787 */ 1788 1789 ret = fec_enet_alloc_buffers(ndev); 1790 if (ret) 1791 return ret; 1792 1793 /* Probe and connect to PHY when open the interface */ 1794 ret = fec_enet_mii_probe(ndev); 1795 if (ret) { 1796 fec_enet_free_buffers(ndev); 1797 return ret; 1798 } 1799 phy_start(fep->phy_dev); 1800 netif_start_queue(ndev); 1801 fep->opened = 1; 1802 return 0; 1803 } 1804 1805 static int 1806 fec_enet_close(struct net_device *ndev) 1807 { 1808 struct fec_enet_private *fep = netdev_priv(ndev); 1809 1810 /* Don't know what to do yet. */ 1811 napi_disable(&fep->napi); 1812 fep->opened = 0; 1813 netif_stop_queue(ndev); 1814 fec_stop(ndev); 1815 1816 if (fep->phy_dev) { 1817 phy_stop(fep->phy_dev); 1818 phy_disconnect(fep->phy_dev); 1819 } 1820 1821 fec_enet_free_buffers(ndev); 1822 1823 return 0; 1824 } 1825 1826 /* Set or clear the multicast filter for this adaptor. 1827 * Skeleton taken from sunlance driver. 1828 * The CPM Ethernet implementation allows Multicast as well as individual 1829 * MAC address filtering. Some of the drivers check to make sure it is 1830 * a group multicast address, and discard those that are not. I guess I 1831 * will do the same for now, but just remove the test if you want 1832 * individual filtering as well (do the upper net layers want or support 1833 * this kind of feature?). 1834 */ 1835 1836 #define HASH_BITS 6 /* #bits in hash */ 1837 #define CRC32_POLY 0xEDB88320 1838 1839 static void set_multicast_list(struct net_device *ndev) 1840 { 1841 struct fec_enet_private *fep = netdev_priv(ndev); 1842 struct netdev_hw_addr *ha; 1843 unsigned int i, bit, data, crc, tmp; 1844 unsigned char hash; 1845 1846 if (ndev->flags & IFF_PROMISC) { 1847 tmp = readl(fep->hwp + FEC_R_CNTRL); 1848 tmp |= 0x8; 1849 writel(tmp, fep->hwp + FEC_R_CNTRL); 1850 return; 1851 } 1852 1853 tmp = readl(fep->hwp + FEC_R_CNTRL); 1854 tmp &= ~0x8; 1855 writel(tmp, fep->hwp + FEC_R_CNTRL); 1856 1857 if (ndev->flags & IFF_ALLMULTI) { 1858 /* Catch all multicast addresses, so set the 1859 * filter to all 1's 1860 */ 1861 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1862 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1863 1864 return; 1865 } 1866 1867 /* Clear filter and add the addresses in hash register 1868 */ 1869 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1870 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1871 1872 netdev_for_each_mc_addr(ha, ndev) { 1873 /* calculate crc32 value of mac address */ 1874 crc = 0xffffffff; 1875 1876 for (i = 0; i < ndev->addr_len; i++) { 1877 data = ha->addr[i]; 1878 for (bit = 0; bit < 8; bit++, data >>= 1) { 1879 crc = (crc >> 1) ^ 1880 (((crc ^ data) & 1) ? CRC32_POLY : 0); 1881 } 1882 } 1883 1884 /* only upper 6 bits (HASH_BITS) are used 1885 * which point to specific bit in he hash registers 1886 */ 1887 hash = (crc >> (32 - HASH_BITS)) & 0x3f; 1888 1889 if (hash > 31) { 1890 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1891 tmp |= 1 << (hash - 32); 1892 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1893 } else { 1894 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1895 tmp |= 1 << hash; 1896 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1897 } 1898 } 1899 } 1900 1901 /* Set a MAC change in hardware. */ 1902 static int 1903 fec_set_mac_address(struct net_device *ndev, void *p) 1904 { 1905 struct fec_enet_private *fep = netdev_priv(ndev); 1906 struct sockaddr *addr = p; 1907 1908 if (!is_valid_ether_addr(addr->sa_data)) 1909 return -EADDRNOTAVAIL; 1910 1911 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 1912 1913 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 1914 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 1915 fep->hwp + FEC_ADDR_LOW); 1916 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 1917 fep->hwp + FEC_ADDR_HIGH); 1918 return 0; 1919 } 1920 1921 #ifdef CONFIG_NET_POLL_CONTROLLER 1922 /** 1923 * fec_poll_controller - FEC Poll controller function 1924 * @dev: The FEC network adapter 1925 * 1926 * Polled functionality used by netconsole and others in non interrupt mode 1927 * 1928 */ 1929 static void fec_poll_controller(struct net_device *dev) 1930 { 1931 int i; 1932 struct fec_enet_private *fep = netdev_priv(dev); 1933 1934 for (i = 0; i < FEC_IRQ_NUM; i++) { 1935 if (fep->irq[i] > 0) { 1936 disable_irq(fep->irq[i]); 1937 fec_enet_interrupt(fep->irq[i], dev); 1938 enable_irq(fep->irq[i]); 1939 } 1940 } 1941 } 1942 #endif 1943 1944 static int fec_set_features(struct net_device *netdev, 1945 netdev_features_t features) 1946 { 1947 struct fec_enet_private *fep = netdev_priv(netdev); 1948 netdev_features_t changed = features ^ netdev->features; 1949 1950 netdev->features = features; 1951 1952 /* Receive checksum has been changed */ 1953 if (changed & NETIF_F_RXCSUM) { 1954 if (features & NETIF_F_RXCSUM) 1955 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 1956 else 1957 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 1958 1959 if (netif_running(netdev)) { 1960 fec_stop(netdev); 1961 fec_restart(netdev, fep->phy_dev->duplex); 1962 netif_wake_queue(netdev); 1963 } else { 1964 fec_restart(netdev, fep->phy_dev->duplex); 1965 } 1966 } 1967 1968 return 0; 1969 } 1970 1971 static const struct net_device_ops fec_netdev_ops = { 1972 .ndo_open = fec_enet_open, 1973 .ndo_stop = fec_enet_close, 1974 .ndo_start_xmit = fec_enet_start_xmit, 1975 .ndo_set_rx_mode = set_multicast_list, 1976 .ndo_change_mtu = eth_change_mtu, 1977 .ndo_validate_addr = eth_validate_addr, 1978 .ndo_tx_timeout = fec_timeout, 1979 .ndo_set_mac_address = fec_set_mac_address, 1980 .ndo_do_ioctl = fec_enet_ioctl, 1981 #ifdef CONFIG_NET_POLL_CONTROLLER 1982 .ndo_poll_controller = fec_poll_controller, 1983 #endif 1984 .ndo_set_features = fec_set_features, 1985 }; 1986 1987 /* 1988 * XXX: We need to clean up on failure exits here. 1989 * 1990 */ 1991 static int fec_enet_init(struct net_device *ndev) 1992 { 1993 struct fec_enet_private *fep = netdev_priv(ndev); 1994 const struct platform_device_id *id_entry = 1995 platform_get_device_id(fep->pdev); 1996 struct bufdesc *cbd_base; 1997 1998 /* Allocate memory for buffer descriptors. */ 1999 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, 2000 GFP_KERNEL); 2001 if (!cbd_base) 2002 return -ENOMEM; 2003 2004 memset(cbd_base, 0, PAGE_SIZE); 2005 2006 fep->netdev = ndev; 2007 2008 /* Get the Ethernet address */ 2009 fec_get_mac(ndev); 2010 2011 /* init the tx & rx ring size */ 2012 fep->tx_ring_size = TX_RING_SIZE; 2013 fep->rx_ring_size = RX_RING_SIZE; 2014 2015 /* Set receive and transmit descriptor base. */ 2016 fep->rx_bd_base = cbd_base; 2017 if (fep->bufdesc_ex) 2018 fep->tx_bd_base = (struct bufdesc *) 2019 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size); 2020 else 2021 fep->tx_bd_base = cbd_base + fep->rx_ring_size; 2022 2023 /* The FEC Ethernet specific entries in the device structure */ 2024 ndev->watchdog_timeo = TX_TIMEOUT; 2025 ndev->netdev_ops = &fec_netdev_ops; 2026 ndev->ethtool_ops = &fec_enet_ethtool_ops; 2027 2028 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 2029 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 2030 2031 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) { 2032 /* enable hw VLAN support */ 2033 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 2034 ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 2035 } 2036 2037 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) { 2038 /* enable hw accelerator */ 2039 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 2040 | NETIF_F_RXCSUM); 2041 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 2042 | NETIF_F_RXCSUM); 2043 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 2044 } 2045 2046 fec_restart(ndev, 0); 2047 2048 return 0; 2049 } 2050 2051 #ifdef CONFIG_OF 2052 static void fec_reset_phy(struct platform_device *pdev) 2053 { 2054 int err, phy_reset; 2055 int msec = 1; 2056 struct device_node *np = pdev->dev.of_node; 2057 2058 if (!np) 2059 return; 2060 2061 of_property_read_u32(np, "phy-reset-duration", &msec); 2062 /* A sane reset duration should not be longer than 1s */ 2063 if (msec > 1000) 2064 msec = 1; 2065 2066 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 2067 if (!gpio_is_valid(phy_reset)) 2068 return; 2069 2070 err = devm_gpio_request_one(&pdev->dev, phy_reset, 2071 GPIOF_OUT_INIT_LOW, "phy-reset"); 2072 if (err) { 2073 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 2074 return; 2075 } 2076 msleep(msec); 2077 gpio_set_value(phy_reset, 1); 2078 } 2079 #else /* CONFIG_OF */ 2080 static void fec_reset_phy(struct platform_device *pdev) 2081 { 2082 /* 2083 * In case of platform probe, the reset has been done 2084 * by machine code. 2085 */ 2086 } 2087 #endif /* CONFIG_OF */ 2088 2089 static int 2090 fec_probe(struct platform_device *pdev) 2091 { 2092 struct fec_enet_private *fep; 2093 struct fec_platform_data *pdata; 2094 struct net_device *ndev; 2095 int i, irq, ret = 0; 2096 struct resource *r; 2097 const struct of_device_id *of_id; 2098 static int dev_id; 2099 2100 of_id = of_match_device(fec_dt_ids, &pdev->dev); 2101 if (of_id) 2102 pdev->id_entry = of_id->data; 2103 2104 /* Init network device */ 2105 ndev = alloc_etherdev(sizeof(struct fec_enet_private)); 2106 if (!ndev) 2107 return -ENOMEM; 2108 2109 SET_NETDEV_DEV(ndev, &pdev->dev); 2110 2111 /* setup board info structure */ 2112 fep = netdev_priv(ndev); 2113 2114 #if !defined(CONFIG_M5272) 2115 /* default enable pause frame auto negotiation */ 2116 if (pdev->id_entry && 2117 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT)) 2118 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 2119 #endif 2120 2121 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2122 fep->hwp = devm_ioremap_resource(&pdev->dev, r); 2123 if (IS_ERR(fep->hwp)) { 2124 ret = PTR_ERR(fep->hwp); 2125 goto failed_ioremap; 2126 } 2127 2128 fep->pdev = pdev; 2129 fep->dev_id = dev_id++; 2130 2131 fep->bufdesc_ex = 0; 2132 2133 platform_set_drvdata(pdev, ndev); 2134 2135 ret = of_get_phy_mode(pdev->dev.of_node); 2136 if (ret < 0) { 2137 pdata = dev_get_platdata(&pdev->dev); 2138 if (pdata) 2139 fep->phy_interface = pdata->phy; 2140 else 2141 fep->phy_interface = PHY_INTERFACE_MODE_MII; 2142 } else { 2143 fep->phy_interface = ret; 2144 } 2145 2146 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2147 if (IS_ERR(fep->clk_ipg)) { 2148 ret = PTR_ERR(fep->clk_ipg); 2149 goto failed_clk; 2150 } 2151 2152 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 2153 if (IS_ERR(fep->clk_ahb)) { 2154 ret = PTR_ERR(fep->clk_ahb); 2155 goto failed_clk; 2156 } 2157 2158 /* enet_out is optional, depends on board */ 2159 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 2160 if (IS_ERR(fep->clk_enet_out)) 2161 fep->clk_enet_out = NULL; 2162 2163 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 2164 fep->bufdesc_ex = 2165 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX; 2166 if (IS_ERR(fep->clk_ptp)) { 2167 fep->clk_ptp = NULL; 2168 fep->bufdesc_ex = 0; 2169 } 2170 2171 ret = clk_prepare_enable(fep->clk_ahb); 2172 if (ret) 2173 goto failed_clk; 2174 2175 ret = clk_prepare_enable(fep->clk_ipg); 2176 if (ret) 2177 goto failed_clk_ipg; 2178 2179 if (fep->clk_enet_out) { 2180 ret = clk_prepare_enable(fep->clk_enet_out); 2181 if (ret) 2182 goto failed_clk_enet_out; 2183 } 2184 2185 if (fep->clk_ptp) { 2186 ret = clk_prepare_enable(fep->clk_ptp); 2187 if (ret) 2188 goto failed_clk_ptp; 2189 } 2190 2191 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); 2192 if (!IS_ERR(fep->reg_phy)) { 2193 ret = regulator_enable(fep->reg_phy); 2194 if (ret) { 2195 dev_err(&pdev->dev, 2196 "Failed to enable phy regulator: %d\n", ret); 2197 goto failed_regulator; 2198 } 2199 } else { 2200 fep->reg_phy = NULL; 2201 } 2202 2203 fec_reset_phy(pdev); 2204 2205 if (fep->bufdesc_ex) 2206 fec_ptp_init(pdev); 2207 2208 ret = fec_enet_init(ndev); 2209 if (ret) 2210 goto failed_init; 2211 2212 for (i = 0; i < FEC_IRQ_NUM; i++) { 2213 irq = platform_get_irq(pdev, i); 2214 if (irq < 0) { 2215 if (i) 2216 break; 2217 ret = irq; 2218 goto failed_irq; 2219 } 2220 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 2221 0, pdev->name, ndev); 2222 if (ret) 2223 goto failed_irq; 2224 } 2225 2226 ret = fec_enet_mii_init(pdev); 2227 if (ret) 2228 goto failed_mii_init; 2229 2230 /* Carrier starts down, phylib will bring it up */ 2231 netif_carrier_off(ndev); 2232 2233 ret = register_netdev(ndev); 2234 if (ret) 2235 goto failed_register; 2236 2237 if (fep->bufdesc_ex && fep->ptp_clock) 2238 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 2239 2240 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work); 2241 return 0; 2242 2243 failed_register: 2244 fec_enet_mii_remove(fep); 2245 failed_mii_init: 2246 failed_irq: 2247 failed_init: 2248 if (fep->reg_phy) 2249 regulator_disable(fep->reg_phy); 2250 failed_regulator: 2251 if (fep->clk_ptp) 2252 clk_disable_unprepare(fep->clk_ptp); 2253 failed_clk_ptp: 2254 if (fep->clk_enet_out) 2255 clk_disable_unprepare(fep->clk_enet_out); 2256 failed_clk_enet_out: 2257 clk_disable_unprepare(fep->clk_ipg); 2258 failed_clk_ipg: 2259 clk_disable_unprepare(fep->clk_ahb); 2260 failed_clk: 2261 failed_ioremap: 2262 free_netdev(ndev); 2263 2264 return ret; 2265 } 2266 2267 static int 2268 fec_drv_remove(struct platform_device *pdev) 2269 { 2270 struct net_device *ndev = platform_get_drvdata(pdev); 2271 struct fec_enet_private *fep = netdev_priv(ndev); 2272 2273 cancel_delayed_work_sync(&(fep->delay_work.delay_work)); 2274 unregister_netdev(ndev); 2275 fec_enet_mii_remove(fep); 2276 del_timer_sync(&fep->time_keep); 2277 if (fep->reg_phy) 2278 regulator_disable(fep->reg_phy); 2279 if (fep->clk_ptp) 2280 clk_disable_unprepare(fep->clk_ptp); 2281 if (fep->ptp_clock) 2282 ptp_clock_unregister(fep->ptp_clock); 2283 if (fep->clk_enet_out) 2284 clk_disable_unprepare(fep->clk_enet_out); 2285 clk_disable_unprepare(fep->clk_ipg); 2286 clk_disable_unprepare(fep->clk_ahb); 2287 free_netdev(ndev); 2288 2289 return 0; 2290 } 2291 2292 #ifdef CONFIG_PM_SLEEP 2293 static int 2294 fec_suspend(struct device *dev) 2295 { 2296 struct net_device *ndev = dev_get_drvdata(dev); 2297 struct fec_enet_private *fep = netdev_priv(ndev); 2298 2299 if (netif_running(ndev)) { 2300 fec_stop(ndev); 2301 netif_device_detach(ndev); 2302 } 2303 if (fep->clk_ptp) 2304 clk_disable_unprepare(fep->clk_ptp); 2305 if (fep->clk_enet_out) 2306 clk_disable_unprepare(fep->clk_enet_out); 2307 clk_disable_unprepare(fep->clk_ipg); 2308 clk_disable_unprepare(fep->clk_ahb); 2309 2310 if (fep->reg_phy) 2311 regulator_disable(fep->reg_phy); 2312 2313 return 0; 2314 } 2315 2316 static int 2317 fec_resume(struct device *dev) 2318 { 2319 struct net_device *ndev = dev_get_drvdata(dev); 2320 struct fec_enet_private *fep = netdev_priv(ndev); 2321 int ret; 2322 2323 if (fep->reg_phy) { 2324 ret = regulator_enable(fep->reg_phy); 2325 if (ret) 2326 return ret; 2327 } 2328 2329 ret = clk_prepare_enable(fep->clk_ahb); 2330 if (ret) 2331 goto failed_clk_ahb; 2332 2333 ret = clk_prepare_enable(fep->clk_ipg); 2334 if (ret) 2335 goto failed_clk_ipg; 2336 2337 if (fep->clk_enet_out) { 2338 ret = clk_prepare_enable(fep->clk_enet_out); 2339 if (ret) 2340 goto failed_clk_enet_out; 2341 } 2342 2343 if (fep->clk_ptp) { 2344 ret = clk_prepare_enable(fep->clk_ptp); 2345 if (ret) 2346 goto failed_clk_ptp; 2347 } 2348 2349 if (netif_running(ndev)) { 2350 fec_restart(ndev, fep->full_duplex); 2351 netif_device_attach(ndev); 2352 } 2353 2354 return 0; 2355 2356 failed_clk_ptp: 2357 if (fep->clk_enet_out) 2358 clk_disable_unprepare(fep->clk_enet_out); 2359 failed_clk_enet_out: 2360 clk_disable_unprepare(fep->clk_ipg); 2361 failed_clk_ipg: 2362 clk_disable_unprepare(fep->clk_ahb); 2363 failed_clk_ahb: 2364 if (fep->reg_phy) 2365 regulator_disable(fep->reg_phy); 2366 return ret; 2367 } 2368 #endif /* CONFIG_PM_SLEEP */ 2369 2370 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume); 2371 2372 static struct platform_driver fec_driver = { 2373 .driver = { 2374 .name = DRIVER_NAME, 2375 .owner = THIS_MODULE, 2376 .pm = &fec_pm_ops, 2377 .of_match_table = fec_dt_ids, 2378 }, 2379 .id_table = fec_devtype, 2380 .probe = fec_probe, 2381 .remove = fec_drv_remove, 2382 }; 2383 2384 module_platform_driver(fec_driver); 2385 2386 MODULE_ALIAS("platform:"DRIVER_NAME); 2387 MODULE_LICENSE("GPL"); 2388